// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
// Legal Notice: Copyright 2022 Intel Corporation.  All rights reserved.
// Your use of  Intel Corporation's design tools,  logic functions and other
// software and  tools, and its AMPP partner logic functions, and any output
// files any  of the foregoing (including  device programming  or simulation
// files), and  any associated  documentation  or information  are expressly
// subject  to the terms and  conditions of the  Intel FPGA Software License
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement,  including,  without limitation,  that your use is for
// the  sole  purpose of  programming  logic devices  manufactured by  Intel
// and  sold by Intel  or its authorized  distributors. Please refer  to the
// applicable agreement for further details.
// ---------------------------------------------------------------------------

// SystemVerilog created from i_sfc_logic_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr0
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_i_sfc_logic_s_c0_in_for_body340000enter7245_c_compstr0 (
    input wire [4095:0] in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdata,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writeack,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdatavalid,
    output wire [31:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write,
    output wire [4095:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata,
    output wire [511:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount,
    output wire [0:0] out_pipeline_dummy_out,
    output wire [0:0] out_pipeline_forked_out,
    output wire [0:0] out_pipeline_valid_out,
    output wire [0:0] out_c0_exi5730_0_tpl,
    output wire [0:0] out_c0_exi5730_1_tpl,
    output wire [0:0] out_c0_exi5730_2_tpl,
    output wire [15:0] out_c0_exi5730_3_tpl,
    output wire [15:0] out_c0_exi5730_4_tpl,
    output wire [0:0] out_c0_exi5730_5_tpl,
    output wire [0:0] out_c0_exi5730_6_tpl,
    output wire [0:0] out_c_compSTR_B7_current_iter_isspec,
    output wire [0:0] out_o_valid,
    input wire [0:0] in_buffer_in,
    input wire [0:0] in_c0_eni1723_0_tpl,
    input wire [0:0] in_c0_eni1723_1_tpl,
    input wire [0:0] in_dummy_in,
    input wire [0:0] in_i_valid,
    input wire [4095:0] in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdata,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writeack,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdatavalid,
    output wire [31:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write,
    output wire [4095:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata,
    output wire [511:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount,
    input wire [0:0] in_flush,
    output wire [0:0] out_exiting_valid_out,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [0:0] VCC_q;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_100_c_compstr2826_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_101_c_compstr2854_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_102_c_compstr2882_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_103_c_compstr2910_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_104_c_compstr2938_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_105_c_compstr2966_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_106_c_compstr2994_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_107_c_compstr3022_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_108_c_compstr3050_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_109_c_compstr3078_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_10_c_compstr306_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_110_c_compstr3106_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_111_c_compstr3134_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_112_c_compstr3162_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_113_c_compstr3190_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_114_c_compstr3218_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_115_c_compstr3246_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_116_c_compstr3274_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_117_c_compstr3302_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_118_c_compstr3330_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_119_c_compstr3358_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_11_c_compstr334_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_120_c_compstr3386_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_121_c_compstr3414_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_122_c_compstr3442_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_123_c_compstr3470_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_124_c_compstr3498_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_125_c_compstr3526_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_126_c_compstr3554_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_127_c_compstr3582_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_12_c_compstr362_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_13_c_compstr390_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_14_c_compstr418_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_15_c_compstr446_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_16_c_compstr474_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_17_c_compstr502_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_18_c_compstr530_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_19_c_compstr558_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_1_c_compstr54_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_20_c_compstr586_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_21_c_compstr614_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_22_c_compstr642_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_23_c_compstr670_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_24_c_compstr698_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_25_c_compstr726_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_26_c_compstr754_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_27_c_compstr782_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_28_c_compstr810_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_29_c_compstr838_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_2_c_compstr82_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_30_c_compstr866_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_31_c_compstr894_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_32_c_compstr922_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_33_c_compstr950_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_34_c_compstr978_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_35_c_compstr1006_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_36_c_compstr1034_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_37_c_compstr1062_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_38_c_compstr1090_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_39_c_compstr1118_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_3_c_compstr110_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_40_c_compstr1146_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_41_c_compstr1174_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_42_c_compstr1202_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_43_c_compstr1230_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_44_c_compstr1258_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_45_c_compstr1286_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_46_c_compstr1314_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_47_c_compstr1342_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_48_c_compstr1370_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_49_c_compstr1398_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_4_c_compstr138_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_50_c_compstr1426_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_51_c_compstr1454_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_52_c_compstr1482_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_53_c_compstr1510_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_54_c_compstr1538_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_55_c_compstr1566_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_56_c_compstr1594_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_57_c_compstr1622_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_58_c_compstr1650_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_59_c_compstr1678_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_5_c_compstr166_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_60_c_compstr1706_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_61_c_compstr1734_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_62_c_compstr1762_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_63_c_compstr1790_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_64_c_compstr1818_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_65_c_compstr1846_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_66_c_compstr1874_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_67_c_compstr1902_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_68_c_compstr1930_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_69_c_compstr1958_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_6_c_compstr194_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_70_c_compstr1986_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_71_c_compstr2014_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_72_c_compstr2042_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_73_c_compstr2070_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_74_c_compstr2098_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_75_c_compstr2126_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_76_c_compstr2154_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_77_c_compstr2182_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_78_c_compstr2210_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_79_c_compstr2238_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_7_c_compstr222_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_80_c_compstr2266_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_81_c_compstr2294_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_82_c_compstr2322_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_83_c_compstr2350_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_84_c_compstr2378_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_85_c_compstr2406_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_86_c_compstr2434_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_87_c_compstr2462_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_88_c_compstr2490_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_89_c_compstr2518_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_8_c_compstr250_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_90_c_compstr2546_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_91_c_compstr2574_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_92_c_compstr2602_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_93_c_compstr2630_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_94_c_compstr2658_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_95_c_compstr2686_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_96_c_compstr2714_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_97_c_compstr2742_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_98_c_compstr2770_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_99_c_compstr2798_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_9_c_compstr278_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_c_compstr28_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_100_c_compstr2842_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_101_c_compstr2870_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_102_c_compstr2898_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_103_c_compstr2926_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_104_c_compstr2954_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_105_c_compstr2982_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_106_c_compstr3010_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_107_c_compstr3038_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_108_c_compstr3066_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_109_c_compstr3094_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_10_c_compstr322_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_110_c_compstr3122_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_111_c_compstr3150_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_112_c_compstr3178_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_113_c_compstr3206_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_114_c_compstr3234_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_115_c_compstr3262_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_116_c_compstr3290_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_117_c_compstr3318_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_118_c_compstr3346_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_119_c_compstr3374_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_11_c_compstr350_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_120_c_compstr3402_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_121_c_compstr3430_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_122_c_compstr3458_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_123_c_compstr3486_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_124_c_compstr3514_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_125_c_compstr3542_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_126_c_compstr3570_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_127_c_compstr3598_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_12_c_compstr378_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_13_c_compstr406_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_14_c_compstr434_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_15_c_compstr462_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_16_c_compstr490_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_17_c_compstr518_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_18_c_compstr546_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_19_c_compstr574_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_1_c_compstr70_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_20_c_compstr602_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_21_c_compstr630_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_22_c_compstr658_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_23_c_compstr686_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_24_c_compstr714_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_25_c_compstr742_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_26_c_compstr770_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_27_c_compstr798_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_28_c_compstr826_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_29_c_compstr854_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_2_c_compstr98_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_30_c_compstr882_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_31_c_compstr910_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_32_c_compstr938_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_33_c_compstr966_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_34_c_compstr994_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_35_c_compstr1022_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_36_c_compstr1050_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_37_c_compstr1078_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_38_c_compstr1106_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_39_c_compstr1134_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_3_c_compstr126_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_40_c_compstr1162_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_41_c_compstr1190_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_42_c_compstr1218_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_43_c_compstr1246_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_44_c_compstr1274_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_45_c_compstr1302_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_46_c_compstr1330_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_47_c_compstr1358_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_48_c_compstr1386_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_49_c_compstr1414_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_4_c_compstr154_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_50_c_compstr1442_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_51_c_compstr1470_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_52_c_compstr1498_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_53_c_compstr1526_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_54_c_compstr1554_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_55_c_compstr1582_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_56_c_compstr1610_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_57_c_compstr1638_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_58_c_compstr1666_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_59_c_compstr1694_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_5_c_compstr182_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_60_c_compstr1722_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_61_c_compstr1750_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_62_c_compstr1778_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_63_c_compstr1806_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_64_c_compstr1834_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_65_c_compstr1862_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_66_c_compstr1890_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_67_c_compstr1918_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_68_c_compstr1946_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_69_c_compstr1974_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_6_c_compstr210_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_70_c_compstr2002_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_71_c_compstr2030_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_72_c_compstr2058_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_73_c_compstr2086_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_74_c_compstr2114_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_75_c_compstr2142_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_76_c_compstr2170_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_77_c_compstr2198_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_78_c_compstr2226_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_79_c_compstr2254_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_7_c_compstr238_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_80_c_compstr2282_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_81_c_compstr2310_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_82_c_compstr2338_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_83_c_compstr2366_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_84_c_compstr2394_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_85_c_compstr2422_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_86_c_compstr2450_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_87_c_compstr2478_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_88_c_compstr2506_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_89_c_compstr2534_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_8_c_compstr266_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_90_c_compstr2562_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_91_c_compstr2590_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_92_c_compstr2618_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_93_c_compstr2646_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_94_c_compstr2674_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_95_c_compstr2702_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_96_c_compstr2730_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_97_c_compstr2758_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_98_c_compstr2786_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_99_c_compstr2814_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_9_c_compstr294_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_c_compstr42_sel_x_b;
    wire [4:0] bgTrunc_i_fpga_indvars_iv_next14_c_compstr3611_sel_x_b;
    wire [31:0] bgTrunc_i_inc44_c_compstr3604_sel_x_b;
    wire [33:0] i_conv_i_i_i84_i_c_compstr22_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_100_c_compstr2822_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_101_c_compstr2850_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_102_c_compstr2878_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_103_c_compstr2906_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_104_c_compstr2934_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_105_c_compstr2962_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_106_c_compstr2990_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_107_c_compstr3018_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_108_c_compstr3046_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_109_c_compstr3074_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_10_c_compstr302_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_110_c_compstr3102_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_111_c_compstr3130_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_112_c_compstr3158_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_113_c_compstr3186_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_114_c_compstr3214_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_115_c_compstr3242_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_116_c_compstr3270_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_117_c_compstr3298_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_118_c_compstr3326_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_119_c_compstr3354_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_11_c_compstr330_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_120_c_compstr3382_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_121_c_compstr3410_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_122_c_compstr3438_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_123_c_compstr3466_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_124_c_compstr3494_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_125_c_compstr3522_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_126_c_compstr3550_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_127_c_compstr3578_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_12_c_compstr358_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_13_c_compstr386_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_14_c_compstr414_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_15_c_compstr442_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_16_c_compstr470_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_17_c_compstr498_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_18_c_compstr526_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_19_c_compstr554_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_1_c_compstr50_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_20_c_compstr582_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_21_c_compstr610_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_22_c_compstr638_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_23_c_compstr666_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_24_c_compstr694_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_25_c_compstr722_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_26_c_compstr750_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_27_c_compstr778_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_28_c_compstr806_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_29_c_compstr834_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_2_c_compstr78_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_30_c_compstr862_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_31_c_compstr890_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_32_c_compstr918_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_33_c_compstr946_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_34_c_compstr974_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_35_c_compstr1002_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_36_c_compstr1030_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_37_c_compstr1058_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_38_c_compstr1086_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_39_c_compstr1114_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_3_c_compstr106_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_40_c_compstr1142_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_41_c_compstr1170_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_42_c_compstr1198_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_43_c_compstr1226_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_44_c_compstr1254_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_45_c_compstr1282_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_46_c_compstr1310_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_47_c_compstr1338_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_48_c_compstr1366_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_49_c_compstr1394_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_4_c_compstr134_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_50_c_compstr1422_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_51_c_compstr1450_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_52_c_compstr1478_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_53_c_compstr1506_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_54_c_compstr1534_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_55_c_compstr1562_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_56_c_compstr1590_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_57_c_compstr1618_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_58_c_compstr1646_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_59_c_compstr1674_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_5_c_compstr162_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_60_c_compstr1702_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_61_c_compstr1730_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_62_c_compstr1758_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_63_c_compstr1786_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_64_c_compstr1814_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_65_c_compstr1842_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_66_c_compstr1870_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_67_c_compstr1898_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_68_c_compstr1926_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_69_c_compstr1954_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_6_c_compstr190_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_70_c_compstr1982_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_71_c_compstr2010_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_72_c_compstr2038_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_73_c_compstr2066_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_74_c_compstr2094_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_75_c_compstr2122_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_76_c_compstr2150_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_77_c_compstr2178_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_78_c_compstr2206_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_79_c_compstr2234_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_7_c_compstr218_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_80_c_compstr2262_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_81_c_compstr2290_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_82_c_compstr2318_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_83_c_compstr2346_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_84_c_compstr2374_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_85_c_compstr2402_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_86_c_compstr2430_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_87_c_compstr2458_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_88_c_compstr2486_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_89_c_compstr2514_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_8_c_compstr246_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_90_c_compstr2542_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_91_c_compstr2570_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_92_c_compstr2598_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_93_c_compstr2626_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_94_c_compstr2654_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_95_c_compstr2682_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_96_c_compstr2710_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_97_c_compstr2738_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_98_c_compstr2766_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_99_c_compstr2794_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_9_c_compstr274_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_c_compstr24_sel_x_b;
    wire [33:0] i_conv_i_i_i_i_c_compstr36_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_100_c_compstr2818_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_101_c_compstr2846_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_102_c_compstr2874_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_103_c_compstr2902_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_104_c_compstr2930_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_105_c_compstr2958_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_106_c_compstr2986_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_107_c_compstr3014_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_108_c_compstr3042_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_109_c_compstr3070_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_10_c_compstr298_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_110_c_compstr3098_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_111_c_compstr3126_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_112_c_compstr3154_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_113_c_compstr3182_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_114_c_compstr3210_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_115_c_compstr3238_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_116_c_compstr3266_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_117_c_compstr3294_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_118_c_compstr3322_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_119_c_compstr3350_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_11_c_compstr326_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_120_c_compstr3378_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_121_c_compstr3406_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_122_c_compstr3434_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_123_c_compstr3462_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_124_c_compstr3490_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_125_c_compstr3518_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_126_c_compstr3546_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_127_c_compstr3574_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_12_c_compstr354_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_13_c_compstr382_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_14_c_compstr410_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_15_c_compstr438_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_16_c_compstr466_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_17_c_compstr494_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_18_c_compstr522_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_19_c_compstr550_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_1_c_compstr46_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_20_c_compstr578_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_21_c_compstr606_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_22_c_compstr634_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_23_c_compstr662_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_24_c_compstr690_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_25_c_compstr718_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_26_c_compstr746_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_27_c_compstr774_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_28_c_compstr802_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_29_c_compstr830_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_2_c_compstr74_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_30_c_compstr858_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_31_c_compstr886_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_32_c_compstr914_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_33_c_compstr942_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_34_c_compstr970_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_35_c_compstr998_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_36_c_compstr1026_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_37_c_compstr1054_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_38_c_compstr1082_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_39_c_compstr1110_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_3_c_compstr102_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_40_c_compstr1138_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_41_c_compstr1166_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_42_c_compstr1194_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_43_c_compstr1222_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_44_c_compstr1250_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_45_c_compstr1278_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_46_c_compstr1306_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_47_c_compstr1334_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_48_c_compstr1362_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_49_c_compstr1390_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_4_c_compstr130_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_50_c_compstr1418_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_51_c_compstr1446_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_52_c_compstr1474_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_53_c_compstr1502_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_54_c_compstr1530_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_55_c_compstr1558_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_56_c_compstr1586_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_57_c_compstr1614_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_58_c_compstr1642_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_59_c_compstr1670_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_5_c_compstr158_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_60_c_compstr1698_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_61_c_compstr1726_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_62_c_compstr1754_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_63_c_compstr1782_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_64_c_compstr1810_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_65_c_compstr1838_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_66_c_compstr1866_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_67_c_compstr1894_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_68_c_compstr1922_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_69_c_compstr1950_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_6_c_compstr186_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_70_c_compstr1978_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_71_c_compstr2006_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_72_c_compstr2034_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_73_c_compstr2062_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_74_c_compstr2090_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_75_c_compstr2118_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_76_c_compstr2146_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_77_c_compstr2174_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_78_c_compstr2202_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_79_c_compstr2230_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_7_c_compstr214_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_80_c_compstr2258_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_81_c_compstr2286_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_82_c_compstr2314_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_83_c_compstr2342_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_84_c_compstr2370_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_85_c_compstr2398_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_86_c_compstr2426_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_87_c_compstr2454_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_88_c_compstr2482_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_89_c_compstr2510_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_8_c_compstr242_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_90_c_compstr2538_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_91_c_compstr2566_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_92_c_compstr2594_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_93_c_compstr2622_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_94_c_compstr2650_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_95_c_compstr2678_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_96_c_compstr2706_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_97_c_compstr2734_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_98_c_compstr2762_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_99_c_compstr2790_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_9_c_compstr270_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_100_c_compstr2838_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_101_c_compstr2866_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_102_c_compstr2894_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_103_c_compstr2922_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_104_c_compstr2950_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_105_c_compstr2978_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_106_c_compstr3006_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_107_c_compstr3034_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_108_c_compstr3062_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_109_c_compstr3090_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_10_c_compstr318_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_110_c_compstr3118_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_111_c_compstr3146_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_112_c_compstr3174_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_113_c_compstr3202_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_114_c_compstr3230_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_115_c_compstr3258_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_116_c_compstr3286_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_117_c_compstr3314_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_118_c_compstr3342_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_119_c_compstr3370_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_11_c_compstr346_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_120_c_compstr3398_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_121_c_compstr3426_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_122_c_compstr3454_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_123_c_compstr3482_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_124_c_compstr3510_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_125_c_compstr3538_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_126_c_compstr3566_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_127_c_compstr3594_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_12_c_compstr374_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_13_c_compstr402_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_14_c_compstr430_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_15_c_compstr458_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_16_c_compstr486_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_17_c_compstr514_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_18_c_compstr542_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_19_c_compstr570_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_1_c_compstr66_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_20_c_compstr598_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_21_c_compstr626_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_22_c_compstr654_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_23_c_compstr682_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_24_c_compstr710_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_25_c_compstr738_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_26_c_compstr766_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_27_c_compstr794_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_28_c_compstr822_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_29_c_compstr850_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_2_c_compstr94_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_30_c_compstr878_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_31_c_compstr906_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_32_c_compstr934_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_33_c_compstr962_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_34_c_compstr990_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_35_c_compstr1018_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_36_c_compstr1046_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_37_c_compstr1074_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_38_c_compstr1102_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_39_c_compstr1130_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_3_c_compstr122_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_40_c_compstr1158_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_41_c_compstr1186_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_42_c_compstr1214_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_43_c_compstr1242_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_44_c_compstr1270_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_45_c_compstr1298_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_46_c_compstr1326_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_47_c_compstr1354_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_48_c_compstr1382_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_49_c_compstr1410_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_4_c_compstr150_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_50_c_compstr1438_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_51_c_compstr1466_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_52_c_compstr1494_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_53_c_compstr1522_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_54_c_compstr1550_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_55_c_compstr1578_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_56_c_compstr1606_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_57_c_compstr1634_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_58_c_compstr1662_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_59_c_compstr1690_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_5_c_compstr178_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_60_c_compstr1718_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_61_c_compstr1746_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_62_c_compstr1774_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_63_c_compstr1802_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_64_c_compstr1830_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_65_c_compstr1858_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_66_c_compstr1886_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_67_c_compstr1914_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_68_c_compstr1942_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_69_c_compstr1970_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_6_c_compstr206_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_70_c_compstr1998_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_71_c_compstr2026_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_72_c_compstr2054_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_73_c_compstr2082_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_74_c_compstr2110_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_75_c_compstr2138_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_76_c_compstr2166_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_77_c_compstr2194_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_78_c_compstr2222_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_79_c_compstr2250_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_7_c_compstr234_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_80_c_compstr2278_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_81_c_compstr2306_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_82_c_compstr2334_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_83_c_compstr2362_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_84_c_compstr2390_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_85_c_compstr2418_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_86_c_compstr2446_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_87_c_compstr2474_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_88_c_compstr2502_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_89_c_compstr2530_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_8_c_compstr262_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_90_c_compstr2558_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_91_c_compstr2586_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_92_c_compstr2614_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_93_c_compstr2642_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_94_c_compstr2670_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_95_c_compstr2698_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_96_c_compstr2726_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_97_c_compstr2754_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_98_c_compstr2782_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_99_c_compstr2810_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_9_c_compstr290_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_c_compstr38_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_100_c_compstr2834_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_101_c_compstr2862_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_102_c_compstr2890_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_103_c_compstr2918_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_104_c_compstr2946_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_105_c_compstr2974_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_106_c_compstr3002_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_107_c_compstr3030_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_108_c_compstr3058_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_109_c_compstr3086_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_10_c_compstr314_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_110_c_compstr3114_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_111_c_compstr3142_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_112_c_compstr3170_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_113_c_compstr3198_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_114_c_compstr3226_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_115_c_compstr3254_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_116_c_compstr3282_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_117_c_compstr3310_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_118_c_compstr3338_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_119_c_compstr3366_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_11_c_compstr342_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_120_c_compstr3394_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_121_c_compstr3422_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_122_c_compstr3450_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_123_c_compstr3478_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_124_c_compstr3506_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_125_c_compstr3534_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_126_c_compstr3562_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_127_c_compstr3590_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_12_c_compstr370_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_13_c_compstr398_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_14_c_compstr426_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_15_c_compstr454_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_16_c_compstr482_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_17_c_compstr510_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_18_c_compstr538_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_19_c_compstr566_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_1_c_compstr62_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_20_c_compstr594_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_21_c_compstr622_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_22_c_compstr650_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_23_c_compstr678_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_24_c_compstr706_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_25_c_compstr734_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_26_c_compstr762_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_27_c_compstr790_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_28_c_compstr818_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_29_c_compstr846_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_2_c_compstr90_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_30_c_compstr874_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_31_c_compstr902_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_32_c_compstr930_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_33_c_compstr958_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_34_c_compstr986_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_35_c_compstr1014_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_36_c_compstr1042_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_37_c_compstr1070_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_38_c_compstr1098_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_39_c_compstr1126_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_3_c_compstr118_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_40_c_compstr1154_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_41_c_compstr1182_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_42_c_compstr1210_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_43_c_compstr1238_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_44_c_compstr1266_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_45_c_compstr1294_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_46_c_compstr1322_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_47_c_compstr1350_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_48_c_compstr1378_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_49_c_compstr1406_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_4_c_compstr146_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_50_c_compstr1434_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_51_c_compstr1462_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_52_c_compstr1490_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_53_c_compstr1518_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_54_c_compstr1546_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_55_c_compstr1574_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_56_c_compstr1602_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_57_c_compstr1630_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_58_c_compstr1658_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_59_c_compstr1686_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_5_c_compstr174_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_60_c_compstr1714_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_61_c_compstr1742_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_62_c_compstr1770_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_63_c_compstr1798_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_64_c_compstr1826_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_65_c_compstr1854_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_66_c_compstr1882_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_67_c_compstr1910_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_68_c_compstr1938_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_69_c_compstr1966_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_6_c_compstr202_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_70_c_compstr1994_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_71_c_compstr2022_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_72_c_compstr2050_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_73_c_compstr2078_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_74_c_compstr2106_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_75_c_compstr2134_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_76_c_compstr2162_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_77_c_compstr2190_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_78_c_compstr2218_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_79_c_compstr2246_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_7_c_compstr230_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_80_c_compstr2274_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_81_c_compstr2302_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_82_c_compstr2330_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_83_c_compstr2358_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_84_c_compstr2386_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_85_c_compstr2414_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_86_c_compstr2442_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_87_c_compstr2470_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_88_c_compstr2498_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_89_c_compstr2526_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_8_c_compstr258_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_90_c_compstr2554_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_91_c_compstr2582_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_92_c_compstr2610_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_93_c_compstr2638_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_94_c_compstr2666_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_95_c_compstr2694_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_96_c_compstr2722_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_97_c_compstr2750_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_98_c_compstr2778_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_99_c_compstr2806_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_9_c_compstr286_sel_x_b;
    wire [63:0] i_idxprom36_c_compstr10_sel_x_b;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_0_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_1_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_2_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_3_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_4_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_5_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl;
    wire [31:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount;
    wire [511:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write;
    wire [4095:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_0_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_1_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_2_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_3_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_4_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_5_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl;
    wire [31:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount;
    wire [511:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write;
    wire [4095:0] i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata;
    wire [0:0] i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr4_mux_x_s;
    reg [0:0] i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr4_mux_x_q;
    wire [0:0] i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr0_i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr9_mux_x_s;
    reg [31:0] i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr0_i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr9_mux_x_q;
    wire [0:0] i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr0_i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr3605_mux_x_s;
    reg [4:0] i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr0_i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr3605_mux_x_q;
    wire [0:0] i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_adapt_scalar_trunc4_sel_x_b;
    wire [6:0] i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_c_i7_03_x_q;
    wire [7:0] i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_element_extension2_x_q;
    wire [0:0] i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_i_valid;
    wire i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_i_stall;
    wire i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_i_stall_bitsignaltemp;
    wire [7:0] i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_i_data;
    wire [7:0] i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_o_data;
    wire [0:0] i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q;
    wire [0:0] i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_i_valid;
    wire i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_i_stall;
    wire i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_i_stall_bitsignaltemp;
    wire [31:0] i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_i_data;
    wire [31:0] i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_o_data;
    wire [4:0] i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_adapt_scalar_trunc4_sel_x_b;
    wire [2:0] i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_c_i3_03_x_q;
    wire [7:0] i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_element_extension2_x_q;
    wire [0:0] i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_i_valid;
    wire i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_i_stall;
    wire i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_i_stall_bitsignaltemp;
    wire [7:0] i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_i_data;
    wire [7:0] i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_o_data;
    wire [0:0] i_memcoalesce_load_c_compstr_fpgaunique_5126_toi1_intcast_c_compstr13_sel_x_b;
    wire [0:0] i_memcoalesce_load_c_compstr_fpgaunique_5138_toi1_intcast_c_compstr18_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1004_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1020_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1032_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1048_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1060_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1076_sel_x_b;
    wire [15:0] i_unnamed_c_compstr108_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1088_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1104_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1116_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1132_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1144_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1160_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1172_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1188_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1200_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1216_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1228_sel_x_b;
    wire [15:0] i_unnamed_c_compstr124_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1244_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1256_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1272_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1284_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1300_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1312_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1328_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1340_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1356_sel_x_b;
    wire [15:0] i_unnamed_c_compstr136_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1368_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1384_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1396_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1412_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1424_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1440_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1452_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1468_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1480_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1496_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1508_sel_x_b;
    wire [15:0] i_unnamed_c_compstr152_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1524_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1536_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1552_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1564_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1580_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1592_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1608_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1620_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1636_sel_x_b;
    wire [15:0] i_unnamed_c_compstr164_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1648_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1664_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1676_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1692_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1704_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1720_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1732_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1748_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1760_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1776_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1788_sel_x_b;
    wire [15:0] i_unnamed_c_compstr180_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1804_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1816_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1832_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1844_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1860_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1872_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1888_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1900_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1916_sel_x_b;
    wire [15:0] i_unnamed_c_compstr192_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1928_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1944_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1956_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1972_sel_x_b;
    wire [15:0] i_unnamed_c_compstr1984_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2000_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2012_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2028_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2040_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2056_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2068_sel_x_b;
    wire [15:0] i_unnamed_c_compstr208_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2084_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2096_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2112_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2124_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2140_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2152_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2168_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2180_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2196_sel_x_b;
    wire [15:0] i_unnamed_c_compstr220_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2208_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2224_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2236_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2252_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2264_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2280_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2292_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2308_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2320_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2336_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2348_sel_x_b;
    wire [15:0] i_unnamed_c_compstr236_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2364_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2376_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2392_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2404_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2420_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2432_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2448_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2460_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2476_sel_x_b;
    wire [15:0] i_unnamed_c_compstr248_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2488_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2504_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2516_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2532_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2544_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2560_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2572_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2588_sel_x_b;
    wire [15:0] i_unnamed_c_compstr26_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2600_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2616_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2628_sel_x_b;
    wire [15:0] i_unnamed_c_compstr264_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2644_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2656_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2672_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2684_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2700_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2712_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2728_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2740_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2756_sel_x_b;
    wire [15:0] i_unnamed_c_compstr276_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2768_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2784_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2796_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2812_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2824_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2840_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2852_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2868_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2880_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2896_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2908_sel_x_b;
    wire [15:0] i_unnamed_c_compstr292_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2924_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2936_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2952_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2964_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2980_sel_x_b;
    wire [15:0] i_unnamed_c_compstr2992_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3008_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3020_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3036_sel_x_b;
    wire [15:0] i_unnamed_c_compstr304_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3048_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3064_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3076_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3092_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3104_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3120_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3132_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3148_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3160_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3176_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3188_sel_x_b;
    wire [15:0] i_unnamed_c_compstr320_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3204_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3216_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3232_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3244_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3260_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3272_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3288_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3300_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3316_sel_x_b;
    wire [15:0] i_unnamed_c_compstr332_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3328_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3344_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3356_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3372_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3384_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3400_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3412_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3428_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3440_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3456_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3468_sel_x_b;
    wire [15:0] i_unnamed_c_compstr348_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3484_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3496_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3512_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3524_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3540_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3552_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3568_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3580_sel_x_b;
    wire [15:0] i_unnamed_c_compstr3596_sel_x_b;
    wire [15:0] i_unnamed_c_compstr360_sel_x_b;
    wire [15:0] i_unnamed_c_compstr376_sel_x_b;
    wire [15:0] i_unnamed_c_compstr388_sel_x_b;
    wire [15:0] i_unnamed_c_compstr40_sel_x_b;
    wire [15:0] i_unnamed_c_compstr404_sel_x_b;
    wire [15:0] i_unnamed_c_compstr416_sel_x_b;
    wire [15:0] i_unnamed_c_compstr432_sel_x_b;
    wire [15:0] i_unnamed_c_compstr444_sel_x_b;
    wire [15:0] i_unnamed_c_compstr460_sel_x_b;
    wire [15:0] i_unnamed_c_compstr472_sel_x_b;
    wire [15:0] i_unnamed_c_compstr488_sel_x_b;
    wire [15:0] i_unnamed_c_compstr500_sel_x_b;
    wire [15:0] i_unnamed_c_compstr516_sel_x_b;
    wire [15:0] i_unnamed_c_compstr52_sel_x_b;
    wire [15:0] i_unnamed_c_compstr528_sel_x_b;
    wire [15:0] i_unnamed_c_compstr544_sel_x_b;
    wire [15:0] i_unnamed_c_compstr556_sel_x_b;
    wire [15:0] i_unnamed_c_compstr572_sel_x_b;
    wire [15:0] i_unnamed_c_compstr584_sel_x_b;
    wire [15:0] i_unnamed_c_compstr600_sel_x_b;
    wire [15:0] i_unnamed_c_compstr612_sel_x_b;
    wire [15:0] i_unnamed_c_compstr628_sel_x_b;
    wire [15:0] i_unnamed_c_compstr640_sel_x_b;
    wire [15:0] i_unnamed_c_compstr656_sel_x_b;
    wire [15:0] i_unnamed_c_compstr668_sel_x_b;
    wire [15:0] i_unnamed_c_compstr68_sel_x_b;
    wire [15:0] i_unnamed_c_compstr684_sel_x_b;
    wire [15:0] i_unnamed_c_compstr696_sel_x_b;
    wire [15:0] i_unnamed_c_compstr712_sel_x_b;
    wire [15:0] i_unnamed_c_compstr724_sel_x_b;
    wire [15:0] i_unnamed_c_compstr740_sel_x_b;
    wire [15:0] i_unnamed_c_compstr752_sel_x_b;
    wire [15:0] i_unnamed_c_compstr768_sel_x_b;
    wire [15:0] i_unnamed_c_compstr780_sel_x_b;
    wire [15:0] i_unnamed_c_compstr796_sel_x_b;
    wire [15:0] i_unnamed_c_compstr80_sel_x_b;
    wire [15:0] i_unnamed_c_compstr808_sel_x_b;
    wire [15:0] i_unnamed_c_compstr824_sel_x_b;
    wire [15:0] i_unnamed_c_compstr836_sel_x_b;
    wire [15:0] i_unnamed_c_compstr852_sel_x_b;
    wire [15:0] i_unnamed_c_compstr864_sel_x_b;
    wire [15:0] i_unnamed_c_compstr880_sel_x_b;
    wire [15:0] i_unnamed_c_compstr892_sel_x_b;
    wire [15:0] i_unnamed_c_compstr908_sel_x_b;
    wire [15:0] i_unnamed_c_compstr920_sel_x_b;
    wire [15:0] i_unnamed_c_compstr936_sel_x_b;
    wire [15:0] i_unnamed_c_compstr948_sel_x_b;
    wire [15:0] i_unnamed_c_compstr96_sel_x_b;
    wire [15:0] i_unnamed_c_compstr964_sel_x_b;
    wire [15:0] i_unnamed_c_compstr976_sel_x_b;
    wire [15:0] i_unnamed_c_compstr992_sel_x_b;
    wire [12:0] i_value2_i_i157_i3_c_compstr0_dupName_0_trunc_sel_x_b;
    wire [12:0] i_value2_i_i157_i3_c_compstr0_dupName_2_trunc_sel_x_b;
    wire [13:0] i_value2_i_i157_i3_c_compstr0_add_x_a;
    wire [13:0] i_value2_i_i157_i3_c_compstr0_add_x_b;
    logic [13:0] i_value2_i_i157_i3_c_compstr0_add_x_o;
    wire [13:0] i_value2_i_i157_i3_c_compstr0_add_x_q;
    wire [63:0] i_value2_i_i157_i3_c_compstr0_append_upper_bits_x_q;
    wire [8:0] i_value2_i_i157_i3_c_compstr0_c_i9_01_x_q;
    wire [3:0] i_value2_i_i157_i3_c_compstr0_narrow_x_b;
    wire [12:0] i_value2_i_i157_i3_c_compstr0_shift_join_x_q;
    wire [63:0] c_c_compSTR_W_pmem_q;
    wire [31:0] c_i32_03636_q;
    wire [31:0] c_i32_13647_q;
    wire [4:0] c_i5_13650_q;
    wire [4:0] c_i5_143648_q;
    wire [63:0] c_i64_46297004169368698883637_q;
    wire [16:0] i_add_i_i_i_i_i126_i_100_c_compstr2826_a;
    wire [16:0] i_add_i_i_i_i_i126_i_100_c_compstr2826_b;
    logic [16:0] i_add_i_i_i_i_i126_i_100_c_compstr2826_o;
    wire [16:0] i_add_i_i_i_i_i126_i_100_c_compstr2826_q;
    wire [16:0] i_add_i_i_i_i_i126_i_101_c_compstr2854_a;
    wire [16:0] i_add_i_i_i_i_i126_i_101_c_compstr2854_b;
    logic [16:0] i_add_i_i_i_i_i126_i_101_c_compstr2854_o;
    wire [16:0] i_add_i_i_i_i_i126_i_101_c_compstr2854_q;
    wire [16:0] i_add_i_i_i_i_i126_i_102_c_compstr2882_a;
    wire [16:0] i_add_i_i_i_i_i126_i_102_c_compstr2882_b;
    logic [16:0] i_add_i_i_i_i_i126_i_102_c_compstr2882_o;
    wire [16:0] i_add_i_i_i_i_i126_i_102_c_compstr2882_q;
    wire [16:0] i_add_i_i_i_i_i126_i_103_c_compstr2910_a;
    wire [16:0] i_add_i_i_i_i_i126_i_103_c_compstr2910_b;
    logic [16:0] i_add_i_i_i_i_i126_i_103_c_compstr2910_o;
    wire [16:0] i_add_i_i_i_i_i126_i_103_c_compstr2910_q;
    wire [16:0] i_add_i_i_i_i_i126_i_104_c_compstr2938_a;
    wire [16:0] i_add_i_i_i_i_i126_i_104_c_compstr2938_b;
    logic [16:0] i_add_i_i_i_i_i126_i_104_c_compstr2938_o;
    wire [16:0] i_add_i_i_i_i_i126_i_104_c_compstr2938_q;
    wire [16:0] i_add_i_i_i_i_i126_i_105_c_compstr2966_a;
    wire [16:0] i_add_i_i_i_i_i126_i_105_c_compstr2966_b;
    logic [16:0] i_add_i_i_i_i_i126_i_105_c_compstr2966_o;
    wire [16:0] i_add_i_i_i_i_i126_i_105_c_compstr2966_q;
    wire [16:0] i_add_i_i_i_i_i126_i_106_c_compstr2994_a;
    wire [16:0] i_add_i_i_i_i_i126_i_106_c_compstr2994_b;
    logic [16:0] i_add_i_i_i_i_i126_i_106_c_compstr2994_o;
    wire [16:0] i_add_i_i_i_i_i126_i_106_c_compstr2994_q;
    wire [16:0] i_add_i_i_i_i_i126_i_107_c_compstr3022_a;
    wire [16:0] i_add_i_i_i_i_i126_i_107_c_compstr3022_b;
    logic [16:0] i_add_i_i_i_i_i126_i_107_c_compstr3022_o;
    wire [16:0] i_add_i_i_i_i_i126_i_107_c_compstr3022_q;
    wire [16:0] i_add_i_i_i_i_i126_i_108_c_compstr3050_a;
    wire [16:0] i_add_i_i_i_i_i126_i_108_c_compstr3050_b;
    logic [16:0] i_add_i_i_i_i_i126_i_108_c_compstr3050_o;
    wire [16:0] i_add_i_i_i_i_i126_i_108_c_compstr3050_q;
    wire [16:0] i_add_i_i_i_i_i126_i_109_c_compstr3078_a;
    wire [16:0] i_add_i_i_i_i_i126_i_109_c_compstr3078_b;
    logic [16:0] i_add_i_i_i_i_i126_i_109_c_compstr3078_o;
    wire [16:0] i_add_i_i_i_i_i126_i_109_c_compstr3078_q;
    wire [16:0] i_add_i_i_i_i_i126_i_10_c_compstr306_a;
    wire [16:0] i_add_i_i_i_i_i126_i_10_c_compstr306_b;
    logic [16:0] i_add_i_i_i_i_i126_i_10_c_compstr306_o;
    wire [16:0] i_add_i_i_i_i_i126_i_10_c_compstr306_q;
    wire [16:0] i_add_i_i_i_i_i126_i_110_c_compstr3106_a;
    wire [16:0] i_add_i_i_i_i_i126_i_110_c_compstr3106_b;
    logic [16:0] i_add_i_i_i_i_i126_i_110_c_compstr3106_o;
    wire [16:0] i_add_i_i_i_i_i126_i_110_c_compstr3106_q;
    wire [16:0] i_add_i_i_i_i_i126_i_111_c_compstr3134_a;
    wire [16:0] i_add_i_i_i_i_i126_i_111_c_compstr3134_b;
    logic [16:0] i_add_i_i_i_i_i126_i_111_c_compstr3134_o;
    wire [16:0] i_add_i_i_i_i_i126_i_111_c_compstr3134_q;
    wire [16:0] i_add_i_i_i_i_i126_i_112_c_compstr3162_a;
    wire [16:0] i_add_i_i_i_i_i126_i_112_c_compstr3162_b;
    logic [16:0] i_add_i_i_i_i_i126_i_112_c_compstr3162_o;
    wire [16:0] i_add_i_i_i_i_i126_i_112_c_compstr3162_q;
    wire [16:0] i_add_i_i_i_i_i126_i_113_c_compstr3190_a;
    wire [16:0] i_add_i_i_i_i_i126_i_113_c_compstr3190_b;
    logic [16:0] i_add_i_i_i_i_i126_i_113_c_compstr3190_o;
    wire [16:0] i_add_i_i_i_i_i126_i_113_c_compstr3190_q;
    wire [16:0] i_add_i_i_i_i_i126_i_114_c_compstr3218_a;
    wire [16:0] i_add_i_i_i_i_i126_i_114_c_compstr3218_b;
    logic [16:0] i_add_i_i_i_i_i126_i_114_c_compstr3218_o;
    wire [16:0] i_add_i_i_i_i_i126_i_114_c_compstr3218_q;
    wire [16:0] i_add_i_i_i_i_i126_i_115_c_compstr3246_a;
    wire [16:0] i_add_i_i_i_i_i126_i_115_c_compstr3246_b;
    logic [16:0] i_add_i_i_i_i_i126_i_115_c_compstr3246_o;
    wire [16:0] i_add_i_i_i_i_i126_i_115_c_compstr3246_q;
    wire [16:0] i_add_i_i_i_i_i126_i_116_c_compstr3274_a;
    wire [16:0] i_add_i_i_i_i_i126_i_116_c_compstr3274_b;
    logic [16:0] i_add_i_i_i_i_i126_i_116_c_compstr3274_o;
    wire [16:0] i_add_i_i_i_i_i126_i_116_c_compstr3274_q;
    wire [16:0] i_add_i_i_i_i_i126_i_117_c_compstr3302_a;
    wire [16:0] i_add_i_i_i_i_i126_i_117_c_compstr3302_b;
    logic [16:0] i_add_i_i_i_i_i126_i_117_c_compstr3302_o;
    wire [16:0] i_add_i_i_i_i_i126_i_117_c_compstr3302_q;
    wire [16:0] i_add_i_i_i_i_i126_i_118_c_compstr3330_a;
    wire [16:0] i_add_i_i_i_i_i126_i_118_c_compstr3330_b;
    logic [16:0] i_add_i_i_i_i_i126_i_118_c_compstr3330_o;
    wire [16:0] i_add_i_i_i_i_i126_i_118_c_compstr3330_q;
    wire [16:0] i_add_i_i_i_i_i126_i_119_c_compstr3358_a;
    wire [16:0] i_add_i_i_i_i_i126_i_119_c_compstr3358_b;
    logic [16:0] i_add_i_i_i_i_i126_i_119_c_compstr3358_o;
    wire [16:0] i_add_i_i_i_i_i126_i_119_c_compstr3358_q;
    wire [16:0] i_add_i_i_i_i_i126_i_11_c_compstr334_a;
    wire [16:0] i_add_i_i_i_i_i126_i_11_c_compstr334_b;
    logic [16:0] i_add_i_i_i_i_i126_i_11_c_compstr334_o;
    wire [16:0] i_add_i_i_i_i_i126_i_11_c_compstr334_q;
    wire [16:0] i_add_i_i_i_i_i126_i_120_c_compstr3386_a;
    wire [16:0] i_add_i_i_i_i_i126_i_120_c_compstr3386_b;
    logic [16:0] i_add_i_i_i_i_i126_i_120_c_compstr3386_o;
    wire [16:0] i_add_i_i_i_i_i126_i_120_c_compstr3386_q;
    wire [16:0] i_add_i_i_i_i_i126_i_121_c_compstr3414_a;
    wire [16:0] i_add_i_i_i_i_i126_i_121_c_compstr3414_b;
    logic [16:0] i_add_i_i_i_i_i126_i_121_c_compstr3414_o;
    wire [16:0] i_add_i_i_i_i_i126_i_121_c_compstr3414_q;
    wire [16:0] i_add_i_i_i_i_i126_i_122_c_compstr3442_a;
    wire [16:0] i_add_i_i_i_i_i126_i_122_c_compstr3442_b;
    logic [16:0] i_add_i_i_i_i_i126_i_122_c_compstr3442_o;
    wire [16:0] i_add_i_i_i_i_i126_i_122_c_compstr3442_q;
    wire [16:0] i_add_i_i_i_i_i126_i_123_c_compstr3470_a;
    wire [16:0] i_add_i_i_i_i_i126_i_123_c_compstr3470_b;
    logic [16:0] i_add_i_i_i_i_i126_i_123_c_compstr3470_o;
    wire [16:0] i_add_i_i_i_i_i126_i_123_c_compstr3470_q;
    wire [16:0] i_add_i_i_i_i_i126_i_124_c_compstr3498_a;
    wire [16:0] i_add_i_i_i_i_i126_i_124_c_compstr3498_b;
    logic [16:0] i_add_i_i_i_i_i126_i_124_c_compstr3498_o;
    wire [16:0] i_add_i_i_i_i_i126_i_124_c_compstr3498_q;
    wire [16:0] i_add_i_i_i_i_i126_i_125_c_compstr3526_a;
    wire [16:0] i_add_i_i_i_i_i126_i_125_c_compstr3526_b;
    logic [16:0] i_add_i_i_i_i_i126_i_125_c_compstr3526_o;
    wire [16:0] i_add_i_i_i_i_i126_i_125_c_compstr3526_q;
    wire [16:0] i_add_i_i_i_i_i126_i_126_c_compstr3554_a;
    wire [16:0] i_add_i_i_i_i_i126_i_126_c_compstr3554_b;
    logic [16:0] i_add_i_i_i_i_i126_i_126_c_compstr3554_o;
    wire [16:0] i_add_i_i_i_i_i126_i_126_c_compstr3554_q;
    wire [16:0] i_add_i_i_i_i_i126_i_127_c_compstr3582_a;
    wire [16:0] i_add_i_i_i_i_i126_i_127_c_compstr3582_b;
    logic [16:0] i_add_i_i_i_i_i126_i_127_c_compstr3582_o;
    wire [16:0] i_add_i_i_i_i_i126_i_127_c_compstr3582_q;
    wire [16:0] i_add_i_i_i_i_i126_i_12_c_compstr362_a;
    wire [16:0] i_add_i_i_i_i_i126_i_12_c_compstr362_b;
    logic [16:0] i_add_i_i_i_i_i126_i_12_c_compstr362_o;
    wire [16:0] i_add_i_i_i_i_i126_i_12_c_compstr362_q;
    wire [16:0] i_add_i_i_i_i_i126_i_13_c_compstr390_a;
    wire [16:0] i_add_i_i_i_i_i126_i_13_c_compstr390_b;
    logic [16:0] i_add_i_i_i_i_i126_i_13_c_compstr390_o;
    wire [16:0] i_add_i_i_i_i_i126_i_13_c_compstr390_q;
    wire [16:0] i_add_i_i_i_i_i126_i_14_c_compstr418_a;
    wire [16:0] i_add_i_i_i_i_i126_i_14_c_compstr418_b;
    logic [16:0] i_add_i_i_i_i_i126_i_14_c_compstr418_o;
    wire [16:0] i_add_i_i_i_i_i126_i_14_c_compstr418_q;
    wire [16:0] i_add_i_i_i_i_i126_i_15_c_compstr446_a;
    wire [16:0] i_add_i_i_i_i_i126_i_15_c_compstr446_b;
    logic [16:0] i_add_i_i_i_i_i126_i_15_c_compstr446_o;
    wire [16:0] i_add_i_i_i_i_i126_i_15_c_compstr446_q;
    wire [16:0] i_add_i_i_i_i_i126_i_16_c_compstr474_a;
    wire [16:0] i_add_i_i_i_i_i126_i_16_c_compstr474_b;
    logic [16:0] i_add_i_i_i_i_i126_i_16_c_compstr474_o;
    wire [16:0] i_add_i_i_i_i_i126_i_16_c_compstr474_q;
    wire [16:0] i_add_i_i_i_i_i126_i_17_c_compstr502_a;
    wire [16:0] i_add_i_i_i_i_i126_i_17_c_compstr502_b;
    logic [16:0] i_add_i_i_i_i_i126_i_17_c_compstr502_o;
    wire [16:0] i_add_i_i_i_i_i126_i_17_c_compstr502_q;
    wire [16:0] i_add_i_i_i_i_i126_i_18_c_compstr530_a;
    wire [16:0] i_add_i_i_i_i_i126_i_18_c_compstr530_b;
    logic [16:0] i_add_i_i_i_i_i126_i_18_c_compstr530_o;
    wire [16:0] i_add_i_i_i_i_i126_i_18_c_compstr530_q;
    wire [16:0] i_add_i_i_i_i_i126_i_19_c_compstr558_a;
    wire [16:0] i_add_i_i_i_i_i126_i_19_c_compstr558_b;
    logic [16:0] i_add_i_i_i_i_i126_i_19_c_compstr558_o;
    wire [16:0] i_add_i_i_i_i_i126_i_19_c_compstr558_q;
    wire [16:0] i_add_i_i_i_i_i126_i_1_c_compstr54_a;
    wire [16:0] i_add_i_i_i_i_i126_i_1_c_compstr54_b;
    logic [16:0] i_add_i_i_i_i_i126_i_1_c_compstr54_o;
    wire [16:0] i_add_i_i_i_i_i126_i_1_c_compstr54_q;
    wire [16:0] i_add_i_i_i_i_i126_i_20_c_compstr586_a;
    wire [16:0] i_add_i_i_i_i_i126_i_20_c_compstr586_b;
    logic [16:0] i_add_i_i_i_i_i126_i_20_c_compstr586_o;
    wire [16:0] i_add_i_i_i_i_i126_i_20_c_compstr586_q;
    wire [16:0] i_add_i_i_i_i_i126_i_21_c_compstr614_a;
    wire [16:0] i_add_i_i_i_i_i126_i_21_c_compstr614_b;
    logic [16:0] i_add_i_i_i_i_i126_i_21_c_compstr614_o;
    wire [16:0] i_add_i_i_i_i_i126_i_21_c_compstr614_q;
    wire [16:0] i_add_i_i_i_i_i126_i_22_c_compstr642_a;
    wire [16:0] i_add_i_i_i_i_i126_i_22_c_compstr642_b;
    logic [16:0] i_add_i_i_i_i_i126_i_22_c_compstr642_o;
    wire [16:0] i_add_i_i_i_i_i126_i_22_c_compstr642_q;
    wire [16:0] i_add_i_i_i_i_i126_i_23_c_compstr670_a;
    wire [16:0] i_add_i_i_i_i_i126_i_23_c_compstr670_b;
    logic [16:0] i_add_i_i_i_i_i126_i_23_c_compstr670_o;
    wire [16:0] i_add_i_i_i_i_i126_i_23_c_compstr670_q;
    wire [16:0] i_add_i_i_i_i_i126_i_24_c_compstr698_a;
    wire [16:0] i_add_i_i_i_i_i126_i_24_c_compstr698_b;
    logic [16:0] i_add_i_i_i_i_i126_i_24_c_compstr698_o;
    wire [16:0] i_add_i_i_i_i_i126_i_24_c_compstr698_q;
    wire [16:0] i_add_i_i_i_i_i126_i_25_c_compstr726_a;
    wire [16:0] i_add_i_i_i_i_i126_i_25_c_compstr726_b;
    logic [16:0] i_add_i_i_i_i_i126_i_25_c_compstr726_o;
    wire [16:0] i_add_i_i_i_i_i126_i_25_c_compstr726_q;
    wire [16:0] i_add_i_i_i_i_i126_i_26_c_compstr754_a;
    wire [16:0] i_add_i_i_i_i_i126_i_26_c_compstr754_b;
    logic [16:0] i_add_i_i_i_i_i126_i_26_c_compstr754_o;
    wire [16:0] i_add_i_i_i_i_i126_i_26_c_compstr754_q;
    wire [16:0] i_add_i_i_i_i_i126_i_27_c_compstr782_a;
    wire [16:0] i_add_i_i_i_i_i126_i_27_c_compstr782_b;
    logic [16:0] i_add_i_i_i_i_i126_i_27_c_compstr782_o;
    wire [16:0] i_add_i_i_i_i_i126_i_27_c_compstr782_q;
    wire [16:0] i_add_i_i_i_i_i126_i_28_c_compstr810_a;
    wire [16:0] i_add_i_i_i_i_i126_i_28_c_compstr810_b;
    logic [16:0] i_add_i_i_i_i_i126_i_28_c_compstr810_o;
    wire [16:0] i_add_i_i_i_i_i126_i_28_c_compstr810_q;
    wire [16:0] i_add_i_i_i_i_i126_i_29_c_compstr838_a;
    wire [16:0] i_add_i_i_i_i_i126_i_29_c_compstr838_b;
    logic [16:0] i_add_i_i_i_i_i126_i_29_c_compstr838_o;
    wire [16:0] i_add_i_i_i_i_i126_i_29_c_compstr838_q;
    wire [16:0] i_add_i_i_i_i_i126_i_2_c_compstr82_a;
    wire [16:0] i_add_i_i_i_i_i126_i_2_c_compstr82_b;
    logic [16:0] i_add_i_i_i_i_i126_i_2_c_compstr82_o;
    wire [16:0] i_add_i_i_i_i_i126_i_2_c_compstr82_q;
    wire [16:0] i_add_i_i_i_i_i126_i_30_c_compstr866_a;
    wire [16:0] i_add_i_i_i_i_i126_i_30_c_compstr866_b;
    logic [16:0] i_add_i_i_i_i_i126_i_30_c_compstr866_o;
    wire [16:0] i_add_i_i_i_i_i126_i_30_c_compstr866_q;
    wire [16:0] i_add_i_i_i_i_i126_i_31_c_compstr894_a;
    wire [16:0] i_add_i_i_i_i_i126_i_31_c_compstr894_b;
    logic [16:0] i_add_i_i_i_i_i126_i_31_c_compstr894_o;
    wire [16:0] i_add_i_i_i_i_i126_i_31_c_compstr894_q;
    wire [16:0] i_add_i_i_i_i_i126_i_32_c_compstr922_a;
    wire [16:0] i_add_i_i_i_i_i126_i_32_c_compstr922_b;
    logic [16:0] i_add_i_i_i_i_i126_i_32_c_compstr922_o;
    wire [16:0] i_add_i_i_i_i_i126_i_32_c_compstr922_q;
    wire [16:0] i_add_i_i_i_i_i126_i_33_c_compstr950_a;
    wire [16:0] i_add_i_i_i_i_i126_i_33_c_compstr950_b;
    logic [16:0] i_add_i_i_i_i_i126_i_33_c_compstr950_o;
    wire [16:0] i_add_i_i_i_i_i126_i_33_c_compstr950_q;
    wire [16:0] i_add_i_i_i_i_i126_i_34_c_compstr978_a;
    wire [16:0] i_add_i_i_i_i_i126_i_34_c_compstr978_b;
    logic [16:0] i_add_i_i_i_i_i126_i_34_c_compstr978_o;
    wire [16:0] i_add_i_i_i_i_i126_i_34_c_compstr978_q;
    wire [16:0] i_add_i_i_i_i_i126_i_35_c_compstr1006_a;
    wire [16:0] i_add_i_i_i_i_i126_i_35_c_compstr1006_b;
    logic [16:0] i_add_i_i_i_i_i126_i_35_c_compstr1006_o;
    wire [16:0] i_add_i_i_i_i_i126_i_35_c_compstr1006_q;
    wire [16:0] i_add_i_i_i_i_i126_i_36_c_compstr1034_a;
    wire [16:0] i_add_i_i_i_i_i126_i_36_c_compstr1034_b;
    logic [16:0] i_add_i_i_i_i_i126_i_36_c_compstr1034_o;
    wire [16:0] i_add_i_i_i_i_i126_i_36_c_compstr1034_q;
    wire [16:0] i_add_i_i_i_i_i126_i_37_c_compstr1062_a;
    wire [16:0] i_add_i_i_i_i_i126_i_37_c_compstr1062_b;
    logic [16:0] i_add_i_i_i_i_i126_i_37_c_compstr1062_o;
    wire [16:0] i_add_i_i_i_i_i126_i_37_c_compstr1062_q;
    wire [16:0] i_add_i_i_i_i_i126_i_38_c_compstr1090_a;
    wire [16:0] i_add_i_i_i_i_i126_i_38_c_compstr1090_b;
    logic [16:0] i_add_i_i_i_i_i126_i_38_c_compstr1090_o;
    wire [16:0] i_add_i_i_i_i_i126_i_38_c_compstr1090_q;
    wire [16:0] i_add_i_i_i_i_i126_i_39_c_compstr1118_a;
    wire [16:0] i_add_i_i_i_i_i126_i_39_c_compstr1118_b;
    logic [16:0] i_add_i_i_i_i_i126_i_39_c_compstr1118_o;
    wire [16:0] i_add_i_i_i_i_i126_i_39_c_compstr1118_q;
    wire [16:0] i_add_i_i_i_i_i126_i_3_c_compstr110_a;
    wire [16:0] i_add_i_i_i_i_i126_i_3_c_compstr110_b;
    logic [16:0] i_add_i_i_i_i_i126_i_3_c_compstr110_o;
    wire [16:0] i_add_i_i_i_i_i126_i_3_c_compstr110_q;
    wire [16:0] i_add_i_i_i_i_i126_i_40_c_compstr1146_a;
    wire [16:0] i_add_i_i_i_i_i126_i_40_c_compstr1146_b;
    logic [16:0] i_add_i_i_i_i_i126_i_40_c_compstr1146_o;
    wire [16:0] i_add_i_i_i_i_i126_i_40_c_compstr1146_q;
    wire [16:0] i_add_i_i_i_i_i126_i_41_c_compstr1174_a;
    wire [16:0] i_add_i_i_i_i_i126_i_41_c_compstr1174_b;
    logic [16:0] i_add_i_i_i_i_i126_i_41_c_compstr1174_o;
    wire [16:0] i_add_i_i_i_i_i126_i_41_c_compstr1174_q;
    wire [16:0] i_add_i_i_i_i_i126_i_42_c_compstr1202_a;
    wire [16:0] i_add_i_i_i_i_i126_i_42_c_compstr1202_b;
    logic [16:0] i_add_i_i_i_i_i126_i_42_c_compstr1202_o;
    wire [16:0] i_add_i_i_i_i_i126_i_42_c_compstr1202_q;
    wire [16:0] i_add_i_i_i_i_i126_i_43_c_compstr1230_a;
    wire [16:0] i_add_i_i_i_i_i126_i_43_c_compstr1230_b;
    logic [16:0] i_add_i_i_i_i_i126_i_43_c_compstr1230_o;
    wire [16:0] i_add_i_i_i_i_i126_i_43_c_compstr1230_q;
    wire [16:0] i_add_i_i_i_i_i126_i_44_c_compstr1258_a;
    wire [16:0] i_add_i_i_i_i_i126_i_44_c_compstr1258_b;
    logic [16:0] i_add_i_i_i_i_i126_i_44_c_compstr1258_o;
    wire [16:0] i_add_i_i_i_i_i126_i_44_c_compstr1258_q;
    wire [16:0] i_add_i_i_i_i_i126_i_45_c_compstr1286_a;
    wire [16:0] i_add_i_i_i_i_i126_i_45_c_compstr1286_b;
    logic [16:0] i_add_i_i_i_i_i126_i_45_c_compstr1286_o;
    wire [16:0] i_add_i_i_i_i_i126_i_45_c_compstr1286_q;
    wire [16:0] i_add_i_i_i_i_i126_i_46_c_compstr1314_a;
    wire [16:0] i_add_i_i_i_i_i126_i_46_c_compstr1314_b;
    logic [16:0] i_add_i_i_i_i_i126_i_46_c_compstr1314_o;
    wire [16:0] i_add_i_i_i_i_i126_i_46_c_compstr1314_q;
    wire [16:0] i_add_i_i_i_i_i126_i_47_c_compstr1342_a;
    wire [16:0] i_add_i_i_i_i_i126_i_47_c_compstr1342_b;
    logic [16:0] i_add_i_i_i_i_i126_i_47_c_compstr1342_o;
    wire [16:0] i_add_i_i_i_i_i126_i_47_c_compstr1342_q;
    wire [16:0] i_add_i_i_i_i_i126_i_48_c_compstr1370_a;
    wire [16:0] i_add_i_i_i_i_i126_i_48_c_compstr1370_b;
    logic [16:0] i_add_i_i_i_i_i126_i_48_c_compstr1370_o;
    wire [16:0] i_add_i_i_i_i_i126_i_48_c_compstr1370_q;
    wire [16:0] i_add_i_i_i_i_i126_i_49_c_compstr1398_a;
    wire [16:0] i_add_i_i_i_i_i126_i_49_c_compstr1398_b;
    logic [16:0] i_add_i_i_i_i_i126_i_49_c_compstr1398_o;
    wire [16:0] i_add_i_i_i_i_i126_i_49_c_compstr1398_q;
    wire [16:0] i_add_i_i_i_i_i126_i_4_c_compstr138_a;
    wire [16:0] i_add_i_i_i_i_i126_i_4_c_compstr138_b;
    logic [16:0] i_add_i_i_i_i_i126_i_4_c_compstr138_o;
    wire [16:0] i_add_i_i_i_i_i126_i_4_c_compstr138_q;
    wire [16:0] i_add_i_i_i_i_i126_i_50_c_compstr1426_a;
    wire [16:0] i_add_i_i_i_i_i126_i_50_c_compstr1426_b;
    logic [16:0] i_add_i_i_i_i_i126_i_50_c_compstr1426_o;
    wire [16:0] i_add_i_i_i_i_i126_i_50_c_compstr1426_q;
    wire [16:0] i_add_i_i_i_i_i126_i_51_c_compstr1454_a;
    wire [16:0] i_add_i_i_i_i_i126_i_51_c_compstr1454_b;
    logic [16:0] i_add_i_i_i_i_i126_i_51_c_compstr1454_o;
    wire [16:0] i_add_i_i_i_i_i126_i_51_c_compstr1454_q;
    wire [16:0] i_add_i_i_i_i_i126_i_52_c_compstr1482_a;
    wire [16:0] i_add_i_i_i_i_i126_i_52_c_compstr1482_b;
    logic [16:0] i_add_i_i_i_i_i126_i_52_c_compstr1482_o;
    wire [16:0] i_add_i_i_i_i_i126_i_52_c_compstr1482_q;
    wire [16:0] i_add_i_i_i_i_i126_i_53_c_compstr1510_a;
    wire [16:0] i_add_i_i_i_i_i126_i_53_c_compstr1510_b;
    logic [16:0] i_add_i_i_i_i_i126_i_53_c_compstr1510_o;
    wire [16:0] i_add_i_i_i_i_i126_i_53_c_compstr1510_q;
    wire [16:0] i_add_i_i_i_i_i126_i_54_c_compstr1538_a;
    wire [16:0] i_add_i_i_i_i_i126_i_54_c_compstr1538_b;
    logic [16:0] i_add_i_i_i_i_i126_i_54_c_compstr1538_o;
    wire [16:0] i_add_i_i_i_i_i126_i_54_c_compstr1538_q;
    wire [16:0] i_add_i_i_i_i_i126_i_55_c_compstr1566_a;
    wire [16:0] i_add_i_i_i_i_i126_i_55_c_compstr1566_b;
    logic [16:0] i_add_i_i_i_i_i126_i_55_c_compstr1566_o;
    wire [16:0] i_add_i_i_i_i_i126_i_55_c_compstr1566_q;
    wire [16:0] i_add_i_i_i_i_i126_i_56_c_compstr1594_a;
    wire [16:0] i_add_i_i_i_i_i126_i_56_c_compstr1594_b;
    logic [16:0] i_add_i_i_i_i_i126_i_56_c_compstr1594_o;
    wire [16:0] i_add_i_i_i_i_i126_i_56_c_compstr1594_q;
    wire [16:0] i_add_i_i_i_i_i126_i_57_c_compstr1622_a;
    wire [16:0] i_add_i_i_i_i_i126_i_57_c_compstr1622_b;
    logic [16:0] i_add_i_i_i_i_i126_i_57_c_compstr1622_o;
    wire [16:0] i_add_i_i_i_i_i126_i_57_c_compstr1622_q;
    wire [16:0] i_add_i_i_i_i_i126_i_58_c_compstr1650_a;
    wire [16:0] i_add_i_i_i_i_i126_i_58_c_compstr1650_b;
    logic [16:0] i_add_i_i_i_i_i126_i_58_c_compstr1650_o;
    wire [16:0] i_add_i_i_i_i_i126_i_58_c_compstr1650_q;
    wire [16:0] i_add_i_i_i_i_i126_i_59_c_compstr1678_a;
    wire [16:0] i_add_i_i_i_i_i126_i_59_c_compstr1678_b;
    logic [16:0] i_add_i_i_i_i_i126_i_59_c_compstr1678_o;
    wire [16:0] i_add_i_i_i_i_i126_i_59_c_compstr1678_q;
    wire [16:0] i_add_i_i_i_i_i126_i_5_c_compstr166_a;
    wire [16:0] i_add_i_i_i_i_i126_i_5_c_compstr166_b;
    logic [16:0] i_add_i_i_i_i_i126_i_5_c_compstr166_o;
    wire [16:0] i_add_i_i_i_i_i126_i_5_c_compstr166_q;
    wire [16:0] i_add_i_i_i_i_i126_i_60_c_compstr1706_a;
    wire [16:0] i_add_i_i_i_i_i126_i_60_c_compstr1706_b;
    logic [16:0] i_add_i_i_i_i_i126_i_60_c_compstr1706_o;
    wire [16:0] i_add_i_i_i_i_i126_i_60_c_compstr1706_q;
    wire [16:0] i_add_i_i_i_i_i126_i_61_c_compstr1734_a;
    wire [16:0] i_add_i_i_i_i_i126_i_61_c_compstr1734_b;
    logic [16:0] i_add_i_i_i_i_i126_i_61_c_compstr1734_o;
    wire [16:0] i_add_i_i_i_i_i126_i_61_c_compstr1734_q;
    wire [16:0] i_add_i_i_i_i_i126_i_62_c_compstr1762_a;
    wire [16:0] i_add_i_i_i_i_i126_i_62_c_compstr1762_b;
    logic [16:0] i_add_i_i_i_i_i126_i_62_c_compstr1762_o;
    wire [16:0] i_add_i_i_i_i_i126_i_62_c_compstr1762_q;
    wire [16:0] i_add_i_i_i_i_i126_i_63_c_compstr1790_a;
    wire [16:0] i_add_i_i_i_i_i126_i_63_c_compstr1790_b;
    logic [16:0] i_add_i_i_i_i_i126_i_63_c_compstr1790_o;
    wire [16:0] i_add_i_i_i_i_i126_i_63_c_compstr1790_q;
    wire [16:0] i_add_i_i_i_i_i126_i_64_c_compstr1818_a;
    wire [16:0] i_add_i_i_i_i_i126_i_64_c_compstr1818_b;
    logic [16:0] i_add_i_i_i_i_i126_i_64_c_compstr1818_o;
    wire [16:0] i_add_i_i_i_i_i126_i_64_c_compstr1818_q;
    wire [16:0] i_add_i_i_i_i_i126_i_65_c_compstr1846_a;
    wire [16:0] i_add_i_i_i_i_i126_i_65_c_compstr1846_b;
    logic [16:0] i_add_i_i_i_i_i126_i_65_c_compstr1846_o;
    wire [16:0] i_add_i_i_i_i_i126_i_65_c_compstr1846_q;
    wire [16:0] i_add_i_i_i_i_i126_i_66_c_compstr1874_a;
    wire [16:0] i_add_i_i_i_i_i126_i_66_c_compstr1874_b;
    logic [16:0] i_add_i_i_i_i_i126_i_66_c_compstr1874_o;
    wire [16:0] i_add_i_i_i_i_i126_i_66_c_compstr1874_q;
    wire [16:0] i_add_i_i_i_i_i126_i_67_c_compstr1902_a;
    wire [16:0] i_add_i_i_i_i_i126_i_67_c_compstr1902_b;
    logic [16:0] i_add_i_i_i_i_i126_i_67_c_compstr1902_o;
    wire [16:0] i_add_i_i_i_i_i126_i_67_c_compstr1902_q;
    wire [16:0] i_add_i_i_i_i_i126_i_68_c_compstr1930_a;
    wire [16:0] i_add_i_i_i_i_i126_i_68_c_compstr1930_b;
    logic [16:0] i_add_i_i_i_i_i126_i_68_c_compstr1930_o;
    wire [16:0] i_add_i_i_i_i_i126_i_68_c_compstr1930_q;
    wire [16:0] i_add_i_i_i_i_i126_i_69_c_compstr1958_a;
    wire [16:0] i_add_i_i_i_i_i126_i_69_c_compstr1958_b;
    logic [16:0] i_add_i_i_i_i_i126_i_69_c_compstr1958_o;
    wire [16:0] i_add_i_i_i_i_i126_i_69_c_compstr1958_q;
    wire [16:0] i_add_i_i_i_i_i126_i_6_c_compstr194_a;
    wire [16:0] i_add_i_i_i_i_i126_i_6_c_compstr194_b;
    logic [16:0] i_add_i_i_i_i_i126_i_6_c_compstr194_o;
    wire [16:0] i_add_i_i_i_i_i126_i_6_c_compstr194_q;
    wire [16:0] i_add_i_i_i_i_i126_i_70_c_compstr1986_a;
    wire [16:0] i_add_i_i_i_i_i126_i_70_c_compstr1986_b;
    logic [16:0] i_add_i_i_i_i_i126_i_70_c_compstr1986_o;
    wire [16:0] i_add_i_i_i_i_i126_i_70_c_compstr1986_q;
    wire [16:0] i_add_i_i_i_i_i126_i_71_c_compstr2014_a;
    wire [16:0] i_add_i_i_i_i_i126_i_71_c_compstr2014_b;
    logic [16:0] i_add_i_i_i_i_i126_i_71_c_compstr2014_o;
    wire [16:0] i_add_i_i_i_i_i126_i_71_c_compstr2014_q;
    wire [16:0] i_add_i_i_i_i_i126_i_72_c_compstr2042_a;
    wire [16:0] i_add_i_i_i_i_i126_i_72_c_compstr2042_b;
    logic [16:0] i_add_i_i_i_i_i126_i_72_c_compstr2042_o;
    wire [16:0] i_add_i_i_i_i_i126_i_72_c_compstr2042_q;
    wire [16:0] i_add_i_i_i_i_i126_i_73_c_compstr2070_a;
    wire [16:0] i_add_i_i_i_i_i126_i_73_c_compstr2070_b;
    logic [16:0] i_add_i_i_i_i_i126_i_73_c_compstr2070_o;
    wire [16:0] i_add_i_i_i_i_i126_i_73_c_compstr2070_q;
    wire [16:0] i_add_i_i_i_i_i126_i_74_c_compstr2098_a;
    wire [16:0] i_add_i_i_i_i_i126_i_74_c_compstr2098_b;
    logic [16:0] i_add_i_i_i_i_i126_i_74_c_compstr2098_o;
    wire [16:0] i_add_i_i_i_i_i126_i_74_c_compstr2098_q;
    wire [16:0] i_add_i_i_i_i_i126_i_75_c_compstr2126_a;
    wire [16:0] i_add_i_i_i_i_i126_i_75_c_compstr2126_b;
    logic [16:0] i_add_i_i_i_i_i126_i_75_c_compstr2126_o;
    wire [16:0] i_add_i_i_i_i_i126_i_75_c_compstr2126_q;
    wire [16:0] i_add_i_i_i_i_i126_i_76_c_compstr2154_a;
    wire [16:0] i_add_i_i_i_i_i126_i_76_c_compstr2154_b;
    logic [16:0] i_add_i_i_i_i_i126_i_76_c_compstr2154_o;
    wire [16:0] i_add_i_i_i_i_i126_i_76_c_compstr2154_q;
    wire [16:0] i_add_i_i_i_i_i126_i_77_c_compstr2182_a;
    wire [16:0] i_add_i_i_i_i_i126_i_77_c_compstr2182_b;
    logic [16:0] i_add_i_i_i_i_i126_i_77_c_compstr2182_o;
    wire [16:0] i_add_i_i_i_i_i126_i_77_c_compstr2182_q;
    wire [16:0] i_add_i_i_i_i_i126_i_78_c_compstr2210_a;
    wire [16:0] i_add_i_i_i_i_i126_i_78_c_compstr2210_b;
    logic [16:0] i_add_i_i_i_i_i126_i_78_c_compstr2210_o;
    wire [16:0] i_add_i_i_i_i_i126_i_78_c_compstr2210_q;
    wire [16:0] i_add_i_i_i_i_i126_i_79_c_compstr2238_a;
    wire [16:0] i_add_i_i_i_i_i126_i_79_c_compstr2238_b;
    logic [16:0] i_add_i_i_i_i_i126_i_79_c_compstr2238_o;
    wire [16:0] i_add_i_i_i_i_i126_i_79_c_compstr2238_q;
    wire [16:0] i_add_i_i_i_i_i126_i_7_c_compstr222_a;
    wire [16:0] i_add_i_i_i_i_i126_i_7_c_compstr222_b;
    logic [16:0] i_add_i_i_i_i_i126_i_7_c_compstr222_o;
    wire [16:0] i_add_i_i_i_i_i126_i_7_c_compstr222_q;
    wire [16:0] i_add_i_i_i_i_i126_i_80_c_compstr2266_a;
    wire [16:0] i_add_i_i_i_i_i126_i_80_c_compstr2266_b;
    logic [16:0] i_add_i_i_i_i_i126_i_80_c_compstr2266_o;
    wire [16:0] i_add_i_i_i_i_i126_i_80_c_compstr2266_q;
    wire [16:0] i_add_i_i_i_i_i126_i_81_c_compstr2294_a;
    wire [16:0] i_add_i_i_i_i_i126_i_81_c_compstr2294_b;
    logic [16:0] i_add_i_i_i_i_i126_i_81_c_compstr2294_o;
    wire [16:0] i_add_i_i_i_i_i126_i_81_c_compstr2294_q;
    wire [16:0] i_add_i_i_i_i_i126_i_82_c_compstr2322_a;
    wire [16:0] i_add_i_i_i_i_i126_i_82_c_compstr2322_b;
    logic [16:0] i_add_i_i_i_i_i126_i_82_c_compstr2322_o;
    wire [16:0] i_add_i_i_i_i_i126_i_82_c_compstr2322_q;
    wire [16:0] i_add_i_i_i_i_i126_i_83_c_compstr2350_a;
    wire [16:0] i_add_i_i_i_i_i126_i_83_c_compstr2350_b;
    logic [16:0] i_add_i_i_i_i_i126_i_83_c_compstr2350_o;
    wire [16:0] i_add_i_i_i_i_i126_i_83_c_compstr2350_q;
    wire [16:0] i_add_i_i_i_i_i126_i_84_c_compstr2378_a;
    wire [16:0] i_add_i_i_i_i_i126_i_84_c_compstr2378_b;
    logic [16:0] i_add_i_i_i_i_i126_i_84_c_compstr2378_o;
    wire [16:0] i_add_i_i_i_i_i126_i_84_c_compstr2378_q;
    wire [16:0] i_add_i_i_i_i_i126_i_85_c_compstr2406_a;
    wire [16:0] i_add_i_i_i_i_i126_i_85_c_compstr2406_b;
    logic [16:0] i_add_i_i_i_i_i126_i_85_c_compstr2406_o;
    wire [16:0] i_add_i_i_i_i_i126_i_85_c_compstr2406_q;
    wire [16:0] i_add_i_i_i_i_i126_i_86_c_compstr2434_a;
    wire [16:0] i_add_i_i_i_i_i126_i_86_c_compstr2434_b;
    logic [16:0] i_add_i_i_i_i_i126_i_86_c_compstr2434_o;
    wire [16:0] i_add_i_i_i_i_i126_i_86_c_compstr2434_q;
    wire [16:0] i_add_i_i_i_i_i126_i_87_c_compstr2462_a;
    wire [16:0] i_add_i_i_i_i_i126_i_87_c_compstr2462_b;
    logic [16:0] i_add_i_i_i_i_i126_i_87_c_compstr2462_o;
    wire [16:0] i_add_i_i_i_i_i126_i_87_c_compstr2462_q;
    wire [16:0] i_add_i_i_i_i_i126_i_88_c_compstr2490_a;
    wire [16:0] i_add_i_i_i_i_i126_i_88_c_compstr2490_b;
    logic [16:0] i_add_i_i_i_i_i126_i_88_c_compstr2490_o;
    wire [16:0] i_add_i_i_i_i_i126_i_88_c_compstr2490_q;
    wire [16:0] i_add_i_i_i_i_i126_i_89_c_compstr2518_a;
    wire [16:0] i_add_i_i_i_i_i126_i_89_c_compstr2518_b;
    logic [16:0] i_add_i_i_i_i_i126_i_89_c_compstr2518_o;
    wire [16:0] i_add_i_i_i_i_i126_i_89_c_compstr2518_q;
    wire [16:0] i_add_i_i_i_i_i126_i_8_c_compstr250_a;
    wire [16:0] i_add_i_i_i_i_i126_i_8_c_compstr250_b;
    logic [16:0] i_add_i_i_i_i_i126_i_8_c_compstr250_o;
    wire [16:0] i_add_i_i_i_i_i126_i_8_c_compstr250_q;
    wire [16:0] i_add_i_i_i_i_i126_i_90_c_compstr2546_a;
    wire [16:0] i_add_i_i_i_i_i126_i_90_c_compstr2546_b;
    logic [16:0] i_add_i_i_i_i_i126_i_90_c_compstr2546_o;
    wire [16:0] i_add_i_i_i_i_i126_i_90_c_compstr2546_q;
    wire [16:0] i_add_i_i_i_i_i126_i_91_c_compstr2574_a;
    wire [16:0] i_add_i_i_i_i_i126_i_91_c_compstr2574_b;
    logic [16:0] i_add_i_i_i_i_i126_i_91_c_compstr2574_o;
    wire [16:0] i_add_i_i_i_i_i126_i_91_c_compstr2574_q;
    wire [16:0] i_add_i_i_i_i_i126_i_92_c_compstr2602_a;
    wire [16:0] i_add_i_i_i_i_i126_i_92_c_compstr2602_b;
    logic [16:0] i_add_i_i_i_i_i126_i_92_c_compstr2602_o;
    wire [16:0] i_add_i_i_i_i_i126_i_92_c_compstr2602_q;
    wire [16:0] i_add_i_i_i_i_i126_i_93_c_compstr2630_a;
    wire [16:0] i_add_i_i_i_i_i126_i_93_c_compstr2630_b;
    logic [16:0] i_add_i_i_i_i_i126_i_93_c_compstr2630_o;
    wire [16:0] i_add_i_i_i_i_i126_i_93_c_compstr2630_q;
    wire [16:0] i_add_i_i_i_i_i126_i_94_c_compstr2658_a;
    wire [16:0] i_add_i_i_i_i_i126_i_94_c_compstr2658_b;
    logic [16:0] i_add_i_i_i_i_i126_i_94_c_compstr2658_o;
    wire [16:0] i_add_i_i_i_i_i126_i_94_c_compstr2658_q;
    wire [16:0] i_add_i_i_i_i_i126_i_95_c_compstr2686_a;
    wire [16:0] i_add_i_i_i_i_i126_i_95_c_compstr2686_b;
    logic [16:0] i_add_i_i_i_i_i126_i_95_c_compstr2686_o;
    wire [16:0] i_add_i_i_i_i_i126_i_95_c_compstr2686_q;
    wire [16:0] i_add_i_i_i_i_i126_i_96_c_compstr2714_a;
    wire [16:0] i_add_i_i_i_i_i126_i_96_c_compstr2714_b;
    logic [16:0] i_add_i_i_i_i_i126_i_96_c_compstr2714_o;
    wire [16:0] i_add_i_i_i_i_i126_i_96_c_compstr2714_q;
    wire [16:0] i_add_i_i_i_i_i126_i_97_c_compstr2742_a;
    wire [16:0] i_add_i_i_i_i_i126_i_97_c_compstr2742_b;
    logic [16:0] i_add_i_i_i_i_i126_i_97_c_compstr2742_o;
    wire [16:0] i_add_i_i_i_i_i126_i_97_c_compstr2742_q;
    wire [16:0] i_add_i_i_i_i_i126_i_98_c_compstr2770_a;
    wire [16:0] i_add_i_i_i_i_i126_i_98_c_compstr2770_b;
    logic [16:0] i_add_i_i_i_i_i126_i_98_c_compstr2770_o;
    wire [16:0] i_add_i_i_i_i_i126_i_98_c_compstr2770_q;
    wire [16:0] i_add_i_i_i_i_i126_i_99_c_compstr2798_a;
    wire [16:0] i_add_i_i_i_i_i126_i_99_c_compstr2798_b;
    logic [16:0] i_add_i_i_i_i_i126_i_99_c_compstr2798_o;
    wire [16:0] i_add_i_i_i_i_i126_i_99_c_compstr2798_q;
    wire [16:0] i_add_i_i_i_i_i126_i_9_c_compstr278_a;
    wire [16:0] i_add_i_i_i_i_i126_i_9_c_compstr278_b;
    logic [16:0] i_add_i_i_i_i_i126_i_9_c_compstr278_o;
    wire [16:0] i_add_i_i_i_i_i126_i_9_c_compstr278_q;
    wire [16:0] i_add_i_i_i_i_i126_i_c_compstr28_a;
    wire [16:0] i_add_i_i_i_i_i126_i_c_compstr28_b;
    logic [16:0] i_add_i_i_i_i_i126_i_c_compstr28_o;
    wire [16:0] i_add_i_i_i_i_i126_i_c_compstr28_q;
    wire [16:0] i_add_i_i_i_i_i_i_100_c_compstr2842_a;
    wire [16:0] i_add_i_i_i_i_i_i_100_c_compstr2842_b;
    logic [16:0] i_add_i_i_i_i_i_i_100_c_compstr2842_o;
    wire [16:0] i_add_i_i_i_i_i_i_100_c_compstr2842_q;
    wire [16:0] i_add_i_i_i_i_i_i_101_c_compstr2870_a;
    wire [16:0] i_add_i_i_i_i_i_i_101_c_compstr2870_b;
    logic [16:0] i_add_i_i_i_i_i_i_101_c_compstr2870_o;
    wire [16:0] i_add_i_i_i_i_i_i_101_c_compstr2870_q;
    wire [16:0] i_add_i_i_i_i_i_i_102_c_compstr2898_a;
    wire [16:0] i_add_i_i_i_i_i_i_102_c_compstr2898_b;
    logic [16:0] i_add_i_i_i_i_i_i_102_c_compstr2898_o;
    wire [16:0] i_add_i_i_i_i_i_i_102_c_compstr2898_q;
    wire [16:0] i_add_i_i_i_i_i_i_103_c_compstr2926_a;
    wire [16:0] i_add_i_i_i_i_i_i_103_c_compstr2926_b;
    logic [16:0] i_add_i_i_i_i_i_i_103_c_compstr2926_o;
    wire [16:0] i_add_i_i_i_i_i_i_103_c_compstr2926_q;
    wire [16:0] i_add_i_i_i_i_i_i_104_c_compstr2954_a;
    wire [16:0] i_add_i_i_i_i_i_i_104_c_compstr2954_b;
    logic [16:0] i_add_i_i_i_i_i_i_104_c_compstr2954_o;
    wire [16:0] i_add_i_i_i_i_i_i_104_c_compstr2954_q;
    wire [16:0] i_add_i_i_i_i_i_i_105_c_compstr2982_a;
    wire [16:0] i_add_i_i_i_i_i_i_105_c_compstr2982_b;
    logic [16:0] i_add_i_i_i_i_i_i_105_c_compstr2982_o;
    wire [16:0] i_add_i_i_i_i_i_i_105_c_compstr2982_q;
    wire [16:0] i_add_i_i_i_i_i_i_106_c_compstr3010_a;
    wire [16:0] i_add_i_i_i_i_i_i_106_c_compstr3010_b;
    logic [16:0] i_add_i_i_i_i_i_i_106_c_compstr3010_o;
    wire [16:0] i_add_i_i_i_i_i_i_106_c_compstr3010_q;
    wire [16:0] i_add_i_i_i_i_i_i_107_c_compstr3038_a;
    wire [16:0] i_add_i_i_i_i_i_i_107_c_compstr3038_b;
    logic [16:0] i_add_i_i_i_i_i_i_107_c_compstr3038_o;
    wire [16:0] i_add_i_i_i_i_i_i_107_c_compstr3038_q;
    wire [16:0] i_add_i_i_i_i_i_i_108_c_compstr3066_a;
    wire [16:0] i_add_i_i_i_i_i_i_108_c_compstr3066_b;
    logic [16:0] i_add_i_i_i_i_i_i_108_c_compstr3066_o;
    wire [16:0] i_add_i_i_i_i_i_i_108_c_compstr3066_q;
    wire [16:0] i_add_i_i_i_i_i_i_109_c_compstr3094_a;
    wire [16:0] i_add_i_i_i_i_i_i_109_c_compstr3094_b;
    logic [16:0] i_add_i_i_i_i_i_i_109_c_compstr3094_o;
    wire [16:0] i_add_i_i_i_i_i_i_109_c_compstr3094_q;
    wire [16:0] i_add_i_i_i_i_i_i_10_c_compstr322_a;
    wire [16:0] i_add_i_i_i_i_i_i_10_c_compstr322_b;
    logic [16:0] i_add_i_i_i_i_i_i_10_c_compstr322_o;
    wire [16:0] i_add_i_i_i_i_i_i_10_c_compstr322_q;
    wire [16:0] i_add_i_i_i_i_i_i_110_c_compstr3122_a;
    wire [16:0] i_add_i_i_i_i_i_i_110_c_compstr3122_b;
    logic [16:0] i_add_i_i_i_i_i_i_110_c_compstr3122_o;
    wire [16:0] i_add_i_i_i_i_i_i_110_c_compstr3122_q;
    wire [16:0] i_add_i_i_i_i_i_i_111_c_compstr3150_a;
    wire [16:0] i_add_i_i_i_i_i_i_111_c_compstr3150_b;
    logic [16:0] i_add_i_i_i_i_i_i_111_c_compstr3150_o;
    wire [16:0] i_add_i_i_i_i_i_i_111_c_compstr3150_q;
    wire [16:0] i_add_i_i_i_i_i_i_112_c_compstr3178_a;
    wire [16:0] i_add_i_i_i_i_i_i_112_c_compstr3178_b;
    logic [16:0] i_add_i_i_i_i_i_i_112_c_compstr3178_o;
    wire [16:0] i_add_i_i_i_i_i_i_112_c_compstr3178_q;
    wire [16:0] i_add_i_i_i_i_i_i_113_c_compstr3206_a;
    wire [16:0] i_add_i_i_i_i_i_i_113_c_compstr3206_b;
    logic [16:0] i_add_i_i_i_i_i_i_113_c_compstr3206_o;
    wire [16:0] i_add_i_i_i_i_i_i_113_c_compstr3206_q;
    wire [16:0] i_add_i_i_i_i_i_i_114_c_compstr3234_a;
    wire [16:0] i_add_i_i_i_i_i_i_114_c_compstr3234_b;
    logic [16:0] i_add_i_i_i_i_i_i_114_c_compstr3234_o;
    wire [16:0] i_add_i_i_i_i_i_i_114_c_compstr3234_q;
    wire [16:0] i_add_i_i_i_i_i_i_115_c_compstr3262_a;
    wire [16:0] i_add_i_i_i_i_i_i_115_c_compstr3262_b;
    logic [16:0] i_add_i_i_i_i_i_i_115_c_compstr3262_o;
    wire [16:0] i_add_i_i_i_i_i_i_115_c_compstr3262_q;
    wire [16:0] i_add_i_i_i_i_i_i_116_c_compstr3290_a;
    wire [16:0] i_add_i_i_i_i_i_i_116_c_compstr3290_b;
    logic [16:0] i_add_i_i_i_i_i_i_116_c_compstr3290_o;
    wire [16:0] i_add_i_i_i_i_i_i_116_c_compstr3290_q;
    wire [16:0] i_add_i_i_i_i_i_i_117_c_compstr3318_a;
    wire [16:0] i_add_i_i_i_i_i_i_117_c_compstr3318_b;
    logic [16:0] i_add_i_i_i_i_i_i_117_c_compstr3318_o;
    wire [16:0] i_add_i_i_i_i_i_i_117_c_compstr3318_q;
    wire [16:0] i_add_i_i_i_i_i_i_118_c_compstr3346_a;
    wire [16:0] i_add_i_i_i_i_i_i_118_c_compstr3346_b;
    logic [16:0] i_add_i_i_i_i_i_i_118_c_compstr3346_o;
    wire [16:0] i_add_i_i_i_i_i_i_118_c_compstr3346_q;
    wire [16:0] i_add_i_i_i_i_i_i_119_c_compstr3374_a;
    wire [16:0] i_add_i_i_i_i_i_i_119_c_compstr3374_b;
    logic [16:0] i_add_i_i_i_i_i_i_119_c_compstr3374_o;
    wire [16:0] i_add_i_i_i_i_i_i_119_c_compstr3374_q;
    wire [16:0] i_add_i_i_i_i_i_i_11_c_compstr350_a;
    wire [16:0] i_add_i_i_i_i_i_i_11_c_compstr350_b;
    logic [16:0] i_add_i_i_i_i_i_i_11_c_compstr350_o;
    wire [16:0] i_add_i_i_i_i_i_i_11_c_compstr350_q;
    wire [16:0] i_add_i_i_i_i_i_i_120_c_compstr3402_a;
    wire [16:0] i_add_i_i_i_i_i_i_120_c_compstr3402_b;
    logic [16:0] i_add_i_i_i_i_i_i_120_c_compstr3402_o;
    wire [16:0] i_add_i_i_i_i_i_i_120_c_compstr3402_q;
    wire [16:0] i_add_i_i_i_i_i_i_121_c_compstr3430_a;
    wire [16:0] i_add_i_i_i_i_i_i_121_c_compstr3430_b;
    logic [16:0] i_add_i_i_i_i_i_i_121_c_compstr3430_o;
    wire [16:0] i_add_i_i_i_i_i_i_121_c_compstr3430_q;
    wire [16:0] i_add_i_i_i_i_i_i_122_c_compstr3458_a;
    wire [16:0] i_add_i_i_i_i_i_i_122_c_compstr3458_b;
    logic [16:0] i_add_i_i_i_i_i_i_122_c_compstr3458_o;
    wire [16:0] i_add_i_i_i_i_i_i_122_c_compstr3458_q;
    wire [16:0] i_add_i_i_i_i_i_i_123_c_compstr3486_a;
    wire [16:0] i_add_i_i_i_i_i_i_123_c_compstr3486_b;
    logic [16:0] i_add_i_i_i_i_i_i_123_c_compstr3486_o;
    wire [16:0] i_add_i_i_i_i_i_i_123_c_compstr3486_q;
    wire [16:0] i_add_i_i_i_i_i_i_124_c_compstr3514_a;
    wire [16:0] i_add_i_i_i_i_i_i_124_c_compstr3514_b;
    logic [16:0] i_add_i_i_i_i_i_i_124_c_compstr3514_o;
    wire [16:0] i_add_i_i_i_i_i_i_124_c_compstr3514_q;
    wire [16:0] i_add_i_i_i_i_i_i_125_c_compstr3542_a;
    wire [16:0] i_add_i_i_i_i_i_i_125_c_compstr3542_b;
    logic [16:0] i_add_i_i_i_i_i_i_125_c_compstr3542_o;
    wire [16:0] i_add_i_i_i_i_i_i_125_c_compstr3542_q;
    wire [16:0] i_add_i_i_i_i_i_i_126_c_compstr3570_a;
    wire [16:0] i_add_i_i_i_i_i_i_126_c_compstr3570_b;
    logic [16:0] i_add_i_i_i_i_i_i_126_c_compstr3570_o;
    wire [16:0] i_add_i_i_i_i_i_i_126_c_compstr3570_q;
    wire [16:0] i_add_i_i_i_i_i_i_127_c_compstr3598_a;
    wire [16:0] i_add_i_i_i_i_i_i_127_c_compstr3598_b;
    logic [16:0] i_add_i_i_i_i_i_i_127_c_compstr3598_o;
    wire [16:0] i_add_i_i_i_i_i_i_127_c_compstr3598_q;
    wire [16:0] i_add_i_i_i_i_i_i_12_c_compstr378_a;
    wire [16:0] i_add_i_i_i_i_i_i_12_c_compstr378_b;
    logic [16:0] i_add_i_i_i_i_i_i_12_c_compstr378_o;
    wire [16:0] i_add_i_i_i_i_i_i_12_c_compstr378_q;
    wire [16:0] i_add_i_i_i_i_i_i_13_c_compstr406_a;
    wire [16:0] i_add_i_i_i_i_i_i_13_c_compstr406_b;
    logic [16:0] i_add_i_i_i_i_i_i_13_c_compstr406_o;
    wire [16:0] i_add_i_i_i_i_i_i_13_c_compstr406_q;
    wire [16:0] i_add_i_i_i_i_i_i_14_c_compstr434_a;
    wire [16:0] i_add_i_i_i_i_i_i_14_c_compstr434_b;
    logic [16:0] i_add_i_i_i_i_i_i_14_c_compstr434_o;
    wire [16:0] i_add_i_i_i_i_i_i_14_c_compstr434_q;
    wire [16:0] i_add_i_i_i_i_i_i_15_c_compstr462_a;
    wire [16:0] i_add_i_i_i_i_i_i_15_c_compstr462_b;
    logic [16:0] i_add_i_i_i_i_i_i_15_c_compstr462_o;
    wire [16:0] i_add_i_i_i_i_i_i_15_c_compstr462_q;
    wire [16:0] i_add_i_i_i_i_i_i_16_c_compstr490_a;
    wire [16:0] i_add_i_i_i_i_i_i_16_c_compstr490_b;
    logic [16:0] i_add_i_i_i_i_i_i_16_c_compstr490_o;
    wire [16:0] i_add_i_i_i_i_i_i_16_c_compstr490_q;
    wire [16:0] i_add_i_i_i_i_i_i_17_c_compstr518_a;
    wire [16:0] i_add_i_i_i_i_i_i_17_c_compstr518_b;
    logic [16:0] i_add_i_i_i_i_i_i_17_c_compstr518_o;
    wire [16:0] i_add_i_i_i_i_i_i_17_c_compstr518_q;
    wire [16:0] i_add_i_i_i_i_i_i_18_c_compstr546_a;
    wire [16:0] i_add_i_i_i_i_i_i_18_c_compstr546_b;
    logic [16:0] i_add_i_i_i_i_i_i_18_c_compstr546_o;
    wire [16:0] i_add_i_i_i_i_i_i_18_c_compstr546_q;
    wire [16:0] i_add_i_i_i_i_i_i_19_c_compstr574_a;
    wire [16:0] i_add_i_i_i_i_i_i_19_c_compstr574_b;
    logic [16:0] i_add_i_i_i_i_i_i_19_c_compstr574_o;
    wire [16:0] i_add_i_i_i_i_i_i_19_c_compstr574_q;
    wire [16:0] i_add_i_i_i_i_i_i_1_c_compstr70_a;
    wire [16:0] i_add_i_i_i_i_i_i_1_c_compstr70_b;
    logic [16:0] i_add_i_i_i_i_i_i_1_c_compstr70_o;
    wire [16:0] i_add_i_i_i_i_i_i_1_c_compstr70_q;
    wire [16:0] i_add_i_i_i_i_i_i_20_c_compstr602_a;
    wire [16:0] i_add_i_i_i_i_i_i_20_c_compstr602_b;
    logic [16:0] i_add_i_i_i_i_i_i_20_c_compstr602_o;
    wire [16:0] i_add_i_i_i_i_i_i_20_c_compstr602_q;
    wire [16:0] i_add_i_i_i_i_i_i_21_c_compstr630_a;
    wire [16:0] i_add_i_i_i_i_i_i_21_c_compstr630_b;
    logic [16:0] i_add_i_i_i_i_i_i_21_c_compstr630_o;
    wire [16:0] i_add_i_i_i_i_i_i_21_c_compstr630_q;
    wire [16:0] i_add_i_i_i_i_i_i_22_c_compstr658_a;
    wire [16:0] i_add_i_i_i_i_i_i_22_c_compstr658_b;
    logic [16:0] i_add_i_i_i_i_i_i_22_c_compstr658_o;
    wire [16:0] i_add_i_i_i_i_i_i_22_c_compstr658_q;
    wire [16:0] i_add_i_i_i_i_i_i_23_c_compstr686_a;
    wire [16:0] i_add_i_i_i_i_i_i_23_c_compstr686_b;
    logic [16:0] i_add_i_i_i_i_i_i_23_c_compstr686_o;
    wire [16:0] i_add_i_i_i_i_i_i_23_c_compstr686_q;
    wire [16:0] i_add_i_i_i_i_i_i_24_c_compstr714_a;
    wire [16:0] i_add_i_i_i_i_i_i_24_c_compstr714_b;
    logic [16:0] i_add_i_i_i_i_i_i_24_c_compstr714_o;
    wire [16:0] i_add_i_i_i_i_i_i_24_c_compstr714_q;
    wire [16:0] i_add_i_i_i_i_i_i_25_c_compstr742_a;
    wire [16:0] i_add_i_i_i_i_i_i_25_c_compstr742_b;
    logic [16:0] i_add_i_i_i_i_i_i_25_c_compstr742_o;
    wire [16:0] i_add_i_i_i_i_i_i_25_c_compstr742_q;
    wire [16:0] i_add_i_i_i_i_i_i_26_c_compstr770_a;
    wire [16:0] i_add_i_i_i_i_i_i_26_c_compstr770_b;
    logic [16:0] i_add_i_i_i_i_i_i_26_c_compstr770_o;
    wire [16:0] i_add_i_i_i_i_i_i_26_c_compstr770_q;
    wire [16:0] i_add_i_i_i_i_i_i_27_c_compstr798_a;
    wire [16:0] i_add_i_i_i_i_i_i_27_c_compstr798_b;
    logic [16:0] i_add_i_i_i_i_i_i_27_c_compstr798_o;
    wire [16:0] i_add_i_i_i_i_i_i_27_c_compstr798_q;
    wire [16:0] i_add_i_i_i_i_i_i_28_c_compstr826_a;
    wire [16:0] i_add_i_i_i_i_i_i_28_c_compstr826_b;
    logic [16:0] i_add_i_i_i_i_i_i_28_c_compstr826_o;
    wire [16:0] i_add_i_i_i_i_i_i_28_c_compstr826_q;
    wire [16:0] i_add_i_i_i_i_i_i_29_c_compstr854_a;
    wire [16:0] i_add_i_i_i_i_i_i_29_c_compstr854_b;
    logic [16:0] i_add_i_i_i_i_i_i_29_c_compstr854_o;
    wire [16:0] i_add_i_i_i_i_i_i_29_c_compstr854_q;
    wire [16:0] i_add_i_i_i_i_i_i_2_c_compstr98_a;
    wire [16:0] i_add_i_i_i_i_i_i_2_c_compstr98_b;
    logic [16:0] i_add_i_i_i_i_i_i_2_c_compstr98_o;
    wire [16:0] i_add_i_i_i_i_i_i_2_c_compstr98_q;
    wire [16:0] i_add_i_i_i_i_i_i_30_c_compstr882_a;
    wire [16:0] i_add_i_i_i_i_i_i_30_c_compstr882_b;
    logic [16:0] i_add_i_i_i_i_i_i_30_c_compstr882_o;
    wire [16:0] i_add_i_i_i_i_i_i_30_c_compstr882_q;
    wire [16:0] i_add_i_i_i_i_i_i_31_c_compstr910_a;
    wire [16:0] i_add_i_i_i_i_i_i_31_c_compstr910_b;
    logic [16:0] i_add_i_i_i_i_i_i_31_c_compstr910_o;
    wire [16:0] i_add_i_i_i_i_i_i_31_c_compstr910_q;
    wire [16:0] i_add_i_i_i_i_i_i_32_c_compstr938_a;
    wire [16:0] i_add_i_i_i_i_i_i_32_c_compstr938_b;
    logic [16:0] i_add_i_i_i_i_i_i_32_c_compstr938_o;
    wire [16:0] i_add_i_i_i_i_i_i_32_c_compstr938_q;
    wire [16:0] i_add_i_i_i_i_i_i_33_c_compstr966_a;
    wire [16:0] i_add_i_i_i_i_i_i_33_c_compstr966_b;
    logic [16:0] i_add_i_i_i_i_i_i_33_c_compstr966_o;
    wire [16:0] i_add_i_i_i_i_i_i_33_c_compstr966_q;
    wire [16:0] i_add_i_i_i_i_i_i_34_c_compstr994_a;
    wire [16:0] i_add_i_i_i_i_i_i_34_c_compstr994_b;
    logic [16:0] i_add_i_i_i_i_i_i_34_c_compstr994_o;
    wire [16:0] i_add_i_i_i_i_i_i_34_c_compstr994_q;
    wire [16:0] i_add_i_i_i_i_i_i_35_c_compstr1022_a;
    wire [16:0] i_add_i_i_i_i_i_i_35_c_compstr1022_b;
    logic [16:0] i_add_i_i_i_i_i_i_35_c_compstr1022_o;
    wire [16:0] i_add_i_i_i_i_i_i_35_c_compstr1022_q;
    wire [16:0] i_add_i_i_i_i_i_i_36_c_compstr1050_a;
    wire [16:0] i_add_i_i_i_i_i_i_36_c_compstr1050_b;
    logic [16:0] i_add_i_i_i_i_i_i_36_c_compstr1050_o;
    wire [16:0] i_add_i_i_i_i_i_i_36_c_compstr1050_q;
    wire [16:0] i_add_i_i_i_i_i_i_37_c_compstr1078_a;
    wire [16:0] i_add_i_i_i_i_i_i_37_c_compstr1078_b;
    logic [16:0] i_add_i_i_i_i_i_i_37_c_compstr1078_o;
    wire [16:0] i_add_i_i_i_i_i_i_37_c_compstr1078_q;
    wire [16:0] i_add_i_i_i_i_i_i_38_c_compstr1106_a;
    wire [16:0] i_add_i_i_i_i_i_i_38_c_compstr1106_b;
    logic [16:0] i_add_i_i_i_i_i_i_38_c_compstr1106_o;
    wire [16:0] i_add_i_i_i_i_i_i_38_c_compstr1106_q;
    wire [16:0] i_add_i_i_i_i_i_i_39_c_compstr1134_a;
    wire [16:0] i_add_i_i_i_i_i_i_39_c_compstr1134_b;
    logic [16:0] i_add_i_i_i_i_i_i_39_c_compstr1134_o;
    wire [16:0] i_add_i_i_i_i_i_i_39_c_compstr1134_q;
    wire [16:0] i_add_i_i_i_i_i_i_3_c_compstr126_a;
    wire [16:0] i_add_i_i_i_i_i_i_3_c_compstr126_b;
    logic [16:0] i_add_i_i_i_i_i_i_3_c_compstr126_o;
    wire [16:0] i_add_i_i_i_i_i_i_3_c_compstr126_q;
    wire [16:0] i_add_i_i_i_i_i_i_40_c_compstr1162_a;
    wire [16:0] i_add_i_i_i_i_i_i_40_c_compstr1162_b;
    logic [16:0] i_add_i_i_i_i_i_i_40_c_compstr1162_o;
    wire [16:0] i_add_i_i_i_i_i_i_40_c_compstr1162_q;
    wire [16:0] i_add_i_i_i_i_i_i_41_c_compstr1190_a;
    wire [16:0] i_add_i_i_i_i_i_i_41_c_compstr1190_b;
    logic [16:0] i_add_i_i_i_i_i_i_41_c_compstr1190_o;
    wire [16:0] i_add_i_i_i_i_i_i_41_c_compstr1190_q;
    wire [16:0] i_add_i_i_i_i_i_i_42_c_compstr1218_a;
    wire [16:0] i_add_i_i_i_i_i_i_42_c_compstr1218_b;
    logic [16:0] i_add_i_i_i_i_i_i_42_c_compstr1218_o;
    wire [16:0] i_add_i_i_i_i_i_i_42_c_compstr1218_q;
    wire [16:0] i_add_i_i_i_i_i_i_43_c_compstr1246_a;
    wire [16:0] i_add_i_i_i_i_i_i_43_c_compstr1246_b;
    logic [16:0] i_add_i_i_i_i_i_i_43_c_compstr1246_o;
    wire [16:0] i_add_i_i_i_i_i_i_43_c_compstr1246_q;
    wire [16:0] i_add_i_i_i_i_i_i_44_c_compstr1274_a;
    wire [16:0] i_add_i_i_i_i_i_i_44_c_compstr1274_b;
    logic [16:0] i_add_i_i_i_i_i_i_44_c_compstr1274_o;
    wire [16:0] i_add_i_i_i_i_i_i_44_c_compstr1274_q;
    wire [16:0] i_add_i_i_i_i_i_i_45_c_compstr1302_a;
    wire [16:0] i_add_i_i_i_i_i_i_45_c_compstr1302_b;
    logic [16:0] i_add_i_i_i_i_i_i_45_c_compstr1302_o;
    wire [16:0] i_add_i_i_i_i_i_i_45_c_compstr1302_q;
    wire [16:0] i_add_i_i_i_i_i_i_46_c_compstr1330_a;
    wire [16:0] i_add_i_i_i_i_i_i_46_c_compstr1330_b;
    logic [16:0] i_add_i_i_i_i_i_i_46_c_compstr1330_o;
    wire [16:0] i_add_i_i_i_i_i_i_46_c_compstr1330_q;
    wire [16:0] i_add_i_i_i_i_i_i_47_c_compstr1358_a;
    wire [16:0] i_add_i_i_i_i_i_i_47_c_compstr1358_b;
    logic [16:0] i_add_i_i_i_i_i_i_47_c_compstr1358_o;
    wire [16:0] i_add_i_i_i_i_i_i_47_c_compstr1358_q;
    wire [16:0] i_add_i_i_i_i_i_i_48_c_compstr1386_a;
    wire [16:0] i_add_i_i_i_i_i_i_48_c_compstr1386_b;
    logic [16:0] i_add_i_i_i_i_i_i_48_c_compstr1386_o;
    wire [16:0] i_add_i_i_i_i_i_i_48_c_compstr1386_q;
    wire [16:0] i_add_i_i_i_i_i_i_49_c_compstr1414_a;
    wire [16:0] i_add_i_i_i_i_i_i_49_c_compstr1414_b;
    logic [16:0] i_add_i_i_i_i_i_i_49_c_compstr1414_o;
    wire [16:0] i_add_i_i_i_i_i_i_49_c_compstr1414_q;
    wire [16:0] i_add_i_i_i_i_i_i_4_c_compstr154_a;
    wire [16:0] i_add_i_i_i_i_i_i_4_c_compstr154_b;
    logic [16:0] i_add_i_i_i_i_i_i_4_c_compstr154_o;
    wire [16:0] i_add_i_i_i_i_i_i_4_c_compstr154_q;
    wire [16:0] i_add_i_i_i_i_i_i_50_c_compstr1442_a;
    wire [16:0] i_add_i_i_i_i_i_i_50_c_compstr1442_b;
    logic [16:0] i_add_i_i_i_i_i_i_50_c_compstr1442_o;
    wire [16:0] i_add_i_i_i_i_i_i_50_c_compstr1442_q;
    wire [16:0] i_add_i_i_i_i_i_i_51_c_compstr1470_a;
    wire [16:0] i_add_i_i_i_i_i_i_51_c_compstr1470_b;
    logic [16:0] i_add_i_i_i_i_i_i_51_c_compstr1470_o;
    wire [16:0] i_add_i_i_i_i_i_i_51_c_compstr1470_q;
    wire [16:0] i_add_i_i_i_i_i_i_52_c_compstr1498_a;
    wire [16:0] i_add_i_i_i_i_i_i_52_c_compstr1498_b;
    logic [16:0] i_add_i_i_i_i_i_i_52_c_compstr1498_o;
    wire [16:0] i_add_i_i_i_i_i_i_52_c_compstr1498_q;
    wire [16:0] i_add_i_i_i_i_i_i_53_c_compstr1526_a;
    wire [16:0] i_add_i_i_i_i_i_i_53_c_compstr1526_b;
    logic [16:0] i_add_i_i_i_i_i_i_53_c_compstr1526_o;
    wire [16:0] i_add_i_i_i_i_i_i_53_c_compstr1526_q;
    wire [16:0] i_add_i_i_i_i_i_i_54_c_compstr1554_a;
    wire [16:0] i_add_i_i_i_i_i_i_54_c_compstr1554_b;
    logic [16:0] i_add_i_i_i_i_i_i_54_c_compstr1554_o;
    wire [16:0] i_add_i_i_i_i_i_i_54_c_compstr1554_q;
    wire [16:0] i_add_i_i_i_i_i_i_55_c_compstr1582_a;
    wire [16:0] i_add_i_i_i_i_i_i_55_c_compstr1582_b;
    logic [16:0] i_add_i_i_i_i_i_i_55_c_compstr1582_o;
    wire [16:0] i_add_i_i_i_i_i_i_55_c_compstr1582_q;
    wire [16:0] i_add_i_i_i_i_i_i_56_c_compstr1610_a;
    wire [16:0] i_add_i_i_i_i_i_i_56_c_compstr1610_b;
    logic [16:0] i_add_i_i_i_i_i_i_56_c_compstr1610_o;
    wire [16:0] i_add_i_i_i_i_i_i_56_c_compstr1610_q;
    wire [16:0] i_add_i_i_i_i_i_i_57_c_compstr1638_a;
    wire [16:0] i_add_i_i_i_i_i_i_57_c_compstr1638_b;
    logic [16:0] i_add_i_i_i_i_i_i_57_c_compstr1638_o;
    wire [16:0] i_add_i_i_i_i_i_i_57_c_compstr1638_q;
    wire [16:0] i_add_i_i_i_i_i_i_58_c_compstr1666_a;
    wire [16:0] i_add_i_i_i_i_i_i_58_c_compstr1666_b;
    logic [16:0] i_add_i_i_i_i_i_i_58_c_compstr1666_o;
    wire [16:0] i_add_i_i_i_i_i_i_58_c_compstr1666_q;
    wire [16:0] i_add_i_i_i_i_i_i_59_c_compstr1694_a;
    wire [16:0] i_add_i_i_i_i_i_i_59_c_compstr1694_b;
    logic [16:0] i_add_i_i_i_i_i_i_59_c_compstr1694_o;
    wire [16:0] i_add_i_i_i_i_i_i_59_c_compstr1694_q;
    wire [16:0] i_add_i_i_i_i_i_i_5_c_compstr182_a;
    wire [16:0] i_add_i_i_i_i_i_i_5_c_compstr182_b;
    logic [16:0] i_add_i_i_i_i_i_i_5_c_compstr182_o;
    wire [16:0] i_add_i_i_i_i_i_i_5_c_compstr182_q;
    wire [16:0] i_add_i_i_i_i_i_i_60_c_compstr1722_a;
    wire [16:0] i_add_i_i_i_i_i_i_60_c_compstr1722_b;
    logic [16:0] i_add_i_i_i_i_i_i_60_c_compstr1722_o;
    wire [16:0] i_add_i_i_i_i_i_i_60_c_compstr1722_q;
    wire [16:0] i_add_i_i_i_i_i_i_61_c_compstr1750_a;
    wire [16:0] i_add_i_i_i_i_i_i_61_c_compstr1750_b;
    logic [16:0] i_add_i_i_i_i_i_i_61_c_compstr1750_o;
    wire [16:0] i_add_i_i_i_i_i_i_61_c_compstr1750_q;
    wire [16:0] i_add_i_i_i_i_i_i_62_c_compstr1778_a;
    wire [16:0] i_add_i_i_i_i_i_i_62_c_compstr1778_b;
    logic [16:0] i_add_i_i_i_i_i_i_62_c_compstr1778_o;
    wire [16:0] i_add_i_i_i_i_i_i_62_c_compstr1778_q;
    wire [16:0] i_add_i_i_i_i_i_i_63_c_compstr1806_a;
    wire [16:0] i_add_i_i_i_i_i_i_63_c_compstr1806_b;
    logic [16:0] i_add_i_i_i_i_i_i_63_c_compstr1806_o;
    wire [16:0] i_add_i_i_i_i_i_i_63_c_compstr1806_q;
    wire [16:0] i_add_i_i_i_i_i_i_64_c_compstr1834_a;
    wire [16:0] i_add_i_i_i_i_i_i_64_c_compstr1834_b;
    logic [16:0] i_add_i_i_i_i_i_i_64_c_compstr1834_o;
    wire [16:0] i_add_i_i_i_i_i_i_64_c_compstr1834_q;
    wire [16:0] i_add_i_i_i_i_i_i_65_c_compstr1862_a;
    wire [16:0] i_add_i_i_i_i_i_i_65_c_compstr1862_b;
    logic [16:0] i_add_i_i_i_i_i_i_65_c_compstr1862_o;
    wire [16:0] i_add_i_i_i_i_i_i_65_c_compstr1862_q;
    wire [16:0] i_add_i_i_i_i_i_i_66_c_compstr1890_a;
    wire [16:0] i_add_i_i_i_i_i_i_66_c_compstr1890_b;
    logic [16:0] i_add_i_i_i_i_i_i_66_c_compstr1890_o;
    wire [16:0] i_add_i_i_i_i_i_i_66_c_compstr1890_q;
    wire [16:0] i_add_i_i_i_i_i_i_67_c_compstr1918_a;
    wire [16:0] i_add_i_i_i_i_i_i_67_c_compstr1918_b;
    logic [16:0] i_add_i_i_i_i_i_i_67_c_compstr1918_o;
    wire [16:0] i_add_i_i_i_i_i_i_67_c_compstr1918_q;
    wire [16:0] i_add_i_i_i_i_i_i_68_c_compstr1946_a;
    wire [16:0] i_add_i_i_i_i_i_i_68_c_compstr1946_b;
    logic [16:0] i_add_i_i_i_i_i_i_68_c_compstr1946_o;
    wire [16:0] i_add_i_i_i_i_i_i_68_c_compstr1946_q;
    wire [16:0] i_add_i_i_i_i_i_i_69_c_compstr1974_a;
    wire [16:0] i_add_i_i_i_i_i_i_69_c_compstr1974_b;
    logic [16:0] i_add_i_i_i_i_i_i_69_c_compstr1974_o;
    wire [16:0] i_add_i_i_i_i_i_i_69_c_compstr1974_q;
    wire [16:0] i_add_i_i_i_i_i_i_6_c_compstr210_a;
    wire [16:0] i_add_i_i_i_i_i_i_6_c_compstr210_b;
    logic [16:0] i_add_i_i_i_i_i_i_6_c_compstr210_o;
    wire [16:0] i_add_i_i_i_i_i_i_6_c_compstr210_q;
    wire [16:0] i_add_i_i_i_i_i_i_70_c_compstr2002_a;
    wire [16:0] i_add_i_i_i_i_i_i_70_c_compstr2002_b;
    logic [16:0] i_add_i_i_i_i_i_i_70_c_compstr2002_o;
    wire [16:0] i_add_i_i_i_i_i_i_70_c_compstr2002_q;
    wire [16:0] i_add_i_i_i_i_i_i_71_c_compstr2030_a;
    wire [16:0] i_add_i_i_i_i_i_i_71_c_compstr2030_b;
    logic [16:0] i_add_i_i_i_i_i_i_71_c_compstr2030_o;
    wire [16:0] i_add_i_i_i_i_i_i_71_c_compstr2030_q;
    wire [16:0] i_add_i_i_i_i_i_i_72_c_compstr2058_a;
    wire [16:0] i_add_i_i_i_i_i_i_72_c_compstr2058_b;
    logic [16:0] i_add_i_i_i_i_i_i_72_c_compstr2058_o;
    wire [16:0] i_add_i_i_i_i_i_i_72_c_compstr2058_q;
    wire [16:0] i_add_i_i_i_i_i_i_73_c_compstr2086_a;
    wire [16:0] i_add_i_i_i_i_i_i_73_c_compstr2086_b;
    logic [16:0] i_add_i_i_i_i_i_i_73_c_compstr2086_o;
    wire [16:0] i_add_i_i_i_i_i_i_73_c_compstr2086_q;
    wire [16:0] i_add_i_i_i_i_i_i_74_c_compstr2114_a;
    wire [16:0] i_add_i_i_i_i_i_i_74_c_compstr2114_b;
    logic [16:0] i_add_i_i_i_i_i_i_74_c_compstr2114_o;
    wire [16:0] i_add_i_i_i_i_i_i_74_c_compstr2114_q;
    wire [16:0] i_add_i_i_i_i_i_i_75_c_compstr2142_a;
    wire [16:0] i_add_i_i_i_i_i_i_75_c_compstr2142_b;
    logic [16:0] i_add_i_i_i_i_i_i_75_c_compstr2142_o;
    wire [16:0] i_add_i_i_i_i_i_i_75_c_compstr2142_q;
    wire [16:0] i_add_i_i_i_i_i_i_76_c_compstr2170_a;
    wire [16:0] i_add_i_i_i_i_i_i_76_c_compstr2170_b;
    logic [16:0] i_add_i_i_i_i_i_i_76_c_compstr2170_o;
    wire [16:0] i_add_i_i_i_i_i_i_76_c_compstr2170_q;
    wire [16:0] i_add_i_i_i_i_i_i_77_c_compstr2198_a;
    wire [16:0] i_add_i_i_i_i_i_i_77_c_compstr2198_b;
    logic [16:0] i_add_i_i_i_i_i_i_77_c_compstr2198_o;
    wire [16:0] i_add_i_i_i_i_i_i_77_c_compstr2198_q;
    wire [16:0] i_add_i_i_i_i_i_i_78_c_compstr2226_a;
    wire [16:0] i_add_i_i_i_i_i_i_78_c_compstr2226_b;
    logic [16:0] i_add_i_i_i_i_i_i_78_c_compstr2226_o;
    wire [16:0] i_add_i_i_i_i_i_i_78_c_compstr2226_q;
    wire [16:0] i_add_i_i_i_i_i_i_79_c_compstr2254_a;
    wire [16:0] i_add_i_i_i_i_i_i_79_c_compstr2254_b;
    logic [16:0] i_add_i_i_i_i_i_i_79_c_compstr2254_o;
    wire [16:0] i_add_i_i_i_i_i_i_79_c_compstr2254_q;
    wire [16:0] i_add_i_i_i_i_i_i_7_c_compstr238_a;
    wire [16:0] i_add_i_i_i_i_i_i_7_c_compstr238_b;
    logic [16:0] i_add_i_i_i_i_i_i_7_c_compstr238_o;
    wire [16:0] i_add_i_i_i_i_i_i_7_c_compstr238_q;
    wire [16:0] i_add_i_i_i_i_i_i_80_c_compstr2282_a;
    wire [16:0] i_add_i_i_i_i_i_i_80_c_compstr2282_b;
    logic [16:0] i_add_i_i_i_i_i_i_80_c_compstr2282_o;
    wire [16:0] i_add_i_i_i_i_i_i_80_c_compstr2282_q;
    wire [16:0] i_add_i_i_i_i_i_i_81_c_compstr2310_a;
    wire [16:0] i_add_i_i_i_i_i_i_81_c_compstr2310_b;
    logic [16:0] i_add_i_i_i_i_i_i_81_c_compstr2310_o;
    wire [16:0] i_add_i_i_i_i_i_i_81_c_compstr2310_q;
    wire [16:0] i_add_i_i_i_i_i_i_82_c_compstr2338_a;
    wire [16:0] i_add_i_i_i_i_i_i_82_c_compstr2338_b;
    logic [16:0] i_add_i_i_i_i_i_i_82_c_compstr2338_o;
    wire [16:0] i_add_i_i_i_i_i_i_82_c_compstr2338_q;
    wire [16:0] i_add_i_i_i_i_i_i_83_c_compstr2366_a;
    wire [16:0] i_add_i_i_i_i_i_i_83_c_compstr2366_b;
    logic [16:0] i_add_i_i_i_i_i_i_83_c_compstr2366_o;
    wire [16:0] i_add_i_i_i_i_i_i_83_c_compstr2366_q;
    wire [16:0] i_add_i_i_i_i_i_i_84_c_compstr2394_a;
    wire [16:0] i_add_i_i_i_i_i_i_84_c_compstr2394_b;
    logic [16:0] i_add_i_i_i_i_i_i_84_c_compstr2394_o;
    wire [16:0] i_add_i_i_i_i_i_i_84_c_compstr2394_q;
    wire [16:0] i_add_i_i_i_i_i_i_85_c_compstr2422_a;
    wire [16:0] i_add_i_i_i_i_i_i_85_c_compstr2422_b;
    logic [16:0] i_add_i_i_i_i_i_i_85_c_compstr2422_o;
    wire [16:0] i_add_i_i_i_i_i_i_85_c_compstr2422_q;
    wire [16:0] i_add_i_i_i_i_i_i_86_c_compstr2450_a;
    wire [16:0] i_add_i_i_i_i_i_i_86_c_compstr2450_b;
    logic [16:0] i_add_i_i_i_i_i_i_86_c_compstr2450_o;
    wire [16:0] i_add_i_i_i_i_i_i_86_c_compstr2450_q;
    wire [16:0] i_add_i_i_i_i_i_i_87_c_compstr2478_a;
    wire [16:0] i_add_i_i_i_i_i_i_87_c_compstr2478_b;
    logic [16:0] i_add_i_i_i_i_i_i_87_c_compstr2478_o;
    wire [16:0] i_add_i_i_i_i_i_i_87_c_compstr2478_q;
    wire [16:0] i_add_i_i_i_i_i_i_88_c_compstr2506_a;
    wire [16:0] i_add_i_i_i_i_i_i_88_c_compstr2506_b;
    logic [16:0] i_add_i_i_i_i_i_i_88_c_compstr2506_o;
    wire [16:0] i_add_i_i_i_i_i_i_88_c_compstr2506_q;
    wire [16:0] i_add_i_i_i_i_i_i_89_c_compstr2534_a;
    wire [16:0] i_add_i_i_i_i_i_i_89_c_compstr2534_b;
    logic [16:0] i_add_i_i_i_i_i_i_89_c_compstr2534_o;
    wire [16:0] i_add_i_i_i_i_i_i_89_c_compstr2534_q;
    wire [16:0] i_add_i_i_i_i_i_i_8_c_compstr266_a;
    wire [16:0] i_add_i_i_i_i_i_i_8_c_compstr266_b;
    logic [16:0] i_add_i_i_i_i_i_i_8_c_compstr266_o;
    wire [16:0] i_add_i_i_i_i_i_i_8_c_compstr266_q;
    wire [16:0] i_add_i_i_i_i_i_i_90_c_compstr2562_a;
    wire [16:0] i_add_i_i_i_i_i_i_90_c_compstr2562_b;
    logic [16:0] i_add_i_i_i_i_i_i_90_c_compstr2562_o;
    wire [16:0] i_add_i_i_i_i_i_i_90_c_compstr2562_q;
    wire [16:0] i_add_i_i_i_i_i_i_91_c_compstr2590_a;
    wire [16:0] i_add_i_i_i_i_i_i_91_c_compstr2590_b;
    logic [16:0] i_add_i_i_i_i_i_i_91_c_compstr2590_o;
    wire [16:0] i_add_i_i_i_i_i_i_91_c_compstr2590_q;
    wire [16:0] i_add_i_i_i_i_i_i_92_c_compstr2618_a;
    wire [16:0] i_add_i_i_i_i_i_i_92_c_compstr2618_b;
    logic [16:0] i_add_i_i_i_i_i_i_92_c_compstr2618_o;
    wire [16:0] i_add_i_i_i_i_i_i_92_c_compstr2618_q;
    wire [16:0] i_add_i_i_i_i_i_i_93_c_compstr2646_a;
    wire [16:0] i_add_i_i_i_i_i_i_93_c_compstr2646_b;
    logic [16:0] i_add_i_i_i_i_i_i_93_c_compstr2646_o;
    wire [16:0] i_add_i_i_i_i_i_i_93_c_compstr2646_q;
    wire [16:0] i_add_i_i_i_i_i_i_94_c_compstr2674_a;
    wire [16:0] i_add_i_i_i_i_i_i_94_c_compstr2674_b;
    logic [16:0] i_add_i_i_i_i_i_i_94_c_compstr2674_o;
    wire [16:0] i_add_i_i_i_i_i_i_94_c_compstr2674_q;
    wire [16:0] i_add_i_i_i_i_i_i_95_c_compstr2702_a;
    wire [16:0] i_add_i_i_i_i_i_i_95_c_compstr2702_b;
    logic [16:0] i_add_i_i_i_i_i_i_95_c_compstr2702_o;
    wire [16:0] i_add_i_i_i_i_i_i_95_c_compstr2702_q;
    wire [16:0] i_add_i_i_i_i_i_i_96_c_compstr2730_a;
    wire [16:0] i_add_i_i_i_i_i_i_96_c_compstr2730_b;
    logic [16:0] i_add_i_i_i_i_i_i_96_c_compstr2730_o;
    wire [16:0] i_add_i_i_i_i_i_i_96_c_compstr2730_q;
    wire [16:0] i_add_i_i_i_i_i_i_97_c_compstr2758_a;
    wire [16:0] i_add_i_i_i_i_i_i_97_c_compstr2758_b;
    logic [16:0] i_add_i_i_i_i_i_i_97_c_compstr2758_o;
    wire [16:0] i_add_i_i_i_i_i_i_97_c_compstr2758_q;
    wire [16:0] i_add_i_i_i_i_i_i_98_c_compstr2786_a;
    wire [16:0] i_add_i_i_i_i_i_i_98_c_compstr2786_b;
    logic [16:0] i_add_i_i_i_i_i_i_98_c_compstr2786_o;
    wire [16:0] i_add_i_i_i_i_i_i_98_c_compstr2786_q;
    wire [16:0] i_add_i_i_i_i_i_i_99_c_compstr2814_a;
    wire [16:0] i_add_i_i_i_i_i_i_99_c_compstr2814_b;
    logic [16:0] i_add_i_i_i_i_i_i_99_c_compstr2814_o;
    wire [16:0] i_add_i_i_i_i_i_i_99_c_compstr2814_q;
    wire [16:0] i_add_i_i_i_i_i_i_9_c_compstr294_a;
    wire [16:0] i_add_i_i_i_i_i_i_9_c_compstr294_b;
    logic [16:0] i_add_i_i_i_i_i_i_9_c_compstr294_o;
    wire [16:0] i_add_i_i_i_i_i_i_9_c_compstr294_q;
    wire [16:0] i_add_i_i_i_i_i_i_c_compstr42_a;
    wire [16:0] i_add_i_i_i_i_i_i_c_compstr42_b;
    logic [16:0] i_add_i_i_i_i_i_i_c_compstr42_o;
    wire [16:0] i_add_i_i_i_i_i_i_c_compstr42_q;
    wire [0:0] i_c_compstr_b7_current_iter_isspec_c_compstr5_q;
    wire [0:0] i_c_compstr_b7_next_iter_isreal_c_compstr7_q;
    wire [12:0] i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q;
    wire [28:0] i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_101_c_compstr2846_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_101_c_compstr2846_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_102_c_compstr2874_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_102_c_compstr2874_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_103_c_compstr2902_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_103_c_compstr2902_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_104_c_compstr2930_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_104_c_compstr2930_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_105_c_compstr2958_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_105_c_compstr2958_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_106_c_compstr2986_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_106_c_compstr2986_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_107_c_compstr3014_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_107_c_compstr3014_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_108_c_compstr3042_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_108_c_compstr3042_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_109_c_compstr3070_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_109_c_compstr3070_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_10_c_compstr298_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_10_c_compstr298_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_110_c_compstr3098_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_110_c_compstr3098_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_111_c_compstr3126_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_111_c_compstr3126_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_112_c_compstr3154_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_112_c_compstr3154_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_113_c_compstr3182_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_113_c_compstr3182_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_114_c_compstr3210_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_114_c_compstr3210_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_115_c_compstr3238_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_115_c_compstr3238_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_116_c_compstr3266_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_116_c_compstr3266_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_117_c_compstr3294_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_117_c_compstr3294_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_118_c_compstr3322_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_118_c_compstr3322_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_119_c_compstr3350_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_119_c_compstr3350_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_11_c_compstr326_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_11_c_compstr326_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_120_c_compstr3378_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_120_c_compstr3378_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_121_c_compstr3406_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_121_c_compstr3406_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_122_c_compstr3434_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_122_c_compstr3434_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_123_c_compstr3462_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_123_c_compstr3462_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_124_c_compstr3490_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_124_c_compstr3490_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_125_c_compstr3518_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_125_c_compstr3518_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_126_c_compstr3546_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_126_c_compstr3546_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_127_c_compstr3574_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_127_c_compstr3574_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_12_c_compstr354_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_12_c_compstr354_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_13_c_compstr382_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_13_c_compstr382_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_14_c_compstr410_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_14_c_compstr410_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_15_c_compstr438_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_15_c_compstr438_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_16_c_compstr466_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_16_c_compstr466_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_17_c_compstr494_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_17_c_compstr494_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_18_c_compstr522_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_18_c_compstr522_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_19_c_compstr550_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_19_c_compstr550_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_1_c_compstr46_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_1_c_compstr46_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_20_c_compstr578_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_20_c_compstr578_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_21_c_compstr606_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_21_c_compstr606_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_22_c_compstr634_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_22_c_compstr634_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_23_c_compstr662_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_23_c_compstr662_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_24_c_compstr690_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_24_c_compstr690_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_25_c_compstr718_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_25_c_compstr718_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_26_c_compstr746_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_26_c_compstr746_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_27_c_compstr774_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_27_c_compstr774_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_28_c_compstr802_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_28_c_compstr802_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_29_c_compstr830_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_29_c_compstr830_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_2_c_compstr74_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_2_c_compstr74_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_30_c_compstr858_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_30_c_compstr858_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_31_c_compstr886_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_31_c_compstr886_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_32_c_compstr914_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_32_c_compstr914_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_33_c_compstr942_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_33_c_compstr942_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_34_c_compstr970_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_34_c_compstr970_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_35_c_compstr998_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_35_c_compstr998_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_36_c_compstr1026_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_36_c_compstr1026_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_37_c_compstr1054_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_37_c_compstr1054_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_38_c_compstr1082_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_38_c_compstr1082_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_39_c_compstr1110_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_39_c_compstr1110_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_3_c_compstr102_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_3_c_compstr102_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_40_c_compstr1138_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_40_c_compstr1138_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_41_c_compstr1166_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_41_c_compstr1166_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_42_c_compstr1194_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_42_c_compstr1194_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_43_c_compstr1222_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_43_c_compstr1222_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_44_c_compstr1250_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_44_c_compstr1250_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_45_c_compstr1278_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_45_c_compstr1278_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_46_c_compstr1306_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_46_c_compstr1306_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_47_c_compstr1334_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_47_c_compstr1334_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_48_c_compstr1362_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_48_c_compstr1362_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_49_c_compstr1390_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_49_c_compstr1390_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_4_c_compstr130_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_4_c_compstr130_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_50_c_compstr1418_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_50_c_compstr1418_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_51_c_compstr1446_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_51_c_compstr1446_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_52_c_compstr1474_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_52_c_compstr1474_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_53_c_compstr1502_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_53_c_compstr1502_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_54_c_compstr1530_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_54_c_compstr1530_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_55_c_compstr1558_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_55_c_compstr1558_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_56_c_compstr1586_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_56_c_compstr1586_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_57_c_compstr1614_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_57_c_compstr1614_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_58_c_compstr1642_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_58_c_compstr1642_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_59_c_compstr1670_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_59_c_compstr1670_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_5_c_compstr158_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_5_c_compstr158_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_60_c_compstr1698_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_60_c_compstr1698_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_61_c_compstr1726_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_61_c_compstr1726_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_62_c_compstr1754_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_62_c_compstr1754_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_63_c_compstr1782_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_63_c_compstr1782_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_64_c_compstr1810_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_64_c_compstr1810_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_65_c_compstr1838_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_65_c_compstr1838_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_66_c_compstr1866_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_66_c_compstr1866_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_67_c_compstr1894_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_67_c_compstr1894_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_68_c_compstr1922_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_68_c_compstr1922_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_69_c_compstr1950_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_69_c_compstr1950_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_6_c_compstr186_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_6_c_compstr186_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_70_c_compstr1978_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_70_c_compstr1978_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_71_c_compstr2006_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_71_c_compstr2006_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_72_c_compstr2034_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_72_c_compstr2034_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_73_c_compstr2062_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_73_c_compstr2062_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_74_c_compstr2090_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_74_c_compstr2090_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_75_c_compstr2118_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_75_c_compstr2118_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_76_c_compstr2146_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_76_c_compstr2146_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_77_c_compstr2174_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_77_c_compstr2174_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_78_c_compstr2202_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_78_c_compstr2202_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_79_c_compstr2230_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_79_c_compstr2230_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_7_c_compstr214_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_7_c_compstr214_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_80_c_compstr2258_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_80_c_compstr2258_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_81_c_compstr2286_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_81_c_compstr2286_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_82_c_compstr2314_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_82_c_compstr2314_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_83_c_compstr2342_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_83_c_compstr2342_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_84_c_compstr2370_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_84_c_compstr2370_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_85_c_compstr2398_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_85_c_compstr2398_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_86_c_compstr2426_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_86_c_compstr2426_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_87_c_compstr2454_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_87_c_compstr2454_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_88_c_compstr2482_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_88_c_compstr2482_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_89_c_compstr2510_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_89_c_compstr2510_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_8_c_compstr242_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_8_c_compstr242_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_90_c_compstr2538_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_90_c_compstr2538_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_91_c_compstr2566_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_91_c_compstr2566_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_92_c_compstr2594_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_92_c_compstr2594_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_93_c_compstr2622_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_93_c_compstr2622_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_94_c_compstr2650_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_94_c_compstr2650_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_95_c_compstr2678_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_95_c_compstr2678_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_96_c_compstr2706_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_96_c_compstr2706_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_97_c_compstr2734_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_97_c_compstr2734_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_98_c_compstr2762_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_98_c_compstr2762_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_99_c_compstr2790_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_99_c_compstr2790_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i277_9_c_compstr270_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i277_9_c_compstr270_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_100_c_compstr2834_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_100_c_compstr2834_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_101_c_compstr2862_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_101_c_compstr2862_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_102_c_compstr2890_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_102_c_compstr2890_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_103_c_compstr2918_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_103_c_compstr2918_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_104_c_compstr2946_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_104_c_compstr2946_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_105_c_compstr2974_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_105_c_compstr2974_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_106_c_compstr3002_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_106_c_compstr3002_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_107_c_compstr3030_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_107_c_compstr3030_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_108_c_compstr3058_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_108_c_compstr3058_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_109_c_compstr3086_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_109_c_compstr3086_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_10_c_compstr314_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_10_c_compstr314_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_110_c_compstr3114_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_110_c_compstr3114_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_111_c_compstr3142_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_111_c_compstr3142_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_112_c_compstr3170_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_112_c_compstr3170_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_113_c_compstr3198_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_113_c_compstr3198_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_114_c_compstr3226_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_114_c_compstr3226_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_115_c_compstr3254_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_115_c_compstr3254_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_116_c_compstr3282_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_116_c_compstr3282_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_117_c_compstr3310_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_117_c_compstr3310_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_118_c_compstr3338_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_118_c_compstr3338_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_119_c_compstr3366_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_119_c_compstr3366_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_11_c_compstr342_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_11_c_compstr342_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_120_c_compstr3394_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_120_c_compstr3394_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_121_c_compstr3422_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_121_c_compstr3422_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_122_c_compstr3450_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_122_c_compstr3450_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_123_c_compstr3478_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_123_c_compstr3478_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_124_c_compstr3506_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_124_c_compstr3506_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_125_c_compstr3534_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_125_c_compstr3534_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_126_c_compstr3562_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_126_c_compstr3562_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_127_c_compstr3590_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_127_c_compstr3590_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_12_c_compstr370_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_12_c_compstr370_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_13_c_compstr398_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_13_c_compstr398_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_14_c_compstr426_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_14_c_compstr426_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_15_c_compstr454_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_15_c_compstr454_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_16_c_compstr482_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_16_c_compstr482_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_17_c_compstr510_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_17_c_compstr510_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_18_c_compstr538_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_18_c_compstr538_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_19_c_compstr566_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_19_c_compstr566_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_1_c_compstr62_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_1_c_compstr62_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_20_c_compstr594_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_20_c_compstr594_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_21_c_compstr622_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_21_c_compstr622_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_22_c_compstr650_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_22_c_compstr650_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_23_c_compstr678_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_23_c_compstr678_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_24_c_compstr706_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_24_c_compstr706_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_25_c_compstr734_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_25_c_compstr734_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_26_c_compstr762_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_26_c_compstr762_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_27_c_compstr790_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_27_c_compstr790_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_28_c_compstr818_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_28_c_compstr818_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_29_c_compstr846_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_29_c_compstr846_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_2_c_compstr90_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_2_c_compstr90_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_30_c_compstr874_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_30_c_compstr874_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_31_c_compstr902_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_31_c_compstr902_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_32_c_compstr930_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_32_c_compstr930_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_33_c_compstr958_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_33_c_compstr958_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_34_c_compstr986_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_34_c_compstr986_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_35_c_compstr1014_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_35_c_compstr1014_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_36_c_compstr1042_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_36_c_compstr1042_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_37_c_compstr1070_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_37_c_compstr1070_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_38_c_compstr1098_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_38_c_compstr1098_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_39_c_compstr1126_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_39_c_compstr1126_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_3_c_compstr118_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_3_c_compstr118_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_40_c_compstr1154_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_40_c_compstr1154_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_41_c_compstr1182_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_41_c_compstr1182_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_42_c_compstr1210_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_42_c_compstr1210_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_43_c_compstr1238_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_43_c_compstr1238_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_44_c_compstr1266_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_44_c_compstr1266_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_45_c_compstr1294_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_45_c_compstr1294_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_46_c_compstr1322_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_46_c_compstr1322_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_47_c_compstr1350_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_47_c_compstr1350_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_48_c_compstr1378_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_48_c_compstr1378_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_49_c_compstr1406_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_49_c_compstr1406_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_4_c_compstr146_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_4_c_compstr146_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_50_c_compstr1434_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_50_c_compstr1434_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_51_c_compstr1462_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_51_c_compstr1462_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_52_c_compstr1490_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_52_c_compstr1490_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_53_c_compstr1518_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_53_c_compstr1518_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_54_c_compstr1546_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_54_c_compstr1546_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_55_c_compstr1574_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_55_c_compstr1574_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_56_c_compstr1602_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_56_c_compstr1602_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_57_c_compstr1630_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_57_c_compstr1630_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_58_c_compstr1658_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_58_c_compstr1658_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_59_c_compstr1686_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_59_c_compstr1686_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_5_c_compstr174_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_5_c_compstr174_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_60_c_compstr1714_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_60_c_compstr1714_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_61_c_compstr1742_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_61_c_compstr1742_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_62_c_compstr1770_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_62_c_compstr1770_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_63_c_compstr1798_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_63_c_compstr1798_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_64_c_compstr1826_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_64_c_compstr1826_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_65_c_compstr1854_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_65_c_compstr1854_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_66_c_compstr1882_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_66_c_compstr1882_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_67_c_compstr1910_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_67_c_compstr1910_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_68_c_compstr1938_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_68_c_compstr1938_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_69_c_compstr1966_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_69_c_compstr1966_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_6_c_compstr202_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_6_c_compstr202_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_70_c_compstr1994_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_70_c_compstr1994_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_71_c_compstr2022_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_71_c_compstr2022_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_72_c_compstr2050_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_72_c_compstr2050_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_73_c_compstr2078_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_73_c_compstr2078_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_74_c_compstr2106_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_74_c_compstr2106_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_75_c_compstr2134_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_75_c_compstr2134_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_76_c_compstr2162_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_76_c_compstr2162_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_77_c_compstr2190_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_77_c_compstr2190_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_78_c_compstr2218_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_78_c_compstr2218_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_79_c_compstr2246_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_79_c_compstr2246_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_7_c_compstr230_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_7_c_compstr230_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_80_c_compstr2274_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_80_c_compstr2274_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_81_c_compstr2302_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_81_c_compstr2302_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_82_c_compstr2330_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_82_c_compstr2330_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_83_c_compstr2358_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_83_c_compstr2358_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_84_c_compstr2386_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_84_c_compstr2386_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_85_c_compstr2414_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_85_c_compstr2414_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_86_c_compstr2442_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_86_c_compstr2442_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_87_c_compstr2470_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_87_c_compstr2470_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_88_c_compstr2498_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_88_c_compstr2498_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_89_c_compstr2526_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_89_c_compstr2526_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_8_c_compstr258_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_8_c_compstr258_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_90_c_compstr2554_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_90_c_compstr2554_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_91_c_compstr2582_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_91_c_compstr2582_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_92_c_compstr2610_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_92_c_compstr2610_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_93_c_compstr2638_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_93_c_compstr2638_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_94_c_compstr2666_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_94_c_compstr2666_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_95_c_compstr2694_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_95_c_compstr2694_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_96_c_compstr2722_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_96_c_compstr2722_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_97_c_compstr2750_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_97_c_compstr2750_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_98_c_compstr2778_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_98_c_compstr2778_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_99_c_compstr2806_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_99_c_compstr2806_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i279_9_c_compstr286_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i279_9_c_compstr286_vt_select_15_b;
    wire [5:0] i_fpga_indvars_iv_next14_c_compstr3611_a;
    wire [5:0] i_fpga_indvars_iv_next14_c_compstr3611_b;
    logic [5:0] i_fpga_indvars_iv_next14_c_compstr3611_o;
    wire [5:0] i_fpga_indvars_iv_next14_c_compstr3611_q;
    wire [63:0] i_idxprom36_c_compstr10_vt_join_q;
    wire [31:0] i_idxprom36_c_compstr10_vt_select_31_b;
    wire [32:0] i_inc44_c_compstr3604_a;
    wire [32:0] i_inc44_c_compstr3604_b;
    logic [32:0] i_inc44_c_compstr3604_o;
    wire [32:0] i_inc44_c_compstr3604_q;
    wire [0:0] i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out;
    wire [0:0] i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_q;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_c_compstr6_out_data_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_c_compstr6_out_exiting_valid_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_c_compstr6_out_not_exitcond_stall_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_c_compstr6_out_pipeline_dummy_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_c_compstr6_out_pipeline_forked_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_c_compstr6_out_pipeline_valid_out;
    wire [0:0] i_llvm_fpga_push_i1_notexitcond_c_compstr3610_out_feedback_out_2;
    wire [0:0] i_llvm_fpga_push_i1_notexitcond_c_compstr3610_out_feedback_valid_out_2;
    wire [63:0] i_memcoalesce_bitcast_c_compstr_fpgaunique_533_c_compstr15_vt_join_q;
    wire [54:0] i_memcoalesce_bitcast_c_compstr_fpgaunique_533_c_compstr15_vt_select_63_b;
    wire [0:0] i_notcmp_c_compstr3609_q;
    wire [28:0] i_shl_i_i_i_i_i77_i_100_c_compstr2819_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_100_c_compstr2819_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_101_c_compstr2847_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_101_c_compstr2847_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_102_c_compstr2875_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_102_c_compstr2875_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_103_c_compstr2903_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_103_c_compstr2903_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_104_c_compstr2931_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_104_c_compstr2931_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_105_c_compstr2959_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_105_c_compstr2959_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_106_c_compstr2987_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_106_c_compstr2987_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_107_c_compstr3015_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_107_c_compstr3015_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_108_c_compstr3043_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_108_c_compstr3043_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_109_c_compstr3071_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_109_c_compstr3071_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_10_c_compstr299_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_10_c_compstr299_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_110_c_compstr3099_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_110_c_compstr3099_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_111_c_compstr3127_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_111_c_compstr3127_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_112_c_compstr3155_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_112_c_compstr3155_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_113_c_compstr3183_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_113_c_compstr3183_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_114_c_compstr3211_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_114_c_compstr3211_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_115_c_compstr3239_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_115_c_compstr3239_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_116_c_compstr3267_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_116_c_compstr3267_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_117_c_compstr3295_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_117_c_compstr3295_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_118_c_compstr3323_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_118_c_compstr3323_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_119_c_compstr3351_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_119_c_compstr3351_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_11_c_compstr327_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_11_c_compstr327_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_120_c_compstr3379_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_120_c_compstr3379_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_121_c_compstr3407_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_121_c_compstr3407_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_122_c_compstr3435_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_122_c_compstr3435_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_123_c_compstr3463_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_123_c_compstr3463_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_124_c_compstr3491_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_124_c_compstr3491_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_125_c_compstr3519_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_125_c_compstr3519_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_126_c_compstr3547_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_126_c_compstr3547_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_127_c_compstr3575_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_127_c_compstr3575_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_12_c_compstr355_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_12_c_compstr355_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_13_c_compstr383_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_13_c_compstr383_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_14_c_compstr411_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_14_c_compstr411_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_15_c_compstr439_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_15_c_compstr439_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_16_c_compstr467_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_16_c_compstr467_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_17_c_compstr495_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_17_c_compstr495_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_18_c_compstr523_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_18_c_compstr523_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_19_c_compstr551_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_19_c_compstr551_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_1_c_compstr47_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_1_c_compstr47_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_20_c_compstr579_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_20_c_compstr579_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_21_c_compstr607_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_21_c_compstr607_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_22_c_compstr635_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_22_c_compstr635_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_23_c_compstr663_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_23_c_compstr663_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_24_c_compstr691_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_24_c_compstr691_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_25_c_compstr719_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_25_c_compstr719_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_26_c_compstr747_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_26_c_compstr747_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_27_c_compstr775_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_27_c_compstr775_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_28_c_compstr803_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_28_c_compstr803_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_29_c_compstr831_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_29_c_compstr831_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_2_c_compstr75_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_2_c_compstr75_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_30_c_compstr859_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_30_c_compstr859_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_31_c_compstr887_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_31_c_compstr887_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_32_c_compstr915_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_32_c_compstr915_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_33_c_compstr943_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_33_c_compstr943_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_34_c_compstr971_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_34_c_compstr971_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_35_c_compstr999_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_35_c_compstr999_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_36_c_compstr1027_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_36_c_compstr1027_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_37_c_compstr1055_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_37_c_compstr1055_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_38_c_compstr1083_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_38_c_compstr1083_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_39_c_compstr1111_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_39_c_compstr1111_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_3_c_compstr103_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_3_c_compstr103_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_40_c_compstr1139_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_40_c_compstr1139_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_41_c_compstr1167_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_41_c_compstr1167_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_42_c_compstr1195_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_42_c_compstr1195_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_43_c_compstr1223_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_43_c_compstr1223_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_44_c_compstr1251_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_44_c_compstr1251_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_45_c_compstr1279_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_45_c_compstr1279_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_46_c_compstr1307_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_46_c_compstr1307_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_47_c_compstr1335_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_47_c_compstr1335_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_48_c_compstr1363_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_48_c_compstr1363_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_49_c_compstr1391_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_49_c_compstr1391_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_4_c_compstr131_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_4_c_compstr131_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_50_c_compstr1419_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_50_c_compstr1419_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_51_c_compstr1447_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_51_c_compstr1447_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_52_c_compstr1475_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_52_c_compstr1475_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_53_c_compstr1503_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_53_c_compstr1503_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_54_c_compstr1531_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_54_c_compstr1531_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_55_c_compstr1559_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_55_c_compstr1559_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_56_c_compstr1587_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_56_c_compstr1587_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_57_c_compstr1615_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_57_c_compstr1615_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_58_c_compstr1643_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_58_c_compstr1643_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_59_c_compstr1671_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_59_c_compstr1671_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_5_c_compstr159_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_5_c_compstr159_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_60_c_compstr1699_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_60_c_compstr1699_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_61_c_compstr1727_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_61_c_compstr1727_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_62_c_compstr1755_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_62_c_compstr1755_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_63_c_compstr1783_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_63_c_compstr1783_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_64_c_compstr1811_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_64_c_compstr1811_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_65_c_compstr1839_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_65_c_compstr1839_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_66_c_compstr1867_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_66_c_compstr1867_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_67_c_compstr1895_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_67_c_compstr1895_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_68_c_compstr1923_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_68_c_compstr1923_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_69_c_compstr1951_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_69_c_compstr1951_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_6_c_compstr187_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_6_c_compstr187_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_70_c_compstr1979_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_70_c_compstr1979_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_71_c_compstr2007_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_71_c_compstr2007_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_72_c_compstr2035_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_72_c_compstr2035_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_73_c_compstr2063_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_73_c_compstr2063_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_74_c_compstr2091_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_74_c_compstr2091_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_75_c_compstr2119_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_75_c_compstr2119_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_76_c_compstr2147_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_76_c_compstr2147_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_77_c_compstr2175_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_77_c_compstr2175_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_78_c_compstr2203_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_78_c_compstr2203_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_79_c_compstr2231_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_79_c_compstr2231_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_7_c_compstr215_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_7_c_compstr215_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_80_c_compstr2259_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_80_c_compstr2259_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_81_c_compstr2287_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_81_c_compstr2287_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_82_c_compstr2315_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_82_c_compstr2315_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_83_c_compstr2343_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_83_c_compstr2343_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_84_c_compstr2371_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_84_c_compstr2371_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_85_c_compstr2399_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_85_c_compstr2399_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_86_c_compstr2427_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_86_c_compstr2427_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_87_c_compstr2455_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_87_c_compstr2455_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_88_c_compstr2483_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_88_c_compstr2483_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_89_c_compstr2511_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_89_c_compstr2511_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_8_c_compstr243_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_8_c_compstr243_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_90_c_compstr2539_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_90_c_compstr2539_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_91_c_compstr2567_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_91_c_compstr2567_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_92_c_compstr2595_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_92_c_compstr2595_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_93_c_compstr2623_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_93_c_compstr2623_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_94_c_compstr2651_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_94_c_compstr2651_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_95_c_compstr2679_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_95_c_compstr2679_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_96_c_compstr2707_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_96_c_compstr2707_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_97_c_compstr2735_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_97_c_compstr2735_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_98_c_compstr2763_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_98_c_compstr2763_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_99_c_compstr2791_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_99_c_compstr2791_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_9_c_compstr271_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_9_c_compstr271_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_100_c_compstr2835_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_100_c_compstr2835_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_101_c_compstr2863_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_101_c_compstr2863_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_102_c_compstr2891_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_102_c_compstr2891_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_103_c_compstr2919_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_103_c_compstr2919_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_104_c_compstr2947_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_104_c_compstr2947_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_105_c_compstr2975_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_105_c_compstr2975_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_106_c_compstr3003_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_106_c_compstr3003_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_107_c_compstr3031_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_107_c_compstr3031_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_108_c_compstr3059_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_108_c_compstr3059_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_109_c_compstr3087_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_109_c_compstr3087_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_10_c_compstr315_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_10_c_compstr315_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_110_c_compstr3115_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_110_c_compstr3115_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_111_c_compstr3143_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_111_c_compstr3143_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_112_c_compstr3171_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_112_c_compstr3171_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_113_c_compstr3199_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_113_c_compstr3199_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_114_c_compstr3227_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_114_c_compstr3227_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_115_c_compstr3255_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_115_c_compstr3255_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_116_c_compstr3283_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_116_c_compstr3283_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_117_c_compstr3311_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_117_c_compstr3311_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_118_c_compstr3339_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_118_c_compstr3339_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_119_c_compstr3367_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_119_c_compstr3367_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_11_c_compstr343_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_11_c_compstr343_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_120_c_compstr3395_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_120_c_compstr3395_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_121_c_compstr3423_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_121_c_compstr3423_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_122_c_compstr3451_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_122_c_compstr3451_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_123_c_compstr3479_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_123_c_compstr3479_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_124_c_compstr3507_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_124_c_compstr3507_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_125_c_compstr3535_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_125_c_compstr3535_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_126_c_compstr3563_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_126_c_compstr3563_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_127_c_compstr3591_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_127_c_compstr3591_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_12_c_compstr371_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_12_c_compstr371_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_13_c_compstr399_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_13_c_compstr399_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_14_c_compstr427_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_14_c_compstr427_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_15_c_compstr455_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_15_c_compstr455_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_16_c_compstr483_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_16_c_compstr483_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_17_c_compstr511_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_17_c_compstr511_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_18_c_compstr539_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_18_c_compstr539_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_19_c_compstr567_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_19_c_compstr567_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_1_c_compstr63_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_1_c_compstr63_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_20_c_compstr595_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_20_c_compstr595_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_21_c_compstr623_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_21_c_compstr623_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_22_c_compstr651_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_22_c_compstr651_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_23_c_compstr679_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_23_c_compstr679_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_24_c_compstr707_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_24_c_compstr707_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_25_c_compstr735_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_25_c_compstr735_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_26_c_compstr763_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_26_c_compstr763_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_27_c_compstr791_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_27_c_compstr791_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_28_c_compstr819_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_28_c_compstr819_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_29_c_compstr847_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_29_c_compstr847_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_2_c_compstr91_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_2_c_compstr91_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_30_c_compstr875_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_30_c_compstr875_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_31_c_compstr903_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_31_c_compstr903_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_32_c_compstr931_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_32_c_compstr931_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_33_c_compstr959_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_33_c_compstr959_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_34_c_compstr987_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_34_c_compstr987_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_35_c_compstr1015_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_35_c_compstr1015_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_36_c_compstr1043_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_36_c_compstr1043_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_37_c_compstr1071_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_37_c_compstr1071_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_38_c_compstr1099_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_38_c_compstr1099_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_39_c_compstr1127_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_39_c_compstr1127_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_3_c_compstr119_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_3_c_compstr119_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_40_c_compstr1155_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_40_c_compstr1155_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_41_c_compstr1183_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_41_c_compstr1183_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_42_c_compstr1211_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_42_c_compstr1211_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_43_c_compstr1239_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_43_c_compstr1239_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_44_c_compstr1267_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_44_c_compstr1267_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_45_c_compstr1295_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_45_c_compstr1295_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_46_c_compstr1323_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_46_c_compstr1323_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_47_c_compstr1351_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_47_c_compstr1351_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_48_c_compstr1379_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_48_c_compstr1379_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_49_c_compstr1407_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_49_c_compstr1407_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_4_c_compstr147_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_4_c_compstr147_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_50_c_compstr1435_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_50_c_compstr1435_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_51_c_compstr1463_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_51_c_compstr1463_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_52_c_compstr1491_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_52_c_compstr1491_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_53_c_compstr1519_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_53_c_compstr1519_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_54_c_compstr1547_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_54_c_compstr1547_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_55_c_compstr1575_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_55_c_compstr1575_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_56_c_compstr1603_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_56_c_compstr1603_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_57_c_compstr1631_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_57_c_compstr1631_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_58_c_compstr1659_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_58_c_compstr1659_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_59_c_compstr1687_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_59_c_compstr1687_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_5_c_compstr175_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_5_c_compstr175_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_60_c_compstr1715_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_60_c_compstr1715_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_61_c_compstr1743_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_61_c_compstr1743_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_62_c_compstr1771_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_62_c_compstr1771_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_63_c_compstr1799_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_63_c_compstr1799_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_64_c_compstr1827_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_64_c_compstr1827_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_65_c_compstr1855_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_65_c_compstr1855_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_66_c_compstr1883_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_66_c_compstr1883_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_67_c_compstr1911_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_67_c_compstr1911_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_68_c_compstr1939_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_68_c_compstr1939_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_69_c_compstr1967_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_69_c_compstr1967_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_6_c_compstr203_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_6_c_compstr203_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_70_c_compstr1995_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_70_c_compstr1995_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_71_c_compstr2023_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_71_c_compstr2023_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_72_c_compstr2051_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_72_c_compstr2051_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_73_c_compstr2079_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_73_c_compstr2079_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_74_c_compstr2107_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_74_c_compstr2107_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_75_c_compstr2135_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_75_c_compstr2135_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_76_c_compstr2163_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_76_c_compstr2163_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_77_c_compstr2191_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_77_c_compstr2191_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_78_c_compstr2219_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_78_c_compstr2219_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_79_c_compstr2247_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_79_c_compstr2247_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_7_c_compstr231_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_7_c_compstr231_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_80_c_compstr2275_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_80_c_compstr2275_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_81_c_compstr2303_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_81_c_compstr2303_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_82_c_compstr2331_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_82_c_compstr2331_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_83_c_compstr2359_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_83_c_compstr2359_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_84_c_compstr2387_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_84_c_compstr2387_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_85_c_compstr2415_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_85_c_compstr2415_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_86_c_compstr2443_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_86_c_compstr2443_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_87_c_compstr2471_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_87_c_compstr2471_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_88_c_compstr2499_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_88_c_compstr2499_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_89_c_compstr2527_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_89_c_compstr2527_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_8_c_compstr259_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_8_c_compstr259_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_90_c_compstr2555_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_90_c_compstr2555_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_91_c_compstr2583_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_91_c_compstr2583_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_92_c_compstr2611_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_92_c_compstr2611_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_93_c_compstr2639_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_93_c_compstr2639_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_94_c_compstr2667_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_94_c_compstr2667_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_95_c_compstr2695_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_95_c_compstr2695_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_96_c_compstr2723_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_96_c_compstr2723_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_97_c_compstr2751_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_97_c_compstr2751_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_98_c_compstr2779_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_98_c_compstr2779_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_99_c_compstr2807_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_99_c_compstr2807_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_9_c_compstr287_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_9_c_compstr287_vt_select_28_b;
    wire [33:0] i_unnamed_c_compstr1001_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1001_vt_select_20_b;
    wire [11:0] i_unnamed_c_compstr1003_vt_const_33_q;
    wire [33:0] i_unnamed_c_compstr1003_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1003_vt_select_21_b;
    wire [14:0] i_unnamed_c_compstr1005_vt_const_15_q;
    wire [15:0] i_unnamed_c_compstr1005_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1005_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1017_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1017_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1019_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1019_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1021_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1021_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1029_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1029_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1031_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1031_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1033_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1033_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1045_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1045_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1047_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1047_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1049_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1049_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1057_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1057_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1059_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1059_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr105_vt_join_q;
    wire [20:0] i_unnamed_c_compstr105_vt_select_20_b;
    wire [15:0] i_unnamed_c_compstr1061_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1061_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1073_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1073_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1075_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1075_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1077_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1077_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr107_vt_join_q;
    wire [21:0] i_unnamed_c_compstr107_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr1085_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1085_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1087_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1087_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1089_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1089_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr109_vt_join_q;
    wire [0:0] i_unnamed_c_compstr109_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1101_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1101_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1103_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1103_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1105_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1105_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1113_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1113_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1115_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1115_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1117_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1117_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1129_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1129_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1131_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1131_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1133_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1133_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1141_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1141_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1143_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1143_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1145_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1145_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1157_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1157_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1159_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1159_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1161_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1161_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1169_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1169_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1171_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1171_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1173_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1173_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1185_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1185_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1187_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1187_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1189_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1189_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1197_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1197_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1199_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1199_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1201_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1201_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1213_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1213_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1215_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1215_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1217_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1217_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr121_vt_join_q;
    wire [20:0] i_unnamed_c_compstr121_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1225_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1225_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1227_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1227_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1229_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1229_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr123_vt_join_q;
    wire [21:0] i_unnamed_c_compstr123_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr1241_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1241_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1243_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1243_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1245_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1245_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1253_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1253_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1255_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1255_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1257_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1257_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr125_vt_join_q;
    wire [0:0] i_unnamed_c_compstr125_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1269_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1269_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1271_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1271_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1273_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1273_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1281_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1281_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1283_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1283_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1285_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1285_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1297_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1297_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1299_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1299_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1301_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1301_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1309_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1309_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1311_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1311_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1313_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1313_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1325_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1325_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1327_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1327_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1329_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1329_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1337_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1337_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1339_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1339_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr133_vt_join_q;
    wire [20:0] i_unnamed_c_compstr133_vt_select_20_b;
    wire [15:0] i_unnamed_c_compstr1341_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1341_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1353_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1353_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1355_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1355_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1357_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1357_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr135_vt_join_q;
    wire [21:0] i_unnamed_c_compstr135_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr1365_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1365_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1367_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1367_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1369_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1369_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr137_vt_join_q;
    wire [0:0] i_unnamed_c_compstr137_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1381_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1381_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1383_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1383_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1385_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1385_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1393_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1393_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1395_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1395_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1397_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1397_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1409_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1409_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1411_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1411_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1413_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1413_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1421_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1421_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1423_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1423_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1425_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1425_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1437_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1437_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1439_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1439_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1441_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1441_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1449_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1449_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1451_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1451_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1453_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1453_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1465_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1465_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1467_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1467_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1469_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1469_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1477_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1477_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1479_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1479_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1481_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1481_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1493_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1493_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1495_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1495_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1497_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1497_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr149_vt_join_q;
    wire [20:0] i_unnamed_c_compstr149_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1505_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1505_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1507_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1507_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1509_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1509_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr151_vt_join_q;
    wire [21:0] i_unnamed_c_compstr151_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr1521_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1521_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1523_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1523_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1525_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1525_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1533_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1533_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1535_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1535_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1537_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1537_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr153_vt_join_q;
    wire [0:0] i_unnamed_c_compstr153_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1549_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1549_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1551_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1551_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1553_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1553_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1561_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1561_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1563_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1563_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1565_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1565_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1577_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1577_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1579_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1579_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1581_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1581_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1589_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1589_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1591_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1591_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1593_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1593_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1605_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1605_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1607_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1607_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1609_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1609_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1617_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1617_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1619_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1619_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr161_vt_join_q;
    wire [20:0] i_unnamed_c_compstr161_vt_select_20_b;
    wire [15:0] i_unnamed_c_compstr1621_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1621_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1633_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1633_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1635_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1635_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1637_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1637_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr163_vt_join_q;
    wire [21:0] i_unnamed_c_compstr163_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr1645_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1645_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1647_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1647_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1649_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1649_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr165_vt_join_q;
    wire [0:0] i_unnamed_c_compstr165_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1661_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1661_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1663_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1663_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1665_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1665_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1673_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1673_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1675_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1675_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1677_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1677_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1689_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1689_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1691_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1691_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1693_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1693_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1701_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1701_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1703_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1703_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1705_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1705_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1717_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1717_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1719_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1719_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1721_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1721_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1729_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1729_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1731_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1731_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1733_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1733_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1745_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1745_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1747_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1747_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1749_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1749_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1757_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1757_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1759_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1759_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1761_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1761_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1773_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1773_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1775_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1775_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1777_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1777_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr177_vt_join_q;
    wire [20:0] i_unnamed_c_compstr177_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1785_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1785_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1787_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1787_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1789_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1789_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr179_vt_join_q;
    wire [21:0] i_unnamed_c_compstr179_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr1801_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1801_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1803_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1803_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1805_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1805_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1813_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1813_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1815_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1815_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1817_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1817_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr181_vt_join_q;
    wire [0:0] i_unnamed_c_compstr181_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1829_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1829_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1831_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1831_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1833_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1833_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1841_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1841_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1843_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1843_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1845_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1845_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1857_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1857_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1859_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1859_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1861_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1861_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1869_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1869_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1871_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1871_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1873_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1873_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1885_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1885_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1887_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1887_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1889_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1889_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1897_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1897_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1899_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1899_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr189_vt_join_q;
    wire [20:0] i_unnamed_c_compstr189_vt_select_20_b;
    wire [15:0] i_unnamed_c_compstr1901_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1901_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1913_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1913_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1915_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1915_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1917_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1917_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr191_vt_join_q;
    wire [21:0] i_unnamed_c_compstr191_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr1925_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1925_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1927_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1927_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1929_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1929_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr193_vt_join_q;
    wire [0:0] i_unnamed_c_compstr193_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1941_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1941_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1943_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1943_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1945_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1945_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1953_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1953_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1955_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1955_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1957_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1957_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1969_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1969_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1971_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1971_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1973_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1973_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1981_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1981_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1983_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1983_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr1985_vt_join_q;
    wire [0:0] i_unnamed_c_compstr1985_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr1997_vt_join_q;
    wire [20:0] i_unnamed_c_compstr1997_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr1999_vt_join_q;
    wire [21:0] i_unnamed_c_compstr1999_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2001_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2001_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2009_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2009_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2011_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2011_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2013_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2013_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2025_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2025_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2027_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2027_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2029_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2029_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2037_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2037_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2039_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2039_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2041_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2041_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2053_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2053_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2055_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2055_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2057_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2057_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr205_vt_join_q;
    wire [20:0] i_unnamed_c_compstr205_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2065_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2065_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2067_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2067_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2069_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2069_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr207_vt_join_q;
    wire [21:0] i_unnamed_c_compstr207_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr2081_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2081_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2083_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2083_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2085_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2085_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2093_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2093_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2095_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2095_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2097_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2097_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr209_vt_join_q;
    wire [0:0] i_unnamed_c_compstr209_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2109_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2109_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2111_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2111_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2113_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2113_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2121_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2121_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2123_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2123_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2125_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2125_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2137_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2137_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2139_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2139_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2141_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2141_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2149_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2149_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2151_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2151_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2153_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2153_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2165_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2165_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2167_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2167_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2169_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2169_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2177_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2177_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2179_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2179_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr217_vt_join_q;
    wire [20:0] i_unnamed_c_compstr217_vt_select_20_b;
    wire [15:0] i_unnamed_c_compstr2181_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2181_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2193_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2193_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2195_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2195_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2197_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2197_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr219_vt_join_q;
    wire [21:0] i_unnamed_c_compstr219_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr2205_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2205_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2207_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2207_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2209_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2209_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr221_vt_join_q;
    wire [0:0] i_unnamed_c_compstr221_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2221_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2221_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2223_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2223_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2225_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2225_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2233_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2233_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2235_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2235_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2237_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2237_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2249_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2249_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2251_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2251_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2253_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2253_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2261_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2261_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2263_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2263_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2265_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2265_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2277_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2277_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2279_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2279_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2281_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2281_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2289_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2289_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2291_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2291_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2293_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2293_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2305_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2305_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2307_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2307_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2309_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2309_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2317_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2317_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2319_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2319_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2321_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2321_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2333_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2333_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2335_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2335_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2337_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2337_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr233_vt_join_q;
    wire [20:0] i_unnamed_c_compstr233_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2345_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2345_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2347_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2347_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2349_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2349_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr235_vt_join_q;
    wire [21:0] i_unnamed_c_compstr235_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr2361_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2361_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2363_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2363_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2365_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2365_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2373_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2373_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2375_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2375_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2377_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2377_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr237_vt_join_q;
    wire [0:0] i_unnamed_c_compstr237_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2389_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2389_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2391_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2391_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2393_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2393_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr23_vt_join_q;
    wire [20:0] i_unnamed_c_compstr23_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2401_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2401_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2403_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2403_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2405_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2405_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2417_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2417_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2419_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2419_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2421_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2421_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2429_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2429_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2431_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2431_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2433_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2433_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2445_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2445_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2447_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2447_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2449_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2449_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2457_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2457_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2459_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2459_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr245_vt_join_q;
    wire [20:0] i_unnamed_c_compstr245_vt_select_20_b;
    wire [15:0] i_unnamed_c_compstr2461_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2461_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2473_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2473_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2475_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2475_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2477_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2477_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr247_vt_join_q;
    wire [21:0] i_unnamed_c_compstr247_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr2485_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2485_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2487_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2487_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2489_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2489_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr249_vt_join_q;
    wire [0:0] i_unnamed_c_compstr249_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2501_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2501_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2503_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2503_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2505_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2505_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2513_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2513_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2515_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2515_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2517_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2517_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2529_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2529_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2531_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2531_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2533_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2533_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2541_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2541_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2543_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2543_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2545_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2545_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2557_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2557_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2559_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2559_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2561_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2561_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2569_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2569_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2571_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2571_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2573_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2573_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2585_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2585_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2587_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2587_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2589_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2589_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2597_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2597_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2599_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2599_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr25_vt_join_q;
    wire [21:0] i_unnamed_c_compstr25_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2601_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2601_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2613_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2613_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2615_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2615_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2617_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2617_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr261_vt_join_q;
    wire [20:0] i_unnamed_c_compstr261_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2625_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2625_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2627_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2627_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2629_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2629_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr263_vt_join_q;
    wire [21:0] i_unnamed_c_compstr263_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr2641_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2641_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2643_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2643_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2645_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2645_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2653_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2653_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2655_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2655_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2657_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2657_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr265_vt_join_q;
    wire [0:0] i_unnamed_c_compstr265_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2669_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2669_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2671_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2671_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2673_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2673_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2681_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2681_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2683_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2683_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2685_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2685_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2697_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2697_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2699_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2699_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2701_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2701_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2709_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2709_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2711_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2711_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2713_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2713_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2725_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2725_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2727_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2727_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2729_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2729_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2737_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2737_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2739_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2739_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr273_vt_join_q;
    wire [20:0] i_unnamed_c_compstr273_vt_select_20_b;
    wire [15:0] i_unnamed_c_compstr2741_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2741_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2753_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2753_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2755_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2755_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2757_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2757_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr275_vt_join_q;
    wire [21:0] i_unnamed_c_compstr275_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr2765_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2765_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2767_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2767_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2769_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2769_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr277_vt_join_q;
    wire [0:0] i_unnamed_c_compstr277_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2781_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2781_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2783_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2783_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2785_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2785_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2793_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2793_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2795_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2795_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2797_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2797_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr27_vt_join_q;
    wire [0:0] i_unnamed_c_compstr27_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2809_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2809_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2811_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2811_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2813_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2813_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2821_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2821_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2823_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2823_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2825_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2825_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2837_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2837_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2839_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2839_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2841_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2841_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2849_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2849_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2851_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2851_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2853_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2853_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2865_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2865_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2867_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2867_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2869_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2869_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2877_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2877_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2879_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2879_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2881_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2881_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2893_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2893_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2895_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2895_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2897_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2897_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr289_vt_join_q;
    wire [20:0] i_unnamed_c_compstr289_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2905_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2905_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2907_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2907_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2909_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2909_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr291_vt_join_q;
    wire [21:0] i_unnamed_c_compstr291_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr2921_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2921_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2923_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2923_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2925_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2925_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2933_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2933_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2935_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2935_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2937_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2937_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr293_vt_join_q;
    wire [0:0] i_unnamed_c_compstr293_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2949_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2949_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2951_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2951_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2953_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2953_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2961_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2961_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2963_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2963_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2965_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2965_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2977_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2977_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2979_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2979_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2981_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2981_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr2989_vt_join_q;
    wire [20:0] i_unnamed_c_compstr2989_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr2991_vt_join_q;
    wire [21:0] i_unnamed_c_compstr2991_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr2993_vt_join_q;
    wire [0:0] i_unnamed_c_compstr2993_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3005_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3005_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3007_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3007_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3009_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3009_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3017_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3017_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3019_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3019_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr301_vt_join_q;
    wire [20:0] i_unnamed_c_compstr301_vt_select_20_b;
    wire [15:0] i_unnamed_c_compstr3021_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3021_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3033_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3033_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3035_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3035_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3037_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3037_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr303_vt_join_q;
    wire [21:0] i_unnamed_c_compstr303_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr3045_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3045_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3047_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3047_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3049_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3049_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr305_vt_join_q;
    wire [0:0] i_unnamed_c_compstr305_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3061_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3061_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3063_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3063_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3065_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3065_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3073_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3073_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3075_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3075_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3077_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3077_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3089_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3089_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3091_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3091_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3093_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3093_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3101_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3101_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3103_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3103_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3105_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3105_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3117_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3117_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3119_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3119_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3121_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3121_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3129_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3129_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3131_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3131_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3133_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3133_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3145_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3145_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3147_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3147_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3149_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3149_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3157_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3157_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3159_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3159_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3161_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3161_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3173_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3173_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3175_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3175_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3177_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3177_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr317_vt_join_q;
    wire [20:0] i_unnamed_c_compstr317_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3185_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3185_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3187_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3187_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3189_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3189_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr319_vt_join_q;
    wire [21:0] i_unnamed_c_compstr319_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr3201_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3201_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3203_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3203_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3205_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3205_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3213_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3213_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3215_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3215_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3217_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3217_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr321_vt_join_q;
    wire [0:0] i_unnamed_c_compstr321_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3229_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3229_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3231_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3231_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3233_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3233_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3241_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3241_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3243_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3243_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3245_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3245_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3257_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3257_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3259_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3259_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3261_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3261_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3269_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3269_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3271_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3271_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3273_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3273_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3285_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3285_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3287_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3287_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3289_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3289_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3297_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3297_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3299_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3299_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr329_vt_join_q;
    wire [20:0] i_unnamed_c_compstr329_vt_select_20_b;
    wire [15:0] i_unnamed_c_compstr3301_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3301_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3313_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3313_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3315_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3315_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3317_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3317_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr331_vt_join_q;
    wire [21:0] i_unnamed_c_compstr331_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr3325_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3325_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3327_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3327_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3329_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3329_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr333_vt_join_q;
    wire [0:0] i_unnamed_c_compstr333_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3341_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3341_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3343_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3343_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3345_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3345_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3353_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3353_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3355_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3355_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3357_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3357_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3369_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3369_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3371_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3371_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3373_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3373_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3381_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3381_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3383_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3383_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3385_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3385_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3397_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3397_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3399_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3399_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3401_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3401_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3409_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3409_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3411_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3411_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3413_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3413_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3425_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3425_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3427_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3427_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3429_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3429_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3437_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3437_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3439_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3439_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3441_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3441_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3453_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3453_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3455_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3455_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3457_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3457_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr345_vt_join_q;
    wire [20:0] i_unnamed_c_compstr345_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3465_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3465_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3467_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3467_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3469_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3469_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr347_vt_join_q;
    wire [21:0] i_unnamed_c_compstr347_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr3481_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3481_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3483_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3483_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3485_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3485_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3493_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3493_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3495_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3495_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3497_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3497_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr349_vt_join_q;
    wire [0:0] i_unnamed_c_compstr349_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3509_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3509_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3511_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3511_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3513_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3513_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3521_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3521_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3523_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3523_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3525_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3525_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3537_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3537_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3539_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3539_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3541_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3541_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3549_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3549_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3551_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3551_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3553_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3553_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3565_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3565_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3567_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3567_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3569_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3569_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3577_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3577_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3579_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3579_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr357_vt_join_q;
    wire [20:0] i_unnamed_c_compstr357_vt_select_20_b;
    wire [15:0] i_unnamed_c_compstr3581_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3581_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr3593_vt_join_q;
    wire [20:0] i_unnamed_c_compstr3593_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr3595_vt_join_q;
    wire [21:0] i_unnamed_c_compstr3595_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr3597_vt_join_q;
    wire [0:0] i_unnamed_c_compstr3597_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr359_vt_join_q;
    wire [21:0] i_unnamed_c_compstr359_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr361_vt_join_q;
    wire [0:0] i_unnamed_c_compstr361_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr373_vt_join_q;
    wire [20:0] i_unnamed_c_compstr373_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr375_vt_join_q;
    wire [21:0] i_unnamed_c_compstr375_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr377_vt_join_q;
    wire [0:0] i_unnamed_c_compstr377_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr37_vt_join_q;
    wire [20:0] i_unnamed_c_compstr37_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr385_vt_join_q;
    wire [20:0] i_unnamed_c_compstr385_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr387_vt_join_q;
    wire [21:0] i_unnamed_c_compstr387_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr389_vt_join_q;
    wire [0:0] i_unnamed_c_compstr389_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr39_vt_join_q;
    wire [21:0] i_unnamed_c_compstr39_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr401_vt_join_q;
    wire [20:0] i_unnamed_c_compstr401_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr403_vt_join_q;
    wire [21:0] i_unnamed_c_compstr403_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr405_vt_join_q;
    wire [0:0] i_unnamed_c_compstr405_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr413_vt_join_q;
    wire [20:0] i_unnamed_c_compstr413_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr415_vt_join_q;
    wire [21:0] i_unnamed_c_compstr415_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr417_vt_join_q;
    wire [0:0] i_unnamed_c_compstr417_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr41_vt_join_q;
    wire [0:0] i_unnamed_c_compstr41_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr429_vt_join_q;
    wire [20:0] i_unnamed_c_compstr429_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr431_vt_join_q;
    wire [21:0] i_unnamed_c_compstr431_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr433_vt_join_q;
    wire [0:0] i_unnamed_c_compstr433_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr441_vt_join_q;
    wire [20:0] i_unnamed_c_compstr441_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr443_vt_join_q;
    wire [21:0] i_unnamed_c_compstr443_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr445_vt_join_q;
    wire [0:0] i_unnamed_c_compstr445_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr457_vt_join_q;
    wire [20:0] i_unnamed_c_compstr457_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr459_vt_join_q;
    wire [21:0] i_unnamed_c_compstr459_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr461_vt_join_q;
    wire [0:0] i_unnamed_c_compstr461_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr469_vt_join_q;
    wire [20:0] i_unnamed_c_compstr469_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr471_vt_join_q;
    wire [21:0] i_unnamed_c_compstr471_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr473_vt_join_q;
    wire [0:0] i_unnamed_c_compstr473_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr485_vt_join_q;
    wire [20:0] i_unnamed_c_compstr485_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr487_vt_join_q;
    wire [21:0] i_unnamed_c_compstr487_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr489_vt_join_q;
    wire [0:0] i_unnamed_c_compstr489_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr497_vt_join_q;
    wire [20:0] i_unnamed_c_compstr497_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr499_vt_join_q;
    wire [21:0] i_unnamed_c_compstr499_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr49_vt_join_q;
    wire [20:0] i_unnamed_c_compstr49_vt_select_20_b;
    wire [15:0] i_unnamed_c_compstr501_vt_join_q;
    wire [0:0] i_unnamed_c_compstr501_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr513_vt_join_q;
    wire [20:0] i_unnamed_c_compstr513_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr515_vt_join_q;
    wire [21:0] i_unnamed_c_compstr515_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr517_vt_join_q;
    wire [0:0] i_unnamed_c_compstr517_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr51_vt_join_q;
    wire [21:0] i_unnamed_c_compstr51_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr525_vt_join_q;
    wire [20:0] i_unnamed_c_compstr525_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr527_vt_join_q;
    wire [21:0] i_unnamed_c_compstr527_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr529_vt_join_q;
    wire [0:0] i_unnamed_c_compstr529_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr53_vt_join_q;
    wire [0:0] i_unnamed_c_compstr53_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr541_vt_join_q;
    wire [20:0] i_unnamed_c_compstr541_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr543_vt_join_q;
    wire [21:0] i_unnamed_c_compstr543_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr545_vt_join_q;
    wire [0:0] i_unnamed_c_compstr545_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr553_vt_join_q;
    wire [20:0] i_unnamed_c_compstr553_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr555_vt_join_q;
    wire [21:0] i_unnamed_c_compstr555_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr557_vt_join_q;
    wire [0:0] i_unnamed_c_compstr557_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr569_vt_join_q;
    wire [20:0] i_unnamed_c_compstr569_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr571_vt_join_q;
    wire [21:0] i_unnamed_c_compstr571_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr573_vt_join_q;
    wire [0:0] i_unnamed_c_compstr573_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr581_vt_join_q;
    wire [20:0] i_unnamed_c_compstr581_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr583_vt_join_q;
    wire [21:0] i_unnamed_c_compstr583_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr585_vt_join_q;
    wire [0:0] i_unnamed_c_compstr585_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr597_vt_join_q;
    wire [20:0] i_unnamed_c_compstr597_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr599_vt_join_q;
    wire [21:0] i_unnamed_c_compstr599_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr601_vt_join_q;
    wire [0:0] i_unnamed_c_compstr601_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr609_vt_join_q;
    wire [20:0] i_unnamed_c_compstr609_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr611_vt_join_q;
    wire [21:0] i_unnamed_c_compstr611_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr613_vt_join_q;
    wire [0:0] i_unnamed_c_compstr613_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr625_vt_join_q;
    wire [20:0] i_unnamed_c_compstr625_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr627_vt_join_q;
    wire [21:0] i_unnamed_c_compstr627_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr629_vt_join_q;
    wire [0:0] i_unnamed_c_compstr629_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr637_vt_join_q;
    wire [20:0] i_unnamed_c_compstr637_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr639_vt_join_q;
    wire [21:0] i_unnamed_c_compstr639_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr641_vt_join_q;
    wire [0:0] i_unnamed_c_compstr641_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr653_vt_join_q;
    wire [20:0] i_unnamed_c_compstr653_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr655_vt_join_q;
    wire [21:0] i_unnamed_c_compstr655_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr657_vt_join_q;
    wire [0:0] i_unnamed_c_compstr657_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr65_vt_join_q;
    wire [20:0] i_unnamed_c_compstr65_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr665_vt_join_q;
    wire [20:0] i_unnamed_c_compstr665_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr667_vt_join_q;
    wire [21:0] i_unnamed_c_compstr667_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr669_vt_join_q;
    wire [0:0] i_unnamed_c_compstr669_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr67_vt_join_q;
    wire [21:0] i_unnamed_c_compstr67_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr681_vt_join_q;
    wire [20:0] i_unnamed_c_compstr681_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr683_vt_join_q;
    wire [21:0] i_unnamed_c_compstr683_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr685_vt_join_q;
    wire [0:0] i_unnamed_c_compstr685_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr693_vt_join_q;
    wire [20:0] i_unnamed_c_compstr693_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr695_vt_join_q;
    wire [21:0] i_unnamed_c_compstr695_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr697_vt_join_q;
    wire [0:0] i_unnamed_c_compstr697_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr69_vt_join_q;
    wire [0:0] i_unnamed_c_compstr69_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr709_vt_join_q;
    wire [20:0] i_unnamed_c_compstr709_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr711_vt_join_q;
    wire [21:0] i_unnamed_c_compstr711_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr713_vt_join_q;
    wire [0:0] i_unnamed_c_compstr713_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr721_vt_join_q;
    wire [20:0] i_unnamed_c_compstr721_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr723_vt_join_q;
    wire [21:0] i_unnamed_c_compstr723_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr725_vt_join_q;
    wire [0:0] i_unnamed_c_compstr725_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr737_vt_join_q;
    wire [20:0] i_unnamed_c_compstr737_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr739_vt_join_q;
    wire [21:0] i_unnamed_c_compstr739_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr741_vt_join_q;
    wire [0:0] i_unnamed_c_compstr741_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr749_vt_join_q;
    wire [20:0] i_unnamed_c_compstr749_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr751_vt_join_q;
    wire [21:0] i_unnamed_c_compstr751_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr753_vt_join_q;
    wire [0:0] i_unnamed_c_compstr753_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr765_vt_join_q;
    wire [20:0] i_unnamed_c_compstr765_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr767_vt_join_q;
    wire [21:0] i_unnamed_c_compstr767_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr769_vt_join_q;
    wire [0:0] i_unnamed_c_compstr769_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr777_vt_join_q;
    wire [20:0] i_unnamed_c_compstr777_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr779_vt_join_q;
    wire [21:0] i_unnamed_c_compstr779_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr77_vt_join_q;
    wire [20:0] i_unnamed_c_compstr77_vt_select_20_b;
    wire [15:0] i_unnamed_c_compstr781_vt_join_q;
    wire [0:0] i_unnamed_c_compstr781_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr793_vt_join_q;
    wire [20:0] i_unnamed_c_compstr793_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr795_vt_join_q;
    wire [21:0] i_unnamed_c_compstr795_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr797_vt_join_q;
    wire [0:0] i_unnamed_c_compstr797_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr79_vt_join_q;
    wire [21:0] i_unnamed_c_compstr79_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr805_vt_join_q;
    wire [20:0] i_unnamed_c_compstr805_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr807_vt_join_q;
    wire [21:0] i_unnamed_c_compstr807_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr809_vt_join_q;
    wire [0:0] i_unnamed_c_compstr809_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr81_vt_join_q;
    wire [0:0] i_unnamed_c_compstr81_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr821_vt_join_q;
    wire [20:0] i_unnamed_c_compstr821_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr823_vt_join_q;
    wire [21:0] i_unnamed_c_compstr823_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr825_vt_join_q;
    wire [0:0] i_unnamed_c_compstr825_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr833_vt_join_q;
    wire [20:0] i_unnamed_c_compstr833_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr835_vt_join_q;
    wire [21:0] i_unnamed_c_compstr835_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr837_vt_join_q;
    wire [0:0] i_unnamed_c_compstr837_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr849_vt_join_q;
    wire [20:0] i_unnamed_c_compstr849_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr851_vt_join_q;
    wire [21:0] i_unnamed_c_compstr851_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr853_vt_join_q;
    wire [0:0] i_unnamed_c_compstr853_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr861_vt_join_q;
    wire [20:0] i_unnamed_c_compstr861_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr863_vt_join_q;
    wire [21:0] i_unnamed_c_compstr863_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr865_vt_join_q;
    wire [0:0] i_unnamed_c_compstr865_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr877_vt_join_q;
    wire [20:0] i_unnamed_c_compstr877_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr879_vt_join_q;
    wire [21:0] i_unnamed_c_compstr879_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr881_vt_join_q;
    wire [0:0] i_unnamed_c_compstr881_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr889_vt_join_q;
    wire [20:0] i_unnamed_c_compstr889_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr891_vt_join_q;
    wire [21:0] i_unnamed_c_compstr891_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr893_vt_join_q;
    wire [0:0] i_unnamed_c_compstr893_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr905_vt_join_q;
    wire [20:0] i_unnamed_c_compstr905_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr907_vt_join_q;
    wire [21:0] i_unnamed_c_compstr907_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr909_vt_join_q;
    wire [0:0] i_unnamed_c_compstr909_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr917_vt_join_q;
    wire [20:0] i_unnamed_c_compstr917_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr919_vt_join_q;
    wire [21:0] i_unnamed_c_compstr919_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr921_vt_join_q;
    wire [0:0] i_unnamed_c_compstr921_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr933_vt_join_q;
    wire [20:0] i_unnamed_c_compstr933_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr935_vt_join_q;
    wire [21:0] i_unnamed_c_compstr935_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr937_vt_join_q;
    wire [0:0] i_unnamed_c_compstr937_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr93_vt_join_q;
    wire [20:0] i_unnamed_c_compstr93_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr945_vt_join_q;
    wire [20:0] i_unnamed_c_compstr945_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr947_vt_join_q;
    wire [21:0] i_unnamed_c_compstr947_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr949_vt_join_q;
    wire [0:0] i_unnamed_c_compstr949_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr95_vt_join_q;
    wire [21:0] i_unnamed_c_compstr95_vt_select_21_b;
    wire [33:0] i_unnamed_c_compstr961_vt_join_q;
    wire [20:0] i_unnamed_c_compstr961_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr963_vt_join_q;
    wire [21:0] i_unnamed_c_compstr963_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr965_vt_join_q;
    wire [0:0] i_unnamed_c_compstr965_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr973_vt_join_q;
    wire [20:0] i_unnamed_c_compstr973_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr975_vt_join_q;
    wire [21:0] i_unnamed_c_compstr975_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr977_vt_join_q;
    wire [0:0] i_unnamed_c_compstr977_vt_select_0_b;
    wire [15:0] i_unnamed_c_compstr97_vt_join_q;
    wire [0:0] i_unnamed_c_compstr97_vt_select_0_b;
    wire [33:0] i_unnamed_c_compstr989_vt_join_q;
    wire [20:0] i_unnamed_c_compstr989_vt_select_20_b;
    wire [33:0] i_unnamed_c_compstr991_vt_join_q;
    wire [21:0] i_unnamed_c_compstr991_vt_select_21_b;
    wire [15:0] i_unnamed_c_compstr993_vt_join_q;
    wire [0:0] i_unnamed_c_compstr993_vt_select_0_b;
    wire [63:0] i_value2_i_i157_i3_c_compstr14_vt_join_q;
    wire [54:0] i_value2_i_i157_i3_c_compstr14_vt_select_63_b;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg0_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg2_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg3_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg4_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg6_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg7_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg9_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg10_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg11_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg12_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg13_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid14952_dupName_0_i_unnamed_c_compstr0_shift_x_b;
    wire [3:0] rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q;
    wire [33:0] rightShiftStage0Idx1_uid14954_dupName_0_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid14956_dupName_0_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid14956_dupName_0_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid14957_dupName_0_i_unnamed_c_compstr0_shift_x_b;
    wire [7:0] rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q;
    wire [33:0] rightShiftStage1Idx1_uid14959_dupName_0_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid14961_dupName_0_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid14961_dupName_0_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid14965_dupName_1_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid14967_dupName_1_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid14969_dupName_1_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid14969_dupName_1_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid14970_dupName_1_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid14972_dupName_1_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid14974_dupName_1_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid14974_dupName_1_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid14975_dupName_1_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid14977_dupName_1_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid14979_dupName_1_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid14979_dupName_1_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid14983_dupName_2_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid14985_dupName_2_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid14987_dupName_2_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid14987_dupName_2_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid14988_dupName_2_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid14990_dupName_2_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid14992_dupName_2_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid14992_dupName_2_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid14996_dupName_3_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid14998_dupName_3_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15000_dupName_3_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15000_dupName_3_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15001_dupName_3_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15003_dupName_3_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15005_dupName_3_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15005_dupName_3_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15006_dupName_3_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15008_dupName_3_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15010_dupName_3_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15010_dupName_3_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15014_dupName_4_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15016_dupName_4_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15018_dupName_4_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15018_dupName_4_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15019_dupName_4_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15021_dupName_4_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15023_dupName_4_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15023_dupName_4_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15027_dupName_5_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15029_dupName_5_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15031_dupName_5_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15031_dupName_5_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15032_dupName_5_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15034_dupName_5_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15036_dupName_5_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15036_dupName_5_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15037_dupName_5_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15039_dupName_5_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15041_dupName_5_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15041_dupName_5_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15045_dupName_6_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15047_dupName_6_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15049_dupName_6_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15049_dupName_6_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15050_dupName_6_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15052_dupName_6_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15054_dupName_6_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15054_dupName_6_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15058_dupName_7_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15060_dupName_7_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15062_dupName_7_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15062_dupName_7_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15063_dupName_7_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15065_dupName_7_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15067_dupName_7_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15067_dupName_7_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15068_dupName_7_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15070_dupName_7_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15072_dupName_7_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15072_dupName_7_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15076_dupName_8_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15078_dupName_8_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15080_dupName_8_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15080_dupName_8_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15081_dupName_8_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15083_dupName_8_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15085_dupName_8_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15085_dupName_8_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15089_dupName_9_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15091_dupName_9_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15093_dupName_9_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15093_dupName_9_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15094_dupName_9_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15096_dupName_9_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15098_dupName_9_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15098_dupName_9_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15099_dupName_9_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15101_dupName_9_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15103_dupName_9_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15103_dupName_9_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15107_dupName_10_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15109_dupName_10_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15111_dupName_10_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15111_dupName_10_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15112_dupName_10_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15114_dupName_10_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15116_dupName_10_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15116_dupName_10_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15120_dupName_11_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15122_dupName_11_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15124_dupName_11_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15124_dupName_11_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15125_dupName_11_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15127_dupName_11_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15129_dupName_11_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15129_dupName_11_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15130_dupName_11_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15132_dupName_11_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15134_dupName_11_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15134_dupName_11_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15138_dupName_12_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15140_dupName_12_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15142_dupName_12_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15142_dupName_12_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15143_dupName_12_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15145_dupName_12_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15147_dupName_12_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15147_dupName_12_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15151_dupName_13_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15153_dupName_13_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15155_dupName_13_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15155_dupName_13_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15156_dupName_13_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15158_dupName_13_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15160_dupName_13_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15160_dupName_13_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15161_dupName_13_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15163_dupName_13_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15165_dupName_13_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15165_dupName_13_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15169_dupName_14_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15171_dupName_14_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15173_dupName_14_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15173_dupName_14_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15174_dupName_14_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15176_dupName_14_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15178_dupName_14_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15178_dupName_14_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15182_dupName_15_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15184_dupName_15_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15186_dupName_15_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15186_dupName_15_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15187_dupName_15_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15189_dupName_15_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15191_dupName_15_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15191_dupName_15_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15192_dupName_15_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15194_dupName_15_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15196_dupName_15_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15196_dupName_15_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15200_dupName_16_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15202_dupName_16_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15204_dupName_16_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15204_dupName_16_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15205_dupName_16_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15207_dupName_16_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15209_dupName_16_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15209_dupName_16_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15213_dupName_17_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15215_dupName_17_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15217_dupName_17_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15217_dupName_17_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15218_dupName_17_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15220_dupName_17_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15222_dupName_17_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15222_dupName_17_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15223_dupName_17_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15225_dupName_17_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15227_dupName_17_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15227_dupName_17_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15231_dupName_18_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15233_dupName_18_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15235_dupName_18_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15235_dupName_18_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15236_dupName_18_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15238_dupName_18_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15240_dupName_18_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15240_dupName_18_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15244_dupName_19_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15246_dupName_19_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15248_dupName_19_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15248_dupName_19_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15249_dupName_19_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15251_dupName_19_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15253_dupName_19_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15253_dupName_19_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15254_dupName_19_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15256_dupName_19_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15258_dupName_19_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15258_dupName_19_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15262_dupName_20_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15264_dupName_20_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15266_dupName_20_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15266_dupName_20_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15267_dupName_20_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15269_dupName_20_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15271_dupName_20_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15271_dupName_20_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15275_dupName_21_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15277_dupName_21_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15279_dupName_21_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15279_dupName_21_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15280_dupName_21_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15282_dupName_21_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15284_dupName_21_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15284_dupName_21_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15285_dupName_21_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15287_dupName_21_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15289_dupName_21_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15289_dupName_21_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15293_dupName_22_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15295_dupName_22_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15297_dupName_22_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15297_dupName_22_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15298_dupName_22_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15300_dupName_22_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15302_dupName_22_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15302_dupName_22_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15306_dupName_23_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15308_dupName_23_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15310_dupName_23_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15310_dupName_23_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15311_dupName_23_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15313_dupName_23_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15315_dupName_23_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15315_dupName_23_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15316_dupName_23_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15318_dupName_23_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15320_dupName_23_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15320_dupName_23_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15324_dupName_24_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15326_dupName_24_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15328_dupName_24_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15328_dupName_24_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15329_dupName_24_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15331_dupName_24_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15333_dupName_24_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15333_dupName_24_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15337_dupName_25_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15339_dupName_25_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15341_dupName_25_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15341_dupName_25_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15342_dupName_25_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15344_dupName_25_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15346_dupName_25_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15346_dupName_25_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15347_dupName_25_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15349_dupName_25_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15351_dupName_25_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15351_dupName_25_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15355_dupName_26_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15357_dupName_26_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15359_dupName_26_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15359_dupName_26_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15360_dupName_26_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15362_dupName_26_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15364_dupName_26_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15364_dupName_26_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15368_dupName_27_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15370_dupName_27_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15372_dupName_27_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15372_dupName_27_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15373_dupName_27_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15375_dupName_27_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15377_dupName_27_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15377_dupName_27_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15378_dupName_27_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15380_dupName_27_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15382_dupName_27_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15382_dupName_27_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15386_dupName_28_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15388_dupName_28_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15390_dupName_28_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15390_dupName_28_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15391_dupName_28_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15393_dupName_28_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15395_dupName_28_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15395_dupName_28_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15399_dupName_29_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15401_dupName_29_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15403_dupName_29_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15403_dupName_29_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15404_dupName_29_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15406_dupName_29_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15408_dupName_29_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15408_dupName_29_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15409_dupName_29_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15411_dupName_29_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15413_dupName_29_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15413_dupName_29_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15417_dupName_30_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15419_dupName_30_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15421_dupName_30_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15421_dupName_30_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15422_dupName_30_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15424_dupName_30_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15426_dupName_30_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15426_dupName_30_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15430_dupName_31_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15432_dupName_31_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15434_dupName_31_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15434_dupName_31_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15435_dupName_31_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15437_dupName_31_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15439_dupName_31_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15439_dupName_31_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15440_dupName_31_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15442_dupName_31_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15444_dupName_31_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15444_dupName_31_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15448_dupName_32_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15450_dupName_32_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15452_dupName_32_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15452_dupName_32_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15453_dupName_32_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15455_dupName_32_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15457_dupName_32_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15457_dupName_32_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15461_dupName_33_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15463_dupName_33_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15465_dupName_33_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15465_dupName_33_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15466_dupName_33_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15468_dupName_33_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15470_dupName_33_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15470_dupName_33_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15471_dupName_33_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15473_dupName_33_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15475_dupName_33_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15475_dupName_33_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15479_dupName_34_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15481_dupName_34_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15483_dupName_34_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15483_dupName_34_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15484_dupName_34_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15486_dupName_34_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15488_dupName_34_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15488_dupName_34_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15492_dupName_35_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15494_dupName_35_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15496_dupName_35_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15496_dupName_35_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15497_dupName_35_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15499_dupName_35_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15501_dupName_35_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15501_dupName_35_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15502_dupName_35_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15504_dupName_35_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15506_dupName_35_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15506_dupName_35_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15510_dupName_36_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15512_dupName_36_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15514_dupName_36_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15514_dupName_36_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15515_dupName_36_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15517_dupName_36_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15519_dupName_36_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15519_dupName_36_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15523_dupName_37_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15525_dupName_37_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15527_dupName_37_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15527_dupName_37_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15528_dupName_37_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15530_dupName_37_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15532_dupName_37_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15532_dupName_37_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15533_dupName_37_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15535_dupName_37_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15537_dupName_37_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15537_dupName_37_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15541_dupName_38_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15543_dupName_38_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15545_dupName_38_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15545_dupName_38_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15546_dupName_38_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15548_dupName_38_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15550_dupName_38_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15550_dupName_38_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15554_dupName_39_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15556_dupName_39_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15558_dupName_39_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15558_dupName_39_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15559_dupName_39_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15561_dupName_39_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15563_dupName_39_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15563_dupName_39_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15564_dupName_39_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15566_dupName_39_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15568_dupName_39_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15568_dupName_39_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15572_dupName_40_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15574_dupName_40_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15576_dupName_40_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15576_dupName_40_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15577_dupName_40_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15579_dupName_40_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15581_dupName_40_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15581_dupName_40_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15585_dupName_41_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15587_dupName_41_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15589_dupName_41_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15589_dupName_41_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15590_dupName_41_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15592_dupName_41_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15594_dupName_41_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15594_dupName_41_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15595_dupName_41_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15597_dupName_41_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15599_dupName_41_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15599_dupName_41_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15603_dupName_42_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15605_dupName_42_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15607_dupName_42_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15607_dupName_42_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15608_dupName_42_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15610_dupName_42_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15612_dupName_42_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15612_dupName_42_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15616_dupName_43_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15618_dupName_43_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15620_dupName_43_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15620_dupName_43_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15621_dupName_43_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15623_dupName_43_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15625_dupName_43_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15625_dupName_43_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15626_dupName_43_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15628_dupName_43_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15630_dupName_43_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15630_dupName_43_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15634_dupName_44_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15636_dupName_44_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15638_dupName_44_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15638_dupName_44_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15639_dupName_44_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15641_dupName_44_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15643_dupName_44_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15643_dupName_44_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15647_dupName_45_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15649_dupName_45_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15651_dupName_45_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15651_dupName_45_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15652_dupName_45_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15654_dupName_45_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15656_dupName_45_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15656_dupName_45_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15657_dupName_45_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15659_dupName_45_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15661_dupName_45_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15661_dupName_45_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15665_dupName_46_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15667_dupName_46_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15669_dupName_46_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15669_dupName_46_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15670_dupName_46_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15672_dupName_46_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15674_dupName_46_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15674_dupName_46_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15678_dupName_47_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15680_dupName_47_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15682_dupName_47_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15682_dupName_47_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15683_dupName_47_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15685_dupName_47_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15687_dupName_47_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15687_dupName_47_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15688_dupName_47_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15690_dupName_47_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15692_dupName_47_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15692_dupName_47_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15696_dupName_48_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15698_dupName_48_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15700_dupName_48_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15700_dupName_48_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15701_dupName_48_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15703_dupName_48_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15705_dupName_48_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15705_dupName_48_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15709_dupName_49_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15711_dupName_49_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15713_dupName_49_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15713_dupName_49_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15714_dupName_49_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15716_dupName_49_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15718_dupName_49_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15718_dupName_49_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15719_dupName_49_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15721_dupName_49_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15723_dupName_49_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15723_dupName_49_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15727_dupName_50_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15729_dupName_50_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15731_dupName_50_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15731_dupName_50_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15732_dupName_50_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15734_dupName_50_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15736_dupName_50_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15736_dupName_50_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15740_dupName_51_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15742_dupName_51_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15744_dupName_51_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15744_dupName_51_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15745_dupName_51_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15747_dupName_51_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15749_dupName_51_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15749_dupName_51_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15750_dupName_51_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15752_dupName_51_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15754_dupName_51_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15754_dupName_51_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15758_dupName_52_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15760_dupName_52_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15762_dupName_52_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15762_dupName_52_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15763_dupName_52_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15765_dupName_52_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15767_dupName_52_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15767_dupName_52_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15771_dupName_53_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15773_dupName_53_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15775_dupName_53_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15775_dupName_53_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15776_dupName_53_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15778_dupName_53_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15780_dupName_53_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15780_dupName_53_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15781_dupName_53_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15783_dupName_53_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15785_dupName_53_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15785_dupName_53_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15789_dupName_54_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15791_dupName_54_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15793_dupName_54_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15793_dupName_54_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15794_dupName_54_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15796_dupName_54_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15798_dupName_54_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15798_dupName_54_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15802_dupName_55_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15804_dupName_55_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15806_dupName_55_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15806_dupName_55_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15807_dupName_55_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15809_dupName_55_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15811_dupName_55_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15811_dupName_55_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15812_dupName_55_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15814_dupName_55_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15816_dupName_55_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15816_dupName_55_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15820_dupName_56_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15822_dupName_56_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15824_dupName_56_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15824_dupName_56_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15825_dupName_56_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15827_dupName_56_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15829_dupName_56_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15829_dupName_56_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15833_dupName_57_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15835_dupName_57_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15837_dupName_57_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15837_dupName_57_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15838_dupName_57_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15840_dupName_57_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15842_dupName_57_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15842_dupName_57_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15843_dupName_57_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15845_dupName_57_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15847_dupName_57_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15847_dupName_57_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15851_dupName_58_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15853_dupName_58_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15855_dupName_58_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15855_dupName_58_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15856_dupName_58_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15858_dupName_58_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15860_dupName_58_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15860_dupName_58_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15864_dupName_59_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15866_dupName_59_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15868_dupName_59_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15868_dupName_59_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15869_dupName_59_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15871_dupName_59_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15873_dupName_59_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15873_dupName_59_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15874_dupName_59_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15876_dupName_59_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15878_dupName_59_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15878_dupName_59_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15882_dupName_60_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15884_dupName_60_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15886_dupName_60_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15886_dupName_60_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15887_dupName_60_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15889_dupName_60_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15891_dupName_60_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15891_dupName_60_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15895_dupName_61_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15897_dupName_61_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15899_dupName_61_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15899_dupName_61_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15900_dupName_61_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15902_dupName_61_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15904_dupName_61_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15904_dupName_61_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15905_dupName_61_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15907_dupName_61_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15909_dupName_61_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15909_dupName_61_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15913_dupName_62_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15915_dupName_62_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15917_dupName_62_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15917_dupName_62_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15918_dupName_62_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15920_dupName_62_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15922_dupName_62_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15922_dupName_62_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15926_dupName_63_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15928_dupName_63_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15930_dupName_63_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15930_dupName_63_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15931_dupName_63_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15933_dupName_63_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15935_dupName_63_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15935_dupName_63_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15936_dupName_63_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15938_dupName_63_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15940_dupName_63_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15940_dupName_63_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15944_dupName_64_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15946_dupName_64_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15948_dupName_64_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15948_dupName_64_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15949_dupName_64_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15951_dupName_64_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15953_dupName_64_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15953_dupName_64_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15957_dupName_65_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15959_dupName_65_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15961_dupName_65_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15961_dupName_65_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15962_dupName_65_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15964_dupName_65_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15966_dupName_65_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15966_dupName_65_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15967_dupName_65_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15969_dupName_65_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15971_dupName_65_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15971_dupName_65_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15975_dupName_66_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15977_dupName_66_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15979_dupName_66_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15979_dupName_66_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15980_dupName_66_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15982_dupName_66_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15984_dupName_66_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15984_dupName_66_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15988_dupName_67_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15990_dupName_67_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15992_dupName_67_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15992_dupName_67_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15993_dupName_67_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15995_dupName_67_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15997_dupName_67_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15997_dupName_67_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15998_dupName_67_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16000_dupName_67_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16002_dupName_67_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16002_dupName_67_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16006_dupName_68_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16008_dupName_68_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16010_dupName_68_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16010_dupName_68_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16011_dupName_68_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16013_dupName_68_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16015_dupName_68_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16015_dupName_68_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16019_dupName_69_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16021_dupName_69_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16023_dupName_69_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16023_dupName_69_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16024_dupName_69_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16026_dupName_69_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16028_dupName_69_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16028_dupName_69_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16029_dupName_69_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16031_dupName_69_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16033_dupName_69_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16033_dupName_69_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16037_dupName_70_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16039_dupName_70_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16041_dupName_70_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16041_dupName_70_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16042_dupName_70_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16044_dupName_70_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16046_dupName_70_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16046_dupName_70_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16050_dupName_71_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16052_dupName_71_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16054_dupName_71_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16054_dupName_71_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16055_dupName_71_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16057_dupName_71_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16059_dupName_71_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16059_dupName_71_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16060_dupName_71_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16062_dupName_71_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16064_dupName_71_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16064_dupName_71_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16068_dupName_72_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16070_dupName_72_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16072_dupName_72_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16072_dupName_72_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16073_dupName_72_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16075_dupName_72_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16077_dupName_72_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16077_dupName_72_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16081_dupName_73_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16083_dupName_73_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16085_dupName_73_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16085_dupName_73_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16086_dupName_73_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16088_dupName_73_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16090_dupName_73_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16090_dupName_73_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16091_dupName_73_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16093_dupName_73_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16095_dupName_73_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16095_dupName_73_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16099_dupName_74_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16101_dupName_74_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16103_dupName_74_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16103_dupName_74_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16104_dupName_74_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16106_dupName_74_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16108_dupName_74_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16108_dupName_74_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16112_dupName_75_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16114_dupName_75_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16116_dupName_75_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16116_dupName_75_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16117_dupName_75_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16119_dupName_75_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16121_dupName_75_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16121_dupName_75_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16122_dupName_75_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16124_dupName_75_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16126_dupName_75_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16126_dupName_75_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16130_dupName_76_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16132_dupName_76_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16134_dupName_76_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16134_dupName_76_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16135_dupName_76_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16137_dupName_76_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16139_dupName_76_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16139_dupName_76_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16143_dupName_77_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16145_dupName_77_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16147_dupName_77_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16147_dupName_77_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16148_dupName_77_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16150_dupName_77_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16152_dupName_77_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16152_dupName_77_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16153_dupName_77_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16155_dupName_77_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16157_dupName_77_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16157_dupName_77_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16161_dupName_78_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16163_dupName_78_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16165_dupName_78_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16165_dupName_78_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16166_dupName_78_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16168_dupName_78_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16170_dupName_78_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16170_dupName_78_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16174_dupName_79_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16176_dupName_79_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16178_dupName_79_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16178_dupName_79_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16179_dupName_79_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16181_dupName_79_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16183_dupName_79_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16183_dupName_79_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16184_dupName_79_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16186_dupName_79_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16188_dupName_79_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16188_dupName_79_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16192_dupName_80_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16194_dupName_80_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16196_dupName_80_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16196_dupName_80_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16197_dupName_80_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16199_dupName_80_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16201_dupName_80_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16201_dupName_80_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16205_dupName_81_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16207_dupName_81_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16209_dupName_81_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16209_dupName_81_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16210_dupName_81_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16212_dupName_81_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16214_dupName_81_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16214_dupName_81_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16215_dupName_81_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16217_dupName_81_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16219_dupName_81_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16219_dupName_81_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16223_dupName_82_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16225_dupName_82_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16227_dupName_82_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16227_dupName_82_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16228_dupName_82_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16230_dupName_82_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16232_dupName_82_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16232_dupName_82_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16236_dupName_83_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16238_dupName_83_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16240_dupName_83_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16240_dupName_83_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16241_dupName_83_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16243_dupName_83_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16245_dupName_83_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16245_dupName_83_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16246_dupName_83_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16248_dupName_83_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16250_dupName_83_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16250_dupName_83_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16254_dupName_84_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16256_dupName_84_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16258_dupName_84_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16258_dupName_84_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16259_dupName_84_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16261_dupName_84_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16263_dupName_84_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16263_dupName_84_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16267_dupName_85_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16269_dupName_85_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16271_dupName_85_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16271_dupName_85_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16272_dupName_85_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16274_dupName_85_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16276_dupName_85_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16276_dupName_85_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16277_dupName_85_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16279_dupName_85_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16281_dupName_85_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16281_dupName_85_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16285_dupName_86_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16287_dupName_86_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16289_dupName_86_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16289_dupName_86_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16290_dupName_86_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16292_dupName_86_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16294_dupName_86_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16294_dupName_86_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16298_dupName_87_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16300_dupName_87_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16302_dupName_87_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16302_dupName_87_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16303_dupName_87_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16305_dupName_87_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16307_dupName_87_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16307_dupName_87_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16308_dupName_87_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16310_dupName_87_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16312_dupName_87_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16312_dupName_87_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16316_dupName_88_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16318_dupName_88_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16320_dupName_88_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16320_dupName_88_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16321_dupName_88_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16323_dupName_88_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16325_dupName_88_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16325_dupName_88_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16329_dupName_89_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16331_dupName_89_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16333_dupName_89_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16333_dupName_89_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16334_dupName_89_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16336_dupName_89_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16338_dupName_89_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16338_dupName_89_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16339_dupName_89_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16341_dupName_89_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16343_dupName_89_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16343_dupName_89_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16347_dupName_90_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16349_dupName_90_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16351_dupName_90_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16351_dupName_90_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16352_dupName_90_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16354_dupName_90_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16356_dupName_90_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16356_dupName_90_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16360_dupName_91_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16362_dupName_91_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16364_dupName_91_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16364_dupName_91_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16365_dupName_91_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16367_dupName_91_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16369_dupName_91_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16369_dupName_91_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16370_dupName_91_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16372_dupName_91_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16374_dupName_91_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16374_dupName_91_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16378_dupName_92_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16380_dupName_92_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16382_dupName_92_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16382_dupName_92_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16383_dupName_92_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16385_dupName_92_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16387_dupName_92_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16387_dupName_92_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16391_dupName_93_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16393_dupName_93_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16395_dupName_93_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16395_dupName_93_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16396_dupName_93_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16398_dupName_93_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16400_dupName_93_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16400_dupName_93_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16401_dupName_93_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16403_dupName_93_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16405_dupName_93_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16405_dupName_93_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16409_dupName_94_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16411_dupName_94_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16413_dupName_94_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16413_dupName_94_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16414_dupName_94_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16416_dupName_94_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16418_dupName_94_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16418_dupName_94_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16422_dupName_95_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16424_dupName_95_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16426_dupName_95_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16426_dupName_95_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16427_dupName_95_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16429_dupName_95_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16431_dupName_95_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16431_dupName_95_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16432_dupName_95_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16434_dupName_95_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16436_dupName_95_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16436_dupName_95_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16440_dupName_96_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16442_dupName_96_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16444_dupName_96_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16444_dupName_96_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16445_dupName_96_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16447_dupName_96_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16449_dupName_96_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16449_dupName_96_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16453_dupName_97_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16455_dupName_97_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16457_dupName_97_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16457_dupName_97_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16458_dupName_97_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16460_dupName_97_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16462_dupName_97_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16462_dupName_97_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16463_dupName_97_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16465_dupName_97_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16467_dupName_97_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16467_dupName_97_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16471_dupName_98_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16473_dupName_98_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16475_dupName_98_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16475_dupName_98_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16476_dupName_98_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16478_dupName_98_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16480_dupName_98_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16480_dupName_98_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16484_dupName_99_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16486_dupName_99_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16488_dupName_99_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16488_dupName_99_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16489_dupName_99_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16491_dupName_99_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16493_dupName_99_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16493_dupName_99_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16494_dupName_99_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16496_dupName_99_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16498_dupName_99_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16498_dupName_99_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16502_dupName_100_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16504_dupName_100_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16506_dupName_100_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16506_dupName_100_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16507_dupName_100_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16509_dupName_100_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16511_dupName_100_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16511_dupName_100_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16515_dupName_101_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16517_dupName_101_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16519_dupName_101_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16519_dupName_101_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16520_dupName_101_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16522_dupName_101_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16524_dupName_101_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16524_dupName_101_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16525_dupName_101_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16527_dupName_101_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16529_dupName_101_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16529_dupName_101_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16533_dupName_102_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16535_dupName_102_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16537_dupName_102_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16537_dupName_102_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16538_dupName_102_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16540_dupName_102_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16542_dupName_102_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16542_dupName_102_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16546_dupName_103_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16548_dupName_103_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16550_dupName_103_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16550_dupName_103_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16551_dupName_103_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16553_dupName_103_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16555_dupName_103_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16555_dupName_103_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16556_dupName_103_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16558_dupName_103_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16560_dupName_103_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16560_dupName_103_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16564_dupName_104_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16566_dupName_104_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16568_dupName_104_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16568_dupName_104_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16569_dupName_104_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16571_dupName_104_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16573_dupName_104_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16573_dupName_104_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16577_dupName_105_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16579_dupName_105_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16581_dupName_105_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16581_dupName_105_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16582_dupName_105_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16584_dupName_105_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16586_dupName_105_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16586_dupName_105_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16587_dupName_105_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16589_dupName_105_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16591_dupName_105_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16591_dupName_105_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16595_dupName_106_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16597_dupName_106_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16599_dupName_106_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16599_dupName_106_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16600_dupName_106_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16602_dupName_106_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16604_dupName_106_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16604_dupName_106_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16608_dupName_107_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16610_dupName_107_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16612_dupName_107_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16612_dupName_107_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16613_dupName_107_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16615_dupName_107_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16617_dupName_107_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16617_dupName_107_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16618_dupName_107_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16620_dupName_107_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16622_dupName_107_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16622_dupName_107_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16626_dupName_108_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16628_dupName_108_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16630_dupName_108_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16630_dupName_108_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16631_dupName_108_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16633_dupName_108_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16635_dupName_108_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16635_dupName_108_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16639_dupName_109_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16641_dupName_109_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16643_dupName_109_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16643_dupName_109_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16644_dupName_109_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16646_dupName_109_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16648_dupName_109_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16648_dupName_109_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16649_dupName_109_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16651_dupName_109_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16653_dupName_109_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16653_dupName_109_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16657_dupName_110_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16659_dupName_110_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16661_dupName_110_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16661_dupName_110_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16662_dupName_110_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16664_dupName_110_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16666_dupName_110_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16666_dupName_110_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16670_dupName_111_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16672_dupName_111_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16674_dupName_111_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16674_dupName_111_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16675_dupName_111_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16677_dupName_111_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16679_dupName_111_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16679_dupName_111_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16680_dupName_111_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16682_dupName_111_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16684_dupName_111_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16684_dupName_111_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16688_dupName_112_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16690_dupName_112_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16692_dupName_112_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16692_dupName_112_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16693_dupName_112_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16695_dupName_112_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16697_dupName_112_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16697_dupName_112_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16701_dupName_113_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16703_dupName_113_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16705_dupName_113_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16705_dupName_113_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16706_dupName_113_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16708_dupName_113_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16710_dupName_113_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16710_dupName_113_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16711_dupName_113_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16713_dupName_113_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16715_dupName_113_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16715_dupName_113_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16719_dupName_114_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16721_dupName_114_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16723_dupName_114_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16723_dupName_114_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16724_dupName_114_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16726_dupName_114_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16728_dupName_114_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16728_dupName_114_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16732_dupName_115_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16734_dupName_115_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16736_dupName_115_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16736_dupName_115_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16737_dupName_115_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16739_dupName_115_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16741_dupName_115_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16741_dupName_115_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16742_dupName_115_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16744_dupName_115_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16746_dupName_115_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16746_dupName_115_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16750_dupName_116_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16752_dupName_116_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16754_dupName_116_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16754_dupName_116_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16755_dupName_116_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16757_dupName_116_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16759_dupName_116_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16759_dupName_116_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16763_dupName_117_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16765_dupName_117_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16767_dupName_117_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16767_dupName_117_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16768_dupName_117_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16770_dupName_117_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16772_dupName_117_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16772_dupName_117_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16773_dupName_117_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16775_dupName_117_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16777_dupName_117_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16777_dupName_117_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16781_dupName_118_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16783_dupName_118_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16785_dupName_118_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16785_dupName_118_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16786_dupName_118_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16788_dupName_118_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16790_dupName_118_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16790_dupName_118_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16794_dupName_119_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16796_dupName_119_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16798_dupName_119_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16798_dupName_119_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16799_dupName_119_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16801_dupName_119_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16803_dupName_119_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16803_dupName_119_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16804_dupName_119_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16806_dupName_119_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16808_dupName_119_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16808_dupName_119_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16812_dupName_120_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16814_dupName_120_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16816_dupName_120_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16816_dupName_120_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16817_dupName_120_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16819_dupName_120_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16821_dupName_120_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16821_dupName_120_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16825_dupName_121_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16827_dupName_121_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16829_dupName_121_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16829_dupName_121_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16830_dupName_121_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16832_dupName_121_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16834_dupName_121_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16834_dupName_121_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16835_dupName_121_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16837_dupName_121_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16839_dupName_121_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16839_dupName_121_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16843_dupName_122_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16845_dupName_122_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16847_dupName_122_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16847_dupName_122_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16848_dupName_122_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16850_dupName_122_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16852_dupName_122_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16852_dupName_122_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16856_dupName_123_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16858_dupName_123_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16860_dupName_123_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16860_dupName_123_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16861_dupName_123_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16863_dupName_123_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16865_dupName_123_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16865_dupName_123_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16866_dupName_123_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16868_dupName_123_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16870_dupName_123_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16870_dupName_123_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16874_dupName_124_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16876_dupName_124_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16878_dupName_124_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16878_dupName_124_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16879_dupName_124_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16881_dupName_124_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16883_dupName_124_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16883_dupName_124_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16887_dupName_125_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16889_dupName_125_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16891_dupName_125_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16891_dupName_125_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16892_dupName_125_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16894_dupName_125_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16896_dupName_125_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16896_dupName_125_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16897_dupName_125_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16899_dupName_125_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16901_dupName_125_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16901_dupName_125_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16905_dupName_126_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16907_dupName_126_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16909_dupName_126_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16909_dupName_126_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16910_dupName_126_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16912_dupName_126_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16914_dupName_126_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16914_dupName_126_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16918_dupName_127_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16920_dupName_127_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16922_dupName_127_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16922_dupName_127_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16923_dupName_127_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16925_dupName_127_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16927_dupName_127_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16927_dupName_127_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16928_dupName_127_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16930_dupName_127_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16932_dupName_127_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16932_dupName_127_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16936_dupName_128_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16938_dupName_128_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16940_dupName_128_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16940_dupName_128_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16941_dupName_128_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16943_dupName_128_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16945_dupName_128_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16945_dupName_128_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16949_dupName_129_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16951_dupName_129_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16953_dupName_129_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16953_dupName_129_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16954_dupName_129_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16956_dupName_129_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16958_dupName_129_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16958_dupName_129_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16959_dupName_129_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16961_dupName_129_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16963_dupName_129_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16963_dupName_129_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16967_dupName_130_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16969_dupName_130_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16971_dupName_130_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16971_dupName_130_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16972_dupName_130_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16974_dupName_130_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16976_dupName_130_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16976_dupName_130_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16980_dupName_131_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16982_dupName_131_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16984_dupName_131_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16984_dupName_131_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16985_dupName_131_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16987_dupName_131_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16989_dupName_131_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16989_dupName_131_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16990_dupName_131_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16992_dupName_131_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16994_dupName_131_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16994_dupName_131_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16998_dupName_132_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17000_dupName_132_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17002_dupName_132_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17002_dupName_132_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17003_dupName_132_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17005_dupName_132_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17007_dupName_132_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17007_dupName_132_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17011_dupName_133_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17013_dupName_133_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17015_dupName_133_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17015_dupName_133_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17016_dupName_133_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17018_dupName_133_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17020_dupName_133_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17020_dupName_133_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17021_dupName_133_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17023_dupName_133_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17025_dupName_133_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17025_dupName_133_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17029_dupName_134_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17031_dupName_134_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17033_dupName_134_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17033_dupName_134_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17034_dupName_134_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17036_dupName_134_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17038_dupName_134_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17038_dupName_134_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17042_dupName_135_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17044_dupName_135_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17046_dupName_135_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17046_dupName_135_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17047_dupName_135_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17049_dupName_135_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17051_dupName_135_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17051_dupName_135_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17052_dupName_135_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17054_dupName_135_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17056_dupName_135_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17056_dupName_135_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17060_dupName_136_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17062_dupName_136_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17064_dupName_136_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17064_dupName_136_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17065_dupName_136_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17067_dupName_136_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17069_dupName_136_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17069_dupName_136_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17073_dupName_137_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17075_dupName_137_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17077_dupName_137_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17077_dupName_137_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17078_dupName_137_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17080_dupName_137_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17082_dupName_137_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17082_dupName_137_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17083_dupName_137_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17085_dupName_137_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17087_dupName_137_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17087_dupName_137_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17091_dupName_138_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17093_dupName_138_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17095_dupName_138_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17095_dupName_138_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17096_dupName_138_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17098_dupName_138_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17100_dupName_138_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17100_dupName_138_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17104_dupName_139_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17106_dupName_139_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17108_dupName_139_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17108_dupName_139_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17109_dupName_139_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17111_dupName_139_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17113_dupName_139_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17113_dupName_139_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17114_dupName_139_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17116_dupName_139_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17118_dupName_139_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17118_dupName_139_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17122_dupName_140_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17124_dupName_140_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17126_dupName_140_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17126_dupName_140_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17127_dupName_140_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17129_dupName_140_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17131_dupName_140_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17131_dupName_140_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17135_dupName_141_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17137_dupName_141_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17139_dupName_141_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17139_dupName_141_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17140_dupName_141_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17142_dupName_141_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17144_dupName_141_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17144_dupName_141_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17145_dupName_141_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17147_dupName_141_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17149_dupName_141_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17149_dupName_141_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17153_dupName_142_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17155_dupName_142_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17157_dupName_142_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17157_dupName_142_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17158_dupName_142_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17160_dupName_142_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17162_dupName_142_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17162_dupName_142_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17166_dupName_143_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17168_dupName_143_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17170_dupName_143_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17170_dupName_143_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17171_dupName_143_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17173_dupName_143_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17175_dupName_143_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17175_dupName_143_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17176_dupName_143_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17178_dupName_143_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17180_dupName_143_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17180_dupName_143_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17184_dupName_144_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17186_dupName_144_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17188_dupName_144_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17188_dupName_144_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17189_dupName_144_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17191_dupName_144_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17193_dupName_144_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17193_dupName_144_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17197_dupName_145_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17199_dupName_145_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17201_dupName_145_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17201_dupName_145_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17202_dupName_145_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17204_dupName_145_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17206_dupName_145_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17206_dupName_145_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17207_dupName_145_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17209_dupName_145_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17211_dupName_145_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17211_dupName_145_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17215_dupName_146_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17217_dupName_146_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17219_dupName_146_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17219_dupName_146_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17220_dupName_146_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17222_dupName_146_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17224_dupName_146_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17224_dupName_146_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17228_dupName_147_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17230_dupName_147_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17232_dupName_147_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17232_dupName_147_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17233_dupName_147_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17235_dupName_147_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17237_dupName_147_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17237_dupName_147_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17238_dupName_147_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17240_dupName_147_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17242_dupName_147_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17242_dupName_147_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17246_dupName_148_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17248_dupName_148_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17250_dupName_148_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17250_dupName_148_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17251_dupName_148_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17253_dupName_148_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17255_dupName_148_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17255_dupName_148_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17259_dupName_149_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17261_dupName_149_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17263_dupName_149_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17263_dupName_149_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17264_dupName_149_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17266_dupName_149_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17268_dupName_149_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17268_dupName_149_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17269_dupName_149_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17271_dupName_149_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17273_dupName_149_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17273_dupName_149_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17277_dupName_150_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17279_dupName_150_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17281_dupName_150_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17281_dupName_150_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17282_dupName_150_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17284_dupName_150_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17286_dupName_150_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17286_dupName_150_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17290_dupName_151_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17292_dupName_151_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17294_dupName_151_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17294_dupName_151_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17295_dupName_151_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17297_dupName_151_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17299_dupName_151_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17299_dupName_151_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17300_dupName_151_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17302_dupName_151_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17304_dupName_151_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17304_dupName_151_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17308_dupName_152_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17310_dupName_152_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17312_dupName_152_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17312_dupName_152_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17313_dupName_152_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17315_dupName_152_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17317_dupName_152_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17317_dupName_152_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17321_dupName_153_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17323_dupName_153_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17325_dupName_153_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17325_dupName_153_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17326_dupName_153_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17328_dupName_153_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17330_dupName_153_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17330_dupName_153_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17331_dupName_153_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17333_dupName_153_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17335_dupName_153_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17335_dupName_153_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17339_dupName_154_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17341_dupName_154_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17343_dupName_154_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17343_dupName_154_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17344_dupName_154_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17346_dupName_154_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17348_dupName_154_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17348_dupName_154_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17352_dupName_155_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17354_dupName_155_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17356_dupName_155_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17356_dupName_155_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17357_dupName_155_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17359_dupName_155_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17361_dupName_155_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17361_dupName_155_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17362_dupName_155_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17364_dupName_155_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17366_dupName_155_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17366_dupName_155_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17370_dupName_156_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17372_dupName_156_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17374_dupName_156_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17374_dupName_156_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17375_dupName_156_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17377_dupName_156_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17379_dupName_156_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17379_dupName_156_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17383_dupName_157_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17385_dupName_157_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17387_dupName_157_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17387_dupName_157_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17388_dupName_157_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17390_dupName_157_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17392_dupName_157_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17392_dupName_157_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17393_dupName_157_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17395_dupName_157_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17397_dupName_157_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17397_dupName_157_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17401_dupName_158_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17403_dupName_158_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17405_dupName_158_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17405_dupName_158_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17406_dupName_158_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17408_dupName_158_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17410_dupName_158_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17410_dupName_158_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17414_dupName_159_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17416_dupName_159_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17418_dupName_159_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17418_dupName_159_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17419_dupName_159_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17421_dupName_159_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17423_dupName_159_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17423_dupName_159_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17424_dupName_159_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17426_dupName_159_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17428_dupName_159_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17428_dupName_159_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17432_dupName_160_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17434_dupName_160_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17436_dupName_160_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17436_dupName_160_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17437_dupName_160_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17439_dupName_160_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17441_dupName_160_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17441_dupName_160_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17445_dupName_161_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17447_dupName_161_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17449_dupName_161_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17449_dupName_161_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17450_dupName_161_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17452_dupName_161_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17454_dupName_161_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17454_dupName_161_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17455_dupName_161_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17457_dupName_161_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17459_dupName_161_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17459_dupName_161_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17463_dupName_162_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17465_dupName_162_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17467_dupName_162_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17467_dupName_162_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17468_dupName_162_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17470_dupName_162_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17472_dupName_162_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17472_dupName_162_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17476_dupName_163_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17478_dupName_163_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17480_dupName_163_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17480_dupName_163_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17481_dupName_163_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17483_dupName_163_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17485_dupName_163_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17485_dupName_163_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17486_dupName_163_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17488_dupName_163_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17490_dupName_163_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17490_dupName_163_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17494_dupName_164_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17496_dupName_164_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17498_dupName_164_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17498_dupName_164_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17499_dupName_164_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17501_dupName_164_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17503_dupName_164_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17503_dupName_164_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17507_dupName_165_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17509_dupName_165_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17511_dupName_165_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17511_dupName_165_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17512_dupName_165_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17514_dupName_165_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17516_dupName_165_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17516_dupName_165_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17517_dupName_165_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17519_dupName_165_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17521_dupName_165_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17521_dupName_165_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17525_dupName_166_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17527_dupName_166_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17529_dupName_166_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17529_dupName_166_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17530_dupName_166_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17532_dupName_166_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17534_dupName_166_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17534_dupName_166_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17538_dupName_167_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17540_dupName_167_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17542_dupName_167_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17542_dupName_167_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17543_dupName_167_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17545_dupName_167_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17547_dupName_167_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17547_dupName_167_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17548_dupName_167_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17550_dupName_167_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17552_dupName_167_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17552_dupName_167_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17556_dupName_168_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17558_dupName_168_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17560_dupName_168_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17560_dupName_168_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17561_dupName_168_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17563_dupName_168_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17565_dupName_168_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17565_dupName_168_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17569_dupName_169_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17571_dupName_169_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17573_dupName_169_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17573_dupName_169_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17574_dupName_169_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17576_dupName_169_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17578_dupName_169_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17578_dupName_169_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17579_dupName_169_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17581_dupName_169_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17583_dupName_169_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17583_dupName_169_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17587_dupName_170_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17589_dupName_170_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17591_dupName_170_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17591_dupName_170_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17592_dupName_170_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17594_dupName_170_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17596_dupName_170_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17596_dupName_170_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17600_dupName_171_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17602_dupName_171_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17604_dupName_171_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17604_dupName_171_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17605_dupName_171_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17607_dupName_171_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17609_dupName_171_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17609_dupName_171_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17610_dupName_171_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17612_dupName_171_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17614_dupName_171_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17614_dupName_171_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17618_dupName_172_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17620_dupName_172_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17622_dupName_172_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17622_dupName_172_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17623_dupName_172_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17625_dupName_172_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17627_dupName_172_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17627_dupName_172_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17631_dupName_173_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17633_dupName_173_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17635_dupName_173_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17635_dupName_173_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17636_dupName_173_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17638_dupName_173_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17640_dupName_173_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17640_dupName_173_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17641_dupName_173_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17643_dupName_173_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17645_dupName_173_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17645_dupName_173_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17649_dupName_174_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17651_dupName_174_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17653_dupName_174_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17653_dupName_174_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17654_dupName_174_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17656_dupName_174_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17658_dupName_174_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17658_dupName_174_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17662_dupName_175_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17664_dupName_175_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17666_dupName_175_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17666_dupName_175_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17667_dupName_175_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17669_dupName_175_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17671_dupName_175_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17671_dupName_175_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17672_dupName_175_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17674_dupName_175_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17676_dupName_175_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17676_dupName_175_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17680_dupName_176_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17682_dupName_176_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17684_dupName_176_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17684_dupName_176_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17685_dupName_176_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17687_dupName_176_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17689_dupName_176_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17689_dupName_176_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17693_dupName_177_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17695_dupName_177_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17697_dupName_177_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17697_dupName_177_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17698_dupName_177_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17700_dupName_177_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17702_dupName_177_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17702_dupName_177_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17703_dupName_177_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17705_dupName_177_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17707_dupName_177_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17707_dupName_177_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17711_dupName_178_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17713_dupName_178_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17715_dupName_178_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17715_dupName_178_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17716_dupName_178_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17718_dupName_178_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17720_dupName_178_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17720_dupName_178_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17724_dupName_179_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17726_dupName_179_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17728_dupName_179_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17728_dupName_179_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17729_dupName_179_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17731_dupName_179_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17733_dupName_179_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17733_dupName_179_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17734_dupName_179_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17736_dupName_179_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17738_dupName_179_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17738_dupName_179_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17742_dupName_180_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17744_dupName_180_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17746_dupName_180_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17746_dupName_180_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17747_dupName_180_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17749_dupName_180_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17751_dupName_180_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17751_dupName_180_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17755_dupName_181_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17757_dupName_181_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17759_dupName_181_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17759_dupName_181_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17760_dupName_181_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17762_dupName_181_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17764_dupName_181_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17764_dupName_181_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17765_dupName_181_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17767_dupName_181_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17769_dupName_181_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17769_dupName_181_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17773_dupName_182_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17775_dupName_182_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17777_dupName_182_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17777_dupName_182_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17778_dupName_182_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17780_dupName_182_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17782_dupName_182_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17782_dupName_182_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17786_dupName_183_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17788_dupName_183_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17790_dupName_183_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17790_dupName_183_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17791_dupName_183_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17793_dupName_183_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17795_dupName_183_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17795_dupName_183_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17796_dupName_183_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17798_dupName_183_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17800_dupName_183_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17800_dupName_183_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17804_dupName_184_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17806_dupName_184_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17808_dupName_184_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17808_dupName_184_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17809_dupName_184_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17811_dupName_184_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17813_dupName_184_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17813_dupName_184_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17817_dupName_185_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17819_dupName_185_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17821_dupName_185_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17821_dupName_185_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17822_dupName_185_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17824_dupName_185_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17826_dupName_185_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17826_dupName_185_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17827_dupName_185_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17829_dupName_185_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17831_dupName_185_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17831_dupName_185_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17835_dupName_186_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17837_dupName_186_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17839_dupName_186_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17839_dupName_186_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17840_dupName_186_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17842_dupName_186_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17844_dupName_186_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17844_dupName_186_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17848_dupName_187_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17850_dupName_187_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17852_dupName_187_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17852_dupName_187_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17853_dupName_187_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17855_dupName_187_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17857_dupName_187_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17857_dupName_187_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17858_dupName_187_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17860_dupName_187_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17862_dupName_187_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17862_dupName_187_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17866_dupName_188_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17868_dupName_188_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17870_dupName_188_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17870_dupName_188_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17871_dupName_188_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17873_dupName_188_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17875_dupName_188_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17875_dupName_188_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17879_dupName_189_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17881_dupName_189_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17883_dupName_189_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17883_dupName_189_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17884_dupName_189_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17886_dupName_189_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17888_dupName_189_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17888_dupName_189_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17889_dupName_189_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17891_dupName_189_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17893_dupName_189_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17893_dupName_189_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17897_dupName_190_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17899_dupName_190_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17901_dupName_190_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17901_dupName_190_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17902_dupName_190_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17904_dupName_190_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17906_dupName_190_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17906_dupName_190_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17910_dupName_191_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17912_dupName_191_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17914_dupName_191_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17914_dupName_191_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17915_dupName_191_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17917_dupName_191_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17919_dupName_191_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17919_dupName_191_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17920_dupName_191_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17922_dupName_191_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17924_dupName_191_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17924_dupName_191_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17928_dupName_192_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17930_dupName_192_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17932_dupName_192_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17932_dupName_192_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17933_dupName_192_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17935_dupName_192_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17937_dupName_192_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17937_dupName_192_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17941_dupName_193_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17943_dupName_193_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17945_dupName_193_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17945_dupName_193_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17946_dupName_193_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17948_dupName_193_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17950_dupName_193_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17950_dupName_193_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17951_dupName_193_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17953_dupName_193_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17955_dupName_193_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17955_dupName_193_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17959_dupName_194_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17961_dupName_194_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17963_dupName_194_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17963_dupName_194_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17964_dupName_194_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17966_dupName_194_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17968_dupName_194_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17968_dupName_194_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17972_dupName_195_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17974_dupName_195_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17976_dupName_195_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17976_dupName_195_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17977_dupName_195_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17979_dupName_195_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17981_dupName_195_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17981_dupName_195_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17982_dupName_195_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17984_dupName_195_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17986_dupName_195_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17986_dupName_195_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17990_dupName_196_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17992_dupName_196_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17994_dupName_196_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17994_dupName_196_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17995_dupName_196_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17997_dupName_196_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17999_dupName_196_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17999_dupName_196_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18003_dupName_197_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18005_dupName_197_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18007_dupName_197_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18007_dupName_197_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18008_dupName_197_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18010_dupName_197_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18012_dupName_197_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18012_dupName_197_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18013_dupName_197_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18015_dupName_197_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18017_dupName_197_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18017_dupName_197_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18021_dupName_198_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18023_dupName_198_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18025_dupName_198_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18025_dupName_198_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18026_dupName_198_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18028_dupName_198_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18030_dupName_198_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18030_dupName_198_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18034_dupName_199_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18036_dupName_199_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18038_dupName_199_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18038_dupName_199_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18039_dupName_199_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18041_dupName_199_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18043_dupName_199_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18043_dupName_199_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18044_dupName_199_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18046_dupName_199_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18048_dupName_199_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18048_dupName_199_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18052_dupName_200_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18054_dupName_200_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18056_dupName_200_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18056_dupName_200_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18057_dupName_200_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18059_dupName_200_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18061_dupName_200_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18061_dupName_200_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18065_dupName_201_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18067_dupName_201_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18069_dupName_201_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18069_dupName_201_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18070_dupName_201_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18072_dupName_201_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18074_dupName_201_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18074_dupName_201_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18075_dupName_201_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18077_dupName_201_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18079_dupName_201_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18079_dupName_201_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18083_dupName_202_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18085_dupName_202_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18087_dupName_202_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18087_dupName_202_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18088_dupName_202_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18090_dupName_202_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18092_dupName_202_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18092_dupName_202_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18096_dupName_203_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18098_dupName_203_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18100_dupName_203_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18100_dupName_203_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18101_dupName_203_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18103_dupName_203_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18105_dupName_203_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18105_dupName_203_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18106_dupName_203_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18108_dupName_203_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18110_dupName_203_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18110_dupName_203_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18114_dupName_204_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18116_dupName_204_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18118_dupName_204_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18118_dupName_204_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18119_dupName_204_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18121_dupName_204_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18123_dupName_204_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18123_dupName_204_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18127_dupName_205_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18129_dupName_205_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18131_dupName_205_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18131_dupName_205_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18132_dupName_205_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18134_dupName_205_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18136_dupName_205_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18136_dupName_205_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18137_dupName_205_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18139_dupName_205_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18141_dupName_205_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18141_dupName_205_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18145_dupName_206_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18147_dupName_206_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18149_dupName_206_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18149_dupName_206_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18150_dupName_206_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18152_dupName_206_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18154_dupName_206_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18154_dupName_206_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18158_dupName_207_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18160_dupName_207_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18162_dupName_207_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18162_dupName_207_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18163_dupName_207_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18165_dupName_207_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18167_dupName_207_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18167_dupName_207_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18168_dupName_207_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18170_dupName_207_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18172_dupName_207_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18172_dupName_207_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18176_dupName_208_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18178_dupName_208_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18180_dupName_208_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18180_dupName_208_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18181_dupName_208_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18183_dupName_208_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18185_dupName_208_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18185_dupName_208_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18189_dupName_209_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18191_dupName_209_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18193_dupName_209_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18193_dupName_209_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18194_dupName_209_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18196_dupName_209_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18198_dupName_209_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18198_dupName_209_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18199_dupName_209_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18201_dupName_209_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18203_dupName_209_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18203_dupName_209_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18207_dupName_210_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18209_dupName_210_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18211_dupName_210_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18211_dupName_210_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18212_dupName_210_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18214_dupName_210_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18216_dupName_210_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18216_dupName_210_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18220_dupName_211_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18222_dupName_211_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18224_dupName_211_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18224_dupName_211_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18225_dupName_211_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18227_dupName_211_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18229_dupName_211_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18229_dupName_211_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18230_dupName_211_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18232_dupName_211_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18234_dupName_211_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18234_dupName_211_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18238_dupName_212_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18240_dupName_212_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18242_dupName_212_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18242_dupName_212_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18243_dupName_212_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18245_dupName_212_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18247_dupName_212_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18247_dupName_212_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18251_dupName_213_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18253_dupName_213_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18255_dupName_213_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18255_dupName_213_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18256_dupName_213_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18258_dupName_213_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18260_dupName_213_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18260_dupName_213_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18261_dupName_213_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18263_dupName_213_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18265_dupName_213_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18265_dupName_213_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18269_dupName_214_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18271_dupName_214_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18273_dupName_214_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18273_dupName_214_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18274_dupName_214_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18276_dupName_214_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18278_dupName_214_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18278_dupName_214_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18282_dupName_215_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18284_dupName_215_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18286_dupName_215_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18286_dupName_215_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18287_dupName_215_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18289_dupName_215_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18291_dupName_215_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18291_dupName_215_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18292_dupName_215_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18294_dupName_215_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18296_dupName_215_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18296_dupName_215_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18300_dupName_216_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18302_dupName_216_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18304_dupName_216_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18304_dupName_216_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18305_dupName_216_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18307_dupName_216_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18309_dupName_216_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18309_dupName_216_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18313_dupName_217_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18315_dupName_217_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18317_dupName_217_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18317_dupName_217_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18318_dupName_217_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18320_dupName_217_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18322_dupName_217_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18322_dupName_217_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18323_dupName_217_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18325_dupName_217_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18327_dupName_217_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18327_dupName_217_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18331_dupName_218_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18333_dupName_218_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18335_dupName_218_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18335_dupName_218_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18336_dupName_218_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18338_dupName_218_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18340_dupName_218_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18340_dupName_218_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18344_dupName_219_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18346_dupName_219_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18348_dupName_219_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18348_dupName_219_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18349_dupName_219_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18351_dupName_219_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18353_dupName_219_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18353_dupName_219_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18354_dupName_219_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18356_dupName_219_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18358_dupName_219_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18358_dupName_219_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18362_dupName_220_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18364_dupName_220_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18366_dupName_220_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18366_dupName_220_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18367_dupName_220_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18369_dupName_220_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18371_dupName_220_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18371_dupName_220_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18375_dupName_221_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18377_dupName_221_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18379_dupName_221_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18379_dupName_221_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18380_dupName_221_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18382_dupName_221_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18384_dupName_221_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18384_dupName_221_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18385_dupName_221_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18387_dupName_221_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18389_dupName_221_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18389_dupName_221_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18393_dupName_222_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18395_dupName_222_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18397_dupName_222_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18397_dupName_222_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18398_dupName_222_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18400_dupName_222_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18402_dupName_222_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18402_dupName_222_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18406_dupName_223_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18408_dupName_223_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18410_dupName_223_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18410_dupName_223_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18411_dupName_223_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18413_dupName_223_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18415_dupName_223_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18415_dupName_223_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18416_dupName_223_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18418_dupName_223_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18420_dupName_223_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18420_dupName_223_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18424_dupName_224_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18426_dupName_224_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18428_dupName_224_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18428_dupName_224_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18429_dupName_224_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18431_dupName_224_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18433_dupName_224_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18433_dupName_224_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18437_dupName_225_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18439_dupName_225_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18441_dupName_225_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18441_dupName_225_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18442_dupName_225_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18444_dupName_225_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18446_dupName_225_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18446_dupName_225_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18447_dupName_225_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18449_dupName_225_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18451_dupName_225_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18451_dupName_225_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18455_dupName_226_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18457_dupName_226_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18459_dupName_226_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18459_dupName_226_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18460_dupName_226_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18462_dupName_226_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18464_dupName_226_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18464_dupName_226_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18468_dupName_227_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18470_dupName_227_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18472_dupName_227_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18472_dupName_227_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18473_dupName_227_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18475_dupName_227_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18477_dupName_227_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18477_dupName_227_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18478_dupName_227_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18480_dupName_227_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18482_dupName_227_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18482_dupName_227_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18486_dupName_228_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18488_dupName_228_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18490_dupName_228_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18490_dupName_228_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18491_dupName_228_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18493_dupName_228_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18495_dupName_228_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18495_dupName_228_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18499_dupName_229_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18501_dupName_229_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18503_dupName_229_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18503_dupName_229_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18504_dupName_229_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18506_dupName_229_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18508_dupName_229_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18508_dupName_229_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18509_dupName_229_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18511_dupName_229_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18513_dupName_229_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18513_dupName_229_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18517_dupName_230_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18519_dupName_230_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18521_dupName_230_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18521_dupName_230_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18522_dupName_230_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18524_dupName_230_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18526_dupName_230_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18526_dupName_230_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18530_dupName_231_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18532_dupName_231_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18534_dupName_231_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18534_dupName_231_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18535_dupName_231_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18537_dupName_231_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18539_dupName_231_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18539_dupName_231_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18540_dupName_231_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18542_dupName_231_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18544_dupName_231_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18544_dupName_231_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18548_dupName_232_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18550_dupName_232_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18552_dupName_232_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18552_dupName_232_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18553_dupName_232_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18555_dupName_232_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18557_dupName_232_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18557_dupName_232_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18561_dupName_233_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18563_dupName_233_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18565_dupName_233_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18565_dupName_233_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18566_dupName_233_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18568_dupName_233_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18570_dupName_233_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18570_dupName_233_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18571_dupName_233_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18573_dupName_233_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18575_dupName_233_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18575_dupName_233_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18579_dupName_234_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18581_dupName_234_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18583_dupName_234_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18583_dupName_234_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18584_dupName_234_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18586_dupName_234_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18588_dupName_234_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18588_dupName_234_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18592_dupName_235_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18594_dupName_235_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18596_dupName_235_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18596_dupName_235_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18597_dupName_235_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18599_dupName_235_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18601_dupName_235_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18601_dupName_235_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18602_dupName_235_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18604_dupName_235_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18606_dupName_235_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18606_dupName_235_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18610_dupName_236_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18612_dupName_236_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18614_dupName_236_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18614_dupName_236_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18615_dupName_236_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18617_dupName_236_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18619_dupName_236_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18619_dupName_236_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18623_dupName_237_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18625_dupName_237_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18627_dupName_237_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18627_dupName_237_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18628_dupName_237_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18630_dupName_237_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18632_dupName_237_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18632_dupName_237_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18633_dupName_237_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18635_dupName_237_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18637_dupName_237_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18637_dupName_237_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18641_dupName_238_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18643_dupName_238_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18645_dupName_238_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18645_dupName_238_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18646_dupName_238_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18648_dupName_238_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18650_dupName_238_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18650_dupName_238_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18654_dupName_239_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18656_dupName_239_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18658_dupName_239_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18658_dupName_239_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18659_dupName_239_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18661_dupName_239_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18663_dupName_239_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18663_dupName_239_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18664_dupName_239_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18666_dupName_239_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18668_dupName_239_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18668_dupName_239_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18672_dupName_240_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18674_dupName_240_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18676_dupName_240_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18676_dupName_240_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18677_dupName_240_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18679_dupName_240_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18681_dupName_240_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18681_dupName_240_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18685_dupName_241_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18687_dupName_241_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18689_dupName_241_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18689_dupName_241_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18690_dupName_241_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18692_dupName_241_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18694_dupName_241_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18694_dupName_241_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18695_dupName_241_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18697_dupName_241_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18699_dupName_241_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18699_dupName_241_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18703_dupName_242_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18705_dupName_242_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18707_dupName_242_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18707_dupName_242_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18708_dupName_242_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18710_dupName_242_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18712_dupName_242_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18712_dupName_242_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18716_dupName_243_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18718_dupName_243_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18720_dupName_243_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18720_dupName_243_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18721_dupName_243_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18723_dupName_243_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18725_dupName_243_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18725_dupName_243_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18726_dupName_243_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18728_dupName_243_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18730_dupName_243_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18730_dupName_243_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18734_dupName_244_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18736_dupName_244_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18738_dupName_244_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18738_dupName_244_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18739_dupName_244_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18741_dupName_244_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18743_dupName_244_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18743_dupName_244_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18747_dupName_245_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18749_dupName_245_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18751_dupName_245_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18751_dupName_245_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18752_dupName_245_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18754_dupName_245_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18756_dupName_245_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18756_dupName_245_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18757_dupName_245_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18759_dupName_245_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18761_dupName_245_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18761_dupName_245_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18765_dupName_246_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18767_dupName_246_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18769_dupName_246_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18769_dupName_246_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18770_dupName_246_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18772_dupName_246_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18774_dupName_246_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18774_dupName_246_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18778_dupName_247_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18780_dupName_247_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18782_dupName_247_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18782_dupName_247_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18783_dupName_247_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18785_dupName_247_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18787_dupName_247_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18787_dupName_247_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18788_dupName_247_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18790_dupName_247_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18792_dupName_247_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18792_dupName_247_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18796_dupName_248_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18798_dupName_248_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18800_dupName_248_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18800_dupName_248_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18801_dupName_248_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18803_dupName_248_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18805_dupName_248_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18805_dupName_248_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18809_dupName_249_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18811_dupName_249_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18813_dupName_249_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18813_dupName_249_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18814_dupName_249_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18816_dupName_249_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18818_dupName_249_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18818_dupName_249_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18819_dupName_249_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18821_dupName_249_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18823_dupName_249_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18823_dupName_249_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18827_dupName_250_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18829_dupName_250_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18831_dupName_250_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18831_dupName_250_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18832_dupName_250_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18834_dupName_250_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18836_dupName_250_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18836_dupName_250_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18840_dupName_251_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18842_dupName_251_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18844_dupName_251_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18844_dupName_251_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18845_dupName_251_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18847_dupName_251_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18849_dupName_251_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18849_dupName_251_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18850_dupName_251_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18852_dupName_251_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18854_dupName_251_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18854_dupName_251_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18858_dupName_252_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18860_dupName_252_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18862_dupName_252_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18862_dupName_252_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18863_dupName_252_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18865_dupName_252_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18867_dupName_252_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18867_dupName_252_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18871_dupName_253_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18873_dupName_253_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18875_dupName_253_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18875_dupName_253_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18876_dupName_253_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18878_dupName_253_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18880_dupName_253_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18880_dupName_253_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18881_dupName_253_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18883_dupName_253_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18885_dupName_253_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18885_dupName_253_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18889_dupName_254_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18891_dupName_254_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18893_dupName_254_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18893_dupName_254_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18894_dupName_254_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18896_dupName_254_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18898_dupName_254_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18898_dupName_254_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18902_dupName_255_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18904_dupName_255_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18906_dupName_255_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18906_dupName_255_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18907_dupName_255_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18909_dupName_255_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18911_dupName_255_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18911_dupName_255_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18912_dupName_255_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18914_dupName_255_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18916_dupName_255_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18916_dupName_255_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18920_dupName_256_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18922_dupName_256_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18924_dupName_256_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18924_dupName_256_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18925_dupName_256_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18927_dupName_256_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18929_dupName_256_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18929_dupName_256_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18933_dupName_257_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18935_dupName_257_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18937_dupName_257_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18937_dupName_257_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18938_dupName_257_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18940_dupName_257_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18942_dupName_257_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18942_dupName_257_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18943_dupName_257_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18945_dupName_257_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18947_dupName_257_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18947_dupName_257_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18951_dupName_258_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18953_dupName_258_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18955_dupName_258_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18955_dupName_258_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18956_dupName_258_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18958_dupName_258_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18960_dupName_258_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18960_dupName_258_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18964_dupName_259_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18966_dupName_259_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18968_dupName_259_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18968_dupName_259_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18969_dupName_259_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18971_dupName_259_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18973_dupName_259_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18973_dupName_259_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18974_dupName_259_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18976_dupName_259_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18978_dupName_259_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18978_dupName_259_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18982_dupName_260_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18984_dupName_260_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18986_dupName_260_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18986_dupName_260_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18987_dupName_260_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18989_dupName_260_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18991_dupName_260_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18991_dupName_260_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18995_dupName_261_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18997_dupName_261_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18999_dupName_261_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18999_dupName_261_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19000_dupName_261_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19002_dupName_261_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19004_dupName_261_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19004_dupName_261_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19005_dupName_261_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19007_dupName_261_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19009_dupName_261_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19009_dupName_261_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19013_dupName_262_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19015_dupName_262_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19017_dupName_262_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19017_dupName_262_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19018_dupName_262_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19020_dupName_262_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19022_dupName_262_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19022_dupName_262_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19026_dupName_263_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19028_dupName_263_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19030_dupName_263_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19030_dupName_263_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19031_dupName_263_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19033_dupName_263_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19035_dupName_263_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19035_dupName_263_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19036_dupName_263_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19038_dupName_263_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19040_dupName_263_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19040_dupName_263_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19044_dupName_264_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19046_dupName_264_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19048_dupName_264_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19048_dupName_264_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19049_dupName_264_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19051_dupName_264_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19053_dupName_264_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19053_dupName_264_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19057_dupName_265_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19059_dupName_265_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19061_dupName_265_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19061_dupName_265_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19062_dupName_265_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19064_dupName_265_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19066_dupName_265_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19066_dupName_265_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19067_dupName_265_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19069_dupName_265_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19071_dupName_265_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19071_dupName_265_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19075_dupName_266_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19077_dupName_266_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19079_dupName_266_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19079_dupName_266_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19080_dupName_266_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19082_dupName_266_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19084_dupName_266_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19084_dupName_266_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19088_dupName_267_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19090_dupName_267_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19092_dupName_267_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19092_dupName_267_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19093_dupName_267_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19095_dupName_267_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19097_dupName_267_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19097_dupName_267_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19098_dupName_267_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19100_dupName_267_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19102_dupName_267_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19102_dupName_267_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19106_dupName_268_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19108_dupName_268_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19110_dupName_268_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19110_dupName_268_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19111_dupName_268_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19113_dupName_268_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19115_dupName_268_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19115_dupName_268_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19119_dupName_269_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19121_dupName_269_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19123_dupName_269_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19123_dupName_269_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19124_dupName_269_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19126_dupName_269_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19128_dupName_269_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19128_dupName_269_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19129_dupName_269_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19131_dupName_269_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19133_dupName_269_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19133_dupName_269_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19137_dupName_270_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19139_dupName_270_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19141_dupName_270_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19141_dupName_270_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19142_dupName_270_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19144_dupName_270_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19146_dupName_270_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19146_dupName_270_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19150_dupName_271_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19152_dupName_271_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19154_dupName_271_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19154_dupName_271_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19155_dupName_271_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19157_dupName_271_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19159_dupName_271_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19159_dupName_271_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19160_dupName_271_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19162_dupName_271_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19164_dupName_271_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19164_dupName_271_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19168_dupName_272_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19170_dupName_272_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19172_dupName_272_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19172_dupName_272_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19173_dupName_272_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19175_dupName_272_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19177_dupName_272_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19177_dupName_272_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19181_dupName_273_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19183_dupName_273_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19185_dupName_273_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19185_dupName_273_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19186_dupName_273_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19188_dupName_273_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19190_dupName_273_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19190_dupName_273_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19191_dupName_273_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19193_dupName_273_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19195_dupName_273_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19195_dupName_273_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19199_dupName_274_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19201_dupName_274_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19203_dupName_274_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19203_dupName_274_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19204_dupName_274_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19206_dupName_274_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19208_dupName_274_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19208_dupName_274_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19212_dupName_275_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19214_dupName_275_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19216_dupName_275_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19216_dupName_275_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19217_dupName_275_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19219_dupName_275_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19221_dupName_275_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19221_dupName_275_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19222_dupName_275_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19224_dupName_275_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19226_dupName_275_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19226_dupName_275_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19230_dupName_276_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19232_dupName_276_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19234_dupName_276_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19234_dupName_276_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19235_dupName_276_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19237_dupName_276_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19239_dupName_276_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19239_dupName_276_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19243_dupName_277_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19245_dupName_277_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19247_dupName_277_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19247_dupName_277_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19248_dupName_277_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19250_dupName_277_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19252_dupName_277_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19252_dupName_277_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19253_dupName_277_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19255_dupName_277_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19257_dupName_277_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19257_dupName_277_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19261_dupName_278_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19263_dupName_278_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19265_dupName_278_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19265_dupName_278_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19266_dupName_278_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19268_dupName_278_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19270_dupName_278_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19270_dupName_278_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19274_dupName_279_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19276_dupName_279_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19278_dupName_279_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19278_dupName_279_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19279_dupName_279_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19281_dupName_279_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19283_dupName_279_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19283_dupName_279_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19284_dupName_279_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19286_dupName_279_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19288_dupName_279_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19288_dupName_279_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19292_dupName_280_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19294_dupName_280_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19296_dupName_280_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19296_dupName_280_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19297_dupName_280_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19299_dupName_280_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19301_dupName_280_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19301_dupName_280_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19305_dupName_281_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19307_dupName_281_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19309_dupName_281_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19309_dupName_281_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19310_dupName_281_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19312_dupName_281_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19314_dupName_281_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19314_dupName_281_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19315_dupName_281_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19317_dupName_281_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19319_dupName_281_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19319_dupName_281_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19323_dupName_282_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19325_dupName_282_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19327_dupName_282_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19327_dupName_282_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19328_dupName_282_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19330_dupName_282_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19332_dupName_282_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19332_dupName_282_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19336_dupName_283_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19338_dupName_283_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19340_dupName_283_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19340_dupName_283_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19341_dupName_283_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19343_dupName_283_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19345_dupName_283_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19345_dupName_283_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19346_dupName_283_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19348_dupName_283_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19350_dupName_283_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19350_dupName_283_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19354_dupName_284_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19356_dupName_284_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19358_dupName_284_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19358_dupName_284_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19359_dupName_284_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19361_dupName_284_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19363_dupName_284_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19363_dupName_284_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19367_dupName_285_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19369_dupName_285_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19371_dupName_285_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19371_dupName_285_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19372_dupName_285_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19374_dupName_285_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19376_dupName_285_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19376_dupName_285_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19377_dupName_285_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19379_dupName_285_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19381_dupName_285_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19381_dupName_285_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19385_dupName_286_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19387_dupName_286_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19389_dupName_286_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19389_dupName_286_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19390_dupName_286_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19392_dupName_286_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19394_dupName_286_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19394_dupName_286_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19398_dupName_287_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19400_dupName_287_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19402_dupName_287_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19402_dupName_287_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19403_dupName_287_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19405_dupName_287_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19407_dupName_287_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19407_dupName_287_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19408_dupName_287_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19410_dupName_287_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19412_dupName_287_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19412_dupName_287_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19416_dupName_288_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19418_dupName_288_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19420_dupName_288_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19420_dupName_288_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19421_dupName_288_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19423_dupName_288_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19425_dupName_288_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19425_dupName_288_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19429_dupName_289_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19431_dupName_289_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19433_dupName_289_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19433_dupName_289_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19434_dupName_289_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19436_dupName_289_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19438_dupName_289_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19438_dupName_289_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19439_dupName_289_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19441_dupName_289_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19443_dupName_289_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19443_dupName_289_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19447_dupName_290_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19449_dupName_290_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19451_dupName_290_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19451_dupName_290_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19452_dupName_290_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19454_dupName_290_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19456_dupName_290_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19456_dupName_290_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19460_dupName_291_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19462_dupName_291_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19464_dupName_291_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19464_dupName_291_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19465_dupName_291_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19467_dupName_291_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19469_dupName_291_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19469_dupName_291_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19470_dupName_291_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19472_dupName_291_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19474_dupName_291_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19474_dupName_291_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19478_dupName_292_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19480_dupName_292_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19482_dupName_292_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19482_dupName_292_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19483_dupName_292_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19485_dupName_292_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19487_dupName_292_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19487_dupName_292_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19491_dupName_293_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19493_dupName_293_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19495_dupName_293_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19495_dupName_293_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19496_dupName_293_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19498_dupName_293_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19500_dupName_293_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19500_dupName_293_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19501_dupName_293_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19503_dupName_293_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19505_dupName_293_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19505_dupName_293_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19509_dupName_294_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19511_dupName_294_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19513_dupName_294_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19513_dupName_294_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19514_dupName_294_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19516_dupName_294_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19518_dupName_294_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19518_dupName_294_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19522_dupName_295_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19524_dupName_295_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19526_dupName_295_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19526_dupName_295_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19527_dupName_295_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19529_dupName_295_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19531_dupName_295_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19531_dupName_295_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19532_dupName_295_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19534_dupName_295_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19536_dupName_295_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19536_dupName_295_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19540_dupName_296_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19542_dupName_296_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19544_dupName_296_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19544_dupName_296_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19545_dupName_296_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19547_dupName_296_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19549_dupName_296_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19549_dupName_296_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19553_dupName_297_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19555_dupName_297_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19557_dupName_297_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19557_dupName_297_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19558_dupName_297_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19560_dupName_297_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19562_dupName_297_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19562_dupName_297_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19563_dupName_297_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19565_dupName_297_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19567_dupName_297_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19567_dupName_297_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19571_dupName_298_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19573_dupName_298_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19575_dupName_298_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19575_dupName_298_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19576_dupName_298_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19578_dupName_298_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19580_dupName_298_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19580_dupName_298_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19584_dupName_299_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19586_dupName_299_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19588_dupName_299_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19588_dupName_299_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19589_dupName_299_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19591_dupName_299_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19593_dupName_299_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19593_dupName_299_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19594_dupName_299_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19596_dupName_299_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19598_dupName_299_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19598_dupName_299_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19602_dupName_300_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19604_dupName_300_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19606_dupName_300_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19606_dupName_300_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19607_dupName_300_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19609_dupName_300_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19611_dupName_300_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19611_dupName_300_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19615_dupName_301_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19617_dupName_301_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19619_dupName_301_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19619_dupName_301_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19620_dupName_301_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19622_dupName_301_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19624_dupName_301_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19624_dupName_301_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19625_dupName_301_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19627_dupName_301_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19629_dupName_301_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19629_dupName_301_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19633_dupName_302_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19635_dupName_302_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19637_dupName_302_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19637_dupName_302_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19638_dupName_302_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19640_dupName_302_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19642_dupName_302_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19642_dupName_302_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19646_dupName_303_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19648_dupName_303_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19650_dupName_303_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19650_dupName_303_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19651_dupName_303_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19653_dupName_303_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19655_dupName_303_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19655_dupName_303_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19656_dupName_303_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19658_dupName_303_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19660_dupName_303_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19660_dupName_303_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19664_dupName_304_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19666_dupName_304_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19668_dupName_304_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19668_dupName_304_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19669_dupName_304_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19671_dupName_304_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19673_dupName_304_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19673_dupName_304_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19677_dupName_305_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19679_dupName_305_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19681_dupName_305_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19681_dupName_305_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19682_dupName_305_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19684_dupName_305_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19686_dupName_305_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19686_dupName_305_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19687_dupName_305_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19689_dupName_305_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19691_dupName_305_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19691_dupName_305_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19695_dupName_306_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19697_dupName_306_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19699_dupName_306_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19699_dupName_306_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19700_dupName_306_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19702_dupName_306_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19704_dupName_306_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19704_dupName_306_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19708_dupName_307_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19710_dupName_307_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19712_dupName_307_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19712_dupName_307_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19713_dupName_307_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19715_dupName_307_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19717_dupName_307_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19717_dupName_307_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19718_dupName_307_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19720_dupName_307_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19722_dupName_307_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19722_dupName_307_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19726_dupName_308_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19728_dupName_308_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19730_dupName_308_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19730_dupName_308_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19731_dupName_308_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19733_dupName_308_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19735_dupName_308_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19735_dupName_308_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19739_dupName_309_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19741_dupName_309_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19743_dupName_309_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19743_dupName_309_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19744_dupName_309_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19746_dupName_309_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19748_dupName_309_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19748_dupName_309_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19749_dupName_309_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19751_dupName_309_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19753_dupName_309_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19753_dupName_309_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19757_dupName_310_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19759_dupName_310_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19761_dupName_310_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19761_dupName_310_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19762_dupName_310_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19764_dupName_310_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19766_dupName_310_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19766_dupName_310_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19770_dupName_311_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19772_dupName_311_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19774_dupName_311_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19774_dupName_311_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19775_dupName_311_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19777_dupName_311_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19779_dupName_311_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19779_dupName_311_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19780_dupName_311_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19782_dupName_311_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19784_dupName_311_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19784_dupName_311_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19788_dupName_312_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19790_dupName_312_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19792_dupName_312_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19792_dupName_312_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19793_dupName_312_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19795_dupName_312_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19797_dupName_312_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19797_dupName_312_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19801_dupName_313_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19803_dupName_313_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19805_dupName_313_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19805_dupName_313_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19806_dupName_313_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19808_dupName_313_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19810_dupName_313_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19810_dupName_313_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19811_dupName_313_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19813_dupName_313_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19815_dupName_313_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19815_dupName_313_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19819_dupName_314_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19821_dupName_314_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19823_dupName_314_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19823_dupName_314_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19824_dupName_314_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19826_dupName_314_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19828_dupName_314_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19828_dupName_314_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19832_dupName_315_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19834_dupName_315_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19836_dupName_315_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19836_dupName_315_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19837_dupName_315_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19839_dupName_315_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19841_dupName_315_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19841_dupName_315_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19842_dupName_315_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19844_dupName_315_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19846_dupName_315_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19846_dupName_315_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19850_dupName_316_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19852_dupName_316_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19854_dupName_316_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19854_dupName_316_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19855_dupName_316_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19857_dupName_316_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19859_dupName_316_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19859_dupName_316_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19863_dupName_317_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19865_dupName_317_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19867_dupName_317_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19867_dupName_317_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19868_dupName_317_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19870_dupName_317_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19872_dupName_317_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19872_dupName_317_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19873_dupName_317_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19875_dupName_317_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19877_dupName_317_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19877_dupName_317_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19881_dupName_318_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19883_dupName_318_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19885_dupName_318_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19885_dupName_318_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19886_dupName_318_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19888_dupName_318_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19890_dupName_318_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19890_dupName_318_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19894_dupName_319_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19896_dupName_319_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19898_dupName_319_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19898_dupName_319_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19899_dupName_319_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19901_dupName_319_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19903_dupName_319_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19903_dupName_319_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19904_dupName_319_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19906_dupName_319_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19908_dupName_319_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19908_dupName_319_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19912_dupName_320_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19914_dupName_320_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19916_dupName_320_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19916_dupName_320_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19917_dupName_320_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19919_dupName_320_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19921_dupName_320_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19921_dupName_320_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19925_dupName_321_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19927_dupName_321_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19929_dupName_321_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19929_dupName_321_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19930_dupName_321_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19932_dupName_321_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19934_dupName_321_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19934_dupName_321_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19935_dupName_321_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19937_dupName_321_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19939_dupName_321_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19939_dupName_321_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19943_dupName_322_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19945_dupName_322_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19947_dupName_322_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19947_dupName_322_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19948_dupName_322_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19950_dupName_322_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19952_dupName_322_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19952_dupName_322_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19956_dupName_323_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19958_dupName_323_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19960_dupName_323_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19960_dupName_323_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19961_dupName_323_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19963_dupName_323_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19965_dupName_323_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19965_dupName_323_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19966_dupName_323_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19968_dupName_323_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19970_dupName_323_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19970_dupName_323_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19974_dupName_324_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19976_dupName_324_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19978_dupName_324_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19978_dupName_324_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19979_dupName_324_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19981_dupName_324_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19983_dupName_324_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19983_dupName_324_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19987_dupName_325_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19989_dupName_325_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19991_dupName_325_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19991_dupName_325_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19992_dupName_325_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19994_dupName_325_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19996_dupName_325_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19996_dupName_325_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19997_dupName_325_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19999_dupName_325_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20001_dupName_325_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20001_dupName_325_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20005_dupName_326_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20007_dupName_326_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20009_dupName_326_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20009_dupName_326_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20010_dupName_326_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20012_dupName_326_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20014_dupName_326_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20014_dupName_326_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20018_dupName_327_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20020_dupName_327_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20022_dupName_327_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20022_dupName_327_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20023_dupName_327_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20025_dupName_327_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20027_dupName_327_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20027_dupName_327_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20028_dupName_327_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20030_dupName_327_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20032_dupName_327_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20032_dupName_327_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20036_dupName_328_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20038_dupName_328_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20040_dupName_328_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20040_dupName_328_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20041_dupName_328_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20043_dupName_328_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20045_dupName_328_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20045_dupName_328_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20049_dupName_329_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20051_dupName_329_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20053_dupName_329_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20053_dupName_329_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20054_dupName_329_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20056_dupName_329_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20058_dupName_329_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20058_dupName_329_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20059_dupName_329_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20061_dupName_329_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20063_dupName_329_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20063_dupName_329_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20067_dupName_330_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20069_dupName_330_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20071_dupName_330_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20071_dupName_330_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20072_dupName_330_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20074_dupName_330_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20076_dupName_330_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20076_dupName_330_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20080_dupName_331_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20082_dupName_331_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20084_dupName_331_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20084_dupName_331_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20085_dupName_331_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20087_dupName_331_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20089_dupName_331_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20089_dupName_331_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20090_dupName_331_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20092_dupName_331_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20094_dupName_331_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20094_dupName_331_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20098_dupName_332_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20100_dupName_332_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20102_dupName_332_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20102_dupName_332_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20103_dupName_332_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20105_dupName_332_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20107_dupName_332_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20107_dupName_332_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20111_dupName_333_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20113_dupName_333_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20115_dupName_333_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20115_dupName_333_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20116_dupName_333_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20118_dupName_333_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20120_dupName_333_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20120_dupName_333_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20121_dupName_333_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20123_dupName_333_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20125_dupName_333_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20125_dupName_333_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20129_dupName_334_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20131_dupName_334_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20133_dupName_334_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20133_dupName_334_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20134_dupName_334_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20136_dupName_334_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20138_dupName_334_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20138_dupName_334_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20142_dupName_335_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20144_dupName_335_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20146_dupName_335_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20146_dupName_335_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20147_dupName_335_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20149_dupName_335_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20151_dupName_335_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20151_dupName_335_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20152_dupName_335_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20154_dupName_335_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20156_dupName_335_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20156_dupName_335_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20160_dupName_336_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20162_dupName_336_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20164_dupName_336_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20164_dupName_336_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20165_dupName_336_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20167_dupName_336_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20169_dupName_336_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20169_dupName_336_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20173_dupName_337_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20175_dupName_337_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20177_dupName_337_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20177_dupName_337_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20178_dupName_337_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20180_dupName_337_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20182_dupName_337_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20182_dupName_337_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20183_dupName_337_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20185_dupName_337_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20187_dupName_337_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20187_dupName_337_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20191_dupName_338_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20193_dupName_338_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20195_dupName_338_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20195_dupName_338_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20196_dupName_338_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20198_dupName_338_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20200_dupName_338_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20200_dupName_338_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20204_dupName_339_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20206_dupName_339_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20208_dupName_339_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20208_dupName_339_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20209_dupName_339_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20211_dupName_339_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20213_dupName_339_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20213_dupName_339_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20214_dupName_339_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20216_dupName_339_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20218_dupName_339_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20218_dupName_339_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20222_dupName_340_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20224_dupName_340_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20226_dupName_340_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20226_dupName_340_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20227_dupName_340_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20229_dupName_340_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20231_dupName_340_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20231_dupName_340_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20235_dupName_341_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20237_dupName_341_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20239_dupName_341_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20239_dupName_341_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20240_dupName_341_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20242_dupName_341_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20244_dupName_341_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20244_dupName_341_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20245_dupName_341_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20247_dupName_341_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20249_dupName_341_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20249_dupName_341_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20253_dupName_342_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20255_dupName_342_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20257_dupName_342_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20257_dupName_342_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20258_dupName_342_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20260_dupName_342_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20262_dupName_342_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20262_dupName_342_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20266_dupName_343_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20268_dupName_343_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20270_dupName_343_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20270_dupName_343_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20271_dupName_343_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20273_dupName_343_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20275_dupName_343_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20275_dupName_343_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20276_dupName_343_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20278_dupName_343_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20280_dupName_343_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20280_dupName_343_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20284_dupName_344_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20286_dupName_344_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20288_dupName_344_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20288_dupName_344_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20289_dupName_344_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20291_dupName_344_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20293_dupName_344_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20293_dupName_344_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20297_dupName_345_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20299_dupName_345_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20301_dupName_345_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20301_dupName_345_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20302_dupName_345_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20304_dupName_345_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20306_dupName_345_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20306_dupName_345_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20307_dupName_345_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20309_dupName_345_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20311_dupName_345_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20311_dupName_345_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20315_dupName_346_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20317_dupName_346_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20319_dupName_346_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20319_dupName_346_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20320_dupName_346_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20322_dupName_346_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20324_dupName_346_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20324_dupName_346_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20328_dupName_347_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20330_dupName_347_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20332_dupName_347_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20332_dupName_347_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20333_dupName_347_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20335_dupName_347_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20337_dupName_347_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20337_dupName_347_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20338_dupName_347_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20340_dupName_347_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20342_dupName_347_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20342_dupName_347_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20346_dupName_348_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20348_dupName_348_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20350_dupName_348_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20350_dupName_348_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20351_dupName_348_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20353_dupName_348_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20355_dupName_348_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20355_dupName_348_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20359_dupName_349_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20361_dupName_349_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20363_dupName_349_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20363_dupName_349_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20364_dupName_349_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20366_dupName_349_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20368_dupName_349_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20368_dupName_349_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20369_dupName_349_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20371_dupName_349_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20373_dupName_349_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20373_dupName_349_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20377_dupName_350_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20379_dupName_350_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20381_dupName_350_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20381_dupName_350_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20382_dupName_350_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20384_dupName_350_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20386_dupName_350_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20386_dupName_350_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20390_dupName_351_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20392_dupName_351_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20394_dupName_351_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20394_dupName_351_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20395_dupName_351_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20397_dupName_351_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20399_dupName_351_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20399_dupName_351_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20400_dupName_351_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20402_dupName_351_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20404_dupName_351_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20404_dupName_351_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20408_dupName_352_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20410_dupName_352_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20412_dupName_352_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20412_dupName_352_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20413_dupName_352_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20415_dupName_352_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20417_dupName_352_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20417_dupName_352_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20421_dupName_353_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20423_dupName_353_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20425_dupName_353_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20425_dupName_353_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20426_dupName_353_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20428_dupName_353_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20430_dupName_353_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20430_dupName_353_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20431_dupName_353_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20433_dupName_353_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20435_dupName_353_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20435_dupName_353_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20439_dupName_354_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20441_dupName_354_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20443_dupName_354_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20443_dupName_354_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20444_dupName_354_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20446_dupName_354_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20448_dupName_354_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20448_dupName_354_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20452_dupName_355_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20454_dupName_355_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20456_dupName_355_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20456_dupName_355_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20457_dupName_355_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20459_dupName_355_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20461_dupName_355_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20461_dupName_355_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20462_dupName_355_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20464_dupName_355_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20466_dupName_355_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20466_dupName_355_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20470_dupName_356_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20472_dupName_356_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20474_dupName_356_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20474_dupName_356_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20475_dupName_356_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20477_dupName_356_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20479_dupName_356_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20479_dupName_356_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20483_dupName_357_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20485_dupName_357_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20487_dupName_357_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20487_dupName_357_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20488_dupName_357_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20490_dupName_357_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20492_dupName_357_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20492_dupName_357_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20493_dupName_357_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20495_dupName_357_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20497_dupName_357_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20497_dupName_357_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20501_dupName_358_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20503_dupName_358_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20505_dupName_358_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20505_dupName_358_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20506_dupName_358_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20508_dupName_358_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20510_dupName_358_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20510_dupName_358_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20514_dupName_359_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20516_dupName_359_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20518_dupName_359_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20518_dupName_359_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20519_dupName_359_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20521_dupName_359_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20523_dupName_359_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20523_dupName_359_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20524_dupName_359_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20526_dupName_359_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20528_dupName_359_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20528_dupName_359_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20532_dupName_360_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20534_dupName_360_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20536_dupName_360_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20536_dupName_360_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20537_dupName_360_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20539_dupName_360_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20541_dupName_360_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20541_dupName_360_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20545_dupName_361_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20547_dupName_361_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20549_dupName_361_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20549_dupName_361_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20550_dupName_361_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20552_dupName_361_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20554_dupName_361_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20554_dupName_361_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20555_dupName_361_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20557_dupName_361_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20559_dupName_361_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20559_dupName_361_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20563_dupName_362_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20565_dupName_362_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20567_dupName_362_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20567_dupName_362_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20568_dupName_362_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20570_dupName_362_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20572_dupName_362_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20572_dupName_362_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20576_dupName_363_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20578_dupName_363_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20580_dupName_363_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20580_dupName_363_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20581_dupName_363_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20583_dupName_363_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20585_dupName_363_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20585_dupName_363_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20586_dupName_363_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20588_dupName_363_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20590_dupName_363_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20590_dupName_363_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20594_dupName_364_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20596_dupName_364_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20598_dupName_364_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20598_dupName_364_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20599_dupName_364_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20601_dupName_364_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20603_dupName_364_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20603_dupName_364_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20607_dupName_365_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20609_dupName_365_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20611_dupName_365_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20611_dupName_365_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20612_dupName_365_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20614_dupName_365_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20616_dupName_365_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20616_dupName_365_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20617_dupName_365_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20619_dupName_365_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20621_dupName_365_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20621_dupName_365_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20625_dupName_366_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20627_dupName_366_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20629_dupName_366_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20629_dupName_366_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20630_dupName_366_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20632_dupName_366_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20634_dupName_366_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20634_dupName_366_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20638_dupName_367_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20640_dupName_367_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20642_dupName_367_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20642_dupName_367_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20643_dupName_367_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20645_dupName_367_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20647_dupName_367_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20647_dupName_367_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20648_dupName_367_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20650_dupName_367_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20652_dupName_367_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20652_dupName_367_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20656_dupName_368_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20658_dupName_368_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20660_dupName_368_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20660_dupName_368_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20661_dupName_368_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20663_dupName_368_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20665_dupName_368_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20665_dupName_368_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20669_dupName_369_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20671_dupName_369_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20673_dupName_369_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20673_dupName_369_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20674_dupName_369_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20676_dupName_369_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20678_dupName_369_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20678_dupName_369_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20679_dupName_369_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20681_dupName_369_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20683_dupName_369_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20683_dupName_369_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20687_dupName_370_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20689_dupName_370_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20691_dupName_370_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20691_dupName_370_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20692_dupName_370_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20694_dupName_370_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20696_dupName_370_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20696_dupName_370_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20700_dupName_371_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20702_dupName_371_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20704_dupName_371_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20704_dupName_371_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20705_dupName_371_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20707_dupName_371_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20709_dupName_371_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20709_dupName_371_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20710_dupName_371_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20712_dupName_371_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20714_dupName_371_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20714_dupName_371_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20718_dupName_372_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20720_dupName_372_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20722_dupName_372_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20722_dupName_372_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20723_dupName_372_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20725_dupName_372_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20727_dupName_372_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20727_dupName_372_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20731_dupName_373_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20733_dupName_373_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20735_dupName_373_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20735_dupName_373_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20736_dupName_373_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20738_dupName_373_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20740_dupName_373_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20740_dupName_373_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20741_dupName_373_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20743_dupName_373_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20745_dupName_373_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20745_dupName_373_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20749_dupName_374_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20751_dupName_374_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20753_dupName_374_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20753_dupName_374_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20754_dupName_374_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20756_dupName_374_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20758_dupName_374_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20758_dupName_374_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20762_dupName_375_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20764_dupName_375_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20766_dupName_375_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20766_dupName_375_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20767_dupName_375_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20769_dupName_375_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20771_dupName_375_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20771_dupName_375_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20772_dupName_375_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20774_dupName_375_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20776_dupName_375_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20776_dupName_375_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20780_dupName_376_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20782_dupName_376_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20784_dupName_376_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20784_dupName_376_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20785_dupName_376_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20787_dupName_376_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20789_dupName_376_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20789_dupName_376_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20793_dupName_377_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20795_dupName_377_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20797_dupName_377_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20797_dupName_377_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20798_dupName_377_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20800_dupName_377_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20802_dupName_377_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20802_dupName_377_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20803_dupName_377_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20805_dupName_377_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20807_dupName_377_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20807_dupName_377_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20811_dupName_378_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20813_dupName_378_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20815_dupName_378_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20815_dupName_378_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20816_dupName_378_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20818_dupName_378_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20820_dupName_378_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20820_dupName_378_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20824_dupName_379_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20826_dupName_379_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20828_dupName_379_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20828_dupName_379_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20829_dupName_379_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20831_dupName_379_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20833_dupName_379_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20833_dupName_379_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20834_dupName_379_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20836_dupName_379_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20838_dupName_379_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20838_dupName_379_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20842_dupName_380_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20844_dupName_380_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20846_dupName_380_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20846_dupName_380_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20847_dupName_380_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20849_dupName_380_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20851_dupName_380_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20851_dupName_380_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20855_dupName_381_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20857_dupName_381_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20859_dupName_381_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20859_dupName_381_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20860_dupName_381_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20862_dupName_381_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20864_dupName_381_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20864_dupName_381_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20865_dupName_381_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20867_dupName_381_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20869_dupName_381_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20869_dupName_381_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20873_dupName_382_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20875_dupName_382_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20877_dupName_382_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20877_dupName_382_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20878_dupName_382_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20880_dupName_382_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20882_dupName_382_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20882_dupName_382_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20886_dupName_383_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20888_dupName_383_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20890_dupName_383_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20890_dupName_383_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20891_dupName_383_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20893_dupName_383_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20895_dupName_383_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20895_dupName_383_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20896_dupName_383_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20898_dupName_383_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20900_dupName_383_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20900_dupName_383_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20904_dupName_384_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20906_dupName_384_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20908_dupName_384_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20908_dupName_384_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20909_dupName_384_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20911_dupName_384_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20913_dupName_384_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20913_dupName_384_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20917_dupName_385_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20919_dupName_385_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20921_dupName_385_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20921_dupName_385_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20922_dupName_385_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20924_dupName_385_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20926_dupName_385_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20926_dupName_385_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20927_dupName_385_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20929_dupName_385_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20931_dupName_385_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20931_dupName_385_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20935_dupName_386_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20937_dupName_386_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20939_dupName_386_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20939_dupName_386_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20940_dupName_386_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20942_dupName_386_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20944_dupName_386_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20944_dupName_386_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20948_dupName_387_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20950_dupName_387_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20952_dupName_387_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20952_dupName_387_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20953_dupName_387_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20955_dupName_387_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20957_dupName_387_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20957_dupName_387_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20958_dupName_387_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20960_dupName_387_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20962_dupName_387_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20962_dupName_387_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20966_dupName_388_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20968_dupName_388_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20970_dupName_388_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20970_dupName_388_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20971_dupName_388_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20973_dupName_388_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20975_dupName_388_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20975_dupName_388_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20979_dupName_389_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20981_dupName_389_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20983_dupName_389_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20983_dupName_389_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20984_dupName_389_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20986_dupName_389_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20988_dupName_389_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20988_dupName_389_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20989_dupName_389_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20991_dupName_389_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20993_dupName_389_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20993_dupName_389_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20997_dupName_390_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20999_dupName_390_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21001_dupName_390_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21001_dupName_390_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21002_dupName_390_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21004_dupName_390_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21006_dupName_390_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21006_dupName_390_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21010_dupName_391_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21012_dupName_391_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21014_dupName_391_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21014_dupName_391_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21015_dupName_391_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21017_dupName_391_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21019_dupName_391_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21019_dupName_391_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21020_dupName_391_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21022_dupName_391_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21024_dupName_391_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21024_dupName_391_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21028_dupName_392_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21030_dupName_392_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21032_dupName_392_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21032_dupName_392_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21033_dupName_392_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21035_dupName_392_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21037_dupName_392_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21037_dupName_392_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21041_dupName_393_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21043_dupName_393_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21045_dupName_393_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21045_dupName_393_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21046_dupName_393_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21048_dupName_393_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21050_dupName_393_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21050_dupName_393_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21051_dupName_393_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21053_dupName_393_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21055_dupName_393_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21055_dupName_393_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21059_dupName_394_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21061_dupName_394_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21063_dupName_394_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21063_dupName_394_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21064_dupName_394_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21066_dupName_394_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21068_dupName_394_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21068_dupName_394_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21072_dupName_395_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21074_dupName_395_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21076_dupName_395_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21076_dupName_395_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21077_dupName_395_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21079_dupName_395_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21081_dupName_395_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21081_dupName_395_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21082_dupName_395_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21084_dupName_395_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21086_dupName_395_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21086_dupName_395_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21090_dupName_396_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21092_dupName_396_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21094_dupName_396_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21094_dupName_396_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21095_dupName_396_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21097_dupName_396_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21099_dupName_396_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21099_dupName_396_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21103_dupName_397_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21105_dupName_397_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21107_dupName_397_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21107_dupName_397_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21108_dupName_397_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21110_dupName_397_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21112_dupName_397_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21112_dupName_397_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21113_dupName_397_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21115_dupName_397_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21117_dupName_397_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21117_dupName_397_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21121_dupName_398_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21123_dupName_398_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21125_dupName_398_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21125_dupName_398_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21126_dupName_398_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21128_dupName_398_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21130_dupName_398_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21130_dupName_398_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21134_dupName_399_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21136_dupName_399_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21138_dupName_399_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21138_dupName_399_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21139_dupName_399_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21141_dupName_399_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21143_dupName_399_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21143_dupName_399_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21144_dupName_399_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21146_dupName_399_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21148_dupName_399_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21148_dupName_399_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21152_dupName_400_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21154_dupName_400_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21156_dupName_400_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21156_dupName_400_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21157_dupName_400_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21159_dupName_400_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21161_dupName_400_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21161_dupName_400_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21165_dupName_401_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21167_dupName_401_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21169_dupName_401_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21169_dupName_401_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21170_dupName_401_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21172_dupName_401_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21174_dupName_401_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21174_dupName_401_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21175_dupName_401_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21177_dupName_401_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21179_dupName_401_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21179_dupName_401_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21183_dupName_402_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21185_dupName_402_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21187_dupName_402_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21187_dupName_402_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21188_dupName_402_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21190_dupName_402_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21192_dupName_402_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21192_dupName_402_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21196_dupName_403_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21198_dupName_403_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21200_dupName_403_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21200_dupName_403_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21201_dupName_403_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21203_dupName_403_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21205_dupName_403_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21205_dupName_403_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21206_dupName_403_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21208_dupName_403_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21210_dupName_403_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21210_dupName_403_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21214_dupName_404_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21216_dupName_404_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21218_dupName_404_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21218_dupName_404_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21219_dupName_404_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21221_dupName_404_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21223_dupName_404_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21223_dupName_404_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21227_dupName_405_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21229_dupName_405_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21231_dupName_405_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21231_dupName_405_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21232_dupName_405_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21234_dupName_405_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21236_dupName_405_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21236_dupName_405_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21237_dupName_405_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21239_dupName_405_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21241_dupName_405_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21241_dupName_405_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21245_dupName_406_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21247_dupName_406_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21249_dupName_406_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21249_dupName_406_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21250_dupName_406_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21252_dupName_406_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21254_dupName_406_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21254_dupName_406_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21258_dupName_407_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21260_dupName_407_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21262_dupName_407_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21262_dupName_407_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21263_dupName_407_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21265_dupName_407_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21267_dupName_407_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21267_dupName_407_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21268_dupName_407_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21270_dupName_407_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21272_dupName_407_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21272_dupName_407_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21276_dupName_408_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21278_dupName_408_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21280_dupName_408_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21280_dupName_408_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21281_dupName_408_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21283_dupName_408_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21285_dupName_408_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21285_dupName_408_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21289_dupName_409_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21291_dupName_409_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21293_dupName_409_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21293_dupName_409_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21294_dupName_409_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21296_dupName_409_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21298_dupName_409_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21298_dupName_409_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21299_dupName_409_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21301_dupName_409_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21303_dupName_409_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21303_dupName_409_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21307_dupName_410_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21309_dupName_410_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21311_dupName_410_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21311_dupName_410_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21312_dupName_410_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21314_dupName_410_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21316_dupName_410_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21316_dupName_410_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21320_dupName_411_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21322_dupName_411_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21324_dupName_411_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21324_dupName_411_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21325_dupName_411_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21327_dupName_411_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21329_dupName_411_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21329_dupName_411_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21330_dupName_411_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21332_dupName_411_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21334_dupName_411_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21334_dupName_411_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21338_dupName_412_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21340_dupName_412_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21342_dupName_412_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21342_dupName_412_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21343_dupName_412_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21345_dupName_412_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21347_dupName_412_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21347_dupName_412_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21351_dupName_413_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21353_dupName_413_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21355_dupName_413_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21355_dupName_413_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21356_dupName_413_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21358_dupName_413_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21360_dupName_413_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21360_dupName_413_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21361_dupName_413_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21363_dupName_413_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21365_dupName_413_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21365_dupName_413_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21369_dupName_414_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21371_dupName_414_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21373_dupName_414_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21373_dupName_414_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21374_dupName_414_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21376_dupName_414_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21378_dupName_414_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21378_dupName_414_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21382_dupName_415_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21384_dupName_415_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21386_dupName_415_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21386_dupName_415_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21387_dupName_415_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21389_dupName_415_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21391_dupName_415_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21391_dupName_415_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21392_dupName_415_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21394_dupName_415_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21396_dupName_415_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21396_dupName_415_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21400_dupName_416_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21402_dupName_416_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21404_dupName_416_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21404_dupName_416_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21405_dupName_416_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21407_dupName_416_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21409_dupName_416_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21409_dupName_416_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21413_dupName_417_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21415_dupName_417_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21417_dupName_417_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21417_dupName_417_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21418_dupName_417_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21420_dupName_417_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21422_dupName_417_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21422_dupName_417_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21423_dupName_417_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21425_dupName_417_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21427_dupName_417_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21427_dupName_417_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21431_dupName_418_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21433_dupName_418_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21435_dupName_418_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21435_dupName_418_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21436_dupName_418_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21438_dupName_418_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21440_dupName_418_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21440_dupName_418_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21444_dupName_419_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21446_dupName_419_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21448_dupName_419_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21448_dupName_419_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21449_dupName_419_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21451_dupName_419_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21453_dupName_419_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21453_dupName_419_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21454_dupName_419_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21456_dupName_419_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21458_dupName_419_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21458_dupName_419_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21462_dupName_420_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21464_dupName_420_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21466_dupName_420_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21466_dupName_420_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21467_dupName_420_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21469_dupName_420_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21471_dupName_420_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21471_dupName_420_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21475_dupName_421_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21477_dupName_421_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21479_dupName_421_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21479_dupName_421_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21480_dupName_421_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21482_dupName_421_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21484_dupName_421_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21484_dupName_421_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21485_dupName_421_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21487_dupName_421_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21489_dupName_421_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21489_dupName_421_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21493_dupName_422_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21495_dupName_422_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21497_dupName_422_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21497_dupName_422_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21498_dupName_422_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21500_dupName_422_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21502_dupName_422_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21502_dupName_422_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21506_dupName_423_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21508_dupName_423_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21510_dupName_423_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21510_dupName_423_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21511_dupName_423_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21513_dupName_423_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21515_dupName_423_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21515_dupName_423_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21516_dupName_423_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21518_dupName_423_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21520_dupName_423_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21520_dupName_423_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21524_dupName_424_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21526_dupName_424_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21528_dupName_424_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21528_dupName_424_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21529_dupName_424_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21531_dupName_424_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21533_dupName_424_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21533_dupName_424_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21537_dupName_425_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21539_dupName_425_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21541_dupName_425_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21541_dupName_425_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21542_dupName_425_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21544_dupName_425_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21546_dupName_425_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21546_dupName_425_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21547_dupName_425_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21549_dupName_425_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21551_dupName_425_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21551_dupName_425_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21555_dupName_426_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21557_dupName_426_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21559_dupName_426_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21559_dupName_426_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21560_dupName_426_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21562_dupName_426_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21564_dupName_426_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21564_dupName_426_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21568_dupName_427_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21570_dupName_427_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21572_dupName_427_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21572_dupName_427_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21573_dupName_427_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21575_dupName_427_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21577_dupName_427_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21577_dupName_427_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21578_dupName_427_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21580_dupName_427_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21582_dupName_427_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21582_dupName_427_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21586_dupName_428_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21588_dupName_428_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21590_dupName_428_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21590_dupName_428_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21591_dupName_428_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21593_dupName_428_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21595_dupName_428_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21595_dupName_428_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21599_dupName_429_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21601_dupName_429_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21603_dupName_429_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21603_dupName_429_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21604_dupName_429_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21606_dupName_429_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21608_dupName_429_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21608_dupName_429_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21609_dupName_429_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21611_dupName_429_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21613_dupName_429_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21613_dupName_429_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21617_dupName_430_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21619_dupName_430_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21621_dupName_430_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21621_dupName_430_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21622_dupName_430_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21624_dupName_430_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21626_dupName_430_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21626_dupName_430_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21630_dupName_431_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21632_dupName_431_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21634_dupName_431_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21634_dupName_431_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21635_dupName_431_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21637_dupName_431_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21639_dupName_431_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21639_dupName_431_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21640_dupName_431_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21642_dupName_431_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21644_dupName_431_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21644_dupName_431_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21648_dupName_432_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21650_dupName_432_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21652_dupName_432_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21652_dupName_432_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21653_dupName_432_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21655_dupName_432_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21657_dupName_432_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21657_dupName_432_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21661_dupName_433_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21663_dupName_433_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21665_dupName_433_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21665_dupName_433_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21666_dupName_433_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21668_dupName_433_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21670_dupName_433_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21670_dupName_433_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21671_dupName_433_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21673_dupName_433_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21675_dupName_433_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21675_dupName_433_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21679_dupName_434_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21681_dupName_434_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21683_dupName_434_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21683_dupName_434_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21684_dupName_434_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21686_dupName_434_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21688_dupName_434_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21688_dupName_434_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21692_dupName_435_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21694_dupName_435_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21696_dupName_435_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21696_dupName_435_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21697_dupName_435_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21699_dupName_435_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21701_dupName_435_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21701_dupName_435_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21702_dupName_435_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21704_dupName_435_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21706_dupName_435_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21706_dupName_435_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21710_dupName_436_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21712_dupName_436_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21714_dupName_436_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21714_dupName_436_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21715_dupName_436_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21717_dupName_436_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21719_dupName_436_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21719_dupName_436_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21723_dupName_437_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21725_dupName_437_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21727_dupName_437_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21727_dupName_437_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21728_dupName_437_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21730_dupName_437_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21732_dupName_437_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21732_dupName_437_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21733_dupName_437_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21735_dupName_437_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21737_dupName_437_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21737_dupName_437_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21741_dupName_438_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21743_dupName_438_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21745_dupName_438_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21745_dupName_438_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21746_dupName_438_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21748_dupName_438_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21750_dupName_438_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21750_dupName_438_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21754_dupName_439_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21756_dupName_439_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21758_dupName_439_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21758_dupName_439_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21759_dupName_439_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21761_dupName_439_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21763_dupName_439_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21763_dupName_439_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21764_dupName_439_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21766_dupName_439_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21768_dupName_439_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21768_dupName_439_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21772_dupName_440_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21774_dupName_440_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21776_dupName_440_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21776_dupName_440_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21777_dupName_440_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21779_dupName_440_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21781_dupName_440_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21781_dupName_440_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21785_dupName_441_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21787_dupName_441_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21789_dupName_441_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21789_dupName_441_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21790_dupName_441_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21792_dupName_441_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21794_dupName_441_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21794_dupName_441_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21795_dupName_441_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21797_dupName_441_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21799_dupName_441_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21799_dupName_441_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21803_dupName_442_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21805_dupName_442_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21807_dupName_442_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21807_dupName_442_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21808_dupName_442_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21810_dupName_442_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21812_dupName_442_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21812_dupName_442_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21816_dupName_443_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21818_dupName_443_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21820_dupName_443_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21820_dupName_443_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21821_dupName_443_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21823_dupName_443_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21825_dupName_443_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21825_dupName_443_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21826_dupName_443_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21828_dupName_443_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21830_dupName_443_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21830_dupName_443_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21834_dupName_444_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21836_dupName_444_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21838_dupName_444_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21838_dupName_444_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21839_dupName_444_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21841_dupName_444_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21843_dupName_444_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21843_dupName_444_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21847_dupName_445_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21849_dupName_445_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21851_dupName_445_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21851_dupName_445_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21852_dupName_445_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21854_dupName_445_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21856_dupName_445_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21856_dupName_445_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21857_dupName_445_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21859_dupName_445_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21861_dupName_445_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21861_dupName_445_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21865_dupName_446_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21867_dupName_446_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21869_dupName_446_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21869_dupName_446_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21870_dupName_446_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21872_dupName_446_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21874_dupName_446_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21874_dupName_446_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21878_dupName_447_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21880_dupName_447_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21882_dupName_447_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21882_dupName_447_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21883_dupName_447_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21885_dupName_447_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21887_dupName_447_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21887_dupName_447_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21888_dupName_447_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21890_dupName_447_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21892_dupName_447_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21892_dupName_447_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21896_dupName_448_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21898_dupName_448_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21900_dupName_448_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21900_dupName_448_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21901_dupName_448_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21903_dupName_448_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21905_dupName_448_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21905_dupName_448_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21909_dupName_449_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21911_dupName_449_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21913_dupName_449_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21913_dupName_449_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21914_dupName_449_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21916_dupName_449_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21918_dupName_449_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21918_dupName_449_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21919_dupName_449_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21921_dupName_449_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21923_dupName_449_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21923_dupName_449_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21927_dupName_450_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21929_dupName_450_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21931_dupName_450_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21931_dupName_450_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21932_dupName_450_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21934_dupName_450_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21936_dupName_450_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21936_dupName_450_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21940_dupName_451_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21942_dupName_451_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21944_dupName_451_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21944_dupName_451_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21945_dupName_451_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21947_dupName_451_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21949_dupName_451_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21949_dupName_451_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21950_dupName_451_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21952_dupName_451_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21954_dupName_451_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21954_dupName_451_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21958_dupName_452_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21960_dupName_452_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21962_dupName_452_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21962_dupName_452_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21963_dupName_452_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21965_dupName_452_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21967_dupName_452_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21967_dupName_452_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21971_dupName_453_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21973_dupName_453_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21975_dupName_453_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21975_dupName_453_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21976_dupName_453_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21978_dupName_453_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21980_dupName_453_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21980_dupName_453_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21981_dupName_453_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21983_dupName_453_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21985_dupName_453_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21985_dupName_453_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21989_dupName_454_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21991_dupName_454_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21993_dupName_454_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21993_dupName_454_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21994_dupName_454_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21996_dupName_454_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21998_dupName_454_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21998_dupName_454_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22002_dupName_455_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22004_dupName_455_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22006_dupName_455_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22006_dupName_455_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22007_dupName_455_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22009_dupName_455_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22011_dupName_455_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22011_dupName_455_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22012_dupName_455_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22014_dupName_455_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22016_dupName_455_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22016_dupName_455_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22020_dupName_456_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22022_dupName_456_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22024_dupName_456_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22024_dupName_456_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22025_dupName_456_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22027_dupName_456_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22029_dupName_456_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22029_dupName_456_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22033_dupName_457_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22035_dupName_457_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22037_dupName_457_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22037_dupName_457_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22038_dupName_457_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22040_dupName_457_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22042_dupName_457_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22042_dupName_457_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22043_dupName_457_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22045_dupName_457_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22047_dupName_457_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22047_dupName_457_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22051_dupName_458_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22053_dupName_458_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22055_dupName_458_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22055_dupName_458_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22056_dupName_458_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22058_dupName_458_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22060_dupName_458_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22060_dupName_458_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22064_dupName_459_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22066_dupName_459_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22068_dupName_459_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22068_dupName_459_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22069_dupName_459_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22071_dupName_459_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22073_dupName_459_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22073_dupName_459_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22074_dupName_459_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22076_dupName_459_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22078_dupName_459_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22078_dupName_459_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22082_dupName_460_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22084_dupName_460_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22086_dupName_460_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22086_dupName_460_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22087_dupName_460_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22089_dupName_460_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22091_dupName_460_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22091_dupName_460_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22095_dupName_461_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22097_dupName_461_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22099_dupName_461_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22099_dupName_461_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22100_dupName_461_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22102_dupName_461_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22104_dupName_461_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22104_dupName_461_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22105_dupName_461_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22107_dupName_461_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22109_dupName_461_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22109_dupName_461_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22113_dupName_462_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22115_dupName_462_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22117_dupName_462_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22117_dupName_462_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22118_dupName_462_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22120_dupName_462_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22122_dupName_462_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22122_dupName_462_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22126_dupName_463_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22128_dupName_463_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22130_dupName_463_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22130_dupName_463_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22131_dupName_463_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22133_dupName_463_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22135_dupName_463_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22135_dupName_463_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22136_dupName_463_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22138_dupName_463_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22140_dupName_463_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22140_dupName_463_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22144_dupName_464_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22146_dupName_464_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22148_dupName_464_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22148_dupName_464_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22149_dupName_464_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22151_dupName_464_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22153_dupName_464_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22153_dupName_464_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22157_dupName_465_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22159_dupName_465_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22161_dupName_465_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22161_dupName_465_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22162_dupName_465_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22164_dupName_465_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22166_dupName_465_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22166_dupName_465_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22167_dupName_465_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22169_dupName_465_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22171_dupName_465_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22171_dupName_465_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22175_dupName_466_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22177_dupName_466_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22179_dupName_466_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22179_dupName_466_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22180_dupName_466_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22182_dupName_466_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22184_dupName_466_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22184_dupName_466_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22188_dupName_467_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22190_dupName_467_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22192_dupName_467_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22192_dupName_467_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22193_dupName_467_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22195_dupName_467_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22197_dupName_467_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22197_dupName_467_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22198_dupName_467_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22200_dupName_467_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22202_dupName_467_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22202_dupName_467_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22206_dupName_468_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22208_dupName_468_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22210_dupName_468_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22210_dupName_468_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22211_dupName_468_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22213_dupName_468_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22215_dupName_468_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22215_dupName_468_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22219_dupName_469_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22221_dupName_469_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22223_dupName_469_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22223_dupName_469_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22224_dupName_469_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22226_dupName_469_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22228_dupName_469_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22228_dupName_469_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22229_dupName_469_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22231_dupName_469_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22233_dupName_469_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22233_dupName_469_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22237_dupName_470_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22239_dupName_470_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22241_dupName_470_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22241_dupName_470_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22242_dupName_470_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22244_dupName_470_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22246_dupName_470_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22246_dupName_470_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22250_dupName_471_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22252_dupName_471_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22254_dupName_471_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22254_dupName_471_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22255_dupName_471_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22257_dupName_471_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22259_dupName_471_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22259_dupName_471_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22260_dupName_471_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22262_dupName_471_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22264_dupName_471_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22264_dupName_471_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22268_dupName_472_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22270_dupName_472_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22272_dupName_472_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22272_dupName_472_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22273_dupName_472_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22275_dupName_472_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22277_dupName_472_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22277_dupName_472_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22281_dupName_473_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22283_dupName_473_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22285_dupName_473_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22285_dupName_473_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22286_dupName_473_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22288_dupName_473_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22290_dupName_473_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22290_dupName_473_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22291_dupName_473_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22293_dupName_473_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22295_dupName_473_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22295_dupName_473_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22299_dupName_474_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22301_dupName_474_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22303_dupName_474_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22303_dupName_474_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22304_dupName_474_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22306_dupName_474_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22308_dupName_474_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22308_dupName_474_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22312_dupName_475_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22314_dupName_475_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22316_dupName_475_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22316_dupName_475_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22317_dupName_475_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22319_dupName_475_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22321_dupName_475_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22321_dupName_475_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22322_dupName_475_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22324_dupName_475_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22326_dupName_475_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22326_dupName_475_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22330_dupName_476_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22332_dupName_476_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22334_dupName_476_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22334_dupName_476_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22335_dupName_476_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22337_dupName_476_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22339_dupName_476_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22339_dupName_476_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22343_dupName_477_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22345_dupName_477_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22347_dupName_477_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22347_dupName_477_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22348_dupName_477_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22350_dupName_477_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22352_dupName_477_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22352_dupName_477_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22353_dupName_477_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22355_dupName_477_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22357_dupName_477_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22357_dupName_477_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22361_dupName_478_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22363_dupName_478_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22365_dupName_478_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22365_dupName_478_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22366_dupName_478_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22368_dupName_478_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22370_dupName_478_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22370_dupName_478_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22374_dupName_479_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22376_dupName_479_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22378_dupName_479_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22378_dupName_479_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22379_dupName_479_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22381_dupName_479_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22383_dupName_479_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22383_dupName_479_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22384_dupName_479_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22386_dupName_479_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22388_dupName_479_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22388_dupName_479_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22392_dupName_480_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22394_dupName_480_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22396_dupName_480_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22396_dupName_480_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22397_dupName_480_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22399_dupName_480_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22401_dupName_480_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22401_dupName_480_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22405_dupName_481_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22407_dupName_481_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22409_dupName_481_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22409_dupName_481_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22410_dupName_481_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22412_dupName_481_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22414_dupName_481_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22414_dupName_481_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22415_dupName_481_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22417_dupName_481_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22419_dupName_481_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22419_dupName_481_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22423_dupName_482_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22425_dupName_482_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22427_dupName_482_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22427_dupName_482_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22428_dupName_482_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22430_dupName_482_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22432_dupName_482_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22432_dupName_482_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22436_dupName_483_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22438_dupName_483_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22440_dupName_483_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22440_dupName_483_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22441_dupName_483_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22443_dupName_483_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22445_dupName_483_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22445_dupName_483_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22446_dupName_483_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22448_dupName_483_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22450_dupName_483_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22450_dupName_483_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22454_dupName_484_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22456_dupName_484_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22458_dupName_484_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22458_dupName_484_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22459_dupName_484_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22461_dupName_484_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22463_dupName_484_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22463_dupName_484_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22467_dupName_485_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22469_dupName_485_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22471_dupName_485_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22471_dupName_485_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22472_dupName_485_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22474_dupName_485_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22476_dupName_485_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22476_dupName_485_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22477_dupName_485_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22479_dupName_485_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22481_dupName_485_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22481_dupName_485_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22485_dupName_486_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22487_dupName_486_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22489_dupName_486_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22489_dupName_486_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22490_dupName_486_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22492_dupName_486_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22494_dupName_486_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22494_dupName_486_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22498_dupName_487_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22500_dupName_487_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22502_dupName_487_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22502_dupName_487_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22503_dupName_487_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22505_dupName_487_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22507_dupName_487_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22507_dupName_487_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22508_dupName_487_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22510_dupName_487_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22512_dupName_487_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22512_dupName_487_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22516_dupName_488_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22518_dupName_488_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22520_dupName_488_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22520_dupName_488_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22521_dupName_488_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22523_dupName_488_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22525_dupName_488_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22525_dupName_488_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22529_dupName_489_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22531_dupName_489_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22533_dupName_489_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22533_dupName_489_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22534_dupName_489_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22536_dupName_489_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22538_dupName_489_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22538_dupName_489_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22539_dupName_489_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22541_dupName_489_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22543_dupName_489_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22543_dupName_489_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22547_dupName_490_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22549_dupName_490_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22551_dupName_490_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22551_dupName_490_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22552_dupName_490_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22554_dupName_490_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22556_dupName_490_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22556_dupName_490_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22560_dupName_491_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22562_dupName_491_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22564_dupName_491_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22564_dupName_491_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22565_dupName_491_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22567_dupName_491_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22569_dupName_491_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22569_dupName_491_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22570_dupName_491_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22572_dupName_491_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22574_dupName_491_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22574_dupName_491_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22578_dupName_492_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22580_dupName_492_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22582_dupName_492_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22582_dupName_492_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22583_dupName_492_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22585_dupName_492_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22587_dupName_492_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22587_dupName_492_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22591_dupName_493_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22593_dupName_493_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22595_dupName_493_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22595_dupName_493_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22596_dupName_493_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22598_dupName_493_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22600_dupName_493_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22600_dupName_493_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22601_dupName_493_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22603_dupName_493_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22605_dupName_493_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22605_dupName_493_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22609_dupName_494_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22611_dupName_494_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22613_dupName_494_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22613_dupName_494_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22614_dupName_494_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22616_dupName_494_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22618_dupName_494_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22618_dupName_494_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22622_dupName_495_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22624_dupName_495_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22626_dupName_495_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22626_dupName_495_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22627_dupName_495_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22629_dupName_495_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22631_dupName_495_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22631_dupName_495_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22632_dupName_495_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22634_dupName_495_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22636_dupName_495_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22636_dupName_495_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22640_dupName_496_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22642_dupName_496_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22644_dupName_496_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22644_dupName_496_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22645_dupName_496_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22647_dupName_496_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22649_dupName_496_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22649_dupName_496_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22653_dupName_497_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22655_dupName_497_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22657_dupName_497_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22657_dupName_497_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22658_dupName_497_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22660_dupName_497_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22662_dupName_497_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22662_dupName_497_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22663_dupName_497_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22665_dupName_497_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22667_dupName_497_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22667_dupName_497_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22671_dupName_498_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22673_dupName_498_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22675_dupName_498_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22675_dupName_498_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22676_dupName_498_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22678_dupName_498_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22680_dupName_498_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22680_dupName_498_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22684_dupName_499_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22686_dupName_499_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22688_dupName_499_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22688_dupName_499_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22689_dupName_499_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22691_dupName_499_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22693_dupName_499_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22693_dupName_499_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22694_dupName_499_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22696_dupName_499_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22698_dupName_499_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22698_dupName_499_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22702_dupName_500_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22704_dupName_500_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22706_dupName_500_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22706_dupName_500_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22707_dupName_500_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22709_dupName_500_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22711_dupName_500_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22711_dupName_500_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22715_dupName_501_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22717_dupName_501_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22719_dupName_501_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22719_dupName_501_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22720_dupName_501_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22722_dupName_501_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22724_dupName_501_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22724_dupName_501_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22725_dupName_501_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22727_dupName_501_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22729_dupName_501_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22729_dupName_501_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22733_dupName_502_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22735_dupName_502_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22737_dupName_502_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22737_dupName_502_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22738_dupName_502_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22740_dupName_502_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22742_dupName_502_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22742_dupName_502_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22746_dupName_503_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22748_dupName_503_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22750_dupName_503_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22750_dupName_503_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22751_dupName_503_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22753_dupName_503_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22755_dupName_503_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22755_dupName_503_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22756_dupName_503_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22758_dupName_503_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22760_dupName_503_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22760_dupName_503_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22764_dupName_504_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22766_dupName_504_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22768_dupName_504_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22768_dupName_504_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22769_dupName_504_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22771_dupName_504_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22773_dupName_504_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22773_dupName_504_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22777_dupName_505_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22779_dupName_505_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22781_dupName_505_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22781_dupName_505_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22782_dupName_505_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22784_dupName_505_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22786_dupName_505_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22786_dupName_505_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22787_dupName_505_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22789_dupName_505_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22791_dupName_505_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22791_dupName_505_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22795_dupName_506_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22797_dupName_506_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22799_dupName_506_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22799_dupName_506_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22800_dupName_506_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22802_dupName_506_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22804_dupName_506_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22804_dupName_506_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22808_dupName_507_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22810_dupName_507_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22812_dupName_507_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22812_dupName_507_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22813_dupName_507_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22815_dupName_507_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22817_dupName_507_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22817_dupName_507_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22818_dupName_507_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22820_dupName_507_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22822_dupName_507_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22822_dupName_507_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22826_dupName_508_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22828_dupName_508_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22830_dupName_508_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22830_dupName_508_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22831_dupName_508_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22833_dupName_508_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22835_dupName_508_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22835_dupName_508_i_unnamed_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22839_dupName_509_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22841_dupName_509_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22843_dupName_509_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22843_dupName_509_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22844_dupName_509_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22846_dupName_509_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22848_dupName_509_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22848_dupName_509_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22849_dupName_509_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22851_dupName_509_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22853_dupName_509_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22853_dupName_509_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22857_dupName_510_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22859_dupName_510_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22861_dupName_510_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22861_dupName_510_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22862_dupName_510_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22864_dupName_510_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22866_dupName_510_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22866_dupName_510_i_unnamed_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22871_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22871_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid22872_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid22874_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid22874_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid22876_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid22876_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid22877_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid22879_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid22879_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid22881_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid22881_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid22882_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid22884_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid22884_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22889_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22889_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid22890_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid22892_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid22892_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid22894_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid22894_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid22895_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid22897_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid22897_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid22899_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid22899_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid22900_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid22902_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid22902_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22907_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22907_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid22908_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid22910_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid22910_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid22912_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid22912_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid22913_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid22915_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid22915_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid22917_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid22917_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid22918_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid22920_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid22920_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22925_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22925_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid22926_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid22928_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid22928_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid22930_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid22930_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid22931_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid22933_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid22933_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid22935_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid22935_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid22936_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid22938_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid22938_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22943_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22943_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid22944_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid22946_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid22946_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid22948_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid22948_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid22949_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid22951_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid22951_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid22953_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid22953_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid22954_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid22956_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid22956_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22961_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22961_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid22962_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid22964_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid22964_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid22966_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid22966_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid22967_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid22969_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid22969_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid22971_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid22971_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid22972_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid22974_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid22974_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22979_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22979_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid22980_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid22982_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid22982_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid22984_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid22984_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid22985_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid22987_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid22987_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid22989_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid22989_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid22990_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid22992_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid22992_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22997_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid22997_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid22998_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23000_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23000_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23002_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23002_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23003_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23005_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23005_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23007_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23007_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23008_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23010_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23010_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23015_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23015_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23016_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23018_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23018_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23020_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23020_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23021_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23023_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23023_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23025_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23025_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23026_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23028_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23028_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23033_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23033_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23034_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23036_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23036_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23038_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23038_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23039_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23041_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23041_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23043_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23043_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23044_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23046_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23046_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23051_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23051_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23052_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23054_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23054_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23056_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23056_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23057_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23059_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23059_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23061_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23061_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23062_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23064_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23064_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23069_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23069_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23070_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23072_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23072_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23074_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23074_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23075_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23077_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23077_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23079_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23079_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23080_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23082_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23082_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23087_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23087_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23088_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23090_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23090_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23092_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23092_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23093_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23095_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23095_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23097_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23097_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23098_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23100_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23100_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23105_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23105_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23106_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23108_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23108_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23110_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23110_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23111_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23113_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23113_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23115_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23115_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23116_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23118_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23118_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23123_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23123_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23124_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23126_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23126_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23128_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23128_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23129_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23131_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23131_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23133_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23133_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23134_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23136_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23136_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23141_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23141_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23142_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23144_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23144_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23146_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23146_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23147_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23149_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23149_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23151_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23151_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23152_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23154_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23154_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23159_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23159_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23160_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23162_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23162_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23164_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23164_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23165_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23167_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23167_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23169_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23169_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23170_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23172_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23172_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23177_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23177_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23178_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23180_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23180_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23182_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23182_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23183_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23185_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23185_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23187_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23187_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23188_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23190_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23190_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23195_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23195_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23196_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23198_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23198_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23200_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23200_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23201_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23203_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23203_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23205_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23205_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23206_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23208_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23208_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23213_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23213_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23214_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23216_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23216_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23218_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23218_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23219_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23221_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23221_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23223_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23223_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23224_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23226_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23226_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23231_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23231_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23232_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23234_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23234_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23236_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23236_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23237_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23239_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23239_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23241_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23241_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23242_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23244_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23244_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23249_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23249_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23250_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23252_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23252_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23254_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23254_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23255_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23257_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23257_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23259_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23259_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23260_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23262_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23262_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23267_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23267_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23268_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23270_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23270_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23272_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23272_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23273_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23275_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23275_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23277_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23277_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23278_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23280_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23280_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23285_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23285_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23286_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23288_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23288_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23290_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23290_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23291_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23293_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23293_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23295_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23295_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23296_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23298_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23298_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23303_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23303_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23304_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23306_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23306_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23308_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23308_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23309_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23311_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23311_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23313_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23313_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23314_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23316_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23316_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23321_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23321_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23322_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23324_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23324_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23326_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23326_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23327_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23329_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23329_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23331_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23331_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23332_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23334_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23334_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23339_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23339_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23340_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23342_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23342_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23344_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23344_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23345_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23347_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23347_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23349_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23349_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23350_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23352_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23352_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23357_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23357_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23358_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23360_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23360_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23362_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23362_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23363_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23365_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23365_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23367_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23367_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23368_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23370_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23370_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23375_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23375_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23376_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23378_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23378_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23380_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23380_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23381_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23383_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23383_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23385_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23385_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23386_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23388_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23388_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23393_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23393_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23394_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23396_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23396_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23398_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23398_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23399_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23401_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23401_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23403_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23403_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23404_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23406_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23406_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23411_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23411_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23412_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23414_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23414_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23416_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23416_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23417_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23419_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23419_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23421_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23421_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23422_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23424_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23424_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23429_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23429_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23430_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23432_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23432_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23434_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23434_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23435_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23437_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23437_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23439_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23439_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23440_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23442_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23442_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23447_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23447_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23448_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23450_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23450_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23452_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23452_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23453_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23455_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23455_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23457_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23457_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23458_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23460_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23460_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23465_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23465_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23466_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23468_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23468_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23470_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23470_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23471_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23473_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23473_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23475_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23475_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23476_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23478_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23478_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23483_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23483_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23484_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23486_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23486_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23488_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23488_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23489_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23491_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23491_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23493_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23493_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23494_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23496_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23496_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23501_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23501_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23502_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23504_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23504_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23506_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23506_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23507_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23509_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23509_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23511_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23511_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23512_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23514_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23514_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23519_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23519_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23520_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23522_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23522_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23524_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23524_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23525_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23527_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23527_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23529_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23529_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23530_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23532_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23532_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23537_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23537_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23538_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23540_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23540_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23542_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23542_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23543_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23545_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23545_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23547_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23547_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23548_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23550_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23550_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23555_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23555_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23556_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23558_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23558_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23560_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23560_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23561_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23563_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23563_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23565_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23565_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23566_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23568_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23568_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23573_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23573_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23574_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23576_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23576_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23578_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23578_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23579_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23581_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23581_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23583_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23583_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23584_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23586_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23586_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23591_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23591_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23592_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23594_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23594_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23596_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23596_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23597_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23599_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23599_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23601_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23601_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23602_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23604_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23604_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23609_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23609_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23610_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23612_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23612_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23614_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23614_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23615_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23617_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23617_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23619_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23619_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23620_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23622_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23622_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23627_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23627_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23628_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23630_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23630_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23632_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23632_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23633_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23635_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23635_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23637_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23637_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23638_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23640_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23640_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23645_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23645_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23646_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23648_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23648_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23650_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23650_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23651_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23653_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23653_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23655_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23655_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23656_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23658_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23658_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23663_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23663_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23664_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23666_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23666_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23668_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23668_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23669_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23671_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23671_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23673_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23673_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23674_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23676_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23676_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23681_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23681_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23682_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23684_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23684_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23686_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23686_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23687_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23689_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23689_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23691_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23691_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23692_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23694_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23694_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23699_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23699_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23700_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23702_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23702_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23704_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23704_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23705_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23707_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23707_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23709_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23709_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23710_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23712_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23712_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23717_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23717_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23718_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23720_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23720_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23722_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23722_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23723_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23725_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23725_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23727_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23727_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23728_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23730_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23730_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23735_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23735_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23736_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23738_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23738_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23740_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23740_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23741_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23743_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23743_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23745_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23745_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23746_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23748_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23748_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23753_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23753_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23754_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23756_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23756_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23758_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23758_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23759_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23761_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23761_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23763_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23763_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23764_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23766_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23766_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23771_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23771_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23772_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23774_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23774_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23776_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23776_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23777_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23779_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23779_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23781_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23781_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23782_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23784_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23784_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23789_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23789_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23790_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23792_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23792_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23794_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23794_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23795_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23797_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23797_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23799_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23799_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23800_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23802_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23802_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23807_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23807_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23808_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23810_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23810_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23812_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23812_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23813_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23815_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23815_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23817_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23817_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23818_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23820_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23820_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23825_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23825_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23826_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23828_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23828_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23830_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23830_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23831_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23833_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23833_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23835_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23835_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23836_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23838_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23838_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23843_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23843_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23844_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23846_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23846_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23848_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23848_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23849_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23851_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23851_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23853_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23853_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23854_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23856_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23856_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23861_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23861_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23862_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23864_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23864_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23866_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23866_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23867_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23869_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23869_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23871_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23871_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23872_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23874_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23874_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23879_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23879_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23880_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23882_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23882_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23884_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23884_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23885_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23887_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23887_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23889_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23889_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23890_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23892_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23892_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23897_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23897_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23898_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23900_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23900_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23902_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23902_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23903_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23905_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23905_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23907_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23907_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23908_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23910_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23910_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23915_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23915_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23916_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23918_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23918_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23920_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23920_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23921_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23923_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23923_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23925_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23925_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23926_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23928_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23928_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23933_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23933_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23934_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23936_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23936_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23938_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23938_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23939_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23941_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23941_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23943_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23943_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23944_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23946_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23946_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23951_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23951_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23952_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23954_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23954_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23956_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23956_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23957_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23959_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23959_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23961_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23961_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23962_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23964_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23964_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23969_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23969_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23970_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23972_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23972_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23974_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23974_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23975_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23977_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23977_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23979_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23979_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23980_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23982_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23982_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23987_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23987_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23988_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23990_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23990_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23992_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23992_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23993_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23995_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23995_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23997_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23997_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23998_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24000_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24000_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24005_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24005_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24006_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24008_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24008_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24010_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24010_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24011_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24013_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24013_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24015_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24015_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24016_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24018_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24018_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24023_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24023_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24024_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24026_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24026_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24028_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24028_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24029_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24031_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24031_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24033_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24033_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24034_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24036_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24036_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24041_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24041_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24042_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24044_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24044_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24046_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24046_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24047_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24049_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24049_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24051_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24051_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24052_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24054_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24054_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24059_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24059_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24060_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24062_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24062_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24064_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24064_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24065_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24067_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24067_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24069_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24069_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24070_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24072_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24072_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24077_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24077_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24078_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24080_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24080_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24082_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24082_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24083_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24085_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24085_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24087_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24087_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24088_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24090_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24090_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24095_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24095_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24096_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24098_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24098_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24100_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24100_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24101_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24103_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24103_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24105_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24105_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24106_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24108_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24108_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24113_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24113_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24114_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24116_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24116_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24118_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24118_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24119_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24121_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24121_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24123_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24123_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24124_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24126_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24126_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24131_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24131_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24132_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24134_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24134_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24136_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24136_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24137_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24139_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24139_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24141_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24141_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24142_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24144_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24144_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24149_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24149_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24150_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24152_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24152_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24154_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24154_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24155_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24157_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24157_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24159_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24159_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24160_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24162_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24162_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24167_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24167_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24168_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24170_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24170_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24172_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24172_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24173_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24175_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24175_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24177_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24177_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24178_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24180_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24180_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24185_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24185_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24186_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24188_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24188_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24190_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24190_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24191_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24193_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24193_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24195_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24195_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24196_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24198_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24198_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24203_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24203_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24204_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24206_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24206_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24208_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24208_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24209_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24211_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24211_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24213_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24213_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24214_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24216_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24216_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24221_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24221_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24222_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24224_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24224_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24226_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24226_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24227_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24229_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24229_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24231_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24231_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24232_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24234_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24234_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24239_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24239_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24240_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24242_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24242_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24244_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24244_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24245_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24247_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24247_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24249_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24249_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24250_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24252_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24252_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24257_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24257_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24258_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24260_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24260_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24262_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24262_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24263_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24265_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24265_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24267_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24267_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24268_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24270_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24270_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24275_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24275_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24276_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24278_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24278_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24280_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24280_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24281_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24283_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24283_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24285_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24285_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24286_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24288_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24288_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24293_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24293_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24294_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24296_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24296_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24298_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24298_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24299_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24301_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24301_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24303_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24303_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24304_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24306_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24306_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24311_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24311_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24312_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24314_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24314_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24316_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24316_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24317_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24319_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24319_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24321_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24321_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24322_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24324_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24324_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24329_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24329_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24330_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24332_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24332_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24334_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24334_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24335_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24337_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24337_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24339_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24339_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24340_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24342_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24342_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24347_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24347_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24348_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24350_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24350_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24352_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24352_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24353_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24355_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24355_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24357_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24357_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24358_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24360_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24360_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24365_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24365_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24366_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24368_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24368_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24370_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24370_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24371_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24373_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24373_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24375_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24375_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24376_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24378_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24378_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24383_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24383_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24384_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24386_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24386_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24388_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24388_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24389_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24391_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24391_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24393_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24393_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24394_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24396_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24396_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24401_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24401_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24402_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24404_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24404_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24406_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24406_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24407_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24409_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24409_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24411_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24411_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24412_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24414_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24414_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24419_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24419_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24420_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24422_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24422_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24424_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24424_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24425_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24427_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24427_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24429_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24429_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24430_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24432_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24432_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24437_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24437_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24438_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24440_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24440_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24442_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24442_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24443_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24445_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24445_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24447_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24447_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24448_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24450_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24450_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24455_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24455_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24456_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24458_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24458_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24460_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24460_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24461_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24463_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24463_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24465_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24465_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24466_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24468_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24468_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24473_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24473_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24474_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24476_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24476_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24478_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24478_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24479_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24481_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24481_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24483_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24483_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24484_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24486_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24486_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24491_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24491_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24492_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24494_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24494_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24496_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24496_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24497_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24499_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24499_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24501_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24501_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24502_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24504_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24504_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24509_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24509_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24510_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24512_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24512_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24514_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24514_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24515_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24517_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24517_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24519_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24519_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24520_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24522_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24522_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24527_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24527_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24528_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24530_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24530_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24532_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24532_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24533_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24535_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24535_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24537_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24537_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24538_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24540_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24540_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24545_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24545_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24546_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24548_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24548_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24550_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24550_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24551_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24553_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24553_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24555_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24555_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24556_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24558_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24558_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24563_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24563_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24564_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24566_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24566_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24568_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24568_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24569_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24571_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24571_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24573_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24573_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24574_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24576_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24576_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24581_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24581_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24582_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24584_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24584_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24586_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24586_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24587_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24589_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24589_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24591_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24591_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24592_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24594_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24594_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24599_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24599_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24600_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24602_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24602_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24604_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24604_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24605_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24607_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24607_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24609_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24609_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24610_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24612_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24612_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24617_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24617_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24618_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24620_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24620_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24622_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24622_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24623_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24625_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24625_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24627_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24627_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24628_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24630_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24630_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24635_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24635_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24636_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24638_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24638_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24640_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24640_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24641_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24643_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24643_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24645_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24645_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24646_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24648_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24648_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24653_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24653_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24654_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24656_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24656_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24658_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24658_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24659_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24661_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24661_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24663_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24663_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24664_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24666_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24666_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24671_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24671_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24672_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24674_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24674_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24676_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24676_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24677_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24679_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24679_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24681_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24681_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24682_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24684_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24684_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24689_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24689_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24690_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24692_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24692_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24694_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24694_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24695_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24697_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24697_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24699_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24699_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24700_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24702_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24702_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24707_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24707_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24708_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24710_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24710_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24712_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24712_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24713_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24715_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24715_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24717_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24717_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24718_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24720_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24720_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24725_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24725_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24726_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24728_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24728_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24730_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24730_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24731_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24733_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24733_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24735_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24735_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24736_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24738_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24738_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24743_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24743_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24744_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24746_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24746_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24748_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24748_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24749_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24751_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24751_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24753_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24753_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24754_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24756_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24756_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24761_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24761_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24762_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24764_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24764_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24766_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24766_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24767_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24769_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24769_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24771_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24771_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24772_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24774_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24774_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24779_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24779_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24780_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24782_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24782_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24784_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24784_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24785_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24787_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24787_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24789_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24789_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24790_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24792_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24792_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24797_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24797_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24798_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24800_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24800_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24802_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24802_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24803_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24805_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24805_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24807_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24807_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24808_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24810_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24810_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24815_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24815_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24816_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24818_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24818_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24820_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24820_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24821_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24823_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24823_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24825_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24825_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24826_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24828_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24828_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24833_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24833_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24834_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24836_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24836_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24838_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24838_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24839_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24841_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24841_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24843_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24843_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24844_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24846_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24846_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24851_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24851_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24852_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24854_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24854_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24856_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24856_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24857_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24859_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24859_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24861_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24861_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24862_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24864_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24864_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24869_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24869_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24870_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24872_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24872_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24874_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24874_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24875_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24877_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24877_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24879_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24879_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24880_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24882_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24882_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24887_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24887_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24888_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24890_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24890_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24892_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24892_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24893_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24895_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24895_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24897_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24897_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24898_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24900_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24900_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24905_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24905_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24906_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24908_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24908_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24910_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24910_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24911_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24913_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24913_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24915_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24915_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24916_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24918_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24918_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24923_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24923_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24924_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24926_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24926_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24928_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24928_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24929_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24931_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24931_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24933_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24933_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24934_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24936_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24936_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24941_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24941_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24942_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24944_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24944_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24946_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24946_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24947_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24949_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24949_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24951_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24951_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24952_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24954_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24954_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24959_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24959_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24960_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24962_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24962_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24964_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24964_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24965_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24967_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24967_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24969_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24969_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24970_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24972_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24972_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24977_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24977_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24978_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24980_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24980_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24982_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24982_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24983_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24985_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24985_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24987_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24987_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24988_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24990_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24990_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24995_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24995_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24996_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24998_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24998_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25000_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25000_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25001_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25003_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25003_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25005_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25005_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25006_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25008_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25008_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25013_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25013_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25014_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25016_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25016_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25018_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25018_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25019_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25021_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25021_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25023_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25023_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25024_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25026_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25026_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25031_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25031_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25032_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25034_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25034_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25036_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25036_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25037_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25039_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25039_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25041_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25041_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25042_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25044_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25044_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25049_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25049_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25050_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25052_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25052_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25054_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25054_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25055_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25057_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25057_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25059_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25059_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25060_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25062_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25062_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25067_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25067_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25068_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25070_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25070_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25072_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25072_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25073_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25075_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25075_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25077_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25077_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25078_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25080_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25080_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25085_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25085_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25086_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25088_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25088_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25090_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25090_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25091_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25093_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25093_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25095_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25095_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25096_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25098_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25098_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25103_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25103_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25104_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25106_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25106_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25108_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25108_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25109_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25111_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25111_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25113_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25113_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25114_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25116_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25116_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25121_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25121_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25122_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25124_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25124_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25126_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25126_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25127_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25129_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25129_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25131_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25131_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25132_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25134_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25134_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25139_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25139_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25140_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25142_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25142_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25144_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25144_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25145_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25147_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25147_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25149_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25149_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25150_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25152_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25152_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25157_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25157_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25158_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25160_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25160_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25162_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25162_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25163_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25165_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25165_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25167_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25167_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25168_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25170_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25170_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25175_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25175_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25176_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25178_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25178_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25180_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25180_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25181_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25183_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25183_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25185_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25185_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25186_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25188_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25188_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25193_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25193_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25194_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25196_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25196_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25198_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25198_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25199_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25201_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25201_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25203_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25203_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25204_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25206_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25206_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25211_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25211_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25212_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25214_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25214_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25216_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25216_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25217_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25219_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25219_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25221_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25221_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25222_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25224_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25224_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25229_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25229_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25230_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25232_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25232_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25234_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25234_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25235_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25237_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25237_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25239_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25239_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25240_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25242_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25242_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25247_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25247_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25248_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25250_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25250_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25252_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25252_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25253_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25255_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25255_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25257_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25257_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25258_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25260_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25260_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25265_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25265_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25266_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25268_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25268_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25270_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25270_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25271_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25273_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25273_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25275_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25275_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25276_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25278_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25278_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25283_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25283_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25284_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25286_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25286_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25288_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25288_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25289_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25291_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25291_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25293_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25293_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25294_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25296_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25296_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25301_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25301_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25302_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25304_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25304_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25306_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25306_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25307_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25309_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25309_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25311_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25311_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25312_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25314_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25314_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25319_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25319_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25320_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25322_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25322_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25324_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25324_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25325_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25327_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25327_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25329_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25329_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25330_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25332_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25332_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25337_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25337_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25338_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25340_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25340_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25342_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25342_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25343_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25345_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25345_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25347_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25347_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25348_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25350_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25350_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25355_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25355_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25356_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25358_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25358_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25360_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25360_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25361_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25363_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25363_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25365_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25365_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25366_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25368_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25368_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25373_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25373_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25374_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25376_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25376_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25378_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25378_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25379_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25381_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25381_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25383_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25383_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25384_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25386_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25386_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25391_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25391_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25392_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25394_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25394_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25396_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25396_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25397_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25399_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25399_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25401_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25401_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25402_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25404_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25404_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25409_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25409_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25410_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25412_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25412_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25414_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25414_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25415_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25417_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25417_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25419_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25419_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25420_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25422_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25422_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25427_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25427_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25428_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25430_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25430_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25432_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25432_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25433_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25435_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25435_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25437_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25437_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25438_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25440_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25440_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25445_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25445_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25446_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25448_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25448_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25450_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25450_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25451_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25453_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25453_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25455_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25455_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25456_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25458_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25458_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25463_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25463_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25464_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25466_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25466_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25468_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25468_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25469_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25471_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25471_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25473_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25473_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25474_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25476_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25476_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25481_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25481_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25482_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25484_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25484_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25486_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25486_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25487_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25489_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25489_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25491_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25491_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25492_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25494_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25494_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25499_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25499_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25500_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25502_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25502_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25504_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25504_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25505_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25507_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25507_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25509_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25509_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25510_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25512_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25512_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25517_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25517_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25518_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25520_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25520_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25522_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25522_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25523_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25525_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25525_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25527_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25527_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25528_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25530_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25530_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25535_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25535_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25536_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25538_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25538_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25540_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25540_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25541_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25543_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25543_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25545_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25545_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25546_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25548_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25548_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25553_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25553_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25554_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25556_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25556_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25558_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25558_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25559_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25561_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25561_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25563_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25563_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25564_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25566_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25566_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25571_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25571_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25572_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25574_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25574_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25576_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25576_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25577_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25579_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25579_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25581_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25581_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25582_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25584_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25584_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25589_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25589_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25590_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25592_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25592_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25594_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25594_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25595_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25597_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25597_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25599_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25599_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25600_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25602_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25602_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25607_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25607_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25608_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25610_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25610_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25612_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25612_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25613_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25615_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25615_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25617_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25617_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25618_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25620_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25620_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25625_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25625_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25626_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25628_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25628_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25630_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25630_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25631_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25633_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25633_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25635_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25635_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25636_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25638_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25638_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25643_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25643_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25644_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25646_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25646_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25648_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25648_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25649_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25651_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25651_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25653_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25653_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25654_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25656_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25656_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25661_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25661_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25662_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25664_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25664_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25666_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25666_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25667_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25669_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25669_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25671_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25671_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25672_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25674_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25674_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25679_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25679_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25680_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25682_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25682_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25684_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25684_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25685_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25687_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25687_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25689_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25689_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25690_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25692_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25692_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25697_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25697_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25698_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25700_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25700_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25702_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25702_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25703_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25705_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25705_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25707_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25707_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25708_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25710_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25710_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25715_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25715_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25716_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25718_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25718_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25720_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25720_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25721_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25723_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25723_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25725_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25725_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25726_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25728_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25728_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25733_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25733_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25734_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25736_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25736_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25738_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25738_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25739_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25741_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25741_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25743_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25743_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25744_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25746_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25746_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25751_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25751_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25752_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25754_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25754_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25756_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25756_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25757_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25759_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25759_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25761_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25761_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25762_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25764_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25764_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25769_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25769_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25770_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25772_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25772_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25774_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25774_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25775_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25777_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25777_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25779_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25779_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25780_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25782_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25782_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25787_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25787_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25788_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25790_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25790_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25792_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25792_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25793_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25795_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25795_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25797_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25797_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25798_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25800_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25800_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25805_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25805_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25806_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25808_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25808_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25810_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25810_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25811_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25813_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25813_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25815_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25815_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25816_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25818_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25818_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25823_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25823_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25824_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25826_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25826_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25828_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25828_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25829_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25831_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25831_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25833_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25833_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25834_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25836_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25836_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25841_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25841_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25842_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25844_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25844_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25846_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25846_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25847_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25849_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25849_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25851_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25851_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25852_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25854_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25854_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25859_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25859_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25860_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25862_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25862_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25864_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25864_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25865_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25867_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25867_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25869_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25869_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25870_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25872_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25872_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25877_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25877_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25878_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25880_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25880_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25882_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25882_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25883_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25885_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25885_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25887_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25887_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25888_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25890_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25890_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25895_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25895_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25896_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25898_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25898_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25900_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25900_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25901_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25903_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25903_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25905_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25905_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25906_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25908_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25908_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25913_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25913_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25914_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25916_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25916_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25918_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25918_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25919_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25921_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25921_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25923_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25923_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25924_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25926_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25926_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25931_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25931_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25932_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25934_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25934_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25936_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25936_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25937_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25939_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25939_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25941_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25941_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25942_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25944_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25944_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25949_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25949_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25950_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25952_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25952_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25954_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25954_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25955_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25957_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25957_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25959_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25959_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25960_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25962_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25962_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25967_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25967_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25968_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25970_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25970_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25972_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25972_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25973_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25975_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25975_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25977_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25977_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25978_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25980_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25980_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25985_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25985_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25986_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25988_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25988_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25990_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25990_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25991_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25993_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25993_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25995_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25995_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25996_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25998_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25998_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26003_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26003_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26004_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26006_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26006_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26008_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26008_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26009_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26011_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26011_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26013_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26013_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26014_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26016_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26016_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26021_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26021_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26022_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26024_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26024_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26026_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26026_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26027_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26029_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26029_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26031_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26031_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26032_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26034_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26034_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26039_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26039_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26040_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26042_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26042_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26044_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26044_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26045_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26047_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26047_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26049_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26049_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26050_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26052_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26052_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26057_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26057_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26058_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26060_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26060_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26062_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26062_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26063_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26065_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26065_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26067_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26067_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26068_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26070_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26070_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26075_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26075_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26076_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26078_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26078_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26080_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26080_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26081_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26083_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26083_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26085_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26085_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26086_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26088_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26088_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26093_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26093_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26094_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26096_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26096_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26098_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26098_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26099_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26101_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26101_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26103_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26103_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26104_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26106_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26106_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26111_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26111_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26112_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26114_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26114_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26116_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26116_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26117_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26119_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26119_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26121_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26121_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26122_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26124_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26124_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26129_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26129_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26130_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26132_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26132_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26134_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26134_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26135_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26137_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26137_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26139_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26139_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26140_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26142_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26142_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26147_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26147_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26148_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26150_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26150_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26152_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26152_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26153_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26155_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26155_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26157_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26157_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26158_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26160_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26160_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26165_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26165_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26166_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26168_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26168_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26170_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26170_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26171_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26173_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26173_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26175_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26175_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26176_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26178_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26178_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26183_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26183_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26184_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26186_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26186_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26188_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26188_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26189_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26191_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26191_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26193_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26193_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26194_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26196_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26196_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26201_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26201_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26202_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26204_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26204_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26206_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26206_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26207_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26209_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26209_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26211_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26211_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26212_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26214_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26214_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26219_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26219_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26220_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26222_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26222_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26224_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26224_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26225_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26227_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26227_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26229_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26229_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26230_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26232_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26232_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26237_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26237_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26238_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26240_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26240_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26242_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26242_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26243_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26245_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26245_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26247_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26247_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26248_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26250_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26250_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26255_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26255_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26256_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26258_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26258_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26260_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26260_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26261_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26263_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26263_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26265_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26265_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26266_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26268_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26268_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26273_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26273_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26274_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26276_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26276_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26278_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26278_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26279_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26281_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26281_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26283_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26283_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26284_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26286_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26286_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26291_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26291_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26292_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26294_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26294_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26296_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26296_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26297_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26299_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26299_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26301_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26301_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26302_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26304_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26304_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26309_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26309_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26310_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26312_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26312_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26314_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26314_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26315_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26317_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26317_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26319_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26319_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26320_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26322_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26322_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26327_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26327_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26328_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26330_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26330_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26332_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26332_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26333_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26335_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26335_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26337_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26337_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26338_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26340_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26340_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26345_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26345_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26346_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26348_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26348_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26350_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26350_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26351_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26353_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26353_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26355_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26355_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26356_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26358_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26358_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26363_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26363_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26364_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26366_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26366_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26368_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26368_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26369_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26371_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26371_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26373_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26373_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26374_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26376_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26376_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26381_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26381_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26382_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26384_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26384_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26386_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26386_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26387_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26389_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26389_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26391_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26391_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26392_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26394_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26394_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26399_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26399_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26400_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26402_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26402_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26404_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26404_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26405_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26407_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26407_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26409_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26409_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26410_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26412_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26412_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26417_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26417_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26418_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26420_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26420_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26422_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26422_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26423_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26425_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26425_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26427_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26427_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26428_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26430_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26430_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26435_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26435_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26436_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26438_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26438_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26440_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26440_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26441_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26443_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26443_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26445_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26445_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26446_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26448_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26448_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26453_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26453_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26454_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26456_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26456_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26458_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26458_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26459_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26461_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26461_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26463_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26463_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26464_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26466_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26466_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26471_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26471_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26472_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26474_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26474_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26476_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26476_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26477_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26479_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26479_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26481_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26481_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26482_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26484_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26484_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26489_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26489_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26490_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26492_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26492_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26494_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26494_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26495_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26497_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26497_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26499_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26499_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26500_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26502_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26502_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26507_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26507_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26508_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26510_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26510_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26512_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26512_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26513_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26515_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26515_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26517_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26517_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26518_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26520_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26520_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26525_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26525_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26526_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26528_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26528_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26530_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26530_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26531_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26533_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26533_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26535_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26535_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26536_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26538_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26538_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26543_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26543_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26544_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26546_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26546_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26548_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26548_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26549_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26551_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26551_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26553_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26553_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26554_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26556_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26556_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26561_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26561_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26562_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26564_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26564_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26566_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26566_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26567_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26569_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26569_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26571_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26571_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26572_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26574_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26574_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26579_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26579_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26580_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26582_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26582_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26584_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26584_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26585_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26587_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26587_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26589_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26589_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26590_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26592_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26592_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26597_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26597_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26598_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26600_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26600_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26602_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26602_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26603_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26605_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26605_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26607_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26607_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26608_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26610_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26610_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26615_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26615_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26616_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26618_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26618_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26620_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26620_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26621_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26623_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26623_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26625_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26625_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26626_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26628_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26628_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26633_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26633_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26634_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26636_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26636_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26638_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26638_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26639_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26641_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26641_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26643_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26643_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26644_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26646_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26646_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26651_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26651_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26652_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26654_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26654_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26656_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26656_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26657_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26659_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26659_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26661_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26661_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26662_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26664_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26664_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26669_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26669_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26670_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26672_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26672_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26674_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26674_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26675_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26677_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26677_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26679_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26679_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26680_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26682_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26682_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26687_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26687_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26688_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26690_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26690_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26692_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26692_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26693_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26695_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26695_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26697_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26697_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26698_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26700_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26700_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26705_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26705_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26706_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26708_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26708_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26710_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26710_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26711_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26713_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26713_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26715_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26715_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26716_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26718_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26718_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26723_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26723_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26724_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26726_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26726_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26728_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26728_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26729_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26731_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26731_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26733_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26733_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26734_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26736_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26736_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26741_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26741_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26742_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26744_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26744_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26746_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26746_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26747_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26749_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26749_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26751_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26751_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26752_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26754_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26754_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26759_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26759_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26760_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26762_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26762_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26764_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26764_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26765_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26767_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26767_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26769_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26769_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26770_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26772_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26772_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26777_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26777_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26778_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26780_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26780_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26782_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26782_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26783_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26785_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26785_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26787_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26787_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26788_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26790_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26790_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26795_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26795_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26796_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26798_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26798_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26800_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26800_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26801_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26803_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26803_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26805_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26805_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26806_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26808_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26808_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26813_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26813_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26814_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26816_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26816_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26818_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26818_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26819_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26821_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26821_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26823_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26823_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26824_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26826_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26826_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26831_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26831_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26832_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26834_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26834_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26836_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26836_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26837_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26839_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26839_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26841_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26841_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26842_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26844_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26844_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26849_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26849_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26850_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26852_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26852_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26854_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26854_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26855_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26857_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26857_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26859_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26859_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26860_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26862_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26862_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26867_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26867_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26868_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26870_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26870_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26872_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26872_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26873_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26875_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26875_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26877_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26877_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26878_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26880_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26880_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26885_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26885_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26886_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26888_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26888_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26890_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26890_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26891_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26893_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26893_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26895_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26895_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26896_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26898_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26898_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26903_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26903_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26904_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26906_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26906_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26908_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26908_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26909_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26911_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26911_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26913_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26913_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26914_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26916_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26916_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26921_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26921_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26922_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26924_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26924_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26926_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26926_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26927_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26929_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26929_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26931_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26931_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26932_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26934_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26934_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26939_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26939_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26940_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26942_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26942_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26944_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26944_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26945_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26947_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26947_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26949_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26949_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26950_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26952_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26952_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26957_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26957_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26958_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26960_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26960_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26962_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26962_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26963_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26965_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26965_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26967_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26967_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26968_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26970_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26970_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26975_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26975_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26976_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26978_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26978_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26980_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26980_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26981_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26983_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26983_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26985_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26985_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26986_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26988_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26988_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26993_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26993_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26994_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26996_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26996_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26998_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26998_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26999_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27001_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27001_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27003_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27003_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27004_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27006_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27006_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27011_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27011_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27012_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27014_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27014_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27016_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27016_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27017_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27019_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27019_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27021_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27021_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27022_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27024_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27024_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27029_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27029_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27030_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27032_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27032_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27034_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27034_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27035_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27037_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27037_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27039_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27039_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27040_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27042_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27042_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27047_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27047_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27048_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27050_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27050_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27052_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27052_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27053_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27055_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27055_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27057_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27057_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27058_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27060_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27060_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27065_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27065_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27066_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27068_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27068_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27070_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27070_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27071_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27073_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27073_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27075_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27075_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27076_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27078_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27078_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27083_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27083_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27084_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27086_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27086_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27088_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27088_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27089_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27091_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27091_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27093_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27093_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27094_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27096_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27096_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27101_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27101_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27102_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27104_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27104_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27106_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27106_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27107_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27109_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27109_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27111_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27111_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27112_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27114_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27114_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27119_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27119_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27120_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27122_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27122_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27124_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27124_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27125_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27127_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27127_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27129_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27129_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27130_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27132_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27132_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27137_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27137_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27138_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27140_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27140_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27142_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27142_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27143_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27145_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27145_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27147_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27147_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27148_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27150_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27150_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27155_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27155_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27156_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27158_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27158_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27160_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27160_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27161_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27163_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27163_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27165_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27165_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27166_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27168_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27168_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27173_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27173_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27174_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27176_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27176_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27178_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27178_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27179_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27181_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27181_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27183_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27183_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27184_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27186_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27186_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27191_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27191_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27192_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27194_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27194_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27196_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27196_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27197_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27199_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27199_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27201_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27201_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27202_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27204_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27204_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27209_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27209_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27210_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27212_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27212_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27214_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27214_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27215_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27217_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27217_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27219_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27219_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27220_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27222_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27222_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27227_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27227_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27228_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27230_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27230_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27232_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27232_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27233_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27235_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27235_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27237_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27237_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27238_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27240_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27240_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27245_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27245_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27246_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27248_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27248_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27250_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27250_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27251_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27253_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27253_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27255_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27255_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27256_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27258_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27258_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27263_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27263_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27264_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27266_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27266_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27268_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27268_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27269_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27271_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27271_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27273_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27273_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27274_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27276_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27276_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27281_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27281_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27282_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27284_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27284_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27286_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27286_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27287_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27289_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27289_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27291_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27291_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27292_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27294_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27294_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27299_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27299_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27300_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27302_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27302_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27304_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27304_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27305_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27307_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27307_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27309_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27309_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27310_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27312_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27312_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27317_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27317_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27318_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27320_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27320_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27322_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27322_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27323_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27325_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27325_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27327_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27327_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27328_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27330_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27330_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27335_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27335_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27336_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27338_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27338_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27340_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27340_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27341_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27343_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27343_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27345_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27345_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27346_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27348_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27348_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27353_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27353_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27354_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27356_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27356_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27358_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27358_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27359_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27361_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27361_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27363_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27363_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27364_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27366_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27366_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27371_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27371_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27372_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27374_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27374_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27376_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27376_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27377_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27379_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27379_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27381_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27381_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27382_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27384_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27384_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27389_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27389_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27390_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27392_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27392_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27394_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27394_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27395_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27397_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27397_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27399_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27399_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27400_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27402_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27402_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27407_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27407_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27408_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27410_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27410_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27412_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27412_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27413_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27415_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27415_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27417_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27417_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27418_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27420_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27420_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27425_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27425_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27426_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27428_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27428_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27430_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27430_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27431_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27433_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27433_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27435_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27435_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27436_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27438_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27438_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid27442_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid27444_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage0_uid27446_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage0_uid27446_i_unnamed_c_compstr0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid27447_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid27449_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage1_uid27451_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage1_uid27451_i_unnamed_c_compstr0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid27452_i_unnamed_c_compstr0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid27454_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] rightShiftStage2_uid27456_i_unnamed_c_compstr0_shift_x_s;
    reg [33:0] rightShiftStage2_uid27456_i_unnamed_c_compstr0_shift_x_q;
    wire [0:0] i_exitcond15_c_compstr3606_cmp_nsign_q;
    wire [0:0] i_unnamed_c_compstr1005_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1005_join_q;
    wire [0:0] i_unnamed_c_compstr1021_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1021_join_q;
    wire [0:0] i_unnamed_c_compstr1033_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1033_join_q;
    wire [0:0] i_unnamed_c_compstr1049_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1049_join_q;
    wire [0:0] i_unnamed_c_compstr1061_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1061_join_q;
    wire [0:0] i_unnamed_c_compstr1077_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1077_join_q;
    wire [0:0] i_unnamed_c_compstr1089_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1089_join_q;
    wire [0:0] i_unnamed_c_compstr109_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr109_join_q;
    wire [0:0] i_unnamed_c_compstr1105_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1105_join_q;
    wire [0:0] i_unnamed_c_compstr1117_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1117_join_q;
    wire [0:0] i_unnamed_c_compstr1133_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1133_join_q;
    wire [0:0] i_unnamed_c_compstr1145_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1145_join_q;
    wire [0:0] i_unnamed_c_compstr1161_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1161_join_q;
    wire [0:0] i_unnamed_c_compstr1173_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1173_join_q;
    wire [0:0] i_unnamed_c_compstr1189_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1189_join_q;
    wire [0:0] i_unnamed_c_compstr1201_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1201_join_q;
    wire [0:0] i_unnamed_c_compstr1217_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1217_join_q;
    wire [0:0] i_unnamed_c_compstr1229_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1229_join_q;
    wire [0:0] i_unnamed_c_compstr1245_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1245_join_q;
    wire [0:0] i_unnamed_c_compstr125_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr125_join_q;
    wire [0:0] i_unnamed_c_compstr1257_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1257_join_q;
    wire [0:0] i_unnamed_c_compstr1273_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1273_join_q;
    wire [0:0] i_unnamed_c_compstr1285_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1285_join_q;
    wire [0:0] i_unnamed_c_compstr1301_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1301_join_q;
    wire [0:0] i_unnamed_c_compstr1313_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1313_join_q;
    wire [0:0] i_unnamed_c_compstr1329_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1329_join_q;
    wire [0:0] i_unnamed_c_compstr1341_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1341_join_q;
    wire [0:0] i_unnamed_c_compstr1357_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1357_join_q;
    wire [0:0] i_unnamed_c_compstr1369_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1369_join_q;
    wire [0:0] i_unnamed_c_compstr137_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr137_join_q;
    wire [0:0] i_unnamed_c_compstr1385_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1385_join_q;
    wire [0:0] i_unnamed_c_compstr1397_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1397_join_q;
    wire [0:0] i_unnamed_c_compstr1413_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1413_join_q;
    wire [0:0] i_unnamed_c_compstr1425_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1425_join_q;
    wire [0:0] i_unnamed_c_compstr1441_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1441_join_q;
    wire [0:0] i_unnamed_c_compstr1453_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1453_join_q;
    wire [0:0] i_unnamed_c_compstr1469_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1469_join_q;
    wire [0:0] i_unnamed_c_compstr1481_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1481_join_q;
    wire [0:0] i_unnamed_c_compstr1497_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1497_join_q;
    wire [0:0] i_unnamed_c_compstr1509_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1509_join_q;
    wire [0:0] i_unnamed_c_compstr1525_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1525_join_q;
    wire [0:0] i_unnamed_c_compstr153_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr153_join_q;
    wire [0:0] i_unnamed_c_compstr1537_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1537_join_q;
    wire [0:0] i_unnamed_c_compstr1553_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1553_join_q;
    wire [0:0] i_unnamed_c_compstr1565_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1565_join_q;
    wire [0:0] i_unnamed_c_compstr1581_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1581_join_q;
    wire [0:0] i_unnamed_c_compstr1593_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1593_join_q;
    wire [0:0] i_unnamed_c_compstr1609_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1609_join_q;
    wire [0:0] i_unnamed_c_compstr1621_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1621_join_q;
    wire [0:0] i_unnamed_c_compstr1637_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1637_join_q;
    wire [0:0] i_unnamed_c_compstr1649_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1649_join_q;
    wire [0:0] i_unnamed_c_compstr165_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr165_join_q;
    wire [0:0] i_unnamed_c_compstr1665_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1665_join_q;
    wire [0:0] i_unnamed_c_compstr1677_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1677_join_q;
    wire [0:0] i_unnamed_c_compstr1693_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1693_join_q;
    wire [0:0] i_unnamed_c_compstr1705_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1705_join_q;
    wire [0:0] i_unnamed_c_compstr1721_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1721_join_q;
    wire [0:0] i_unnamed_c_compstr1733_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1733_join_q;
    wire [0:0] i_unnamed_c_compstr1749_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1749_join_q;
    wire [0:0] i_unnamed_c_compstr1761_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1761_join_q;
    wire [0:0] i_unnamed_c_compstr1777_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1777_join_q;
    wire [0:0] i_unnamed_c_compstr1789_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1789_join_q;
    wire [0:0] i_unnamed_c_compstr1805_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1805_join_q;
    wire [0:0] i_unnamed_c_compstr181_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr181_join_q;
    wire [0:0] i_unnamed_c_compstr1817_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1817_join_q;
    wire [0:0] i_unnamed_c_compstr1833_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1833_join_q;
    wire [0:0] i_unnamed_c_compstr1845_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1845_join_q;
    wire [0:0] i_unnamed_c_compstr1861_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1861_join_q;
    wire [0:0] i_unnamed_c_compstr1873_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1873_join_q;
    wire [0:0] i_unnamed_c_compstr1889_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1889_join_q;
    wire [0:0] i_unnamed_c_compstr1901_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1901_join_q;
    wire [0:0] i_unnamed_c_compstr1917_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1917_join_q;
    wire [0:0] i_unnamed_c_compstr1929_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1929_join_q;
    wire [0:0] i_unnamed_c_compstr193_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr193_join_q;
    wire [0:0] i_unnamed_c_compstr1945_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1945_join_q;
    wire [0:0] i_unnamed_c_compstr1957_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1957_join_q;
    wire [0:0] i_unnamed_c_compstr1973_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1973_join_q;
    wire [0:0] i_unnamed_c_compstr1985_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr1985_join_q;
    wire [0:0] i_unnamed_c_compstr2001_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2001_join_q;
    wire [0:0] i_unnamed_c_compstr2013_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2013_join_q;
    wire [0:0] i_unnamed_c_compstr2029_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2029_join_q;
    wire [0:0] i_unnamed_c_compstr2041_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2041_join_q;
    wire [0:0] i_unnamed_c_compstr2057_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2057_join_q;
    wire [0:0] i_unnamed_c_compstr2069_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2069_join_q;
    wire [0:0] i_unnamed_c_compstr2085_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2085_join_q;
    wire [0:0] i_unnamed_c_compstr209_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr209_join_q;
    wire [0:0] i_unnamed_c_compstr2097_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2097_join_q;
    wire [0:0] i_unnamed_c_compstr2113_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2113_join_q;
    wire [0:0] i_unnamed_c_compstr2125_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2125_join_q;
    wire [0:0] i_unnamed_c_compstr2141_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2141_join_q;
    wire [0:0] i_unnamed_c_compstr2153_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2153_join_q;
    wire [0:0] i_unnamed_c_compstr2169_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2169_join_q;
    wire [0:0] i_unnamed_c_compstr2181_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2181_join_q;
    wire [0:0] i_unnamed_c_compstr2197_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2197_join_q;
    wire [0:0] i_unnamed_c_compstr2209_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2209_join_q;
    wire [0:0] i_unnamed_c_compstr221_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr221_join_q;
    wire [0:0] i_unnamed_c_compstr2225_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2225_join_q;
    wire [0:0] i_unnamed_c_compstr2237_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2237_join_q;
    wire [0:0] i_unnamed_c_compstr2253_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2253_join_q;
    wire [0:0] i_unnamed_c_compstr2265_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2265_join_q;
    wire [0:0] i_unnamed_c_compstr2281_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2281_join_q;
    wire [0:0] i_unnamed_c_compstr2293_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2293_join_q;
    wire [0:0] i_unnamed_c_compstr2309_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2309_join_q;
    wire [0:0] i_unnamed_c_compstr2321_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2321_join_q;
    wire [0:0] i_unnamed_c_compstr2337_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2337_join_q;
    wire [0:0] i_unnamed_c_compstr2349_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2349_join_q;
    wire [0:0] i_unnamed_c_compstr2365_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2365_join_q;
    wire [0:0] i_unnamed_c_compstr237_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr237_join_q;
    wire [0:0] i_unnamed_c_compstr2377_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2377_join_q;
    wire [0:0] i_unnamed_c_compstr2393_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2393_join_q;
    wire [0:0] i_unnamed_c_compstr2405_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2405_join_q;
    wire [0:0] i_unnamed_c_compstr2421_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2421_join_q;
    wire [0:0] i_unnamed_c_compstr2433_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2433_join_q;
    wire [0:0] i_unnamed_c_compstr2449_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2449_join_q;
    wire [0:0] i_unnamed_c_compstr2461_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2461_join_q;
    wire [0:0] i_unnamed_c_compstr2477_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2477_join_q;
    wire [0:0] i_unnamed_c_compstr2489_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2489_join_q;
    wire [0:0] i_unnamed_c_compstr249_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr249_join_q;
    wire [0:0] i_unnamed_c_compstr2505_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2505_join_q;
    wire [0:0] i_unnamed_c_compstr2517_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2517_join_q;
    wire [0:0] i_unnamed_c_compstr2533_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2533_join_q;
    wire [0:0] i_unnamed_c_compstr2545_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2545_join_q;
    wire [0:0] i_unnamed_c_compstr2561_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2561_join_q;
    wire [0:0] i_unnamed_c_compstr2573_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2573_join_q;
    wire [0:0] i_unnamed_c_compstr2589_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2589_join_q;
    wire [0:0] i_unnamed_c_compstr2601_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2601_join_q;
    wire [0:0] i_unnamed_c_compstr2617_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2617_join_q;
    wire [0:0] i_unnamed_c_compstr2629_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2629_join_q;
    wire [0:0] i_unnamed_c_compstr2645_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2645_join_q;
    wire [0:0] i_unnamed_c_compstr265_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr265_join_q;
    wire [0:0] i_unnamed_c_compstr2657_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2657_join_q;
    wire [0:0] i_unnamed_c_compstr2673_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2673_join_q;
    wire [0:0] i_unnamed_c_compstr2685_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2685_join_q;
    wire [0:0] i_unnamed_c_compstr27_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr27_join_q;
    wire [0:0] i_unnamed_c_compstr2701_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2701_join_q;
    wire [0:0] i_unnamed_c_compstr2713_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2713_join_q;
    wire [0:0] i_unnamed_c_compstr2729_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2729_join_q;
    wire [0:0] i_unnamed_c_compstr2741_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2741_join_q;
    wire [0:0] i_unnamed_c_compstr2757_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2757_join_q;
    wire [0:0] i_unnamed_c_compstr2769_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2769_join_q;
    wire [0:0] i_unnamed_c_compstr277_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr277_join_q;
    wire [0:0] i_unnamed_c_compstr2785_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2785_join_q;
    wire [0:0] i_unnamed_c_compstr2797_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2797_join_q;
    wire [0:0] i_unnamed_c_compstr2813_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2813_join_q;
    wire [0:0] i_unnamed_c_compstr2825_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2825_join_q;
    wire [0:0] i_unnamed_c_compstr2841_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2841_join_q;
    wire [0:0] i_unnamed_c_compstr2853_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2853_join_q;
    wire [0:0] i_unnamed_c_compstr2869_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2869_join_q;
    wire [0:0] i_unnamed_c_compstr2881_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2881_join_q;
    wire [0:0] i_unnamed_c_compstr2897_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2897_join_q;
    wire [0:0] i_unnamed_c_compstr2909_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2909_join_q;
    wire [0:0] i_unnamed_c_compstr2925_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2925_join_q;
    wire [0:0] i_unnamed_c_compstr293_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr293_join_q;
    wire [0:0] i_unnamed_c_compstr2937_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2937_join_q;
    wire [0:0] i_unnamed_c_compstr2953_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2953_join_q;
    wire [0:0] i_unnamed_c_compstr2965_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2965_join_q;
    wire [0:0] i_unnamed_c_compstr2981_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2981_join_q;
    wire [0:0] i_unnamed_c_compstr2993_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr2993_join_q;
    wire [0:0] i_unnamed_c_compstr3009_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3009_join_q;
    wire [0:0] i_unnamed_c_compstr3021_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3021_join_q;
    wire [0:0] i_unnamed_c_compstr3037_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3037_join_q;
    wire [0:0] i_unnamed_c_compstr3049_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3049_join_q;
    wire [0:0] i_unnamed_c_compstr305_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr305_join_q;
    wire [0:0] i_unnamed_c_compstr3065_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3065_join_q;
    wire [0:0] i_unnamed_c_compstr3077_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3077_join_q;
    wire [0:0] i_unnamed_c_compstr3093_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3093_join_q;
    wire [0:0] i_unnamed_c_compstr3105_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3105_join_q;
    wire [0:0] i_unnamed_c_compstr3121_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3121_join_q;
    wire [0:0] i_unnamed_c_compstr3133_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3133_join_q;
    wire [0:0] i_unnamed_c_compstr3149_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3149_join_q;
    wire [0:0] i_unnamed_c_compstr3161_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3161_join_q;
    wire [0:0] i_unnamed_c_compstr3177_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3177_join_q;
    wire [0:0] i_unnamed_c_compstr3189_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3189_join_q;
    wire [0:0] i_unnamed_c_compstr3205_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3205_join_q;
    wire [0:0] i_unnamed_c_compstr321_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr321_join_q;
    wire [0:0] i_unnamed_c_compstr3217_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3217_join_q;
    wire [0:0] i_unnamed_c_compstr3233_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3233_join_q;
    wire [0:0] i_unnamed_c_compstr3245_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3245_join_q;
    wire [0:0] i_unnamed_c_compstr3261_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3261_join_q;
    wire [0:0] i_unnamed_c_compstr3273_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3273_join_q;
    wire [0:0] i_unnamed_c_compstr3289_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3289_join_q;
    wire [0:0] i_unnamed_c_compstr3301_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3301_join_q;
    wire [0:0] i_unnamed_c_compstr3317_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3317_join_q;
    wire [0:0] i_unnamed_c_compstr3329_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3329_join_q;
    wire [0:0] i_unnamed_c_compstr333_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr333_join_q;
    wire [0:0] i_unnamed_c_compstr3345_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3345_join_q;
    wire [0:0] i_unnamed_c_compstr3357_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3357_join_q;
    wire [0:0] i_unnamed_c_compstr3373_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3373_join_q;
    wire [0:0] i_unnamed_c_compstr3385_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3385_join_q;
    wire [0:0] i_unnamed_c_compstr3401_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3401_join_q;
    wire [0:0] i_unnamed_c_compstr3413_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3413_join_q;
    wire [0:0] i_unnamed_c_compstr3429_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3429_join_q;
    wire [0:0] i_unnamed_c_compstr3441_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3441_join_q;
    wire [0:0] i_unnamed_c_compstr3457_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3457_join_q;
    wire [0:0] i_unnamed_c_compstr3469_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3469_join_q;
    wire [0:0] i_unnamed_c_compstr3485_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3485_join_q;
    wire [0:0] i_unnamed_c_compstr349_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr349_join_q;
    wire [0:0] i_unnamed_c_compstr3497_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3497_join_q;
    wire [0:0] i_unnamed_c_compstr3513_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3513_join_q;
    wire [0:0] i_unnamed_c_compstr3525_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3525_join_q;
    wire [0:0] i_unnamed_c_compstr3541_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3541_join_q;
    wire [0:0] i_unnamed_c_compstr3553_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3553_join_q;
    wire [0:0] i_unnamed_c_compstr3569_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3569_join_q;
    wire [0:0] i_unnamed_c_compstr3581_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3581_join_q;
    wire [0:0] i_unnamed_c_compstr3597_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr3597_join_q;
    wire [0:0] i_unnamed_c_compstr361_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr361_join_q;
    wire [0:0] i_unnamed_c_compstr377_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr377_join_q;
    wire [0:0] i_unnamed_c_compstr389_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr389_join_q;
    wire [0:0] i_unnamed_c_compstr405_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr405_join_q;
    wire [0:0] i_unnamed_c_compstr41_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr41_join_q;
    wire [0:0] i_unnamed_c_compstr417_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr417_join_q;
    wire [0:0] i_unnamed_c_compstr433_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr433_join_q;
    wire [0:0] i_unnamed_c_compstr445_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr445_join_q;
    wire [0:0] i_unnamed_c_compstr461_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr461_join_q;
    wire [0:0] i_unnamed_c_compstr473_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr473_join_q;
    wire [0:0] i_unnamed_c_compstr489_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr489_join_q;
    wire [0:0] i_unnamed_c_compstr501_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr501_join_q;
    wire [0:0] i_unnamed_c_compstr517_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr517_join_q;
    wire [0:0] i_unnamed_c_compstr529_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr529_join_q;
    wire [0:0] i_unnamed_c_compstr53_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr53_join_q;
    wire [0:0] i_unnamed_c_compstr545_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr545_join_q;
    wire [0:0] i_unnamed_c_compstr557_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr557_join_q;
    wire [0:0] i_unnamed_c_compstr573_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr573_join_q;
    wire [0:0] i_unnamed_c_compstr585_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr585_join_q;
    wire [0:0] i_unnamed_c_compstr601_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr601_join_q;
    wire [0:0] i_unnamed_c_compstr613_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr613_join_q;
    wire [0:0] i_unnamed_c_compstr629_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr629_join_q;
    wire [0:0] i_unnamed_c_compstr641_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr641_join_q;
    wire [0:0] i_unnamed_c_compstr657_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr657_join_q;
    wire [0:0] i_unnamed_c_compstr669_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr669_join_q;
    wire [0:0] i_unnamed_c_compstr685_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr685_join_q;
    wire [0:0] i_unnamed_c_compstr69_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr69_join_q;
    wire [0:0] i_unnamed_c_compstr697_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr697_join_q;
    wire [0:0] i_unnamed_c_compstr713_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr713_join_q;
    wire [0:0] i_unnamed_c_compstr725_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr725_join_q;
    wire [0:0] i_unnamed_c_compstr741_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr741_join_q;
    wire [0:0] i_unnamed_c_compstr753_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr753_join_q;
    wire [0:0] i_unnamed_c_compstr769_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr769_join_q;
    wire [0:0] i_unnamed_c_compstr781_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr781_join_q;
    wire [0:0] i_unnamed_c_compstr797_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr797_join_q;
    wire [0:0] i_unnamed_c_compstr809_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr809_join_q;
    wire [0:0] i_unnamed_c_compstr81_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr81_join_q;
    wire [0:0] i_unnamed_c_compstr825_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr825_join_q;
    wire [0:0] i_unnamed_c_compstr837_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr837_join_q;
    wire [0:0] i_unnamed_c_compstr853_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr853_join_q;
    wire [0:0] i_unnamed_c_compstr865_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr865_join_q;
    wire [0:0] i_unnamed_c_compstr881_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr881_join_q;
    wire [0:0] i_unnamed_c_compstr893_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr893_join_q;
    wire [0:0] i_unnamed_c_compstr909_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr909_join_q;
    wire [0:0] i_unnamed_c_compstr921_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr921_join_q;
    wire [0:0] i_unnamed_c_compstr937_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr937_join_q;
    wire [0:0] i_unnamed_c_compstr949_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr949_join_q;
    wire [0:0] i_unnamed_c_compstr965_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr965_join_q;
    wire [0:0] i_unnamed_c_compstr97_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr97_join_q;
    wire [0:0] i_unnamed_c_compstr977_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr977_join_q;
    wire [0:0] i_unnamed_c_compstr993_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compstr993_join_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ena2;
    wire [12:0] i_value2_i_i157_i3_c_compstr0_trunc_sel_x_merged_bit_select_b;
    wire [50:0] i_value2_i_i157_i3_c_compstr0_trunc_sel_x_merged_bit_select_c;
    reg [0:0] redist0_i_exitcond15_c_compstr3606_cmp_nsign_q_264_q;
    reg [0:0] redist1_valid_fanout_reg0_q_264_q;
    reg [0:0] redist2_i_unnamed_c_compstr993_vt_select_0_b_1_q;
    reg [0:0] redist3_i_unnamed_c_compstr97_vt_select_0_b_1_q;
    reg [0:0] redist4_i_unnamed_c_compstr977_vt_select_0_b_1_q;
    reg [0:0] redist5_i_unnamed_c_compstr965_vt_select_0_b_1_q;
    reg [0:0] redist6_i_unnamed_c_compstr949_vt_select_0_b_1_q;
    reg [0:0] redist7_i_unnamed_c_compstr937_vt_select_0_b_1_q;
    reg [0:0] redist8_i_unnamed_c_compstr921_vt_select_0_b_1_q;
    reg [0:0] redist9_i_unnamed_c_compstr909_vt_select_0_b_1_q;
    reg [0:0] redist10_i_unnamed_c_compstr893_vt_select_0_b_1_q;
    reg [0:0] redist11_i_unnamed_c_compstr881_vt_select_0_b_1_q;
    reg [0:0] redist12_i_unnamed_c_compstr865_vt_select_0_b_1_q;
    reg [0:0] redist13_i_unnamed_c_compstr853_vt_select_0_b_1_q;
    reg [0:0] redist14_i_unnamed_c_compstr837_vt_select_0_b_1_q;
    reg [0:0] redist15_i_unnamed_c_compstr825_vt_select_0_b_1_q;
    reg [0:0] redist16_i_unnamed_c_compstr81_vt_select_0_b_1_q;
    reg [0:0] redist17_i_unnamed_c_compstr809_vt_select_0_b_1_q;
    reg [0:0] redist18_i_unnamed_c_compstr797_vt_select_0_b_1_q;
    reg [0:0] redist19_i_unnamed_c_compstr781_vt_select_0_b_1_q;
    reg [0:0] redist20_i_unnamed_c_compstr769_vt_select_0_b_1_q;
    reg [0:0] redist21_i_unnamed_c_compstr753_vt_select_0_b_1_q;
    reg [0:0] redist22_i_unnamed_c_compstr741_vt_select_0_b_1_q;
    reg [0:0] redist23_i_unnamed_c_compstr725_vt_select_0_b_1_q;
    reg [0:0] redist24_i_unnamed_c_compstr713_vt_select_0_b_1_q;
    reg [0:0] redist25_i_unnamed_c_compstr69_vt_select_0_b_1_q;
    reg [0:0] redist26_i_unnamed_c_compstr697_vt_select_0_b_1_q;
    reg [0:0] redist27_i_unnamed_c_compstr685_vt_select_0_b_1_q;
    reg [0:0] redist28_i_unnamed_c_compstr669_vt_select_0_b_1_q;
    reg [0:0] redist29_i_unnamed_c_compstr657_vt_select_0_b_1_q;
    reg [0:0] redist30_i_unnamed_c_compstr641_vt_select_0_b_1_q;
    reg [0:0] redist31_i_unnamed_c_compstr629_vt_select_0_b_1_q;
    reg [0:0] redist32_i_unnamed_c_compstr613_vt_select_0_b_1_q;
    reg [0:0] redist33_i_unnamed_c_compstr601_vt_select_0_b_1_q;
    reg [0:0] redist34_i_unnamed_c_compstr585_vt_select_0_b_1_q;
    reg [0:0] redist35_i_unnamed_c_compstr573_vt_select_0_b_1_q;
    reg [0:0] redist36_i_unnamed_c_compstr557_vt_select_0_b_1_q;
    reg [0:0] redist37_i_unnamed_c_compstr545_vt_select_0_b_1_q;
    reg [0:0] redist38_i_unnamed_c_compstr53_vt_select_0_b_1_q;
    reg [0:0] redist39_i_unnamed_c_compstr529_vt_select_0_b_1_q;
    reg [0:0] redist40_i_unnamed_c_compstr517_vt_select_0_b_1_q;
    reg [0:0] redist41_i_unnamed_c_compstr501_vt_select_0_b_1_q;
    reg [0:0] redist42_i_unnamed_c_compstr489_vt_select_0_b_1_q;
    reg [0:0] redist43_i_unnamed_c_compstr473_vt_select_0_b_1_q;
    reg [0:0] redist44_i_unnamed_c_compstr461_vt_select_0_b_1_q;
    reg [0:0] redist45_i_unnamed_c_compstr445_vt_select_0_b_1_q;
    reg [0:0] redist46_i_unnamed_c_compstr433_vt_select_0_b_1_q;
    reg [0:0] redist47_i_unnamed_c_compstr417_vt_select_0_b_1_q;
    reg [0:0] redist48_i_unnamed_c_compstr405_vt_select_0_b_1_q;
    reg [0:0] redist49_i_unnamed_c_compstr389_vt_select_0_b_1_q;
    reg [0:0] redist50_i_unnamed_c_compstr377_vt_select_0_b_1_q;
    reg [0:0] redist51_i_unnamed_c_compstr361_vt_select_0_b_1_q;
    reg [0:0] redist52_i_unnamed_c_compstr3597_vt_select_0_b_1_q;
    reg [0:0] redist53_i_unnamed_c_compstr3581_vt_select_0_b_1_q;
    reg [0:0] redist54_i_unnamed_c_compstr3569_vt_select_0_b_1_q;
    reg [0:0] redist55_i_unnamed_c_compstr3553_vt_select_0_b_1_q;
    reg [0:0] redist56_i_unnamed_c_compstr3541_vt_select_0_b_1_q;
    reg [0:0] redist57_i_unnamed_c_compstr3525_vt_select_0_b_1_q;
    reg [0:0] redist58_i_unnamed_c_compstr3513_vt_select_0_b_1_q;
    reg [0:0] redist59_i_unnamed_c_compstr349_vt_select_0_b_1_q;
    reg [0:0] redist60_i_unnamed_c_compstr3497_vt_select_0_b_1_q;
    reg [0:0] redist61_i_unnamed_c_compstr3485_vt_select_0_b_1_q;
    reg [0:0] redist62_i_unnamed_c_compstr3469_vt_select_0_b_1_q;
    reg [0:0] redist63_i_unnamed_c_compstr3457_vt_select_0_b_1_q;
    reg [0:0] redist64_i_unnamed_c_compstr3441_vt_select_0_b_1_q;
    reg [0:0] redist65_i_unnamed_c_compstr3429_vt_select_0_b_1_q;
    reg [0:0] redist66_i_unnamed_c_compstr3413_vt_select_0_b_1_q;
    reg [0:0] redist67_i_unnamed_c_compstr3401_vt_select_0_b_1_q;
    reg [0:0] redist68_i_unnamed_c_compstr3385_vt_select_0_b_1_q;
    reg [0:0] redist69_i_unnamed_c_compstr3373_vt_select_0_b_1_q;
    reg [0:0] redist70_i_unnamed_c_compstr3357_vt_select_0_b_1_q;
    reg [0:0] redist71_i_unnamed_c_compstr3345_vt_select_0_b_1_q;
    reg [0:0] redist72_i_unnamed_c_compstr333_vt_select_0_b_1_q;
    reg [0:0] redist73_i_unnamed_c_compstr3329_vt_select_0_b_1_q;
    reg [0:0] redist74_i_unnamed_c_compstr3317_vt_select_0_b_1_q;
    reg [0:0] redist75_i_unnamed_c_compstr3301_vt_select_0_b_1_q;
    reg [0:0] redist76_i_unnamed_c_compstr3289_vt_select_0_b_1_q;
    reg [0:0] redist77_i_unnamed_c_compstr3273_vt_select_0_b_1_q;
    reg [0:0] redist78_i_unnamed_c_compstr3261_vt_select_0_b_1_q;
    reg [0:0] redist79_i_unnamed_c_compstr3245_vt_select_0_b_1_q;
    reg [0:0] redist80_i_unnamed_c_compstr3233_vt_select_0_b_1_q;
    reg [0:0] redist81_i_unnamed_c_compstr321_vt_select_0_b_1_q;
    reg [0:0] redist82_i_unnamed_c_compstr3217_vt_select_0_b_1_q;
    reg [0:0] redist83_i_unnamed_c_compstr3205_vt_select_0_b_1_q;
    reg [0:0] redist84_i_unnamed_c_compstr3189_vt_select_0_b_1_q;
    reg [0:0] redist85_i_unnamed_c_compstr3177_vt_select_0_b_1_q;
    reg [0:0] redist86_i_unnamed_c_compstr3161_vt_select_0_b_1_q;
    reg [0:0] redist87_i_unnamed_c_compstr3149_vt_select_0_b_1_q;
    reg [0:0] redist88_i_unnamed_c_compstr3133_vt_select_0_b_1_q;
    reg [0:0] redist89_i_unnamed_c_compstr3121_vt_select_0_b_1_q;
    reg [0:0] redist90_i_unnamed_c_compstr3105_vt_select_0_b_1_q;
    reg [0:0] redist91_i_unnamed_c_compstr3093_vt_select_0_b_1_q;
    reg [0:0] redist92_i_unnamed_c_compstr3077_vt_select_0_b_1_q;
    reg [0:0] redist93_i_unnamed_c_compstr3065_vt_select_0_b_1_q;
    reg [0:0] redist94_i_unnamed_c_compstr305_vt_select_0_b_1_q;
    reg [0:0] redist95_i_unnamed_c_compstr3049_vt_select_0_b_1_q;
    reg [0:0] redist96_i_unnamed_c_compstr3037_vt_select_0_b_1_q;
    reg [0:0] redist97_i_unnamed_c_compstr3021_vt_select_0_b_1_q;
    reg [0:0] redist98_i_unnamed_c_compstr3009_vt_select_0_b_1_q;
    reg [0:0] redist99_i_unnamed_c_compstr2993_vt_select_0_b_1_q;
    reg [0:0] redist100_i_unnamed_c_compstr2981_vt_select_0_b_1_q;
    reg [0:0] redist101_i_unnamed_c_compstr2965_vt_select_0_b_1_q;
    reg [0:0] redist102_i_unnamed_c_compstr2953_vt_select_0_b_1_q;
    reg [0:0] redist103_i_unnamed_c_compstr293_vt_select_0_b_1_q;
    reg [0:0] redist104_i_unnamed_c_compstr2937_vt_select_0_b_1_q;
    reg [0:0] redist105_i_unnamed_c_compstr2925_vt_select_0_b_1_q;
    reg [0:0] redist106_i_unnamed_c_compstr2909_vt_select_0_b_1_q;
    reg [0:0] redist107_i_unnamed_c_compstr2897_vt_select_0_b_1_q;
    reg [0:0] redist108_i_unnamed_c_compstr2881_vt_select_0_b_1_q;
    reg [0:0] redist109_i_unnamed_c_compstr2869_vt_select_0_b_1_q;
    reg [0:0] redist110_i_unnamed_c_compstr2853_vt_select_0_b_1_q;
    reg [0:0] redist111_i_unnamed_c_compstr2841_vt_select_0_b_1_q;
    reg [0:0] redist112_i_unnamed_c_compstr2825_vt_select_0_b_1_q;
    reg [0:0] redist113_i_unnamed_c_compstr2813_vt_select_0_b_1_q;
    reg [0:0] redist114_i_unnamed_c_compstr2797_vt_select_0_b_1_q;
    reg [0:0] redist115_i_unnamed_c_compstr2785_vt_select_0_b_1_q;
    reg [0:0] redist116_i_unnamed_c_compstr277_vt_select_0_b_1_q;
    reg [0:0] redist117_i_unnamed_c_compstr2769_vt_select_0_b_1_q;
    reg [0:0] redist118_i_unnamed_c_compstr2757_vt_select_0_b_1_q;
    reg [0:0] redist119_i_unnamed_c_compstr2741_vt_select_0_b_1_q;
    reg [0:0] redist120_i_unnamed_c_compstr2729_vt_select_0_b_1_q;
    reg [0:0] redist121_i_unnamed_c_compstr2713_vt_select_0_b_1_q;
    reg [0:0] redist122_i_unnamed_c_compstr2701_vt_select_0_b_1_q;
    reg [0:0] redist123_i_unnamed_c_compstr2685_vt_select_0_b_1_q;
    reg [0:0] redist124_i_unnamed_c_compstr2673_vt_select_0_b_1_q;
    reg [0:0] redist125_i_unnamed_c_compstr265_vt_select_0_b_1_q;
    reg [0:0] redist126_i_unnamed_c_compstr2657_vt_select_0_b_1_q;
    reg [0:0] redist127_i_unnamed_c_compstr2645_vt_select_0_b_1_q;
    reg [0:0] redist128_i_unnamed_c_compstr2629_vt_select_0_b_1_q;
    reg [0:0] redist129_i_unnamed_c_compstr2617_vt_select_0_b_1_q;
    reg [0:0] redist130_i_unnamed_c_compstr2601_vt_select_0_b_1_q;
    reg [0:0] redist131_i_unnamed_c_compstr2589_vt_select_0_b_1_q;
    reg [0:0] redist132_i_unnamed_c_compstr2573_vt_select_0_b_1_q;
    reg [0:0] redist133_i_unnamed_c_compstr2561_vt_select_0_b_1_q;
    reg [0:0] redist134_i_unnamed_c_compstr2545_vt_select_0_b_1_q;
    reg [0:0] redist135_i_unnamed_c_compstr2533_vt_select_0_b_1_q;
    reg [0:0] redist136_i_unnamed_c_compstr2517_vt_select_0_b_1_q;
    reg [0:0] redist137_i_unnamed_c_compstr2505_vt_select_0_b_1_q;
    reg [0:0] redist138_i_unnamed_c_compstr249_vt_select_0_b_1_q;
    reg [0:0] redist139_i_unnamed_c_compstr2489_vt_select_0_b_1_q;
    reg [0:0] redist140_i_unnamed_c_compstr2477_vt_select_0_b_1_q;
    reg [0:0] redist141_i_unnamed_c_compstr2461_vt_select_0_b_1_q;
    reg [0:0] redist142_i_unnamed_c_compstr2449_vt_select_0_b_1_q;
    reg [0:0] redist143_i_unnamed_c_compstr2433_vt_select_0_b_1_q;
    reg [0:0] redist144_i_unnamed_c_compstr2421_vt_select_0_b_1_q;
    reg [0:0] redist145_i_unnamed_c_compstr2405_vt_select_0_b_1_q;
    reg [0:0] redist146_i_unnamed_c_compstr2393_vt_select_0_b_1_q;
    reg [0:0] redist147_i_unnamed_c_compstr237_vt_select_0_b_1_q;
    reg [0:0] redist148_i_unnamed_c_compstr2377_vt_select_0_b_1_q;
    reg [0:0] redist149_i_unnamed_c_compstr2365_vt_select_0_b_1_q;
    reg [0:0] redist150_i_unnamed_c_compstr2349_vt_select_0_b_1_q;
    reg [0:0] redist151_i_unnamed_c_compstr2337_vt_select_0_b_1_q;
    reg [0:0] redist152_i_unnamed_c_compstr2321_vt_select_0_b_1_q;
    reg [0:0] redist153_i_unnamed_c_compstr2309_vt_select_0_b_1_q;
    reg [0:0] redist154_i_unnamed_c_compstr2293_vt_select_0_b_1_q;
    reg [0:0] redist155_i_unnamed_c_compstr2281_vt_select_0_b_1_q;
    reg [0:0] redist156_i_unnamed_c_compstr2265_vt_select_0_b_1_q;
    reg [0:0] redist157_i_unnamed_c_compstr2253_vt_select_0_b_1_q;
    reg [0:0] redist158_i_unnamed_c_compstr2237_vt_select_0_b_1_q;
    reg [0:0] redist159_i_unnamed_c_compstr2225_vt_select_0_b_1_q;
    reg [0:0] redist160_i_unnamed_c_compstr221_vt_select_0_b_1_q;
    reg [0:0] redist161_i_unnamed_c_compstr2209_vt_select_0_b_1_q;
    reg [0:0] redist162_i_unnamed_c_compstr2197_vt_select_0_b_1_q;
    reg [0:0] redist163_i_unnamed_c_compstr2181_vt_select_0_b_1_q;
    reg [0:0] redist164_i_unnamed_c_compstr2169_vt_select_0_b_1_q;
    reg [0:0] redist165_i_unnamed_c_compstr2153_vt_select_0_b_1_q;
    reg [0:0] redist166_i_unnamed_c_compstr2141_vt_select_0_b_1_q;
    reg [0:0] redist167_i_unnamed_c_compstr2125_vt_select_0_b_1_q;
    reg [0:0] redist168_i_unnamed_c_compstr2113_vt_select_0_b_1_q;
    reg [0:0] redist169_i_unnamed_c_compstr209_vt_select_0_b_1_q;
    reg [0:0] redist170_i_unnamed_c_compstr2097_vt_select_0_b_1_q;
    reg [0:0] redist171_i_unnamed_c_compstr2085_vt_select_0_b_1_q;
    reg [0:0] redist172_i_unnamed_c_compstr2069_vt_select_0_b_1_q;
    reg [0:0] redist173_i_unnamed_c_compstr2057_vt_select_0_b_1_q;
    reg [0:0] redist174_i_unnamed_c_compstr2041_vt_select_0_b_1_q;
    reg [0:0] redist175_i_unnamed_c_compstr2029_vt_select_0_b_1_q;
    reg [0:0] redist176_i_unnamed_c_compstr2013_vt_select_0_b_1_q;
    reg [0:0] redist177_i_unnamed_c_compstr2001_vt_select_0_b_1_q;
    reg [0:0] redist178_i_unnamed_c_compstr1985_vt_select_0_b_1_q;
    reg [0:0] redist179_i_unnamed_c_compstr1973_vt_select_0_b_1_q;
    reg [0:0] redist180_i_unnamed_c_compstr1957_vt_select_0_b_1_q;
    reg [0:0] redist181_i_unnamed_c_compstr1945_vt_select_0_b_1_q;
    reg [0:0] redist182_i_unnamed_c_compstr193_vt_select_0_b_1_q;
    reg [0:0] redist183_i_unnamed_c_compstr1929_vt_select_0_b_1_q;
    reg [0:0] redist184_i_unnamed_c_compstr1917_vt_select_0_b_1_q;
    reg [0:0] redist185_i_unnamed_c_compstr1901_vt_select_0_b_1_q;
    reg [0:0] redist186_i_unnamed_c_compstr1889_vt_select_0_b_1_q;
    reg [0:0] redist187_i_unnamed_c_compstr1873_vt_select_0_b_1_q;
    reg [0:0] redist188_i_unnamed_c_compstr1861_vt_select_0_b_1_q;
    reg [0:0] redist189_i_unnamed_c_compstr1845_vt_select_0_b_1_q;
    reg [0:0] redist190_i_unnamed_c_compstr1833_vt_select_0_b_1_q;
    reg [0:0] redist191_i_unnamed_c_compstr181_vt_select_0_b_1_q;
    reg [0:0] redist192_i_unnamed_c_compstr1817_vt_select_0_b_1_q;
    reg [0:0] redist193_i_unnamed_c_compstr1805_vt_select_0_b_1_q;
    reg [0:0] redist194_i_unnamed_c_compstr1789_vt_select_0_b_1_q;
    reg [0:0] redist195_i_unnamed_c_compstr1777_vt_select_0_b_1_q;
    reg [0:0] redist196_i_unnamed_c_compstr1761_vt_select_0_b_1_q;
    reg [0:0] redist197_i_unnamed_c_compstr1749_vt_select_0_b_1_q;
    reg [0:0] redist198_i_unnamed_c_compstr1733_vt_select_0_b_1_q;
    reg [0:0] redist199_i_unnamed_c_compstr1721_vt_select_0_b_1_q;
    reg [0:0] redist200_i_unnamed_c_compstr1705_vt_select_0_b_1_q;
    reg [0:0] redist201_i_unnamed_c_compstr1693_vt_select_0_b_1_q;
    reg [0:0] redist202_i_unnamed_c_compstr1677_vt_select_0_b_1_q;
    reg [0:0] redist203_i_unnamed_c_compstr1665_vt_select_0_b_1_q;
    reg [0:0] redist204_i_unnamed_c_compstr165_vt_select_0_b_1_q;
    reg [0:0] redist205_i_unnamed_c_compstr1649_vt_select_0_b_1_q;
    reg [0:0] redist206_i_unnamed_c_compstr1637_vt_select_0_b_1_q;
    reg [0:0] redist207_i_unnamed_c_compstr1621_vt_select_0_b_1_q;
    reg [0:0] redist208_i_unnamed_c_compstr1609_vt_select_0_b_1_q;
    reg [0:0] redist209_i_unnamed_c_compstr1593_vt_select_0_b_1_q;
    reg [0:0] redist210_i_unnamed_c_compstr1581_vt_select_0_b_1_q;
    reg [0:0] redist211_i_unnamed_c_compstr1565_vt_select_0_b_1_q;
    reg [0:0] redist212_i_unnamed_c_compstr1553_vt_select_0_b_1_q;
    reg [0:0] redist213_i_unnamed_c_compstr153_vt_select_0_b_1_q;
    reg [0:0] redist214_i_unnamed_c_compstr1537_vt_select_0_b_1_q;
    reg [0:0] redist215_i_unnamed_c_compstr1525_vt_select_0_b_1_q;
    reg [0:0] redist216_i_unnamed_c_compstr1509_vt_select_0_b_1_q;
    reg [0:0] redist217_i_unnamed_c_compstr1497_vt_select_0_b_1_q;
    reg [0:0] redist218_i_unnamed_c_compstr1481_vt_select_0_b_1_q;
    reg [0:0] redist219_i_unnamed_c_compstr1469_vt_select_0_b_1_q;
    reg [0:0] redist220_i_unnamed_c_compstr1453_vt_select_0_b_1_q;
    reg [0:0] redist221_i_unnamed_c_compstr1441_vt_select_0_b_1_q;
    reg [0:0] redist222_i_unnamed_c_compstr1425_vt_select_0_b_1_q;
    reg [0:0] redist223_i_unnamed_c_compstr1413_vt_select_0_b_1_q;
    reg [0:0] redist224_i_unnamed_c_compstr1397_vt_select_0_b_1_q;
    reg [0:0] redist225_i_unnamed_c_compstr1385_vt_select_0_b_1_q;
    reg [0:0] redist226_i_unnamed_c_compstr137_vt_select_0_b_1_q;
    reg [0:0] redist227_i_unnamed_c_compstr1369_vt_select_0_b_1_q;
    reg [0:0] redist228_i_unnamed_c_compstr1357_vt_select_0_b_1_q;
    reg [0:0] redist229_i_unnamed_c_compstr1341_vt_select_0_b_1_q;
    reg [0:0] redist230_i_unnamed_c_compstr1329_vt_select_0_b_1_q;
    reg [0:0] redist231_i_unnamed_c_compstr1313_vt_select_0_b_1_q;
    reg [0:0] redist232_i_unnamed_c_compstr1301_vt_select_0_b_1_q;
    reg [0:0] redist233_i_unnamed_c_compstr1285_vt_select_0_b_1_q;
    reg [0:0] redist234_i_unnamed_c_compstr1273_vt_select_0_b_1_q;
    reg [0:0] redist235_i_unnamed_c_compstr125_vt_select_0_b_1_q;
    reg [0:0] redist236_i_unnamed_c_compstr1257_vt_select_0_b_1_q;
    reg [0:0] redist237_i_unnamed_c_compstr1245_vt_select_0_b_1_q;
    reg [0:0] redist238_i_unnamed_c_compstr1229_vt_select_0_b_1_q;
    reg [0:0] redist239_i_unnamed_c_compstr1217_vt_select_0_b_1_q;
    reg [0:0] redist240_i_unnamed_c_compstr1201_vt_select_0_b_1_q;
    reg [0:0] redist241_i_unnamed_c_compstr1189_vt_select_0_b_1_q;
    reg [0:0] redist242_i_unnamed_c_compstr1173_vt_select_0_b_1_q;
    reg [0:0] redist243_i_unnamed_c_compstr1161_vt_select_0_b_1_q;
    reg [0:0] redist244_i_unnamed_c_compstr1145_vt_select_0_b_1_q;
    reg [0:0] redist245_i_unnamed_c_compstr1133_vt_select_0_b_1_q;
    reg [0:0] redist246_i_unnamed_c_compstr1117_vt_select_0_b_1_q;
    reg [0:0] redist247_i_unnamed_c_compstr1105_vt_select_0_b_1_q;
    reg [0:0] redist248_i_unnamed_c_compstr109_vt_select_0_b_1_q;
    reg [0:0] redist249_i_unnamed_c_compstr1089_vt_select_0_b_1_q;
    reg [0:0] redist250_i_unnamed_c_compstr1077_vt_select_0_b_1_q;
    reg [0:0] redist251_i_unnamed_c_compstr1061_vt_select_0_b_1_q;
    reg [0:0] redist252_i_unnamed_c_compstr1049_vt_select_0_b_1_q;
    reg [0:0] redist253_i_unnamed_c_compstr1033_vt_select_0_b_1_q;
    reg [0:0] redist254_i_unnamed_c_compstr1021_vt_select_0_b_1_q;
    reg [0:0] redist255_i_unnamed_c_compstr1005_vt_select_0_b_1_q;
    reg [15:0] redist256_i_shl_i_i_i_i_i_i_9_c_compstr287_vt_select_28_b_1_q;
    reg [15:0] redist257_i_shl_i_i_i_i_i_i_99_c_compstr2807_vt_select_28_b_1_q;
    reg [15:0] redist258_i_shl_i_i_i_i_i_i_98_c_compstr2779_vt_select_28_b_1_q;
    reg [15:0] redist259_i_shl_i_i_i_i_i_i_97_c_compstr2751_vt_select_28_b_1_q;
    reg [15:0] redist260_i_shl_i_i_i_i_i_i_96_c_compstr2723_vt_select_28_b_1_q;
    reg [15:0] redist261_i_shl_i_i_i_i_i_i_95_c_compstr2695_vt_select_28_b_1_q;
    reg [15:0] redist262_i_shl_i_i_i_i_i_i_94_c_compstr2667_vt_select_28_b_1_q;
    reg [15:0] redist263_i_shl_i_i_i_i_i_i_93_c_compstr2639_vt_select_28_b_1_q;
    reg [15:0] redist264_i_shl_i_i_i_i_i_i_92_c_compstr2611_vt_select_28_b_1_q;
    reg [15:0] redist265_i_shl_i_i_i_i_i_i_91_c_compstr2583_vt_select_28_b_1_q;
    reg [15:0] redist266_i_shl_i_i_i_i_i_i_90_c_compstr2555_vt_select_28_b_1_q;
    reg [15:0] redist267_i_shl_i_i_i_i_i_i_8_c_compstr259_vt_select_28_b_1_q;
    reg [15:0] redist268_i_shl_i_i_i_i_i_i_89_c_compstr2527_vt_select_28_b_1_q;
    reg [15:0] redist269_i_shl_i_i_i_i_i_i_88_c_compstr2499_vt_select_28_b_1_q;
    reg [15:0] redist270_i_shl_i_i_i_i_i_i_87_c_compstr2471_vt_select_28_b_1_q;
    reg [15:0] redist271_i_shl_i_i_i_i_i_i_86_c_compstr2443_vt_select_28_b_1_q;
    reg [15:0] redist272_i_shl_i_i_i_i_i_i_85_c_compstr2415_vt_select_28_b_1_q;
    reg [15:0] redist273_i_shl_i_i_i_i_i_i_84_c_compstr2387_vt_select_28_b_1_q;
    reg [15:0] redist274_i_shl_i_i_i_i_i_i_83_c_compstr2359_vt_select_28_b_1_q;
    reg [15:0] redist275_i_shl_i_i_i_i_i_i_82_c_compstr2331_vt_select_28_b_1_q;
    reg [15:0] redist276_i_shl_i_i_i_i_i_i_81_c_compstr2303_vt_select_28_b_1_q;
    reg [15:0] redist277_i_shl_i_i_i_i_i_i_80_c_compstr2275_vt_select_28_b_1_q;
    reg [15:0] redist278_i_shl_i_i_i_i_i_i_7_c_compstr231_vt_select_28_b_1_q;
    reg [15:0] redist279_i_shl_i_i_i_i_i_i_79_c_compstr2247_vt_select_28_b_1_q;
    reg [15:0] redist280_i_shl_i_i_i_i_i_i_78_c_compstr2219_vt_select_28_b_1_q;
    reg [15:0] redist281_i_shl_i_i_i_i_i_i_77_c_compstr2191_vt_select_28_b_1_q;
    reg [15:0] redist282_i_shl_i_i_i_i_i_i_76_c_compstr2163_vt_select_28_b_1_q;
    reg [15:0] redist283_i_shl_i_i_i_i_i_i_75_c_compstr2135_vt_select_28_b_1_q;
    reg [15:0] redist284_i_shl_i_i_i_i_i_i_74_c_compstr2107_vt_select_28_b_1_q;
    reg [15:0] redist285_i_shl_i_i_i_i_i_i_73_c_compstr2079_vt_select_28_b_1_q;
    reg [15:0] redist286_i_shl_i_i_i_i_i_i_72_c_compstr2051_vt_select_28_b_1_q;
    reg [15:0] redist287_i_shl_i_i_i_i_i_i_71_c_compstr2023_vt_select_28_b_1_q;
    reg [15:0] redist288_i_shl_i_i_i_i_i_i_70_c_compstr1995_vt_select_28_b_1_q;
    reg [15:0] redist289_i_shl_i_i_i_i_i_i_6_c_compstr203_vt_select_28_b_1_q;
    reg [15:0] redist290_i_shl_i_i_i_i_i_i_69_c_compstr1967_vt_select_28_b_1_q;
    reg [15:0] redist291_i_shl_i_i_i_i_i_i_68_c_compstr1939_vt_select_28_b_1_q;
    reg [15:0] redist292_i_shl_i_i_i_i_i_i_67_c_compstr1911_vt_select_28_b_1_q;
    reg [15:0] redist293_i_shl_i_i_i_i_i_i_66_c_compstr1883_vt_select_28_b_1_q;
    reg [15:0] redist294_i_shl_i_i_i_i_i_i_65_c_compstr1855_vt_select_28_b_1_q;
    reg [15:0] redist295_i_shl_i_i_i_i_i_i_64_c_compstr1827_vt_select_28_b_1_q;
    reg [15:0] redist296_i_shl_i_i_i_i_i_i_63_c_compstr1799_vt_select_28_b_1_q;
    reg [15:0] redist297_i_shl_i_i_i_i_i_i_62_c_compstr1771_vt_select_28_b_1_q;
    reg [15:0] redist298_i_shl_i_i_i_i_i_i_61_c_compstr1743_vt_select_28_b_1_q;
    reg [15:0] redist299_i_shl_i_i_i_i_i_i_60_c_compstr1715_vt_select_28_b_1_q;
    reg [15:0] redist300_i_shl_i_i_i_i_i_i_5_c_compstr175_vt_select_28_b_1_q;
    reg [15:0] redist301_i_shl_i_i_i_i_i_i_59_c_compstr1687_vt_select_28_b_1_q;
    reg [15:0] redist302_i_shl_i_i_i_i_i_i_58_c_compstr1659_vt_select_28_b_1_q;
    reg [15:0] redist303_i_shl_i_i_i_i_i_i_57_c_compstr1631_vt_select_28_b_1_q;
    reg [15:0] redist304_i_shl_i_i_i_i_i_i_56_c_compstr1603_vt_select_28_b_1_q;
    reg [15:0] redist305_i_shl_i_i_i_i_i_i_55_c_compstr1575_vt_select_28_b_1_q;
    reg [15:0] redist306_i_shl_i_i_i_i_i_i_54_c_compstr1547_vt_select_28_b_1_q;
    reg [15:0] redist307_i_shl_i_i_i_i_i_i_53_c_compstr1519_vt_select_28_b_1_q;
    reg [15:0] redist308_i_shl_i_i_i_i_i_i_52_c_compstr1491_vt_select_28_b_1_q;
    reg [15:0] redist309_i_shl_i_i_i_i_i_i_51_c_compstr1463_vt_select_28_b_1_q;
    reg [15:0] redist310_i_shl_i_i_i_i_i_i_50_c_compstr1435_vt_select_28_b_1_q;
    reg [15:0] redist311_i_shl_i_i_i_i_i_i_4_c_compstr147_vt_select_28_b_1_q;
    reg [15:0] redist312_i_shl_i_i_i_i_i_i_49_c_compstr1407_vt_select_28_b_1_q;
    reg [15:0] redist313_i_shl_i_i_i_i_i_i_48_c_compstr1379_vt_select_28_b_1_q;
    reg [15:0] redist314_i_shl_i_i_i_i_i_i_47_c_compstr1351_vt_select_28_b_1_q;
    reg [15:0] redist315_i_shl_i_i_i_i_i_i_46_c_compstr1323_vt_select_28_b_1_q;
    reg [15:0] redist316_i_shl_i_i_i_i_i_i_45_c_compstr1295_vt_select_28_b_1_q;
    reg [15:0] redist317_i_shl_i_i_i_i_i_i_44_c_compstr1267_vt_select_28_b_1_q;
    reg [15:0] redist318_i_shl_i_i_i_i_i_i_43_c_compstr1239_vt_select_28_b_1_q;
    reg [15:0] redist319_i_shl_i_i_i_i_i_i_42_c_compstr1211_vt_select_28_b_1_q;
    reg [15:0] redist320_i_shl_i_i_i_i_i_i_41_c_compstr1183_vt_select_28_b_1_q;
    reg [15:0] redist321_i_shl_i_i_i_i_i_i_40_c_compstr1155_vt_select_28_b_1_q;
    reg [15:0] redist322_i_shl_i_i_i_i_i_i_3_c_compstr119_vt_select_28_b_1_q;
    reg [15:0] redist323_i_shl_i_i_i_i_i_i_39_c_compstr1127_vt_select_28_b_1_q;
    reg [15:0] redist324_i_shl_i_i_i_i_i_i_38_c_compstr1099_vt_select_28_b_1_q;
    reg [15:0] redist325_i_shl_i_i_i_i_i_i_37_c_compstr1071_vt_select_28_b_1_q;
    reg [15:0] redist326_i_shl_i_i_i_i_i_i_36_c_compstr1043_vt_select_28_b_1_q;
    reg [15:0] redist327_i_shl_i_i_i_i_i_i_35_c_compstr1015_vt_select_28_b_1_q;
    reg [15:0] redist328_i_shl_i_i_i_i_i_i_34_c_compstr987_vt_select_28_b_1_q;
    reg [15:0] redist329_i_shl_i_i_i_i_i_i_33_c_compstr959_vt_select_28_b_1_q;
    reg [15:0] redist330_i_shl_i_i_i_i_i_i_32_c_compstr931_vt_select_28_b_1_q;
    reg [15:0] redist331_i_shl_i_i_i_i_i_i_31_c_compstr903_vt_select_28_b_1_q;
    reg [15:0] redist332_i_shl_i_i_i_i_i_i_30_c_compstr875_vt_select_28_b_1_q;
    reg [15:0] redist333_i_shl_i_i_i_i_i_i_2_c_compstr91_vt_select_28_b_1_q;
    reg [15:0] redist334_i_shl_i_i_i_i_i_i_29_c_compstr847_vt_select_28_b_1_q;
    reg [15:0] redist335_i_shl_i_i_i_i_i_i_28_c_compstr819_vt_select_28_b_1_q;
    reg [15:0] redist336_i_shl_i_i_i_i_i_i_27_c_compstr791_vt_select_28_b_1_q;
    reg [15:0] redist337_i_shl_i_i_i_i_i_i_26_c_compstr763_vt_select_28_b_1_q;
    reg [15:0] redist338_i_shl_i_i_i_i_i_i_25_c_compstr735_vt_select_28_b_1_q;
    reg [15:0] redist339_i_shl_i_i_i_i_i_i_24_c_compstr707_vt_select_28_b_1_q;
    reg [15:0] redist340_i_shl_i_i_i_i_i_i_23_c_compstr679_vt_select_28_b_1_q;
    reg [15:0] redist341_i_shl_i_i_i_i_i_i_22_c_compstr651_vt_select_28_b_1_q;
    reg [15:0] redist342_i_shl_i_i_i_i_i_i_21_c_compstr623_vt_select_28_b_1_q;
    reg [15:0] redist343_i_shl_i_i_i_i_i_i_20_c_compstr595_vt_select_28_b_1_q;
    reg [15:0] redist344_i_shl_i_i_i_i_i_i_1_c_compstr63_vt_select_28_b_1_q;
    reg [15:0] redist345_i_shl_i_i_i_i_i_i_19_c_compstr567_vt_select_28_b_1_q;
    reg [15:0] redist346_i_shl_i_i_i_i_i_i_18_c_compstr539_vt_select_28_b_1_q;
    reg [15:0] redist347_i_shl_i_i_i_i_i_i_17_c_compstr511_vt_select_28_b_1_q;
    reg [15:0] redist348_i_shl_i_i_i_i_i_i_16_c_compstr483_vt_select_28_b_1_q;
    reg [15:0] redist349_i_shl_i_i_i_i_i_i_15_c_compstr455_vt_select_28_b_1_q;
    reg [15:0] redist350_i_shl_i_i_i_i_i_i_14_c_compstr427_vt_select_28_b_1_q;
    reg [15:0] redist351_i_shl_i_i_i_i_i_i_13_c_compstr399_vt_select_28_b_1_q;
    reg [15:0] redist352_i_shl_i_i_i_i_i_i_12_c_compstr371_vt_select_28_b_1_q;
    reg [15:0] redist353_i_shl_i_i_i_i_i_i_127_c_compstr3591_vt_select_28_b_1_q;
    reg [15:0] redist354_i_shl_i_i_i_i_i_i_126_c_compstr3563_vt_select_28_b_1_q;
    reg [15:0] redist355_i_shl_i_i_i_i_i_i_125_c_compstr3535_vt_select_28_b_1_q;
    reg [15:0] redist356_i_shl_i_i_i_i_i_i_124_c_compstr3507_vt_select_28_b_1_q;
    reg [15:0] redist357_i_shl_i_i_i_i_i_i_123_c_compstr3479_vt_select_28_b_1_q;
    reg [15:0] redist358_i_shl_i_i_i_i_i_i_122_c_compstr3451_vt_select_28_b_1_q;
    reg [15:0] redist359_i_shl_i_i_i_i_i_i_121_c_compstr3423_vt_select_28_b_1_q;
    reg [15:0] redist360_i_shl_i_i_i_i_i_i_120_c_compstr3395_vt_select_28_b_1_q;
    reg [15:0] redist361_i_shl_i_i_i_i_i_i_11_c_compstr343_vt_select_28_b_1_q;
    reg [15:0] redist362_i_shl_i_i_i_i_i_i_119_c_compstr3367_vt_select_28_b_1_q;
    reg [15:0] redist363_i_shl_i_i_i_i_i_i_118_c_compstr3339_vt_select_28_b_1_q;
    reg [15:0] redist364_i_shl_i_i_i_i_i_i_117_c_compstr3311_vt_select_28_b_1_q;
    reg [15:0] redist365_i_shl_i_i_i_i_i_i_116_c_compstr3283_vt_select_28_b_1_q;
    reg [15:0] redist366_i_shl_i_i_i_i_i_i_115_c_compstr3255_vt_select_28_b_1_q;
    reg [15:0] redist367_i_shl_i_i_i_i_i_i_114_c_compstr3227_vt_select_28_b_1_q;
    reg [15:0] redist368_i_shl_i_i_i_i_i_i_113_c_compstr3199_vt_select_28_b_1_q;
    reg [15:0] redist369_i_shl_i_i_i_i_i_i_112_c_compstr3171_vt_select_28_b_1_q;
    reg [15:0] redist370_i_shl_i_i_i_i_i_i_111_c_compstr3143_vt_select_28_b_1_q;
    reg [15:0] redist371_i_shl_i_i_i_i_i_i_110_c_compstr3115_vt_select_28_b_1_q;
    reg [15:0] redist372_i_shl_i_i_i_i_i_i_10_c_compstr315_vt_select_28_b_1_q;
    reg [15:0] redist373_i_shl_i_i_i_i_i_i_109_c_compstr3087_vt_select_28_b_1_q;
    reg [15:0] redist374_i_shl_i_i_i_i_i_i_108_c_compstr3059_vt_select_28_b_1_q;
    reg [15:0] redist375_i_shl_i_i_i_i_i_i_107_c_compstr3031_vt_select_28_b_1_q;
    reg [15:0] redist376_i_shl_i_i_i_i_i_i_106_c_compstr3003_vt_select_28_b_1_q;
    reg [15:0] redist377_i_shl_i_i_i_i_i_i_105_c_compstr2975_vt_select_28_b_1_q;
    reg [15:0] redist378_i_shl_i_i_i_i_i_i_104_c_compstr2947_vt_select_28_b_1_q;
    reg [15:0] redist379_i_shl_i_i_i_i_i_i_103_c_compstr2919_vt_select_28_b_1_q;
    reg [15:0] redist380_i_shl_i_i_i_i_i_i_102_c_compstr2891_vt_select_28_b_1_q;
    reg [15:0] redist381_i_shl_i_i_i_i_i_i_101_c_compstr2863_vt_select_28_b_1_q;
    reg [15:0] redist382_i_shl_i_i_i_i_i_i_100_c_compstr2835_vt_select_28_b_1_q;
    reg [15:0] redist383_i_shl_i_i_i_i_i77_i_9_c_compstr271_vt_select_28_b_1_q;
    reg [15:0] redist384_i_shl_i_i_i_i_i77_i_99_c_compstr2791_vt_select_28_b_1_q;
    reg [15:0] redist385_i_shl_i_i_i_i_i77_i_98_c_compstr2763_vt_select_28_b_1_q;
    reg [15:0] redist386_i_shl_i_i_i_i_i77_i_97_c_compstr2735_vt_select_28_b_1_q;
    reg [15:0] redist387_i_shl_i_i_i_i_i77_i_96_c_compstr2707_vt_select_28_b_1_q;
    reg [15:0] redist388_i_shl_i_i_i_i_i77_i_95_c_compstr2679_vt_select_28_b_1_q;
    reg [15:0] redist389_i_shl_i_i_i_i_i77_i_94_c_compstr2651_vt_select_28_b_1_q;
    reg [15:0] redist390_i_shl_i_i_i_i_i77_i_93_c_compstr2623_vt_select_28_b_1_q;
    reg [15:0] redist391_i_shl_i_i_i_i_i77_i_92_c_compstr2595_vt_select_28_b_1_q;
    reg [15:0] redist392_i_shl_i_i_i_i_i77_i_91_c_compstr2567_vt_select_28_b_1_q;
    reg [15:0] redist393_i_shl_i_i_i_i_i77_i_90_c_compstr2539_vt_select_28_b_1_q;
    reg [15:0] redist394_i_shl_i_i_i_i_i77_i_8_c_compstr243_vt_select_28_b_1_q;
    reg [15:0] redist395_i_shl_i_i_i_i_i77_i_89_c_compstr2511_vt_select_28_b_1_q;
    reg [15:0] redist396_i_shl_i_i_i_i_i77_i_88_c_compstr2483_vt_select_28_b_1_q;
    reg [15:0] redist397_i_shl_i_i_i_i_i77_i_87_c_compstr2455_vt_select_28_b_1_q;
    reg [15:0] redist398_i_shl_i_i_i_i_i77_i_86_c_compstr2427_vt_select_28_b_1_q;
    reg [15:0] redist399_i_shl_i_i_i_i_i77_i_85_c_compstr2399_vt_select_28_b_1_q;
    reg [15:0] redist400_i_shl_i_i_i_i_i77_i_84_c_compstr2371_vt_select_28_b_1_q;
    reg [15:0] redist401_i_shl_i_i_i_i_i77_i_83_c_compstr2343_vt_select_28_b_1_q;
    reg [15:0] redist402_i_shl_i_i_i_i_i77_i_82_c_compstr2315_vt_select_28_b_1_q;
    reg [15:0] redist403_i_shl_i_i_i_i_i77_i_81_c_compstr2287_vt_select_28_b_1_q;
    reg [15:0] redist404_i_shl_i_i_i_i_i77_i_80_c_compstr2259_vt_select_28_b_1_q;
    reg [15:0] redist405_i_shl_i_i_i_i_i77_i_7_c_compstr215_vt_select_28_b_1_q;
    reg [15:0] redist406_i_shl_i_i_i_i_i77_i_79_c_compstr2231_vt_select_28_b_1_q;
    reg [15:0] redist407_i_shl_i_i_i_i_i77_i_78_c_compstr2203_vt_select_28_b_1_q;
    reg [15:0] redist408_i_shl_i_i_i_i_i77_i_77_c_compstr2175_vt_select_28_b_1_q;
    reg [15:0] redist409_i_shl_i_i_i_i_i77_i_76_c_compstr2147_vt_select_28_b_1_q;
    reg [15:0] redist410_i_shl_i_i_i_i_i77_i_75_c_compstr2119_vt_select_28_b_1_q;
    reg [15:0] redist411_i_shl_i_i_i_i_i77_i_74_c_compstr2091_vt_select_28_b_1_q;
    reg [15:0] redist412_i_shl_i_i_i_i_i77_i_73_c_compstr2063_vt_select_28_b_1_q;
    reg [15:0] redist413_i_shl_i_i_i_i_i77_i_72_c_compstr2035_vt_select_28_b_1_q;
    reg [15:0] redist414_i_shl_i_i_i_i_i77_i_71_c_compstr2007_vt_select_28_b_1_q;
    reg [15:0] redist415_i_shl_i_i_i_i_i77_i_70_c_compstr1979_vt_select_28_b_1_q;
    reg [15:0] redist416_i_shl_i_i_i_i_i77_i_6_c_compstr187_vt_select_28_b_1_q;
    reg [15:0] redist417_i_shl_i_i_i_i_i77_i_69_c_compstr1951_vt_select_28_b_1_q;
    reg [15:0] redist418_i_shl_i_i_i_i_i77_i_68_c_compstr1923_vt_select_28_b_1_q;
    reg [15:0] redist419_i_shl_i_i_i_i_i77_i_67_c_compstr1895_vt_select_28_b_1_q;
    reg [15:0] redist420_i_shl_i_i_i_i_i77_i_66_c_compstr1867_vt_select_28_b_1_q;
    reg [15:0] redist421_i_shl_i_i_i_i_i77_i_65_c_compstr1839_vt_select_28_b_1_q;
    reg [15:0] redist422_i_shl_i_i_i_i_i77_i_64_c_compstr1811_vt_select_28_b_1_q;
    reg [15:0] redist423_i_shl_i_i_i_i_i77_i_63_c_compstr1783_vt_select_28_b_1_q;
    reg [15:0] redist424_i_shl_i_i_i_i_i77_i_62_c_compstr1755_vt_select_28_b_1_q;
    reg [15:0] redist425_i_shl_i_i_i_i_i77_i_61_c_compstr1727_vt_select_28_b_1_q;
    reg [15:0] redist426_i_shl_i_i_i_i_i77_i_60_c_compstr1699_vt_select_28_b_1_q;
    reg [15:0] redist427_i_shl_i_i_i_i_i77_i_5_c_compstr159_vt_select_28_b_1_q;
    reg [15:0] redist428_i_shl_i_i_i_i_i77_i_59_c_compstr1671_vt_select_28_b_1_q;
    reg [15:0] redist429_i_shl_i_i_i_i_i77_i_58_c_compstr1643_vt_select_28_b_1_q;
    reg [15:0] redist430_i_shl_i_i_i_i_i77_i_57_c_compstr1615_vt_select_28_b_1_q;
    reg [15:0] redist431_i_shl_i_i_i_i_i77_i_56_c_compstr1587_vt_select_28_b_1_q;
    reg [15:0] redist432_i_shl_i_i_i_i_i77_i_55_c_compstr1559_vt_select_28_b_1_q;
    reg [15:0] redist433_i_shl_i_i_i_i_i77_i_54_c_compstr1531_vt_select_28_b_1_q;
    reg [15:0] redist434_i_shl_i_i_i_i_i77_i_53_c_compstr1503_vt_select_28_b_1_q;
    reg [15:0] redist435_i_shl_i_i_i_i_i77_i_52_c_compstr1475_vt_select_28_b_1_q;
    reg [15:0] redist436_i_shl_i_i_i_i_i77_i_51_c_compstr1447_vt_select_28_b_1_q;
    reg [15:0] redist437_i_shl_i_i_i_i_i77_i_50_c_compstr1419_vt_select_28_b_1_q;
    reg [15:0] redist438_i_shl_i_i_i_i_i77_i_4_c_compstr131_vt_select_28_b_1_q;
    reg [15:0] redist439_i_shl_i_i_i_i_i77_i_49_c_compstr1391_vt_select_28_b_1_q;
    reg [15:0] redist440_i_shl_i_i_i_i_i77_i_48_c_compstr1363_vt_select_28_b_1_q;
    reg [15:0] redist441_i_shl_i_i_i_i_i77_i_47_c_compstr1335_vt_select_28_b_1_q;
    reg [15:0] redist442_i_shl_i_i_i_i_i77_i_46_c_compstr1307_vt_select_28_b_1_q;
    reg [15:0] redist443_i_shl_i_i_i_i_i77_i_45_c_compstr1279_vt_select_28_b_1_q;
    reg [15:0] redist444_i_shl_i_i_i_i_i77_i_44_c_compstr1251_vt_select_28_b_1_q;
    reg [15:0] redist445_i_shl_i_i_i_i_i77_i_43_c_compstr1223_vt_select_28_b_1_q;
    reg [15:0] redist446_i_shl_i_i_i_i_i77_i_42_c_compstr1195_vt_select_28_b_1_q;
    reg [15:0] redist447_i_shl_i_i_i_i_i77_i_41_c_compstr1167_vt_select_28_b_1_q;
    reg [15:0] redist448_i_shl_i_i_i_i_i77_i_40_c_compstr1139_vt_select_28_b_1_q;
    reg [15:0] redist449_i_shl_i_i_i_i_i77_i_3_c_compstr103_vt_select_28_b_1_q;
    reg [15:0] redist450_i_shl_i_i_i_i_i77_i_39_c_compstr1111_vt_select_28_b_1_q;
    reg [15:0] redist451_i_shl_i_i_i_i_i77_i_38_c_compstr1083_vt_select_28_b_1_q;
    reg [15:0] redist452_i_shl_i_i_i_i_i77_i_37_c_compstr1055_vt_select_28_b_1_q;
    reg [15:0] redist453_i_shl_i_i_i_i_i77_i_36_c_compstr1027_vt_select_28_b_1_q;
    reg [15:0] redist454_i_shl_i_i_i_i_i77_i_35_c_compstr999_vt_select_28_b_1_q;
    reg [15:0] redist455_i_shl_i_i_i_i_i77_i_34_c_compstr971_vt_select_28_b_1_q;
    reg [15:0] redist456_i_shl_i_i_i_i_i77_i_33_c_compstr943_vt_select_28_b_1_q;
    reg [15:0] redist457_i_shl_i_i_i_i_i77_i_32_c_compstr915_vt_select_28_b_1_q;
    reg [15:0] redist458_i_shl_i_i_i_i_i77_i_31_c_compstr887_vt_select_28_b_1_q;
    reg [15:0] redist459_i_shl_i_i_i_i_i77_i_30_c_compstr859_vt_select_28_b_1_q;
    reg [15:0] redist460_i_shl_i_i_i_i_i77_i_2_c_compstr75_vt_select_28_b_1_q;
    reg [15:0] redist461_i_shl_i_i_i_i_i77_i_29_c_compstr831_vt_select_28_b_1_q;
    reg [15:0] redist462_i_shl_i_i_i_i_i77_i_28_c_compstr803_vt_select_28_b_1_q;
    reg [15:0] redist463_i_shl_i_i_i_i_i77_i_27_c_compstr775_vt_select_28_b_1_q;
    reg [15:0] redist464_i_shl_i_i_i_i_i77_i_26_c_compstr747_vt_select_28_b_1_q;
    reg [15:0] redist465_i_shl_i_i_i_i_i77_i_25_c_compstr719_vt_select_28_b_1_q;
    reg [15:0] redist466_i_shl_i_i_i_i_i77_i_24_c_compstr691_vt_select_28_b_1_q;
    reg [15:0] redist467_i_shl_i_i_i_i_i77_i_23_c_compstr663_vt_select_28_b_1_q;
    reg [15:0] redist468_i_shl_i_i_i_i_i77_i_22_c_compstr635_vt_select_28_b_1_q;
    reg [15:0] redist469_i_shl_i_i_i_i_i77_i_21_c_compstr607_vt_select_28_b_1_q;
    reg [15:0] redist470_i_shl_i_i_i_i_i77_i_20_c_compstr579_vt_select_28_b_1_q;
    reg [15:0] redist471_i_shl_i_i_i_i_i77_i_1_c_compstr47_vt_select_28_b_1_q;
    reg [15:0] redist472_i_shl_i_i_i_i_i77_i_19_c_compstr551_vt_select_28_b_1_q;
    reg [15:0] redist473_i_shl_i_i_i_i_i77_i_18_c_compstr523_vt_select_28_b_1_q;
    reg [15:0] redist474_i_shl_i_i_i_i_i77_i_17_c_compstr495_vt_select_28_b_1_q;
    reg [15:0] redist475_i_shl_i_i_i_i_i77_i_16_c_compstr467_vt_select_28_b_1_q;
    reg [15:0] redist476_i_shl_i_i_i_i_i77_i_15_c_compstr439_vt_select_28_b_1_q;
    reg [15:0] redist477_i_shl_i_i_i_i_i77_i_14_c_compstr411_vt_select_28_b_1_q;
    reg [15:0] redist478_i_shl_i_i_i_i_i77_i_13_c_compstr383_vt_select_28_b_1_q;
    reg [15:0] redist479_i_shl_i_i_i_i_i77_i_12_c_compstr355_vt_select_28_b_1_q;
    reg [15:0] redist480_i_shl_i_i_i_i_i77_i_127_c_compstr3575_vt_select_28_b_1_q;
    reg [15:0] redist481_i_shl_i_i_i_i_i77_i_126_c_compstr3547_vt_select_28_b_1_q;
    reg [15:0] redist482_i_shl_i_i_i_i_i77_i_125_c_compstr3519_vt_select_28_b_1_q;
    reg [15:0] redist483_i_shl_i_i_i_i_i77_i_124_c_compstr3491_vt_select_28_b_1_q;
    reg [15:0] redist484_i_shl_i_i_i_i_i77_i_123_c_compstr3463_vt_select_28_b_1_q;
    reg [15:0] redist485_i_shl_i_i_i_i_i77_i_122_c_compstr3435_vt_select_28_b_1_q;
    reg [15:0] redist486_i_shl_i_i_i_i_i77_i_121_c_compstr3407_vt_select_28_b_1_q;
    reg [15:0] redist487_i_shl_i_i_i_i_i77_i_120_c_compstr3379_vt_select_28_b_1_q;
    reg [15:0] redist488_i_shl_i_i_i_i_i77_i_11_c_compstr327_vt_select_28_b_1_q;
    reg [15:0] redist489_i_shl_i_i_i_i_i77_i_119_c_compstr3351_vt_select_28_b_1_q;
    reg [15:0] redist490_i_shl_i_i_i_i_i77_i_118_c_compstr3323_vt_select_28_b_1_q;
    reg [15:0] redist491_i_shl_i_i_i_i_i77_i_117_c_compstr3295_vt_select_28_b_1_q;
    reg [15:0] redist492_i_shl_i_i_i_i_i77_i_116_c_compstr3267_vt_select_28_b_1_q;
    reg [15:0] redist493_i_shl_i_i_i_i_i77_i_115_c_compstr3239_vt_select_28_b_1_q;
    reg [15:0] redist494_i_shl_i_i_i_i_i77_i_114_c_compstr3211_vt_select_28_b_1_q;
    reg [15:0] redist495_i_shl_i_i_i_i_i77_i_113_c_compstr3183_vt_select_28_b_1_q;
    reg [15:0] redist496_i_shl_i_i_i_i_i77_i_112_c_compstr3155_vt_select_28_b_1_q;
    reg [15:0] redist497_i_shl_i_i_i_i_i77_i_111_c_compstr3127_vt_select_28_b_1_q;
    reg [15:0] redist498_i_shl_i_i_i_i_i77_i_110_c_compstr3099_vt_select_28_b_1_q;
    reg [15:0] redist499_i_shl_i_i_i_i_i77_i_10_c_compstr299_vt_select_28_b_1_q;
    reg [15:0] redist500_i_shl_i_i_i_i_i77_i_109_c_compstr3071_vt_select_28_b_1_q;
    reg [15:0] redist501_i_shl_i_i_i_i_i77_i_108_c_compstr3043_vt_select_28_b_1_q;
    reg [15:0] redist502_i_shl_i_i_i_i_i77_i_107_c_compstr3015_vt_select_28_b_1_q;
    reg [15:0] redist503_i_shl_i_i_i_i_i77_i_106_c_compstr2987_vt_select_28_b_1_q;
    reg [15:0] redist504_i_shl_i_i_i_i_i77_i_105_c_compstr2959_vt_select_28_b_1_q;
    reg [15:0] redist505_i_shl_i_i_i_i_i77_i_104_c_compstr2931_vt_select_28_b_1_q;
    reg [15:0] redist506_i_shl_i_i_i_i_i77_i_103_c_compstr2903_vt_select_28_b_1_q;
    reg [15:0] redist507_i_shl_i_i_i_i_i77_i_102_c_compstr2875_vt_select_28_b_1_q;
    reg [15:0] redist508_i_shl_i_i_i_i_i77_i_101_c_compstr2847_vt_select_28_b_1_q;
    reg [15:0] redist509_i_shl_i_i_i_i_i77_i_100_c_compstr2819_vt_select_28_b_1_q;
    reg [0:0] redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_q;
    reg [0:0] redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_delay_0;
    reg [0:0] redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_delay_1;
    reg [0:0] redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_delay_2;
    reg [0:0] redist511_i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out_4_q;
    reg [0:0] redist511_i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out_4_delay_0;
    reg [0:0] redist511_i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out_4_delay_1;
    reg [0:0] redist511_i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out_4_delay_2;
    reg [0:0] redist512_i_c_compstr_b7_current_iter_isspec_c_compstr5_q_264_q;
    reg [0:0] redist513_sync_together3657_aunroll_x_in_i_valid_2_q;
    reg [0:0] redist513_sync_together3657_aunroll_x_in_i_valid_2_delay_0;
    reg [0:0] redist514_sync_together3657_aunroll_x_in_i_valid_3_q;
    reg [0:0] redist515_i_memcoalesce_load_c_compstr_fpgaunique_5138_toi1_intcast_c_compstr18_sel_x_b_260_q;
    reg [0:0] redist516_i_memcoalesce_load_c_compstr_fpgaunique_5126_toi1_intcast_c_compstr13_sel_x_b_260_q;
    reg [0:0] redist517_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_q;
    reg [0:0] redist517_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_delay_0;
    reg [15:0] redist518_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_2_tpl_1_q;
    reg [15:0] redist519_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_3_tpl_1_q;
    reg [15:0] redist520_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_4_tpl_3_q;
    reg [15:0] redist520_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_4_tpl_3_delay_0;
    reg [15:0] redist520_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_4_tpl_3_delay_1;
    reg [15:0] redist521_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_5_tpl_3_q;
    reg [15:0] redist521_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_5_tpl_3_delay_0;
    reg [15:0] redist521_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_5_tpl_3_delay_1;
    reg [15:0] redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_q;
    reg [15:0] redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_delay_0;
    reg [15:0] redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_delay_1;
    reg [15:0] redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_q;
    reg [15:0] redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_delay_0;
    reg [15:0] redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_delay_1;
    reg [15:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_q;
    reg [15:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_delay_0;
    reg [15:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_q;
    reg [15:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_delay_0;
    reg [15:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_q;
    reg [15:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_delay_0;
    reg [15:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_delay_1;
    reg [15:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_q;
    reg [15:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_delay_0;
    reg [15:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_delay_1;
    reg [15:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_q;
    reg [15:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_q;
    reg [15:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_q;
    reg [15:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_delay_0;
    reg [15:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_delay_1;
    reg [15:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_q;
    reg [15:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_delay_0;
    reg [15:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_delay_1;
    reg [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_q;
    reg [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_delay_0;
    reg [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_delay_1;
    reg [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_q;
    reg [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_delay_0;
    reg [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_delay_1;
    reg [15:0] redist772_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_2_tpl_1_q;
    reg [15:0] redist773_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_3_tpl_1_q;
    reg [15:0] redist774_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_4_tpl_3_q;
    reg [15:0] redist774_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_4_tpl_3_delay_0;
    reg [15:0] redist774_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_4_tpl_3_delay_1;
    reg [15:0] redist775_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_5_tpl_3_q;
    reg [15:0] redist775_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_5_tpl_3_delay_0;
    reg [15:0] redist775_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_5_tpl_3_delay_1;
    reg [15:0] redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_q;
    reg [15:0] redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_delay_0;
    reg [15:0] redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_delay_1;
    reg [15:0] redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_q;
    reg [15:0] redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_delay_0;
    reg [15:0] redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_delay_1;
    reg [15:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_q;
    reg [15:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_delay_0;
    reg [15:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_q;
    reg [15:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_delay_0;
    reg [15:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_q;
    reg [15:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_delay_0;
    reg [15:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_delay_1;
    reg [15:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_q;
    reg [15:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_delay_0;
    reg [15:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_delay_1;
    reg [15:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_q;
    reg [15:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_q;
    reg [15:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_q;
    reg [15:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_delay_0;
    reg [15:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_delay_1;
    reg [15:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_q;
    reg [15:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_delay_0;
    reg [15:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_delay_1;
    reg [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_q;
    reg [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_delay_0;
    reg [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_delay_1;
    reg [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_q;
    reg [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_delay_0;
    reg [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_delay_1;
    reg [15:0] redist1026_i_conv_i_i_i_i_i_9_c_compstr290_sel_x_b_1_q;
    reg [15:0] redist1027_i_conv_i_i_i_i_i_99_c_compstr2810_sel_x_b_1_q;
    reg [15:0] redist1028_i_conv_i_i_i_i_i_98_c_compstr2782_sel_x_b_1_q;
    reg [15:0] redist1029_i_conv_i_i_i_i_i_97_c_compstr2754_sel_x_b_1_q;
    reg [15:0] redist1030_i_conv_i_i_i_i_i_96_c_compstr2726_sel_x_b_1_q;
    reg [15:0] redist1031_i_conv_i_i_i_i_i_95_c_compstr2698_sel_x_b_1_q;
    reg [15:0] redist1032_i_conv_i_i_i_i_i_94_c_compstr2670_sel_x_b_1_q;
    reg [15:0] redist1033_i_conv_i_i_i_i_i_93_c_compstr2642_sel_x_b_1_q;
    reg [15:0] redist1034_i_conv_i_i_i_i_i_92_c_compstr2614_sel_x_b_1_q;
    reg [15:0] redist1035_i_conv_i_i_i_i_i_91_c_compstr2586_sel_x_b_1_q;
    reg [15:0] redist1036_i_conv_i_i_i_i_i_90_c_compstr2558_sel_x_b_1_q;
    reg [15:0] redist1037_i_conv_i_i_i_i_i_8_c_compstr262_sel_x_b_1_q;
    reg [15:0] redist1038_i_conv_i_i_i_i_i_89_c_compstr2530_sel_x_b_1_q;
    reg [15:0] redist1039_i_conv_i_i_i_i_i_88_c_compstr2502_sel_x_b_1_q;
    reg [15:0] redist1040_i_conv_i_i_i_i_i_87_c_compstr2474_sel_x_b_1_q;
    reg [15:0] redist1041_i_conv_i_i_i_i_i_86_c_compstr2446_sel_x_b_1_q;
    reg [15:0] redist1042_i_conv_i_i_i_i_i_85_c_compstr2418_sel_x_b_1_q;
    reg [15:0] redist1043_i_conv_i_i_i_i_i_84_c_compstr2390_sel_x_b_1_q;
    reg [15:0] redist1044_i_conv_i_i_i_i_i_83_c_compstr2362_sel_x_b_1_q;
    reg [15:0] redist1045_i_conv_i_i_i_i_i_82_c_compstr2334_sel_x_b_1_q;
    reg [15:0] redist1046_i_conv_i_i_i_i_i_81_c_compstr2306_sel_x_b_1_q;
    reg [15:0] redist1047_i_conv_i_i_i_i_i_80_c_compstr2278_sel_x_b_1_q;
    reg [15:0] redist1048_i_conv_i_i_i_i_i_7_c_compstr234_sel_x_b_1_q;
    reg [15:0] redist1049_i_conv_i_i_i_i_i_79_c_compstr2250_sel_x_b_1_q;
    reg [15:0] redist1050_i_conv_i_i_i_i_i_78_c_compstr2222_sel_x_b_1_q;
    reg [15:0] redist1051_i_conv_i_i_i_i_i_77_c_compstr2194_sel_x_b_1_q;
    reg [15:0] redist1052_i_conv_i_i_i_i_i_76_c_compstr2166_sel_x_b_1_q;
    reg [15:0] redist1053_i_conv_i_i_i_i_i_75_c_compstr2138_sel_x_b_1_q;
    reg [15:0] redist1054_i_conv_i_i_i_i_i_74_c_compstr2110_sel_x_b_1_q;
    reg [15:0] redist1055_i_conv_i_i_i_i_i_73_c_compstr2082_sel_x_b_1_q;
    reg [15:0] redist1056_i_conv_i_i_i_i_i_72_c_compstr2054_sel_x_b_1_q;
    reg [15:0] redist1057_i_conv_i_i_i_i_i_71_c_compstr2026_sel_x_b_1_q;
    reg [15:0] redist1058_i_conv_i_i_i_i_i_70_c_compstr1998_sel_x_b_1_q;
    reg [15:0] redist1059_i_conv_i_i_i_i_i_6_c_compstr206_sel_x_b_1_q;
    reg [15:0] redist1060_i_conv_i_i_i_i_i_69_c_compstr1970_sel_x_b_1_q;
    reg [15:0] redist1061_i_conv_i_i_i_i_i_68_c_compstr1942_sel_x_b_1_q;
    reg [15:0] redist1062_i_conv_i_i_i_i_i_67_c_compstr1914_sel_x_b_1_q;
    reg [15:0] redist1063_i_conv_i_i_i_i_i_66_c_compstr1886_sel_x_b_1_q;
    reg [15:0] redist1064_i_conv_i_i_i_i_i_65_c_compstr1858_sel_x_b_1_q;
    reg [15:0] redist1065_i_conv_i_i_i_i_i_64_c_compstr1830_sel_x_b_1_q;
    reg [15:0] redist1066_i_conv_i_i_i_i_i_63_c_compstr1802_sel_x_b_1_q;
    reg [15:0] redist1067_i_conv_i_i_i_i_i_62_c_compstr1774_sel_x_b_1_q;
    reg [15:0] redist1068_i_conv_i_i_i_i_i_61_c_compstr1746_sel_x_b_1_q;
    reg [15:0] redist1069_i_conv_i_i_i_i_i_60_c_compstr1718_sel_x_b_1_q;
    reg [15:0] redist1070_i_conv_i_i_i_i_i_5_c_compstr178_sel_x_b_1_q;
    reg [15:0] redist1071_i_conv_i_i_i_i_i_59_c_compstr1690_sel_x_b_1_q;
    reg [15:0] redist1072_i_conv_i_i_i_i_i_58_c_compstr1662_sel_x_b_1_q;
    reg [15:0] redist1073_i_conv_i_i_i_i_i_57_c_compstr1634_sel_x_b_1_q;
    reg [15:0] redist1074_i_conv_i_i_i_i_i_56_c_compstr1606_sel_x_b_1_q;
    reg [15:0] redist1075_i_conv_i_i_i_i_i_55_c_compstr1578_sel_x_b_1_q;
    reg [15:0] redist1076_i_conv_i_i_i_i_i_54_c_compstr1550_sel_x_b_1_q;
    reg [15:0] redist1077_i_conv_i_i_i_i_i_53_c_compstr1522_sel_x_b_1_q;
    reg [15:0] redist1078_i_conv_i_i_i_i_i_52_c_compstr1494_sel_x_b_1_q;
    reg [15:0] redist1079_i_conv_i_i_i_i_i_51_c_compstr1466_sel_x_b_1_q;
    reg [15:0] redist1080_i_conv_i_i_i_i_i_50_c_compstr1438_sel_x_b_1_q;
    reg [15:0] redist1081_i_conv_i_i_i_i_i_4_c_compstr150_sel_x_b_1_q;
    reg [15:0] redist1082_i_conv_i_i_i_i_i_49_c_compstr1410_sel_x_b_1_q;
    reg [15:0] redist1083_i_conv_i_i_i_i_i_48_c_compstr1382_sel_x_b_1_q;
    reg [15:0] redist1084_i_conv_i_i_i_i_i_47_c_compstr1354_sel_x_b_1_q;
    reg [15:0] redist1085_i_conv_i_i_i_i_i_46_c_compstr1326_sel_x_b_1_q;
    reg [15:0] redist1086_i_conv_i_i_i_i_i_45_c_compstr1298_sel_x_b_1_q;
    reg [15:0] redist1087_i_conv_i_i_i_i_i_44_c_compstr1270_sel_x_b_1_q;
    reg [15:0] redist1088_i_conv_i_i_i_i_i_43_c_compstr1242_sel_x_b_1_q;
    reg [15:0] redist1089_i_conv_i_i_i_i_i_42_c_compstr1214_sel_x_b_1_q;
    reg [15:0] redist1090_i_conv_i_i_i_i_i_41_c_compstr1186_sel_x_b_1_q;
    reg [15:0] redist1091_i_conv_i_i_i_i_i_40_c_compstr1158_sel_x_b_1_q;
    reg [15:0] redist1092_i_conv_i_i_i_i_i_3_c_compstr122_sel_x_b_1_q;
    reg [15:0] redist1093_i_conv_i_i_i_i_i_39_c_compstr1130_sel_x_b_1_q;
    reg [15:0] redist1094_i_conv_i_i_i_i_i_38_c_compstr1102_sel_x_b_1_q;
    reg [15:0] redist1095_i_conv_i_i_i_i_i_37_c_compstr1074_sel_x_b_1_q;
    reg [15:0] redist1096_i_conv_i_i_i_i_i_36_c_compstr1046_sel_x_b_1_q;
    reg [15:0] redist1097_i_conv_i_i_i_i_i_35_c_compstr1018_sel_x_b_1_q;
    reg [15:0] redist1098_i_conv_i_i_i_i_i_34_c_compstr990_sel_x_b_1_q;
    reg [15:0] redist1099_i_conv_i_i_i_i_i_33_c_compstr962_sel_x_b_1_q;
    reg [15:0] redist1100_i_conv_i_i_i_i_i_32_c_compstr934_sel_x_b_1_q;
    reg [15:0] redist1101_i_conv_i_i_i_i_i_31_c_compstr906_sel_x_b_1_q;
    reg [15:0] redist1102_i_conv_i_i_i_i_i_30_c_compstr878_sel_x_b_1_q;
    reg [15:0] redist1103_i_conv_i_i_i_i_i_2_c_compstr94_sel_x_b_1_q;
    reg [15:0] redist1104_i_conv_i_i_i_i_i_29_c_compstr850_sel_x_b_1_q;
    reg [15:0] redist1105_i_conv_i_i_i_i_i_28_c_compstr822_sel_x_b_1_q;
    reg [15:0] redist1106_i_conv_i_i_i_i_i_27_c_compstr794_sel_x_b_1_q;
    reg [15:0] redist1107_i_conv_i_i_i_i_i_26_c_compstr766_sel_x_b_1_q;
    reg [15:0] redist1108_i_conv_i_i_i_i_i_25_c_compstr738_sel_x_b_1_q;
    reg [15:0] redist1109_i_conv_i_i_i_i_i_24_c_compstr710_sel_x_b_1_q;
    reg [15:0] redist1110_i_conv_i_i_i_i_i_23_c_compstr682_sel_x_b_1_q;
    reg [15:0] redist1111_i_conv_i_i_i_i_i_22_c_compstr654_sel_x_b_1_q;
    reg [15:0] redist1112_i_conv_i_i_i_i_i_21_c_compstr626_sel_x_b_1_q;
    reg [15:0] redist1113_i_conv_i_i_i_i_i_20_c_compstr598_sel_x_b_1_q;
    reg [15:0] redist1114_i_conv_i_i_i_i_i_1_c_compstr66_sel_x_b_1_q;
    reg [15:0] redist1115_i_conv_i_i_i_i_i_19_c_compstr570_sel_x_b_1_q;
    reg [15:0] redist1116_i_conv_i_i_i_i_i_18_c_compstr542_sel_x_b_1_q;
    reg [15:0] redist1117_i_conv_i_i_i_i_i_17_c_compstr514_sel_x_b_1_q;
    reg [15:0] redist1118_i_conv_i_i_i_i_i_16_c_compstr486_sel_x_b_1_q;
    reg [15:0] redist1119_i_conv_i_i_i_i_i_15_c_compstr458_sel_x_b_1_q;
    reg [15:0] redist1120_i_conv_i_i_i_i_i_14_c_compstr430_sel_x_b_1_q;
    reg [15:0] redist1121_i_conv_i_i_i_i_i_13_c_compstr402_sel_x_b_1_q;
    reg [15:0] redist1122_i_conv_i_i_i_i_i_12_c_compstr374_sel_x_b_1_q;
    reg [15:0] redist1123_i_conv_i_i_i_i_i_127_c_compstr3594_sel_x_b_1_q;
    reg [15:0] redist1124_i_conv_i_i_i_i_i_126_c_compstr3566_sel_x_b_1_q;
    reg [15:0] redist1125_i_conv_i_i_i_i_i_125_c_compstr3538_sel_x_b_1_q;
    reg [15:0] redist1126_i_conv_i_i_i_i_i_124_c_compstr3510_sel_x_b_1_q;
    reg [15:0] redist1127_i_conv_i_i_i_i_i_123_c_compstr3482_sel_x_b_1_q;
    reg [15:0] redist1128_i_conv_i_i_i_i_i_122_c_compstr3454_sel_x_b_1_q;
    reg [15:0] redist1129_i_conv_i_i_i_i_i_121_c_compstr3426_sel_x_b_1_q;
    reg [15:0] redist1130_i_conv_i_i_i_i_i_120_c_compstr3398_sel_x_b_1_q;
    reg [15:0] redist1131_i_conv_i_i_i_i_i_11_c_compstr346_sel_x_b_1_q;
    reg [15:0] redist1132_i_conv_i_i_i_i_i_119_c_compstr3370_sel_x_b_1_q;
    reg [15:0] redist1133_i_conv_i_i_i_i_i_118_c_compstr3342_sel_x_b_1_q;
    reg [15:0] redist1134_i_conv_i_i_i_i_i_117_c_compstr3314_sel_x_b_1_q;
    reg [15:0] redist1135_i_conv_i_i_i_i_i_116_c_compstr3286_sel_x_b_1_q;
    reg [15:0] redist1136_i_conv_i_i_i_i_i_115_c_compstr3258_sel_x_b_1_q;
    reg [15:0] redist1137_i_conv_i_i_i_i_i_114_c_compstr3230_sel_x_b_1_q;
    reg [15:0] redist1138_i_conv_i_i_i_i_i_113_c_compstr3202_sel_x_b_1_q;
    reg [15:0] redist1139_i_conv_i_i_i_i_i_112_c_compstr3174_sel_x_b_1_q;
    reg [15:0] redist1140_i_conv_i_i_i_i_i_111_c_compstr3146_sel_x_b_1_q;
    reg [15:0] redist1141_i_conv_i_i_i_i_i_110_c_compstr3118_sel_x_b_1_q;
    reg [15:0] redist1142_i_conv_i_i_i_i_i_10_c_compstr318_sel_x_b_1_q;
    reg [15:0] redist1143_i_conv_i_i_i_i_i_109_c_compstr3090_sel_x_b_1_q;
    reg [15:0] redist1144_i_conv_i_i_i_i_i_108_c_compstr3062_sel_x_b_1_q;
    reg [15:0] redist1145_i_conv_i_i_i_i_i_107_c_compstr3034_sel_x_b_1_q;
    reg [15:0] redist1146_i_conv_i_i_i_i_i_106_c_compstr3006_sel_x_b_1_q;
    reg [15:0] redist1147_i_conv_i_i_i_i_i_105_c_compstr2978_sel_x_b_1_q;
    reg [15:0] redist1148_i_conv_i_i_i_i_i_104_c_compstr2950_sel_x_b_1_q;
    reg [15:0] redist1149_i_conv_i_i_i_i_i_103_c_compstr2922_sel_x_b_1_q;
    reg [15:0] redist1150_i_conv_i_i_i_i_i_102_c_compstr2894_sel_x_b_1_q;
    reg [15:0] redist1151_i_conv_i_i_i_i_i_101_c_compstr2866_sel_x_b_1_q;
    reg [15:0] redist1152_i_conv_i_i_i_i_i_100_c_compstr2838_sel_x_b_1_q;
    reg [15:0] redist1153_i_conv_i_i_i_i97_i_9_c_compstr274_sel_x_b_1_q;
    reg [15:0] redist1154_i_conv_i_i_i_i97_i_99_c_compstr2794_sel_x_b_1_q;
    reg [15:0] redist1155_i_conv_i_i_i_i97_i_98_c_compstr2766_sel_x_b_1_q;
    reg [15:0] redist1156_i_conv_i_i_i_i97_i_97_c_compstr2738_sel_x_b_1_q;
    reg [15:0] redist1157_i_conv_i_i_i_i97_i_96_c_compstr2710_sel_x_b_1_q;
    reg [15:0] redist1158_i_conv_i_i_i_i97_i_95_c_compstr2682_sel_x_b_1_q;
    reg [15:0] redist1159_i_conv_i_i_i_i97_i_94_c_compstr2654_sel_x_b_1_q;
    reg [15:0] redist1160_i_conv_i_i_i_i97_i_93_c_compstr2626_sel_x_b_1_q;
    reg [15:0] redist1161_i_conv_i_i_i_i97_i_92_c_compstr2598_sel_x_b_1_q;
    reg [15:0] redist1162_i_conv_i_i_i_i97_i_91_c_compstr2570_sel_x_b_1_q;
    reg [15:0] redist1163_i_conv_i_i_i_i97_i_90_c_compstr2542_sel_x_b_1_q;
    reg [15:0] redist1164_i_conv_i_i_i_i97_i_8_c_compstr246_sel_x_b_1_q;
    reg [15:0] redist1165_i_conv_i_i_i_i97_i_89_c_compstr2514_sel_x_b_1_q;
    reg [15:0] redist1166_i_conv_i_i_i_i97_i_88_c_compstr2486_sel_x_b_1_q;
    reg [15:0] redist1167_i_conv_i_i_i_i97_i_87_c_compstr2458_sel_x_b_1_q;
    reg [15:0] redist1168_i_conv_i_i_i_i97_i_86_c_compstr2430_sel_x_b_1_q;
    reg [15:0] redist1169_i_conv_i_i_i_i97_i_85_c_compstr2402_sel_x_b_1_q;
    reg [15:0] redist1170_i_conv_i_i_i_i97_i_84_c_compstr2374_sel_x_b_1_q;
    reg [15:0] redist1171_i_conv_i_i_i_i97_i_83_c_compstr2346_sel_x_b_1_q;
    reg [15:0] redist1172_i_conv_i_i_i_i97_i_82_c_compstr2318_sel_x_b_1_q;
    reg [15:0] redist1173_i_conv_i_i_i_i97_i_81_c_compstr2290_sel_x_b_1_q;
    reg [15:0] redist1174_i_conv_i_i_i_i97_i_80_c_compstr2262_sel_x_b_1_q;
    reg [15:0] redist1175_i_conv_i_i_i_i97_i_7_c_compstr218_sel_x_b_1_q;
    reg [15:0] redist1176_i_conv_i_i_i_i97_i_79_c_compstr2234_sel_x_b_1_q;
    reg [15:0] redist1177_i_conv_i_i_i_i97_i_78_c_compstr2206_sel_x_b_1_q;
    reg [15:0] redist1178_i_conv_i_i_i_i97_i_77_c_compstr2178_sel_x_b_1_q;
    reg [15:0] redist1179_i_conv_i_i_i_i97_i_76_c_compstr2150_sel_x_b_1_q;
    reg [15:0] redist1180_i_conv_i_i_i_i97_i_75_c_compstr2122_sel_x_b_1_q;
    reg [15:0] redist1181_i_conv_i_i_i_i97_i_74_c_compstr2094_sel_x_b_1_q;
    reg [15:0] redist1182_i_conv_i_i_i_i97_i_73_c_compstr2066_sel_x_b_1_q;
    reg [15:0] redist1183_i_conv_i_i_i_i97_i_72_c_compstr2038_sel_x_b_1_q;
    reg [15:0] redist1184_i_conv_i_i_i_i97_i_71_c_compstr2010_sel_x_b_1_q;
    reg [15:0] redist1185_i_conv_i_i_i_i97_i_70_c_compstr1982_sel_x_b_1_q;
    reg [15:0] redist1186_i_conv_i_i_i_i97_i_6_c_compstr190_sel_x_b_1_q;
    reg [15:0] redist1187_i_conv_i_i_i_i97_i_69_c_compstr1954_sel_x_b_1_q;
    reg [15:0] redist1188_i_conv_i_i_i_i97_i_68_c_compstr1926_sel_x_b_1_q;
    reg [15:0] redist1189_i_conv_i_i_i_i97_i_67_c_compstr1898_sel_x_b_1_q;
    reg [15:0] redist1190_i_conv_i_i_i_i97_i_66_c_compstr1870_sel_x_b_1_q;
    reg [15:0] redist1191_i_conv_i_i_i_i97_i_65_c_compstr1842_sel_x_b_1_q;
    reg [15:0] redist1192_i_conv_i_i_i_i97_i_64_c_compstr1814_sel_x_b_1_q;
    reg [15:0] redist1193_i_conv_i_i_i_i97_i_63_c_compstr1786_sel_x_b_1_q;
    reg [15:0] redist1194_i_conv_i_i_i_i97_i_62_c_compstr1758_sel_x_b_1_q;
    reg [15:0] redist1195_i_conv_i_i_i_i97_i_61_c_compstr1730_sel_x_b_1_q;
    reg [15:0] redist1196_i_conv_i_i_i_i97_i_60_c_compstr1702_sel_x_b_1_q;
    reg [15:0] redist1197_i_conv_i_i_i_i97_i_5_c_compstr162_sel_x_b_1_q;
    reg [15:0] redist1198_i_conv_i_i_i_i97_i_59_c_compstr1674_sel_x_b_1_q;
    reg [15:0] redist1199_i_conv_i_i_i_i97_i_58_c_compstr1646_sel_x_b_1_q;
    reg [15:0] redist1200_i_conv_i_i_i_i97_i_57_c_compstr1618_sel_x_b_1_q;
    reg [15:0] redist1201_i_conv_i_i_i_i97_i_56_c_compstr1590_sel_x_b_1_q;
    reg [15:0] redist1202_i_conv_i_i_i_i97_i_55_c_compstr1562_sel_x_b_1_q;
    reg [15:0] redist1203_i_conv_i_i_i_i97_i_54_c_compstr1534_sel_x_b_1_q;
    reg [15:0] redist1204_i_conv_i_i_i_i97_i_53_c_compstr1506_sel_x_b_1_q;
    reg [15:0] redist1205_i_conv_i_i_i_i97_i_52_c_compstr1478_sel_x_b_1_q;
    reg [15:0] redist1206_i_conv_i_i_i_i97_i_51_c_compstr1450_sel_x_b_1_q;
    reg [15:0] redist1207_i_conv_i_i_i_i97_i_50_c_compstr1422_sel_x_b_1_q;
    reg [15:0] redist1208_i_conv_i_i_i_i97_i_4_c_compstr134_sel_x_b_1_q;
    reg [15:0] redist1209_i_conv_i_i_i_i97_i_49_c_compstr1394_sel_x_b_1_q;
    reg [15:0] redist1210_i_conv_i_i_i_i97_i_48_c_compstr1366_sel_x_b_1_q;
    reg [15:0] redist1211_i_conv_i_i_i_i97_i_47_c_compstr1338_sel_x_b_1_q;
    reg [15:0] redist1212_i_conv_i_i_i_i97_i_46_c_compstr1310_sel_x_b_1_q;
    reg [15:0] redist1213_i_conv_i_i_i_i97_i_45_c_compstr1282_sel_x_b_1_q;
    reg [15:0] redist1214_i_conv_i_i_i_i97_i_44_c_compstr1254_sel_x_b_1_q;
    reg [15:0] redist1215_i_conv_i_i_i_i97_i_43_c_compstr1226_sel_x_b_1_q;
    reg [15:0] redist1216_i_conv_i_i_i_i97_i_42_c_compstr1198_sel_x_b_1_q;
    reg [15:0] redist1217_i_conv_i_i_i_i97_i_41_c_compstr1170_sel_x_b_1_q;
    reg [15:0] redist1218_i_conv_i_i_i_i97_i_40_c_compstr1142_sel_x_b_1_q;
    reg [15:0] redist1219_i_conv_i_i_i_i97_i_3_c_compstr106_sel_x_b_1_q;
    reg [15:0] redist1220_i_conv_i_i_i_i97_i_39_c_compstr1114_sel_x_b_1_q;
    reg [15:0] redist1221_i_conv_i_i_i_i97_i_38_c_compstr1086_sel_x_b_1_q;
    reg [15:0] redist1222_i_conv_i_i_i_i97_i_37_c_compstr1058_sel_x_b_1_q;
    reg [15:0] redist1223_i_conv_i_i_i_i97_i_36_c_compstr1030_sel_x_b_1_q;
    reg [15:0] redist1224_i_conv_i_i_i_i97_i_35_c_compstr1002_sel_x_b_1_q;
    reg [15:0] redist1225_i_conv_i_i_i_i97_i_34_c_compstr974_sel_x_b_1_q;
    reg [15:0] redist1226_i_conv_i_i_i_i97_i_33_c_compstr946_sel_x_b_1_q;
    reg [15:0] redist1227_i_conv_i_i_i_i97_i_32_c_compstr918_sel_x_b_1_q;
    reg [15:0] redist1228_i_conv_i_i_i_i97_i_31_c_compstr890_sel_x_b_1_q;
    reg [15:0] redist1229_i_conv_i_i_i_i97_i_30_c_compstr862_sel_x_b_1_q;
    reg [15:0] redist1230_i_conv_i_i_i_i97_i_2_c_compstr78_sel_x_b_1_q;
    reg [15:0] redist1231_i_conv_i_i_i_i97_i_29_c_compstr834_sel_x_b_1_q;
    reg [15:0] redist1232_i_conv_i_i_i_i97_i_28_c_compstr806_sel_x_b_1_q;
    reg [15:0] redist1233_i_conv_i_i_i_i97_i_27_c_compstr778_sel_x_b_1_q;
    reg [15:0] redist1234_i_conv_i_i_i_i97_i_26_c_compstr750_sel_x_b_1_q;
    reg [15:0] redist1235_i_conv_i_i_i_i97_i_25_c_compstr722_sel_x_b_1_q;
    reg [15:0] redist1236_i_conv_i_i_i_i97_i_24_c_compstr694_sel_x_b_1_q;
    reg [15:0] redist1237_i_conv_i_i_i_i97_i_23_c_compstr666_sel_x_b_1_q;
    reg [15:0] redist1238_i_conv_i_i_i_i97_i_22_c_compstr638_sel_x_b_1_q;
    reg [15:0] redist1239_i_conv_i_i_i_i97_i_21_c_compstr610_sel_x_b_1_q;
    reg [15:0] redist1240_i_conv_i_i_i_i97_i_20_c_compstr582_sel_x_b_1_q;
    reg [15:0] redist1241_i_conv_i_i_i_i97_i_1_c_compstr50_sel_x_b_1_q;
    reg [15:0] redist1242_i_conv_i_i_i_i97_i_19_c_compstr554_sel_x_b_1_q;
    reg [15:0] redist1243_i_conv_i_i_i_i97_i_18_c_compstr526_sel_x_b_1_q;
    reg [15:0] redist1244_i_conv_i_i_i_i97_i_17_c_compstr498_sel_x_b_1_q;
    reg [15:0] redist1245_i_conv_i_i_i_i97_i_16_c_compstr470_sel_x_b_1_q;
    reg [15:0] redist1246_i_conv_i_i_i_i97_i_15_c_compstr442_sel_x_b_1_q;
    reg [15:0] redist1247_i_conv_i_i_i_i97_i_14_c_compstr414_sel_x_b_1_q;
    reg [15:0] redist1248_i_conv_i_i_i_i97_i_13_c_compstr386_sel_x_b_1_q;
    reg [15:0] redist1249_i_conv_i_i_i_i97_i_12_c_compstr358_sel_x_b_1_q;
    reg [15:0] redist1250_i_conv_i_i_i_i97_i_127_c_compstr3578_sel_x_b_1_q;
    reg [15:0] redist1251_i_conv_i_i_i_i97_i_126_c_compstr3550_sel_x_b_1_q;
    reg [15:0] redist1252_i_conv_i_i_i_i97_i_125_c_compstr3522_sel_x_b_1_q;
    reg [15:0] redist1253_i_conv_i_i_i_i97_i_124_c_compstr3494_sel_x_b_1_q;
    reg [15:0] redist1254_i_conv_i_i_i_i97_i_123_c_compstr3466_sel_x_b_1_q;
    reg [15:0] redist1255_i_conv_i_i_i_i97_i_122_c_compstr3438_sel_x_b_1_q;
    reg [15:0] redist1256_i_conv_i_i_i_i97_i_121_c_compstr3410_sel_x_b_1_q;
    reg [15:0] redist1257_i_conv_i_i_i_i97_i_120_c_compstr3382_sel_x_b_1_q;
    reg [15:0] redist1258_i_conv_i_i_i_i97_i_11_c_compstr330_sel_x_b_1_q;
    reg [15:0] redist1259_i_conv_i_i_i_i97_i_119_c_compstr3354_sel_x_b_1_q;
    reg [15:0] redist1260_i_conv_i_i_i_i97_i_118_c_compstr3326_sel_x_b_1_q;
    reg [15:0] redist1261_i_conv_i_i_i_i97_i_117_c_compstr3298_sel_x_b_1_q;
    reg [15:0] redist1262_i_conv_i_i_i_i97_i_116_c_compstr3270_sel_x_b_1_q;
    reg [15:0] redist1263_i_conv_i_i_i_i97_i_115_c_compstr3242_sel_x_b_1_q;
    reg [15:0] redist1264_i_conv_i_i_i_i97_i_114_c_compstr3214_sel_x_b_1_q;
    reg [15:0] redist1265_i_conv_i_i_i_i97_i_113_c_compstr3186_sel_x_b_1_q;
    reg [15:0] redist1266_i_conv_i_i_i_i97_i_112_c_compstr3158_sel_x_b_1_q;
    reg [15:0] redist1267_i_conv_i_i_i_i97_i_111_c_compstr3130_sel_x_b_1_q;
    reg [15:0] redist1268_i_conv_i_i_i_i97_i_110_c_compstr3102_sel_x_b_1_q;
    reg [15:0] redist1269_i_conv_i_i_i_i97_i_10_c_compstr302_sel_x_b_1_q;
    reg [15:0] redist1270_i_conv_i_i_i_i97_i_109_c_compstr3074_sel_x_b_1_q;
    reg [15:0] redist1271_i_conv_i_i_i_i97_i_108_c_compstr3046_sel_x_b_1_q;
    reg [15:0] redist1272_i_conv_i_i_i_i97_i_107_c_compstr3018_sel_x_b_1_q;
    reg [15:0] redist1273_i_conv_i_i_i_i97_i_106_c_compstr2990_sel_x_b_1_q;
    reg [15:0] redist1274_i_conv_i_i_i_i97_i_105_c_compstr2962_sel_x_b_1_q;
    reg [15:0] redist1275_i_conv_i_i_i_i97_i_104_c_compstr2934_sel_x_b_1_q;
    reg [15:0] redist1276_i_conv_i_i_i_i97_i_103_c_compstr2906_sel_x_b_1_q;
    reg [15:0] redist1277_i_conv_i_i_i_i97_i_102_c_compstr2878_sel_x_b_1_q;
    reg [15:0] redist1278_i_conv_i_i_i_i97_i_101_c_compstr2850_sel_x_b_1_q;
    reg [15:0] redist1279_i_conv_i_i_i_i97_i_100_c_compstr2822_sel_x_b_1_q;
    reg [15:0] redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_inputreg0_q;
    reg [15:0] redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_outputreg0_q;
    reg [15:0] redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_inputreg0_q;
    reg [15:0] redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_outputreg0_q;
    reg [15:0] redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_inputreg0_q;
    reg [15:0] redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_outputreg0_q;
    wire redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_reset0;
    wire [15:0] redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_ia;
    wire [1:0] redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_aa;
    wire [1:0] redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_ab;
    wire [15:0] redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_iq;
    wire [15:0] redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_q;
    wire [1:0] redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_wraddr_i = 2'b11;
    wire [1:0] redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_offset_q;
    wire [2:0] redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_a;
    wire [2:0] redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_b;
    logic [2:0] redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_o;
    wire [2:0] redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_q;
    reg [15:0] redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_inputreg0_q;
    reg [15:0] redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_outputreg0_q;
    wire redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_reset0;
    wire [15:0] redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_ia;
    wire [1:0] redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_aa;
    wire [1:0] redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_ab;
    wire [15:0] redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_iq;
    wire [15:0] redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_q;
    wire [1:0] redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_wraddr_i = 2'b11;
    wire [2:0] redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_a;
    wire [2:0] redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_b;
    logic [2:0] redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_o;
    wire [2:0] redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_q;
    reg [15:0] redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_inputreg0_q;
    reg [15:0] redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_outputreg0_q;
    wire redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_reset0;
    wire [15:0] redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_ia;
    wire [2:0] redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_aa;
    wire [2:0] redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_ab;
    wire [15:0] redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_iq;
    wire [15:0] redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_q;
    wire [2:0] redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_wraddr_i = 3'b111;
    wire [2:0] redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_offset_q;
    wire [3:0] redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_a;
    wire [3:0] redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_b;
    logic [3:0] redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_o;
    wire [3:0] redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_q;
    reg [15:0] redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_inputreg0_q;
    reg [15:0] redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_outputreg0_q;
    wire redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_reset0;
    wire [15:0] redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_ia;
    wire [2:0] redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_aa;
    wire [2:0] redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_ab;
    wire [15:0] redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_iq;
    wire [15:0] redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_q;
    wire [2:0] redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_wraddr_i = 3'b111;
    wire [3:0] redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_a;
    wire [3:0] redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_b;
    logic [3:0] redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_o;
    wire [3:0] redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_q;
    reg [15:0] redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_inputreg0_q;
    reg [15:0] redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_outputreg0_q;
    wire redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_reset0;
    wire [15:0] redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_ia;
    wire [2:0] redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_aa;
    wire [2:0] redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_ab;
    wire [15:0] redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_iq;
    wire [15:0] redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_q;
    wire [2:0] redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_wraddr_i = 3'b111;
    wire [2:0] redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_offset_q;
    wire [3:0] redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_a;
    wire [3:0] redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_b;
    logic [3:0] redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_o;
    wire [3:0] redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_q;
    reg [15:0] redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_inputreg0_q;
    reg [15:0] redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_outputreg0_q;
    wire redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_reset0;
    wire [15:0] redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_ia;
    wire [2:0] redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_aa;
    wire [2:0] redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_ab;
    wire [15:0] redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_iq;
    wire [15:0] redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_q;
    wire [2:0] redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_wraddr_i = 3'b111;
    wire [3:0] redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_a;
    wire [3:0] redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_b;
    logic [3:0] redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_o;
    wire [3:0] redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_q;
    reg [15:0] redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_inputreg0_q;
    reg [15:0] redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_outputreg0_q;
    wire redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_reset0;
    wire [15:0] redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_ia;
    wire [3:0] redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_aa;
    wire [3:0] redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_ab;
    wire [15:0] redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_iq;
    wire [15:0] redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_q;
    wire [3:0] redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_wraddr_i = 4'b1111;
    wire [3:0] redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_offset_q;
    wire [4:0] redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_a;
    wire [4:0] redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_b;
    logic [4:0] redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_o;
    wire [4:0] redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_q;
    reg [15:0] redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_inputreg0_q;
    reg [15:0] redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_outputreg0_q;
    wire redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_reset0;
    wire [15:0] redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_ia;
    wire [3:0] redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_aa;
    wire [3:0] redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_ab;
    wire [15:0] redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_iq;
    wire [15:0] redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_q;
    wire [3:0] redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_wraddr_i = 4'b1111;
    wire [4:0] redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_a;
    wire [4:0] redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_b;
    logic [4:0] redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_o;
    wire [4:0] redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_q;
    reg [15:0] redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_inputreg0_q;
    reg [15:0] redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_outputreg0_q;
    wire redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_reset0;
    wire [15:0] redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_ia;
    wire [3:0] redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_aa;
    wire [3:0] redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_ab;
    wire [15:0] redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_iq;
    wire [15:0] redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_q;
    wire [3:0] redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_wraddr_i = 4'b1111;
    wire [3:0] redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_offset_q;
    wire [4:0] redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_a;
    wire [4:0] redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_b;
    logic [4:0] redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_o;
    wire [4:0] redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_q;
    reg [15:0] redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_inputreg0_q;
    reg [15:0] redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_outputreg0_q;
    wire redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_reset0;
    wire [15:0] redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_ia;
    wire [3:0] redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_aa;
    wire [3:0] redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_ab;
    wire [15:0] redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_iq;
    wire [15:0] redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_q;
    wire [3:0] redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_wraddr_i = 4'b1111;
    wire [4:0] redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_a;
    wire [4:0] redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_b;
    logic [4:0] redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_o;
    wire [4:0] redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_q;
    reg [15:0] redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_inputreg0_q;
    reg [15:0] redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_outputreg0_q;
    wire redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_reset0;
    wire [15:0] redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_ia;
    wire [3:0] redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_aa;
    wire [3:0] redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_ab;
    wire [15:0] redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_iq;
    wire [15:0] redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_q;
    wire [3:0] redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_wraddr_i = 4'b1111;
    wire [3:0] redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_offset_q;
    wire [4:0] redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_a;
    wire [4:0] redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_b;
    logic [4:0] redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_o;
    wire [4:0] redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_q;
    reg [15:0] redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_inputreg0_q;
    reg [15:0] redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_outputreg0_q;
    wire redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_reset0;
    wire [15:0] redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_ia;
    wire [3:0] redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_aa;
    wire [3:0] redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_ab;
    wire [15:0] redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_iq;
    wire [15:0] redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_q;
    wire [3:0] redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_wraddr_i = 4'b1111;
    wire [4:0] redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_a;
    wire [4:0] redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_b;
    logic [4:0] redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_o;
    wire [4:0] redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_q;
    reg [15:0] redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_inputreg0_q;
    reg [15:0] redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_outputreg0_q;
    wire redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_reset0;
    wire [15:0] redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_ia;
    wire [3:0] redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_aa;
    wire [3:0] redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_ab;
    wire [15:0] redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_iq;
    wire [15:0] redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_q;
    wire [3:0] redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_wraddr_i = 4'b1111;
    wire [3:0] redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_offset_q;
    wire [4:0] redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_a;
    wire [4:0] redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_b;
    logic [4:0] redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_o;
    wire [4:0] redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_q;
    reg [15:0] redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_inputreg0_q;
    reg [15:0] redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_outputreg0_q;
    wire redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_reset0;
    wire [15:0] redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_ia;
    wire [3:0] redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_aa;
    wire [3:0] redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_ab;
    wire [15:0] redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_iq;
    wire [15:0] redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_q;
    wire [3:0] redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_wraddr_i = 4'b1111;
    wire [4:0] redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_a;
    wire [4:0] redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_b;
    logic [4:0] redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_o;
    wire [4:0] redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_q;
    reg [15:0] redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_inputreg0_q;
    reg [15:0] redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_outputreg0_q;
    wire redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_reset0;
    wire [15:0] redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_ia;
    wire [4:0] redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_aa;
    wire [4:0] redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_ab;
    wire [15:0] redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_iq;
    wire [15:0] redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_q;
    wire [4:0] redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_wraddr_i = 5'b11111;
    wire [4:0] redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_offset_q;
    wire [5:0] redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_a;
    wire [5:0] redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_b;
    logic [5:0] redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_o;
    wire [5:0] redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_q;
    reg [15:0] redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_inputreg0_q;
    reg [15:0] redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_outputreg0_q;
    wire redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_reset0;
    wire [15:0] redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_ia;
    wire [4:0] redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_aa;
    wire [4:0] redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_ab;
    wire [15:0] redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_iq;
    wire [15:0] redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_q;
    wire [4:0] redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_wraddr_i = 5'b11111;
    wire [5:0] redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_a;
    wire [5:0] redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_b;
    logic [5:0] redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_o;
    wire [5:0] redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_q;
    reg [15:0] redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_inputreg0_q;
    reg [15:0] redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_outputreg0_q;
    wire redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_reset0;
    wire [15:0] redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_ia;
    wire [4:0] redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_aa;
    wire [4:0] redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_ab;
    wire [15:0] redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_iq;
    wire [15:0] redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_q;
    wire [4:0] redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_wraddr_i = 5'b11111;
    wire [5:0] redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_a;
    wire [5:0] redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_b;
    logic [5:0] redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_o;
    wire [5:0] redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_q;
    reg [15:0] redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_inputreg0_q;
    reg [15:0] redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_outputreg0_q;
    wire redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_reset0;
    wire [15:0] redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_ia;
    wire [4:0] redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_aa;
    wire [4:0] redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_ab;
    wire [15:0] redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_iq;
    wire [15:0] redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_q;
    wire [4:0] redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_wraddr_i = 5'b11111;
    wire [5:0] redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_a;
    wire [5:0] redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_b;
    logic [5:0] redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_o;
    wire [5:0] redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_q;
    reg [15:0] redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_inputreg0_q;
    reg [15:0] redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_outputreg0_q;
    wire redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_reset0;
    wire [15:0] redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_ia;
    wire [4:0] redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_aa;
    wire [4:0] redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_ab;
    wire [15:0] redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_iq;
    wire [15:0] redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_q;
    wire [4:0] redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_wraddr_i = 5'b11111;
    wire [4:0] redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_offset_q;
    wire [5:0] redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_a;
    wire [5:0] redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_b;
    logic [5:0] redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_o;
    wire [5:0] redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_q;
    reg [15:0] redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_inputreg0_q;
    reg [15:0] redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_outputreg0_q;
    wire redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_reset0;
    wire [15:0] redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_ia;
    wire [4:0] redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_aa;
    wire [4:0] redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_ab;
    wire [15:0] redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_iq;
    wire [15:0] redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_q;
    wire [4:0] redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_wraddr_i = 5'b11111;
    wire [5:0] redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_a;
    wire [5:0] redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_b;
    logic [5:0] redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_o;
    wire [5:0] redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_q;
    reg [15:0] redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_inputreg0_q;
    reg [15:0] redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_outputreg0_q;
    wire redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_reset0;
    wire [15:0] redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_ia;
    wire [4:0] redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_aa;
    wire [4:0] redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_ab;
    wire [15:0] redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_iq;
    wire [15:0] redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_q;
    wire [4:0] redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_wraddr_i = 5'b11111;
    wire [4:0] redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_offset_q;
    wire [5:0] redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_a;
    wire [5:0] redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_b;
    logic [5:0] redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_o;
    wire [5:0] redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_q;
    reg [15:0] redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_inputreg0_q;
    reg [15:0] redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_outputreg0_q;
    wire redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_reset0;
    wire [15:0] redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_ia;
    wire [4:0] redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_aa;
    wire [4:0] redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_ab;
    wire [15:0] redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_iq;
    wire [15:0] redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_q;
    wire [4:0] redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_wraddr_i = 5'b11111;
    wire [5:0] redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_a;
    wire [5:0] redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_b;
    logic [5:0] redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_o;
    wire [5:0] redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_q;
    reg [15:0] redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_inputreg0_q;
    reg [15:0] redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_outputreg0_q;
    wire redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_reset0;
    wire [15:0] redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_ia;
    wire [4:0] redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_aa;
    wire [4:0] redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_ab;
    wire [15:0] redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_iq;
    wire [15:0] redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_q;
    wire [4:0] redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_wraddr_i = 5'b11111;
    wire [4:0] redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_offset_q;
    wire [5:0] redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_a;
    wire [5:0] redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_b;
    logic [5:0] redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_o;
    wire [5:0] redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_q;
    reg [15:0] redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_inputreg0_q;
    reg [15:0] redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_outputreg0_q;
    wire redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_reset0;
    wire [15:0] redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_ia;
    wire [4:0] redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_aa;
    wire [4:0] redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_ab;
    wire [15:0] redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_iq;
    wire [15:0] redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_q;
    wire [4:0] redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_wraddr_i = 5'b11111;
    wire [5:0] redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_a;
    wire [5:0] redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_b;
    logic [5:0] redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_o;
    wire [5:0] redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_q;
    reg [15:0] redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_inputreg0_q;
    reg [15:0] redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_outputreg0_q;
    wire redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_reset0;
    wire [15:0] redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_ia;
    wire [4:0] redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_aa;
    wire [4:0] redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_ab;
    wire [15:0] redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_iq;
    wire [15:0] redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_q;
    wire [4:0] redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_wraddr_i = 5'b11111;
    wire [4:0] redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_offset_q;
    wire [5:0] redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_a;
    wire [5:0] redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_b;
    logic [5:0] redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_o;
    wire [5:0] redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_q;
    reg [15:0] redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_inputreg0_q;
    reg [15:0] redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_outputreg0_q;
    wire redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_reset0;
    wire [15:0] redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_ia;
    wire [4:0] redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_aa;
    wire [4:0] redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_ab;
    wire [15:0] redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_iq;
    wire [15:0] redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_q;
    wire [4:0] redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_wraddr_i = 5'b11111;
    wire [5:0] redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_a;
    wire [5:0] redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_b;
    logic [5:0] redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_o;
    wire [5:0] redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_q;
    reg [15:0] redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_inputreg0_q;
    reg [15:0] redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_outputreg0_q;
    wire redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_reset0;
    wire [15:0] redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_ia;
    wire [4:0] redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_aa;
    wire [4:0] redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_ab;
    wire [15:0] redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_iq;
    wire [15:0] redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_q;
    wire [4:0] redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_wraddr_i = 5'b11111;
    wire [4:0] redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q;
    wire [5:0] redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_a;
    wire [5:0] redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_b;
    logic [5:0] redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_o;
    wire [5:0] redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_q;
    reg [15:0] redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_inputreg0_q;
    reg [15:0] redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_outputreg0_q;
    wire redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_reset0;
    wire [15:0] redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_ia;
    wire [4:0] redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_aa;
    wire [4:0] redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_ab;
    wire [15:0] redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_iq;
    wire [15:0] redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_q;
    wire [4:0] redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_wraddr_i = 5'b11111;
    wire [5:0] redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_a;
    wire [5:0] redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_b;
    logic [5:0] redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_o;
    wire [5:0] redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_q;
    reg [15:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_inputreg0_q;
    reg [15:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_inputreg0_q;
    reg [15:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_inputreg0_q;
    reg [15:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_outputreg0_q;
    wire redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_reset0;
    wire [15:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_ia;
    wire [1:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_aa;
    wire [1:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_ab;
    wire [15:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_iq;
    wire [15:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_q;
    wire [1:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_wraddr_i = 2'b11;
    wire [1:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_offset_q;
    wire [2:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_a;
    wire [2:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_b;
    logic [2:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_o;
    wire [2:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_q;
    reg [15:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_inputreg0_q;
    reg [15:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_outputreg0_q;
    wire redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_reset0;
    wire [15:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_ia;
    wire [1:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_aa;
    wire [1:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_ab;
    wire [15:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_iq;
    wire [15:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_q;
    wire [1:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_wraddr_i = 2'b11;
    wire [2:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_a;
    wire [2:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_b;
    logic [2:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_o;
    wire [2:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_q;
    reg [15:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_inputreg0_q;
    reg [15:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_outputreg0_q;
    wire redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_reset0;
    wire [15:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_ia;
    wire [2:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_aa;
    wire [2:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_ab;
    wire [15:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_iq;
    wire [15:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_q;
    wire [2:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_wraddr_i = 3'b111;
    wire [2:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_offset_q;
    wire [3:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_a;
    wire [3:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_b;
    logic [3:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_o;
    wire [3:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_q;
    reg [15:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_inputreg0_q;
    reg [15:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_outputreg0_q;
    wire redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_reset0;
    wire [15:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_ia;
    wire [2:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_aa;
    wire [2:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_ab;
    wire [15:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_iq;
    wire [15:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_q;
    wire [2:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_wraddr_i = 3'b111;
    wire [3:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_a;
    wire [3:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_b;
    logic [3:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_o;
    wire [3:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_q;
    reg [15:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_inputreg0_q;
    reg [15:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_outputreg0_q;
    wire redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_reset0;
    wire [15:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_ia;
    wire [2:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_aa;
    wire [2:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_ab;
    wire [15:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_iq;
    wire [15:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_q;
    wire [2:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_wraddr_i = 3'b111;
    wire [2:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_offset_q;
    wire [3:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_a;
    wire [3:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_b;
    logic [3:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_o;
    wire [3:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_q;
    reg [15:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_inputreg0_q;
    reg [15:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_outputreg0_q;
    wire redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_reset0;
    wire [15:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_ia;
    wire [2:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_aa;
    wire [2:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_ab;
    wire [15:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_iq;
    wire [15:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_q;
    wire [2:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_wraddr_i = 3'b111;
    wire [3:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_a;
    wire [3:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_b;
    logic [3:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_o;
    wire [3:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_q;
    reg [15:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_inputreg0_q;
    reg [15:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_outputreg0_q;
    wire redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_reset0;
    wire [15:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_ia;
    wire [3:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_aa;
    wire [3:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_ab;
    wire [15:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_iq;
    wire [15:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_q;
    wire [3:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_wraddr_i = 4'b1111;
    wire [3:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_offset_q;
    wire [4:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_a;
    wire [4:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_b;
    logic [4:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_o;
    wire [4:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_q;
    reg [15:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_inputreg0_q;
    reg [15:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_outputreg0_q;
    wire redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_reset0;
    wire [15:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_ia;
    wire [3:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_aa;
    wire [3:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_ab;
    wire [15:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_iq;
    wire [15:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_q;
    wire [3:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_wraddr_i = 4'b1111;
    wire [4:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_a;
    wire [4:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_b;
    logic [4:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_o;
    wire [4:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_q;
    reg [15:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_inputreg0_q;
    reg [15:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_outputreg0_q;
    wire redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_reset0;
    wire [15:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_ia;
    wire [3:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_aa;
    wire [3:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_ab;
    wire [15:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_iq;
    wire [15:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_q;
    wire [3:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_wraddr_i = 4'b1111;
    wire [3:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_offset_q;
    wire [4:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_a;
    wire [4:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_b;
    logic [4:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_o;
    wire [4:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_q;
    reg [15:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_inputreg0_q;
    reg [15:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_outputreg0_q;
    wire redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_reset0;
    wire [15:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_ia;
    wire [3:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_aa;
    wire [3:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_ab;
    wire [15:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_iq;
    wire [15:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_q;
    wire [3:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_wraddr_i = 4'b1111;
    wire [4:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_a;
    wire [4:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_b;
    logic [4:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_o;
    wire [4:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_q;
    reg [15:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_inputreg0_q;
    reg [15:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_outputreg0_q;
    wire redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_reset0;
    wire [15:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_ia;
    wire [3:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_aa;
    wire [3:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_ab;
    wire [15:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_iq;
    wire [15:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_q;
    wire [3:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_wraddr_i = 4'b1111;
    wire [3:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_offset_q;
    wire [4:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_a;
    wire [4:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_b;
    logic [4:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_o;
    wire [4:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_q;
    reg [15:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_inputreg0_q;
    reg [15:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_outputreg0_q;
    wire redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_reset0;
    wire [15:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_ia;
    wire [3:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_aa;
    wire [3:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_ab;
    wire [15:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_iq;
    wire [15:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_q;
    wire [3:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_wraddr_i = 4'b1111;
    wire [4:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_a;
    wire [4:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_b;
    logic [4:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_o;
    wire [4:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_q;
    reg [15:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_inputreg0_q;
    reg [15:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_outputreg0_q;
    wire redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_reset0;
    wire [15:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_ia;
    wire [3:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_aa;
    wire [3:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_ab;
    wire [15:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_iq;
    wire [15:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_q;
    wire [3:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_wraddr_i = 4'b1111;
    wire [3:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_offset_q;
    wire [4:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_a;
    wire [4:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_b;
    logic [4:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_o;
    wire [4:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_q;
    reg [15:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_inputreg0_q;
    reg [15:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_outputreg0_q;
    wire redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_reset0;
    wire [15:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_ia;
    wire [3:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_aa;
    wire [3:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_ab;
    wire [15:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_iq;
    wire [15:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_q;
    wire [3:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_wraddr_i = 4'b1111;
    wire [4:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_a;
    wire [4:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_b;
    logic [4:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_o;
    wire [4:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_q;
    reg [15:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_inputreg0_q;
    reg [15:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_outputreg0_q;
    wire redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_reset0;
    wire [15:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_ia;
    wire [4:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_aa;
    wire [4:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_ab;
    wire [15:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_iq;
    wire [15:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_q;
    wire [4:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_wraddr_i = 5'b11111;
    wire [4:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_offset_q;
    wire [5:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_a;
    wire [5:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_b;
    logic [5:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_o;
    wire [5:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_q;
    reg [15:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_inputreg0_q;
    reg [15:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_outputreg0_q;
    wire redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_reset0;
    wire [15:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_ia;
    wire [4:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_aa;
    wire [4:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_ab;
    wire [15:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_iq;
    wire [15:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_q;
    wire [4:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_wraddr_i = 5'b11111;
    wire [5:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_a;
    wire [5:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_b;
    logic [5:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_o;
    wire [5:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_q;
    reg [15:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_inputreg0_q;
    reg [15:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_outputreg0_q;
    wire redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_reset0;
    wire [15:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_ia;
    wire [4:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_aa;
    wire [4:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_ab;
    wire [15:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_iq;
    wire [15:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_q;
    wire [4:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_wraddr_i = 5'b11111;
    wire [4:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_offset_q;
    wire [5:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_a;
    wire [5:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_b;
    logic [5:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_o;
    wire [5:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_q;
    reg [15:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_inputreg0_q;
    reg [15:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_outputreg0_q;
    wire redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_reset0;
    wire [15:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_ia;
    wire [4:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_aa;
    wire [4:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_ab;
    wire [15:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_iq;
    wire [15:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_q;
    wire [4:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_wraddr_i = 5'b11111;
    wire [5:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_a;
    wire [5:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_b;
    logic [5:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_o;
    wire [5:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_q;
    reg [15:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_inputreg0_q;
    reg [15:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_outputreg0_q;
    wire redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_reset0;
    wire [15:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_ia;
    wire [4:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_aa;
    wire [4:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_ab;
    wire [15:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_iq;
    wire [15:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_q;
    wire [4:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_wraddr_i = 5'b11111;
    wire [4:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_offset_q;
    wire [5:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_a;
    wire [5:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_b;
    logic [5:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_o;
    wire [5:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_q;
    reg [15:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_inputreg0_q;
    reg [15:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_outputreg0_q;
    wire redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_reset0;
    wire [15:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_ia;
    wire [4:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_aa;
    wire [4:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_ab;
    wire [15:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_iq;
    wire [15:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_q;
    wire [4:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_wraddr_i = 5'b11111;
    wire [5:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_a;
    wire [5:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_b;
    logic [5:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_o;
    wire [5:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_q;
    reg [15:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_inputreg0_q;
    reg [15:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_outputreg0_q;
    wire redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_reset0;
    wire [15:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_ia;
    wire [4:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_aa;
    wire [4:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_ab;
    wire [15:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_iq;
    wire [15:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_q;
    wire [4:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_wraddr_i = 5'b11111;
    wire [4:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_offset_q;
    wire [5:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_a;
    wire [5:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_b;
    logic [5:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_o;
    wire [5:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_q;
    reg [15:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_inputreg0_q;
    reg [15:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_outputreg0_q;
    wire redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_reset0;
    wire [15:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_ia;
    wire [4:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_aa;
    wire [4:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_ab;
    wire [15:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_iq;
    wire [15:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_q;
    wire [4:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_wraddr_i = 5'b11111;
    wire [5:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_a;
    wire [5:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_b;
    logic [5:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_o;
    wire [5:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_q;
    reg [15:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_inputreg0_q;
    reg [15:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_outputreg0_q;
    wire redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_reset0;
    wire [15:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_ia;
    wire [4:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_aa;
    wire [4:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_ab;
    wire [15:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_iq;
    wire [15:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_q;
    wire [4:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_wraddr_i = 5'b11111;
    wire [4:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_offset_q;
    wire [5:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_a;
    wire [5:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_b;
    logic [5:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_o;
    wire [5:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_q;
    reg [15:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_inputreg0_q;
    reg [15:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_outputreg0_q;
    wire redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_reset0;
    wire [15:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_ia;
    wire [4:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_aa;
    wire [4:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_ab;
    wire [15:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_iq;
    wire [15:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_q;
    wire [4:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_wraddr_i = 5'b11111;
    wire [5:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_a;
    wire [5:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_b;
    logic [5:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_o;
    wire [5:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_q;
    reg [15:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_inputreg0_q;
    reg [15:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_outputreg0_q;
    wire redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_reset0;
    wire [15:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_ia;
    wire [4:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_aa;
    wire [4:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_ab;
    wire [15:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_iq;
    wire [15:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_q;
    wire [4:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_wraddr_i = 5'b11111;
    wire [4:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_offset_q;
    wire [5:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_a;
    wire [5:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_b;
    logic [5:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_o;
    wire [5:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_q;
    reg [15:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_inputreg0_q;
    reg [15:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_outputreg0_q;
    wire redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_reset0;
    wire [15:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_ia;
    wire [4:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_aa;
    wire [4:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_ab;
    wire [15:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_iq;
    wire [15:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_q;
    wire [4:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_wraddr_i = 5'b11111;
    wire [5:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_a;
    wire [5:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_b;
    logic [5:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_o;
    wire [5:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_q;
    reg [15:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_inputreg0_q;
    reg [15:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_outputreg0_q;
    wire redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_reset0;
    wire [15:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_ia;
    wire [4:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_aa;
    wire [4:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_ab;
    wire [15:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_iq;
    wire [15:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_q;
    wire [4:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_wraddr_i = 5'b11111;
    wire [4:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_offset_q;
    wire [5:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_a;
    wire [5:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_b;
    logic [5:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_o;
    wire [5:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_q;
    reg [15:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_inputreg0_q;
    reg [15:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_outputreg0_q;
    wire redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_reset0;
    wire [15:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_ia;
    wire [4:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_aa;
    wire [4:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_ab;
    wire [15:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_iq;
    wire [15:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_q;
    wire [4:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_wraddr_i = 5'b11111;
    wire [5:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_a;
    wire [5:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_b;
    logic [5:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_o;
    wire [5:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_q;
    reg [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_inputreg0_q;
    reg [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_outputreg0_q;
    reg [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_inputreg0_q;
    reg [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_outputreg0_q;
    reg [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_inputreg0_q;
    reg [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_outputreg0_q;
    wire redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_reset0;
    wire [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_ia;
    wire [1:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_aa;
    wire [1:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_ab;
    wire [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_iq;
    wire [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_q;
    wire [1:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_wraddr_i = 2'b11;
    wire [2:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_a;
    wire [2:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_b;
    logic [2:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_o;
    wire [2:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_q;
    reg [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_inputreg0_q;
    reg [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_outputreg0_q;
    wire redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_reset0;
    wire [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_ia;
    wire [1:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_aa;
    wire [1:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_ab;
    wire [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_iq;
    wire [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_q;
    wire [1:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_wraddr_i = 2'b11;
    wire [2:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_a;
    wire [2:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_b;
    logic [2:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_o;
    wire [2:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_q;
    reg [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_inputreg0_q;
    reg [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_outputreg0_q;
    wire redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_reset0;
    wire [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_ia;
    wire [2:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_aa;
    wire [2:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_ab;
    wire [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_iq;
    wire [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_q;
    wire [2:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_wraddr_i = 3'b111;
    wire [3:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_a;
    wire [3:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_b;
    logic [3:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_o;
    wire [3:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_q;
    reg [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_inputreg0_q;
    reg [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_outputreg0_q;
    wire redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_reset0;
    wire [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_ia;
    wire [2:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_aa;
    wire [2:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_ab;
    wire [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_iq;
    wire [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_q;
    wire [2:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_wraddr_i = 3'b111;
    wire [3:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_a;
    wire [3:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_b;
    logic [3:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_o;
    wire [3:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_q;
    reg [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_inputreg0_q;
    reg [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_outputreg0_q;
    wire redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_reset0;
    wire [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_ia;
    wire [2:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_aa;
    wire [2:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_ab;
    wire [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_iq;
    wire [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_q;
    wire [2:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_wraddr_i = 3'b111;
    wire [3:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_a;
    wire [3:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_b;
    logic [3:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_o;
    wire [3:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_q;
    reg [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_inputreg0_q;
    reg [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_outputreg0_q;
    wire redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_reset0;
    wire [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_ia;
    wire [2:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_aa;
    wire [2:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_ab;
    wire [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_iq;
    wire [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_q;
    wire [2:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_wraddr_i = 3'b111;
    wire [3:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_a;
    wire [3:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_b;
    logic [3:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_o;
    wire [3:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_q;
    reg [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_inputreg0_q;
    reg [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_outputreg0_q;
    wire redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_reset0;
    wire [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_ia;
    wire [3:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_aa;
    wire [3:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_ab;
    wire [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_iq;
    wire [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_q;
    wire [3:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_wraddr_i = 4'b1111;
    wire [4:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_a;
    wire [4:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_b;
    logic [4:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_o;
    wire [4:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_q;
    reg [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_inputreg0_q;
    reg [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_outputreg0_q;
    wire redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_reset0;
    wire [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_ia;
    wire [3:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_aa;
    wire [3:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_ab;
    wire [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_iq;
    wire [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_q;
    wire [3:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_wraddr_i = 4'b1111;
    wire [4:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_a;
    wire [4:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_b;
    logic [4:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_o;
    wire [4:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_q;
    reg [15:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_inputreg0_q;
    reg [15:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_outputreg0_q;
    wire redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_reset0;
    wire [15:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_ia;
    wire [3:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_aa;
    wire [3:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_ab;
    wire [15:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_iq;
    wire [15:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_q;
    wire [3:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_wraddr_i = 4'b1111;
    wire [4:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_a;
    wire [4:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_b;
    logic [4:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_o;
    wire [4:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_q;
    reg [15:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_inputreg0_q;
    reg [15:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_outputreg0_q;
    wire redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_reset0;
    wire [15:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_ia;
    wire [3:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_aa;
    wire [3:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_ab;
    wire [15:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_iq;
    wire [15:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_q;
    wire [3:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_wraddr_i = 4'b1111;
    wire [4:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_a;
    wire [4:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_b;
    logic [4:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_o;
    wire [4:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_q;
    reg [15:0] redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_inputreg0_q;
    reg [15:0] redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_outputreg0_q;
    wire redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_reset0;
    wire [15:0] redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_ia;
    wire [6:0] redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_aa;
    wire [6:0] redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_ab;
    wire [15:0] redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_iq;
    wire [15:0] redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_q;
    wire [6:0] redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_wraddr_i = 7'b1111111;
    wire [6:0] redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_offset_q;
    wire [7:0] redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_a;
    wire [7:0] redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_b;
    logic [7:0] redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_o;
    wire [7:0] redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_q;
    reg [15:0] redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_inputreg0_q;
    reg [15:0] redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_outputreg0_q;
    wire redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_reset0;
    wire [15:0] redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_ia;
    wire [6:0] redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_aa;
    wire [6:0] redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_ab;
    wire [15:0] redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_iq;
    wire [15:0] redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_q;
    wire [6:0] redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_wraddr_i = 7'b1111111;
    wire [7:0] redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_a;
    wire [7:0] redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_b;
    logic [7:0] redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_o;
    wire [7:0] redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_q;
    reg [15:0] redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_inputreg0_q;
    reg [15:0] redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_outputreg0_q;
    wire redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_reset0;
    wire [15:0] redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_ia;
    wire [6:0] redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_aa;
    wire [6:0] redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_ab;
    wire [15:0] redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_iq;
    wire [15:0] redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_q;
    wire [6:0] redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_wraddr_i = 7'b1111111;
    wire [6:0] redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_offset_q;
    wire [7:0] redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_a;
    wire [7:0] redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_b;
    logic [7:0] redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_o;
    wire [7:0] redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_q;
    reg [15:0] redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_inputreg0_q;
    reg [15:0] redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_outputreg0_q;
    wire redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_reset0;
    wire [15:0] redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_ia;
    wire [6:0] redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_aa;
    wire [6:0] redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_ab;
    wire [15:0] redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_iq;
    wire [15:0] redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_q;
    wire [6:0] redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_wraddr_i = 7'b1111111;
    wire [7:0] redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_a;
    wire [7:0] redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_b;
    logic [7:0] redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_o;
    wire [7:0] redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_q;
    reg [15:0] redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_inputreg0_q;
    reg [15:0] redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_outputreg0_q;
    wire redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_reset0;
    wire [15:0] redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_ia;
    wire [6:0] redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_aa;
    wire [6:0] redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_ab;
    wire [15:0] redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_iq;
    wire [15:0] redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_q;
    wire [6:0] redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_wraddr_i = 7'b1111111;
    wire [6:0] redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_offset_q;
    wire [7:0] redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_a;
    wire [7:0] redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_b;
    logic [7:0] redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_o;
    wire [7:0] redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_q;
    reg [15:0] redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_inputreg0_q;
    reg [15:0] redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_outputreg0_q;
    wire redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_reset0;
    wire [15:0] redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_ia;
    wire [6:0] redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_aa;
    wire [6:0] redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_ab;
    wire [15:0] redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_iq;
    wire [15:0] redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_q;
    wire [6:0] redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_wraddr_i = 7'b1111111;
    wire [7:0] redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_a;
    wire [7:0] redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_b;
    logic [7:0] redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_o;
    wire [7:0] redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_q;
    reg [15:0] redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_inputreg0_q;
    reg [15:0] redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_outputreg0_q;
    wire redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_reset0;
    wire [15:0] redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_ia;
    wire [6:0] redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_aa;
    wire [6:0] redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_ab;
    wire [15:0] redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_iq;
    wire [15:0] redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_q;
    wire [6:0] redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_wraddr_i = 7'b1111111;
    wire [6:0] redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_offset_q;
    wire [7:0] redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_a;
    wire [7:0] redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_b;
    logic [7:0] redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_o;
    wire [7:0] redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_q;
    reg [15:0] redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_inputreg0_q;
    reg [15:0] redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_outputreg0_q;
    wire redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_reset0;
    wire [15:0] redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_ia;
    wire [6:0] redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_aa;
    wire [6:0] redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_ab;
    wire [15:0] redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_iq;
    wire [15:0] redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_q;
    wire [6:0] redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_wraddr_i = 7'b1111111;
    wire [7:0] redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_a;
    wire [7:0] redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_b;
    logic [7:0] redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_o;
    wire [7:0] redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_q;
    reg [15:0] redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_inputreg0_q;
    reg [15:0] redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_outputreg0_q;
    wire redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_reset0;
    wire [15:0] redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_ia;
    wire [6:0] redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_aa;
    wire [6:0] redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_ab;
    wire [15:0] redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_iq;
    wire [15:0] redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_q;
    wire [6:0] redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_wraddr_i = 7'b1111111;
    wire [6:0] redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_offset_q;
    wire [7:0] redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_a;
    wire [7:0] redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_b;
    logic [7:0] redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_o;
    wire [7:0] redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_q;
    reg [15:0] redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_inputreg0_q;
    reg [15:0] redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_outputreg0_q;
    wire redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_reset0;
    wire [15:0] redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_ia;
    wire [6:0] redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_aa;
    wire [6:0] redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_ab;
    wire [15:0] redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_iq;
    wire [15:0] redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_q;
    wire [6:0] redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_wraddr_i = 7'b1111111;
    wire [7:0] redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_a;
    wire [7:0] redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_b;
    logic [7:0] redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_o;
    wire [7:0] redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_q;
    reg [15:0] redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_inputreg0_q;
    reg [15:0] redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_outputreg0_q;
    wire redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_reset0;
    wire [15:0] redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_ia;
    wire [6:0] redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_aa;
    wire [6:0] redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_ab;
    wire [15:0] redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_iq;
    wire [15:0] redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_q;
    wire [6:0] redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_wraddr_i = 7'b1111111;
    wire [6:0] redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_offset_q;
    wire [7:0] redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_a;
    wire [7:0] redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_b;
    logic [7:0] redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_o;
    wire [7:0] redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_q;
    reg [15:0] redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_inputreg0_q;
    reg [15:0] redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_outputreg0_q;
    wire redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_reset0;
    wire [15:0] redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_ia;
    wire [6:0] redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_aa;
    wire [6:0] redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_ab;
    wire [15:0] redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_iq;
    wire [15:0] redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_q;
    wire [6:0] redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_wraddr_i = 7'b1111111;
    wire [7:0] redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_a;
    wire [7:0] redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_b;
    logic [7:0] redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_o;
    wire [7:0] redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_q;
    reg [15:0] redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_inputreg0_q;
    reg [15:0] redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_outputreg0_q;
    wire redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_reset0;
    wire [15:0] redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_ia;
    wire [6:0] redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_aa;
    wire [6:0] redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_ab;
    wire [15:0] redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_iq;
    wire [15:0] redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_q;
    wire [6:0] redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_wraddr_i = 7'b1111111;
    wire [6:0] redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_offset_q;
    wire [7:0] redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_a;
    wire [7:0] redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_b;
    logic [7:0] redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_o;
    wire [7:0] redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_q;
    reg [15:0] redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_inputreg0_q;
    reg [15:0] redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_outputreg0_q;
    wire redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_reset0;
    wire [15:0] redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_ia;
    wire [6:0] redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_aa;
    wire [6:0] redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_ab;
    wire [15:0] redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_iq;
    wire [15:0] redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_q;
    wire [6:0] redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_wraddr_i = 7'b1111111;
    wire [7:0] redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_a;
    wire [7:0] redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_b;
    logic [7:0] redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_o;
    wire [7:0] redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_q;
    reg [15:0] redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_inputreg0_q;
    reg [15:0] redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_outputreg0_q;
    wire redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_reset0;
    wire [15:0] redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_ia;
    wire [6:0] redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_aa;
    wire [6:0] redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_ab;
    wire [15:0] redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_iq;
    wire [15:0] redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_q;
    wire [6:0] redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_wraddr_i = 7'b1111111;
    wire [6:0] redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_offset_q;
    wire [7:0] redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_a;
    wire [7:0] redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_b;
    logic [7:0] redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_o;
    wire [7:0] redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_q;
    reg [15:0] redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_inputreg0_q;
    reg [15:0] redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_outputreg0_q;
    wire redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_reset0;
    wire [15:0] redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_ia;
    wire [6:0] redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_aa;
    wire [6:0] redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_ab;
    wire [15:0] redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_iq;
    wire [15:0] redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_q;
    wire [6:0] redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_wraddr_i = 7'b1111111;
    wire [7:0] redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_a;
    wire [7:0] redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_b;
    logic [7:0] redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_o;
    wire [7:0] redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_q;
    reg [15:0] redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_inputreg0_q;
    reg [15:0] redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_outputreg0_q;
    wire redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_reset0;
    wire [15:0] redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_ia;
    wire [6:0] redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_aa;
    wire [6:0] redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_ab;
    wire [15:0] redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_iq;
    wire [15:0] redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_q;
    wire [6:0] redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_wraddr_i = 7'b1111111;
    wire [6:0] redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_offset_q;
    wire [7:0] redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_a;
    wire [7:0] redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_b;
    logic [7:0] redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_o;
    wire [7:0] redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_q;
    reg [15:0] redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_inputreg0_q;
    reg [15:0] redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_outputreg0_q;
    wire redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_reset0;
    wire [15:0] redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_ia;
    wire [6:0] redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_aa;
    wire [6:0] redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_ab;
    wire [15:0] redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_iq;
    wire [15:0] redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_q;
    wire [6:0] redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_wraddr_i = 7'b1111111;
    wire [7:0] redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_a;
    wire [7:0] redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_b;
    logic [7:0] redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_o;
    wire [7:0] redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_q;
    reg [15:0] redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_inputreg0_q;
    reg [15:0] redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_outputreg0_q;
    wire redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_reset0;
    wire [15:0] redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_ia;
    wire [6:0] redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_aa;
    wire [6:0] redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_ab;
    wire [15:0] redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_iq;
    wire [15:0] redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_q;
    wire [6:0] redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_wraddr_i = 7'b1111111;
    wire [6:0] redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_offset_q;
    wire [7:0] redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_a;
    wire [7:0] redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_b;
    logic [7:0] redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_o;
    wire [7:0] redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_q;
    reg [15:0] redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_inputreg0_q;
    reg [15:0] redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_outputreg0_q;
    wire redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_reset0;
    wire [15:0] redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_ia;
    wire [6:0] redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_aa;
    wire [6:0] redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_ab;
    wire [15:0] redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_iq;
    wire [15:0] redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_q;
    wire [6:0] redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_wraddr_i = 7'b1111111;
    wire [7:0] redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_a;
    wire [7:0] redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_b;
    logic [7:0] redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_o;
    wire [7:0] redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_q;
    reg [15:0] redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_inputreg0_q;
    reg [15:0] redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_outputreg0_q;
    wire redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_reset0;
    wire [15:0] redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_ia;
    wire [6:0] redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_aa;
    wire [6:0] redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_ab;
    wire [15:0] redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_iq;
    wire [15:0] redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_q;
    wire [6:0] redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_wraddr_i = 7'b1111111;
    wire [6:0] redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_offset_q;
    wire [7:0] redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_a;
    wire [7:0] redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_b;
    logic [7:0] redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_o;
    wire [7:0] redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_q;
    reg [15:0] redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_inputreg0_q;
    reg [15:0] redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_outputreg0_q;
    wire redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_reset0;
    wire [15:0] redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_ia;
    wire [6:0] redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_aa;
    wire [6:0] redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_ab;
    wire [15:0] redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_iq;
    wire [15:0] redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_q;
    wire [6:0] redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_wraddr_i = 7'b1111111;
    wire [7:0] redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_a;
    wire [7:0] redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_b;
    logic [7:0] redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_o;
    wire [7:0] redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_q;
    reg [15:0] redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_inputreg0_q;
    reg [15:0] redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_outputreg0_q;
    wire redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_reset0;
    wire [15:0] redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_ia;
    wire [6:0] redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_aa;
    wire [6:0] redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_ab;
    wire [15:0] redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_iq;
    wire [15:0] redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_q;
    wire [6:0] redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_wraddr_i = 7'b1111111;
    wire [6:0] redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_offset_q;
    wire [7:0] redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_a;
    wire [7:0] redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_b;
    logic [7:0] redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_o;
    wire [7:0] redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_q;
    reg [15:0] redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_inputreg0_q;
    reg [15:0] redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_outputreg0_q;
    wire redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_reset0;
    wire [15:0] redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_ia;
    wire [6:0] redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_aa;
    wire [6:0] redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_ab;
    wire [15:0] redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_iq;
    wire [15:0] redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_q;
    wire [6:0] redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_wraddr_i = 7'b1111111;
    wire [7:0] redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_a;
    wire [7:0] redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_b;
    logic [7:0] redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_o;
    wire [7:0] redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_q;
    reg [15:0] redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_inputreg0_q;
    reg [15:0] redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_outputreg0_q;
    wire redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_reset0;
    wire [15:0] redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_ia;
    wire [6:0] redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_aa;
    wire [6:0] redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_ab;
    wire [15:0] redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_iq;
    wire [15:0] redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_q;
    wire [6:0] redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_wraddr_i = 7'b1111111;
    wire [6:0] redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_offset_q;
    wire [7:0] redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_a;
    wire [7:0] redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_b;
    logic [7:0] redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_o;
    wire [7:0] redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_q;
    reg [15:0] redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_inputreg0_q;
    reg [15:0] redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_outputreg0_q;
    wire redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_reset0;
    wire [15:0] redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_ia;
    wire [6:0] redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_aa;
    wire [6:0] redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_ab;
    wire [15:0] redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_iq;
    wire [15:0] redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_q;
    wire [6:0] redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_wraddr_i = 7'b1111111;
    wire [7:0] redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_a;
    wire [7:0] redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_b;
    logic [7:0] redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_o;
    wire [7:0] redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_q;
    reg [15:0] redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_inputreg0_q;
    reg [15:0] redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_outputreg0_q;
    wire redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_reset0;
    wire [15:0] redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_ia;
    wire [6:0] redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_aa;
    wire [6:0] redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_ab;
    wire [15:0] redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_iq;
    wire [15:0] redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_q;
    wire [6:0] redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_wraddr_i = 7'b1111111;
    wire [6:0] redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_offset_q;
    wire [7:0] redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_a;
    wire [7:0] redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_b;
    logic [7:0] redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_o;
    wire [7:0] redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_q;
    reg [15:0] redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_inputreg0_q;
    reg [15:0] redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_outputreg0_q;
    wire redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_reset0;
    wire [15:0] redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_ia;
    wire [6:0] redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_aa;
    wire [6:0] redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_ab;
    wire [15:0] redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_iq;
    wire [15:0] redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_q;
    wire [6:0] redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_wraddr_i = 7'b1111111;
    wire [7:0] redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_a;
    wire [7:0] redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_b;
    logic [7:0] redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_o;
    wire [7:0] redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_q;
    reg [15:0] redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_inputreg0_q;
    reg [15:0] redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_outputreg0_q;
    wire redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_reset0;
    wire [15:0] redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_ia;
    wire [6:0] redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_aa;
    wire [6:0] redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_ab;
    wire [15:0] redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_iq;
    wire [15:0] redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_q;
    wire [6:0] redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_wraddr_i = 7'b1111111;
    wire [6:0] redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_offset_q;
    wire [7:0] redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_a;
    wire [7:0] redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_b;
    logic [7:0] redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_o;
    wire [7:0] redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_q;
    reg [15:0] redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_inputreg0_q;
    reg [15:0] redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_outputreg0_q;
    wire redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_reset0;
    wire [15:0] redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_ia;
    wire [6:0] redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_aa;
    wire [6:0] redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_ab;
    wire [15:0] redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_iq;
    wire [15:0] redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_q;
    wire [6:0] redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_wraddr_i = 7'b1111111;
    wire [7:0] redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_a;
    wire [7:0] redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_b;
    logic [7:0] redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_o;
    wire [7:0] redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_q;
    reg [15:0] redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_inputreg0_q;
    reg [15:0] redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_outputreg0_q;
    wire redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_reset0;
    wire [15:0] redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_ia;
    wire [6:0] redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_aa;
    wire [6:0] redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_ab;
    wire [15:0] redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_iq;
    wire [15:0] redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_q;
    wire [6:0] redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_wraddr_i = 7'b1111111;
    wire [6:0] redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_offset_q;
    wire [7:0] redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_a;
    wire [7:0] redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_b;
    logic [7:0] redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_o;
    wire [7:0] redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_q;
    reg [15:0] redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_inputreg0_q;
    reg [15:0] redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_outputreg0_q;
    wire redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_reset0;
    wire [15:0] redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_ia;
    wire [6:0] redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_aa;
    wire [6:0] redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_ab;
    wire [15:0] redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_iq;
    wire [15:0] redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_q;
    wire [6:0] redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_wraddr_i = 7'b1111111;
    wire [7:0] redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_a;
    wire [7:0] redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_b;
    logic [7:0] redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_o;
    wire [7:0] redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_q;
    reg [15:0] redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_inputreg0_q;
    reg [15:0] redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_outputreg0_q;
    wire redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_reset0;
    wire [15:0] redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_ia;
    wire [6:0] redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_aa;
    wire [6:0] redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_ab;
    wire [15:0] redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_iq;
    wire [15:0] redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_q;
    wire [6:0] redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_wraddr_i = 7'b1111111;
    wire [6:0] redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_offset_q;
    wire [7:0] redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_a;
    wire [7:0] redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_b;
    logic [7:0] redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_o;
    wire [7:0] redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_q;
    reg [15:0] redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_inputreg0_q;
    reg [15:0] redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_outputreg0_q;
    wire redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_reset0;
    wire [15:0] redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_ia;
    wire [6:0] redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_aa;
    wire [6:0] redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_ab;
    wire [15:0] redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_iq;
    wire [15:0] redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_q;
    wire [6:0] redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_wraddr_i = 7'b1111111;
    wire [7:0] redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_a;
    wire [7:0] redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_b;
    logic [7:0] redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_o;
    wire [7:0] redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_q;
    reg [15:0] redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_inputreg0_q;
    reg [15:0] redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_outputreg0_q;
    wire redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_reset0;
    wire [15:0] redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_ia;
    wire [6:0] redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_aa;
    wire [6:0] redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_ab;
    wire [15:0] redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_iq;
    wire [15:0] redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_q;
    wire [6:0] redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_wraddr_i = 7'b1111111;
    wire [6:0] redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_offset_q;
    wire [7:0] redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_a;
    wire [7:0] redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_b;
    logic [7:0] redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_o;
    wire [7:0] redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_q;
    reg [15:0] redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_inputreg0_q;
    reg [15:0] redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_outputreg0_q;
    wire redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_reset0;
    wire [15:0] redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_ia;
    wire [6:0] redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_aa;
    wire [6:0] redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_ab;
    wire [15:0] redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_iq;
    wire [15:0] redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_q;
    wire [6:0] redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_wraddr_i = 7'b1111111;
    wire [7:0] redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_a;
    wire [7:0] redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_b;
    logic [7:0] redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_o;
    wire [7:0] redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_q;
    reg [15:0] redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_inputreg0_q;
    reg [15:0] redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_outputreg0_q;
    wire redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_reset0;
    wire [15:0] redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_ia;
    wire [6:0] redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_aa;
    wire [6:0] redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_ab;
    wire [15:0] redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_iq;
    wire [15:0] redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_q;
    wire [6:0] redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_wraddr_i = 7'b1111111;
    wire [6:0] redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_offset_q;
    wire [7:0] redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_a;
    wire [7:0] redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_b;
    logic [7:0] redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_o;
    wire [7:0] redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_q;
    reg [15:0] redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_inputreg0_q;
    reg [15:0] redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_outputreg0_q;
    wire redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_reset0;
    wire [15:0] redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_ia;
    wire [6:0] redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_aa;
    wire [6:0] redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_ab;
    wire [15:0] redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_iq;
    wire [15:0] redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_q;
    wire [6:0] redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_wraddr_i = 7'b1111111;
    wire [7:0] redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_a;
    wire [7:0] redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_b;
    logic [7:0] redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_o;
    wire [7:0] redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_q;
    reg [15:0] redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_inputreg0_q;
    reg [15:0] redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_outputreg0_q;
    wire redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_reset0;
    wire [15:0] redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_ia;
    wire [6:0] redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_aa;
    wire [6:0] redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_ab;
    wire [15:0] redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_iq;
    wire [15:0] redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_q;
    wire [6:0] redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_wraddr_i = 7'b1111111;
    wire [6:0] redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_offset_q;
    wire [7:0] redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_a;
    wire [7:0] redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_b;
    logic [7:0] redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_o;
    wire [7:0] redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_q;
    reg [15:0] redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_inputreg0_q;
    reg [15:0] redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_outputreg0_q;
    wire redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_reset0;
    wire [15:0] redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_ia;
    wire [6:0] redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_aa;
    wire [6:0] redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_ab;
    wire [15:0] redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_iq;
    wire [15:0] redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_q;
    wire [6:0] redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_wraddr_i = 7'b1111111;
    wire [7:0] redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_a;
    wire [7:0] redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_b;
    logic [7:0] redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_o;
    wire [7:0] redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_q;
    reg [15:0] redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_inputreg0_q;
    reg [15:0] redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_outputreg0_q;
    wire redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_reset0;
    wire [15:0] redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_ia;
    wire [6:0] redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_aa;
    wire [6:0] redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_ab;
    wire [15:0] redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_iq;
    wire [15:0] redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_q;
    wire [6:0] redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_wraddr_i = 7'b1111111;
    wire [6:0] redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_offset_q;
    wire [7:0] redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_a;
    wire [7:0] redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_b;
    logic [7:0] redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_o;
    wire [7:0] redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_q;
    reg [15:0] redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_inputreg0_q;
    reg [15:0] redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_outputreg0_q;
    wire redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_reset0;
    wire [15:0] redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_ia;
    wire [6:0] redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_aa;
    wire [6:0] redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_ab;
    wire [15:0] redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_iq;
    wire [15:0] redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_q;
    wire [6:0] redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_wraddr_i = 7'b1111111;
    wire [7:0] redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_a;
    wire [7:0] redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_b;
    logic [7:0] redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_o;
    wire [7:0] redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_q;
    reg [15:0] redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_inputreg0_q;
    reg [15:0] redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_outputreg0_q;
    wire redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_reset0;
    wire [15:0] redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_ia;
    wire [6:0] redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_aa;
    wire [6:0] redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_ab;
    wire [15:0] redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_iq;
    wire [15:0] redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_q;
    wire [6:0] redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_wraddr_i = 7'b1111111;
    wire [6:0] redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_offset_q;
    wire [7:0] redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_a;
    wire [7:0] redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_b;
    logic [7:0] redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_o;
    wire [7:0] redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_q;
    reg [15:0] redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_inputreg0_q;
    reg [15:0] redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_outputreg0_q;
    wire redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_reset0;
    wire [15:0] redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_ia;
    wire [6:0] redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_aa;
    wire [6:0] redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_ab;
    wire [15:0] redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_iq;
    wire [15:0] redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_q;
    wire [6:0] redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_wraddr_i = 7'b1111111;
    wire [7:0] redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_a;
    wire [7:0] redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_b;
    logic [7:0] redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_o;
    wire [7:0] redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_q;
    reg [15:0] redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_inputreg0_q;
    reg [15:0] redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_outputreg0_q;
    wire redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_reset0;
    wire [15:0] redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_ia;
    wire [6:0] redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_aa;
    wire [6:0] redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_ab;
    wire [15:0] redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_iq;
    wire [15:0] redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_q;
    wire [6:0] redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_wraddr_i = 7'b1111111;
    wire [6:0] redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_offset_q;
    wire [7:0] redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_a;
    wire [7:0] redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_b;
    logic [7:0] redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_o;
    wire [7:0] redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_q;
    reg [15:0] redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_inputreg0_q;
    reg [15:0] redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_outputreg0_q;
    wire redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_reset0;
    wire [15:0] redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_ia;
    wire [6:0] redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_aa;
    wire [6:0] redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_ab;
    wire [15:0] redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_iq;
    wire [15:0] redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_q;
    wire [6:0] redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_wraddr_i = 7'b1111111;
    wire [7:0] redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_a;
    wire [7:0] redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_b;
    logic [7:0] redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_o;
    wire [7:0] redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_q;
    reg [15:0] redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_inputreg0_q;
    reg [15:0] redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_outputreg0_q;
    wire redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_reset0;
    wire [15:0] redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_ia;
    wire [6:0] redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_aa;
    wire [6:0] redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_ab;
    wire [15:0] redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_iq;
    wire [15:0] redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_q;
    wire [6:0] redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_wraddr_i = 7'b1111111;
    wire [6:0] redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_offset_q;
    wire [7:0] redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_a;
    wire [7:0] redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_b;
    logic [7:0] redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_o;
    wire [7:0] redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_q;
    reg [15:0] redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_inputreg0_q;
    reg [15:0] redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_outputreg0_q;
    wire redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_reset0;
    wire [15:0] redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_ia;
    wire [6:0] redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_aa;
    wire [6:0] redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_ab;
    wire [15:0] redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_iq;
    wire [15:0] redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_q;
    wire [6:0] redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_wraddr_i = 7'b1111111;
    wire [7:0] redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_a;
    wire [7:0] redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_b;
    logic [7:0] redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_o;
    wire [7:0] redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_q;
    reg [15:0] redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_inputreg0_q;
    reg [15:0] redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_outputreg0_q;
    wire redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_reset0;
    wire [15:0] redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_ia;
    wire [6:0] redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_aa;
    wire [6:0] redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_ab;
    wire [15:0] redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_iq;
    wire [15:0] redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_q;
    wire [6:0] redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_wraddr_i = 7'b1111111;
    wire [6:0] redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_offset_q;
    wire [7:0] redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_a;
    wire [7:0] redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_b;
    logic [7:0] redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_o;
    wire [7:0] redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_q;
    reg [15:0] redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_inputreg0_q;
    reg [15:0] redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_outputreg0_q;
    wire redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_reset0;
    wire [15:0] redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_ia;
    wire [6:0] redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_aa;
    wire [6:0] redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_ab;
    wire [15:0] redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_iq;
    wire [15:0] redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_q;
    wire [6:0] redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_wraddr_i = 7'b1111111;
    wire [7:0] redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_a;
    wire [7:0] redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_b;
    logic [7:0] redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_o;
    wire [7:0] redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_q;
    reg [15:0] redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_inputreg0_q;
    reg [15:0] redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_outputreg0_q;
    wire redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_reset0;
    wire [15:0] redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_ia;
    wire [7:0] redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_aa;
    wire [7:0] redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_ab;
    wire [15:0] redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_iq;
    wire [15:0] redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_q;
    wire [7:0] redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_wraddr_i = 8'b11111111;
    wire [7:0] redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_offset_q;
    wire [8:0] redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_a;
    wire [8:0] redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_b;
    logic [8:0] redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_o;
    wire [8:0] redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_q;
    reg [15:0] redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_inputreg0_q;
    reg [15:0] redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_outputreg0_q;
    wire redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_reset0;
    wire [15:0] redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_ia;
    wire [7:0] redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_aa;
    wire [7:0] redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_ab;
    wire [15:0] redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_iq;
    wire [15:0] redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_q;
    wire [7:0] redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_wraddr_i = 8'b11111111;
    wire [8:0] redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_a;
    wire [8:0] redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_b;
    logic [8:0] redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_o;
    wire [8:0] redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_q;
    reg [15:0] redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_inputreg0_q;
    reg [15:0] redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_outputreg0_q;
    wire redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_reset0;
    wire [15:0] redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_ia;
    wire [7:0] redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_aa;
    wire [7:0] redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_ab;
    wire [15:0] redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_iq;
    wire [15:0] redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_q;
    wire [7:0] redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_wraddr_i = 8'b11111111;
    wire [7:0] redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_offset_q;
    wire [8:0] redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_a;
    wire [8:0] redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_b;
    logic [8:0] redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_o;
    wire [8:0] redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_q;
    reg [15:0] redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_inputreg0_q;
    reg [15:0] redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_outputreg0_q;
    wire redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_reset0;
    wire [15:0] redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_ia;
    wire [7:0] redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_aa;
    wire [7:0] redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_ab;
    wire [15:0] redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_iq;
    wire [15:0] redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_q;
    wire [7:0] redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_wraddr_i = 8'b11111111;
    wire [8:0] redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_a;
    wire [8:0] redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_b;
    logic [8:0] redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_o;
    wire [8:0] redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_q;
    reg [15:0] redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_inputreg0_q;
    reg [15:0] redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_outputreg0_q;
    wire redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_reset0;
    wire [15:0] redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_ia;
    wire [7:0] redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_aa;
    wire [7:0] redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_ab;
    wire [15:0] redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_iq;
    wire [15:0] redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_q;
    wire [7:0] redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_wraddr_i = 8'b11111111;
    wire [7:0] redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_offset_q;
    wire [8:0] redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_a;
    wire [8:0] redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_b;
    logic [8:0] redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_o;
    wire [8:0] redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_q;
    reg [15:0] redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_inputreg0_q;
    reg [15:0] redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_outputreg0_q;
    wire redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_reset0;
    wire [15:0] redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_ia;
    wire [7:0] redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_aa;
    wire [7:0] redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_ab;
    wire [15:0] redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_iq;
    wire [15:0] redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_q;
    wire [7:0] redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_wraddr_i = 8'b11111111;
    wire [8:0] redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_a;
    wire [8:0] redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_b;
    logic [8:0] redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_o;
    wire [8:0] redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_q;
    reg [15:0] redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_inputreg0_q;
    reg [15:0] redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_outputreg0_q;
    wire redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_reset0;
    wire [15:0] redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_ia;
    wire [7:0] redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_aa;
    wire [7:0] redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_ab;
    wire [15:0] redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_iq;
    wire [15:0] redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_q;
    wire [7:0] redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_wraddr_i = 8'b11111111;
    wire [7:0] redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_offset_q;
    wire [8:0] redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_a;
    wire [8:0] redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_b;
    logic [8:0] redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_o;
    wire [8:0] redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_q;
    reg [15:0] redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_inputreg0_q;
    reg [15:0] redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_outputreg0_q;
    wire redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_reset0;
    wire [15:0] redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_ia;
    wire [7:0] redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_aa;
    wire [7:0] redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_ab;
    wire [15:0] redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_iq;
    wire [15:0] redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_q;
    wire [7:0] redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_wraddr_i = 8'b11111111;
    wire [8:0] redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_a;
    wire [8:0] redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_b;
    logic [8:0] redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_o;
    wire [8:0] redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_q;
    reg [15:0] redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_inputreg0_q;
    reg [15:0] redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_outputreg0_q;
    wire redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_reset0;
    wire [15:0] redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_ia;
    wire [7:0] redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_aa;
    wire [7:0] redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_ab;
    wire [15:0] redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_iq;
    wire [15:0] redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_q;
    wire [7:0] redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_wraddr_i = 8'b11111111;
    wire [7:0] redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_offset_q;
    wire [8:0] redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_a;
    wire [8:0] redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_b;
    logic [8:0] redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_o;
    wire [8:0] redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_q;
    reg [15:0] redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_inputreg0_q;
    reg [15:0] redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_outputreg0_q;
    wire redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_reset0;
    wire [15:0] redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_ia;
    wire [7:0] redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_aa;
    wire [7:0] redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_ab;
    wire [15:0] redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_iq;
    wire [15:0] redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_q;
    wire [7:0] redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_wraddr_i = 8'b11111111;
    wire [8:0] redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_a;
    wire [8:0] redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_b;
    logic [8:0] redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_o;
    wire [8:0] redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_q;
    reg [15:0] redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_inputreg0_q;
    reg [15:0] redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_outputreg0_q;
    wire redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_reset0;
    wire [15:0] redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_ia;
    wire [7:0] redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_aa;
    wire [7:0] redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_ab;
    wire [15:0] redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_iq;
    wire [15:0] redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_q;
    wire [7:0] redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_wraddr_i = 8'b11111111;
    wire [7:0] redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_offset_q;
    wire [8:0] redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_a;
    wire [8:0] redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_b;
    logic [8:0] redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_o;
    wire [8:0] redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_q;
    reg [15:0] redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_inputreg0_q;
    reg [15:0] redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_outputreg0_q;
    wire redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_reset0;
    wire [15:0] redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_ia;
    wire [7:0] redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_aa;
    wire [7:0] redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_ab;
    wire [15:0] redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_iq;
    wire [15:0] redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_q;
    wire [7:0] redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_wraddr_i = 8'b11111111;
    wire [8:0] redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_a;
    wire [8:0] redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_b;
    logic [8:0] redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_o;
    wire [8:0] redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_q;
    reg [15:0] redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_inputreg0_q;
    reg [15:0] redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_outputreg0_q;
    wire redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_reset0;
    wire [15:0] redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_ia;
    wire [7:0] redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_aa;
    wire [7:0] redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_ab;
    wire [15:0] redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_iq;
    wire [15:0] redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_q;
    wire [7:0] redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_wraddr_i = 8'b11111111;
    wire [7:0] redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_offset_q;
    wire [8:0] redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_a;
    wire [8:0] redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_b;
    logic [8:0] redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_o;
    wire [8:0] redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_q;
    reg [15:0] redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_inputreg0_q;
    reg [15:0] redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_outputreg0_q;
    wire redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_reset0;
    wire [15:0] redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_ia;
    wire [7:0] redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_aa;
    wire [7:0] redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_ab;
    wire [15:0] redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_iq;
    wire [15:0] redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_q;
    wire [7:0] redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_wraddr_i = 8'b11111111;
    wire [8:0] redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_a;
    wire [8:0] redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_b;
    logic [8:0] redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_o;
    wire [8:0] redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_q;
    reg [15:0] redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_inputreg0_q;
    reg [15:0] redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_outputreg0_q;
    wire redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_reset0;
    wire [15:0] redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_ia;
    wire [7:0] redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_aa;
    wire [7:0] redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_ab;
    wire [15:0] redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_iq;
    wire [15:0] redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_q;
    wire [7:0] redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_wraddr_i = 8'b11111111;
    wire [7:0] redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_offset_q;
    wire [8:0] redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_a;
    wire [8:0] redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_b;
    logic [8:0] redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_o;
    wire [8:0] redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_q;
    reg [15:0] redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_inputreg0_q;
    reg [15:0] redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_outputreg0_q;
    wire redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_reset0;
    wire [15:0] redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_ia;
    wire [7:0] redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_aa;
    wire [7:0] redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_ab;
    wire [15:0] redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_iq;
    wire [15:0] redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_q;
    wire [7:0] redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_wraddr_i = 8'b11111111;
    wire [8:0] redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_a;
    wire [8:0] redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_b;
    logic [8:0] redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_o;
    wire [8:0] redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_q;
    reg [15:0] redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_inputreg0_q;
    reg [15:0] redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_outputreg0_q;
    wire redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_reset0;
    wire [15:0] redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_ia;
    wire [7:0] redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_aa;
    wire [7:0] redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_ab;
    wire [15:0] redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_iq;
    wire [15:0] redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_q;
    wire [7:0] redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_wraddr_i = 8'b11111111;
    wire [7:0] redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_offset_q;
    wire [8:0] redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_a;
    wire [8:0] redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_b;
    logic [8:0] redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_o;
    wire [8:0] redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_q;
    reg [15:0] redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_inputreg0_q;
    reg [15:0] redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_outputreg0_q;
    wire redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_reset0;
    wire [15:0] redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_ia;
    wire [7:0] redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_aa;
    wire [7:0] redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_ab;
    wire [15:0] redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_iq;
    wire [15:0] redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_q;
    wire [7:0] redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_wraddr_i = 8'b11111111;
    wire [8:0] redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_a;
    wire [8:0] redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_b;
    logic [8:0] redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_o;
    wire [8:0] redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_q;
    reg [15:0] redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_inputreg0_q;
    reg [15:0] redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_outputreg0_q;
    wire redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_reset0;
    wire [15:0] redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_ia;
    wire [7:0] redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_aa;
    wire [7:0] redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_ab;
    wire [15:0] redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_iq;
    wire [15:0] redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_q;
    wire [7:0] redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_wraddr_i = 8'b11111111;
    wire [7:0] redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_offset_q;
    wire [8:0] redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_a;
    wire [8:0] redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_b;
    logic [8:0] redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_o;
    wire [8:0] redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_q;
    reg [15:0] redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_inputreg0_q;
    reg [15:0] redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_outputreg0_q;
    wire redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_reset0;
    wire [15:0] redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_ia;
    wire [7:0] redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_aa;
    wire [7:0] redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_ab;
    wire [15:0] redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_iq;
    wire [15:0] redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_q;
    wire [7:0] redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_wraddr_i = 8'b11111111;
    wire [8:0] redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_a;
    wire [8:0] redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_b;
    logic [8:0] redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_o;
    wire [8:0] redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_q;
    reg [15:0] redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_inputreg0_q;
    reg [15:0] redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_outputreg0_q;
    wire redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_reset0;
    wire [15:0] redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_ia;
    wire [7:0] redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_aa;
    wire [7:0] redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_ab;
    wire [15:0] redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_iq;
    wire [15:0] redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_q;
    wire [7:0] redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_wraddr_i = 8'b11111111;
    wire [7:0] redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_offset_q;
    wire [8:0] redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_a;
    wire [8:0] redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_b;
    logic [8:0] redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_o;
    wire [8:0] redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_q;
    reg [15:0] redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_inputreg0_q;
    reg [15:0] redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_outputreg0_q;
    wire redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_reset0;
    wire [15:0] redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_ia;
    wire [7:0] redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_aa;
    wire [7:0] redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_ab;
    wire [15:0] redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_iq;
    wire [15:0] redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_q;
    wire [7:0] redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_wraddr_i = 8'b11111111;
    wire [8:0] redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_a;
    wire [8:0] redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_b;
    logic [8:0] redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_o;
    wire [8:0] redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_q;
    reg [15:0] redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_inputreg0_q;
    reg [15:0] redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_outputreg0_q;
    wire redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_reset0;
    wire [15:0] redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_ia;
    wire [7:0] redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_aa;
    wire [7:0] redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_ab;
    wire [15:0] redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_iq;
    wire [15:0] redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_q;
    wire [7:0] redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_wraddr_i = 8'b11111111;
    wire [7:0] redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_offset_q;
    wire [8:0] redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_a;
    wire [8:0] redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_b;
    logic [8:0] redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_o;
    wire [8:0] redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_q;
    reg [15:0] redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_inputreg0_q;
    reg [15:0] redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_outputreg0_q;
    wire redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_reset0;
    wire [15:0] redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_ia;
    wire [7:0] redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_aa;
    wire [7:0] redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_ab;
    wire [15:0] redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_iq;
    wire [15:0] redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_q;
    wire [7:0] redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_wraddr_i = 8'b11111111;
    wire [8:0] redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_a;
    wire [8:0] redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_b;
    logic [8:0] redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_o;
    wire [8:0] redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_q;
    reg [15:0] redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_inputreg0_q;
    reg [15:0] redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_outputreg0_q;
    wire redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_reset0;
    wire [15:0] redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_ia;
    wire [7:0] redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_aa;
    wire [7:0] redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_ab;
    wire [15:0] redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_iq;
    wire [15:0] redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_q;
    wire [7:0] redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_wraddr_i = 8'b11111111;
    wire [7:0] redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_offset_q;
    wire [8:0] redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_a;
    wire [8:0] redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_b;
    logic [8:0] redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_o;
    wire [8:0] redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_q;
    reg [15:0] redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_inputreg0_q;
    reg [15:0] redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_outputreg0_q;
    wire redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_reset0;
    wire [15:0] redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_ia;
    wire [7:0] redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_aa;
    wire [7:0] redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_ab;
    wire [15:0] redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_iq;
    wire [15:0] redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_q;
    wire [7:0] redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_wraddr_i = 8'b11111111;
    wire [8:0] redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_a;
    wire [8:0] redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_b;
    logic [8:0] redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_o;
    wire [8:0] redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_q;
    reg [15:0] redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_inputreg0_q;
    reg [15:0] redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_outputreg0_q;
    wire redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_reset0;
    wire [15:0] redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_ia;
    wire [7:0] redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_aa;
    wire [7:0] redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_ab;
    wire [15:0] redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_iq;
    wire [15:0] redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_q;
    wire [7:0] redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_wraddr_i = 8'b11111111;
    wire [7:0] redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_offset_q;
    wire [8:0] redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_a;
    wire [8:0] redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_b;
    logic [8:0] redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_o;
    wire [8:0] redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_q;
    reg [15:0] redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_inputreg0_q;
    reg [15:0] redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_outputreg0_q;
    wire redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_reset0;
    wire [15:0] redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_ia;
    wire [7:0] redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_aa;
    wire [7:0] redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_ab;
    wire [15:0] redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_iq;
    wire [15:0] redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_q;
    wire [7:0] redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_wraddr_i = 8'b11111111;
    wire [8:0] redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_a;
    wire [8:0] redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_b;
    logic [8:0] redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_o;
    wire [8:0] redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_q;
    reg [15:0] redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_inputreg0_q;
    reg [15:0] redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_outputreg0_q;
    wire redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_reset0;
    wire [15:0] redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_ia;
    wire [7:0] redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_aa;
    wire [7:0] redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_ab;
    wire [15:0] redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_iq;
    wire [15:0] redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_q;
    wire [7:0] redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_wraddr_i = 8'b11111111;
    wire [7:0] redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_offset_q;
    wire [8:0] redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_a;
    wire [8:0] redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_b;
    logic [8:0] redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_o;
    wire [8:0] redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_q;
    reg [15:0] redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_inputreg0_q;
    reg [15:0] redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_outputreg0_q;
    wire redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_reset0;
    wire [15:0] redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_ia;
    wire [7:0] redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_aa;
    wire [7:0] redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_ab;
    wire [15:0] redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_iq;
    wire [15:0] redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_q;
    wire [7:0] redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_wraddr_i = 8'b11111111;
    wire [8:0] redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_a;
    wire [8:0] redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_b;
    logic [8:0] redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_o;
    wire [8:0] redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_q;
    reg [15:0] redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_inputreg0_q;
    reg [15:0] redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_outputreg0_q;
    wire redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_reset0;
    wire [15:0] redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_ia;
    wire [7:0] redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_aa;
    wire [7:0] redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_ab;
    wire [15:0] redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_iq;
    wire [15:0] redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_q;
    wire [7:0] redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_wraddr_i = 8'b11111111;
    wire [7:0] redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_offset_q;
    wire [8:0] redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_a;
    wire [8:0] redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_b;
    logic [8:0] redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_o;
    wire [8:0] redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_q;
    reg [15:0] redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_inputreg0_q;
    reg [15:0] redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_outputreg0_q;
    wire redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_reset0;
    wire [15:0] redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_ia;
    wire [7:0] redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_aa;
    wire [7:0] redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_ab;
    wire [15:0] redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_iq;
    wire [15:0] redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_q;
    wire [7:0] redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_wraddr_i = 8'b11111111;
    wire [8:0] redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_a;
    wire [8:0] redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_b;
    logic [8:0] redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_o;
    wire [8:0] redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_q;
    reg [15:0] redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_inputreg0_q;
    reg [15:0] redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_outputreg0_q;
    wire redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_reset0;
    wire [15:0] redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_ia;
    wire [7:0] redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_aa;
    wire [7:0] redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_ab;
    wire [15:0] redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_iq;
    wire [15:0] redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_q;
    wire [7:0] redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_wraddr_i = 8'b11111111;
    wire [7:0] redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_offset_q;
    wire [8:0] redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_a;
    wire [8:0] redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_b;
    logic [8:0] redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_o;
    wire [8:0] redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_q;
    reg [15:0] redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_inputreg0_q;
    reg [15:0] redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_outputreg0_q;
    wire redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_reset0;
    wire [15:0] redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_ia;
    wire [7:0] redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_aa;
    wire [7:0] redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_ab;
    wire [15:0] redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_iq;
    wire [15:0] redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_q;
    wire [7:0] redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_wraddr_i = 8'b11111111;
    wire [8:0] redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_a;
    wire [8:0] redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_b;
    logic [8:0] redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_o;
    wire [8:0] redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_q;
    reg [15:0] redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_inputreg0_q;
    reg [15:0] redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_outputreg0_q;
    wire redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_reset0;
    wire [15:0] redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_ia;
    wire [7:0] redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_aa;
    wire [7:0] redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_ab;
    wire [15:0] redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_iq;
    wire [15:0] redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_q;
    wire [7:0] redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_wraddr_i = 8'b11111111;
    wire [7:0] redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_offset_q;
    wire [8:0] redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_a;
    wire [8:0] redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_b;
    logic [8:0] redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_o;
    wire [8:0] redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_q;
    reg [15:0] redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_inputreg0_q;
    reg [15:0] redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_outputreg0_q;
    wire redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_reset0;
    wire [15:0] redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_ia;
    wire [7:0] redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_aa;
    wire [7:0] redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_ab;
    wire [15:0] redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_iq;
    wire [15:0] redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_q;
    wire [7:0] redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_wraddr_i = 8'b11111111;
    wire [8:0] redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_a;
    wire [8:0] redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_b;
    logic [8:0] redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_o;
    wire [8:0] redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_q;
    reg [15:0] redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_inputreg0_q;
    reg [15:0] redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_outputreg0_q;
    wire redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_reset0;
    wire [15:0] redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_ia;
    wire [7:0] redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_aa;
    wire [7:0] redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_ab;
    wire [15:0] redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_iq;
    wire [15:0] redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_q;
    wire [7:0] redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_wraddr_i = 8'b11111111;
    wire [7:0] redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_offset_q;
    wire [8:0] redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_a;
    wire [8:0] redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_b;
    logic [8:0] redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_o;
    wire [8:0] redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_q;
    reg [15:0] redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_inputreg0_q;
    reg [15:0] redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_outputreg0_q;
    wire redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_reset0;
    wire [15:0] redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_ia;
    wire [7:0] redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_aa;
    wire [7:0] redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_ab;
    wire [15:0] redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_iq;
    wire [15:0] redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_q;
    wire [7:0] redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_wraddr_i = 8'b11111111;
    wire [8:0] redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_a;
    wire [8:0] redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_b;
    logic [8:0] redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_o;
    wire [8:0] redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_q;
    reg [15:0] redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_inputreg0_q;
    reg [15:0] redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_outputreg0_q;
    wire redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_reset0;
    wire [15:0] redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_ia;
    wire [7:0] redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_aa;
    wire [7:0] redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_ab;
    wire [15:0] redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_iq;
    wire [15:0] redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_q;
    wire [7:0] redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_wraddr_i = 8'b11111111;
    wire [7:0] redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_offset_q;
    wire [8:0] redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_a;
    wire [8:0] redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_b;
    logic [8:0] redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_o;
    wire [8:0] redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_q;
    reg [15:0] redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_inputreg0_q;
    reg [15:0] redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_outputreg0_q;
    wire redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_reset0;
    wire [15:0] redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_ia;
    wire [7:0] redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_aa;
    wire [7:0] redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_ab;
    wire [15:0] redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_iq;
    wire [15:0] redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_q;
    wire [7:0] redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_wraddr_i = 8'b11111111;
    wire [8:0] redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_a;
    wire [8:0] redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_b;
    logic [8:0] redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_o;
    wire [8:0] redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_q;
    reg [15:0] redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_inputreg0_q;
    reg [15:0] redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_outputreg0_q;
    wire redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_reset0;
    wire [15:0] redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_ia;
    wire [7:0] redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_aa;
    wire [7:0] redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_ab;
    wire [15:0] redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_iq;
    wire [15:0] redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_q;
    wire [7:0] redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_wraddr_i = 8'b11111111;
    wire [7:0] redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_offset_q;
    wire [8:0] redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_a;
    wire [8:0] redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_b;
    logic [8:0] redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_o;
    wire [8:0] redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_q;
    reg [15:0] redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_inputreg0_q;
    reg [15:0] redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_outputreg0_q;
    wire redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_reset0;
    wire [15:0] redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_ia;
    wire [7:0] redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_aa;
    wire [7:0] redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_ab;
    wire [15:0] redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_iq;
    wire [15:0] redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_q;
    wire [7:0] redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_wraddr_i = 8'b11111111;
    wire [8:0] redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_a;
    wire [8:0] redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_b;
    logic [8:0] redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_o;
    wire [8:0] redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_q;
    reg [15:0] redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_inputreg0_q;
    reg [15:0] redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_outputreg0_q;
    wire redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_reset0;
    wire [15:0] redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_ia;
    wire [7:0] redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_aa;
    wire [7:0] redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_ab;
    wire [15:0] redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_iq;
    wire [15:0] redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_q;
    wire [7:0] redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_wraddr_i = 8'b11111111;
    wire [7:0] redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_offset_q;
    wire [8:0] redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_a;
    wire [8:0] redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_b;
    logic [8:0] redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_o;
    wire [8:0] redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_q;
    reg [15:0] redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_inputreg0_q;
    reg [15:0] redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_outputreg0_q;
    wire redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_reset0;
    wire [15:0] redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_ia;
    wire [7:0] redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_aa;
    wire [7:0] redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_ab;
    wire [15:0] redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_iq;
    wire [15:0] redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_q;
    wire [7:0] redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_wraddr_i = 8'b11111111;
    wire [8:0] redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_a;
    wire [8:0] redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_b;
    logic [8:0] redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_o;
    wire [8:0] redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_q;
    reg [15:0] redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_inputreg0_q;
    reg [15:0] redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_outputreg0_q;
    wire redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_reset0;
    wire [15:0] redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_ia;
    wire [7:0] redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_aa;
    wire [7:0] redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_ab;
    wire [15:0] redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_iq;
    wire [15:0] redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_q;
    wire [7:0] redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_wraddr_i = 8'b11111111;
    wire [7:0] redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_offset_q;
    wire [8:0] redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_a;
    wire [8:0] redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_b;
    logic [8:0] redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_o;
    wire [8:0] redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_q;
    reg [15:0] redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_inputreg0_q;
    reg [15:0] redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_outputreg0_q;
    wire redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_reset0;
    wire [15:0] redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_ia;
    wire [7:0] redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_aa;
    wire [7:0] redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_ab;
    wire [15:0] redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_iq;
    wire [15:0] redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_q;
    wire [7:0] redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_wraddr_i = 8'b11111111;
    wire [8:0] redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_a;
    wire [8:0] redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_b;
    logic [8:0] redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_o;
    wire [8:0] redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_q;
    reg [15:0] redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_inputreg0_q;
    reg [15:0] redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_outputreg0_q;
    wire redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_reset0;
    wire [15:0] redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_ia;
    wire [7:0] redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_aa;
    wire [7:0] redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_ab;
    wire [15:0] redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_iq;
    wire [15:0] redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_q;
    wire [7:0] redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_wraddr_i = 8'b11111111;
    wire [7:0] redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_offset_q;
    wire [8:0] redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_a;
    wire [8:0] redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_b;
    logic [8:0] redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_o;
    wire [8:0] redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_q;
    reg [15:0] redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_inputreg0_q;
    reg [15:0] redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_outputreg0_q;
    wire redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_reset0;
    wire [15:0] redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_ia;
    wire [7:0] redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_aa;
    wire [7:0] redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_ab;
    wire [15:0] redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_iq;
    wire [15:0] redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_q;
    wire [7:0] redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_wraddr_i = 8'b11111111;
    wire [8:0] redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_a;
    wire [8:0] redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_b;
    logic [8:0] redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_o;
    wire [8:0] redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_q;
    reg [15:0] redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_inputreg0_q;
    reg [15:0] redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_outputreg0_q;
    wire redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_reset0;
    wire [15:0] redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_ia;
    wire [7:0] redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_aa;
    wire [7:0] redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_ab;
    wire [15:0] redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_iq;
    wire [15:0] redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_q;
    wire [7:0] redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_wraddr_i = 8'b11111111;
    wire [7:0] redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_offset_q;
    wire [8:0] redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_a;
    wire [8:0] redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_b;
    logic [8:0] redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_o;
    wire [8:0] redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_q;
    reg [15:0] redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_inputreg0_q;
    reg [15:0] redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_outputreg0_q;
    wire redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_reset0;
    wire [15:0] redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_ia;
    wire [7:0] redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_aa;
    wire [7:0] redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_ab;
    wire [15:0] redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_iq;
    wire [15:0] redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_q;
    wire [7:0] redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_wraddr_i = 8'b11111111;
    wire [8:0] redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_a;
    wire [8:0] redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_b;
    logic [8:0] redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_o;
    wire [8:0] redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_q;
    reg [15:0] redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_inputreg0_q;
    reg [15:0] redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_outputreg0_q;
    wire redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_reset0;
    wire [15:0] redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_ia;
    wire [7:0] redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_aa;
    wire [7:0] redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_ab;
    wire [15:0] redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_iq;
    wire [15:0] redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_q;
    wire [7:0] redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_wraddr_i = 8'b11111111;
    wire [7:0] redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_offset_q;
    wire [8:0] redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_a;
    wire [8:0] redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_b;
    logic [8:0] redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_o;
    wire [8:0] redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_q;
    reg [15:0] redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_inputreg0_q;
    reg [15:0] redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_outputreg0_q;
    wire redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_reset0;
    wire [15:0] redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_ia;
    wire [7:0] redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_aa;
    wire [7:0] redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_ab;
    wire [15:0] redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_iq;
    wire [15:0] redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_q;
    wire [7:0] redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_wraddr_i = 8'b11111111;
    wire [8:0] redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_a;
    wire [8:0] redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_b;
    logic [8:0] redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_o;
    wire [8:0] redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_q;
    reg [15:0] redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_inputreg0_q;
    reg [15:0] redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_outputreg0_q;
    wire redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_reset0;
    wire [15:0] redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_ia;
    wire [7:0] redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_aa;
    wire [7:0] redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_ab;
    wire [15:0] redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_iq;
    wire [15:0] redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_q;
    wire [7:0] redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_wraddr_i = 8'b11111111;
    wire [7:0] redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_offset_q;
    wire [8:0] redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_a;
    wire [8:0] redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_b;
    logic [8:0] redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_o;
    wire [8:0] redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_q;
    reg [15:0] redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_inputreg0_q;
    reg [15:0] redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_outputreg0_q;
    wire redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_reset0;
    wire [15:0] redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_ia;
    wire [7:0] redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_aa;
    wire [7:0] redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_ab;
    wire [15:0] redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_iq;
    wire [15:0] redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_q;
    wire [7:0] redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_wraddr_i = 8'b11111111;
    wire [8:0] redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_a;
    wire [8:0] redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_b;
    logic [8:0] redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_o;
    wire [8:0] redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_q;
    reg [15:0] redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_inputreg0_q;
    reg [15:0] redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_outputreg0_q;
    wire redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_reset0;
    wire [15:0] redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_ia;
    wire [7:0] redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_aa;
    wire [7:0] redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_ab;
    wire [15:0] redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_iq;
    wire [15:0] redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_q;
    wire [7:0] redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_wraddr_i = 8'b11111111;
    wire [7:0] redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_offset_q;
    wire [8:0] redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_a;
    wire [8:0] redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_b;
    logic [8:0] redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_o;
    wire [8:0] redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_q;
    reg [15:0] redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_inputreg0_q;
    reg [15:0] redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_outputreg0_q;
    wire redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_reset0;
    wire [15:0] redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_ia;
    wire [7:0] redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_aa;
    wire [7:0] redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_ab;
    wire [15:0] redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_iq;
    wire [15:0] redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_q;
    wire [7:0] redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_wraddr_i = 8'b11111111;
    wire [8:0] redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_a;
    wire [8:0] redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_b;
    logic [8:0] redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_o;
    wire [8:0] redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_q;
    reg [15:0] redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_inputreg0_q;
    reg [15:0] redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_outputreg0_q;
    wire redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_reset0;
    wire [15:0] redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_ia;
    wire [7:0] redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_aa;
    wire [7:0] redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_ab;
    wire [15:0] redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_iq;
    wire [15:0] redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_q;
    wire [7:0] redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_wraddr_i = 8'b11111111;
    wire [7:0] redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_offset_q;
    wire [8:0] redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_a;
    wire [8:0] redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_b;
    logic [8:0] redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_o;
    wire [8:0] redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_q;
    reg [15:0] redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_inputreg0_q;
    reg [15:0] redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_outputreg0_q;
    wire redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_reset0;
    wire [15:0] redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_ia;
    wire [7:0] redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_aa;
    wire [7:0] redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_ab;
    wire [15:0] redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_iq;
    wire [15:0] redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_q;
    wire [7:0] redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_wraddr_i = 8'b11111111;
    wire [8:0] redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_a;
    wire [8:0] redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_b;
    logic [8:0] redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_o;
    wire [8:0] redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_q;
    reg [15:0] redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_inputreg0_q;
    reg [15:0] redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_outputreg0_q;
    wire redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_reset0;
    wire [15:0] redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_ia;
    wire [7:0] redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_aa;
    wire [7:0] redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_ab;
    wire [15:0] redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_iq;
    wire [15:0] redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_q;
    wire [7:0] redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_wraddr_i = 8'b11111111;
    wire [7:0] redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_offset_q;
    wire [8:0] redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_a;
    wire [8:0] redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_b;
    logic [8:0] redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_o;
    wire [8:0] redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_q;
    reg [15:0] redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_inputreg0_q;
    reg [15:0] redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_outputreg0_q;
    wire redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_reset0;
    wire [15:0] redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_ia;
    wire [7:0] redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_aa;
    wire [7:0] redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_ab;
    wire [15:0] redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_iq;
    wire [15:0] redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_q;
    wire [7:0] redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_wraddr_i = 8'b11111111;
    wire [8:0] redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_a;
    wire [8:0] redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_b;
    logic [8:0] redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_o;
    wire [8:0] redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_q;
    reg [15:0] redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_inputreg0_q;
    reg [15:0] redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_outputreg0_q;
    wire redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_reset0;
    wire [15:0] redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_ia;
    wire [7:0] redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_aa;
    wire [7:0] redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_ab;
    wire [15:0] redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_iq;
    wire [15:0] redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_q;
    wire [7:0] redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_wraddr_i = 8'b11111111;
    wire [7:0] redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_offset_q;
    wire [8:0] redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_a;
    wire [8:0] redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_b;
    logic [8:0] redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_o;
    wire [8:0] redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_q;
    reg [15:0] redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_inputreg0_q;
    reg [15:0] redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_outputreg0_q;
    wire redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_reset0;
    wire [15:0] redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_ia;
    wire [7:0] redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_aa;
    wire [7:0] redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_ab;
    wire [15:0] redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_iq;
    wire [15:0] redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_q;
    wire [7:0] redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_wraddr_i = 8'b11111111;
    wire [8:0] redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_a;
    wire [8:0] redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_b;
    logic [8:0] redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_o;
    wire [8:0] redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_q;
    reg [15:0] redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_inputreg0_q;
    reg [15:0] redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_outputreg0_q;
    wire redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_reset0;
    wire [15:0] redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_ia;
    wire [7:0] redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_aa;
    wire [7:0] redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_ab;
    wire [15:0] redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_iq;
    wire [15:0] redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_q;
    wire [7:0] redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_wraddr_i = 8'b11111111;
    wire [7:0] redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_offset_q;
    wire [8:0] redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_a;
    wire [8:0] redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_b;
    logic [8:0] redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_o;
    wire [8:0] redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_q;
    reg [15:0] redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_inputreg0_q;
    reg [15:0] redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_outputreg0_q;
    wire redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_reset0;
    wire [15:0] redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_ia;
    wire [7:0] redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_aa;
    wire [7:0] redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_ab;
    wire [15:0] redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_iq;
    wire [15:0] redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_q;
    wire [7:0] redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_wraddr_i = 8'b11111111;
    wire [8:0] redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_a;
    wire [8:0] redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_b;
    logic [8:0] redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_o;
    wire [8:0] redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_q;
    reg [15:0] redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_inputreg0_q;
    reg [15:0] redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_outputreg0_q;
    wire redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_reset0;
    wire [15:0] redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_ia;
    wire [7:0] redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_aa;
    wire [7:0] redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_ab;
    wire [15:0] redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_iq;
    wire [15:0] redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_q;
    wire [7:0] redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_wraddr_i = 8'b11111111;
    wire [7:0] redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_offset_q;
    wire [8:0] redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_a;
    wire [8:0] redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_b;
    logic [8:0] redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_o;
    wire [8:0] redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_q;
    reg [15:0] redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_inputreg0_q;
    reg [15:0] redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_outputreg0_q;
    wire redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_reset0;
    wire [15:0] redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_ia;
    wire [7:0] redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_aa;
    wire [7:0] redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_ab;
    wire [15:0] redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_iq;
    wire [15:0] redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_q;
    wire [7:0] redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_wraddr_i = 8'b11111111;
    wire [8:0] redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_a;
    wire [8:0] redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_b;
    logic [8:0] redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_o;
    wire [8:0] redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_q;
    reg [15:0] redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_inputreg0_q;
    reg [15:0] redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_outputreg0_q;
    wire redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_reset0;
    wire [15:0] redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_ia;
    wire [7:0] redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_aa;
    wire [7:0] redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_ab;
    wire [15:0] redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_iq;
    wire [15:0] redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_q;
    wire [7:0] redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_wraddr_i = 8'b11111111;
    wire [7:0] redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_offset_q;
    wire [8:0] redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_a;
    wire [8:0] redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_b;
    logic [8:0] redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_o;
    wire [8:0] redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_q;
    reg [15:0] redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_inputreg0_q;
    reg [15:0] redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_outputreg0_q;
    wire redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_reset0;
    wire [15:0] redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_ia;
    wire [7:0] redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_aa;
    wire [7:0] redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_ab;
    wire [15:0] redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_iq;
    wire [15:0] redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_q;
    wire [7:0] redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_wraddr_i = 8'b11111111;
    wire [8:0] redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_a;
    wire [8:0] redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_b;
    logic [8:0] redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_o;
    wire [8:0] redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_q;
    reg [15:0] redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_inputreg0_q;
    reg [15:0] redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_outputreg0_q;
    wire redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_reset0;
    wire [15:0] redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_ia;
    wire [7:0] redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_aa;
    wire [7:0] redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_ab;
    wire [15:0] redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_iq;
    wire [15:0] redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_q;
    wire [7:0] redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_wraddr_i = 8'b11111111;
    wire [7:0] redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_offset_q;
    wire [8:0] redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_a;
    wire [8:0] redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_b;
    logic [8:0] redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_o;
    wire [8:0] redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_q;
    reg [15:0] redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_inputreg0_q;
    reg [15:0] redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_outputreg0_q;
    wire redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_reset0;
    wire [15:0] redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_ia;
    wire [7:0] redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_aa;
    wire [7:0] redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_ab;
    wire [15:0] redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_iq;
    wire [15:0] redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_q;
    wire [7:0] redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_wraddr_i = 8'b11111111;
    wire [8:0] redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_a;
    wire [8:0] redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_b;
    logic [8:0] redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_o;
    wire [8:0] redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_q;
    reg [15:0] redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_inputreg0_q;
    reg [15:0] redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_outputreg0_q;
    wire redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_reset0;
    wire [15:0] redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_ia;
    wire [7:0] redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_aa;
    wire [7:0] redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_ab;
    wire [15:0] redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_iq;
    wire [15:0] redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_q;
    wire [7:0] redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_wraddr_i = 8'b11111111;
    wire [7:0] redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_offset_q;
    wire [8:0] redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_a;
    wire [8:0] redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_b;
    logic [8:0] redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_o;
    wire [8:0] redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_q;
    reg [15:0] redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_inputreg0_q;
    reg [15:0] redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_outputreg0_q;
    wire redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_reset0;
    wire [15:0] redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_ia;
    wire [7:0] redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_aa;
    wire [7:0] redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_ab;
    wire [15:0] redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_iq;
    wire [15:0] redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_q;
    wire [7:0] redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_wraddr_i = 8'b11111111;
    wire [8:0] redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_a;
    wire [8:0] redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_b;
    logic [8:0] redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_o;
    wire [8:0] redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_q;
    reg [15:0] redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_inputreg0_q;
    reg [15:0] redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_outputreg0_q;
    wire redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_reset0;
    wire [15:0] redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_ia;
    wire [7:0] redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_aa;
    wire [7:0] redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_ab;
    wire [15:0] redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_iq;
    wire [15:0] redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_q;
    wire [7:0] redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_wraddr_i = 8'b11111111;
    wire [7:0] redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_offset_q;
    wire [8:0] redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_a;
    wire [8:0] redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_b;
    logic [8:0] redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_o;
    wire [8:0] redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_q;
    reg [15:0] redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_inputreg0_q;
    reg [15:0] redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_outputreg0_q;
    wire redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_reset0;
    wire [15:0] redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_ia;
    wire [7:0] redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_aa;
    wire [7:0] redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_ab;
    wire [15:0] redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_iq;
    wire [15:0] redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_q;
    wire [7:0] redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_wraddr_i = 8'b11111111;
    wire [8:0] redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_a;
    wire [8:0] redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_b;
    logic [8:0] redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_o;
    wire [8:0] redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_q;
    reg [15:0] redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_inputreg0_q;
    reg [15:0] redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_outputreg0_q;
    wire redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_reset0;
    wire [15:0] redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_ia;
    wire [7:0] redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_aa;
    wire [7:0] redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_ab;
    wire [15:0] redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_iq;
    wire [15:0] redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_q;
    wire [7:0] redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_wraddr_i = 8'b11111111;
    wire [7:0] redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_offset_q;
    wire [8:0] redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_a;
    wire [8:0] redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_b;
    logic [8:0] redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_o;
    wire [8:0] redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_q;
    reg [15:0] redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_inputreg0_q;
    reg [15:0] redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_outputreg0_q;
    wire redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_reset0;
    wire [15:0] redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_ia;
    wire [7:0] redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_aa;
    wire [7:0] redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_ab;
    wire [15:0] redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_iq;
    wire [15:0] redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_q;
    wire [7:0] redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_wraddr_i = 8'b11111111;
    wire [8:0] redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_a;
    wire [8:0] redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_b;
    logic [8:0] redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_o;
    wire [8:0] redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_q;
    reg [15:0] redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_inputreg0_q;
    reg [15:0] redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_outputreg0_q;
    wire redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_reset0;
    wire [15:0] redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_ia;
    wire [7:0] redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_aa;
    wire [7:0] redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_ab;
    wire [15:0] redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_iq;
    wire [15:0] redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_q;
    wire [7:0] redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_wraddr_i = 8'b11111111;
    wire [7:0] redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_offset_q;
    wire [8:0] redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_a;
    wire [8:0] redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_b;
    logic [8:0] redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_o;
    wire [8:0] redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_q;
    reg [15:0] redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_inputreg0_q;
    reg [15:0] redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_outputreg0_q;
    wire redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_reset0;
    wire [15:0] redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_ia;
    wire [7:0] redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_aa;
    wire [7:0] redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_ab;
    wire [15:0] redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_iq;
    wire [15:0] redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_q;
    wire [7:0] redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_wraddr_i = 8'b11111111;
    wire [8:0] redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_a;
    wire [8:0] redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_b;
    logic [8:0] redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_o;
    wire [8:0] redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_q;
    reg [15:0] redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_inputreg0_q;
    reg [15:0] redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_outputreg0_q;
    wire redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_reset0;
    wire [15:0] redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_ia;
    wire [7:0] redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_aa;
    wire [7:0] redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_ab;
    wire [15:0] redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_iq;
    wire [15:0] redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_q;
    wire [7:0] redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_wraddr_i = 8'b11111111;
    wire [7:0] redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_offset_q;
    wire [8:0] redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_a;
    wire [8:0] redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_b;
    logic [8:0] redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_o;
    wire [8:0] redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_q;
    reg [15:0] redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_inputreg0_q;
    reg [15:0] redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_outputreg0_q;
    wire redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_reset0;
    wire [15:0] redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_ia;
    wire [7:0] redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_aa;
    wire [7:0] redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_ab;
    wire [15:0] redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_iq;
    wire [15:0] redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_q;
    wire [7:0] redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_wraddr_i = 8'b11111111;
    wire [8:0] redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_a;
    wire [8:0] redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_b;
    logic [8:0] redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_o;
    wire [8:0] redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_q;
    reg [15:0] redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_inputreg0_q;
    reg [15:0] redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_outputreg0_q;
    wire redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_reset0;
    wire [15:0] redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_ia;
    wire [7:0] redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_aa;
    wire [7:0] redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_ab;
    wire [15:0] redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_iq;
    wire [15:0] redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_q;
    wire [7:0] redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_wraddr_i = 8'b11111111;
    wire [7:0] redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_offset_q;
    wire [8:0] redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_a;
    wire [8:0] redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_b;
    logic [8:0] redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_o;
    wire [8:0] redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_q;
    reg [15:0] redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_inputreg0_q;
    reg [15:0] redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_outputreg0_q;
    wire redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_reset0;
    wire [15:0] redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_ia;
    wire [7:0] redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_aa;
    wire [7:0] redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_ab;
    wire [15:0] redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_iq;
    wire [15:0] redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_q;
    wire [7:0] redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_wraddr_i = 8'b11111111;
    wire [8:0] redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_a;
    wire [8:0] redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_b;
    logic [8:0] redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_o;
    wire [8:0] redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_q;
    reg [15:0] redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_inputreg0_q;
    reg [15:0] redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_outputreg0_q;
    wire redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_reset0;
    wire [15:0] redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_ia;
    wire [7:0] redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_aa;
    wire [7:0] redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_ab;
    wire [15:0] redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_iq;
    wire [15:0] redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_q;
    wire [7:0] redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_wraddr_i = 8'b11111111;
    wire [7:0] redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_offset_q;
    wire [8:0] redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_a;
    wire [8:0] redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_b;
    logic [8:0] redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_o;
    wire [8:0] redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_q;
    reg [15:0] redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_inputreg0_q;
    reg [15:0] redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_outputreg0_q;
    wire redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_reset0;
    wire [15:0] redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_ia;
    wire [7:0] redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_aa;
    wire [7:0] redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_ab;
    wire [15:0] redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_iq;
    wire [15:0] redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_q;
    wire [7:0] redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_wraddr_i = 8'b11111111;
    wire [8:0] redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_a;
    wire [8:0] redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_b;
    logic [8:0] redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_o;
    wire [8:0] redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_q;
    reg [15:0] redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_inputreg0_q;
    reg [15:0] redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_outputreg0_q;
    wire redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_reset0;
    wire [15:0] redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_ia;
    wire [7:0] redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_aa;
    wire [7:0] redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_ab;
    wire [15:0] redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_iq;
    wire [15:0] redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_q;
    wire [7:0] redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_wraddr_i = 8'b11111111;
    wire [7:0] redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_offset_q;
    wire [8:0] redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_a;
    wire [8:0] redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_b;
    logic [8:0] redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_o;
    wire [8:0] redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_q;
    reg [15:0] redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_inputreg0_q;
    reg [15:0] redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_outputreg0_q;
    wire redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_reset0;
    wire [15:0] redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_ia;
    wire [7:0] redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_aa;
    wire [7:0] redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_ab;
    wire [15:0] redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_iq;
    wire [15:0] redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_q;
    wire [7:0] redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_wraddr_i = 8'b11111111;
    wire [8:0] redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_a;
    wire [8:0] redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_b;
    logic [8:0] redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_o;
    wire [8:0] redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_q;
    reg [15:0] redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_inputreg0_q;
    reg [15:0] redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_outputreg0_q;
    wire redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_reset0;
    wire [15:0] redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_ia;
    wire [7:0] redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_aa;
    wire [7:0] redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_ab;
    wire [15:0] redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_iq;
    wire [15:0] redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_q;
    wire [7:0] redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_wraddr_i = 8'b11111111;
    wire [7:0] redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_offset_q;
    wire [8:0] redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_a;
    wire [8:0] redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_b;
    logic [8:0] redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_o;
    wire [8:0] redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_q;
    reg [15:0] redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_inputreg0_q;
    reg [15:0] redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_outputreg0_q;
    wire redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_reset0;
    wire [15:0] redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_ia;
    wire [7:0] redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_aa;
    wire [7:0] redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_ab;
    wire [15:0] redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_iq;
    wire [15:0] redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_q;
    wire [7:0] redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_wraddr_i = 8'b11111111;
    wire [8:0] redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_a;
    wire [8:0] redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_b;
    logic [8:0] redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_o;
    wire [8:0] redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_q;
    reg [15:0] redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_inputreg0_q;
    reg [15:0] redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_outputreg0_q;
    wire redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_reset0;
    wire [15:0] redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_ia;
    wire [7:0] redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_aa;
    wire [7:0] redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_ab;
    wire [15:0] redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_iq;
    wire [15:0] redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_q;
    wire [7:0] redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_wraddr_i = 8'b11111111;
    wire [7:0] redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_offset_q;
    wire [8:0] redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_a;
    wire [8:0] redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_b;
    logic [8:0] redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_o;
    wire [8:0] redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_q;
    reg [15:0] redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_inputreg0_q;
    reg [15:0] redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_outputreg0_q;
    wire redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_reset0;
    wire [15:0] redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_ia;
    wire [7:0] redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_aa;
    wire [7:0] redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_ab;
    wire [15:0] redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_iq;
    wire [15:0] redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_q;
    wire [7:0] redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_wraddr_i = 8'b11111111;
    wire [8:0] redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_a;
    wire [8:0] redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_b;
    logic [8:0] redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_o;
    wire [8:0] redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_q;
    reg [15:0] redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_inputreg0_q;
    reg [15:0] redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_outputreg0_q;
    wire redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_reset0;
    wire [15:0] redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_ia;
    wire [7:0] redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_aa;
    wire [7:0] redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_ab;
    wire [15:0] redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_iq;
    wire [15:0] redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_q;
    wire [7:0] redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_wraddr_i = 8'b11111111;
    wire [7:0] redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_offset_q;
    wire [8:0] redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_a;
    wire [8:0] redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_b;
    logic [8:0] redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_o;
    wire [8:0] redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_q;
    reg [15:0] redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_inputreg0_q;
    reg [15:0] redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_outputreg0_q;
    wire redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_reset0;
    wire [15:0] redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_ia;
    wire [7:0] redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_aa;
    wire [7:0] redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_ab;
    wire [15:0] redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_iq;
    wire [15:0] redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_q;
    wire [7:0] redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_wraddr_i = 8'b11111111;
    wire [8:0] redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_a;
    wire [8:0] redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_b;
    logic [8:0] redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_o;
    wire [8:0] redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_q;
    reg [15:0] redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_inputreg0_q;
    reg [15:0] redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_outputreg0_q;
    wire redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_reset0;
    wire [15:0] redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_ia;
    wire [7:0] redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_aa;
    wire [7:0] redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_ab;
    wire [15:0] redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_iq;
    wire [15:0] redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_q;
    wire [7:0] redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_wraddr_i = 8'b11111111;
    wire [7:0] redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_offset_q;
    wire [8:0] redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_a;
    wire [8:0] redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_b;
    logic [8:0] redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_o;
    wire [8:0] redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_q;
    reg [15:0] redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_inputreg0_q;
    reg [15:0] redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_outputreg0_q;
    wire redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_reset0;
    wire [15:0] redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_ia;
    wire [7:0] redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_aa;
    wire [7:0] redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_ab;
    wire [15:0] redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_iq;
    wire [15:0] redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_q;
    wire [7:0] redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_wraddr_i = 8'b11111111;
    wire [8:0] redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_a;
    wire [8:0] redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_b;
    logic [8:0] redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_o;
    wire [8:0] redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_q;
    reg [15:0] redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_inputreg0_q;
    reg [15:0] redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_outputreg0_q;
    wire redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_reset0;
    wire [15:0] redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_ia;
    wire [7:0] redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_aa;
    wire [7:0] redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_ab;
    wire [15:0] redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_iq;
    wire [15:0] redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_q;
    wire [7:0] redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_wraddr_i = 8'b11111111;
    wire [7:0] redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_offset_q;
    wire [8:0] redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_a;
    wire [8:0] redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_b;
    logic [8:0] redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_o;
    wire [8:0] redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_q;
    reg [15:0] redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_inputreg0_q;
    reg [15:0] redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_outputreg0_q;
    wire redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_reset0;
    wire [15:0] redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_ia;
    wire [7:0] redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_aa;
    wire [7:0] redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_ab;
    wire [15:0] redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_iq;
    wire [15:0] redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_q;
    wire [7:0] redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_wraddr_i = 8'b11111111;
    wire [8:0] redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_a;
    wire [8:0] redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_b;
    logic [8:0] redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_o;
    wire [8:0] redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_q;
    reg [15:0] redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_inputreg0_q;
    reg [15:0] redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_outputreg0_q;
    wire redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_reset0;
    wire [15:0] redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_ia;
    wire [7:0] redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_aa;
    wire [7:0] redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_ab;
    wire [15:0] redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_iq;
    wire [15:0] redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_q;
    wire [7:0] redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_wraddr_i = 8'b11111111;
    wire [7:0] redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_offset_q;
    wire [8:0] redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_a;
    wire [8:0] redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_b;
    logic [8:0] redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_o;
    wire [8:0] redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_q;
    reg [15:0] redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_inputreg0_q;
    reg [15:0] redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_outputreg0_q;
    wire redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_reset0;
    wire [15:0] redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_ia;
    wire [7:0] redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_aa;
    wire [7:0] redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_ab;
    wire [15:0] redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_iq;
    wire [15:0] redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_q;
    wire [7:0] redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_wraddr_i = 8'b11111111;
    wire [8:0] redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_a;
    wire [8:0] redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_b;
    logic [8:0] redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_o;
    wire [8:0] redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_q;
    reg [15:0] redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_inputreg0_q;
    reg [15:0] redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_outputreg0_q;
    wire redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_reset0;
    wire [15:0] redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_ia;
    wire [7:0] redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_aa;
    wire [7:0] redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_ab;
    wire [15:0] redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_iq;
    wire [15:0] redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_q;
    wire [7:0] redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_wraddr_i = 8'b11111111;
    wire [7:0] redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_offset_q;
    wire [8:0] redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_a;
    wire [8:0] redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_b;
    logic [8:0] redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_o;
    wire [8:0] redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_q;
    reg [15:0] redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_inputreg0_q;
    reg [15:0] redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_outputreg0_q;
    wire redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_reset0;
    wire [15:0] redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_ia;
    wire [7:0] redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_aa;
    wire [7:0] redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_ab;
    wire [15:0] redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_iq;
    wire [15:0] redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_q;
    wire [7:0] redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_wraddr_i = 8'b11111111;
    wire [8:0] redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_a;
    wire [8:0] redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_b;
    logic [8:0] redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_o;
    wire [8:0] redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_q;
    reg [15:0] redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_inputreg0_q;
    reg [15:0] redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_outputreg0_q;
    wire redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_reset0;
    wire [15:0] redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_ia;
    wire [7:0] redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_aa;
    wire [7:0] redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_ab;
    wire [15:0] redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_iq;
    wire [15:0] redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_q;
    wire [7:0] redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_wraddr_i = 8'b11111111;
    wire [7:0] redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_offset_q;
    wire [8:0] redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_a;
    wire [8:0] redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_b;
    logic [8:0] redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_o;
    wire [8:0] redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_q;
    reg [15:0] redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_inputreg0_q;
    reg [15:0] redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_outputreg0_q;
    wire redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_reset0;
    wire [15:0] redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_ia;
    wire [7:0] redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_aa;
    wire [7:0] redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_ab;
    wire [15:0] redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_iq;
    wire [15:0] redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_q;
    wire [7:0] redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_wraddr_i = 8'b11111111;
    wire [8:0] redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_a;
    wire [8:0] redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_b;
    logic [8:0] redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_o;
    wire [8:0] redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_q;
    reg [15:0] redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_inputreg0_q;
    reg [15:0] redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_outputreg0_q;
    wire redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_reset0;
    wire [15:0] redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_ia;
    wire [7:0] redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_aa;
    wire [7:0] redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_ab;
    wire [15:0] redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_iq;
    wire [15:0] redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_q;
    wire [7:0] redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_wraddr_i = 8'b11111111;
    wire [7:0] redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_offset_q;
    wire [8:0] redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_a;
    wire [8:0] redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_b;
    logic [8:0] redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_o;
    wire [8:0] redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_q;
    reg [15:0] redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_inputreg0_q;
    reg [15:0] redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_outputreg0_q;
    wire redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_reset0;
    wire [15:0] redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_ia;
    wire [7:0] redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_aa;
    wire [7:0] redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_ab;
    wire [15:0] redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_iq;
    wire [15:0] redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_q;
    wire [7:0] redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_wraddr_i = 8'b11111111;
    wire [8:0] redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_a;
    wire [8:0] redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_b;
    logic [8:0] redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_o;
    wire [8:0] redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_q;
    reg [15:0] redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_inputreg0_q;
    reg [15:0] redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_outputreg0_q;
    wire redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_reset0;
    wire [15:0] redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_ia;
    wire [7:0] redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_aa;
    wire [7:0] redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_ab;
    wire [15:0] redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_iq;
    wire [15:0] redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_q;
    wire [7:0] redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_wraddr_i = 8'b11111111;
    wire [7:0] redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_offset_q;
    wire [8:0] redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_a;
    wire [8:0] redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_b;
    logic [8:0] redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_o;
    wire [8:0] redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_q;
    reg [15:0] redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_inputreg0_q;
    reg [15:0] redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_outputreg0_q;
    wire redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_reset0;
    wire [15:0] redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_ia;
    wire [7:0] redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_aa;
    wire [7:0] redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_ab;
    wire [15:0] redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_iq;
    wire [15:0] redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_q;
    wire [7:0] redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_wraddr_i = 8'b11111111;
    wire [8:0] redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_a;
    wire [8:0] redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_b;
    logic [8:0] redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_o;
    wire [8:0] redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_q;
    reg [15:0] redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_inputreg0_q;
    reg [15:0] redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_outputreg0_q;
    wire redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_reset0;
    wire [15:0] redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_ia;
    wire [7:0] redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_aa;
    wire [7:0] redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_ab;
    wire [15:0] redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_iq;
    wire [15:0] redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_q;
    wire [7:0] redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_wraddr_i = 8'b11111111;
    wire [7:0] redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_offset_q;
    wire [8:0] redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_a;
    wire [8:0] redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_b;
    logic [8:0] redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_o;
    wire [8:0] redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_q;
    reg [15:0] redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_inputreg0_q;
    reg [15:0] redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_outputreg0_q;
    wire redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_reset0;
    wire [15:0] redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_ia;
    wire [7:0] redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_aa;
    wire [7:0] redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_ab;
    wire [15:0] redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_iq;
    wire [15:0] redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_q;
    wire [7:0] redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_wraddr_i = 8'b11111111;
    wire [8:0] redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_a;
    wire [8:0] redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_b;
    logic [8:0] redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_o;
    wire [8:0] redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_q;
    reg [15:0] redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_inputreg0_q;
    reg [15:0] redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_outputreg0_q;
    wire redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_reset0;
    wire [15:0] redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_ia;
    wire [7:0] redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_aa;
    wire [7:0] redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_ab;
    wire [15:0] redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_iq;
    wire [15:0] redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_q;
    wire [7:0] redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_wraddr_i = 8'b11111111;
    wire [7:0] redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_offset_q;
    wire [8:0] redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_a;
    wire [8:0] redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_b;
    logic [8:0] redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_o;
    wire [8:0] redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_q;
    reg [15:0] redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_inputreg0_q;
    reg [15:0] redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_outputreg0_q;
    wire redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_reset0;
    wire [15:0] redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_ia;
    wire [7:0] redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_aa;
    wire [7:0] redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_ab;
    wire [15:0] redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_iq;
    wire [15:0] redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_q;
    wire [7:0] redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_wraddr_i = 8'b11111111;
    wire [8:0] redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_a;
    wire [8:0] redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_b;
    logic [8:0] redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_o;
    wire [8:0] redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_q;
    reg [15:0] redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_inputreg0_q;
    reg [15:0] redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_outputreg0_q;
    wire redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_reset0;
    wire [15:0] redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_ia;
    wire [7:0] redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_aa;
    wire [7:0] redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_ab;
    wire [15:0] redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_iq;
    wire [15:0] redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_q;
    wire [7:0] redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_wraddr_i = 8'b11111111;
    wire [7:0] redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_offset_q;
    wire [8:0] redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_a;
    wire [8:0] redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_b;
    logic [8:0] redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_o;
    wire [8:0] redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_q;
    reg [15:0] redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_inputreg0_q;
    reg [15:0] redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_outputreg0_q;
    wire redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_reset0;
    wire [15:0] redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_ia;
    wire [7:0] redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_aa;
    wire [7:0] redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_ab;
    wire [15:0] redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_iq;
    wire [15:0] redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_q;
    wire [7:0] redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_wraddr_i = 8'b11111111;
    wire [8:0] redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_a;
    wire [8:0] redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_b;
    logic [8:0] redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_o;
    wire [8:0] redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_q;
    reg [15:0] redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_inputreg0_q;
    reg [15:0] redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_outputreg0_q;
    wire redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_reset0;
    wire [15:0] redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_ia;
    wire [7:0] redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_aa;
    wire [7:0] redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_ab;
    wire [15:0] redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_iq;
    wire [15:0] redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_q;
    wire [7:0] redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_wraddr_i = 8'b11111111;
    wire [7:0] redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_offset_q;
    wire [8:0] redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_a;
    wire [8:0] redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_b;
    logic [8:0] redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_o;
    wire [8:0] redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_q;
    reg [15:0] redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_inputreg0_q;
    reg [15:0] redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_outputreg0_q;
    wire redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_reset0;
    wire [15:0] redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_ia;
    wire [7:0] redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_aa;
    wire [7:0] redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_ab;
    wire [15:0] redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_iq;
    wire [15:0] redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_q;
    wire [7:0] redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_wraddr_i = 8'b11111111;
    wire [8:0] redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_a;
    wire [8:0] redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_b;
    logic [8:0] redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_o;
    wire [8:0] redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_q;
    reg [15:0] redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_inputreg0_q;
    reg [15:0] redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_outputreg0_q;
    wire redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_reset0;
    wire [15:0] redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_ia;
    wire [7:0] redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_aa;
    wire [7:0] redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_ab;
    wire [15:0] redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_iq;
    wire [15:0] redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_q;
    wire [7:0] redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_wraddr_i = 8'b11111111;
    wire [7:0] redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_offset_q;
    wire [8:0] redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_a;
    wire [8:0] redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_b;
    logic [8:0] redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_o;
    wire [8:0] redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_q;
    reg [15:0] redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_inputreg0_q;
    reg [15:0] redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_outputreg0_q;
    wire redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_reset0;
    wire [15:0] redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_ia;
    wire [7:0] redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_aa;
    wire [7:0] redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_ab;
    wire [15:0] redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_iq;
    wire [15:0] redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_q;
    wire [7:0] redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_wraddr_i = 8'b11111111;
    wire [8:0] redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_a;
    wire [8:0] redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_b;
    logic [8:0] redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_o;
    wire [8:0] redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_q;
    reg [15:0] redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_inputreg0_q;
    reg [15:0] redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_outputreg0_q;
    wire redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_reset0;
    wire [15:0] redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_ia;
    wire [7:0] redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_aa;
    wire [7:0] redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_ab;
    wire [15:0] redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_iq;
    wire [15:0] redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_q;
    wire [7:0] redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_wraddr_i = 8'b11111111;
    wire [7:0] redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_offset_q;
    wire [8:0] redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_a;
    wire [8:0] redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_b;
    logic [8:0] redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_o;
    wire [8:0] redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_q;
    reg [15:0] redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_inputreg0_q;
    reg [15:0] redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_outputreg0_q;
    wire redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_reset0;
    wire [15:0] redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_ia;
    wire [7:0] redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_aa;
    wire [7:0] redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_ab;
    wire [15:0] redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_iq;
    wire [15:0] redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_q;
    wire [7:0] redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_wraddr_i = 8'b11111111;
    wire [8:0] redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_a;
    wire [8:0] redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_b;
    logic [8:0] redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_o;
    wire [8:0] redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_q;
    reg [15:0] redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_inputreg0_q;
    reg [15:0] redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_outputreg0_q;
    wire redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_reset0;
    wire [15:0] redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_ia;
    wire [7:0] redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_aa;
    wire [7:0] redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_ab;
    wire [15:0] redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_iq;
    wire [15:0] redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_q;
    wire [7:0] redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_wraddr_i = 8'b11111111;
    wire [7:0] redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_offset_q;
    wire [8:0] redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_a;
    wire [8:0] redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_b;
    logic [8:0] redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_o;
    wire [8:0] redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_q;
    reg [15:0] redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_inputreg0_q;
    reg [15:0] redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_outputreg0_q;
    wire redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_reset0;
    wire [15:0] redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_ia;
    wire [7:0] redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_aa;
    wire [7:0] redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_ab;
    wire [15:0] redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_iq;
    wire [15:0] redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_q;
    wire [7:0] redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_wraddr_i = 8'b11111111;
    wire [8:0] redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_a;
    wire [8:0] redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_b;
    logic [8:0] redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_o;
    wire [8:0] redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_q;
    reg [15:0] redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_inputreg0_q;
    reg [15:0] redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_outputreg0_q;
    wire redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_reset0;
    wire [15:0] redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_ia;
    wire [7:0] redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_aa;
    wire [7:0] redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_ab;
    wire [15:0] redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_iq;
    wire [15:0] redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_q;
    wire [7:0] redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_wraddr_i = 8'b11111111;
    wire [7:0] redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_offset_q;
    wire [8:0] redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_a;
    wire [8:0] redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_b;
    logic [8:0] redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_o;
    wire [8:0] redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_q;
    reg [15:0] redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_inputreg0_q;
    reg [15:0] redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_outputreg0_q;
    wire redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_reset0;
    wire [15:0] redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_ia;
    wire [7:0] redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_aa;
    wire [7:0] redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_ab;
    wire [15:0] redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_iq;
    wire [15:0] redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_q;
    wire [7:0] redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_wraddr_i = 8'b11111111;
    wire [8:0] redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_a;
    wire [8:0] redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_b;
    logic [8:0] redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_o;
    wire [8:0] redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_q;
    reg [15:0] redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_inputreg0_q;
    reg [15:0] redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_outputreg0_q;
    reg [15:0] redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_inputreg0_q;
    reg [15:0] redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_outputreg0_q;
    reg [15:0] redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_inputreg0_q;
    reg [15:0] redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_outputreg0_q;
    wire redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_reset0;
    wire [15:0] redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_ia;
    wire [1:0] redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_aa;
    wire [1:0] redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_ab;
    wire [15:0] redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_iq;
    wire [15:0] redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_q;
    wire [1:0] redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_wraddr_i = 2'b11;
    wire [2:0] redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_a;
    wire [2:0] redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_b;
    logic [2:0] redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_o;
    wire [2:0] redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_q;
    reg [15:0] redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_inputreg0_q;
    reg [15:0] redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_outputreg0_q;
    wire redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_reset0;
    wire [15:0] redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_ia;
    wire [1:0] redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_aa;
    wire [1:0] redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_ab;
    wire [15:0] redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_iq;
    wire [15:0] redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_q;
    wire [1:0] redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_wraddr_i = 2'b11;
    wire [2:0] redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_a;
    wire [2:0] redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_b;
    logic [2:0] redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_o;
    wire [2:0] redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_q;
    reg [15:0] redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_inputreg0_q;
    reg [15:0] redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_outputreg0_q;
    wire redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_reset0;
    wire [15:0] redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_ia;
    wire [2:0] redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_aa;
    wire [2:0] redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_ab;
    wire [15:0] redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_iq;
    wire [15:0] redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_q;
    wire [2:0] redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_wraddr_i = 3'b111;
    wire [3:0] redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_a;
    wire [3:0] redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_b;
    logic [3:0] redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_o;
    wire [3:0] redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_q;
    reg [15:0] redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_inputreg0_q;
    reg [15:0] redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_outputreg0_q;
    wire redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_reset0;
    wire [15:0] redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_ia;
    wire [2:0] redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_aa;
    wire [2:0] redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_ab;
    wire [15:0] redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_iq;
    wire [15:0] redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_q;
    wire [2:0] redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_wraddr_i = 3'b111;
    wire [3:0] redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_a;
    wire [3:0] redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_b;
    logic [3:0] redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_o;
    wire [3:0] redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_q;
    reg [15:0] redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_inputreg0_q;
    reg [15:0] redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_outputreg0_q;
    wire redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_reset0;
    wire [15:0] redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_ia;
    wire [2:0] redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_aa;
    wire [2:0] redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_ab;
    wire [15:0] redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_iq;
    wire [15:0] redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_q;
    wire [2:0] redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_wraddr_i = 3'b111;
    wire [3:0] redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_a;
    wire [3:0] redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_b;
    logic [3:0] redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_o;
    wire [3:0] redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_q;
    reg [15:0] redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_inputreg0_q;
    reg [15:0] redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_outputreg0_q;
    wire redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_reset0;
    wire [15:0] redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_ia;
    wire [2:0] redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_aa;
    wire [2:0] redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_ab;
    wire [15:0] redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_iq;
    wire [15:0] redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_q;
    wire [2:0] redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_wraddr_i = 3'b111;
    wire [3:0] redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_a;
    wire [3:0] redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_b;
    logic [3:0] redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_o;
    wire [3:0] redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_q;
    reg [15:0] redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_inputreg0_q;
    reg [15:0] redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_outputreg0_q;
    wire redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_reset0;
    wire [15:0] redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_ia;
    wire [3:0] redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_aa;
    wire [3:0] redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_ab;
    wire [15:0] redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_iq;
    wire [15:0] redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_q;
    wire [3:0] redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_wraddr_i = 4'b1111;
    wire [4:0] redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_a;
    wire [4:0] redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_b;
    logic [4:0] redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_o;
    wire [4:0] redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_q;
    reg [15:0] redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_inputreg0_q;
    reg [15:0] redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_outputreg0_q;
    wire redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_reset0;
    wire [15:0] redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_ia;
    wire [3:0] redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_aa;
    wire [3:0] redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_ab;
    wire [15:0] redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_iq;
    wire [15:0] redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_q;
    wire [3:0] redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_wraddr_i = 4'b1111;
    wire [4:0] redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_a;
    wire [4:0] redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_b;
    logic [4:0] redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_o;
    wire [4:0] redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_q;
    reg [15:0] redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_inputreg0_q;
    reg [15:0] redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_outputreg0_q;
    wire redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_reset0;
    wire [15:0] redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_ia;
    wire [3:0] redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_aa;
    wire [3:0] redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_ab;
    wire [15:0] redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_iq;
    wire [15:0] redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_q;
    wire [3:0] redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_wraddr_i = 4'b1111;
    wire [4:0] redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_a;
    wire [4:0] redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_b;
    logic [4:0] redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_o;
    wire [4:0] redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_q;
    reg [15:0] redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_inputreg0_q;
    reg [15:0] redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_outputreg0_q;
    wire redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_reset0;
    wire [15:0] redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_ia;
    wire [3:0] redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_aa;
    wire [3:0] redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_ab;
    wire [15:0] redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_iq;
    wire [15:0] redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_q;
    wire [3:0] redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_wraddr_i = 4'b1111;
    wire [4:0] redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_a;
    wire [4:0] redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_b;
    logic [4:0] redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_o;
    wire [4:0] redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_q;
    reg [15:0] redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_inputreg0_q;
    reg [15:0] redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_outputreg0_q;
    wire redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_reset0;
    wire [15:0] redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_ia;
    wire [3:0] redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_aa;
    wire [3:0] redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_ab;
    wire [15:0] redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_iq;
    wire [15:0] redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_q;
    wire [3:0] redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_wraddr_i = 4'b1111;
    wire [4:0] redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_a;
    wire [4:0] redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_b;
    logic [4:0] redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_o;
    wire [4:0] redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_q;
    reg [15:0] redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_inputreg0_q;
    reg [15:0] redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_outputreg0_q;
    wire redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_reset0;
    wire [15:0] redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_ia;
    wire [3:0] redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_aa;
    wire [3:0] redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_ab;
    wire [15:0] redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_iq;
    wire [15:0] redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_q;
    wire [3:0] redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_wraddr_i = 4'b1111;
    wire [4:0] redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_a;
    wire [4:0] redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_b;
    logic [4:0] redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_o;
    wire [4:0] redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_q;
    reg [15:0] redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_inputreg0_q;
    reg [15:0] redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_outputreg0_q;
    wire redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_reset0;
    wire [15:0] redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_ia;
    wire [3:0] redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_aa;
    wire [3:0] redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_ab;
    wire [15:0] redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_iq;
    wire [15:0] redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_q;
    wire [3:0] redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_wraddr_i = 4'b1111;
    wire [4:0] redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_a;
    wire [4:0] redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_b;
    logic [4:0] redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_o;
    wire [4:0] redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_q;
    reg [15:0] redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_inputreg0_q;
    reg [15:0] redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_outputreg0_q;
    wire redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_reset0;
    wire [15:0] redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_ia;
    wire [3:0] redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_aa;
    wire [3:0] redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_ab;
    wire [15:0] redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_iq;
    wire [15:0] redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_q;
    wire [3:0] redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_wraddr_i = 4'b1111;
    wire [4:0] redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_a;
    wire [4:0] redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_b;
    logic [4:0] redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_o;
    wire [4:0] redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_q;
    reg [15:0] redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_inputreg0_q;
    reg [15:0] redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_outputreg0_q;
    wire redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_reset0;
    wire [15:0] redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_ia;
    wire [4:0] redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_aa;
    wire [4:0] redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_ab;
    wire [15:0] redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_iq;
    wire [15:0] redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_q;
    wire [4:0] redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_wraddr_i = 5'b11111;
    wire [5:0] redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_a;
    wire [5:0] redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_b;
    logic [5:0] redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_o;
    wire [5:0] redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_q;
    reg [15:0] redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_inputreg0_q;
    reg [15:0] redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_outputreg0_q;
    wire redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_reset0;
    wire [15:0] redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_ia;
    wire [4:0] redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_aa;
    wire [4:0] redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_ab;
    wire [15:0] redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_iq;
    wire [15:0] redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_q;
    wire [4:0] redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_wraddr_i = 5'b11111;
    wire [5:0] redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_a;
    wire [5:0] redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_b;
    logic [5:0] redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_o;
    wire [5:0] redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_q;
    reg [15:0] redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_inputreg0_q;
    reg [15:0] redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_outputreg0_q;
    wire redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_reset0;
    wire [15:0] redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_ia;
    wire [4:0] redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_aa;
    wire [4:0] redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_ab;
    wire [15:0] redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_iq;
    wire [15:0] redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_q;
    wire [4:0] redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_wraddr_i = 5'b11111;
    wire [5:0] redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_a;
    wire [5:0] redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_b;
    logic [5:0] redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_o;
    wire [5:0] redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_q;
    reg [15:0] redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_inputreg0_q;
    reg [15:0] redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_outputreg0_q;
    wire redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_reset0;
    wire [15:0] redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_ia;
    wire [4:0] redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_aa;
    wire [4:0] redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_ab;
    wire [15:0] redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_iq;
    wire [15:0] redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_q;
    wire [4:0] redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_wraddr_i = 5'b11111;
    wire [5:0] redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_a;
    wire [5:0] redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_b;
    logic [5:0] redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_o;
    wire [5:0] redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_q;
    reg [15:0] redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_inputreg0_q;
    reg [15:0] redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_outputreg0_q;
    wire redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_reset0;
    wire [15:0] redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_ia;
    wire [4:0] redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_aa;
    wire [4:0] redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_ab;
    wire [15:0] redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_iq;
    wire [15:0] redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_q;
    wire [4:0] redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_wraddr_i = 5'b11111;
    wire [5:0] redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_a;
    wire [5:0] redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_b;
    logic [5:0] redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_o;
    wire [5:0] redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_q;
    reg [15:0] redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_inputreg0_q;
    reg [15:0] redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_outputreg0_q;
    wire redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_reset0;
    wire [15:0] redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_ia;
    wire [4:0] redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_aa;
    wire [4:0] redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_ab;
    wire [15:0] redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_iq;
    wire [15:0] redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_q;
    wire [4:0] redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_wraddr_i = 5'b11111;
    wire [5:0] redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_a;
    wire [5:0] redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_b;
    logic [5:0] redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_o;
    wire [5:0] redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_q;
    reg [15:0] redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_inputreg0_q;
    reg [15:0] redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_outputreg0_q;
    wire redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_reset0;
    wire [15:0] redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_ia;
    wire [4:0] redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_aa;
    wire [4:0] redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_ab;
    wire [15:0] redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_iq;
    wire [15:0] redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_q;
    wire [4:0] redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_wraddr_i = 5'b11111;
    wire [5:0] redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_a;
    wire [5:0] redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_b;
    logic [5:0] redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_o;
    wire [5:0] redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_q;
    reg [15:0] redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_inputreg0_q;
    reg [15:0] redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_outputreg0_q;
    wire redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_reset0;
    wire [15:0] redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_ia;
    wire [4:0] redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_aa;
    wire [4:0] redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_ab;
    wire [15:0] redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_iq;
    wire [15:0] redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_q;
    wire [4:0] redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_wraddr_i = 5'b11111;
    wire [5:0] redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_a;
    wire [5:0] redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_b;
    logic [5:0] redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_o;
    wire [5:0] redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_q;
    reg [15:0] redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_inputreg0_q;
    reg [15:0] redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_outputreg0_q;
    wire redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_reset0;
    wire [15:0] redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_ia;
    wire [4:0] redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_aa;
    wire [4:0] redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_ab;
    wire [15:0] redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_iq;
    wire [15:0] redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_q;
    wire [4:0] redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_wraddr_i = 5'b11111;
    wire [5:0] redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_a;
    wire [5:0] redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_b;
    logic [5:0] redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_o;
    wire [5:0] redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_q;
    reg [15:0] redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_inputreg0_q;
    reg [15:0] redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_outputreg0_q;
    wire redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_reset0;
    wire [15:0] redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_ia;
    wire [4:0] redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_aa;
    wire [4:0] redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_ab;
    wire [15:0] redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_iq;
    wire [15:0] redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_q;
    wire [4:0] redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_wraddr_i = 5'b11111;
    wire [5:0] redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_a;
    wire [5:0] redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_b;
    logic [5:0] redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_o;
    wire [5:0] redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_q;
    reg [15:0] redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_inputreg0_q;
    reg [15:0] redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_outputreg0_q;
    wire redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_reset0;
    wire [15:0] redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_ia;
    wire [4:0] redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_aa;
    wire [4:0] redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_ab;
    wire [15:0] redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_iq;
    wire [15:0] redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_q;
    wire [4:0] redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_wraddr_i = 5'b11111;
    wire [5:0] redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_a;
    wire [5:0] redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_b;
    logic [5:0] redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_o;
    wire [5:0] redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_q;
    reg [15:0] redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_inputreg0_q;
    reg [15:0] redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_outputreg0_q;
    wire redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_reset0;
    wire [15:0] redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_ia;
    wire [4:0] redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_aa;
    wire [4:0] redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_ab;
    wire [15:0] redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_iq;
    wire [15:0] redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_q;
    wire [4:0] redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_wraddr_i = 5'b11111;
    wire [5:0] redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_a;
    wire [5:0] redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_b;
    logic [5:0] redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_o;
    wire [5:0] redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_q;
    reg [15:0] redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_inputreg0_q;
    reg [15:0] redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_outputreg0_q;
    wire redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_reset0;
    wire [15:0] redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_ia;
    wire [4:0] redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_aa;
    wire [4:0] redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_ab;
    wire [15:0] redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_iq;
    wire [15:0] redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_q;
    wire [4:0] redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_wraddr_i = 5'b11111;
    wire [5:0] redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_a;
    wire [5:0] redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_b;
    logic [5:0] redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_o;
    wire [5:0] redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_q;
    reg [15:0] redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_inputreg0_q;
    reg [15:0] redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_outputreg0_q;
    wire redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_reset0;
    wire [15:0] redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_ia;
    wire [4:0] redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_aa;
    wire [4:0] redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_ab;
    wire [15:0] redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_iq;
    wire [15:0] redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_q;
    wire [4:0] redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_wraddr_i = 5'b11111;
    wire [5:0] redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_a;
    wire [5:0] redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_b;
    logic [5:0] redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_o;
    wire [5:0] redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_q;
    reg [15:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_inputreg0_q;
    reg [15:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_inputreg0_q;
    reg [15:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_inputreg0_q;
    reg [15:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_outputreg0_q;
    wire redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_reset0;
    wire [15:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_ia;
    wire [1:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_aa;
    wire [1:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_ab;
    wire [15:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_iq;
    wire [15:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_q;
    wire [1:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_wraddr_i = 2'b11;
    wire [2:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_a;
    wire [2:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_b;
    logic [2:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_o;
    wire [2:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_q;
    reg [15:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_inputreg0_q;
    reg [15:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_outputreg0_q;
    wire redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_reset0;
    wire [15:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_ia;
    wire [1:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_aa;
    wire [1:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_ab;
    wire [15:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_iq;
    wire [15:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_q;
    wire [1:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_wraddr_i = 2'b11;
    wire [2:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_a;
    wire [2:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_b;
    logic [2:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_o;
    wire [2:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_q;
    reg [15:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_inputreg0_q;
    reg [15:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_outputreg0_q;
    wire redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_reset0;
    wire [15:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_ia;
    wire [2:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_aa;
    wire [2:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_ab;
    wire [15:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_iq;
    wire [15:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_q;
    wire [2:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_wraddr_i = 3'b111;
    wire [3:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_a;
    wire [3:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_b;
    logic [3:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_o;
    wire [3:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_q;
    reg [15:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_inputreg0_q;
    reg [15:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_outputreg0_q;
    wire redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_reset0;
    wire [15:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_ia;
    wire [2:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_aa;
    wire [2:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_ab;
    wire [15:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_iq;
    wire [15:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_q;
    wire [2:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_wraddr_i = 3'b111;
    wire [3:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_a;
    wire [3:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_b;
    logic [3:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_o;
    wire [3:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_q;
    reg [15:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_inputreg0_q;
    reg [15:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_outputreg0_q;
    wire redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_reset0;
    wire [15:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_ia;
    wire [2:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_aa;
    wire [2:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_ab;
    wire [15:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_iq;
    wire [15:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_q;
    wire [2:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_wraddr_i = 3'b111;
    wire [3:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_a;
    wire [3:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_b;
    logic [3:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_o;
    wire [3:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_q;
    reg [15:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_inputreg0_q;
    reg [15:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_outputreg0_q;
    wire redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_reset0;
    wire [15:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_ia;
    wire [2:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_aa;
    wire [2:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_ab;
    wire [15:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_iq;
    wire [15:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_q;
    wire [2:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_wraddr_i = 3'b111;
    wire [3:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_a;
    wire [3:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_b;
    logic [3:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_o;
    wire [3:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_q;
    reg [15:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_inputreg0_q;
    reg [15:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_outputreg0_q;
    wire redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_reset0;
    wire [15:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_ia;
    wire [3:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_aa;
    wire [3:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_ab;
    wire [15:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_iq;
    wire [15:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_q;
    wire [3:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_wraddr_i = 4'b1111;
    wire [4:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_a;
    wire [4:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_b;
    logic [4:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_o;
    wire [4:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_q;
    reg [15:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_inputreg0_q;
    reg [15:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_outputreg0_q;
    wire redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_reset0;
    wire [15:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_ia;
    wire [3:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_aa;
    wire [3:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_ab;
    wire [15:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_iq;
    wire [15:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_q;
    wire [3:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_wraddr_i = 4'b1111;
    wire [4:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_a;
    wire [4:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_b;
    logic [4:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_o;
    wire [4:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_q;
    reg [15:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_inputreg0_q;
    reg [15:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_outputreg0_q;
    wire redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_reset0;
    wire [15:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_ia;
    wire [3:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_aa;
    wire [3:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_ab;
    wire [15:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_iq;
    wire [15:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_q;
    wire [3:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_wraddr_i = 4'b1111;
    wire [4:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_a;
    wire [4:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_b;
    logic [4:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_o;
    wire [4:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_q;
    reg [15:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_inputreg0_q;
    reg [15:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_outputreg0_q;
    wire redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_reset0;
    wire [15:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_ia;
    wire [3:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_aa;
    wire [3:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_ab;
    wire [15:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_iq;
    wire [15:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_q;
    wire [3:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_wraddr_i = 4'b1111;
    wire [4:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_a;
    wire [4:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_b;
    logic [4:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_o;
    wire [4:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_q;
    reg [15:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_inputreg0_q;
    reg [15:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_outputreg0_q;
    wire redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_reset0;
    wire [15:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_ia;
    wire [3:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_aa;
    wire [3:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_ab;
    wire [15:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_iq;
    wire [15:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_q;
    wire [3:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_wraddr_i = 4'b1111;
    wire [4:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_a;
    wire [4:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_b;
    logic [4:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_o;
    wire [4:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_q;
    reg [15:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_inputreg0_q;
    reg [15:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_outputreg0_q;
    wire redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_reset0;
    wire [15:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_ia;
    wire [3:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_aa;
    wire [3:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_ab;
    wire [15:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_iq;
    wire [15:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_q;
    wire [3:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_wraddr_i = 4'b1111;
    wire [4:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_a;
    wire [4:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_b;
    logic [4:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_o;
    wire [4:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_q;
    reg [15:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_inputreg0_q;
    reg [15:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_outputreg0_q;
    wire redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_reset0;
    wire [15:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_ia;
    wire [3:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_aa;
    wire [3:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_ab;
    wire [15:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_iq;
    wire [15:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_q;
    wire [3:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_wraddr_i = 4'b1111;
    wire [4:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_a;
    wire [4:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_b;
    logic [4:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_o;
    wire [4:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_q;
    reg [15:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_inputreg0_q;
    reg [15:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_outputreg0_q;
    wire redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_reset0;
    wire [15:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_ia;
    wire [3:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_aa;
    wire [3:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_ab;
    wire [15:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_iq;
    wire [15:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_q;
    wire [3:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_wraddr_i = 4'b1111;
    wire [4:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_a;
    wire [4:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_b;
    logic [4:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_o;
    wire [4:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_q;
    reg [15:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_inputreg0_q;
    reg [15:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_outputreg0_q;
    wire redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_reset0;
    wire [15:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_ia;
    wire [4:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_aa;
    wire [4:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_ab;
    wire [15:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_iq;
    wire [15:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_q;
    wire [4:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_wraddr_i = 5'b11111;
    wire [5:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_a;
    wire [5:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_b;
    logic [5:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_o;
    wire [5:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_q;
    reg [15:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_inputreg0_q;
    reg [15:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_outputreg0_q;
    wire redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_reset0;
    wire [15:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_ia;
    wire [4:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_aa;
    wire [4:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_ab;
    wire [15:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_iq;
    wire [15:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_q;
    wire [4:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_wraddr_i = 5'b11111;
    wire [5:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_a;
    wire [5:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_b;
    logic [5:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_o;
    wire [5:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_q;
    reg [15:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_inputreg0_q;
    reg [15:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_outputreg0_q;
    wire redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_reset0;
    wire [15:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_ia;
    wire [4:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_aa;
    wire [4:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_ab;
    wire [15:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_iq;
    wire [15:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_q;
    wire [4:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_wraddr_i = 5'b11111;
    wire [5:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_a;
    wire [5:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_b;
    logic [5:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_o;
    wire [5:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_q;
    reg [15:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_inputreg0_q;
    reg [15:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_outputreg0_q;
    wire redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_reset0;
    wire [15:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_ia;
    wire [4:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_aa;
    wire [4:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_ab;
    wire [15:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_iq;
    wire [15:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_q;
    wire [4:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_wraddr_i = 5'b11111;
    wire [5:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_a;
    wire [5:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_b;
    logic [5:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_o;
    wire [5:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_q;
    reg [15:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_inputreg0_q;
    reg [15:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_outputreg0_q;
    wire redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_reset0;
    wire [15:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_ia;
    wire [4:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_aa;
    wire [4:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_ab;
    wire [15:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_iq;
    wire [15:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_q;
    wire [4:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_wraddr_i = 5'b11111;
    wire [5:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_a;
    wire [5:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_b;
    logic [5:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_o;
    wire [5:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_q;
    reg [15:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_inputreg0_q;
    reg [15:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_outputreg0_q;
    wire redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_reset0;
    wire [15:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_ia;
    wire [4:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_aa;
    wire [4:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_ab;
    wire [15:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_iq;
    wire [15:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_q;
    wire [4:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_wraddr_i = 5'b11111;
    wire [5:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_a;
    wire [5:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_b;
    logic [5:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_o;
    wire [5:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_q;
    reg [15:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_inputreg0_q;
    reg [15:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_outputreg0_q;
    wire redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_reset0;
    wire [15:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_ia;
    wire [4:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_aa;
    wire [4:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_ab;
    wire [15:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_iq;
    wire [15:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_q;
    wire [4:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_wraddr_i = 5'b11111;
    wire [5:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_a;
    wire [5:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_b;
    logic [5:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_o;
    wire [5:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_q;
    reg [15:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_inputreg0_q;
    reg [15:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_outputreg0_q;
    wire redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_reset0;
    wire [15:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_ia;
    wire [4:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_aa;
    wire [4:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_ab;
    wire [15:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_iq;
    wire [15:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_q;
    wire [4:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_wraddr_i = 5'b11111;
    wire [5:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_a;
    wire [5:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_b;
    logic [5:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_o;
    wire [5:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_q;
    reg [15:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_inputreg0_q;
    reg [15:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_outputreg0_q;
    wire redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_reset0;
    wire [15:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_ia;
    wire [4:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_aa;
    wire [4:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_ab;
    wire [15:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_iq;
    wire [15:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_q;
    wire [4:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_wraddr_i = 5'b11111;
    wire [5:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_a;
    wire [5:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_b;
    logic [5:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_o;
    wire [5:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_q;
    reg [15:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_inputreg0_q;
    reg [15:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_outputreg0_q;
    wire redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_reset0;
    wire [15:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_ia;
    wire [4:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_aa;
    wire [4:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_ab;
    wire [15:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_iq;
    wire [15:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_q;
    wire [4:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_wraddr_i = 5'b11111;
    wire [5:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_a;
    wire [5:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_b;
    logic [5:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_o;
    wire [5:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_q;
    reg [15:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_inputreg0_q;
    reg [15:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_outputreg0_q;
    wire redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_reset0;
    wire [15:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_ia;
    wire [4:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_aa;
    wire [4:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_ab;
    wire [15:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_iq;
    wire [15:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_q;
    wire [4:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_wraddr_i = 5'b11111;
    wire [5:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_a;
    wire [5:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_b;
    logic [5:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_o;
    wire [5:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_q;
    reg [15:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_inputreg0_q;
    reg [15:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_outputreg0_q;
    wire redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_reset0;
    wire [15:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_ia;
    wire [4:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_aa;
    wire [4:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_ab;
    wire [15:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_iq;
    wire [15:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_q;
    wire [4:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_wraddr_i = 5'b11111;
    wire [5:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_a;
    wire [5:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_b;
    logic [5:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_o;
    wire [5:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_q;
    reg [15:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_inputreg0_q;
    reg [15:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_outputreg0_q;
    wire redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_reset0;
    wire [15:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_ia;
    wire [4:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_aa;
    wire [4:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_ab;
    wire [15:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_iq;
    wire [15:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_q;
    wire [4:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_wraddr_i = 5'b11111;
    wire [5:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_a;
    wire [5:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_b;
    logic [5:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_o;
    wire [5:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_q;
    reg [15:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_inputreg0_q;
    reg [15:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_outputreg0_q;
    wire redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_reset0;
    wire [15:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_ia;
    wire [4:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_aa;
    wire [4:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_ab;
    wire [15:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_iq;
    wire [15:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_q;
    wire [4:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_wraddr_i = 5'b11111;
    wire [5:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_a;
    wire [5:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_b;
    logic [5:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_o;
    wire [5:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_q;
    reg [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_inputreg0_q;
    reg [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_outputreg0_q;
    reg [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_inputreg0_q;
    reg [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_outputreg0_q;
    reg [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_inputreg0_q;
    reg [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_outputreg0_q;
    wire redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_reset0;
    wire [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_ia;
    wire [1:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_aa;
    wire [1:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_ab;
    wire [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_iq;
    wire [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_q;
    wire [1:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_wraddr_i = 2'b11;
    wire [2:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_a;
    wire [2:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_b;
    logic [2:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_o;
    wire [2:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_q;
    reg [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_inputreg0_q;
    reg [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_outputreg0_q;
    wire redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_reset0;
    wire [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_ia;
    wire [1:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_aa;
    wire [1:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_ab;
    wire [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_iq;
    wire [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_q;
    wire [1:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_wraddr_i = 2'b11;
    wire [2:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_a;
    wire [2:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_b;
    logic [2:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_o;
    wire [2:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_q;
    reg [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_inputreg0_q;
    reg [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_outputreg0_q;
    wire redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_reset0;
    wire [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_ia;
    wire [2:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_aa;
    wire [2:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_ab;
    wire [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_iq;
    wire [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_q;
    wire [2:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_wraddr_i = 3'b111;
    wire [3:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_a;
    wire [3:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_b;
    logic [3:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_o;
    wire [3:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_q;
    reg [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_inputreg0_q;
    reg [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_outputreg0_q;
    wire redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_reset0;
    wire [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_ia;
    wire [2:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_aa;
    wire [2:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_ab;
    wire [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_iq;
    wire [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_q;
    wire [2:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_wraddr_i = 3'b111;
    wire [3:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_a;
    wire [3:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_b;
    logic [3:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_o;
    wire [3:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_q;
    reg [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_inputreg0_q;
    reg [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_outputreg0_q;
    wire redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_reset0;
    wire [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_ia;
    wire [2:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_aa;
    wire [2:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_ab;
    wire [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_iq;
    wire [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_q;
    wire [2:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_wraddr_i = 3'b111;
    wire [3:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_a;
    wire [3:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_b;
    logic [3:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_o;
    wire [3:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_q;
    reg [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_inputreg0_q;
    reg [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_outputreg0_q;
    wire redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_reset0;
    wire [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_ia;
    wire [2:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_aa;
    wire [2:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_ab;
    wire [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_iq;
    wire [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_q;
    wire [2:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_wraddr_i = 3'b111;
    wire [3:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_a;
    wire [3:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_b;
    logic [3:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_o;
    wire [3:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_q;
    reg [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_inputreg0_q;
    reg [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_outputreg0_q;
    wire redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_reset0;
    wire [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_ia;
    wire [3:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_aa;
    wire [3:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_ab;
    wire [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_iq;
    wire [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_q;
    wire [3:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_wraddr_i = 4'b1111;
    wire [4:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_a;
    wire [4:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_b;
    logic [4:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_o;
    wire [4:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_q;
    reg [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_inputreg0_q;
    reg [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_outputreg0_q;
    wire redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_reset0;
    wire [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_ia;
    wire [3:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_aa;
    wire [3:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_ab;
    wire [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_iq;
    wire [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_q;
    wire [3:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_wraddr_i = 4'b1111;
    wire [4:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_a;
    wire [4:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_b;
    logic [4:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_o;
    wire [4:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_q;
    reg [15:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_inputreg0_q;
    reg [15:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_outputreg0_q;
    wire redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_reset0;
    wire [15:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_ia;
    wire [3:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_aa;
    wire [3:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_ab;
    wire [15:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_iq;
    wire [15:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_q;
    wire [3:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_wraddr_i = 4'b1111;
    wire [4:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_a;
    wire [4:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_b;
    logic [4:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_o;
    wire [4:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_q;
    reg [15:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_inputreg0_q;
    reg [15:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_outputreg0_q;
    wire redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_reset0;
    wire [15:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_ia;
    wire [3:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_aa;
    wire [3:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_ab;
    wire [15:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_iq;
    wire [15:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_q;
    wire [3:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_wraddr_i = 4'b1111;
    wire [4:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_a;
    wire [4:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_b;
    logic [4:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_o;
    wire [4:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_q;
    reg [15:0] redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_inputreg0_q;
    reg [15:0] redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_outputreg0_q;
    wire redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_reset0;
    wire [15:0] redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_ia;
    wire [6:0] redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_aa;
    wire [6:0] redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_ab;
    wire [15:0] redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_iq;
    wire [15:0] redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_q;
    wire [6:0] redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_wraddr_i = 7'b1111111;
    wire [7:0] redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_a;
    wire [7:0] redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_b;
    logic [7:0] redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_o;
    wire [7:0] redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_q;
    reg [15:0] redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_inputreg0_q;
    reg [15:0] redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_outputreg0_q;
    wire redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_reset0;
    wire [15:0] redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_ia;
    wire [6:0] redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_aa;
    wire [6:0] redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_ab;
    wire [15:0] redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_iq;
    wire [15:0] redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_q;
    wire [6:0] redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_wraddr_i = 7'b1111111;
    wire [7:0] redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_a;
    wire [7:0] redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_b;
    logic [7:0] redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_o;
    wire [7:0] redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_q;
    reg [15:0] redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_inputreg0_q;
    reg [15:0] redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_outputreg0_q;
    wire redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_reset0;
    wire [15:0] redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_ia;
    wire [6:0] redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_aa;
    wire [6:0] redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_ab;
    wire [15:0] redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_iq;
    wire [15:0] redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_q;
    wire [6:0] redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_wraddr_i = 7'b1111111;
    wire [7:0] redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_a;
    wire [7:0] redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_b;
    logic [7:0] redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_o;
    wire [7:0] redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_q;
    reg [15:0] redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_inputreg0_q;
    reg [15:0] redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_outputreg0_q;
    wire redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_reset0;
    wire [15:0] redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_ia;
    wire [6:0] redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_aa;
    wire [6:0] redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_ab;
    wire [15:0] redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_iq;
    wire [15:0] redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_q;
    wire [6:0] redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_wraddr_i = 7'b1111111;
    wire [7:0] redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_a;
    wire [7:0] redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_b;
    logic [7:0] redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_o;
    wire [7:0] redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_q;
    reg [15:0] redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_inputreg0_q;
    reg [15:0] redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_outputreg0_q;
    wire redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_reset0;
    wire [15:0] redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_ia;
    wire [6:0] redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_aa;
    wire [6:0] redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_ab;
    wire [15:0] redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_iq;
    wire [15:0] redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_q;
    wire [6:0] redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_wraddr_i = 7'b1111111;
    wire [7:0] redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_a;
    wire [7:0] redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_b;
    logic [7:0] redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_o;
    wire [7:0] redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_q;
    reg [15:0] redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_inputreg0_q;
    reg [15:0] redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_outputreg0_q;
    wire redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_reset0;
    wire [15:0] redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_ia;
    wire [6:0] redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_aa;
    wire [6:0] redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_ab;
    wire [15:0] redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_iq;
    wire [15:0] redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_q;
    wire [6:0] redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_wraddr_i = 7'b1111111;
    wire [7:0] redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_a;
    wire [7:0] redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_b;
    logic [7:0] redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_o;
    wire [7:0] redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_q;
    reg [15:0] redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_inputreg0_q;
    reg [15:0] redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_outputreg0_q;
    wire redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_reset0;
    wire [15:0] redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_ia;
    wire [6:0] redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_aa;
    wire [6:0] redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_ab;
    wire [15:0] redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_iq;
    wire [15:0] redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_q;
    wire [6:0] redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_wraddr_i = 7'b1111111;
    wire [7:0] redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_a;
    wire [7:0] redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_b;
    logic [7:0] redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_o;
    wire [7:0] redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_q;
    reg [15:0] redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_inputreg0_q;
    reg [15:0] redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_outputreg0_q;
    wire redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_reset0;
    wire [15:0] redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_ia;
    wire [6:0] redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_aa;
    wire [6:0] redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_ab;
    wire [15:0] redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_iq;
    wire [15:0] redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_q;
    wire [6:0] redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_wraddr_i = 7'b1111111;
    wire [7:0] redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_a;
    wire [7:0] redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_b;
    logic [7:0] redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_o;
    wire [7:0] redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_q;
    reg [15:0] redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_inputreg0_q;
    reg [15:0] redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_outputreg0_q;
    wire redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_reset0;
    wire [15:0] redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_ia;
    wire [6:0] redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_aa;
    wire [6:0] redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_ab;
    wire [15:0] redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_iq;
    wire [15:0] redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_q;
    wire [6:0] redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_wraddr_i = 7'b1111111;
    wire [7:0] redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_a;
    wire [7:0] redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_b;
    logic [7:0] redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_o;
    wire [7:0] redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_q;
    reg [15:0] redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_inputreg0_q;
    reg [15:0] redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_outputreg0_q;
    wire redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_reset0;
    wire [15:0] redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_ia;
    wire [6:0] redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_aa;
    wire [6:0] redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_ab;
    wire [15:0] redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_iq;
    wire [15:0] redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_q;
    wire [6:0] redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_wraddr_i = 7'b1111111;
    wire [7:0] redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_a;
    wire [7:0] redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_b;
    logic [7:0] redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_o;
    wire [7:0] redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_q;
    reg [15:0] redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_inputreg0_q;
    reg [15:0] redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_outputreg0_q;
    wire redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_reset0;
    wire [15:0] redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_ia;
    wire [6:0] redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_aa;
    wire [6:0] redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_ab;
    wire [15:0] redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_iq;
    wire [15:0] redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_q;
    wire [6:0] redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_wraddr_i = 7'b1111111;
    wire [7:0] redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_a;
    wire [7:0] redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_b;
    logic [7:0] redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_o;
    wire [7:0] redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_q;
    reg [15:0] redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_inputreg0_q;
    reg [15:0] redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_outputreg0_q;
    wire redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_reset0;
    wire [15:0] redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_ia;
    wire [6:0] redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_aa;
    wire [6:0] redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_ab;
    wire [15:0] redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_iq;
    wire [15:0] redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_q;
    wire [6:0] redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_wraddr_i = 7'b1111111;
    wire [7:0] redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_a;
    wire [7:0] redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_b;
    logic [7:0] redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_o;
    wire [7:0] redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_q;
    reg [15:0] redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_inputreg0_q;
    reg [15:0] redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_outputreg0_q;
    wire redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_reset0;
    wire [15:0] redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_ia;
    wire [6:0] redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_aa;
    wire [6:0] redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_ab;
    wire [15:0] redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_iq;
    wire [15:0] redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_q;
    wire [6:0] redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_wraddr_i = 7'b1111111;
    wire [7:0] redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_a;
    wire [7:0] redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_b;
    logic [7:0] redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_o;
    wire [7:0] redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_q;
    reg [15:0] redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_inputreg0_q;
    reg [15:0] redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_outputreg0_q;
    wire redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_reset0;
    wire [15:0] redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_ia;
    wire [6:0] redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_aa;
    wire [6:0] redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_ab;
    wire [15:0] redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_iq;
    wire [15:0] redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_q;
    wire [6:0] redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_wraddr_i = 7'b1111111;
    wire [7:0] redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_a;
    wire [7:0] redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_b;
    logic [7:0] redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_o;
    wire [7:0] redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_q;
    reg [15:0] redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_inputreg0_q;
    reg [15:0] redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_outputreg0_q;
    wire redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_reset0;
    wire [15:0] redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_ia;
    wire [6:0] redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_aa;
    wire [6:0] redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_ab;
    wire [15:0] redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_iq;
    wire [15:0] redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_q;
    wire [6:0] redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_wraddr_i = 7'b1111111;
    wire [7:0] redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_a;
    wire [7:0] redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_b;
    logic [7:0] redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_o;
    wire [7:0] redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_q;
    reg [15:0] redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_inputreg0_q;
    reg [15:0] redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_outputreg0_q;
    wire redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_reset0;
    wire [15:0] redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_ia;
    wire [6:0] redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_aa;
    wire [6:0] redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_ab;
    wire [15:0] redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_iq;
    wire [15:0] redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_q;
    wire [6:0] redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_wraddr_i = 7'b1111111;
    wire [7:0] redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_a;
    wire [7:0] redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_b;
    logic [7:0] redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_o;
    wire [7:0] redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_q;
    reg [15:0] redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_inputreg0_q;
    reg [15:0] redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_outputreg0_q;
    wire redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_reset0;
    wire [15:0] redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_ia;
    wire [6:0] redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_aa;
    wire [6:0] redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_ab;
    wire [15:0] redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_iq;
    wire [15:0] redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_q;
    wire [6:0] redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_wraddr_i = 7'b1111111;
    wire [7:0] redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_a;
    wire [7:0] redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_b;
    logic [7:0] redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_o;
    wire [7:0] redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_q;
    reg [15:0] redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_inputreg0_q;
    reg [15:0] redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_outputreg0_q;
    wire redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_reset0;
    wire [15:0] redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_ia;
    wire [6:0] redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_aa;
    wire [6:0] redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_ab;
    wire [15:0] redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_iq;
    wire [15:0] redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_q;
    wire [6:0] redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_wraddr_i = 7'b1111111;
    wire [7:0] redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_a;
    wire [7:0] redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_b;
    logic [7:0] redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_o;
    wire [7:0] redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_q;
    reg [15:0] redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_inputreg0_q;
    reg [15:0] redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_outputreg0_q;
    wire redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_reset0;
    wire [15:0] redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_ia;
    wire [6:0] redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_aa;
    wire [6:0] redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_ab;
    wire [15:0] redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_iq;
    wire [15:0] redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_q;
    wire [6:0] redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_wraddr_i = 7'b1111111;
    wire [7:0] redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_a;
    wire [7:0] redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_b;
    logic [7:0] redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_o;
    wire [7:0] redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_q;
    reg [15:0] redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_inputreg0_q;
    reg [15:0] redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_outputreg0_q;
    wire redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_reset0;
    wire [15:0] redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_ia;
    wire [6:0] redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_aa;
    wire [6:0] redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_ab;
    wire [15:0] redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_iq;
    wire [15:0] redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_q;
    wire [6:0] redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_wraddr_i = 7'b1111111;
    wire [7:0] redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_a;
    wire [7:0] redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_b;
    logic [7:0] redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_o;
    wire [7:0] redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_q;
    reg [15:0] redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_inputreg0_q;
    reg [15:0] redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_outputreg0_q;
    wire redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_reset0;
    wire [15:0] redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_ia;
    wire [6:0] redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_aa;
    wire [6:0] redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_ab;
    wire [15:0] redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_iq;
    wire [15:0] redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_q;
    wire [6:0] redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_wraddr_i = 7'b1111111;
    wire [7:0] redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_a;
    wire [7:0] redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_b;
    logic [7:0] redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_o;
    wire [7:0] redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_q;
    reg [15:0] redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_inputreg0_q;
    reg [15:0] redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_outputreg0_q;
    wire redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_reset0;
    wire [15:0] redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_ia;
    wire [6:0] redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_aa;
    wire [6:0] redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_ab;
    wire [15:0] redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_iq;
    wire [15:0] redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_q;
    wire [6:0] redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_wraddr_i = 7'b1111111;
    wire [7:0] redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_a;
    wire [7:0] redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_b;
    logic [7:0] redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_o;
    wire [7:0] redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_q;
    reg [15:0] redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_inputreg0_q;
    reg [15:0] redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_outputreg0_q;
    wire redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_reset0;
    wire [15:0] redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_ia;
    wire [6:0] redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_aa;
    wire [6:0] redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_ab;
    wire [15:0] redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_iq;
    wire [15:0] redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_q;
    wire [6:0] redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_wraddr_i = 7'b1111111;
    wire [7:0] redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_a;
    wire [7:0] redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_b;
    logic [7:0] redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_o;
    wire [7:0] redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_q;
    reg [15:0] redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_inputreg0_q;
    reg [15:0] redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_outputreg0_q;
    wire redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_reset0;
    wire [15:0] redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_ia;
    wire [6:0] redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_aa;
    wire [6:0] redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_ab;
    wire [15:0] redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_iq;
    wire [15:0] redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_q;
    wire [6:0] redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_wraddr_i = 7'b1111111;
    wire [7:0] redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_a;
    wire [7:0] redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_b;
    logic [7:0] redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_o;
    wire [7:0] redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_q;
    reg [15:0] redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_inputreg0_q;
    reg [15:0] redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_outputreg0_q;
    wire redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_reset0;
    wire [15:0] redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_ia;
    wire [6:0] redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_aa;
    wire [6:0] redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_ab;
    wire [15:0] redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_iq;
    wire [15:0] redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_q;
    wire [6:0] redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_wraddr_i = 7'b1111111;
    wire [7:0] redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_a;
    wire [7:0] redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_b;
    logic [7:0] redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_o;
    wire [7:0] redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_q;
    reg [15:0] redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_inputreg0_q;
    reg [15:0] redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_outputreg0_q;
    wire redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_reset0;
    wire [15:0] redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_ia;
    wire [6:0] redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_aa;
    wire [6:0] redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_ab;
    wire [15:0] redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_iq;
    wire [15:0] redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_q;
    wire [6:0] redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_wraddr_i = 7'b1111111;
    wire [7:0] redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_a;
    wire [7:0] redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_b;
    logic [7:0] redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_o;
    wire [7:0] redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_q;
    reg [15:0] redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_inputreg0_q;
    reg [15:0] redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_outputreg0_q;
    wire redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_reset0;
    wire [15:0] redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_ia;
    wire [6:0] redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_aa;
    wire [6:0] redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_ab;
    wire [15:0] redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_iq;
    wire [15:0] redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_q;
    wire [6:0] redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_wraddr_i = 7'b1111111;
    wire [7:0] redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_a;
    wire [7:0] redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_b;
    logic [7:0] redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_o;
    wire [7:0] redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_q;
    reg [15:0] redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_inputreg0_q;
    reg [15:0] redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_outputreg0_q;
    wire redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_reset0;
    wire [15:0] redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_ia;
    wire [6:0] redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_aa;
    wire [6:0] redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_ab;
    wire [15:0] redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_iq;
    wire [15:0] redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_q;
    wire [6:0] redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_wraddr_i = 7'b1111111;
    wire [7:0] redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_a;
    wire [7:0] redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_b;
    logic [7:0] redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_o;
    wire [7:0] redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_q;
    reg [15:0] redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_inputreg0_q;
    reg [15:0] redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_outputreg0_q;
    wire redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_reset0;
    wire [15:0] redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_ia;
    wire [6:0] redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_aa;
    wire [6:0] redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_ab;
    wire [15:0] redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_iq;
    wire [15:0] redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_q;
    wire [6:0] redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_wraddr_i = 7'b1111111;
    wire [7:0] redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_a;
    wire [7:0] redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_b;
    logic [7:0] redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_o;
    wire [7:0] redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_q;
    reg [15:0] redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_inputreg0_q;
    reg [15:0] redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_outputreg0_q;
    wire redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_reset0;
    wire [15:0] redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_ia;
    wire [6:0] redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_aa;
    wire [6:0] redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_ab;
    wire [15:0] redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_iq;
    wire [15:0] redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_q;
    wire [6:0] redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_wraddr_i = 7'b1111111;
    wire [7:0] redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_a;
    wire [7:0] redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_b;
    logic [7:0] redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_o;
    wire [7:0] redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_q;
    reg [15:0] redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_inputreg0_q;
    reg [15:0] redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_outputreg0_q;
    wire redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_reset0;
    wire [15:0] redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_ia;
    wire [6:0] redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_aa;
    wire [6:0] redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_ab;
    wire [15:0] redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_iq;
    wire [15:0] redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_q;
    wire [6:0] redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_wraddr_i = 7'b1111111;
    wire [7:0] redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_a;
    wire [7:0] redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_b;
    logic [7:0] redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_o;
    wire [7:0] redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_q;
    reg [15:0] redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_inputreg0_q;
    reg [15:0] redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_outputreg0_q;
    wire redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_reset0;
    wire [15:0] redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_ia;
    wire [6:0] redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_aa;
    wire [6:0] redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_ab;
    wire [15:0] redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_iq;
    wire [15:0] redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_q;
    wire [6:0] redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_wraddr_i = 7'b1111111;
    wire [7:0] redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_a;
    wire [7:0] redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_b;
    logic [7:0] redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_o;
    wire [7:0] redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_q;
    reg [15:0] redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_inputreg0_q;
    reg [15:0] redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_outputreg0_q;
    wire redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_reset0;
    wire [15:0] redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_ia;
    wire [6:0] redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_aa;
    wire [6:0] redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_ab;
    wire [15:0] redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_iq;
    wire [15:0] redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_q;
    wire [6:0] redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_wraddr_i = 7'b1111111;
    wire [7:0] redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_a;
    wire [7:0] redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_b;
    logic [7:0] redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_o;
    wire [7:0] redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_q;
    reg [15:0] redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_inputreg0_q;
    reg [15:0] redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_outputreg0_q;
    wire redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_reset0;
    wire [15:0] redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_ia;
    wire [6:0] redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_aa;
    wire [6:0] redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_ab;
    wire [15:0] redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_iq;
    wire [15:0] redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_q;
    wire [6:0] redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_wraddr_i = 7'b1111111;
    wire [7:0] redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_a;
    wire [7:0] redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_b;
    logic [7:0] redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_o;
    wire [7:0] redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_q;
    reg [15:0] redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_inputreg0_q;
    reg [15:0] redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_outputreg0_q;
    wire redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_reset0;
    wire [15:0] redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_ia;
    wire [6:0] redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_aa;
    wire [6:0] redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_ab;
    wire [15:0] redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_iq;
    wire [15:0] redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_q;
    wire [6:0] redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_wraddr_i = 7'b1111111;
    wire [7:0] redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_a;
    wire [7:0] redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_b;
    logic [7:0] redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_o;
    wire [7:0] redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_q;
    reg [15:0] redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_inputreg0_q;
    reg [15:0] redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_outputreg0_q;
    wire redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_reset0;
    wire [15:0] redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_ia;
    wire [6:0] redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_aa;
    wire [6:0] redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_ab;
    wire [15:0] redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_iq;
    wire [15:0] redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_q;
    wire [6:0] redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_wraddr_i = 7'b1111111;
    wire [7:0] redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_a;
    wire [7:0] redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_b;
    logic [7:0] redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_o;
    wire [7:0] redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_q;
    reg [15:0] redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_inputreg0_q;
    reg [15:0] redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_outputreg0_q;
    wire redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_reset0;
    wire [15:0] redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_ia;
    wire [6:0] redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_aa;
    wire [6:0] redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_ab;
    wire [15:0] redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_iq;
    wire [15:0] redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_q;
    wire [6:0] redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_wraddr_i = 7'b1111111;
    wire [7:0] redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_a;
    wire [7:0] redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_b;
    logic [7:0] redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_o;
    wire [7:0] redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_q;
    reg [15:0] redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_inputreg0_q;
    reg [15:0] redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_outputreg0_q;
    wire redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_reset0;
    wire [15:0] redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_ia;
    wire [6:0] redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_aa;
    wire [6:0] redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_ab;
    wire [15:0] redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_iq;
    wire [15:0] redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_q;
    wire [6:0] redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_wraddr_i = 7'b1111111;
    wire [7:0] redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_a;
    wire [7:0] redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_b;
    logic [7:0] redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_o;
    wire [7:0] redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_q;
    reg [15:0] redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_inputreg0_q;
    reg [15:0] redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_outputreg0_q;
    wire redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_reset0;
    wire [15:0] redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_ia;
    wire [6:0] redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_aa;
    wire [6:0] redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_ab;
    wire [15:0] redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_iq;
    wire [15:0] redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_q;
    wire [6:0] redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_wraddr_i = 7'b1111111;
    wire [7:0] redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_a;
    wire [7:0] redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_b;
    logic [7:0] redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_o;
    wire [7:0] redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_q;
    reg [15:0] redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_inputreg0_q;
    reg [15:0] redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_outputreg0_q;
    wire redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_reset0;
    wire [15:0] redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_ia;
    wire [6:0] redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_aa;
    wire [6:0] redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_ab;
    wire [15:0] redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_iq;
    wire [15:0] redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_q;
    wire [6:0] redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_wraddr_i = 7'b1111111;
    wire [7:0] redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_a;
    wire [7:0] redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_b;
    logic [7:0] redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_o;
    wire [7:0] redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_q;
    reg [15:0] redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_inputreg0_q;
    reg [15:0] redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_outputreg0_q;
    wire redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_reset0;
    wire [15:0] redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_ia;
    wire [6:0] redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_aa;
    wire [6:0] redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_ab;
    wire [15:0] redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_iq;
    wire [15:0] redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_q;
    wire [6:0] redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_wraddr_i = 7'b1111111;
    wire [7:0] redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_a;
    wire [7:0] redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_b;
    logic [7:0] redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_o;
    wire [7:0] redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_q;
    reg [15:0] redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_inputreg0_q;
    reg [15:0] redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_outputreg0_q;
    wire redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_reset0;
    wire [15:0] redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_ia;
    wire [6:0] redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_aa;
    wire [6:0] redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_ab;
    wire [15:0] redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_iq;
    wire [15:0] redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_q;
    wire [6:0] redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_wraddr_i = 7'b1111111;
    wire [7:0] redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_a;
    wire [7:0] redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_b;
    logic [7:0] redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_o;
    wire [7:0] redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_q;
    reg [15:0] redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_inputreg0_q;
    reg [15:0] redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_outputreg0_q;
    wire redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_reset0;
    wire [15:0] redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_ia;
    wire [6:0] redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_aa;
    wire [6:0] redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_ab;
    wire [15:0] redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_iq;
    wire [15:0] redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_q;
    wire [6:0] redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_wraddr_i = 7'b1111111;
    wire [7:0] redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_a;
    wire [7:0] redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_b;
    logic [7:0] redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_o;
    wire [7:0] redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_q;
    reg [15:0] redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_inputreg0_q;
    reg [15:0] redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_outputreg0_q;
    wire redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_reset0;
    wire [15:0] redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_ia;
    wire [6:0] redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_aa;
    wire [6:0] redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_ab;
    wire [15:0] redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_iq;
    wire [15:0] redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_q;
    wire [6:0] redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_wraddr_i = 7'b1111111;
    wire [7:0] redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_a;
    wire [7:0] redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_b;
    logic [7:0] redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_o;
    wire [7:0] redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_q;
    reg [15:0] redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_inputreg0_q;
    reg [15:0] redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_outputreg0_q;
    wire redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_reset0;
    wire [15:0] redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_ia;
    wire [6:0] redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_aa;
    wire [6:0] redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_ab;
    wire [15:0] redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_iq;
    wire [15:0] redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_q;
    wire [6:0] redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_wraddr_i = 7'b1111111;
    wire [7:0] redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_a;
    wire [7:0] redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_b;
    logic [7:0] redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_o;
    wire [7:0] redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_q;
    reg [15:0] redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_inputreg0_q;
    reg [15:0] redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_outputreg0_q;
    wire redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_reset0;
    wire [15:0] redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_ia;
    wire [6:0] redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_aa;
    wire [6:0] redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_ab;
    wire [15:0] redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_iq;
    wire [15:0] redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_q;
    wire [6:0] redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_wraddr_i = 7'b1111111;
    wire [7:0] redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_a;
    wire [7:0] redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_b;
    logic [7:0] redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_o;
    wire [7:0] redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_q;
    reg [15:0] redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_inputreg0_q;
    reg [15:0] redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_outputreg0_q;
    wire redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_reset0;
    wire [15:0] redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_ia;
    wire [6:0] redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_aa;
    wire [6:0] redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_ab;
    wire [15:0] redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_iq;
    wire [15:0] redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_q;
    wire [6:0] redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_wraddr_i = 7'b1111111;
    wire [7:0] redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_a;
    wire [7:0] redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_b;
    logic [7:0] redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_o;
    wire [7:0] redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_q;
    reg [15:0] redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_inputreg0_q;
    reg [15:0] redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_outputreg0_q;
    wire redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_reset0;
    wire [15:0] redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_ia;
    wire [6:0] redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_aa;
    wire [6:0] redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_ab;
    wire [15:0] redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_iq;
    wire [15:0] redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_q;
    wire [6:0] redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_wraddr_i = 7'b1111111;
    wire [7:0] redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_a;
    wire [7:0] redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_b;
    logic [7:0] redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_o;
    wire [7:0] redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_q;
    reg [15:0] redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_inputreg0_q;
    reg [15:0] redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_outputreg0_q;
    wire redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_reset0;
    wire [15:0] redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_ia;
    wire [6:0] redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_aa;
    wire [6:0] redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_ab;
    wire [15:0] redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_iq;
    wire [15:0] redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_q;
    wire [6:0] redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_wraddr_i = 7'b1111111;
    wire [7:0] redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_a;
    wire [7:0] redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_b;
    logic [7:0] redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_o;
    wire [7:0] redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_q;
    reg [15:0] redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_inputreg0_q;
    reg [15:0] redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_outputreg0_q;
    wire redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_reset0;
    wire [15:0] redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_ia;
    wire [6:0] redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_aa;
    wire [6:0] redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_ab;
    wire [15:0] redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_iq;
    wire [15:0] redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_q;
    wire [6:0] redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_wraddr_i = 7'b1111111;
    wire [7:0] redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_a;
    wire [7:0] redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_b;
    logic [7:0] redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_o;
    wire [7:0] redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_q;
    reg [15:0] redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_inputreg0_q;
    reg [15:0] redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_outputreg0_q;
    wire redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_reset0;
    wire [15:0] redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_ia;
    wire [7:0] redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_aa;
    wire [7:0] redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_ab;
    wire [15:0] redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_iq;
    wire [15:0] redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_q;
    wire [7:0] redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_wraddr_i = 8'b11111111;
    wire [8:0] redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_a;
    wire [8:0] redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_b;
    logic [8:0] redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_o;
    wire [8:0] redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_q;
    reg [15:0] redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_inputreg0_q;
    reg [15:0] redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_outputreg0_q;
    wire redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_reset0;
    wire [15:0] redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_ia;
    wire [7:0] redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_aa;
    wire [7:0] redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_ab;
    wire [15:0] redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_iq;
    wire [15:0] redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_q;
    wire [7:0] redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_wraddr_i = 8'b11111111;
    wire [8:0] redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_a;
    wire [8:0] redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_b;
    logic [8:0] redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_o;
    wire [8:0] redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_q;
    reg [15:0] redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_inputreg0_q;
    reg [15:0] redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_outputreg0_q;
    wire redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_reset0;
    wire [15:0] redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_ia;
    wire [7:0] redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_aa;
    wire [7:0] redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_ab;
    wire [15:0] redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_iq;
    wire [15:0] redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_q;
    wire [7:0] redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_wraddr_i = 8'b11111111;
    wire [8:0] redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_a;
    wire [8:0] redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_b;
    logic [8:0] redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_o;
    wire [8:0] redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_q;
    reg [15:0] redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_inputreg0_q;
    reg [15:0] redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_outputreg0_q;
    wire redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_reset0;
    wire [15:0] redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_ia;
    wire [7:0] redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_aa;
    wire [7:0] redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_ab;
    wire [15:0] redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_iq;
    wire [15:0] redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_q;
    wire [7:0] redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_wraddr_i = 8'b11111111;
    wire [8:0] redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_a;
    wire [8:0] redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_b;
    logic [8:0] redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_o;
    wire [8:0] redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_q;
    reg [15:0] redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_inputreg0_q;
    reg [15:0] redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_outputreg0_q;
    wire redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_reset0;
    wire [15:0] redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_ia;
    wire [7:0] redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_aa;
    wire [7:0] redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_ab;
    wire [15:0] redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_iq;
    wire [15:0] redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_q;
    wire [7:0] redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_wraddr_i = 8'b11111111;
    wire [8:0] redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_a;
    wire [8:0] redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_b;
    logic [8:0] redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_o;
    wire [8:0] redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_q;
    reg [15:0] redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_inputreg0_q;
    reg [15:0] redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_outputreg0_q;
    wire redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_reset0;
    wire [15:0] redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_ia;
    wire [7:0] redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_aa;
    wire [7:0] redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_ab;
    wire [15:0] redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_iq;
    wire [15:0] redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_q;
    wire [7:0] redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_wraddr_i = 8'b11111111;
    wire [8:0] redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_a;
    wire [8:0] redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_b;
    logic [8:0] redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_o;
    wire [8:0] redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_q;
    reg [15:0] redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_inputreg0_q;
    reg [15:0] redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_outputreg0_q;
    wire redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_reset0;
    wire [15:0] redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_ia;
    wire [7:0] redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_aa;
    wire [7:0] redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_ab;
    wire [15:0] redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_iq;
    wire [15:0] redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_q;
    wire [7:0] redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_wraddr_i = 8'b11111111;
    wire [8:0] redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_a;
    wire [8:0] redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_b;
    logic [8:0] redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_o;
    wire [8:0] redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_q;
    reg [15:0] redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_inputreg0_q;
    reg [15:0] redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_outputreg0_q;
    wire redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_reset0;
    wire [15:0] redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_ia;
    wire [7:0] redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_aa;
    wire [7:0] redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_ab;
    wire [15:0] redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_iq;
    wire [15:0] redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_q;
    wire [7:0] redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_wraddr_i = 8'b11111111;
    wire [8:0] redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_a;
    wire [8:0] redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_b;
    logic [8:0] redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_o;
    wire [8:0] redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_q;
    reg [15:0] redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_inputreg0_q;
    reg [15:0] redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_outputreg0_q;
    wire redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_reset0;
    wire [15:0] redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_ia;
    wire [7:0] redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_aa;
    wire [7:0] redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_ab;
    wire [15:0] redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_iq;
    wire [15:0] redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_q;
    wire [7:0] redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_wraddr_i = 8'b11111111;
    wire [8:0] redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_a;
    wire [8:0] redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_b;
    logic [8:0] redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_o;
    wire [8:0] redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_q;
    reg [15:0] redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_inputreg0_q;
    reg [15:0] redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_outputreg0_q;
    wire redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_reset0;
    wire [15:0] redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_ia;
    wire [7:0] redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_aa;
    wire [7:0] redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_ab;
    wire [15:0] redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_iq;
    wire [15:0] redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_q;
    wire [7:0] redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_wraddr_i = 8'b11111111;
    wire [8:0] redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_a;
    wire [8:0] redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_b;
    logic [8:0] redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_o;
    wire [8:0] redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_q;
    reg [15:0] redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_inputreg0_q;
    reg [15:0] redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_outputreg0_q;
    wire redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_reset0;
    wire [15:0] redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_ia;
    wire [7:0] redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_aa;
    wire [7:0] redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_ab;
    wire [15:0] redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_iq;
    wire [15:0] redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_q;
    wire [7:0] redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_wraddr_i = 8'b11111111;
    wire [8:0] redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_a;
    wire [8:0] redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_b;
    logic [8:0] redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_o;
    wire [8:0] redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_q;
    reg [15:0] redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_inputreg0_q;
    reg [15:0] redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_outputreg0_q;
    wire redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_reset0;
    wire [15:0] redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_ia;
    wire [7:0] redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_aa;
    wire [7:0] redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_ab;
    wire [15:0] redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_iq;
    wire [15:0] redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_q;
    wire [7:0] redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_wraddr_i = 8'b11111111;
    wire [8:0] redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_a;
    wire [8:0] redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_b;
    logic [8:0] redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_o;
    wire [8:0] redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_q;
    reg [15:0] redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_inputreg0_q;
    reg [15:0] redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_outputreg0_q;
    wire redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_reset0;
    wire [15:0] redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_ia;
    wire [7:0] redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_aa;
    wire [7:0] redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_ab;
    wire [15:0] redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_iq;
    wire [15:0] redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_q;
    wire [7:0] redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_wraddr_i = 8'b11111111;
    wire [8:0] redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_a;
    wire [8:0] redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_b;
    logic [8:0] redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_o;
    wire [8:0] redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_q;
    reg [15:0] redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_inputreg0_q;
    reg [15:0] redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_outputreg0_q;
    wire redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_reset0;
    wire [15:0] redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_ia;
    wire [7:0] redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_aa;
    wire [7:0] redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_ab;
    wire [15:0] redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_iq;
    wire [15:0] redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_q;
    wire [7:0] redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_wraddr_i = 8'b11111111;
    wire [8:0] redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_a;
    wire [8:0] redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_b;
    logic [8:0] redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_o;
    wire [8:0] redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_q;
    reg [15:0] redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_inputreg0_q;
    reg [15:0] redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_outputreg0_q;
    wire redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_reset0;
    wire [15:0] redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_ia;
    wire [7:0] redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_aa;
    wire [7:0] redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_ab;
    wire [15:0] redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_iq;
    wire [15:0] redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_q;
    wire [7:0] redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_wraddr_i = 8'b11111111;
    wire [8:0] redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_a;
    wire [8:0] redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_b;
    logic [8:0] redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_o;
    wire [8:0] redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_q;
    reg [15:0] redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_inputreg0_q;
    reg [15:0] redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_outputreg0_q;
    wire redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_reset0;
    wire [15:0] redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_ia;
    wire [7:0] redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_aa;
    wire [7:0] redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_ab;
    wire [15:0] redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_iq;
    wire [15:0] redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_q;
    wire [7:0] redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_wraddr_i = 8'b11111111;
    wire [8:0] redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_a;
    wire [8:0] redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_b;
    logic [8:0] redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_o;
    wire [8:0] redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_q;
    reg [15:0] redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_inputreg0_q;
    reg [15:0] redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_outputreg0_q;
    wire redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_reset0;
    wire [15:0] redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_ia;
    wire [7:0] redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_aa;
    wire [7:0] redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_ab;
    wire [15:0] redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_iq;
    wire [15:0] redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_q;
    wire [7:0] redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_wraddr_i = 8'b11111111;
    wire [8:0] redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_a;
    wire [8:0] redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_b;
    logic [8:0] redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_o;
    wire [8:0] redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_q;
    reg [15:0] redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_inputreg0_q;
    reg [15:0] redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_outputreg0_q;
    wire redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_reset0;
    wire [15:0] redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_ia;
    wire [7:0] redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_aa;
    wire [7:0] redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_ab;
    wire [15:0] redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_iq;
    wire [15:0] redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_q;
    wire [7:0] redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_wraddr_i = 8'b11111111;
    wire [8:0] redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_a;
    wire [8:0] redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_b;
    logic [8:0] redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_o;
    wire [8:0] redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_q;
    reg [15:0] redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_inputreg0_q;
    reg [15:0] redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_outputreg0_q;
    wire redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_reset0;
    wire [15:0] redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_ia;
    wire [7:0] redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_aa;
    wire [7:0] redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_ab;
    wire [15:0] redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_iq;
    wire [15:0] redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_q;
    wire [7:0] redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_wraddr_i = 8'b11111111;
    wire [8:0] redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_a;
    wire [8:0] redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_b;
    logic [8:0] redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_o;
    wire [8:0] redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_q;
    reg [15:0] redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_inputreg0_q;
    reg [15:0] redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_outputreg0_q;
    wire redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_reset0;
    wire [15:0] redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_ia;
    wire [7:0] redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_aa;
    wire [7:0] redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_ab;
    wire [15:0] redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_iq;
    wire [15:0] redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_q;
    wire [7:0] redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_wraddr_i = 8'b11111111;
    wire [8:0] redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_a;
    wire [8:0] redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_b;
    logic [8:0] redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_o;
    wire [8:0] redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_q;
    reg [15:0] redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_inputreg0_q;
    reg [15:0] redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_outputreg0_q;
    wire redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_reset0;
    wire [15:0] redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_ia;
    wire [7:0] redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_aa;
    wire [7:0] redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_ab;
    wire [15:0] redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_iq;
    wire [15:0] redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_q;
    wire [7:0] redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_wraddr_i = 8'b11111111;
    wire [8:0] redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_a;
    wire [8:0] redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_b;
    logic [8:0] redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_o;
    wire [8:0] redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_q;
    reg [15:0] redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_inputreg0_q;
    reg [15:0] redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_outputreg0_q;
    wire redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_reset0;
    wire [15:0] redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_ia;
    wire [7:0] redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_aa;
    wire [7:0] redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_ab;
    wire [15:0] redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_iq;
    wire [15:0] redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_q;
    wire [7:0] redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_wraddr_i = 8'b11111111;
    wire [8:0] redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_a;
    wire [8:0] redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_b;
    logic [8:0] redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_o;
    wire [8:0] redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_q;
    reg [15:0] redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_inputreg0_q;
    reg [15:0] redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_outputreg0_q;
    wire redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_reset0;
    wire [15:0] redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_ia;
    wire [7:0] redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_aa;
    wire [7:0] redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_ab;
    wire [15:0] redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_iq;
    wire [15:0] redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_q;
    wire [7:0] redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_wraddr_i = 8'b11111111;
    wire [8:0] redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_a;
    wire [8:0] redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_b;
    logic [8:0] redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_o;
    wire [8:0] redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_q;
    reg [15:0] redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_inputreg0_q;
    reg [15:0] redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_outputreg0_q;
    wire redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_reset0;
    wire [15:0] redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_ia;
    wire [7:0] redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_aa;
    wire [7:0] redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_ab;
    wire [15:0] redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_iq;
    wire [15:0] redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_q;
    wire [7:0] redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_wraddr_i = 8'b11111111;
    wire [8:0] redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_a;
    wire [8:0] redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_b;
    logic [8:0] redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_o;
    wire [8:0] redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_q;
    reg [15:0] redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_inputreg0_q;
    reg [15:0] redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_outputreg0_q;
    wire redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_reset0;
    wire [15:0] redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_ia;
    wire [7:0] redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_aa;
    wire [7:0] redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_ab;
    wire [15:0] redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_iq;
    wire [15:0] redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_q;
    wire [7:0] redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_wraddr_i = 8'b11111111;
    wire [8:0] redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_a;
    wire [8:0] redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_b;
    logic [8:0] redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_o;
    wire [8:0] redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_q;
    reg [15:0] redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_inputreg0_q;
    reg [15:0] redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_outputreg0_q;
    wire redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_reset0;
    wire [15:0] redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_ia;
    wire [7:0] redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_aa;
    wire [7:0] redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_ab;
    wire [15:0] redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_iq;
    wire [15:0] redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_q;
    wire [7:0] redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_wraddr_i = 8'b11111111;
    wire [8:0] redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_a;
    wire [8:0] redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_b;
    logic [8:0] redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_o;
    wire [8:0] redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_q;
    reg [15:0] redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_inputreg0_q;
    reg [15:0] redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_outputreg0_q;
    wire redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_reset0;
    wire [15:0] redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_ia;
    wire [7:0] redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_aa;
    wire [7:0] redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_ab;
    wire [15:0] redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_iq;
    wire [15:0] redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_q;
    wire [7:0] redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_wraddr_i = 8'b11111111;
    wire [8:0] redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_a;
    wire [8:0] redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_b;
    logic [8:0] redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_o;
    wire [8:0] redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_q;
    reg [15:0] redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_inputreg0_q;
    reg [15:0] redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_outputreg0_q;
    wire redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_reset0;
    wire [15:0] redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_ia;
    wire [7:0] redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_aa;
    wire [7:0] redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_ab;
    wire [15:0] redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_iq;
    wire [15:0] redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_q;
    wire [7:0] redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_wraddr_i = 8'b11111111;
    wire [8:0] redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_a;
    wire [8:0] redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_b;
    logic [8:0] redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_o;
    wire [8:0] redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_q;
    reg [15:0] redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_inputreg0_q;
    reg [15:0] redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_outputreg0_q;
    wire redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_reset0;
    wire [15:0] redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_ia;
    wire [7:0] redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_aa;
    wire [7:0] redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_ab;
    wire [15:0] redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_iq;
    wire [15:0] redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_q;
    wire [7:0] redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_wraddr_i = 8'b11111111;
    wire [8:0] redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_a;
    wire [8:0] redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_b;
    logic [8:0] redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_o;
    wire [8:0] redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_q;
    reg [15:0] redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_inputreg0_q;
    reg [15:0] redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_outputreg0_q;
    wire redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_reset0;
    wire [15:0] redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_ia;
    wire [7:0] redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_aa;
    wire [7:0] redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_ab;
    wire [15:0] redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_iq;
    wire [15:0] redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_q;
    wire [7:0] redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_wraddr_i = 8'b11111111;
    wire [8:0] redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_a;
    wire [8:0] redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_b;
    logic [8:0] redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_o;
    wire [8:0] redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_q;
    reg [15:0] redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_inputreg0_q;
    reg [15:0] redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_outputreg0_q;
    wire redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_reset0;
    wire [15:0] redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_ia;
    wire [7:0] redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_aa;
    wire [7:0] redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_ab;
    wire [15:0] redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_iq;
    wire [15:0] redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_q;
    wire [7:0] redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_wraddr_i = 8'b11111111;
    wire [8:0] redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_a;
    wire [8:0] redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_b;
    logic [8:0] redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_o;
    wire [8:0] redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_q;
    reg [15:0] redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_inputreg0_q;
    reg [15:0] redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_outputreg0_q;
    wire redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_reset0;
    wire [15:0] redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_ia;
    wire [7:0] redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_aa;
    wire [7:0] redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_ab;
    wire [15:0] redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_iq;
    wire [15:0] redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_q;
    wire [7:0] redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_wraddr_i = 8'b11111111;
    wire [8:0] redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_a;
    wire [8:0] redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_b;
    logic [8:0] redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_o;
    wire [8:0] redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_q;
    reg [15:0] redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_inputreg0_q;
    reg [15:0] redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_outputreg0_q;
    wire redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_reset0;
    wire [15:0] redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_ia;
    wire [7:0] redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_aa;
    wire [7:0] redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_ab;
    wire [15:0] redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_iq;
    wire [15:0] redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_q;
    wire [7:0] redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_wraddr_i = 8'b11111111;
    wire [8:0] redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_a;
    wire [8:0] redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_b;
    logic [8:0] redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_o;
    wire [8:0] redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_q;
    reg [15:0] redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_inputreg0_q;
    reg [15:0] redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_outputreg0_q;
    wire redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_reset0;
    wire [15:0] redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_ia;
    wire [7:0] redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_aa;
    wire [7:0] redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_ab;
    wire [15:0] redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_iq;
    wire [15:0] redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_q;
    wire [7:0] redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_wraddr_i = 8'b11111111;
    wire [8:0] redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_a;
    wire [8:0] redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_b;
    logic [8:0] redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_o;
    wire [8:0] redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_q;
    reg [15:0] redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_inputreg0_q;
    reg [15:0] redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_outputreg0_q;
    wire redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_reset0;
    wire [15:0] redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_ia;
    wire [7:0] redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_aa;
    wire [7:0] redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_ab;
    wire [15:0] redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_iq;
    wire [15:0] redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_q;
    wire [7:0] redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_wraddr_i = 8'b11111111;
    wire [8:0] redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_a;
    wire [8:0] redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_b;
    logic [8:0] redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_o;
    wire [8:0] redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_q;
    reg [15:0] redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_inputreg0_q;
    reg [15:0] redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_outputreg0_q;
    wire redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_reset0;
    wire [15:0] redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_ia;
    wire [7:0] redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_aa;
    wire [7:0] redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_ab;
    wire [15:0] redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_iq;
    wire [15:0] redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_q;
    wire [7:0] redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_wraddr_i = 8'b11111111;
    wire [8:0] redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_a;
    wire [8:0] redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_b;
    logic [8:0] redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_o;
    wire [8:0] redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_q;
    reg [15:0] redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_inputreg0_q;
    reg [15:0] redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_outputreg0_q;
    wire redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_reset0;
    wire [15:0] redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_ia;
    wire [7:0] redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_aa;
    wire [7:0] redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_ab;
    wire [15:0] redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_iq;
    wire [15:0] redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_q;
    wire [7:0] redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_wraddr_i = 8'b11111111;
    wire [8:0] redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_a;
    wire [8:0] redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_b;
    logic [8:0] redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_o;
    wire [8:0] redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_q;
    reg [15:0] redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_inputreg0_q;
    reg [15:0] redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_outputreg0_q;
    wire redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_reset0;
    wire [15:0] redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_ia;
    wire [7:0] redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_aa;
    wire [7:0] redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_ab;
    wire [15:0] redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_iq;
    wire [15:0] redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_q;
    wire [7:0] redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_wraddr_i = 8'b11111111;
    wire [8:0] redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_a;
    wire [8:0] redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_b;
    logic [8:0] redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_o;
    wire [8:0] redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_q;
    reg [15:0] redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_inputreg0_q;
    reg [15:0] redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_outputreg0_q;
    wire redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_reset0;
    wire [15:0] redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_ia;
    wire [7:0] redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_aa;
    wire [7:0] redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_ab;
    wire [15:0] redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_iq;
    wire [15:0] redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_q;
    wire [7:0] redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_wraddr_i = 8'b11111111;
    wire [8:0] redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_a;
    wire [8:0] redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_b;
    logic [8:0] redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_o;
    wire [8:0] redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_q;
    reg [15:0] redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_inputreg0_q;
    reg [15:0] redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_outputreg0_q;
    wire redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_reset0;
    wire [15:0] redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_ia;
    wire [7:0] redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_aa;
    wire [7:0] redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_ab;
    wire [15:0] redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_iq;
    wire [15:0] redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_q;
    wire [7:0] redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_wraddr_i = 8'b11111111;
    wire [8:0] redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_a;
    wire [8:0] redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_b;
    logic [8:0] redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_o;
    wire [8:0] redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_q;
    reg [15:0] redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_inputreg0_q;
    reg [15:0] redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_outputreg0_q;
    wire redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_reset0;
    wire [15:0] redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_ia;
    wire [7:0] redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_aa;
    wire [7:0] redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_ab;
    wire [15:0] redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_iq;
    wire [15:0] redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_q;
    wire [7:0] redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_wraddr_i = 8'b11111111;
    wire [8:0] redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_a;
    wire [8:0] redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_b;
    logic [8:0] redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_o;
    wire [8:0] redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_q;
    reg [15:0] redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_inputreg0_q;
    reg [15:0] redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_outputreg0_q;
    wire redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_reset0;
    wire [15:0] redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_ia;
    wire [7:0] redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_aa;
    wire [7:0] redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_ab;
    wire [15:0] redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_iq;
    wire [15:0] redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_q;
    wire [7:0] redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_wraddr_i = 8'b11111111;
    wire [8:0] redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_a;
    wire [8:0] redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_b;
    logic [8:0] redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_o;
    wire [8:0] redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_q;
    reg [15:0] redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_inputreg0_q;
    reg [15:0] redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_outputreg0_q;
    wire redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_reset0;
    wire [15:0] redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_ia;
    wire [7:0] redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_aa;
    wire [7:0] redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_ab;
    wire [15:0] redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_iq;
    wire [15:0] redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_q;
    wire [7:0] redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_wraddr_i = 8'b11111111;
    wire [8:0] redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_a;
    wire [8:0] redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_b;
    logic [8:0] redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_o;
    wire [8:0] redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_q;
    reg [15:0] redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_inputreg0_q;
    reg [15:0] redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_outputreg0_q;
    wire redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_reset0;
    wire [15:0] redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_ia;
    wire [7:0] redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_aa;
    wire [7:0] redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_ab;
    wire [15:0] redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_iq;
    wire [15:0] redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_q;
    wire [7:0] redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_wraddr_i = 8'b11111111;
    wire [8:0] redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_a;
    wire [8:0] redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_b;
    logic [8:0] redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_o;
    wire [8:0] redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_q;
    reg [15:0] redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_inputreg0_q;
    reg [15:0] redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_outputreg0_q;
    wire redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_reset0;
    wire [15:0] redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_ia;
    wire [7:0] redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_aa;
    wire [7:0] redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_ab;
    wire [15:0] redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_iq;
    wire [15:0] redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_q;
    wire [7:0] redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_wraddr_i = 8'b11111111;
    wire [8:0] redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_a;
    wire [8:0] redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_b;
    logic [8:0] redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_o;
    wire [8:0] redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_q;
    reg [15:0] redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_inputreg0_q;
    reg [15:0] redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_outputreg0_q;
    wire redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_reset0;
    wire [15:0] redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_ia;
    wire [7:0] redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_aa;
    wire [7:0] redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_ab;
    wire [15:0] redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_iq;
    wire [15:0] redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_q;
    wire [7:0] redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_wraddr_i = 8'b11111111;
    wire [8:0] redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_a;
    wire [8:0] redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_b;
    logic [8:0] redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_o;
    wire [8:0] redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_q;
    reg [15:0] redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_inputreg0_q;
    reg [15:0] redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_outputreg0_q;
    wire redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_reset0;
    wire [15:0] redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_ia;
    wire [7:0] redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_aa;
    wire [7:0] redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_ab;
    wire [15:0] redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_iq;
    wire [15:0] redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_q;
    wire [7:0] redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_wraddr_i = 8'b11111111;
    wire [8:0] redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_a;
    wire [8:0] redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_b;
    logic [8:0] redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_o;
    wire [8:0] redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_q;
    reg [15:0] redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_inputreg0_q;
    reg [15:0] redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_outputreg0_q;
    wire redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_reset0;
    wire [15:0] redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_ia;
    wire [7:0] redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_aa;
    wire [7:0] redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_ab;
    wire [15:0] redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_iq;
    wire [15:0] redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_q;
    wire [7:0] redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_wraddr_i = 8'b11111111;
    wire [8:0] redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_a;
    wire [8:0] redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_b;
    logic [8:0] redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_o;
    wire [8:0] redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_q;
    reg [15:0] redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_inputreg0_q;
    reg [15:0] redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_outputreg0_q;
    wire redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_reset0;
    wire [15:0] redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_ia;
    wire [7:0] redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_aa;
    wire [7:0] redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_ab;
    wire [15:0] redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_iq;
    wire [15:0] redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_q;
    wire [7:0] redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_wraddr_i = 8'b11111111;
    wire [8:0] redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_a;
    wire [8:0] redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_b;
    logic [8:0] redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_o;
    wire [8:0] redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_q;
    reg [15:0] redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_inputreg0_q;
    reg [15:0] redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_outputreg0_q;
    wire redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_reset0;
    wire [15:0] redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_ia;
    wire [7:0] redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_aa;
    wire [7:0] redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_ab;
    wire [15:0] redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_iq;
    wire [15:0] redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_q;
    wire [7:0] redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_wraddr_i = 8'b11111111;
    wire [8:0] redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_a;
    wire [8:0] redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_b;
    logic [8:0] redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_o;
    wire [8:0] redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_q;
    reg [15:0] redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_inputreg0_q;
    reg [15:0] redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_outputreg0_q;
    wire redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_reset0;
    wire [15:0] redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_ia;
    wire [7:0] redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_aa;
    wire [7:0] redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_ab;
    wire [15:0] redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_iq;
    wire [15:0] redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_q;
    wire [7:0] redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_wraddr_i = 8'b11111111;
    wire [8:0] redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_a;
    wire [8:0] redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_b;
    logic [8:0] redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_o;
    wire [8:0] redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_q;
    reg [15:0] redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_inputreg0_q;
    reg [15:0] redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_outputreg0_q;
    wire redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_reset0;
    wire [15:0] redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_ia;
    wire [7:0] redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_aa;
    wire [7:0] redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_ab;
    wire [15:0] redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_iq;
    wire [15:0] redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_q;
    wire [7:0] redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_wraddr_i = 8'b11111111;
    wire [8:0] redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_a;
    wire [8:0] redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_b;
    logic [8:0] redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_o;
    wire [8:0] redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_q;
    reg [15:0] redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_inputreg0_q;
    reg [15:0] redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_outputreg0_q;
    wire redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_reset0;
    wire [15:0] redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_ia;
    wire [7:0] redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_aa;
    wire [7:0] redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_ab;
    wire [15:0] redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_iq;
    wire [15:0] redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_q;
    wire [7:0] redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_wraddr_i = 8'b11111111;
    wire [8:0] redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_a;
    wire [8:0] redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_b;
    logic [8:0] redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_o;
    wire [8:0] redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_q;
    reg [15:0] redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_inputreg0_q;
    reg [15:0] redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_outputreg0_q;
    wire redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_reset0;
    wire [15:0] redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_ia;
    wire [7:0] redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_aa;
    wire [7:0] redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_ab;
    wire [15:0] redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_iq;
    wire [15:0] redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_q;
    wire [7:0] redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_wraddr_i = 8'b11111111;
    wire [8:0] redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_a;
    wire [8:0] redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_b;
    logic [8:0] redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_o;
    wire [8:0] redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_q;
    reg [15:0] redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_inputreg0_q;
    reg [15:0] redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_outputreg0_q;
    wire redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_reset0;
    wire [15:0] redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_ia;
    wire [7:0] redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_aa;
    wire [7:0] redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_ab;
    wire [15:0] redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_iq;
    wire [15:0] redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_q;
    wire [7:0] redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_wraddr_i = 8'b11111111;
    wire [8:0] redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_a;
    wire [8:0] redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_b;
    logic [8:0] redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_o;
    wire [8:0] redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_q;
    reg [15:0] redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_inputreg0_q;
    reg [15:0] redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_outputreg0_q;
    wire redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_reset0;
    wire [15:0] redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_ia;
    wire [7:0] redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_aa;
    wire [7:0] redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_ab;
    wire [15:0] redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_iq;
    wire [15:0] redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_q;
    wire [7:0] redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_wraddr_i = 8'b11111111;
    wire [8:0] redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_a;
    wire [8:0] redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_b;
    logic [8:0] redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_o;
    wire [8:0] redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_q;
    reg [15:0] redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_inputreg0_q;
    reg [15:0] redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_outputreg0_q;
    wire redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_reset0;
    wire [15:0] redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_ia;
    wire [7:0] redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_aa;
    wire [7:0] redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_ab;
    wire [15:0] redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_iq;
    wire [15:0] redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_q;
    wire [7:0] redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_wraddr_i = 8'b11111111;
    wire [8:0] redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_a;
    wire [8:0] redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_b;
    logic [8:0] redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_o;
    wire [8:0] redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_q;
    reg [15:0] redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_inputreg0_q;
    reg [15:0] redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_outputreg0_q;
    wire redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_reset0;
    wire [15:0] redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_ia;
    wire [7:0] redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_aa;
    wire [7:0] redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_ab;
    wire [15:0] redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_iq;
    wire [15:0] redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_q;
    wire [7:0] redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_wraddr_i = 8'b11111111;
    wire [8:0] redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_a;
    wire [8:0] redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_b;
    logic [8:0] redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_o;
    wire [8:0] redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_q;
    reg [15:0] redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_inputreg0_q;
    reg [15:0] redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_outputreg0_q;
    wire redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_reset0;
    wire [15:0] redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_ia;
    wire [7:0] redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_aa;
    wire [7:0] redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_ab;
    wire [15:0] redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_iq;
    wire [15:0] redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_q;
    wire [7:0] redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_wraddr_i = 8'b11111111;
    wire [8:0] redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_a;
    wire [8:0] redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_b;
    logic [8:0] redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_o;
    wire [8:0] redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_q;
    reg [15:0] redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_inputreg0_q;
    reg [15:0] redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_outputreg0_q;
    wire redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_reset0;
    wire [15:0] redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_ia;
    wire [7:0] redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_aa;
    wire [7:0] redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_ab;
    wire [15:0] redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_iq;
    wire [15:0] redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_q;
    wire [7:0] redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_wraddr_i = 8'b11111111;
    wire [8:0] redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_a;
    wire [8:0] redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_b;
    logic [8:0] redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_o;
    wire [8:0] redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_q;
    reg [15:0] redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_inputreg0_q;
    reg [15:0] redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_outputreg0_q;
    wire redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_reset0;
    wire [15:0] redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_ia;
    wire [7:0] redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_aa;
    wire [7:0] redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_ab;
    wire [15:0] redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_iq;
    wire [15:0] redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_q;
    wire [7:0] redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_wraddr_i = 8'b11111111;
    wire [8:0] redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_a;
    wire [8:0] redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_b;
    logic [8:0] redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_o;
    wire [8:0] redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_q;
    reg [15:0] redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_inputreg0_q;
    reg [15:0] redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_outputreg0_q;
    wire redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_reset0;
    wire [15:0] redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_ia;
    wire [7:0] redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_aa;
    wire [7:0] redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_ab;
    wire [15:0] redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_iq;
    wire [15:0] redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_q;
    wire [7:0] redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_wraddr_i = 8'b11111111;
    wire [8:0] redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_a;
    wire [8:0] redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_b;
    logic [8:0] redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_o;
    wire [8:0] redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_q;
    reg [15:0] redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_inputreg0_q;
    reg [15:0] redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_outputreg0_q;
    wire redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_reset0;
    wire [15:0] redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_ia;
    wire [7:0] redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_aa;
    wire [7:0] redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_ab;
    wire [15:0] redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_iq;
    wire [15:0] redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_q;
    wire [7:0] redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_wraddr_i = 8'b11111111;
    wire [8:0] redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_a;
    wire [8:0] redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_b;
    logic [8:0] redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_o;
    wire [8:0] redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_q;
    reg [15:0] redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_inputreg0_q;
    reg [15:0] redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_outputreg0_q;
    wire redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_reset0;
    wire [15:0] redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_ia;
    wire [7:0] redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_aa;
    wire [7:0] redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_ab;
    wire [15:0] redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_iq;
    wire [15:0] redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_q;
    wire [7:0] redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_wraddr_i = 8'b11111111;
    wire [8:0] redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_a;
    wire [8:0] redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_b;
    logic [8:0] redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_o;
    wire [8:0] redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_q;
    reg [15:0] redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_inputreg0_q;
    reg [15:0] redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_outputreg0_q;
    wire redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_reset0;
    wire [15:0] redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_ia;
    wire [7:0] redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_aa;
    wire [7:0] redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_ab;
    wire [15:0] redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_iq;
    wire [15:0] redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_q;
    wire [7:0] redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_wraddr_i = 8'b11111111;
    wire [8:0] redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_a;
    wire [8:0] redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_b;
    logic [8:0] redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_o;
    wire [8:0] redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_q;
    reg [15:0] redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_inputreg0_q;
    reg [15:0] redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_outputreg0_q;
    wire redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_reset0;
    wire [15:0] redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_ia;
    wire [7:0] redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_aa;
    wire [7:0] redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_ab;
    wire [15:0] redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_iq;
    wire [15:0] redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_q;
    wire [7:0] redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_wraddr_i = 8'b11111111;
    wire [8:0] redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_a;
    wire [8:0] redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_b;
    logic [8:0] redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_o;
    wire [8:0] redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_q;
    reg [15:0] redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_inputreg0_q;
    reg [15:0] redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_outputreg0_q;
    wire redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_reset0;
    wire [15:0] redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_ia;
    wire [7:0] redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_aa;
    wire [7:0] redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_ab;
    wire [15:0] redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_iq;
    wire [15:0] redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_q;
    wire [7:0] redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_wraddr_i = 8'b11111111;
    wire [8:0] redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_a;
    wire [8:0] redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_b;
    logic [8:0] redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_o;
    wire [8:0] redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_q;
    reg [15:0] redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_inputreg0_q;
    reg [15:0] redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_outputreg0_q;
    wire redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_reset0;
    wire [15:0] redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_ia;
    wire [7:0] redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_aa;
    wire [7:0] redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_ab;
    wire [15:0] redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_iq;
    wire [15:0] redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_q;
    wire [7:0] redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_wraddr_i = 8'b11111111;
    wire [8:0] redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_a;
    wire [8:0] redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_b;
    logic [8:0] redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_o;
    wire [8:0] redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_q;
    reg [15:0] redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_inputreg0_q;
    reg [15:0] redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_outputreg0_q;
    wire redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_reset0;
    wire [15:0] redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_ia;
    wire [7:0] redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_aa;
    wire [7:0] redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_ab;
    wire [15:0] redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_iq;
    wire [15:0] redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_q;
    wire [7:0] redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_wraddr_i = 8'b11111111;
    wire [8:0] redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_a;
    wire [8:0] redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_b;
    logic [8:0] redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_o;
    wire [8:0] redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_q;
    reg [15:0] redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_inputreg0_q;
    reg [15:0] redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_outputreg0_q;
    wire redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_reset0;
    wire [15:0] redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_ia;
    wire [7:0] redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_aa;
    wire [7:0] redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_ab;
    wire [15:0] redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_iq;
    wire [15:0] redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_q;
    wire [7:0] redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_wraddr_i = 8'b11111111;
    wire [8:0] redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_a;
    wire [8:0] redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_b;
    logic [8:0] redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_o;
    wire [8:0] redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_q;
    reg [15:0] redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_inputreg0_q;
    reg [15:0] redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_outputreg0_q;
    wire redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_reset0;
    wire [15:0] redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_ia;
    wire [7:0] redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_aa;
    wire [7:0] redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_ab;
    wire [15:0] redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_iq;
    wire [15:0] redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_q;
    wire [7:0] redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_wraddr_i = 8'b11111111;
    wire [8:0] redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_a;
    wire [8:0] redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_b;
    logic [8:0] redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_o;
    wire [8:0] redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_q;
    reg [15:0] redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_inputreg0_q;
    reg [15:0] redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_outputreg0_q;
    wire redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_reset0;
    wire [15:0] redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_ia;
    wire [7:0] redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_aa;
    wire [7:0] redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_ab;
    wire [15:0] redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_iq;
    wire [15:0] redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_q;
    wire [7:0] redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_wraddr_i = 8'b11111111;
    wire [8:0] redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_a;
    wire [8:0] redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_b;
    logic [8:0] redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_o;
    wire [8:0] redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_q;
    reg [15:0] redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_inputreg0_q;
    reg [15:0] redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_outputreg0_q;
    wire redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_reset0;
    wire [15:0] redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_ia;
    wire [7:0] redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_aa;
    wire [7:0] redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_ab;
    wire [15:0] redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_iq;
    wire [15:0] redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_q;
    wire [7:0] redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_wraddr_i = 8'b11111111;
    wire [8:0] redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_a;
    wire [8:0] redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_b;
    logic [8:0] redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_o;
    wire [8:0] redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_q;
    reg [15:0] redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_inputreg0_q;
    reg [15:0] redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_outputreg0_q;
    wire redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_reset0;
    wire [15:0] redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_ia;
    wire [7:0] redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_aa;
    wire [7:0] redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_ab;
    wire [15:0] redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_iq;
    wire [15:0] redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_q;
    wire [7:0] redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_wraddr_i = 8'b11111111;
    wire [8:0] redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_a;
    wire [8:0] redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_b;
    logic [8:0] redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_o;
    wire [8:0] redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_q;
    reg [15:0] redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_inputreg0_q;
    reg [15:0] redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_outputreg0_q;
    wire redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_reset0;
    wire [15:0] redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_ia;
    wire [7:0] redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_aa;
    wire [7:0] redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_ab;
    wire [15:0] redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_iq;
    wire [15:0] redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_q;
    wire [7:0] redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_wraddr_i = 8'b11111111;
    wire [8:0] redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_a;
    wire [8:0] redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_b;
    logic [8:0] redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_o;
    wire [8:0] redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_q;
    reg [15:0] redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_inputreg0_q;
    reg [15:0] redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_outputreg0_q;
    wire redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_reset0;
    wire [15:0] redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_ia;
    wire [7:0] redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_aa;
    wire [7:0] redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_ab;
    wire [15:0] redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_iq;
    wire [15:0] redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_q;
    wire [7:0] redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_wraddr_i = 8'b11111111;
    wire [8:0] redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_a;
    wire [8:0] redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_b;
    logic [8:0] redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_o;
    wire [8:0] redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_q;
    reg [15:0] redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_inputreg0_q;
    reg [15:0] redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_outputreg0_q;
    wire redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_reset0;
    wire [15:0] redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_ia;
    wire [7:0] redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_aa;
    wire [7:0] redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_ab;
    wire [15:0] redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_iq;
    wire [15:0] redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_q;
    wire [7:0] redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_wraddr_i = 8'b11111111;
    wire [8:0] redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_a;
    wire [8:0] redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_b;
    logic [8:0] redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_o;
    wire [8:0] redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_q;
    reg [15:0] redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_inputreg0_q;
    reg [15:0] redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_outputreg0_q;
    wire redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_reset0;
    wire [15:0] redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_ia;
    wire [7:0] redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_aa;
    wire [7:0] redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_ab;
    wire [15:0] redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_iq;
    wire [15:0] redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_q;
    wire [7:0] redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_wraddr_i = 8'b11111111;
    wire [8:0] redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_a;
    wire [8:0] redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_b;
    logic [8:0] redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_o;
    wire [8:0] redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_q;
    reg [15:0] redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_inputreg0_q;
    reg [15:0] redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_outputreg0_q;
    wire redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_reset0;
    wire [15:0] redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_ia;
    wire [7:0] redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_aa;
    wire [7:0] redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_ab;
    wire [15:0] redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_iq;
    wire [15:0] redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_q;
    wire [7:0] redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_wraddr_i = 8'b11111111;
    wire [8:0] redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_a;
    wire [8:0] redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_b;
    logic [8:0] redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_o;
    wire [8:0] redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_q;
    reg [15:0] redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_inputreg0_q;
    reg [15:0] redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_outputreg0_q;
    wire redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_reset0;
    wire [15:0] redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_ia;
    wire [7:0] redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_aa;
    wire [7:0] redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_ab;
    wire [15:0] redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_iq;
    wire [15:0] redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_q;
    wire [7:0] redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_wraddr_i = 8'b11111111;
    wire [8:0] redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_a;
    wire [8:0] redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_b;
    logic [8:0] redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_o;
    wire [8:0] redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_q;
    reg [15:0] redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_inputreg0_q;
    reg [15:0] redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_outputreg0_q;
    wire redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_reset0;
    wire [15:0] redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_ia;
    wire [7:0] redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_aa;
    wire [7:0] redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_ab;
    wire [15:0] redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_iq;
    wire [15:0] redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_q;
    wire [7:0] redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_wraddr_i = 8'b11111111;
    wire [8:0] redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_a;
    wire [8:0] redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_b;
    logic [8:0] redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_o;
    wire [8:0] redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_q;
    reg [15:0] redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_inputreg0_q;
    reg [15:0] redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_outputreg0_q;
    wire redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_reset0;
    wire [15:0] redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_ia;
    wire [7:0] redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_aa;
    wire [7:0] redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_ab;
    wire [15:0] redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_iq;
    wire [15:0] redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_q;
    wire [7:0] redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_wraddr_i = 8'b11111111;
    wire [8:0] redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_a;
    wire [8:0] redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_b;
    logic [8:0] redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_o;
    wire [8:0] redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_q;
    reg [15:0] redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_inputreg0_q;
    reg [15:0] redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_outputreg0_q;
    wire redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_reset0;
    wire [15:0] redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_ia;
    wire [7:0] redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_aa;
    wire [7:0] redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_ab;
    wire [15:0] redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_iq;
    wire [15:0] redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_q;
    wire [7:0] redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_wraddr_i = 8'b11111111;
    wire [8:0] redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_a;
    wire [8:0] redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_b;
    logic [8:0] redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_o;
    wire [8:0] redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_q;
    reg [15:0] redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_inputreg0_q;
    reg [15:0] redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_outputreg0_q;
    wire redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_reset0;
    wire [15:0] redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_ia;
    wire [7:0] redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_aa;
    wire [7:0] redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_ab;
    wire [15:0] redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_iq;
    wire [15:0] redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_q;
    wire [7:0] redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_wraddr_i = 8'b11111111;
    wire [8:0] redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_a;
    wire [8:0] redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_b;
    logic [8:0] redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_o;
    wire [8:0] redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_q;
    reg [15:0] redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_inputreg0_q;
    reg [15:0] redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_outputreg0_q;
    wire redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_reset0;
    wire [15:0] redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_ia;
    wire [7:0] redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_aa;
    wire [7:0] redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_ab;
    wire [15:0] redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_iq;
    wire [15:0] redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_q;
    wire [7:0] redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_wraddr_i = 8'b11111111;
    wire [8:0] redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_a;
    wire [8:0] redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_b;
    logic [8:0] redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_o;
    wire [8:0] redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_q;
    reg [15:0] redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_inputreg0_q;
    reg [15:0] redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_outputreg0_q;
    wire redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_reset0;
    wire [15:0] redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_ia;
    wire [7:0] redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_aa;
    wire [7:0] redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_ab;
    wire [15:0] redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_iq;
    wire [15:0] redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_q;
    wire [7:0] redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_wraddr_i = 8'b11111111;
    wire [8:0] redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_a;
    wire [8:0] redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_b;
    logic [8:0] redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_o;
    wire [8:0] redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_q;
    reg [15:0] redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_inputreg0_q;
    reg [15:0] redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_outputreg0_q;
    wire redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_reset0;
    wire [15:0] redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_ia;
    wire [7:0] redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_aa;
    wire [7:0] redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_ab;
    wire [15:0] redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_iq;
    wire [15:0] redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_q;
    wire [7:0] redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_wraddr_i = 8'b11111111;
    wire [8:0] redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_a;
    wire [8:0] redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_b;
    logic [8:0] redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_o;
    wire [8:0] redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_q;
    reg [15:0] redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_inputreg0_q;
    reg [15:0] redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_outputreg0_q;
    wire redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_reset0;
    wire [15:0] redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_ia;
    wire [7:0] redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_aa;
    wire [7:0] redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_ab;
    wire [15:0] redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_iq;
    wire [15:0] redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_q;
    wire [7:0] redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_wraddr_i = 8'b11111111;
    wire [8:0] redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_a;
    wire [8:0] redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_b;
    logic [8:0] redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_o;
    wire [8:0] redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_q;
    reg [15:0] redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_inputreg0_q;
    reg [15:0] redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_outputreg0_q;
    wire redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_reset0;
    wire [15:0] redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_ia;
    wire [7:0] redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_aa;
    wire [7:0] redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_ab;
    wire [15:0] redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_iq;
    wire [15:0] redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_q;
    wire [7:0] redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_wraddr_i = 8'b11111111;
    wire [8:0] redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_a;
    wire [8:0] redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_b;
    logic [8:0] redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_o;
    wire [8:0] redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_q;
    reg [15:0] redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_inputreg0_q;
    reg [15:0] redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_outputreg0_q;
    wire redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_reset0;
    wire [15:0] redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_ia;
    wire [7:0] redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_aa;
    wire [7:0] redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_ab;
    wire [15:0] redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_iq;
    wire [15:0] redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_q;
    wire [7:0] redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_wraddr_i = 8'b11111111;
    wire [8:0] redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_a;
    wire [8:0] redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_b;
    logic [8:0] redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_o;
    wire [8:0] redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_q;
    reg [15:0] redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_inputreg0_q;
    reg [15:0] redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_outputreg0_q;
    wire redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_reset0;
    wire [15:0] redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_ia;
    wire [7:0] redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_aa;
    wire [7:0] redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_ab;
    wire [15:0] redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_iq;
    wire [15:0] redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_q;
    wire [7:0] redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_wraddr_i = 8'b11111111;
    wire [8:0] redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_a;
    wire [8:0] redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_b;
    logic [8:0] redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_o;
    wire [8:0] redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_q;
    reg [15:0] redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_inputreg0_q;
    reg [15:0] redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_outputreg0_q;
    wire redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_reset0;
    wire [15:0] redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_ia;
    wire [7:0] redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_aa;
    wire [7:0] redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_ab;
    wire [15:0] redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_iq;
    wire [15:0] redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_q;
    wire [7:0] redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_wraddr_i = 8'b11111111;
    wire [8:0] redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_a;
    wire [8:0] redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_b;
    logic [8:0] redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_o;
    wire [8:0] redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_q;
    reg [15:0] redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_inputreg0_q;
    reg [15:0] redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_outputreg0_q;
    wire redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_reset0;
    wire [15:0] redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_ia;
    wire [7:0] redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_aa;
    wire [7:0] redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_ab;
    wire [15:0] redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_iq;
    wire [15:0] redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_q;
    wire [7:0] redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_wraddr_i = 8'b11111111;
    wire [8:0] redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_a;
    wire [8:0] redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_b;
    logic [8:0] redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_o;
    wire [8:0] redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_q;
    reg [15:0] redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_inputreg0_q;
    reg [15:0] redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_outputreg0_q;
    wire redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_reset0;
    wire [15:0] redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_ia;
    wire [7:0] redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_aa;
    wire [7:0] redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_ab;
    wire [15:0] redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_iq;
    wire [15:0] redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_q;
    wire [7:0] redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_wraddr_i = 8'b11111111;
    wire [8:0] redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_a;
    wire [8:0] redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_b;
    logic [8:0] redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_o;
    wire [8:0] redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_q;
    reg [15:0] redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_inputreg0_q;
    reg [15:0] redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_outputreg0_q;
    wire redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_reset0;
    wire [15:0] redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_ia;
    wire [7:0] redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_aa;
    wire [7:0] redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_ab;
    wire [15:0] redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_iq;
    wire [15:0] redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_q;
    wire [7:0] redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_wraddr_i = 8'b11111111;
    wire [8:0] redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_a;
    wire [8:0] redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_b;
    logic [8:0] redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_o;
    wire [8:0] redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_q;
    reg [15:0] redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_inputreg0_q;
    reg [15:0] redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_outputreg0_q;
    wire redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_reset0;
    wire [15:0] redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_ia;
    wire [7:0] redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_aa;
    wire [7:0] redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_ab;
    wire [15:0] redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_iq;
    wire [15:0] redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_q;
    wire [7:0] redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_wraddr_i = 8'b11111111;
    wire [8:0] redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_a;
    wire [8:0] redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_b;
    logic [8:0] redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_o;
    wire [8:0] redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_q;
    reg [15:0] redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_inputreg0_q;
    reg [15:0] redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_outputreg0_q;
    wire redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_reset0;
    wire [15:0] redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_ia;
    wire [7:0] redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_aa;
    wire [7:0] redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_ab;
    wire [15:0] redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_iq;
    wire [15:0] redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_q;
    wire [7:0] redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_wraddr_i = 8'b11111111;
    wire [8:0] redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_a;
    wire [8:0] redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_b;
    logic [8:0] redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_o;
    wire [8:0] redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_q;
    reg [15:0] redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_inputreg0_q;
    reg [15:0] redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_outputreg0_q;
    wire redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_reset0;
    wire [15:0] redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_ia;
    wire [7:0] redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_aa;
    wire [7:0] redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_ab;
    wire [15:0] redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_iq;
    wire [15:0] redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_q;
    wire [7:0] redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_wraddr_i = 8'b11111111;
    wire [8:0] redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_a;
    wire [8:0] redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_b;
    logic [8:0] redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_o;
    wire [8:0] redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_q;
    reg [15:0] redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_inputreg0_q;
    reg [15:0] redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_outputreg0_q;
    wire redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_reset0;
    wire [15:0] redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_ia;
    wire [7:0] redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_aa;
    wire [7:0] redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_ab;
    wire [15:0] redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_iq;
    wire [15:0] redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_q;
    wire [7:0] redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_wraddr_i = 8'b11111111;
    wire [8:0] redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_a;
    wire [8:0] redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_b;
    logic [8:0] redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_o;
    wire [8:0] redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_q;
    reg [15:0] redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_inputreg0_q;
    reg [15:0] redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_outputreg0_q;
    wire redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_reset0;
    wire [15:0] redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_ia;
    wire [7:0] redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_aa;
    wire [7:0] redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_ab;
    wire [15:0] redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_iq;
    wire [15:0] redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_q;
    wire [7:0] redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_wraddr_i = 8'b11111111;
    wire [8:0] redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_a;
    wire [8:0] redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_b;
    logic [8:0] redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_o;
    wire [8:0] redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_q;
    reg [15:0] redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_inputreg0_q;
    reg [15:0] redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_outputreg0_q;
    wire redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_reset0;
    wire [15:0] redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_ia;
    wire [7:0] redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_aa;
    wire [7:0] redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_ab;
    wire [15:0] redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_iq;
    wire [15:0] redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_q;
    wire [7:0] redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_wraddr_i = 8'b11111111;
    wire [8:0] redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_a;
    wire [8:0] redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_b;
    logic [8:0] redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_o;
    wire [8:0] redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_q;
    reg [15:0] redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_inputreg0_q;
    reg [15:0] redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_outputreg0_q;
    wire redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_reset0;
    wire [15:0] redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_ia;
    wire [7:0] redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_aa;
    wire [7:0] redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_ab;
    wire [15:0] redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_iq;
    wire [15:0] redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_q;
    wire [7:0] redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_wraddr_i = 8'b11111111;
    wire [8:0] redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_a;
    wire [8:0] redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_b;
    logic [8:0] redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_o;
    wire [8:0] redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_q;
    reg [15:0] redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_inputreg0_q;
    reg [15:0] redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_outputreg0_q;
    wire redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_reset0;
    wire [15:0] redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_ia;
    wire [7:0] redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_aa;
    wire [7:0] redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_ab;
    wire [15:0] redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_iq;
    wire [15:0] redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_q;
    wire [7:0] redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_wraddr_i = 8'b11111111;
    wire [8:0] redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_a;
    wire [8:0] redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_b;
    logic [8:0] redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_o;
    wire [8:0] redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_q;
    reg [15:0] redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_inputreg0_q;
    reg [15:0] redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_outputreg0_q;
    wire redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_reset0;
    wire [15:0] redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_ia;
    wire [7:0] redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_aa;
    wire [7:0] redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_ab;
    wire [15:0] redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_iq;
    wire [15:0] redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_q;
    wire [7:0] redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_wraddr_i = 8'b11111111;
    wire [8:0] redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_a;
    wire [8:0] redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_b;
    logic [8:0] redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_o;
    wire [8:0] redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_q;
    reg [15:0] redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_inputreg0_q;
    reg [15:0] redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_outputreg0_q;
    wire redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_reset0;
    wire [15:0] redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_ia;
    wire [7:0] redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_aa;
    wire [7:0] redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_ab;
    wire [15:0] redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_iq;
    wire [15:0] redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_q;
    wire [7:0] redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_wraddr_i = 8'b11111111;
    wire [8:0] redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_a;
    wire [8:0] redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_b;
    logic [8:0] redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_o;
    wire [8:0] redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_q;
    reg [15:0] redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_inputreg0_q;
    reg [15:0] redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_outputreg0_q;
    wire redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_reset0;
    wire [15:0] redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_ia;
    wire [7:0] redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_aa;
    wire [7:0] redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_ab;
    wire [15:0] redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_iq;
    wire [15:0] redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_q;
    wire [7:0] redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_wraddr_i = 8'b11111111;
    wire [8:0] redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_a;
    wire [8:0] redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_b;
    logic [8:0] redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_o;
    wire [8:0] redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_q;
    reg [15:0] redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_inputreg0_q;
    reg [15:0] redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_outputreg0_q;
    wire redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_reset0;
    wire [15:0] redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_ia;
    wire [7:0] redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_aa;
    wire [7:0] redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_ab;
    wire [15:0] redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_iq;
    wire [15:0] redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_q;
    wire [7:0] redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_wraddr_i = 8'b11111111;
    wire [8:0] redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_a;
    wire [8:0] redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_b;
    logic [8:0] redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_o;
    wire [8:0] redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_q;
    reg [15:0] redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_inputreg0_q;
    reg [15:0] redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_outputreg0_q;
    wire redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_reset0;
    wire [15:0] redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_ia;
    wire [7:0] redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_aa;
    wire [7:0] redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_ab;
    wire [15:0] redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_iq;
    wire [15:0] redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_q;
    wire [7:0] redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_wraddr_i = 8'b11111111;
    wire [8:0] redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_a;
    wire [8:0] redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_b;
    logic [8:0] redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_o;
    wire [8:0] redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_q;
    reg [15:0] redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_inputreg0_q;
    reg [15:0] redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_outputreg0_q;
    wire redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_reset0;
    wire [15:0] redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_ia;
    wire [7:0] redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_aa;
    wire [7:0] redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_ab;
    wire [15:0] redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_iq;
    wire [15:0] redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_q;
    wire [7:0] redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_wraddr_i = 8'b11111111;
    wire [8:0] redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_a;
    wire [8:0] redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_b;
    logic [8:0] redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_o;
    wire [8:0] redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_q;
    reg [15:0] redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_inputreg0_q;
    reg [15:0] redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_outputreg0_q;
    wire redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_reset0;
    wire [15:0] redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_ia;
    wire [7:0] redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_aa;
    wire [7:0] redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_ab;
    wire [15:0] redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_iq;
    wire [15:0] redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_q;
    wire [7:0] redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_wraddr_i = 8'b11111111;
    wire [8:0] redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_a;
    wire [8:0] redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_b;
    logic [8:0] redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_o;
    wire [8:0] redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_q;
    reg [15:0] redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_inputreg0_q;
    reg [15:0] redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_outputreg0_q;
    wire redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_reset0;
    wire [15:0] redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_ia;
    wire [7:0] redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_aa;
    wire [7:0] redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_ab;
    wire [15:0] redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_iq;
    wire [15:0] redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_q;
    wire [7:0] redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_wraddr_i = 8'b11111111;
    wire [8:0] redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_a;
    wire [8:0] redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_b;
    logic [8:0] redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_o;
    wire [8:0] redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_q;
    reg [15:0] redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_inputreg0_q;
    reg [15:0] redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_outputreg0_q;
    wire redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_reset0;
    wire [15:0] redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_ia;
    wire [7:0] redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_aa;
    wire [7:0] redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_ab;
    wire [15:0] redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_iq;
    wire [15:0] redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_q;
    wire [7:0] redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_wraddr_i = 8'b11111111;
    wire [8:0] redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_a;
    wire [8:0] redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_b;
    logic [8:0] redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_o;
    wire [8:0] redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_q;
    reg [15:0] redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_inputreg0_q;
    reg [15:0] redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_outputreg0_q;
    wire redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_reset0;
    wire [15:0] redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_ia;
    wire [7:0] redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_aa;
    wire [7:0] redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_ab;
    wire [15:0] redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_iq;
    wire [15:0] redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_q;
    wire [7:0] redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_wraddr_i = 8'b11111111;
    wire [8:0] redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_a;
    wire [8:0] redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_b;
    logic [8:0] redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_o;
    wire [8:0] redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_q;
    reg [15:0] redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_inputreg0_q;
    reg [15:0] redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_outputreg0_q;
    wire redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_reset0;
    wire [15:0] redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_ia;
    wire [7:0] redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_aa;
    wire [7:0] redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_ab;
    wire [15:0] redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_iq;
    wire [15:0] redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_q;
    wire [7:0] redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_wraddr_i = 8'b11111111;
    wire [8:0] redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_a;
    wire [8:0] redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_b;
    logic [8:0] redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_o;
    wire [8:0] redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_q;
    reg [15:0] redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_inputreg0_q;
    reg [15:0] redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_outputreg0_q;
    wire redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_reset0;
    wire [15:0] redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_ia;
    wire [7:0] redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_aa;
    wire [7:0] redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_ab;
    wire [15:0] redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_iq;
    wire [15:0] redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_q;
    wire [7:0] redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_wraddr_i = 8'b11111111;
    wire [8:0] redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_a;
    wire [8:0] redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_b;
    logic [8:0] redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_o;
    wire [8:0] redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_q;
    reg [15:0] redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_inputreg0_q;
    reg [15:0] redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_outputreg0_q;
    wire redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_reset0;
    wire [15:0] redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_ia;
    wire [7:0] redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_aa;
    wire [7:0] redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_ab;
    wire [15:0] redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_iq;
    wire [15:0] redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_q;
    wire [7:0] redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_wraddr_i = 8'b11111111;
    wire [8:0] redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_a;
    wire [8:0] redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_b;
    logic [8:0] redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_o;
    wire [8:0] redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_q;
    reg [15:0] redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_inputreg0_q;
    reg [15:0] redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_outputreg0_q;
    wire redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_reset0;
    wire [15:0] redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_ia;
    wire [7:0] redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_aa;
    wire [7:0] redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_ab;
    wire [15:0] redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_iq;
    wire [15:0] redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_q;
    wire [7:0] redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_wraddr_i = 8'b11111111;
    wire [8:0] redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_a;
    wire [8:0] redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_b;
    logic [8:0] redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_o;
    wire [8:0] redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_q;
    reg [15:0] redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_inputreg0_q;
    reg [15:0] redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_outputreg0_q;
    wire redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_reset0;
    wire [15:0] redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_ia;
    wire [7:0] redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_aa;
    wire [7:0] redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_ab;
    wire [15:0] redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_iq;
    wire [15:0] redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_q;
    wire [7:0] redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_wraddr_i = 8'b11111111;
    wire [8:0] redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_a;
    wire [8:0] redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_b;
    logic [8:0] redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_o;
    wire [8:0] redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_q;
    reg [15:0] redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_inputreg0_q;
    reg [15:0] redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_outputreg0_q;
    wire redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_reset0;
    wire [15:0] redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_ia;
    wire [7:0] redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_aa;
    wire [7:0] redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_ab;
    wire [15:0] redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_iq;
    wire [15:0] redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_q;
    wire [7:0] redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_wraddr_i = 8'b11111111;
    wire [8:0] redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_a;
    wire [8:0] redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_b;
    logic [8:0] redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_o;
    wire [8:0] redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_q;
    reg [15:0] redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_inputreg0_q;
    reg [15:0] redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_outputreg0_q;
    wire redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_reset0;
    wire [15:0] redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_ia;
    wire [7:0] redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_aa;
    wire [7:0] redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_ab;
    wire [15:0] redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_iq;
    wire [15:0] redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_q;
    wire [7:0] redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_wraddr_i = 8'b11111111;
    wire [8:0] redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_a;
    wire [8:0] redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_b;
    logic [8:0] redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_o;
    wire [8:0] redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_q;
    reg [15:0] redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_inputreg0_q;
    reg [15:0] redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_outputreg0_q;
    wire redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_reset0;
    wire [15:0] redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_ia;
    wire [7:0] redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_aa;
    wire [7:0] redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_ab;
    wire [15:0] redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_iq;
    wire [15:0] redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_q;
    wire [7:0] redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_wraddr_i = 8'b11111111;
    wire [8:0] redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_a;
    wire [8:0] redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_b;
    logic [8:0] redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_o;
    wire [8:0] redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_q;
    reg [15:0] redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_inputreg0_q;
    reg [15:0] redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_outputreg0_q;
    wire redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_reset0;
    wire [15:0] redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_ia;
    wire [7:0] redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_aa;
    wire [7:0] redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_ab;
    wire [15:0] redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_iq;
    wire [15:0] redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_q;
    wire [7:0] redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_wraddr_i = 8'b11111111;
    wire [8:0] redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_a;
    wire [8:0] redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_b;
    logic [8:0] redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_o;
    wire [8:0] redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_q;
    reg [15:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_inputreg0_q;
    reg [15:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_outputreg0_q;
    wire redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_reset0;
    wire [15:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_ia;
    wire [4:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_aa;
    wire [4:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_ab;
    wire [15:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_iq;
    wire [15:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_q;
    wire [4:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_a;
    wire [5:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_b;
    logic [5:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_o;
    wire [5:0] redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_q;
    reg [15:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_inputreg0_q;
    reg [15:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_outputreg0_q;
    wire redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_reset0;
    wire [15:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_ia;
    wire [4:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_aa;
    wire [4:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_ab;
    wire [15:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_iq;
    wire [15:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_q;
    wire [4:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_a;
    wire [5:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_b;
    logic [5:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_o;
    wire [5:0] redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_q;
    reg [15:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_inputreg0_q;
    reg [15:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_outputreg0_q;
    wire redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_reset0;
    wire [15:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_ia;
    wire [4:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_aa;
    wire [4:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_ab;
    wire [15:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_iq;
    wire [15:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_q;
    wire [4:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_a;
    wire [5:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_b;
    logic [5:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_o;
    wire [5:0] redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_q;
    reg [15:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_inputreg0_q;
    reg [15:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_outputreg0_q;
    wire redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_reset0;
    wire [15:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_ia;
    wire [4:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_aa;
    wire [4:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_ab;
    wire [15:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_iq;
    wire [15:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_q;
    wire [4:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_a;
    wire [5:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_b;
    logic [5:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_o;
    wire [5:0] redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_q;
    reg [15:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_inputreg0_q;
    reg [15:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_outputreg0_q;
    wire redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_reset0;
    wire [15:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_ia;
    wire [4:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_aa;
    wire [4:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_ab;
    wire [15:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_iq;
    wire [15:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_q;
    wire [4:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_a;
    wire [5:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_b;
    logic [5:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_o;
    wire [5:0] redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_q;
    reg [15:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_inputreg0_q;
    reg [15:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_outputreg0_q;
    wire redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_reset0;
    wire [15:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_ia;
    wire [4:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_aa;
    wire [4:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_ab;
    wire [15:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_iq;
    wire [15:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_q;
    wire [4:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_a;
    wire [5:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_b;
    logic [5:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_o;
    wire [5:0] redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_q;
    reg [15:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_inputreg0_q;
    reg [15:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_outputreg0_q;
    wire redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_reset0;
    wire [15:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_ia;
    wire [4:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_aa;
    wire [4:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_ab;
    wire [15:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_iq;
    wire [15:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_q;
    wire [4:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_a;
    wire [5:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_b;
    logic [5:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_o;
    wire [5:0] redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_q;
    reg [15:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_inputreg0_q;
    reg [15:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_outputreg0_q;
    wire redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_reset0;
    wire [15:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_ia;
    wire [4:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_aa;
    wire [4:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_ab;
    wire [15:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_iq;
    wire [15:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_q;
    wire [4:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_a;
    wire [5:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_b;
    logic [5:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_o;
    wire [5:0] redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_q;
    reg [15:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_inputreg0_q;
    reg [15:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_outputreg0_q;
    wire redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_reset0;
    wire [15:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_ia;
    wire [4:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_aa;
    wire [4:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_ab;
    wire [15:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_iq;
    wire [15:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_q;
    wire [4:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_a;
    wire [5:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_b;
    logic [5:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_o;
    wire [5:0] redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_q;
    reg [15:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_inputreg0_q;
    reg [15:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_outputreg0_q;
    wire redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_reset0;
    wire [15:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_ia;
    wire [4:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_aa;
    wire [4:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_ab;
    wire [15:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_iq;
    wire [15:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_q;
    wire [4:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_a;
    wire [5:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_b;
    logic [5:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_o;
    wire [5:0] redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_q;
    reg [15:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_inputreg0_q;
    reg [15:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_outputreg0_q;
    wire redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_reset0;
    wire [15:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_ia;
    wire [4:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_aa;
    wire [4:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_ab;
    wire [15:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_iq;
    wire [15:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_q;
    wire [4:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_a;
    wire [5:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_b;
    logic [5:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_o;
    wire [5:0] redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_q;
    reg [15:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_inputreg0_q;
    reg [15:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_outputreg0_q;
    wire redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_reset0;
    wire [15:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_ia;
    wire [4:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_aa;
    wire [4:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_ab;
    wire [15:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_iq;
    wire [15:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_q;
    wire [4:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_a;
    wire [5:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_b;
    logic [5:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_o;
    wire [5:0] redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_q;
    reg [15:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_inputreg0_q;
    reg [15:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_outputreg0_q;
    wire redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_reset0;
    wire [15:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_ia;
    wire [4:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_aa;
    wire [4:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_ab;
    wire [15:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_iq;
    wire [15:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_q;
    wire [4:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_a;
    wire [5:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_b;
    logic [5:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_o;
    wire [5:0] redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_q;
    reg [15:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_inputreg0_q;
    reg [15:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_outputreg0_q;
    wire redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_reset0;
    wire [15:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_ia;
    wire [4:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_aa;
    wire [4:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_ab;
    wire [15:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_iq;
    wire [15:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_q;
    wire [4:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_a;
    wire [5:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_b;
    logic [5:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_o;
    wire [5:0] redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_q;
    reg [15:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_inputreg0_q;
    reg [15:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_outputreg0_q;
    wire redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_reset0;
    wire [15:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_ia;
    wire [4:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_aa;
    wire [4:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_ab;
    wire [15:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_iq;
    wire [15:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_q;
    wire [4:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_a;
    wire [5:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_b;
    logic [5:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_o;
    wire [5:0] redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_q;
    reg [15:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_inputreg0_q;
    reg [15:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_outputreg0_q;
    wire redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_reset0;
    wire [15:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_ia;
    wire [4:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_aa;
    wire [4:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_ab;
    wire [15:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_iq;
    wire [15:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_q;
    wire [4:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_a;
    wire [5:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_b;
    logic [5:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_o;
    wire [5:0] redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_q;
    reg [15:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_inputreg0_q;
    reg [15:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_outputreg0_q;
    wire redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_reset0;
    wire [15:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_ia;
    wire [4:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_aa;
    wire [4:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_ab;
    wire [15:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_iq;
    wire [15:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_q;
    wire [4:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_a;
    wire [5:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_b;
    logic [5:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_o;
    wire [5:0] redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_q;
    reg [15:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_inputreg0_q;
    reg [15:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_outputreg0_q;
    wire redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_reset0;
    wire [15:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_ia;
    wire [4:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_aa;
    wire [4:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_ab;
    wire [15:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_iq;
    wire [15:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_q;
    wire [4:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_a;
    wire [5:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_b;
    logic [5:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_o;
    wire [5:0] redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_q;
    reg [15:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_inputreg0_q;
    reg [15:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_outputreg0_q;
    wire redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_reset0;
    wire [15:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_ia;
    wire [4:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_aa;
    wire [4:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_ab;
    wire [15:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_iq;
    wire [15:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_q;
    wire [5:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_a;
    wire [5:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_b;
    logic [5:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_o;
    wire [5:0] redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_q;
    reg [15:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_inputreg0_q;
    reg [15:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_outputreg0_q;
    wire redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_reset0;
    wire [15:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_ia;
    wire [4:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_aa;
    wire [4:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_ab;
    wire [15:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_iq;
    wire [15:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_q;
    wire [5:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_a;
    wire [5:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_b;
    logic [5:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_o;
    wire [5:0] redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_q;
    reg [15:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_inputreg0_q;
    reg [15:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_outputreg0_q;
    wire redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_reset0;
    wire [15:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_ia;
    wire [4:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_aa;
    wire [4:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_ab;
    wire [15:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_iq;
    wire [15:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_q;
    wire [5:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_a;
    wire [5:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_b;
    logic [5:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_o;
    wire [5:0] redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_q;
    reg [15:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_inputreg0_q;
    reg [15:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_outputreg0_q;
    wire redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_reset0;
    wire [15:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_ia;
    wire [4:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_aa;
    wire [4:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_ab;
    wire [15:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_iq;
    wire [15:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_q;
    wire [5:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_a;
    wire [5:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_b;
    logic [5:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_o;
    wire [5:0] redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_q;
    reg [15:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_inputreg0_q;
    reg [15:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_outputreg0_q;
    wire redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_reset0;
    wire [15:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_ia;
    wire [4:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_aa;
    wire [4:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_ab;
    wire [15:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_iq;
    wire [15:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_q;
    wire [5:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_a;
    wire [5:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_b;
    logic [5:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_o;
    wire [5:0] redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_q;
    reg [15:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_inputreg0_q;
    reg [15:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_outputreg0_q;
    wire redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_reset0;
    wire [15:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_ia;
    wire [4:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_aa;
    wire [4:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_ab;
    wire [15:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_iq;
    wire [15:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_q;
    wire [5:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_a;
    wire [5:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_b;
    logic [5:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_o;
    wire [5:0] redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_q;
    reg [15:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_inputreg0_q;
    reg [15:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_outputreg0_q;
    wire redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_reset0;
    wire [15:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_ia;
    wire [4:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_aa;
    wire [4:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_ab;
    wire [15:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_iq;
    wire [15:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_q;
    wire [5:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_a;
    wire [5:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_b;
    logic [5:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_o;
    wire [5:0] redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_q;
    reg [15:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_inputreg0_q;
    reg [15:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_outputreg0_q;
    wire redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_reset0;
    wire [15:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_ia;
    wire [4:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_aa;
    wire [4:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_ab;
    wire [15:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_iq;
    wire [15:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_q;
    wire [5:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_a;
    wire [5:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_b;
    logic [5:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_o;
    wire [5:0] redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_q;
    reg [15:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_inputreg0_q;
    reg [15:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_outputreg0_q;
    wire redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_reset0;
    wire [15:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_ia;
    wire [4:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_aa;
    wire [4:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_ab;
    wire [15:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_iq;
    wire [15:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_q;
    wire [5:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_a;
    wire [5:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_b;
    logic [5:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_o;
    wire [5:0] redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_q;
    reg [15:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_inputreg0_q;
    reg [15:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_outputreg0_q;
    wire redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_reset0;
    wire [15:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_ia;
    wire [4:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_aa;
    wire [4:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_ab;
    wire [15:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_iq;
    wire [15:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_q;
    wire [5:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_a;
    wire [5:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_b;
    logic [5:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_o;
    wire [5:0] redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_q;
    reg [15:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_inputreg0_q;
    reg [15:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_outputreg0_q;
    wire redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_reset0;
    wire [15:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_ia;
    wire [4:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_aa;
    wire [4:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_ab;
    wire [15:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_iq;
    wire [15:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_q;
    wire [5:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_a;
    wire [5:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_b;
    logic [5:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_o;
    wire [5:0] redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_q;
    reg [15:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_inputreg0_q;
    reg [15:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_outputreg0_q;
    wire redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_reset0;
    wire [15:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_ia;
    wire [4:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_aa;
    wire [4:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_ab;
    wire [15:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_iq;
    wire [15:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_q;
    wire [5:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_a;
    wire [5:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_b;
    logic [5:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_o;
    wire [5:0] redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_q;
    reg [15:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_inputreg0_q;
    reg [15:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_outputreg0_q;
    wire redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_reset0;
    wire [15:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_ia;
    wire [4:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_aa;
    wire [4:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_ab;
    wire [15:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_iq;
    wire [15:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_q;
    wire [5:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_a;
    wire [5:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_b;
    logic [5:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_o;
    wire [5:0] redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_q;
    reg [15:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_inputreg0_q;
    reg [15:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_outputreg0_q;
    wire redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_reset0;
    wire [15:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_ia;
    wire [4:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_aa;
    wire [4:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_ab;
    wire [15:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_iq;
    wire [15:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_q;
    wire [5:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_a;
    wire [5:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_b;
    logic [5:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_o;
    wire [5:0] redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_q;
    reg [15:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_inputreg0_q;
    reg [15:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_outputreg0_q;
    wire redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_reset0;
    wire [15:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_ia;
    wire [4:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_aa;
    wire [4:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_ab;
    wire [15:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_iq;
    wire [15:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_q;
    wire [4:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_a;
    wire [5:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_b;
    logic [5:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_o;
    wire [5:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_q;
    reg [15:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_inputreg0_q;
    reg [15:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_outputreg0_q;
    wire redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_reset0;
    wire [15:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_ia;
    wire [4:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_aa;
    wire [4:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_ab;
    wire [15:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_iq;
    wire [15:0] redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_q;
    reg [15:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_inputreg0_q;
    reg [15:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_outputreg0_q;
    wire redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_reset0;
    wire [15:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_ia;
    wire [4:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_aa;
    wire [4:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_ab;
    wire [15:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_iq;
    wire [15:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_q;
    wire [4:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_a;
    wire [5:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_b;
    logic [5:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_o;
    wire [5:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_q;
    reg [15:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_inputreg0_q;
    reg [15:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_outputreg0_q;
    wire redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_reset0;
    wire [15:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_ia;
    wire [4:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_aa;
    wire [4:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_ab;
    wire [15:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_iq;
    wire [15:0] redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_q;
    reg [15:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_inputreg0_q;
    reg [15:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_outputreg0_q;
    wire redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_reset0;
    wire [15:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_ia;
    wire [4:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_aa;
    wire [4:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_ab;
    wire [15:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_iq;
    wire [15:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_q;
    wire [4:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_a;
    wire [5:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_b;
    logic [5:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_o;
    wire [5:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_q;
    reg [15:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_inputreg0_q;
    reg [15:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_outputreg0_q;
    wire redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_reset0;
    wire [15:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_ia;
    wire [4:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_aa;
    wire [4:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_ab;
    wire [15:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_iq;
    wire [15:0] redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_q;
    reg [15:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_inputreg0_q;
    reg [15:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_outputreg0_q;
    wire redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_reset0;
    wire [15:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_ia;
    wire [4:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_aa;
    wire [4:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_ab;
    wire [15:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_iq;
    wire [15:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_q;
    wire [4:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_a;
    wire [5:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_b;
    logic [5:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_o;
    wire [5:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_q;
    reg [15:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_inputreg0_q;
    reg [15:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_outputreg0_q;
    wire redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_reset0;
    wire [15:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_ia;
    wire [4:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_aa;
    wire [4:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_ab;
    wire [15:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_iq;
    wire [15:0] redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_q;
    reg [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_inputreg0_q;
    reg [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_outputreg0_q;
    wire redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_reset0;
    wire [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_ia;
    wire [4:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_aa;
    wire [4:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_ab;
    wire [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_iq;
    wire [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_q;
    wire [4:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_a;
    wire [5:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_b;
    logic [5:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_o;
    wire [5:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_q;
    reg [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_inputreg0_q;
    reg [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_outputreg0_q;
    wire redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_reset0;
    wire [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_ia;
    wire [4:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_aa;
    wire [4:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_ab;
    wire [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_iq;
    wire [15:0] redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_q;
    reg [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_inputreg0_q;
    reg [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_outputreg0_q;
    wire redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_reset0;
    wire [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_ia;
    wire [4:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_aa;
    wire [4:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_ab;
    wire [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_iq;
    wire [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_q;
    wire [4:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_a;
    wire [5:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_b;
    logic [5:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_o;
    wire [5:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_q;
    reg [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_inputreg0_q;
    reg [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_outputreg0_q;
    wire redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_reset0;
    wire [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_ia;
    wire [4:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_aa;
    wire [4:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_ab;
    wire [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_iq;
    wire [15:0] redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_q;
    reg [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_inputreg0_q;
    reg [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_outputreg0_q;
    wire redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_reset0;
    wire [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_ia;
    wire [4:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_aa;
    wire [4:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_ab;
    wire [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_iq;
    wire [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_q;
    wire [4:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_a;
    wire [5:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_b;
    logic [5:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_o;
    wire [5:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_q;
    reg [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_inputreg0_q;
    reg [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_outputreg0_q;
    wire redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_reset0;
    wire [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_ia;
    wire [4:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_aa;
    wire [4:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_ab;
    wire [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_iq;
    wire [15:0] redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_q;
    reg [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_inputreg0_q;
    reg [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_outputreg0_q;
    wire redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_reset0;
    wire [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_ia;
    wire [4:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_aa;
    wire [4:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_ab;
    wire [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_iq;
    wire [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_q;
    wire [4:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_a;
    wire [5:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_b;
    logic [5:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_o;
    wire [5:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_q;
    reg [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_inputreg0_q;
    reg [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_outputreg0_q;
    wire redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_reset0;
    wire [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_ia;
    wire [4:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_aa;
    wire [4:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_ab;
    wire [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_iq;
    wire [15:0] redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_q;
    reg [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_inputreg0_q;
    reg [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_outputreg0_q;
    wire redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_reset0;
    wire [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_ia;
    wire [4:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_aa;
    wire [4:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_ab;
    wire [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_iq;
    wire [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_q;
    wire [4:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_a;
    wire [5:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_b;
    logic [5:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_o;
    wire [5:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_q;
    reg [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_inputreg0_q;
    reg [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_outputreg0_q;
    wire redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_reset0;
    wire [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_ia;
    wire [4:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_aa;
    wire [4:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_ab;
    wire [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_iq;
    wire [15:0] redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_q;
    reg [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_inputreg0_q;
    reg [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_outputreg0_q;
    wire redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_reset0;
    wire [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_ia;
    wire [4:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_aa;
    wire [4:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_ab;
    wire [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_iq;
    wire [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_q;
    wire [4:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_a;
    wire [5:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_b;
    logic [5:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_o;
    wire [5:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_q;
    reg [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_inputreg0_q;
    reg [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_outputreg0_q;
    wire redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_reset0;
    wire [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_ia;
    wire [4:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_aa;
    wire [4:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_ab;
    wire [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_iq;
    wire [15:0] redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_q;
    reg [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_inputreg0_q;
    reg [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_outputreg0_q;
    wire redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_reset0;
    wire [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_ia;
    wire [4:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_aa;
    wire [4:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_ab;
    wire [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_iq;
    wire [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_q;
    wire [4:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_a;
    wire [5:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_b;
    logic [5:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_o;
    wire [5:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_q;
    reg [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_inputreg0_q;
    reg [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_outputreg0_q;
    wire redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_reset0;
    wire [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_ia;
    wire [4:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_aa;
    wire [4:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_ab;
    wire [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_iq;
    wire [15:0] redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_q;
    reg [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_inputreg0_q;
    reg [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_outputreg0_q;
    wire redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_reset0;
    wire [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_ia;
    wire [4:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_aa;
    wire [4:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_ab;
    wire [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_iq;
    wire [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_q;
    wire [4:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_a;
    wire [5:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_b;
    logic [5:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_o;
    wire [5:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_q;
    reg [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_inputreg0_q;
    reg [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_outputreg0_q;
    wire redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_reset0;
    wire [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_ia;
    wire [4:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_aa;
    wire [4:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_ab;
    wire [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_iq;
    wire [15:0] redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_q;
    reg [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_inputreg0_q;
    reg [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_outputreg0_q;
    wire redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_reset0;
    wire [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_ia;
    wire [4:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_aa;
    wire [4:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_ab;
    wire [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_iq;
    wire [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_q;
    wire [4:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_a;
    wire [5:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_b;
    logic [5:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_o;
    wire [5:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_q;
    reg [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_inputreg0_q;
    reg [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_outputreg0_q;
    wire redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_reset0;
    wire [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_ia;
    wire [4:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_aa;
    wire [4:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_ab;
    wire [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_iq;
    wire [15:0] redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_q;
    reg [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_inputreg0_q;
    reg [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_outputreg0_q;
    wire redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_reset0;
    wire [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_ia;
    wire [4:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_aa;
    wire [4:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_ab;
    wire [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_iq;
    wire [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_q;
    wire [4:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_a;
    wire [5:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_b;
    logic [5:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_o;
    wire [5:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_q;
    reg [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_inputreg0_q;
    reg [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_outputreg0_q;
    wire redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_reset0;
    wire [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_ia;
    wire [4:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_aa;
    wire [4:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_ab;
    wire [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_iq;
    wire [15:0] redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_q;
    reg [15:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_inputreg0_q;
    reg [15:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_outputreg0_q;
    wire redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_reset0;
    wire [15:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_ia;
    wire [4:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_aa;
    wire [4:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_ab;
    wire [15:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_iq;
    wire [15:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_q;
    wire [4:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_a;
    wire [5:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_b;
    logic [5:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_o;
    wire [5:0] redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_q;
    reg [15:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_inputreg0_q;
    reg [15:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_outputreg0_q;
    wire redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_reset0;
    wire [15:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_ia;
    wire [4:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_aa;
    wire [4:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_ab;
    wire [15:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_iq;
    wire [15:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_q;
    wire [4:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_a;
    wire [5:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_b;
    logic [5:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_o;
    wire [5:0] redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_q;
    reg [15:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_inputreg0_q;
    reg [15:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_outputreg0_q;
    wire redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_reset0;
    wire [15:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_ia;
    wire [4:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_aa;
    wire [4:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_ab;
    wire [15:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_iq;
    wire [15:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_q;
    wire [4:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_a;
    wire [5:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_b;
    logic [5:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_o;
    wire [5:0] redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_q;
    reg [15:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_inputreg0_q;
    reg [15:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_outputreg0_q;
    wire redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_reset0;
    wire [15:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_ia;
    wire [4:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_aa;
    wire [4:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_ab;
    wire [15:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_iq;
    wire [15:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_q;
    wire [4:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_a;
    wire [5:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_b;
    logic [5:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_o;
    wire [5:0] redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_q;
    reg [15:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_inputreg0_q;
    reg [15:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_outputreg0_q;
    wire redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_reset0;
    wire [15:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_ia;
    wire [4:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_aa;
    wire [4:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_ab;
    wire [15:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_iq;
    wire [15:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_q;
    wire [4:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_a;
    wire [5:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_b;
    logic [5:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_o;
    wire [5:0] redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_q;
    reg [15:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_inputreg0_q;
    reg [15:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_outputreg0_q;
    wire redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_reset0;
    wire [15:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_ia;
    wire [4:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_aa;
    wire [4:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_ab;
    wire [15:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_iq;
    wire [15:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_q;
    wire [4:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_a;
    wire [5:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_b;
    logic [5:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_o;
    wire [5:0] redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_q;
    reg [15:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_inputreg0_q;
    reg [15:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_outputreg0_q;
    wire redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_reset0;
    wire [15:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_ia;
    wire [4:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_aa;
    wire [4:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_ab;
    wire [15:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_iq;
    wire [15:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_q;
    wire [4:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_a;
    wire [5:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_b;
    logic [5:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_o;
    wire [5:0] redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_q;
    reg [15:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_inputreg0_q;
    reg [15:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_outputreg0_q;
    wire redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_reset0;
    wire [15:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_ia;
    wire [4:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_aa;
    wire [4:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_ab;
    wire [15:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_iq;
    wire [15:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_q;
    wire [4:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_a;
    wire [5:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_b;
    logic [5:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_o;
    wire [5:0] redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_q;
    reg [15:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_inputreg0_q;
    reg [15:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_outputreg0_q;
    wire redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_reset0;
    wire [15:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_ia;
    wire [4:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_aa;
    wire [4:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_ab;
    wire [15:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_iq;
    wire [15:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_q;
    wire [4:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_a;
    wire [5:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_b;
    logic [5:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_o;
    wire [5:0] redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_q;
    reg [15:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_inputreg0_q;
    reg [15:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_outputreg0_q;
    wire redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_reset0;
    wire [15:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_ia;
    wire [4:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_aa;
    wire [4:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_ab;
    wire [15:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_iq;
    wire [15:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_q;
    wire [4:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_a;
    wire [5:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_b;
    logic [5:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_o;
    wire [5:0] redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_q;
    reg [15:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_inputreg0_q;
    reg [15:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_outputreg0_q;
    wire redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_reset0;
    wire [15:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_ia;
    wire [4:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_aa;
    wire [4:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_ab;
    wire [15:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_iq;
    wire [15:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_q;
    wire [4:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_a;
    wire [5:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_b;
    logic [5:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_o;
    wire [5:0] redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_q;
    reg [15:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_inputreg0_q;
    reg [15:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_outputreg0_q;
    wire redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_reset0;
    wire [15:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_ia;
    wire [4:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_aa;
    wire [4:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_ab;
    wire [15:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_iq;
    wire [15:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_q;
    wire [4:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_a;
    wire [5:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_b;
    logic [5:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_o;
    wire [5:0] redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_q;
    reg [15:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_inputreg0_q;
    reg [15:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_outputreg0_q;
    wire redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_reset0;
    wire [15:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_ia;
    wire [4:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_aa;
    wire [4:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_ab;
    wire [15:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_iq;
    wire [15:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_q;
    wire [4:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_a;
    wire [5:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_b;
    logic [5:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_o;
    wire [5:0] redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_q;
    reg [15:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_inputreg0_q;
    reg [15:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_outputreg0_q;
    wire redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_reset0;
    wire [15:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_ia;
    wire [4:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_aa;
    wire [4:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_ab;
    wire [15:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_iq;
    wire [15:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_q;
    wire [4:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_a;
    wire [5:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_b;
    logic [5:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_o;
    wire [5:0] redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_q;
    reg [15:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_inputreg0_q;
    reg [15:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_outputreg0_q;
    wire redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_reset0;
    wire [15:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_ia;
    wire [4:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_aa;
    wire [4:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_ab;
    wire [15:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_iq;
    wire [15:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_q;
    wire [4:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_a;
    wire [5:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_b;
    logic [5:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_o;
    wire [5:0] redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_q;
    reg [15:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_inputreg0_q;
    reg [15:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_outputreg0_q;
    wire redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_reset0;
    wire [15:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_ia;
    wire [4:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_aa;
    wire [4:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_ab;
    wire [15:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_iq;
    wire [15:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_q;
    wire [4:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_a;
    wire [5:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_b;
    logic [5:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_o;
    wire [5:0] redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_q;
    reg [15:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_inputreg0_q;
    reg [15:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_outputreg0_q;
    wire redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_reset0;
    wire [15:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_ia;
    wire [4:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_aa;
    wire [4:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_ab;
    wire [15:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_iq;
    wire [15:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_q;
    wire [4:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_a;
    wire [5:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_b;
    logic [5:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_o;
    wire [5:0] redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_q;
    reg [15:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_inputreg0_q;
    reg [15:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_outputreg0_q;
    wire redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_reset0;
    wire [15:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_ia;
    wire [4:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_aa;
    wire [4:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_ab;
    wire [15:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_iq;
    wire [15:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_q;
    wire [4:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_a;
    wire [5:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_b;
    logic [5:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_o;
    wire [5:0] redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_q;
    reg [15:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_inputreg0_q;
    reg [15:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_outputreg0_q;
    wire redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_reset0;
    wire [15:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_ia;
    wire [4:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_aa;
    wire [4:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_ab;
    wire [15:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_iq;
    wire [15:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_q;
    wire [5:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_a;
    wire [5:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_b;
    logic [5:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_o;
    wire [5:0] redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_q;
    reg [15:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_inputreg0_q;
    reg [15:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_outputreg0_q;
    wire redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_reset0;
    wire [15:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_ia;
    wire [4:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_aa;
    wire [4:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_ab;
    wire [15:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_iq;
    wire [15:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_q;
    wire [5:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_a;
    wire [5:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_b;
    logic [5:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_o;
    wire [5:0] redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_q;
    reg [15:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_inputreg0_q;
    reg [15:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_outputreg0_q;
    wire redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_reset0;
    wire [15:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_ia;
    wire [4:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_aa;
    wire [4:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_ab;
    wire [15:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_iq;
    wire [15:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_q;
    wire [5:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_a;
    wire [5:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_b;
    logic [5:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_o;
    wire [5:0] redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_q;
    reg [15:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_inputreg0_q;
    reg [15:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_outputreg0_q;
    wire redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_reset0;
    wire [15:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_ia;
    wire [4:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_aa;
    wire [4:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_ab;
    wire [15:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_iq;
    wire [15:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_q;
    wire [5:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_a;
    wire [5:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_b;
    logic [5:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_o;
    wire [5:0] redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_q;
    reg [15:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_inputreg0_q;
    reg [15:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_outputreg0_q;
    wire redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_reset0;
    wire [15:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_ia;
    wire [4:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_aa;
    wire [4:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_ab;
    wire [15:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_iq;
    wire [15:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_q;
    wire [5:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_a;
    wire [5:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_b;
    logic [5:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_o;
    wire [5:0] redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_q;
    reg [15:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_inputreg0_q;
    reg [15:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_outputreg0_q;
    wire redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_reset0;
    wire [15:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_ia;
    wire [4:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_aa;
    wire [4:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_ab;
    wire [15:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_iq;
    wire [15:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_q;
    wire [5:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_a;
    wire [5:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_b;
    logic [5:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_o;
    wire [5:0] redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_q;
    reg [15:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_inputreg0_q;
    reg [15:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_outputreg0_q;
    wire redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_reset0;
    wire [15:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_ia;
    wire [4:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_aa;
    wire [4:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_ab;
    wire [15:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_iq;
    wire [15:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_q;
    wire [5:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_a;
    wire [5:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_b;
    logic [5:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_o;
    wire [5:0] redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_q;
    reg [15:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_inputreg0_q;
    reg [15:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_outputreg0_q;
    wire redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_reset0;
    wire [15:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_ia;
    wire [4:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_aa;
    wire [4:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_ab;
    wire [15:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_iq;
    wire [15:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_q;
    wire [5:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_a;
    wire [5:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_b;
    logic [5:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_o;
    wire [5:0] redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_q;
    reg [15:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_inputreg0_q;
    reg [15:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_outputreg0_q;
    wire redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_reset0;
    wire [15:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_ia;
    wire [4:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_aa;
    wire [4:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_ab;
    wire [15:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_iq;
    wire [15:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_q;
    wire [5:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_a;
    wire [5:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_b;
    logic [5:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_o;
    wire [5:0] redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_q;
    reg [15:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_inputreg0_q;
    reg [15:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_outputreg0_q;
    wire redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_reset0;
    wire [15:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_ia;
    wire [4:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_aa;
    wire [4:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_ab;
    wire [15:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_iq;
    wire [15:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_q;
    wire [5:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_a;
    wire [5:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_b;
    logic [5:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_o;
    wire [5:0] redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_q;
    reg [15:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_inputreg0_q;
    reg [15:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_outputreg0_q;
    wire redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_reset0;
    wire [15:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_ia;
    wire [4:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_aa;
    wire [4:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_ab;
    wire [15:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_iq;
    wire [15:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_q;
    wire [5:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_a;
    wire [5:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_b;
    logic [5:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_o;
    wire [5:0] redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_q;
    reg [15:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_inputreg0_q;
    reg [15:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_outputreg0_q;
    wire redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_reset0;
    wire [15:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_ia;
    wire [4:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_aa;
    wire [4:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_ab;
    wire [15:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_iq;
    wire [15:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_q;
    wire [5:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_a;
    wire [5:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_b;
    logic [5:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_o;
    wire [5:0] redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_q;
    reg [15:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_inputreg0_q;
    reg [15:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_outputreg0_q;
    wire redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_reset0;
    wire [15:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_ia;
    wire [4:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_aa;
    wire [4:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_ab;
    wire [15:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_iq;
    wire [15:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_q;
    wire [5:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_a;
    wire [5:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_b;
    logic [5:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_o;
    wire [5:0] redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_q;
    reg [15:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_inputreg0_q;
    reg [15:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_outputreg0_q;
    wire redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_reset0;
    wire [15:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_ia;
    wire [4:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_aa;
    wire [4:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_ab;
    wire [15:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_iq;
    wire [15:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_q;
    wire [5:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_a;
    wire [5:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_b;
    logic [5:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_o;
    wire [5:0] redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_q;
    reg [15:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_inputreg0_q;
    reg [15:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_outputreg0_q;
    wire redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_reset0;
    wire [15:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_ia;
    wire [4:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_aa;
    wire [4:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_ab;
    wire [15:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_iq;
    wire [15:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_q;
    wire [4:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_a;
    wire [5:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_b;
    logic [5:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_o;
    wire [5:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_q;
    reg [15:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_inputreg0_q;
    reg [15:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_outputreg0_q;
    wire redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_reset0;
    wire [15:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_ia;
    wire [4:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_aa;
    wire [4:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_ab;
    wire [15:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_iq;
    wire [15:0] redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_q;
    reg [15:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_inputreg0_q;
    reg [15:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_outputreg0_q;
    wire redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_reset0;
    wire [15:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_ia;
    wire [4:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_aa;
    wire [4:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_ab;
    wire [15:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_iq;
    wire [15:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_q;
    wire [4:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_a;
    wire [5:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_b;
    logic [5:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_o;
    wire [5:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_q;
    reg [15:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_inputreg0_q;
    reg [15:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_outputreg0_q;
    wire redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_reset0;
    wire [15:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_ia;
    wire [4:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_aa;
    wire [4:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_ab;
    wire [15:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_iq;
    wire [15:0] redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_q;
    reg [15:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_inputreg0_q;
    reg [15:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_outputreg0_q;
    wire redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_reset0;
    wire [15:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_ia;
    wire [4:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_aa;
    wire [4:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_ab;
    wire [15:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_iq;
    wire [15:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_q;
    wire [4:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_a;
    wire [5:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_b;
    logic [5:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_o;
    wire [5:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_q;
    reg [15:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_inputreg0_q;
    reg [15:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_outputreg0_q;
    wire redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_reset0;
    wire [15:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_ia;
    wire [4:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_aa;
    wire [4:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_ab;
    wire [15:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_iq;
    wire [15:0] redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_q;
    reg [15:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_inputreg0_q;
    reg [15:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_outputreg0_q;
    wire redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_reset0;
    wire [15:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_ia;
    wire [4:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_aa;
    wire [4:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_ab;
    wire [15:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_iq;
    wire [15:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_q;
    wire [4:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_a;
    wire [5:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_b;
    logic [5:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_o;
    wire [5:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_q;
    reg [15:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_inputreg0_q;
    reg [15:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_outputreg0_q;
    wire redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_reset0;
    wire [15:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_ia;
    wire [4:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_aa;
    wire [4:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_ab;
    wire [15:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_iq;
    wire [15:0] redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_q;
    reg [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_inputreg0_q;
    reg [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_outputreg0_q;
    wire redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_reset0;
    wire [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_ia;
    wire [4:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_aa;
    wire [4:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_ab;
    wire [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_iq;
    wire [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_q;
    wire [4:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_a;
    wire [5:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_b;
    logic [5:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_o;
    wire [5:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_q;
    reg [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_inputreg0_q;
    reg [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_outputreg0_q;
    wire redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_reset0;
    wire [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_ia;
    wire [4:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_aa;
    wire [4:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_ab;
    wire [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_iq;
    wire [15:0] redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_q;
    reg [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_inputreg0_q;
    reg [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_outputreg0_q;
    wire redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_reset0;
    wire [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_ia;
    wire [4:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_aa;
    wire [4:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_ab;
    wire [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_iq;
    wire [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_q;
    wire [4:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_a;
    wire [5:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_b;
    logic [5:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_o;
    wire [5:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_q;
    reg [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_inputreg0_q;
    reg [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_outputreg0_q;
    wire redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_reset0;
    wire [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_ia;
    wire [4:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_aa;
    wire [4:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_ab;
    wire [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_iq;
    wire [15:0] redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_q;
    reg [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_inputreg0_q;
    reg [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_outputreg0_q;
    wire redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_reset0;
    wire [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_ia;
    wire [4:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_aa;
    wire [4:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_ab;
    wire [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_iq;
    wire [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_q;
    wire [4:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_a;
    wire [5:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_b;
    logic [5:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_o;
    wire [5:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_q;
    reg [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_inputreg0_q;
    reg [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_outputreg0_q;
    wire redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_reset0;
    wire [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_ia;
    wire [4:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_aa;
    wire [4:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_ab;
    wire [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_iq;
    wire [15:0] redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_q;
    reg [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_inputreg0_q;
    reg [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_outputreg0_q;
    wire redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_reset0;
    wire [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_ia;
    wire [4:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_aa;
    wire [4:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_ab;
    wire [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_iq;
    wire [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_q;
    wire [4:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_a;
    wire [5:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_b;
    logic [5:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_o;
    wire [5:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_q;
    reg [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_inputreg0_q;
    reg [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_outputreg0_q;
    wire redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_reset0;
    wire [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_ia;
    wire [4:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_aa;
    wire [4:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_ab;
    wire [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_iq;
    wire [15:0] redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_q;
    reg [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_inputreg0_q;
    reg [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_outputreg0_q;
    wire redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_reset0;
    wire [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_ia;
    wire [4:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_aa;
    wire [4:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_ab;
    wire [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_iq;
    wire [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_q;
    wire [4:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_a;
    wire [5:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_b;
    logic [5:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_o;
    wire [5:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_q;
    reg [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_inputreg0_q;
    reg [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_outputreg0_q;
    wire redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_reset0;
    wire [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_ia;
    wire [4:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_aa;
    wire [4:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_ab;
    wire [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_iq;
    wire [15:0] redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_q;
    reg [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_inputreg0_q;
    reg [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_outputreg0_q;
    wire redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_reset0;
    wire [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_ia;
    wire [4:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_aa;
    wire [4:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_ab;
    wire [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_iq;
    wire [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_q;
    wire [4:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_a;
    wire [5:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_b;
    logic [5:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_o;
    wire [5:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_q;
    reg [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_inputreg0_q;
    reg [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_outputreg0_q;
    wire redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_reset0;
    wire [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_ia;
    wire [4:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_aa;
    wire [4:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_ab;
    wire [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_iq;
    wire [15:0] redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_q;
    reg [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_inputreg0_q;
    reg [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_outputreg0_q;
    wire redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_reset0;
    wire [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_ia;
    wire [4:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_aa;
    wire [4:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_ab;
    wire [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_iq;
    wire [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_q;
    wire [4:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_a;
    wire [5:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_b;
    logic [5:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_o;
    wire [5:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_q;
    reg [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_inputreg0_q;
    reg [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_outputreg0_q;
    wire redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_reset0;
    wire [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_ia;
    wire [4:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_aa;
    wire [4:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_ab;
    wire [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_iq;
    wire [15:0] redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_q;
    reg [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_inputreg0_q;
    reg [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_outputreg0_q;
    wire redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_reset0;
    wire [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_ia;
    wire [4:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_aa;
    wire [4:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_ab;
    wire [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_iq;
    wire [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_q;
    wire [4:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_a;
    wire [5:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_b;
    logic [5:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_o;
    wire [5:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_q;
    reg [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_inputreg0_q;
    reg [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_outputreg0_q;
    wire redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_reset0;
    wire [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_ia;
    wire [4:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_aa;
    wire [4:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_ab;
    wire [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_iq;
    wire [15:0] redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_q;
    reg [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_inputreg0_q;
    reg [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_outputreg0_q;
    wire redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_reset0;
    wire [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_ia;
    wire [4:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_aa;
    wire [4:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_ab;
    wire [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_iq;
    wire [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_q;
    wire [4:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_a;
    wire [5:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_b;
    logic [5:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_o;
    wire [5:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_q;
    reg [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_inputreg0_q;
    reg [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_outputreg0_q;
    wire redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_reset0;
    wire [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_ia;
    wire [4:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_aa;
    wire [4:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_ab;
    wire [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_iq;
    wire [15:0] redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_q;
    reg [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_inputreg0_q;
    reg [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_outputreg0_q;
    wire redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_reset0;
    wire [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_ia;
    wire [4:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_aa;
    wire [4:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_ab;
    wire [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_iq;
    wire [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_q;
    wire [4:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_a;
    wire [5:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_b;
    logic [5:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_o;
    wire [5:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_q;
    reg [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_inputreg0_q;
    reg [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_outputreg0_q;
    wire redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_reset0;
    wire [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_ia;
    wire [4:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_aa;
    wire [4:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_ab;
    wire [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_iq;
    wire [15:0] redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_q;
    wire redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_reset0;
    wire [15:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_ia;
    wire [4:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_aa;
    wire [4:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_ab;
    wire [15:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_iq;
    wire [15:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_q;
    wire [4:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_i = 5'b11111;
    wire [4:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_offset_q;
    wire [5:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_a;
    wire [5:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_b;
    logic [5:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_o;
    wire [5:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_q;
    wire redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_reset0;
    wire [15:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_ia;
    wire [4:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_aa;
    wire [4:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_ab;
    wire [15:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_iq;
    wire [15:0] redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_q;
    wire redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_reset0;
    wire [15:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_ia;
    wire [4:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_aa;
    wire [4:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_ab;
    wire [15:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_iq;
    wire [15:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_q;
    wire [4:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_a;
    wire [5:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_b;
    logic [5:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_o;
    wire [5:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_q;
    wire redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_reset0;
    wire [15:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_ia;
    wire [4:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_aa;
    wire [4:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_ab;
    wire [15:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_iq;
    wire [15:0] redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_q;
    wire redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_reset0;
    wire [15:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_ia;
    wire [4:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_aa;
    wire [4:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_ab;
    wire [15:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_iq;
    wire [15:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_q;
    wire [4:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_a;
    wire [5:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_b;
    logic [5:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_o;
    wire [5:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_q;
    wire redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_reset0;
    wire [15:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_ia;
    wire [4:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_aa;
    wire [4:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_ab;
    wire [15:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_iq;
    wire [15:0] redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_q;
    wire redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_reset0;
    wire [15:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_ia;
    wire [4:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_aa;
    wire [4:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_ab;
    wire [15:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_iq;
    wire [15:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_q;
    wire [4:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_a;
    wire [5:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_b;
    logic [5:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_o;
    wire [5:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_q;
    wire redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_reset0;
    wire [15:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_ia;
    wire [4:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_aa;
    wire [4:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_ab;
    wire [15:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_iq;
    wire [15:0] redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_q;


    // VCC(CONSTANT,1)
    assign VCC_q = $unsigned(1'b1);

    // redist513_sync_together3657_aunroll_x_in_i_valid_2(DELAY,28741)
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist513_sync_together3657_aunroll_x_in_i_valid_2_delay_0 <= '0;
        end
        else
        begin
            redist513_sync_together3657_aunroll_x_in_i_valid_2_delay_0 <= $unsigned(in_i_valid);
        end
    end
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist513_sync_together3657_aunroll_x_in_i_valid_2_q <= redist513_sync_together3657_aunroll_x_in_i_valid_2_delay_0;
        end
    end

    // redist514_sync_together3657_aunroll_x_in_i_valid_3(DELAY,28742)
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist514_sync_together3657_aunroll_x_in_i_valid_3_q <= '0;
        end
        else
        begin
            redist514_sync_together3657_aunroll_x_in_i_valid_3_q <= $unsigned(redist513_sync_together3657_aunroll_x_in_i_valid_2_q);
        end
    end

    // valid_fanout_reg7(REG,12635)@3 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg7_q <= $unsigned(redist514_sync_together3657_aunroll_x_in_i_valid_3_q);
        end
    end

    // i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_c_i7_03_x(CONSTANT,5000)
    assign i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_c_i7_03_x_q = $unsigned(7'b0000000);

    // valid_fanout_reg2(REG,12630)@3 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg2_q <= $unsigned(redist514_sync_together3657_aunroll_x_in_i_valid_3_q);
        end
    end

    // valid_fanout_reg11(REG,12639)@3 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg11_q <= $unsigned(redist514_sync_together3657_aunroll_x_in_i_valid_3_q);
        end
    end

    // c_i5_143648(CONSTANT,6848)
    assign c_i5_143648_q = $unsigned(5'b01110);

    // i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_c_i3_03_x(CONSTANT,5009)
    assign i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_c_i3_03_x_q = $unsigned(3'b000);

    // c_i5_13650(CONSTANT,6847)
    assign c_i5_13650_q = $unsigned(5'b11111);

    // i_fpga_indvars_iv_next14_c_compstr3611(ADD,8387)@4
    assign i_fpga_indvars_iv_next14_c_compstr3611_a = {1'b0, i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr0_i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr3605_mux_x_q};
    assign i_fpga_indvars_iv_next14_c_compstr3611_b = {1'b0, c_i5_13650_q};
    assign i_fpga_indvars_iv_next14_c_compstr3611_o = $unsigned(i_fpga_indvars_iv_next14_c_compstr3611_a) + $unsigned(i_fpga_indvars_iv_next14_c_compstr3611_b);
    assign i_fpga_indvars_iv_next14_c_compstr3611_q = i_fpga_indvars_iv_next14_c_compstr3611_o[5:0];

    // bgTrunc_i_fpga_indvars_iv_next14_c_compstr3611_sel_x(BITSELECT,2302)@4
    assign bgTrunc_i_fpga_indvars_iv_next14_c_compstr3611_sel_x_b = i_fpga_indvars_iv_next14_c_compstr3611_q[4:0];

    // i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_element_extension2_x(BITJOIN,5010)@4
    assign i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_element_extension2_x_q = {i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_c_i3_03_x_q, bgTrunc_i_fpga_indvars_iv_next14_c_compstr3611_sel_x_b};

    // valid_fanout_reg13(REG,12641)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg13_q <= $unsigned(in_i_valid);
        end
    end

    // valid_fanout_reg12(REG,12640)@2 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg12_q <= $unsigned(redist513_sync_together3657_aunroll_x_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x(FIFODELAY,5011)@1 + 1
    // in i_valid@3
    // in i_write_pred@3
    // in i_data@4
    // out o_data@4
    assign i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_i_stall = ~ (valid_fanout_reg13_q & i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q);
    assign i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_i_valid = valid_fanout_reg12_q & redist517_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_i_data = i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_element_extension2_x_q;
    assign i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_i_valid[0];
    assign i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(8),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x (
        .i_valid(i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_i_stall_bitsignaltemp),
        .i_data(i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_element_extension2_x_q),
        .o_data(i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_adapt_scalar_trunc4_sel_x(BITSELECT,5007)@4
    assign i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_adapt_scalar_trunc4_sel_x_b = i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr1_x_o_data[4:0];

    // i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr0_i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr3605_mux_x(MUX,4997)@4
    assign i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr0_i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr3605_mux_x_s = redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_q;
    always @(i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr0_i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr3605_mux_x_s or i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_adapt_scalar_trunc4_sel_x_b or c_i5_143648_q)
    begin
        unique case (i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr0_i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr3605_mux_x_s)
            1'b0 : i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr0_i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr3605_mux_x_q = i_llvm_fpga_push_i5_fpga_indvars_iv13_push15_c_compstr0_adapt_scalar_trunc4_sel_x_b;
            1'b1 : i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr0_i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr3605_mux_x_q = c_i5_143648_q;
            default : i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr0_i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr3605_mux_x_q = 5'b0;
        endcase
    end

    // i_exitcond15_c_compstr3606_cmp_nsign(LOGICAL,27458)@4
    assign i_exitcond15_c_compstr3606_cmp_nsign_q = $unsigned(~ (i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr0_i_llvm_fpga_pop_i5_fpga_indvars_iv13_pop15_c_compstr3605_mux_x_q[4:4]));

    // i_llvm_fpga_push_i1_notexitcond_c_compstr3610(BLACKBOX,9034)@4
    // in in_empty_in@20000000
    // out out_feedback_out_2@20000000
    // out out_feedback_valid_out_2@20000000
    c_compSTR_i_llvm_fpga_push_i1_notexitcond_c_compstr0 thei_llvm_fpga_push_i1_notexitcond_c_compstr3610 (
        .in_almost_empty_in(GND_q),
        .in_data_in(i_exitcond15_c_compstr3606_cmp_nsign_q),
        .in_empty_in(GND_q),
        .in_feedback_stall_in_2(i_llvm_fpga_pipeline_keep_going_c_compstr6_out_not_exitcond_stall_out),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg11_q),
        .out_data_out(),
        .out_feedback_out_2(i_llvm_fpga_push_i1_notexitcond_c_compstr3610_out_feedback_out_2),
        .out_feedback_valid_out_2(i_llvm_fpga_push_i1_notexitcond_c_compstr3610_out_feedback_valid_out_2),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2(BLACKBOX,8393)@0
    // in in_stall_in@20000000
    c_compSTR_i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr0 thei_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2 (
        .in_dummy_in(in_dummy_in),
        .in_stall_in(GND_q),
        .in_valid_in(in_i_valid),
        .out_dummy_out(i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist511_i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out_4(DELAY,28739)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist511_i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out_4_delay_0 <= $unsigned(i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out);
            redist511_i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out_4_delay_1 <= redist511_i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out_4_delay_0;
            redist511_i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out_4_delay_2 <= redist511_i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out_4_delay_1;
            redist511_i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out_4_q <= redist511_i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out_4_delay_2;
        end
    end

    // i_llvm_fpga_pipeline_keep_going_c_compstr6(BLACKBOX,9033)@4
    // out out_exiting_stall_out@20000000
    // out out_exiting_valid_out@20000000
    // out out_not_exitcond_stall_out@20000000
    // out out_pipeline_dummy_out@20000000
    // out out_pipeline_forked_out@20000000
    // out out_pipeline_valid_out@20000000
    c_compSTR_i_llvm_fpga_pipeline_keep_going_c_compstr0 thei_llvm_fpga_pipeline_keep_going_c_compstr6 (
        .in_data_in(redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_q),
        .in_dummy_in(redist511_i_llvm_fpga_dummy_thread_c_compstr_b7_dummy_c_compstr2_out_dummy_out_4_q),
        .in_forked_in(redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_q),
        .in_not_exitcond_in(i_llvm_fpga_push_i1_notexitcond_c_compstr3610_out_feedback_out_2),
        .in_not_exitcond_valid_in(i_llvm_fpga_push_i1_notexitcond_c_compstr3610_out_feedback_valid_out_2),
        .in_pipeline_stall_in(GND_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg2_q),
        .out_data_out(i_llvm_fpga_pipeline_keep_going_c_compstr6_out_data_out),
        .out_exiting_stall_out(),
        .out_exiting_valid_out(i_llvm_fpga_pipeline_keep_going_c_compstr6_out_exiting_valid_out),
        .out_not_exitcond_stall_out(i_llvm_fpga_pipeline_keep_going_c_compstr6_out_not_exitcond_stall_out),
        .out_pipeline_dummy_out(i_llvm_fpga_pipeline_keep_going_c_compstr6_out_pipeline_dummy_out),
        .out_pipeline_forked_out(i_llvm_fpga_pipeline_keep_going_c_compstr6_out_pipeline_forked_out),
        .out_pipeline_valid_out(i_llvm_fpga_pipeline_keep_going_c_compstr6_out_pipeline_valid_out),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_c_compstr_b7_next_iter_isreal_c_compstr7(LOGICAL,7109)@4
    assign i_c_compstr_b7_next_iter_isreal_c_compstr7_q = i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr4_mux_x_q & i_llvm_fpga_pipeline_keep_going_c_compstr6_out_data_out;

    // i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_element_extension2_x(BITJOIN,5001)@4
    assign i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_element_extension2_x_q = {i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_c_i7_03_x_q, i_c_compstr_b7_next_iter_isreal_c_compstr7_q};

    // i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x(LOGICAL,5003)@1
    assign i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q = ~ (GND_q);

    // valid_fanout_reg4(REG,12632)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg4_q <= $unsigned(in_i_valid);
        end
    end

    // redist517_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2(DELAY,28745)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist517_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_delay_0 <= $unsigned(i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q);
            redist517_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_q <= redist517_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_delay_0;
        end
    end

    // valid_fanout_reg3(REG,12631)@2 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg3_q <= $unsigned(redist513_sync_together3657_aunroll_x_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x(FIFODELAY,5002)@1 + 1
    // in i_valid@3
    // in i_write_pred@3
    // in i_data@4
    // out o_data@4
    assign i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_i_stall = ~ (valid_fanout_reg4_q & i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q);
    assign i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_i_valid = valid_fanout_reg3_q & redist517_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_i_data = i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_element_extension2_x_q;
    assign i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_i_valid[0];
    assign i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(8),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x (
        .i_valid(i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_i_stall_bitsignaltemp),
        .i_data(i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_element_extension2_x_q),
        .o_data(i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_adapt_scalar_trunc4_sel_x(BITSELECT,4998)@4
    assign i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_adapt_scalar_trunc4_sel_x_b = i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr1_x_o_data[0:0];

    // i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3(BLACKBOX,8394)@0
    // in in_stall_in@20000000
    c_compSTR_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr0 thei_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3 (
        .in_buffer_in(in_buffer_in),
        .in_stall_in(GND_q),
        .in_valid_in(in_i_valid),
        .out_buffer_out(i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4(DELAY,28738)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_delay_0 <= $unsigned(i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out);
            redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_delay_1 <= redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_delay_0;
            redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_delay_2 <= redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_delay_1;
            redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_q <= redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_delay_2;
        end
    end

    // i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr4_mux_x(MUX,4995)@4
    assign i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr4_mux_x_s = redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_q;
    always @(i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr4_mux_x_s or i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_adapt_scalar_trunc4_sel_x_b or VCC_q)
    begin
        unique case (i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr4_mux_x_s)
            1'b0 : i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr4_mux_x_q = i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_adapt_scalar_trunc4_sel_x_b;
            1'b1 : i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr4_mux_x_q = VCC_q;
            default : i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr4_mux_x_q = 1'b0;
        endcase
    end

    // i_c_compstr_b7_current_iter_isspec_c_compstr5(LOGICAL,7108)@4
    assign i_c_compstr_b7_current_iter_isspec_c_compstr5_q = i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b7_current_iter_isreal_c_compstr4_mux_x_q ^ VCC_q;

    // c_c_compSTR_W_pmem(CONSTANT,6817)
    assign c_c_compSTR_W_pmem_q = $unsigned(64'b0100000001000001000000000000000000000000000000000000000000000000);

    // i_value2_i_i157_i3_c_compstr0_trunc_sel_x_merged_bit_select(BITSELECT,28227)@4
    assign i_value2_i_i157_i3_c_compstr0_trunc_sel_x_merged_bit_select_b = c_c_compSTR_W_pmem_q[12:0];
    assign i_value2_i_i157_i3_c_compstr0_trunc_sel_x_merged_bit_select_c = c_c_compSTR_W_pmem_q[63:13];

    // c_i32_03636(CONSTANT,6843)
    assign c_i32_03636_q = $unsigned(32'b00000000000000000000000000000000);

    // c_i32_13647(CONSTANT,6844)
    assign c_i32_13647_q = $unsigned(32'b00000000000000000000000000000001);

    // i_inc44_c_compstr3604(ADD,8392)@4
    assign i_inc44_c_compstr3604_a = {1'b0, i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr0_i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr9_mux_x_q};
    assign i_inc44_c_compstr3604_b = {1'b0, c_i32_13647_q};
    assign i_inc44_c_compstr3604_o = $unsigned(i_inc44_c_compstr3604_a) + $unsigned(i_inc44_c_compstr3604_b);
    assign i_inc44_c_compstr3604_q = i_inc44_c_compstr3604_o[32:0];

    // bgTrunc_i_inc44_c_compstr3604_sel_x(BITSELECT,2303)@4
    assign bgTrunc_i_inc44_c_compstr3604_sel_x_b = i_inc44_c_compstr3604_q[31:0];

    // valid_fanout_reg10(REG,12638)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg10_q <= $unsigned(in_i_valid);
        end
    end

    // valid_fanout_reg9(REG,12637)@2 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg9_q <= $unsigned(redist513_sync_together3657_aunroll_x_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x(FIFODELAY,5004)@1 + 1
    // in i_valid@3
    // in i_write_pred@3
    // in i_data@4
    // out o_data@4
    assign i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_i_stall = ~ (valid_fanout_reg10_q & i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q);
    assign i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_i_valid = valid_fanout_reg9_q & redist517_i_llvm_fpga_push_i1_c_compstr_b7_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_i_data = bgTrunc_i_inc44_c_compstr3604_sel_x_b;
    assign i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_i_valid[0];
    assign i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(32),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x (
        .i_valid(i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_i_stall_bitsignaltemp),
        .i_data(bgTrunc_i_inc44_c_compstr3604_sel_x_b),
        .o_data(i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr0_i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr9_mux_x(MUX,4996)@4
    assign i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr0_i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr9_mux_x_s = redist510_i_llvm_fpga_forked_c_compstr_b7_forked_c_compstr3_out_buffer_out_4_q;
    always @(i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr0_i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr9_mux_x_s or i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_o_data or c_i32_03636_q)
    begin
        unique case (i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr0_i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr9_mux_x_s)
            1'b0 : i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr0_i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr9_mux_x_q = i_llvm_fpga_push_i32_i30_0285_push16_c_compstr0_i_llvm_fpga_push_i32_i30_0285_push16_c_compstr1_x_o_data;
            1'b1 : i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr0_i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr9_mux_x_q = c_i32_03636_q;
            default : i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr0_i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr9_mux_x_q = 32'b0;
        endcase
    end

    // i_idxprom36_c_compstr10_sel_x(BITSELECT,3968)@4
    assign i_idxprom36_c_compstr10_sel_x_b = {32'b00000000000000000000000000000000, i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr0_i_llvm_fpga_pop_i32_i30_0285_pop16_c_compstr9_mux_x_q[31:0]};

    // i_idxprom36_c_compstr10_vt_select_31(BITSELECT,8391)@4
    assign i_idxprom36_c_compstr10_vt_select_31_b = i_idxprom36_c_compstr10_sel_x_b[31:0];

    // i_idxprom36_c_compstr10_vt_join(BITJOIN,8390)@4
    assign i_idxprom36_c_compstr10_vt_join_q = {c_i32_03636_q, i_idxprom36_c_compstr10_vt_select_31_b};

    // i_value2_i_i157_i3_c_compstr0_dupName_0_trunc_sel_x(BITSELECT,6291)@4
    assign i_value2_i_i157_i3_c_compstr0_dupName_0_trunc_sel_x_b = i_idxprom36_c_compstr10_vt_join_q[12:0];

    // i_value2_i_i157_i3_c_compstr0_narrow_x(BITSELECT,6299)@4
    assign i_value2_i_i157_i3_c_compstr0_narrow_x_b = i_value2_i_i157_i3_c_compstr0_dupName_0_trunc_sel_x_b[3:0];

    // i_value2_i_i157_i3_c_compstr0_shift_join_x(BITJOIN,6300)@4
    assign i_value2_i_i157_i3_c_compstr0_shift_join_x_q = {i_value2_i_i157_i3_c_compstr0_narrow_x_b, i_value2_i_i157_i3_c_compstr0_c_i9_01_x_q};

    // i_value2_i_i157_i3_c_compstr0_add_x(ADD,6296)@4
    assign i_value2_i_i157_i3_c_compstr0_add_x_a = {1'b0, i_value2_i_i157_i3_c_compstr0_trunc_sel_x_merged_bit_select_b};
    assign i_value2_i_i157_i3_c_compstr0_add_x_b = {1'b0, i_value2_i_i157_i3_c_compstr0_shift_join_x_q};
    assign i_value2_i_i157_i3_c_compstr0_add_x_o = $unsigned(i_value2_i_i157_i3_c_compstr0_add_x_a) + $unsigned(i_value2_i_i157_i3_c_compstr0_add_x_b);
    assign i_value2_i_i157_i3_c_compstr0_add_x_q = i_value2_i_i157_i3_c_compstr0_add_x_o[13:0];

    // i_value2_i_i157_i3_c_compstr0_dupName_2_trunc_sel_x(BITSELECT,6292)@4
    assign i_value2_i_i157_i3_c_compstr0_dupName_2_trunc_sel_x_b = i_value2_i_i157_i3_c_compstr0_add_x_q[12:0];

    // i_value2_i_i157_i3_c_compstr0_append_upper_bits_x(BITJOIN,6297)@4
    assign i_value2_i_i157_i3_c_compstr0_append_upper_bits_x_q = {i_value2_i_i157_i3_c_compstr0_trunc_sel_x_merged_bit_select_c, i_value2_i_i157_i3_c_compstr0_dupName_2_trunc_sel_x_b};

    // i_value2_i_i157_i3_c_compstr14_vt_select_63(BITSELECT,12621)@4
    assign i_value2_i_i157_i3_c_compstr14_vt_select_63_b = i_value2_i_i157_i3_c_compstr0_append_upper_bits_x_q[63:9];

    // i_value2_i_i157_i3_c_compstr14_vt_join(BITJOIN,12620)@4
    assign i_value2_i_i157_i3_c_compstr14_vt_join_q = {i_value2_i_i157_i3_c_compstr14_vt_select_63_b, i_value2_i_i157_i3_c_compstr0_c_i9_01_x_q};

    // i_memcoalesce_bitcast_c_compstr_fpgaunique_533_c_compstr15_vt_select_63(BITSELECT,9037)@4
    assign i_memcoalesce_bitcast_c_compstr_fpgaunique_533_c_compstr15_vt_select_63_b = i_value2_i_i157_i3_c_compstr14_vt_join_q[63:9];

    // i_value2_i_i157_i3_c_compstr0_c_i9_01_x(CONSTANT,6298)
    assign i_value2_i_i157_i3_c_compstr0_c_i9_01_x_q = $unsigned(9'b000000000);

    // i_memcoalesce_bitcast_c_compstr_fpgaunique_533_c_compstr15_vt_join(BITJOIN,9036)@4
    assign i_memcoalesce_bitcast_c_compstr_fpgaunique_533_c_compstr15_vt_join_q = {i_memcoalesce_bitcast_c_compstr_fpgaunique_533_c_compstr15_vt_select_63_b, i_value2_i_i157_i3_c_compstr0_c_i9_01_x_q};

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x(BLACKBOX,4994)@4
    // out out_o_readdata_0_tpl@8
    // out out_o_readdata_1_tpl@8
    // out out_o_readdata_2_tpl@8
    // out out_o_readdata_3_tpl@8
    // out out_o_readdata_4_tpl@8
    // out out_o_readdata_5_tpl@8
    // out out_o_readdata_6_tpl@8
    // out out_o_readdata_7_tpl@8
    // out out_o_readdata_8_tpl@8
    // out out_o_readdata_9_tpl@8
    // out out_o_readdata_10_tpl@8
    // out out_o_readdata_11_tpl@8
    // out out_o_readdata_12_tpl@8
    // out out_o_readdata_13_tpl@8
    // out out_o_readdata_14_tpl@8
    // out out_o_readdata_15_tpl@8
    // out out_o_readdata_16_tpl@8
    // out out_o_readdata_17_tpl@8
    // out out_o_readdata_18_tpl@8
    // out out_o_readdata_19_tpl@8
    // out out_o_readdata_20_tpl@8
    // out out_o_readdata_21_tpl@8
    // out out_o_readdata_22_tpl@8
    // out out_o_readdata_23_tpl@8
    // out out_o_readdata_24_tpl@8
    // out out_o_readdata_25_tpl@8
    // out out_o_readdata_26_tpl@8
    // out out_o_readdata_27_tpl@8
    // out out_o_readdata_28_tpl@8
    // out out_o_readdata_29_tpl@8
    // out out_o_readdata_30_tpl@8
    // out out_o_readdata_31_tpl@8
    // out out_o_readdata_32_tpl@8
    // out out_o_readdata_33_tpl@8
    // out out_o_readdata_34_tpl@8
    // out out_o_readdata_35_tpl@8
    // out out_o_readdata_36_tpl@8
    // out out_o_readdata_37_tpl@8
    // out out_o_readdata_38_tpl@8
    // out out_o_readdata_39_tpl@8
    // out out_o_readdata_40_tpl@8
    // out out_o_readdata_41_tpl@8
    // out out_o_readdata_42_tpl@8
    // out out_o_readdata_43_tpl@8
    // out out_o_readdata_44_tpl@8
    // out out_o_readdata_45_tpl@8
    // out out_o_readdata_46_tpl@8
    // out out_o_readdata_47_tpl@8
    // out out_o_readdata_48_tpl@8
    // out out_o_readdata_49_tpl@8
    // out out_o_readdata_50_tpl@8
    // out out_o_readdata_51_tpl@8
    // out out_o_readdata_52_tpl@8
    // out out_o_readdata_53_tpl@8
    // out out_o_readdata_54_tpl@8
    // out out_o_readdata_55_tpl@8
    // out out_o_readdata_56_tpl@8
    // out out_o_readdata_57_tpl@8
    // out out_o_readdata_58_tpl@8
    // out out_o_readdata_59_tpl@8
    // out out_o_readdata_60_tpl@8
    // out out_o_readdata_61_tpl@8
    // out out_o_readdata_62_tpl@8
    // out out_o_readdata_63_tpl@8
    // out out_o_readdata_64_tpl@8
    // out out_o_readdata_65_tpl@8
    // out out_o_readdata_66_tpl@8
    // out out_o_readdata_67_tpl@8
    // out out_o_readdata_68_tpl@8
    // out out_o_readdata_69_tpl@8
    // out out_o_readdata_70_tpl@8
    // out out_o_readdata_71_tpl@8
    // out out_o_readdata_72_tpl@8
    // out out_o_readdata_73_tpl@8
    // out out_o_readdata_74_tpl@8
    // out out_o_readdata_75_tpl@8
    // out out_o_readdata_76_tpl@8
    // out out_o_readdata_77_tpl@8
    // out out_o_readdata_78_tpl@8
    // out out_o_readdata_79_tpl@8
    // out out_o_readdata_80_tpl@8
    // out out_o_readdata_81_tpl@8
    // out out_o_readdata_82_tpl@8
    // out out_o_readdata_83_tpl@8
    // out out_o_readdata_84_tpl@8
    // out out_o_readdata_85_tpl@8
    // out out_o_readdata_86_tpl@8
    // out out_o_readdata_87_tpl@8
    // out out_o_readdata_88_tpl@8
    // out out_o_readdata_89_tpl@8
    // out out_o_readdata_90_tpl@8
    // out out_o_readdata_91_tpl@8
    // out out_o_readdata_92_tpl@8
    // out out_o_readdata_93_tpl@8
    // out out_o_readdata_94_tpl@8
    // out out_o_readdata_95_tpl@8
    // out out_o_readdata_96_tpl@8
    // out out_o_readdata_97_tpl@8
    // out out_o_readdata_98_tpl@8
    // out out_o_readdata_99_tpl@8
    // out out_o_readdata_100_tpl@8
    // out out_o_readdata_101_tpl@8
    // out out_o_readdata_102_tpl@8
    // out out_o_readdata_103_tpl@8
    // out out_o_readdata_104_tpl@8
    // out out_o_readdata_105_tpl@8
    // out out_o_readdata_106_tpl@8
    // out out_o_readdata_107_tpl@8
    // out out_o_readdata_108_tpl@8
    // out out_o_readdata_109_tpl@8
    // out out_o_readdata_110_tpl@8
    // out out_o_readdata_111_tpl@8
    // out out_o_readdata_112_tpl@8
    // out out_o_readdata_113_tpl@8
    // out out_o_readdata_114_tpl@8
    // out out_o_readdata_115_tpl@8
    // out out_o_readdata_116_tpl@8
    // out out_o_readdata_117_tpl@8
    // out out_o_readdata_118_tpl@8
    // out out_o_readdata_119_tpl@8
    // out out_o_readdata_120_tpl@8
    // out out_o_readdata_121_tpl@8
    // out out_o_readdata_122_tpl@8
    // out out_o_readdata_123_tpl@8
    // out out_o_readdata_124_tpl@8
    // out out_o_readdata_125_tpl@8
    // out out_o_readdata_126_tpl@8
    // out out_o_readdata_127_tpl@8
    // out out_o_readdata_128_tpl@8
    // out out_o_readdata_129_tpl@8
    // out out_o_readdata_130_tpl@8
    // out out_o_readdata_131_tpl@8
    // out out_o_readdata_132_tpl@8
    // out out_o_readdata_133_tpl@8
    // out out_o_readdata_134_tpl@8
    // out out_o_readdata_135_tpl@8
    // out out_o_readdata_136_tpl@8
    // out out_o_readdata_137_tpl@8
    // out out_o_readdata_138_tpl@8
    // out out_o_readdata_139_tpl@8
    // out out_o_readdata_140_tpl@8
    // out out_o_readdata_141_tpl@8
    // out out_o_readdata_142_tpl@8
    // out out_o_readdata_143_tpl@8
    // out out_o_readdata_144_tpl@8
    // out out_o_readdata_145_tpl@8
    // out out_o_readdata_146_tpl@8
    // out out_o_readdata_147_tpl@8
    // out out_o_readdata_148_tpl@8
    // out out_o_readdata_149_tpl@8
    // out out_o_readdata_150_tpl@8
    // out out_o_readdata_151_tpl@8
    // out out_o_readdata_152_tpl@8
    // out out_o_readdata_153_tpl@8
    // out out_o_readdata_154_tpl@8
    // out out_o_readdata_155_tpl@8
    // out out_o_readdata_156_tpl@8
    // out out_o_readdata_157_tpl@8
    // out out_o_readdata_158_tpl@8
    // out out_o_readdata_159_tpl@8
    // out out_o_readdata_160_tpl@8
    // out out_o_readdata_161_tpl@8
    // out out_o_readdata_162_tpl@8
    // out out_o_readdata_163_tpl@8
    // out out_o_readdata_164_tpl@8
    // out out_o_readdata_165_tpl@8
    // out out_o_readdata_166_tpl@8
    // out out_o_readdata_167_tpl@8
    // out out_o_readdata_168_tpl@8
    // out out_o_readdata_169_tpl@8
    // out out_o_readdata_170_tpl@8
    // out out_o_readdata_171_tpl@8
    // out out_o_readdata_172_tpl@8
    // out out_o_readdata_173_tpl@8
    // out out_o_readdata_174_tpl@8
    // out out_o_readdata_175_tpl@8
    // out out_o_readdata_176_tpl@8
    // out out_o_readdata_177_tpl@8
    // out out_o_readdata_178_tpl@8
    // out out_o_readdata_179_tpl@8
    // out out_o_readdata_180_tpl@8
    // out out_o_readdata_181_tpl@8
    // out out_o_readdata_182_tpl@8
    // out out_o_readdata_183_tpl@8
    // out out_o_readdata_184_tpl@8
    // out out_o_readdata_185_tpl@8
    // out out_o_readdata_186_tpl@8
    // out out_o_readdata_187_tpl@8
    // out out_o_readdata_188_tpl@8
    // out out_o_readdata_189_tpl@8
    // out out_o_readdata_190_tpl@8
    // out out_o_readdata_191_tpl@8
    // out out_o_readdata_192_tpl@8
    // out out_o_readdata_193_tpl@8
    // out out_o_readdata_194_tpl@8
    // out out_o_readdata_195_tpl@8
    // out out_o_readdata_196_tpl@8
    // out out_o_readdata_197_tpl@8
    // out out_o_readdata_198_tpl@8
    // out out_o_readdata_199_tpl@8
    // out out_o_readdata_200_tpl@8
    // out out_o_readdata_201_tpl@8
    // out out_o_readdata_202_tpl@8
    // out out_o_readdata_203_tpl@8
    // out out_o_readdata_204_tpl@8
    // out out_o_readdata_205_tpl@8
    // out out_o_readdata_206_tpl@8
    // out out_o_readdata_207_tpl@8
    // out out_o_readdata_208_tpl@8
    // out out_o_readdata_209_tpl@8
    // out out_o_readdata_210_tpl@8
    // out out_o_readdata_211_tpl@8
    // out out_o_readdata_212_tpl@8
    // out out_o_readdata_213_tpl@8
    // out out_o_readdata_214_tpl@8
    // out out_o_readdata_215_tpl@8
    // out out_o_readdata_216_tpl@8
    // out out_o_readdata_217_tpl@8
    // out out_o_readdata_218_tpl@8
    // out out_o_readdata_219_tpl@8
    // out out_o_readdata_220_tpl@8
    // out out_o_readdata_221_tpl@8
    // out out_o_readdata_222_tpl@8
    // out out_o_readdata_223_tpl@8
    // out out_o_readdata_224_tpl@8
    // out out_o_readdata_225_tpl@8
    // out out_o_readdata_226_tpl@8
    // out out_o_readdata_227_tpl@8
    // out out_o_readdata_228_tpl@8
    // out out_o_readdata_229_tpl@8
    // out out_o_readdata_230_tpl@8
    // out out_o_readdata_231_tpl@8
    // out out_o_readdata_232_tpl@8
    // out out_o_readdata_233_tpl@8
    // out out_o_readdata_234_tpl@8
    // out out_o_readdata_235_tpl@8
    // out out_o_readdata_236_tpl@8
    // out out_o_readdata_237_tpl@8
    // out out_o_readdata_238_tpl@8
    // out out_o_readdata_239_tpl@8
    // out out_o_readdata_240_tpl@8
    // out out_o_readdata_241_tpl@8
    // out out_o_readdata_242_tpl@8
    // out out_o_readdata_243_tpl@8
    // out out_o_readdata_244_tpl@8
    // out out_o_readdata_245_tpl@8
    // out out_o_readdata_246_tpl@8
    // out out_o_readdata_247_tpl@8
    // out out_o_readdata_248_tpl@8
    // out out_o_readdata_249_tpl@8
    // out out_o_readdata_250_tpl@8
    // out out_o_readdata_251_tpl@8
    // out out_o_readdata_252_tpl@8
    // out out_o_readdata_253_tpl@8
    // out out_o_readdata_254_tpl@8
    // out out_o_readdata_255_tpl@8
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata@20000000
    // out out_o_almost_empty@8
    // out out_o_empty@8
    // out out_o_stall@8
    // out out_o_valid@8
    c_compSTR_i_llvm_fpga_mem_memcoalesce_lo0000ique_5138_c_compstr0 thei_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x (
        .in_almost_empty_in(GND_q),
        .in_empty_in(GND_q),
        .in_flush(in_flush),
        .in_i_address(i_memcoalesce_bitcast_c_compstr_fpgaunique_533_c_compstr15_vt_join_q),
        .in_i_predicate(i_c_compstr_b7_current_iter_isspec_c_compstr5_q),
        .in_i_stall(GND_q),
        .in_i_valid(valid_fanout_reg7_q),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdata(in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdata),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdatavalid(in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdatavalid),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_waitrequest(in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_waitrequest),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writeack(in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writeack),
        .out_o_readdata_0_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_0_tpl),
        .out_o_readdata_1_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_1_tpl),
        .out_o_readdata_2_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_2_tpl),
        .out_o_readdata_3_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_3_tpl),
        .out_o_readdata_4_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_4_tpl),
        .out_o_readdata_5_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_5_tpl),
        .out_o_readdata_6_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl),
        .out_o_readdata_7_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl),
        .out_o_readdata_8_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl),
        .out_o_readdata_9_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl),
        .out_o_readdata_10_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl),
        .out_o_readdata_11_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl),
        .out_o_readdata_12_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl),
        .out_o_readdata_13_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl),
        .out_o_readdata_14_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl),
        .out_o_readdata_15_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl),
        .out_o_readdata_16_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl),
        .out_o_readdata_17_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl),
        .out_o_readdata_18_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl),
        .out_o_readdata_19_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl),
        .out_o_readdata_20_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl),
        .out_o_readdata_21_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl),
        .out_o_readdata_22_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl),
        .out_o_readdata_23_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl),
        .out_o_readdata_24_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl),
        .out_o_readdata_25_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl),
        .out_o_readdata_26_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl),
        .out_o_readdata_27_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl),
        .out_o_readdata_28_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl),
        .out_o_readdata_29_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl),
        .out_o_readdata_30_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl),
        .out_o_readdata_31_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl),
        .out_o_readdata_32_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl),
        .out_o_readdata_33_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl),
        .out_o_readdata_34_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl),
        .out_o_readdata_35_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl),
        .out_o_readdata_36_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl),
        .out_o_readdata_37_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl),
        .out_o_readdata_38_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl),
        .out_o_readdata_39_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl),
        .out_o_readdata_40_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl),
        .out_o_readdata_41_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl),
        .out_o_readdata_42_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl),
        .out_o_readdata_43_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl),
        .out_o_readdata_44_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl),
        .out_o_readdata_45_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl),
        .out_o_readdata_46_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl),
        .out_o_readdata_47_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl),
        .out_o_readdata_48_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl),
        .out_o_readdata_49_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl),
        .out_o_readdata_50_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl),
        .out_o_readdata_51_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl),
        .out_o_readdata_52_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl),
        .out_o_readdata_53_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl),
        .out_o_readdata_54_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl),
        .out_o_readdata_55_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl),
        .out_o_readdata_56_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl),
        .out_o_readdata_57_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl),
        .out_o_readdata_58_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl),
        .out_o_readdata_59_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl),
        .out_o_readdata_60_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl),
        .out_o_readdata_61_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl),
        .out_o_readdata_62_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl),
        .out_o_readdata_63_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl),
        .out_o_readdata_64_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl),
        .out_o_readdata_65_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl),
        .out_o_readdata_66_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl),
        .out_o_readdata_67_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl),
        .out_o_readdata_68_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl),
        .out_o_readdata_69_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl),
        .out_o_readdata_70_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl),
        .out_o_readdata_71_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl),
        .out_o_readdata_72_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl),
        .out_o_readdata_73_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl),
        .out_o_readdata_74_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl),
        .out_o_readdata_75_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl),
        .out_o_readdata_76_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl),
        .out_o_readdata_77_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl),
        .out_o_readdata_78_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl),
        .out_o_readdata_79_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl),
        .out_o_readdata_80_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl),
        .out_o_readdata_81_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl),
        .out_o_readdata_82_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl),
        .out_o_readdata_83_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl),
        .out_o_readdata_84_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl),
        .out_o_readdata_85_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl),
        .out_o_readdata_86_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl),
        .out_o_readdata_87_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl),
        .out_o_readdata_88_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl),
        .out_o_readdata_89_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl),
        .out_o_readdata_90_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl),
        .out_o_readdata_91_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl),
        .out_o_readdata_92_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl),
        .out_o_readdata_93_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl),
        .out_o_readdata_94_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl),
        .out_o_readdata_95_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl),
        .out_o_readdata_96_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl),
        .out_o_readdata_97_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl),
        .out_o_readdata_98_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl),
        .out_o_readdata_99_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl),
        .out_o_readdata_100_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl),
        .out_o_readdata_101_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl),
        .out_o_readdata_102_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl),
        .out_o_readdata_103_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl),
        .out_o_readdata_104_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl),
        .out_o_readdata_105_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl),
        .out_o_readdata_106_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl),
        .out_o_readdata_107_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl),
        .out_o_readdata_108_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl),
        .out_o_readdata_109_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl),
        .out_o_readdata_110_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl),
        .out_o_readdata_111_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl),
        .out_o_readdata_112_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl),
        .out_o_readdata_113_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl),
        .out_o_readdata_114_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl),
        .out_o_readdata_115_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl),
        .out_o_readdata_116_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl),
        .out_o_readdata_117_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl),
        .out_o_readdata_118_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl),
        .out_o_readdata_119_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl),
        .out_o_readdata_120_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl),
        .out_o_readdata_121_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl),
        .out_o_readdata_122_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl),
        .out_o_readdata_123_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl),
        .out_o_readdata_124_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl),
        .out_o_readdata_125_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl),
        .out_o_readdata_126_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl),
        .out_o_readdata_127_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl),
        .out_o_readdata_128_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl),
        .out_o_readdata_129_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl),
        .out_o_readdata_130_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl),
        .out_o_readdata_131_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl),
        .out_o_readdata_132_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl),
        .out_o_readdata_133_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl),
        .out_o_readdata_134_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl),
        .out_o_readdata_135_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl),
        .out_o_readdata_136_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl),
        .out_o_readdata_137_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl),
        .out_o_readdata_138_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl),
        .out_o_readdata_139_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl),
        .out_o_readdata_140_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl),
        .out_o_readdata_141_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl),
        .out_o_readdata_142_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl),
        .out_o_readdata_143_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl),
        .out_o_readdata_144_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl),
        .out_o_readdata_145_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl),
        .out_o_readdata_146_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl),
        .out_o_readdata_147_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl),
        .out_o_readdata_148_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl),
        .out_o_readdata_149_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl),
        .out_o_readdata_150_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl),
        .out_o_readdata_151_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl),
        .out_o_readdata_152_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl),
        .out_o_readdata_153_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl),
        .out_o_readdata_154_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl),
        .out_o_readdata_155_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl),
        .out_o_readdata_156_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl),
        .out_o_readdata_157_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl),
        .out_o_readdata_158_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl),
        .out_o_readdata_159_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl),
        .out_o_readdata_160_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl),
        .out_o_readdata_161_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl),
        .out_o_readdata_162_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl),
        .out_o_readdata_163_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl),
        .out_o_readdata_164_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl),
        .out_o_readdata_165_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl),
        .out_o_readdata_166_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl),
        .out_o_readdata_167_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl),
        .out_o_readdata_168_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl),
        .out_o_readdata_169_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl),
        .out_o_readdata_170_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl),
        .out_o_readdata_171_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl),
        .out_o_readdata_172_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl),
        .out_o_readdata_173_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl),
        .out_o_readdata_174_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl),
        .out_o_readdata_175_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl),
        .out_o_readdata_176_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl),
        .out_o_readdata_177_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl),
        .out_o_readdata_178_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl),
        .out_o_readdata_179_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl),
        .out_o_readdata_180_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl),
        .out_o_readdata_181_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl),
        .out_o_readdata_182_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl),
        .out_o_readdata_183_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl),
        .out_o_readdata_184_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl),
        .out_o_readdata_185_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl),
        .out_o_readdata_186_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl),
        .out_o_readdata_187_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl),
        .out_o_readdata_188_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl),
        .out_o_readdata_189_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl),
        .out_o_readdata_190_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl),
        .out_o_readdata_191_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl),
        .out_o_readdata_192_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl),
        .out_o_readdata_193_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl),
        .out_o_readdata_194_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl),
        .out_o_readdata_195_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl),
        .out_o_readdata_196_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl),
        .out_o_readdata_197_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl),
        .out_o_readdata_198_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl),
        .out_o_readdata_199_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl),
        .out_o_readdata_200_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl),
        .out_o_readdata_201_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl),
        .out_o_readdata_202_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl),
        .out_o_readdata_203_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl),
        .out_o_readdata_204_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl),
        .out_o_readdata_205_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl),
        .out_o_readdata_206_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl),
        .out_o_readdata_207_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl),
        .out_o_readdata_208_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl),
        .out_o_readdata_209_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl),
        .out_o_readdata_210_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl),
        .out_o_readdata_211_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl),
        .out_o_readdata_212_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl),
        .out_o_readdata_213_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl),
        .out_o_readdata_214_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl),
        .out_o_readdata_215_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl),
        .out_o_readdata_216_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl),
        .out_o_readdata_217_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl),
        .out_o_readdata_218_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl),
        .out_o_readdata_219_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl),
        .out_o_readdata_220_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl),
        .out_o_readdata_221_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl),
        .out_o_readdata_222_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl),
        .out_o_readdata_223_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl),
        .out_o_readdata_224_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl),
        .out_o_readdata_225_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl),
        .out_o_readdata_226_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl),
        .out_o_readdata_227_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl),
        .out_o_readdata_228_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl),
        .out_o_readdata_229_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl),
        .out_o_readdata_230_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl),
        .out_o_readdata_231_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl),
        .out_o_readdata_232_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl),
        .out_o_readdata_233_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl),
        .out_o_readdata_234_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl),
        .out_o_readdata_235_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl),
        .out_o_readdata_236_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl),
        .out_o_readdata_237_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl),
        .out_o_readdata_238_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl),
        .out_o_readdata_239_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl),
        .out_o_readdata_240_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl),
        .out_o_readdata_241_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl),
        .out_o_readdata_242_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl),
        .out_o_readdata_243_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl),
        .out_o_readdata_244_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl),
        .out_o_readdata_245_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl),
        .out_o_readdata_246_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl),
        .out_o_readdata_247_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl),
        .out_o_readdata_248_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl),
        .out_o_readdata_249_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl),
        .out_o_readdata_250_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl),
        .out_o_readdata_251_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl),
        .out_o_readdata_252_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl),
        .out_o_readdata_253_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl),
        .out_o_readdata_254_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl),
        .out_o_readdata_255_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata),
        .out_o_almost_empty(),
        .out_o_empty(),
        .out_o_stall(),
        .out_o_valid(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_ext_sig_sync_out_x(GPOUT,2560)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount;

    // dupName_0_regfree_osync_x(GPOUT,2562)
    assign out_pipeline_dummy_out = i_llvm_fpga_pipeline_keep_going_c_compstr6_out_pipeline_dummy_out;

    // dupName_1_regfree_osync_x(GPOUT,2565)
    assign out_pipeline_forked_out = i_llvm_fpga_pipeline_keep_going_c_compstr6_out_pipeline_forked_out;

    // dupName_2_regfree_osync_x(GPOUT,2566)
    assign out_pipeline_valid_out = i_llvm_fpga_pipeline_keep_going_c_compstr6_out_pipeline_valid_out;

    // valid_fanout_reg0(REG,12628)@3 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg0_q <= $unsigned(redist514_sync_together3657_aunroll_x_in_i_valid_3_q);
        end
    end

    // redist1_valid_fanout_reg0_q_264(DELAY,28229)
    dspba_delay_ver #( .width(1), .depth(264), .reset_kind("SYNC"), .phase(4), .modulus(2), .reset_high(1'b0) )
    redist1_valid_fanout_reg0_q_264 ( .xin(valid_fanout_reg0_q), .xout(redist1_valid_fanout_reg0_q_264_q), .clk(clock), .aclr(resetn), .ena(1'b1) );

    // redist512_i_c_compstr_b7_current_iter_isspec_c_compstr5_q_264(DELAY,28740)
    dspba_delay_ver #( .width(1), .depth(264), .reset_kind("NONE"), .phase(0), .modulus(2), .reset_high(1'b0) )
    redist512_i_c_compstr_b7_current_iter_isspec_c_compstr5_q_264 ( .xin(i_c_compstr_b7_current_iter_isspec_c_compstr5_q), .xout(redist512_i_c_compstr_b7_current_iter_isspec_c_compstr5_q_264_q), .clk(clock), .aclr(resetn), .ena(1'b1) );

    // i_notcmp_c_compstr3609(LOGICAL,9040)@268
    assign i_notcmp_c_compstr3609_q = redist0_i_exitcond15_c_compstr3606_cmp_nsign_q_264_q ^ VCC_q;

    // redist0_i_exitcond15_c_compstr3606_cmp_nsign_q_264(DELAY,28228)
    dspba_delay_ver #( .width(1), .depth(264), .reset_kind("NONE"), .phase(0), .modulus(2), .reset_high(1'b0) )
    redist0_i_exitcond15_c_compstr3606_cmp_nsign_q_264 ( .xin(i_exitcond15_c_compstr3606_cmp_nsign_q), .xout(redist0_i_exitcond15_c_compstr3606_cmp_nsign_q_264_q), .clk(clock), .aclr(resetn), .ena(1'b1) );

    // i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28(CONSTANT,7243)
    assign i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q = $unsigned(13'b0000000000000);

    // rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x(CONSTANT,14957)
    assign rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q = $unsigned(8'b00000000);

    // rightShiftStage2Idx1Rng8_uid22849_dupName_509_i_unnamed_c_compstr0_shift_x(BITSELECT,22848)@267
    assign rightShiftStage2Idx1Rng8_uid22849_dupName_509_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22848_dupName_509_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22851_dupName_509_i_unnamed_c_compstr0_shift_x(BITJOIN,22850)@267
    assign rightShiftStage2Idx1_uid22851_dupName_509_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22849_dupName_509_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x(CONSTANT,14952)
    assign rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q = $unsigned(4'b0000);

    // rightShiftStage1Idx1Rng4_uid22844_dupName_509_i_unnamed_c_compstr0_shift_x(BITSELECT,22843)@267
    assign rightShiftStage1Idx1Rng4_uid22844_dupName_509_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22843_dupName_509_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22846_dupName_509_i_unnamed_c_compstr0_shift_x(BITJOIN,22845)@267
    assign rightShiftStage1Idx1_uid22846_dupName_509_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22844_dupName_509_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22839_dupName_509_i_unnamed_c_compstr0_shift_x(BITSELECT,22838)@267
    assign rightShiftStage0Idx1Rng1_uid22839_dupName_509_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_q[33:1];

    // rightShiftStage0Idx1_uid22841_dupName_509_i_unnamed_c_compstr0_shift_x(BITJOIN,22840)@267
    assign rightShiftStage0Idx1_uid22841_dupName_509_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22839_dupName_509_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25689_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x(BITSELECT,25688)@266
    assign leftShiftStage2Idx1Rng8_uid25689_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_in = leftShiftStage1_uid25687_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25689_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25689_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25690_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x(BITJOIN,25689)@266
    assign leftShiftStage2Idx1_uid25690_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25689_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25684_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x(BITSELECT,25683)@266
    assign leftShiftStage1Idx1Rng4_uid25684_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_in = leftShiftStage0_uid25682_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25684_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25684_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25685_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x(BITJOIN,25684)@266
    assign leftShiftStage1Idx1_uid25685_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25684_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25679_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x(BITSELECT,25678)@266
    assign leftShiftStage0Idx1Rng1_uid25679_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_127_c_compstr3590_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25679_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25679_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25680_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x(BITJOIN,25679)@266
    assign leftShiftStage0Idx1_uid25680_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25679_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22787_dupName_505_i_unnamed_c_compstr0_shift_x(BITSELECT,22786)@265
    assign rightShiftStage2Idx1Rng8_uid22787_dupName_505_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22786_dupName_505_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22789_dupName_505_i_unnamed_c_compstr0_shift_x(BITJOIN,22788)@265
    assign rightShiftStage2Idx1_uid22789_dupName_505_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22787_dupName_505_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22782_dupName_505_i_unnamed_c_compstr0_shift_x(BITSELECT,22781)@265
    assign rightShiftStage1Idx1Rng4_uid22782_dupName_505_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22781_dupName_505_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22784_dupName_505_i_unnamed_c_compstr0_shift_x(BITJOIN,22783)@265
    assign rightShiftStage1Idx1_uid22784_dupName_505_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22782_dupName_505_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22777_dupName_505_i_unnamed_c_compstr0_shift_x(BITSELECT,22776)@265
    assign rightShiftStage0Idx1Rng1_uid22777_dupName_505_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_q[33:1];

    // rightShiftStage0Idx1_uid22779_dupName_505_i_unnamed_c_compstr0_shift_x(BITJOIN,22778)@265
    assign rightShiftStage0Idx1_uid22779_dupName_505_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22777_dupName_505_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25671_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x(BITSELECT,25670)@264
    assign leftShiftStage2Idx1Rng8_uid25671_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_in = leftShiftStage1_uid25669_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25671_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25671_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25672_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x(BITJOIN,25671)@264
    assign leftShiftStage2Idx1_uid25672_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25671_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25666_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x(BITSELECT,25665)@264
    assign leftShiftStage1Idx1Rng4_uid25666_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_in = leftShiftStage0_uid25664_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25666_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25666_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25667_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x(BITJOIN,25666)@264
    assign leftShiftStage1Idx1_uid25667_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25666_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25661_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x(BITSELECT,25660)@264
    assign leftShiftStage0Idx1Rng1_uid25661_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_126_c_compstr3562_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25661_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25661_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25662_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x(BITJOIN,25661)@264
    assign leftShiftStage0Idx1_uid25662_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25661_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22725_dupName_501_i_unnamed_c_compstr0_shift_x(BITSELECT,22724)@263
    assign rightShiftStage2Idx1Rng8_uid22725_dupName_501_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22724_dupName_501_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22727_dupName_501_i_unnamed_c_compstr0_shift_x(BITJOIN,22726)@263
    assign rightShiftStage2Idx1_uid22727_dupName_501_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22725_dupName_501_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22720_dupName_501_i_unnamed_c_compstr0_shift_x(BITSELECT,22719)@263
    assign rightShiftStage1Idx1Rng4_uid22720_dupName_501_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22719_dupName_501_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22722_dupName_501_i_unnamed_c_compstr0_shift_x(BITJOIN,22721)@263
    assign rightShiftStage1Idx1_uid22722_dupName_501_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22720_dupName_501_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22715_dupName_501_i_unnamed_c_compstr0_shift_x(BITSELECT,22714)@263
    assign rightShiftStage0Idx1Rng1_uid22715_dupName_501_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_q[33:1];

    // rightShiftStage0Idx1_uid22717_dupName_501_i_unnamed_c_compstr0_shift_x(BITJOIN,22716)@263
    assign rightShiftStage0Idx1_uid22717_dupName_501_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22715_dupName_501_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25653_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x(BITSELECT,25652)@262
    assign leftShiftStage2Idx1Rng8_uid25653_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_in = leftShiftStage1_uid25651_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25653_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25653_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25654_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x(BITJOIN,25653)@262
    assign leftShiftStage2Idx1_uid25654_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25653_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25648_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x(BITSELECT,25647)@262
    assign leftShiftStage1Idx1Rng4_uid25648_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_in = leftShiftStage0_uid25646_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25648_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25648_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25649_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x(BITJOIN,25648)@262
    assign leftShiftStage1Idx1_uid25649_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25648_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25643_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x(BITSELECT,25642)@262
    assign leftShiftStage0Idx1Rng1_uid25643_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_125_c_compstr3534_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25643_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25643_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25644_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x(BITJOIN,25643)@262
    assign leftShiftStage0Idx1_uid25644_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25643_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22663_dupName_497_i_unnamed_c_compstr0_shift_x(BITSELECT,22662)@261
    assign rightShiftStage2Idx1Rng8_uid22663_dupName_497_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22662_dupName_497_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22665_dupName_497_i_unnamed_c_compstr0_shift_x(BITJOIN,22664)@261
    assign rightShiftStage2Idx1_uid22665_dupName_497_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22663_dupName_497_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22658_dupName_497_i_unnamed_c_compstr0_shift_x(BITSELECT,22657)@261
    assign rightShiftStage1Idx1Rng4_uid22658_dupName_497_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22657_dupName_497_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22660_dupName_497_i_unnamed_c_compstr0_shift_x(BITJOIN,22659)@261
    assign rightShiftStage1Idx1_uid22660_dupName_497_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22658_dupName_497_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22653_dupName_497_i_unnamed_c_compstr0_shift_x(BITSELECT,22652)@261
    assign rightShiftStage0Idx1Rng1_uid22653_dupName_497_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_q[33:1];

    // rightShiftStage0Idx1_uid22655_dupName_497_i_unnamed_c_compstr0_shift_x(BITJOIN,22654)@261
    assign rightShiftStage0Idx1_uid22655_dupName_497_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22653_dupName_497_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25635_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x(BITSELECT,25634)@260
    assign leftShiftStage2Idx1Rng8_uid25635_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_in = leftShiftStage1_uid25633_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25635_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25635_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25636_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x(BITJOIN,25635)@260
    assign leftShiftStage2Idx1_uid25636_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25635_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25630_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x(BITSELECT,25629)@260
    assign leftShiftStage1Idx1Rng4_uid25630_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_in = leftShiftStage0_uid25628_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25630_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25630_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25631_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x(BITJOIN,25630)@260
    assign leftShiftStage1Idx1_uid25631_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25630_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25625_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x(BITSELECT,25624)@260
    assign leftShiftStage0Idx1Rng1_uid25625_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_124_c_compstr3506_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25625_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25625_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25626_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x(BITJOIN,25625)@260
    assign leftShiftStage0Idx1_uid25626_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25625_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22601_dupName_493_i_unnamed_c_compstr0_shift_x(BITSELECT,22600)@259
    assign rightShiftStage2Idx1Rng8_uid22601_dupName_493_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22600_dupName_493_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22603_dupName_493_i_unnamed_c_compstr0_shift_x(BITJOIN,22602)@259
    assign rightShiftStage2Idx1_uid22603_dupName_493_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22601_dupName_493_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22596_dupName_493_i_unnamed_c_compstr0_shift_x(BITSELECT,22595)@259
    assign rightShiftStage1Idx1Rng4_uid22596_dupName_493_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22595_dupName_493_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22598_dupName_493_i_unnamed_c_compstr0_shift_x(BITJOIN,22597)@259
    assign rightShiftStage1Idx1_uid22598_dupName_493_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22596_dupName_493_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22591_dupName_493_i_unnamed_c_compstr0_shift_x(BITSELECT,22590)@259
    assign rightShiftStage0Idx1Rng1_uid22591_dupName_493_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_q[33:1];

    // rightShiftStage0Idx1_uid22593_dupName_493_i_unnamed_c_compstr0_shift_x(BITJOIN,22592)@259
    assign rightShiftStage0Idx1_uid22593_dupName_493_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22591_dupName_493_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25617_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x(BITSELECT,25616)@258
    assign leftShiftStage2Idx1Rng8_uid25617_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_in = leftShiftStage1_uid25615_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25617_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25617_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25618_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x(BITJOIN,25617)@258
    assign leftShiftStage2Idx1_uid25618_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25617_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25612_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x(BITSELECT,25611)@258
    assign leftShiftStage1Idx1Rng4_uid25612_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_in = leftShiftStage0_uid25610_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25612_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25612_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25613_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x(BITJOIN,25612)@258
    assign leftShiftStage1Idx1_uid25613_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25612_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25607_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x(BITSELECT,25606)@258
    assign leftShiftStage0Idx1Rng1_uid25607_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_123_c_compstr3478_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25607_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25607_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25608_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x(BITJOIN,25607)@258
    assign leftShiftStage0Idx1_uid25608_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25607_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22539_dupName_489_i_unnamed_c_compstr0_shift_x(BITSELECT,22538)@257
    assign rightShiftStage2Idx1Rng8_uid22539_dupName_489_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22538_dupName_489_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22541_dupName_489_i_unnamed_c_compstr0_shift_x(BITJOIN,22540)@257
    assign rightShiftStage2Idx1_uid22541_dupName_489_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22539_dupName_489_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22534_dupName_489_i_unnamed_c_compstr0_shift_x(BITSELECT,22533)@257
    assign rightShiftStage1Idx1Rng4_uid22534_dupName_489_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22533_dupName_489_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22536_dupName_489_i_unnamed_c_compstr0_shift_x(BITJOIN,22535)@257
    assign rightShiftStage1Idx1_uid22536_dupName_489_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22534_dupName_489_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22529_dupName_489_i_unnamed_c_compstr0_shift_x(BITSELECT,22528)@257
    assign rightShiftStage0Idx1Rng1_uid22529_dupName_489_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_q[33:1];

    // rightShiftStage0Idx1_uid22531_dupName_489_i_unnamed_c_compstr0_shift_x(BITJOIN,22530)@257
    assign rightShiftStage0Idx1_uid22531_dupName_489_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22529_dupName_489_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25599_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x(BITSELECT,25598)@256
    assign leftShiftStage2Idx1Rng8_uid25599_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_in = leftShiftStage1_uid25597_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25599_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25599_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25600_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x(BITJOIN,25599)@256
    assign leftShiftStage2Idx1_uid25600_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25599_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25594_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x(BITSELECT,25593)@256
    assign leftShiftStage1Idx1Rng4_uid25594_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_in = leftShiftStage0_uid25592_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25594_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25594_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25595_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x(BITJOIN,25594)@256
    assign leftShiftStage1Idx1_uid25595_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25594_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25589_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x(BITSELECT,25588)@256
    assign leftShiftStage0Idx1Rng1_uid25589_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_122_c_compstr3450_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25589_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25589_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25590_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x(BITJOIN,25589)@256
    assign leftShiftStage0Idx1_uid25590_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25589_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22477_dupName_485_i_unnamed_c_compstr0_shift_x(BITSELECT,22476)@255
    assign rightShiftStage2Idx1Rng8_uid22477_dupName_485_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22476_dupName_485_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22479_dupName_485_i_unnamed_c_compstr0_shift_x(BITJOIN,22478)@255
    assign rightShiftStage2Idx1_uid22479_dupName_485_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22477_dupName_485_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22472_dupName_485_i_unnamed_c_compstr0_shift_x(BITSELECT,22471)@255
    assign rightShiftStage1Idx1Rng4_uid22472_dupName_485_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22471_dupName_485_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22474_dupName_485_i_unnamed_c_compstr0_shift_x(BITJOIN,22473)@255
    assign rightShiftStage1Idx1_uid22474_dupName_485_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22472_dupName_485_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22467_dupName_485_i_unnamed_c_compstr0_shift_x(BITSELECT,22466)@255
    assign rightShiftStage0Idx1Rng1_uid22467_dupName_485_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_q[33:1];

    // rightShiftStage0Idx1_uid22469_dupName_485_i_unnamed_c_compstr0_shift_x(BITJOIN,22468)@255
    assign rightShiftStage0Idx1_uid22469_dupName_485_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22467_dupName_485_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25581_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x(BITSELECT,25580)@254
    assign leftShiftStage2Idx1Rng8_uid25581_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_in = leftShiftStage1_uid25579_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25581_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25581_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25582_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x(BITJOIN,25581)@254
    assign leftShiftStage2Idx1_uid25582_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25581_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25576_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x(BITSELECT,25575)@254
    assign leftShiftStage1Idx1Rng4_uid25576_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_in = leftShiftStage0_uid25574_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25576_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25576_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25577_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x(BITJOIN,25576)@254
    assign leftShiftStage1Idx1_uid25577_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25576_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25571_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x(BITSELECT,25570)@254
    assign leftShiftStage0Idx1Rng1_uid25571_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_121_c_compstr3422_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25571_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25571_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25572_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x(BITJOIN,25571)@254
    assign leftShiftStage0Idx1_uid25572_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25571_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22415_dupName_481_i_unnamed_c_compstr0_shift_x(BITSELECT,22414)@253
    assign rightShiftStage2Idx1Rng8_uid22415_dupName_481_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22414_dupName_481_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22417_dupName_481_i_unnamed_c_compstr0_shift_x(BITJOIN,22416)@253
    assign rightShiftStage2Idx1_uid22417_dupName_481_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22415_dupName_481_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22410_dupName_481_i_unnamed_c_compstr0_shift_x(BITSELECT,22409)@253
    assign rightShiftStage1Idx1Rng4_uid22410_dupName_481_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22409_dupName_481_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22412_dupName_481_i_unnamed_c_compstr0_shift_x(BITJOIN,22411)@253
    assign rightShiftStage1Idx1_uid22412_dupName_481_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22410_dupName_481_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22405_dupName_481_i_unnamed_c_compstr0_shift_x(BITSELECT,22404)@253
    assign rightShiftStage0Idx1Rng1_uid22405_dupName_481_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_q[33:1];

    // rightShiftStage0Idx1_uid22407_dupName_481_i_unnamed_c_compstr0_shift_x(BITJOIN,22406)@253
    assign rightShiftStage0Idx1_uid22407_dupName_481_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22405_dupName_481_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25563_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x(BITSELECT,25562)@252
    assign leftShiftStage2Idx1Rng8_uid25563_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_in = leftShiftStage1_uid25561_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25563_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25563_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25564_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x(BITJOIN,25563)@252
    assign leftShiftStage2Idx1_uid25564_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25563_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25558_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x(BITSELECT,25557)@252
    assign leftShiftStage1Idx1Rng4_uid25558_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_in = leftShiftStage0_uid25556_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25558_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25558_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25559_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x(BITJOIN,25558)@252
    assign leftShiftStage1Idx1_uid25559_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25558_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25553_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x(BITSELECT,25552)@252
    assign leftShiftStage0Idx1Rng1_uid25553_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_120_c_compstr3394_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25553_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25553_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25554_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x(BITJOIN,25553)@252
    assign leftShiftStage0Idx1_uid25554_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25553_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22353_dupName_477_i_unnamed_c_compstr0_shift_x(BITSELECT,22352)@251
    assign rightShiftStage2Idx1Rng8_uid22353_dupName_477_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22352_dupName_477_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22355_dupName_477_i_unnamed_c_compstr0_shift_x(BITJOIN,22354)@251
    assign rightShiftStage2Idx1_uid22355_dupName_477_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22353_dupName_477_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22348_dupName_477_i_unnamed_c_compstr0_shift_x(BITSELECT,22347)@251
    assign rightShiftStage1Idx1Rng4_uid22348_dupName_477_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22347_dupName_477_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22350_dupName_477_i_unnamed_c_compstr0_shift_x(BITJOIN,22349)@251
    assign rightShiftStage1Idx1_uid22350_dupName_477_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22348_dupName_477_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22343_dupName_477_i_unnamed_c_compstr0_shift_x(BITSELECT,22342)@251
    assign rightShiftStage0Idx1Rng1_uid22343_dupName_477_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_q[33:1];

    // rightShiftStage0Idx1_uid22345_dupName_477_i_unnamed_c_compstr0_shift_x(BITJOIN,22344)@251
    assign rightShiftStage0Idx1_uid22345_dupName_477_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22343_dupName_477_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25527_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x(BITSELECT,25526)@250
    assign leftShiftStage2Idx1Rng8_uid25527_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_in = leftShiftStage1_uid25525_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25527_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25527_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25528_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x(BITJOIN,25527)@250
    assign leftShiftStage2Idx1_uid25528_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25527_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25522_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x(BITSELECT,25521)@250
    assign leftShiftStage1Idx1Rng4_uid25522_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_in = leftShiftStage0_uid25520_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25522_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25522_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25523_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x(BITJOIN,25522)@250
    assign leftShiftStage1Idx1_uid25523_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25522_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25517_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x(BITSELECT,25516)@250
    assign leftShiftStage0Idx1Rng1_uid25517_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_119_c_compstr3366_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25517_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25517_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25518_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x(BITJOIN,25517)@250
    assign leftShiftStage0Idx1_uid25518_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25517_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22291_dupName_473_i_unnamed_c_compstr0_shift_x(BITSELECT,22290)@249
    assign rightShiftStage2Idx1Rng8_uid22291_dupName_473_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22290_dupName_473_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22293_dupName_473_i_unnamed_c_compstr0_shift_x(BITJOIN,22292)@249
    assign rightShiftStage2Idx1_uid22293_dupName_473_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22291_dupName_473_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22286_dupName_473_i_unnamed_c_compstr0_shift_x(BITSELECT,22285)@249
    assign rightShiftStage1Idx1Rng4_uid22286_dupName_473_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22285_dupName_473_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22288_dupName_473_i_unnamed_c_compstr0_shift_x(BITJOIN,22287)@249
    assign rightShiftStage1Idx1_uid22288_dupName_473_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22286_dupName_473_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22281_dupName_473_i_unnamed_c_compstr0_shift_x(BITSELECT,22280)@249
    assign rightShiftStage0Idx1Rng1_uid22281_dupName_473_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_q[33:1];

    // rightShiftStage0Idx1_uid22283_dupName_473_i_unnamed_c_compstr0_shift_x(BITJOIN,22282)@249
    assign rightShiftStage0Idx1_uid22283_dupName_473_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22281_dupName_473_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25509_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x(BITSELECT,25508)@248
    assign leftShiftStage2Idx1Rng8_uid25509_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_in = leftShiftStage1_uid25507_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25509_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25509_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25510_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x(BITJOIN,25509)@248
    assign leftShiftStage2Idx1_uid25510_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25509_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25504_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x(BITSELECT,25503)@248
    assign leftShiftStage1Idx1Rng4_uid25504_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_in = leftShiftStage0_uid25502_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25504_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25504_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25505_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x(BITJOIN,25504)@248
    assign leftShiftStage1Idx1_uid25505_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25504_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25499_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x(BITSELECT,25498)@248
    assign leftShiftStage0Idx1Rng1_uid25499_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_118_c_compstr3338_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25499_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25499_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25500_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x(BITJOIN,25499)@248
    assign leftShiftStage0Idx1_uid25500_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25499_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22229_dupName_469_i_unnamed_c_compstr0_shift_x(BITSELECT,22228)@247
    assign rightShiftStage2Idx1Rng8_uid22229_dupName_469_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22228_dupName_469_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22231_dupName_469_i_unnamed_c_compstr0_shift_x(BITJOIN,22230)@247
    assign rightShiftStage2Idx1_uid22231_dupName_469_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22229_dupName_469_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22224_dupName_469_i_unnamed_c_compstr0_shift_x(BITSELECT,22223)@247
    assign rightShiftStage1Idx1Rng4_uid22224_dupName_469_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22223_dupName_469_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22226_dupName_469_i_unnamed_c_compstr0_shift_x(BITJOIN,22225)@247
    assign rightShiftStage1Idx1_uid22226_dupName_469_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22224_dupName_469_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22219_dupName_469_i_unnamed_c_compstr0_shift_x(BITSELECT,22218)@247
    assign rightShiftStage0Idx1Rng1_uid22219_dupName_469_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_q[33:1];

    // rightShiftStage0Idx1_uid22221_dupName_469_i_unnamed_c_compstr0_shift_x(BITJOIN,22220)@247
    assign rightShiftStage0Idx1_uid22221_dupName_469_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22219_dupName_469_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25491_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x(BITSELECT,25490)@246
    assign leftShiftStage2Idx1Rng8_uid25491_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_in = leftShiftStage1_uid25489_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25491_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25491_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25492_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x(BITJOIN,25491)@246
    assign leftShiftStage2Idx1_uid25492_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25491_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25486_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x(BITSELECT,25485)@246
    assign leftShiftStage1Idx1Rng4_uid25486_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_in = leftShiftStage0_uid25484_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25486_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25486_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25487_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x(BITJOIN,25486)@246
    assign leftShiftStage1Idx1_uid25487_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25486_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25481_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x(BITSELECT,25480)@246
    assign leftShiftStage0Idx1Rng1_uid25481_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_117_c_compstr3310_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25481_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25481_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25482_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x(BITJOIN,25481)@246
    assign leftShiftStage0Idx1_uid25482_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25481_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22167_dupName_465_i_unnamed_c_compstr0_shift_x(BITSELECT,22166)@245
    assign rightShiftStage2Idx1Rng8_uid22167_dupName_465_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22166_dupName_465_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22169_dupName_465_i_unnamed_c_compstr0_shift_x(BITJOIN,22168)@245
    assign rightShiftStage2Idx1_uid22169_dupName_465_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22167_dupName_465_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22162_dupName_465_i_unnamed_c_compstr0_shift_x(BITSELECT,22161)@245
    assign rightShiftStage1Idx1Rng4_uid22162_dupName_465_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22161_dupName_465_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22164_dupName_465_i_unnamed_c_compstr0_shift_x(BITJOIN,22163)@245
    assign rightShiftStage1Idx1_uid22164_dupName_465_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22162_dupName_465_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22157_dupName_465_i_unnamed_c_compstr0_shift_x(BITSELECT,22156)@245
    assign rightShiftStage0Idx1Rng1_uid22157_dupName_465_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_q[33:1];

    // rightShiftStage0Idx1_uid22159_dupName_465_i_unnamed_c_compstr0_shift_x(BITJOIN,22158)@245
    assign rightShiftStage0Idx1_uid22159_dupName_465_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22157_dupName_465_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25473_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x(BITSELECT,25472)@244
    assign leftShiftStage2Idx1Rng8_uid25473_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_in = leftShiftStage1_uid25471_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25473_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25473_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25474_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x(BITJOIN,25473)@244
    assign leftShiftStage2Idx1_uid25474_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25473_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25468_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x(BITSELECT,25467)@244
    assign leftShiftStage1Idx1Rng4_uid25468_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_in = leftShiftStage0_uid25466_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25468_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25468_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25469_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x(BITJOIN,25468)@244
    assign leftShiftStage1Idx1_uid25469_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25468_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25463_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x(BITSELECT,25462)@244
    assign leftShiftStage0Idx1Rng1_uid25463_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_116_c_compstr3282_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25463_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25463_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25464_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x(BITJOIN,25463)@244
    assign leftShiftStage0Idx1_uid25464_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25463_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22105_dupName_461_i_unnamed_c_compstr0_shift_x(BITSELECT,22104)@243
    assign rightShiftStage2Idx1Rng8_uid22105_dupName_461_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22104_dupName_461_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22107_dupName_461_i_unnamed_c_compstr0_shift_x(BITJOIN,22106)@243
    assign rightShiftStage2Idx1_uid22107_dupName_461_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22105_dupName_461_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22100_dupName_461_i_unnamed_c_compstr0_shift_x(BITSELECT,22099)@243
    assign rightShiftStage1Idx1Rng4_uid22100_dupName_461_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22099_dupName_461_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22102_dupName_461_i_unnamed_c_compstr0_shift_x(BITJOIN,22101)@243
    assign rightShiftStage1Idx1_uid22102_dupName_461_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22100_dupName_461_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22095_dupName_461_i_unnamed_c_compstr0_shift_x(BITSELECT,22094)@243
    assign rightShiftStage0Idx1Rng1_uid22095_dupName_461_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_q[33:1];

    // rightShiftStage0Idx1_uid22097_dupName_461_i_unnamed_c_compstr0_shift_x(BITJOIN,22096)@243
    assign rightShiftStage0Idx1_uid22097_dupName_461_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22095_dupName_461_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25455_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x(BITSELECT,25454)@242
    assign leftShiftStage2Idx1Rng8_uid25455_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_in = leftShiftStage1_uid25453_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25455_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25455_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25456_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x(BITJOIN,25455)@242
    assign leftShiftStage2Idx1_uid25456_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25455_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25450_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x(BITSELECT,25449)@242
    assign leftShiftStage1Idx1Rng4_uid25450_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_in = leftShiftStage0_uid25448_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25450_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25450_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25451_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x(BITJOIN,25450)@242
    assign leftShiftStage1Idx1_uid25451_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25450_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25445_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x(BITSELECT,25444)@242
    assign leftShiftStage0Idx1Rng1_uid25445_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_115_c_compstr3254_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25445_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25445_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25446_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x(BITJOIN,25445)@242
    assign leftShiftStage0Idx1_uid25446_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25445_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22043_dupName_457_i_unnamed_c_compstr0_shift_x(BITSELECT,22042)@241
    assign rightShiftStage2Idx1Rng8_uid22043_dupName_457_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22042_dupName_457_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22045_dupName_457_i_unnamed_c_compstr0_shift_x(BITJOIN,22044)@241
    assign rightShiftStage2Idx1_uid22045_dupName_457_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22043_dupName_457_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22038_dupName_457_i_unnamed_c_compstr0_shift_x(BITSELECT,22037)@241
    assign rightShiftStage1Idx1Rng4_uid22038_dupName_457_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22037_dupName_457_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22040_dupName_457_i_unnamed_c_compstr0_shift_x(BITJOIN,22039)@241
    assign rightShiftStage1Idx1_uid22040_dupName_457_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22038_dupName_457_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22033_dupName_457_i_unnamed_c_compstr0_shift_x(BITSELECT,22032)@241
    assign rightShiftStage0Idx1Rng1_uid22033_dupName_457_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_q[33:1];

    // rightShiftStage0Idx1_uid22035_dupName_457_i_unnamed_c_compstr0_shift_x(BITJOIN,22034)@241
    assign rightShiftStage0Idx1_uid22035_dupName_457_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22033_dupName_457_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25437_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x(BITSELECT,25436)@240
    assign leftShiftStage2Idx1Rng8_uid25437_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_in = leftShiftStage1_uid25435_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25437_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25437_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25438_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x(BITJOIN,25437)@240
    assign leftShiftStage2Idx1_uid25438_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25437_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25432_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x(BITSELECT,25431)@240
    assign leftShiftStage1Idx1Rng4_uid25432_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_in = leftShiftStage0_uid25430_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25432_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25432_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25433_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x(BITJOIN,25432)@240
    assign leftShiftStage1Idx1_uid25433_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25432_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25427_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x(BITSELECT,25426)@240
    assign leftShiftStage0Idx1Rng1_uid25427_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_114_c_compstr3226_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25427_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25427_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25428_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x(BITJOIN,25427)@240
    assign leftShiftStage0Idx1_uid25428_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25427_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21981_dupName_453_i_unnamed_c_compstr0_shift_x(BITSELECT,21980)@239
    assign rightShiftStage2Idx1Rng8_uid21981_dupName_453_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21980_dupName_453_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21983_dupName_453_i_unnamed_c_compstr0_shift_x(BITJOIN,21982)@239
    assign rightShiftStage2Idx1_uid21983_dupName_453_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21981_dupName_453_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21976_dupName_453_i_unnamed_c_compstr0_shift_x(BITSELECT,21975)@239
    assign rightShiftStage1Idx1Rng4_uid21976_dupName_453_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21975_dupName_453_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21978_dupName_453_i_unnamed_c_compstr0_shift_x(BITJOIN,21977)@239
    assign rightShiftStage1Idx1_uid21978_dupName_453_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21976_dupName_453_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21971_dupName_453_i_unnamed_c_compstr0_shift_x(BITSELECT,21970)@239
    assign rightShiftStage0Idx1Rng1_uid21971_dupName_453_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_q[33:1];

    // rightShiftStage0Idx1_uid21973_dupName_453_i_unnamed_c_compstr0_shift_x(BITJOIN,21972)@239
    assign rightShiftStage0Idx1_uid21973_dupName_453_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21971_dupName_453_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25419_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x(BITSELECT,25418)@238
    assign leftShiftStage2Idx1Rng8_uid25419_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_in = leftShiftStage1_uid25417_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25419_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25419_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25420_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x(BITJOIN,25419)@238
    assign leftShiftStage2Idx1_uid25420_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25419_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25414_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x(BITSELECT,25413)@238
    assign leftShiftStage1Idx1Rng4_uid25414_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_in = leftShiftStage0_uid25412_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25414_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25414_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25415_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x(BITJOIN,25414)@238
    assign leftShiftStage1Idx1_uid25415_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25414_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25409_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x(BITSELECT,25408)@238
    assign leftShiftStage0Idx1Rng1_uid25409_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_113_c_compstr3198_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25409_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25409_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25410_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x(BITJOIN,25409)@238
    assign leftShiftStage0Idx1_uid25410_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25409_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21919_dupName_449_i_unnamed_c_compstr0_shift_x(BITSELECT,21918)@237
    assign rightShiftStage2Idx1Rng8_uid21919_dupName_449_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21918_dupName_449_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21921_dupName_449_i_unnamed_c_compstr0_shift_x(BITJOIN,21920)@237
    assign rightShiftStage2Idx1_uid21921_dupName_449_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21919_dupName_449_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21914_dupName_449_i_unnamed_c_compstr0_shift_x(BITSELECT,21913)@237
    assign rightShiftStage1Idx1Rng4_uid21914_dupName_449_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21913_dupName_449_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21916_dupName_449_i_unnamed_c_compstr0_shift_x(BITJOIN,21915)@237
    assign rightShiftStage1Idx1_uid21916_dupName_449_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21914_dupName_449_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21909_dupName_449_i_unnamed_c_compstr0_shift_x(BITSELECT,21908)@237
    assign rightShiftStage0Idx1Rng1_uid21909_dupName_449_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_q[33:1];

    // rightShiftStage0Idx1_uid21911_dupName_449_i_unnamed_c_compstr0_shift_x(BITJOIN,21910)@237
    assign rightShiftStage0Idx1_uid21911_dupName_449_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21909_dupName_449_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25401_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x(BITSELECT,25400)@236
    assign leftShiftStage2Idx1Rng8_uid25401_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_in = leftShiftStage1_uid25399_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25401_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25401_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25402_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x(BITJOIN,25401)@236
    assign leftShiftStage2Idx1_uid25402_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25401_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25396_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x(BITSELECT,25395)@236
    assign leftShiftStage1Idx1Rng4_uid25396_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_in = leftShiftStage0_uid25394_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25396_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25396_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25397_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x(BITJOIN,25396)@236
    assign leftShiftStage1Idx1_uid25397_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25396_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25391_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x(BITSELECT,25390)@236
    assign leftShiftStage0Idx1Rng1_uid25391_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_112_c_compstr3170_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25391_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25391_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25392_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x(BITJOIN,25391)@236
    assign leftShiftStage0Idx1_uid25392_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25391_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21857_dupName_445_i_unnamed_c_compstr0_shift_x(BITSELECT,21856)@235
    assign rightShiftStage2Idx1Rng8_uid21857_dupName_445_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21856_dupName_445_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21859_dupName_445_i_unnamed_c_compstr0_shift_x(BITJOIN,21858)@235
    assign rightShiftStage2Idx1_uid21859_dupName_445_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21857_dupName_445_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21852_dupName_445_i_unnamed_c_compstr0_shift_x(BITSELECT,21851)@235
    assign rightShiftStage1Idx1Rng4_uid21852_dupName_445_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21851_dupName_445_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21854_dupName_445_i_unnamed_c_compstr0_shift_x(BITJOIN,21853)@235
    assign rightShiftStage1Idx1_uid21854_dupName_445_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21852_dupName_445_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21847_dupName_445_i_unnamed_c_compstr0_shift_x(BITSELECT,21846)@235
    assign rightShiftStage0Idx1Rng1_uid21847_dupName_445_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_q[33:1];

    // rightShiftStage0Idx1_uid21849_dupName_445_i_unnamed_c_compstr0_shift_x(BITJOIN,21848)@235
    assign rightShiftStage0Idx1_uid21849_dupName_445_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21847_dupName_445_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25383_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x(BITSELECT,25382)@234
    assign leftShiftStage2Idx1Rng8_uid25383_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_in = leftShiftStage1_uid25381_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25383_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25383_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25384_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x(BITJOIN,25383)@234
    assign leftShiftStage2Idx1_uid25384_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25383_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25378_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x(BITSELECT,25377)@234
    assign leftShiftStage1Idx1Rng4_uid25378_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_in = leftShiftStage0_uid25376_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25378_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25378_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25379_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x(BITJOIN,25378)@234
    assign leftShiftStage1Idx1_uid25379_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25378_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25373_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x(BITSELECT,25372)@234
    assign leftShiftStage0Idx1Rng1_uid25373_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_111_c_compstr3142_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25373_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25373_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25374_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x(BITJOIN,25373)@234
    assign leftShiftStage0Idx1_uid25374_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25373_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21795_dupName_441_i_unnamed_c_compstr0_shift_x(BITSELECT,21794)@233
    assign rightShiftStage2Idx1Rng8_uid21795_dupName_441_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21794_dupName_441_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21797_dupName_441_i_unnamed_c_compstr0_shift_x(BITJOIN,21796)@233
    assign rightShiftStage2Idx1_uid21797_dupName_441_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21795_dupName_441_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21790_dupName_441_i_unnamed_c_compstr0_shift_x(BITSELECT,21789)@233
    assign rightShiftStage1Idx1Rng4_uid21790_dupName_441_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21789_dupName_441_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21792_dupName_441_i_unnamed_c_compstr0_shift_x(BITJOIN,21791)@233
    assign rightShiftStage1Idx1_uid21792_dupName_441_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21790_dupName_441_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21785_dupName_441_i_unnamed_c_compstr0_shift_x(BITSELECT,21784)@233
    assign rightShiftStage0Idx1Rng1_uid21785_dupName_441_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_q[33:1];

    // rightShiftStage0Idx1_uid21787_dupName_441_i_unnamed_c_compstr0_shift_x(BITJOIN,21786)@233
    assign rightShiftStage0Idx1_uid21787_dupName_441_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21785_dupName_441_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25365_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x(BITSELECT,25364)@232
    assign leftShiftStage2Idx1Rng8_uid25365_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_in = leftShiftStage1_uid25363_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25365_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25365_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25366_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x(BITJOIN,25365)@232
    assign leftShiftStage2Idx1_uid25366_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25365_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25360_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x(BITSELECT,25359)@232
    assign leftShiftStage1Idx1Rng4_uid25360_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_in = leftShiftStage0_uid25358_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25360_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25360_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25361_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x(BITJOIN,25360)@232
    assign leftShiftStage1Idx1_uid25361_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25360_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25355_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x(BITSELECT,25354)@232
    assign leftShiftStage0Idx1Rng1_uid25355_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_110_c_compstr3114_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25355_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25355_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25356_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x(BITJOIN,25355)@232
    assign leftShiftStage0Idx1_uid25356_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25355_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21733_dupName_437_i_unnamed_c_compstr0_shift_x(BITSELECT,21732)@231
    assign rightShiftStage2Idx1Rng8_uid21733_dupName_437_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21732_dupName_437_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21735_dupName_437_i_unnamed_c_compstr0_shift_x(BITJOIN,21734)@231
    assign rightShiftStage2Idx1_uid21735_dupName_437_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21733_dupName_437_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21728_dupName_437_i_unnamed_c_compstr0_shift_x(BITSELECT,21727)@231
    assign rightShiftStage1Idx1Rng4_uid21728_dupName_437_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21727_dupName_437_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21730_dupName_437_i_unnamed_c_compstr0_shift_x(BITJOIN,21729)@231
    assign rightShiftStage1Idx1_uid21730_dupName_437_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21728_dupName_437_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21723_dupName_437_i_unnamed_c_compstr0_shift_x(BITSELECT,21722)@231
    assign rightShiftStage0Idx1Rng1_uid21723_dupName_437_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_q[33:1];

    // rightShiftStage0Idx1_uid21725_dupName_437_i_unnamed_c_compstr0_shift_x(BITJOIN,21724)@231
    assign rightShiftStage0Idx1_uid21725_dupName_437_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21723_dupName_437_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25329_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x(BITSELECT,25328)@230
    assign leftShiftStage2Idx1Rng8_uid25329_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_in = leftShiftStage1_uid25327_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25329_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25329_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25330_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x(BITJOIN,25329)@230
    assign leftShiftStage2Idx1_uid25330_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25329_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25324_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x(BITSELECT,25323)@230
    assign leftShiftStage1Idx1Rng4_uid25324_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_in = leftShiftStage0_uid25322_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25324_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25324_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25325_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x(BITJOIN,25324)@230
    assign leftShiftStage1Idx1_uid25325_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25324_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25319_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x(BITSELECT,25318)@230
    assign leftShiftStage0Idx1Rng1_uid25319_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_109_c_compstr3086_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25319_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25319_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25320_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x(BITJOIN,25319)@230
    assign leftShiftStage0Idx1_uid25320_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25319_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21671_dupName_433_i_unnamed_c_compstr0_shift_x(BITSELECT,21670)@229
    assign rightShiftStage2Idx1Rng8_uid21671_dupName_433_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21670_dupName_433_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21673_dupName_433_i_unnamed_c_compstr0_shift_x(BITJOIN,21672)@229
    assign rightShiftStage2Idx1_uid21673_dupName_433_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21671_dupName_433_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21666_dupName_433_i_unnamed_c_compstr0_shift_x(BITSELECT,21665)@229
    assign rightShiftStage1Idx1Rng4_uid21666_dupName_433_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21665_dupName_433_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21668_dupName_433_i_unnamed_c_compstr0_shift_x(BITJOIN,21667)@229
    assign rightShiftStage1Idx1_uid21668_dupName_433_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21666_dupName_433_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21661_dupName_433_i_unnamed_c_compstr0_shift_x(BITSELECT,21660)@229
    assign rightShiftStage0Idx1Rng1_uid21661_dupName_433_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_q[33:1];

    // rightShiftStage0Idx1_uid21663_dupName_433_i_unnamed_c_compstr0_shift_x(BITJOIN,21662)@229
    assign rightShiftStage0Idx1_uid21663_dupName_433_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21661_dupName_433_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25311_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x(BITSELECT,25310)@228
    assign leftShiftStage2Idx1Rng8_uid25311_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_in = leftShiftStage1_uid25309_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25311_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25311_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25312_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x(BITJOIN,25311)@228
    assign leftShiftStage2Idx1_uid25312_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25311_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25306_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x(BITSELECT,25305)@228
    assign leftShiftStage1Idx1Rng4_uid25306_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_in = leftShiftStage0_uid25304_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25306_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25306_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25307_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x(BITJOIN,25306)@228
    assign leftShiftStage1Idx1_uid25307_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25306_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25301_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x(BITSELECT,25300)@228
    assign leftShiftStage0Idx1Rng1_uid25301_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_108_c_compstr3058_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25301_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25301_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25302_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x(BITJOIN,25301)@228
    assign leftShiftStage0Idx1_uid25302_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25301_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21609_dupName_429_i_unnamed_c_compstr0_shift_x(BITSELECT,21608)@227
    assign rightShiftStage2Idx1Rng8_uid21609_dupName_429_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21608_dupName_429_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21611_dupName_429_i_unnamed_c_compstr0_shift_x(BITJOIN,21610)@227
    assign rightShiftStage2Idx1_uid21611_dupName_429_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21609_dupName_429_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21604_dupName_429_i_unnamed_c_compstr0_shift_x(BITSELECT,21603)@227
    assign rightShiftStage1Idx1Rng4_uid21604_dupName_429_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21603_dupName_429_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21606_dupName_429_i_unnamed_c_compstr0_shift_x(BITJOIN,21605)@227
    assign rightShiftStage1Idx1_uid21606_dupName_429_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21604_dupName_429_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21599_dupName_429_i_unnamed_c_compstr0_shift_x(BITSELECT,21598)@227
    assign rightShiftStage0Idx1Rng1_uid21599_dupName_429_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_q[33:1];

    // rightShiftStage0Idx1_uid21601_dupName_429_i_unnamed_c_compstr0_shift_x(BITJOIN,21600)@227
    assign rightShiftStage0Idx1_uid21601_dupName_429_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21599_dupName_429_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25293_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x(BITSELECT,25292)@226
    assign leftShiftStage2Idx1Rng8_uid25293_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_in = leftShiftStage1_uid25291_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25293_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25293_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25294_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x(BITJOIN,25293)@226
    assign leftShiftStage2Idx1_uid25294_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25293_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25288_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x(BITSELECT,25287)@226
    assign leftShiftStage1Idx1Rng4_uid25288_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_in = leftShiftStage0_uid25286_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25288_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25288_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25289_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x(BITJOIN,25288)@226
    assign leftShiftStage1Idx1_uid25289_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25288_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25283_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x(BITSELECT,25282)@226
    assign leftShiftStage0Idx1Rng1_uid25283_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_107_c_compstr3030_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25283_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25283_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25284_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x(BITJOIN,25283)@226
    assign leftShiftStage0Idx1_uid25284_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25283_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21547_dupName_425_i_unnamed_c_compstr0_shift_x(BITSELECT,21546)@225
    assign rightShiftStage2Idx1Rng8_uid21547_dupName_425_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21546_dupName_425_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21549_dupName_425_i_unnamed_c_compstr0_shift_x(BITJOIN,21548)@225
    assign rightShiftStage2Idx1_uid21549_dupName_425_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21547_dupName_425_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21542_dupName_425_i_unnamed_c_compstr0_shift_x(BITSELECT,21541)@225
    assign rightShiftStage1Idx1Rng4_uid21542_dupName_425_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21541_dupName_425_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21544_dupName_425_i_unnamed_c_compstr0_shift_x(BITJOIN,21543)@225
    assign rightShiftStage1Idx1_uid21544_dupName_425_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21542_dupName_425_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21537_dupName_425_i_unnamed_c_compstr0_shift_x(BITSELECT,21536)@225
    assign rightShiftStage0Idx1Rng1_uid21537_dupName_425_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_q[33:1];

    // rightShiftStage0Idx1_uid21539_dupName_425_i_unnamed_c_compstr0_shift_x(BITJOIN,21538)@225
    assign rightShiftStage0Idx1_uid21539_dupName_425_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21537_dupName_425_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25275_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x(BITSELECT,25274)@224
    assign leftShiftStage2Idx1Rng8_uid25275_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_in = leftShiftStage1_uid25273_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25275_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25275_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25276_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x(BITJOIN,25275)@224
    assign leftShiftStage2Idx1_uid25276_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25275_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25270_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x(BITSELECT,25269)@224
    assign leftShiftStage1Idx1Rng4_uid25270_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_in = leftShiftStage0_uid25268_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25270_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25270_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25271_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x(BITJOIN,25270)@224
    assign leftShiftStage1Idx1_uid25271_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25270_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25265_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x(BITSELECT,25264)@224
    assign leftShiftStage0Idx1Rng1_uid25265_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_106_c_compstr3002_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25265_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25265_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25266_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x(BITJOIN,25265)@224
    assign leftShiftStage0Idx1_uid25266_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25265_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21485_dupName_421_i_unnamed_c_compstr0_shift_x(BITSELECT,21484)@223
    assign rightShiftStage2Idx1Rng8_uid21485_dupName_421_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21484_dupName_421_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21487_dupName_421_i_unnamed_c_compstr0_shift_x(BITJOIN,21486)@223
    assign rightShiftStage2Idx1_uid21487_dupName_421_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21485_dupName_421_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21480_dupName_421_i_unnamed_c_compstr0_shift_x(BITSELECT,21479)@223
    assign rightShiftStage1Idx1Rng4_uid21480_dupName_421_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21479_dupName_421_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21482_dupName_421_i_unnamed_c_compstr0_shift_x(BITJOIN,21481)@223
    assign rightShiftStage1Idx1_uid21482_dupName_421_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21480_dupName_421_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21475_dupName_421_i_unnamed_c_compstr0_shift_x(BITSELECT,21474)@223
    assign rightShiftStage0Idx1Rng1_uid21475_dupName_421_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_q[33:1];

    // rightShiftStage0Idx1_uid21477_dupName_421_i_unnamed_c_compstr0_shift_x(BITJOIN,21476)@223
    assign rightShiftStage0Idx1_uid21477_dupName_421_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21475_dupName_421_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25257_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x(BITSELECT,25256)@222
    assign leftShiftStage2Idx1Rng8_uid25257_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_in = leftShiftStage1_uid25255_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25257_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25257_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25258_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x(BITJOIN,25257)@222
    assign leftShiftStage2Idx1_uid25258_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25257_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25252_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x(BITSELECT,25251)@222
    assign leftShiftStage1Idx1Rng4_uid25252_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_in = leftShiftStage0_uid25250_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25252_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25252_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25253_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x(BITJOIN,25252)@222
    assign leftShiftStage1Idx1_uid25253_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25252_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25247_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x(BITSELECT,25246)@222
    assign leftShiftStage0Idx1Rng1_uid25247_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_105_c_compstr2974_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25247_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25247_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25248_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x(BITJOIN,25247)@222
    assign leftShiftStage0Idx1_uid25248_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25247_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21423_dupName_417_i_unnamed_c_compstr0_shift_x(BITSELECT,21422)@221
    assign rightShiftStage2Idx1Rng8_uid21423_dupName_417_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21422_dupName_417_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21425_dupName_417_i_unnamed_c_compstr0_shift_x(BITJOIN,21424)@221
    assign rightShiftStage2Idx1_uid21425_dupName_417_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21423_dupName_417_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21418_dupName_417_i_unnamed_c_compstr0_shift_x(BITSELECT,21417)@221
    assign rightShiftStage1Idx1Rng4_uid21418_dupName_417_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21417_dupName_417_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21420_dupName_417_i_unnamed_c_compstr0_shift_x(BITJOIN,21419)@221
    assign rightShiftStage1Idx1_uid21420_dupName_417_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21418_dupName_417_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21413_dupName_417_i_unnamed_c_compstr0_shift_x(BITSELECT,21412)@221
    assign rightShiftStage0Idx1Rng1_uid21413_dupName_417_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_q[33:1];

    // rightShiftStage0Idx1_uid21415_dupName_417_i_unnamed_c_compstr0_shift_x(BITJOIN,21414)@221
    assign rightShiftStage0Idx1_uid21415_dupName_417_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21413_dupName_417_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25239_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x(BITSELECT,25238)@220
    assign leftShiftStage2Idx1Rng8_uid25239_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_in = leftShiftStage1_uid25237_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25239_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25239_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25240_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x(BITJOIN,25239)@220
    assign leftShiftStage2Idx1_uid25240_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25239_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25234_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x(BITSELECT,25233)@220
    assign leftShiftStage1Idx1Rng4_uid25234_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_in = leftShiftStage0_uid25232_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25234_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25234_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25235_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x(BITJOIN,25234)@220
    assign leftShiftStage1Idx1_uid25235_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25234_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25229_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x(BITSELECT,25228)@220
    assign leftShiftStage0Idx1Rng1_uid25229_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_104_c_compstr2946_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25229_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25229_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25230_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x(BITJOIN,25229)@220
    assign leftShiftStage0Idx1_uid25230_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25229_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21361_dupName_413_i_unnamed_c_compstr0_shift_x(BITSELECT,21360)@219
    assign rightShiftStage2Idx1Rng8_uid21361_dupName_413_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21360_dupName_413_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21363_dupName_413_i_unnamed_c_compstr0_shift_x(BITJOIN,21362)@219
    assign rightShiftStage2Idx1_uid21363_dupName_413_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21361_dupName_413_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21356_dupName_413_i_unnamed_c_compstr0_shift_x(BITSELECT,21355)@219
    assign rightShiftStage1Idx1Rng4_uid21356_dupName_413_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21355_dupName_413_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21358_dupName_413_i_unnamed_c_compstr0_shift_x(BITJOIN,21357)@219
    assign rightShiftStage1Idx1_uid21358_dupName_413_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21356_dupName_413_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21351_dupName_413_i_unnamed_c_compstr0_shift_x(BITSELECT,21350)@219
    assign rightShiftStage0Idx1Rng1_uid21351_dupName_413_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_q[33:1];

    // rightShiftStage0Idx1_uid21353_dupName_413_i_unnamed_c_compstr0_shift_x(BITJOIN,21352)@219
    assign rightShiftStage0Idx1_uid21353_dupName_413_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21351_dupName_413_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25221_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x(BITSELECT,25220)@218
    assign leftShiftStage2Idx1Rng8_uid25221_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_in = leftShiftStage1_uid25219_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25221_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25221_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25222_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x(BITJOIN,25221)@218
    assign leftShiftStage2Idx1_uid25222_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25221_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25216_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x(BITSELECT,25215)@218
    assign leftShiftStage1Idx1Rng4_uid25216_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_in = leftShiftStage0_uid25214_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25216_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25216_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25217_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x(BITJOIN,25216)@218
    assign leftShiftStage1Idx1_uid25217_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25216_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25211_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x(BITSELECT,25210)@218
    assign leftShiftStage0Idx1Rng1_uid25211_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_103_c_compstr2918_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25211_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25211_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25212_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x(BITJOIN,25211)@218
    assign leftShiftStage0Idx1_uid25212_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25211_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21299_dupName_409_i_unnamed_c_compstr0_shift_x(BITSELECT,21298)@217
    assign rightShiftStage2Idx1Rng8_uid21299_dupName_409_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21298_dupName_409_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21301_dupName_409_i_unnamed_c_compstr0_shift_x(BITJOIN,21300)@217
    assign rightShiftStage2Idx1_uid21301_dupName_409_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21299_dupName_409_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21294_dupName_409_i_unnamed_c_compstr0_shift_x(BITSELECT,21293)@217
    assign rightShiftStage1Idx1Rng4_uid21294_dupName_409_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21293_dupName_409_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21296_dupName_409_i_unnamed_c_compstr0_shift_x(BITJOIN,21295)@217
    assign rightShiftStage1Idx1_uid21296_dupName_409_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21294_dupName_409_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21289_dupName_409_i_unnamed_c_compstr0_shift_x(BITSELECT,21288)@217
    assign rightShiftStage0Idx1Rng1_uid21289_dupName_409_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_q[33:1];

    // rightShiftStage0Idx1_uid21291_dupName_409_i_unnamed_c_compstr0_shift_x(BITJOIN,21290)@217
    assign rightShiftStage0Idx1_uid21291_dupName_409_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21289_dupName_409_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25203_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x(BITSELECT,25202)@216
    assign leftShiftStage2Idx1Rng8_uid25203_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_in = leftShiftStage1_uid25201_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25203_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25203_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25204_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x(BITJOIN,25203)@216
    assign leftShiftStage2Idx1_uid25204_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25203_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25198_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x(BITSELECT,25197)@216
    assign leftShiftStage1Idx1Rng4_uid25198_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_in = leftShiftStage0_uid25196_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25198_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25198_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25199_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x(BITJOIN,25198)@216
    assign leftShiftStage1Idx1_uid25199_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25198_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25193_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x(BITSELECT,25192)@216
    assign leftShiftStage0Idx1Rng1_uid25193_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_102_c_compstr2890_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25193_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25193_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25194_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x(BITJOIN,25193)@216
    assign leftShiftStage0Idx1_uid25194_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25193_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21237_dupName_405_i_unnamed_c_compstr0_shift_x(BITSELECT,21236)@215
    assign rightShiftStage2Idx1Rng8_uid21237_dupName_405_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21236_dupName_405_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21239_dupName_405_i_unnamed_c_compstr0_shift_x(BITJOIN,21238)@215
    assign rightShiftStage2Idx1_uid21239_dupName_405_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21237_dupName_405_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21232_dupName_405_i_unnamed_c_compstr0_shift_x(BITSELECT,21231)@215
    assign rightShiftStage1Idx1Rng4_uid21232_dupName_405_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21231_dupName_405_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21234_dupName_405_i_unnamed_c_compstr0_shift_x(BITJOIN,21233)@215
    assign rightShiftStage1Idx1_uid21234_dupName_405_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21232_dupName_405_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21227_dupName_405_i_unnamed_c_compstr0_shift_x(BITSELECT,21226)@215
    assign rightShiftStage0Idx1Rng1_uid21227_dupName_405_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_q[33:1];

    // rightShiftStage0Idx1_uid21229_dupName_405_i_unnamed_c_compstr0_shift_x(BITJOIN,21228)@215
    assign rightShiftStage0Idx1_uid21229_dupName_405_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21227_dupName_405_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25185_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x(BITSELECT,25184)@214
    assign leftShiftStage2Idx1Rng8_uid25185_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_in = leftShiftStage1_uid25183_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25185_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25185_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25186_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x(BITJOIN,25185)@214
    assign leftShiftStage2Idx1_uid25186_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25185_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25180_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x(BITSELECT,25179)@214
    assign leftShiftStage1Idx1Rng4_uid25180_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_in = leftShiftStage0_uid25178_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25180_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25180_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25181_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x(BITJOIN,25180)@214
    assign leftShiftStage1Idx1_uid25181_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25180_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25175_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x(BITSELECT,25174)@214
    assign leftShiftStage0Idx1Rng1_uid25175_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_101_c_compstr2862_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25175_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25175_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25176_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x(BITJOIN,25175)@214
    assign leftShiftStage0Idx1_uid25176_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25175_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21175_dupName_401_i_unnamed_c_compstr0_shift_x(BITSELECT,21174)@213
    assign rightShiftStage2Idx1Rng8_uid21175_dupName_401_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21174_dupName_401_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21177_dupName_401_i_unnamed_c_compstr0_shift_x(BITJOIN,21176)@213
    assign rightShiftStage2Idx1_uid21177_dupName_401_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21175_dupName_401_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21170_dupName_401_i_unnamed_c_compstr0_shift_x(BITSELECT,21169)@213
    assign rightShiftStage1Idx1Rng4_uid21170_dupName_401_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21169_dupName_401_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21172_dupName_401_i_unnamed_c_compstr0_shift_x(BITJOIN,21171)@213
    assign rightShiftStage1Idx1_uid21172_dupName_401_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21170_dupName_401_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21165_dupName_401_i_unnamed_c_compstr0_shift_x(BITSELECT,21164)@213
    assign rightShiftStage0Idx1Rng1_uid21165_dupName_401_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_q[33:1];

    // rightShiftStage0Idx1_uid21167_dupName_401_i_unnamed_c_compstr0_shift_x(BITJOIN,21166)@213
    assign rightShiftStage0Idx1_uid21167_dupName_401_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21165_dupName_401_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25167_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x(BITSELECT,25166)@212
    assign leftShiftStage2Idx1Rng8_uid25167_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_in = leftShiftStage1_uid25165_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25167_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25167_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25168_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x(BITJOIN,25167)@212
    assign leftShiftStage2Idx1_uid25168_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25167_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25162_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x(BITSELECT,25161)@212
    assign leftShiftStage1Idx1Rng4_uid25162_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_in = leftShiftStage0_uid25160_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25162_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25162_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25163_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x(BITJOIN,25162)@212
    assign leftShiftStage1Idx1_uid25163_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25162_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25157_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x(BITSELECT,25156)@212
    assign leftShiftStage0Idx1Rng1_uid25157_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_100_c_compstr2834_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25157_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25157_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25158_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x(BITJOIN,25157)@212
    assign leftShiftStage0Idx1_uid25158_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25157_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21113_dupName_397_i_unnamed_c_compstr0_shift_x(BITSELECT,21112)@211
    assign rightShiftStage2Idx1Rng8_uid21113_dupName_397_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21112_dupName_397_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21115_dupName_397_i_unnamed_c_compstr0_shift_x(BITJOIN,21114)@211
    assign rightShiftStage2Idx1_uid21115_dupName_397_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21113_dupName_397_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21108_dupName_397_i_unnamed_c_compstr0_shift_x(BITSELECT,21107)@211
    assign rightShiftStage1Idx1Rng4_uid21108_dupName_397_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21107_dupName_397_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21110_dupName_397_i_unnamed_c_compstr0_shift_x(BITJOIN,21109)@211
    assign rightShiftStage1Idx1_uid21110_dupName_397_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21108_dupName_397_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21103_dupName_397_i_unnamed_c_compstr0_shift_x(BITSELECT,21102)@211
    assign rightShiftStage0Idx1Rng1_uid21103_dupName_397_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_q[33:1];

    // rightShiftStage0Idx1_uid21105_dupName_397_i_unnamed_c_compstr0_shift_x(BITJOIN,21104)@211
    assign rightShiftStage0Idx1_uid21105_dupName_397_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21103_dupName_397_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27417_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x(BITSELECT,27416)@210
    assign leftShiftStage2Idx1Rng8_uid27417_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_in = leftShiftStage1_uid27415_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27417_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27417_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27418_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x(BITJOIN,27417)@210
    assign leftShiftStage2Idx1_uid27418_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27417_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27412_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x(BITSELECT,27411)@210
    assign leftShiftStage1Idx1Rng4_uid27412_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_in = leftShiftStage0_uid27410_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27412_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27412_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27413_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x(BITJOIN,27412)@210
    assign leftShiftStage1Idx1_uid27413_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27412_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27407_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x(BITSELECT,27406)@210
    assign leftShiftStage0Idx1Rng1_uid27407_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_99_c_compstr2806_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27407_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27407_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27408_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x(BITJOIN,27407)@210
    assign leftShiftStage0Idx1_uid27408_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27407_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21051_dupName_393_i_unnamed_c_compstr0_shift_x(BITSELECT,21050)@209
    assign rightShiftStage2Idx1Rng8_uid21051_dupName_393_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21050_dupName_393_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21053_dupName_393_i_unnamed_c_compstr0_shift_x(BITJOIN,21052)@209
    assign rightShiftStage2Idx1_uid21053_dupName_393_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21051_dupName_393_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21046_dupName_393_i_unnamed_c_compstr0_shift_x(BITSELECT,21045)@209
    assign rightShiftStage1Idx1Rng4_uid21046_dupName_393_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21045_dupName_393_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21048_dupName_393_i_unnamed_c_compstr0_shift_x(BITJOIN,21047)@209
    assign rightShiftStage1Idx1_uid21048_dupName_393_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21046_dupName_393_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21041_dupName_393_i_unnamed_c_compstr0_shift_x(BITSELECT,21040)@209
    assign rightShiftStage0Idx1Rng1_uid21041_dupName_393_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_q[33:1];

    // rightShiftStage0Idx1_uid21043_dupName_393_i_unnamed_c_compstr0_shift_x(BITJOIN,21042)@209
    assign rightShiftStage0Idx1_uid21043_dupName_393_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21041_dupName_393_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27399_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x(BITSELECT,27398)@208
    assign leftShiftStage2Idx1Rng8_uid27399_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_in = leftShiftStage1_uid27397_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27399_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27399_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27400_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x(BITJOIN,27399)@208
    assign leftShiftStage2Idx1_uid27400_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27399_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27394_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x(BITSELECT,27393)@208
    assign leftShiftStage1Idx1Rng4_uid27394_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_in = leftShiftStage0_uid27392_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27394_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27394_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27395_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x(BITJOIN,27394)@208
    assign leftShiftStage1Idx1_uid27395_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27394_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27389_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x(BITSELECT,27388)@208
    assign leftShiftStage0Idx1Rng1_uid27389_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_98_c_compstr2778_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27389_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27389_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27390_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x(BITJOIN,27389)@208
    assign leftShiftStage0Idx1_uid27390_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27389_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20989_dupName_389_i_unnamed_c_compstr0_shift_x(BITSELECT,20988)@207
    assign rightShiftStage2Idx1Rng8_uid20989_dupName_389_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20988_dupName_389_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20991_dupName_389_i_unnamed_c_compstr0_shift_x(BITJOIN,20990)@207
    assign rightShiftStage2Idx1_uid20991_dupName_389_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20989_dupName_389_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20984_dupName_389_i_unnamed_c_compstr0_shift_x(BITSELECT,20983)@207
    assign rightShiftStage1Idx1Rng4_uid20984_dupName_389_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20983_dupName_389_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20986_dupName_389_i_unnamed_c_compstr0_shift_x(BITJOIN,20985)@207
    assign rightShiftStage1Idx1_uid20986_dupName_389_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20984_dupName_389_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20979_dupName_389_i_unnamed_c_compstr0_shift_x(BITSELECT,20978)@207
    assign rightShiftStage0Idx1Rng1_uid20979_dupName_389_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_q[33:1];

    // rightShiftStage0Idx1_uid20981_dupName_389_i_unnamed_c_compstr0_shift_x(BITJOIN,20980)@207
    assign rightShiftStage0Idx1_uid20981_dupName_389_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20979_dupName_389_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27381_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x(BITSELECT,27380)@206
    assign leftShiftStage2Idx1Rng8_uid27381_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_in = leftShiftStage1_uid27379_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27381_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27381_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27382_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x(BITJOIN,27381)@206
    assign leftShiftStage2Idx1_uid27382_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27381_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27376_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x(BITSELECT,27375)@206
    assign leftShiftStage1Idx1Rng4_uid27376_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_in = leftShiftStage0_uid27374_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27376_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27376_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27377_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x(BITJOIN,27376)@206
    assign leftShiftStage1Idx1_uid27377_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27376_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27371_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x(BITSELECT,27370)@206
    assign leftShiftStage0Idx1Rng1_uid27371_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_97_c_compstr2750_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27371_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27371_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27372_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x(BITJOIN,27371)@206
    assign leftShiftStage0Idx1_uid27372_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27371_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20927_dupName_385_i_unnamed_c_compstr0_shift_x(BITSELECT,20926)@205
    assign rightShiftStage2Idx1Rng8_uid20927_dupName_385_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20926_dupName_385_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20929_dupName_385_i_unnamed_c_compstr0_shift_x(BITJOIN,20928)@205
    assign rightShiftStage2Idx1_uid20929_dupName_385_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20927_dupName_385_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20922_dupName_385_i_unnamed_c_compstr0_shift_x(BITSELECT,20921)@205
    assign rightShiftStage1Idx1Rng4_uid20922_dupName_385_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20921_dupName_385_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20924_dupName_385_i_unnamed_c_compstr0_shift_x(BITJOIN,20923)@205
    assign rightShiftStage1Idx1_uid20924_dupName_385_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20922_dupName_385_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20917_dupName_385_i_unnamed_c_compstr0_shift_x(BITSELECT,20916)@205
    assign rightShiftStage0Idx1Rng1_uid20917_dupName_385_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_q[33:1];

    // rightShiftStage0Idx1_uid20919_dupName_385_i_unnamed_c_compstr0_shift_x(BITJOIN,20918)@205
    assign rightShiftStage0Idx1_uid20919_dupName_385_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20917_dupName_385_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27363_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x(BITSELECT,27362)@204
    assign leftShiftStage2Idx1Rng8_uid27363_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_in = leftShiftStage1_uid27361_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27363_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27363_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27364_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x(BITJOIN,27363)@204
    assign leftShiftStage2Idx1_uid27364_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27363_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27358_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x(BITSELECT,27357)@204
    assign leftShiftStage1Idx1Rng4_uid27358_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_in = leftShiftStage0_uid27356_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27358_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27358_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27359_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x(BITJOIN,27358)@204
    assign leftShiftStage1Idx1_uid27359_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27358_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27353_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x(BITSELECT,27352)@204
    assign leftShiftStage0Idx1Rng1_uid27353_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_96_c_compstr2722_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27353_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27353_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27354_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x(BITJOIN,27353)@204
    assign leftShiftStage0Idx1_uid27354_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27353_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20865_dupName_381_i_unnamed_c_compstr0_shift_x(BITSELECT,20864)@203
    assign rightShiftStage2Idx1Rng8_uid20865_dupName_381_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20864_dupName_381_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20867_dupName_381_i_unnamed_c_compstr0_shift_x(BITJOIN,20866)@203
    assign rightShiftStage2Idx1_uid20867_dupName_381_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20865_dupName_381_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20860_dupName_381_i_unnamed_c_compstr0_shift_x(BITSELECT,20859)@203
    assign rightShiftStage1Idx1Rng4_uid20860_dupName_381_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20859_dupName_381_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20862_dupName_381_i_unnamed_c_compstr0_shift_x(BITJOIN,20861)@203
    assign rightShiftStage1Idx1_uid20862_dupName_381_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20860_dupName_381_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20855_dupName_381_i_unnamed_c_compstr0_shift_x(BITSELECT,20854)@203
    assign rightShiftStage0Idx1Rng1_uid20855_dupName_381_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_q[33:1];

    // rightShiftStage0Idx1_uid20857_dupName_381_i_unnamed_c_compstr0_shift_x(BITJOIN,20856)@203
    assign rightShiftStage0Idx1_uid20857_dupName_381_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20855_dupName_381_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27345_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x(BITSELECT,27344)@202
    assign leftShiftStage2Idx1Rng8_uid27345_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_in = leftShiftStage1_uid27343_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27345_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27345_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27346_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x(BITJOIN,27345)@202
    assign leftShiftStage2Idx1_uid27346_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27345_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27340_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x(BITSELECT,27339)@202
    assign leftShiftStage1Idx1Rng4_uid27340_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_in = leftShiftStage0_uid27338_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27340_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27340_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27341_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x(BITJOIN,27340)@202
    assign leftShiftStage1Idx1_uid27341_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27340_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27335_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x(BITSELECT,27334)@202
    assign leftShiftStage0Idx1Rng1_uid27335_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_95_c_compstr2694_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27335_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27335_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27336_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x(BITJOIN,27335)@202
    assign leftShiftStage0Idx1_uid27336_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27335_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20803_dupName_377_i_unnamed_c_compstr0_shift_x(BITSELECT,20802)@201
    assign rightShiftStage2Idx1Rng8_uid20803_dupName_377_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20802_dupName_377_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20805_dupName_377_i_unnamed_c_compstr0_shift_x(BITJOIN,20804)@201
    assign rightShiftStage2Idx1_uid20805_dupName_377_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20803_dupName_377_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20798_dupName_377_i_unnamed_c_compstr0_shift_x(BITSELECT,20797)@201
    assign rightShiftStage1Idx1Rng4_uid20798_dupName_377_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20797_dupName_377_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20800_dupName_377_i_unnamed_c_compstr0_shift_x(BITJOIN,20799)@201
    assign rightShiftStage1Idx1_uid20800_dupName_377_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20798_dupName_377_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20793_dupName_377_i_unnamed_c_compstr0_shift_x(BITSELECT,20792)@201
    assign rightShiftStage0Idx1Rng1_uid20793_dupName_377_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_q[33:1];

    // rightShiftStage0Idx1_uid20795_dupName_377_i_unnamed_c_compstr0_shift_x(BITJOIN,20794)@201
    assign rightShiftStage0Idx1_uid20795_dupName_377_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20793_dupName_377_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27327_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x(BITSELECT,27326)@200
    assign leftShiftStage2Idx1Rng8_uid27327_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_in = leftShiftStage1_uid27325_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27327_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27327_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27328_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x(BITJOIN,27327)@200
    assign leftShiftStage2Idx1_uid27328_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27327_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27322_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x(BITSELECT,27321)@200
    assign leftShiftStage1Idx1Rng4_uid27322_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_in = leftShiftStage0_uid27320_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27322_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27322_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27323_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x(BITJOIN,27322)@200
    assign leftShiftStage1Idx1_uid27323_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27322_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27317_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x(BITSELECT,27316)@200
    assign leftShiftStage0Idx1Rng1_uid27317_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_94_c_compstr2666_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27317_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27317_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27318_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x(BITJOIN,27317)@200
    assign leftShiftStage0Idx1_uid27318_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27317_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20741_dupName_373_i_unnamed_c_compstr0_shift_x(BITSELECT,20740)@199
    assign rightShiftStage2Idx1Rng8_uid20741_dupName_373_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20740_dupName_373_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20743_dupName_373_i_unnamed_c_compstr0_shift_x(BITJOIN,20742)@199
    assign rightShiftStage2Idx1_uid20743_dupName_373_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20741_dupName_373_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20736_dupName_373_i_unnamed_c_compstr0_shift_x(BITSELECT,20735)@199
    assign rightShiftStage1Idx1Rng4_uid20736_dupName_373_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20735_dupName_373_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20738_dupName_373_i_unnamed_c_compstr0_shift_x(BITJOIN,20737)@199
    assign rightShiftStage1Idx1_uid20738_dupName_373_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20736_dupName_373_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20731_dupName_373_i_unnamed_c_compstr0_shift_x(BITSELECT,20730)@199
    assign rightShiftStage0Idx1Rng1_uid20731_dupName_373_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_q[33:1];

    // rightShiftStage0Idx1_uid20733_dupName_373_i_unnamed_c_compstr0_shift_x(BITJOIN,20732)@199
    assign rightShiftStage0Idx1_uid20733_dupName_373_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20731_dupName_373_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27309_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x(BITSELECT,27308)@198
    assign leftShiftStage2Idx1Rng8_uid27309_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_in = leftShiftStage1_uid27307_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27309_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27309_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27310_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x(BITJOIN,27309)@198
    assign leftShiftStage2Idx1_uid27310_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27309_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27304_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x(BITSELECT,27303)@198
    assign leftShiftStage1Idx1Rng4_uid27304_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_in = leftShiftStage0_uid27302_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27304_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27304_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27305_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x(BITJOIN,27304)@198
    assign leftShiftStage1Idx1_uid27305_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27304_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27299_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x(BITSELECT,27298)@198
    assign leftShiftStage0Idx1Rng1_uid27299_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_93_c_compstr2638_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27299_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27299_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27300_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x(BITJOIN,27299)@198
    assign leftShiftStage0Idx1_uid27300_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27299_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20679_dupName_369_i_unnamed_c_compstr0_shift_x(BITSELECT,20678)@197
    assign rightShiftStage2Idx1Rng8_uid20679_dupName_369_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20678_dupName_369_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20681_dupName_369_i_unnamed_c_compstr0_shift_x(BITJOIN,20680)@197
    assign rightShiftStage2Idx1_uid20681_dupName_369_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20679_dupName_369_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20674_dupName_369_i_unnamed_c_compstr0_shift_x(BITSELECT,20673)@197
    assign rightShiftStage1Idx1Rng4_uid20674_dupName_369_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20673_dupName_369_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20676_dupName_369_i_unnamed_c_compstr0_shift_x(BITJOIN,20675)@197
    assign rightShiftStage1Idx1_uid20676_dupName_369_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20674_dupName_369_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20669_dupName_369_i_unnamed_c_compstr0_shift_x(BITSELECT,20668)@197
    assign rightShiftStage0Idx1Rng1_uid20669_dupName_369_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_q[33:1];

    // rightShiftStage0Idx1_uid20671_dupName_369_i_unnamed_c_compstr0_shift_x(BITJOIN,20670)@197
    assign rightShiftStage0Idx1_uid20671_dupName_369_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20669_dupName_369_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27291_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x(BITSELECT,27290)@196
    assign leftShiftStage2Idx1Rng8_uid27291_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_in = leftShiftStage1_uid27289_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27291_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27291_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27292_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x(BITJOIN,27291)@196
    assign leftShiftStage2Idx1_uid27292_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27291_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27286_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x(BITSELECT,27285)@196
    assign leftShiftStage1Idx1Rng4_uid27286_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_in = leftShiftStage0_uid27284_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27286_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27286_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27287_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x(BITJOIN,27286)@196
    assign leftShiftStage1Idx1_uid27287_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27286_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27281_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x(BITSELECT,27280)@196
    assign leftShiftStage0Idx1Rng1_uid27281_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_92_c_compstr2610_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27281_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27281_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27282_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x(BITJOIN,27281)@196
    assign leftShiftStage0Idx1_uid27282_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27281_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20617_dupName_365_i_unnamed_c_compstr0_shift_x(BITSELECT,20616)@195
    assign rightShiftStage2Idx1Rng8_uid20617_dupName_365_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20616_dupName_365_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20619_dupName_365_i_unnamed_c_compstr0_shift_x(BITJOIN,20618)@195
    assign rightShiftStage2Idx1_uid20619_dupName_365_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20617_dupName_365_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20612_dupName_365_i_unnamed_c_compstr0_shift_x(BITSELECT,20611)@195
    assign rightShiftStage1Idx1Rng4_uid20612_dupName_365_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20611_dupName_365_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20614_dupName_365_i_unnamed_c_compstr0_shift_x(BITJOIN,20613)@195
    assign rightShiftStage1Idx1_uid20614_dupName_365_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20612_dupName_365_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20607_dupName_365_i_unnamed_c_compstr0_shift_x(BITSELECT,20606)@195
    assign rightShiftStage0Idx1Rng1_uid20607_dupName_365_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_q[33:1];

    // rightShiftStage0Idx1_uid20609_dupName_365_i_unnamed_c_compstr0_shift_x(BITJOIN,20608)@195
    assign rightShiftStage0Idx1_uid20609_dupName_365_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20607_dupName_365_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27273_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x(BITSELECT,27272)@194
    assign leftShiftStage2Idx1Rng8_uid27273_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_in = leftShiftStage1_uid27271_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27273_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27273_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27274_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x(BITJOIN,27273)@194
    assign leftShiftStage2Idx1_uid27274_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27273_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27268_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x(BITSELECT,27267)@194
    assign leftShiftStage1Idx1Rng4_uid27268_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_in = leftShiftStage0_uid27266_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27268_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27268_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27269_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x(BITJOIN,27268)@194
    assign leftShiftStage1Idx1_uid27269_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27268_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27263_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x(BITSELECT,27262)@194
    assign leftShiftStage0Idx1Rng1_uid27263_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_91_c_compstr2582_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27263_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27263_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27264_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x(BITJOIN,27263)@194
    assign leftShiftStage0Idx1_uid27264_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27263_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20555_dupName_361_i_unnamed_c_compstr0_shift_x(BITSELECT,20554)@193
    assign rightShiftStage2Idx1Rng8_uid20555_dupName_361_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20554_dupName_361_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20557_dupName_361_i_unnamed_c_compstr0_shift_x(BITJOIN,20556)@193
    assign rightShiftStage2Idx1_uid20557_dupName_361_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20555_dupName_361_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20550_dupName_361_i_unnamed_c_compstr0_shift_x(BITSELECT,20549)@193
    assign rightShiftStage1Idx1Rng4_uid20550_dupName_361_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20549_dupName_361_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20552_dupName_361_i_unnamed_c_compstr0_shift_x(BITJOIN,20551)@193
    assign rightShiftStage1Idx1_uid20552_dupName_361_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20550_dupName_361_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20545_dupName_361_i_unnamed_c_compstr0_shift_x(BITSELECT,20544)@193
    assign rightShiftStage0Idx1Rng1_uid20545_dupName_361_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_q[33:1];

    // rightShiftStage0Idx1_uid20547_dupName_361_i_unnamed_c_compstr0_shift_x(BITJOIN,20546)@193
    assign rightShiftStage0Idx1_uid20547_dupName_361_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20545_dupName_361_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27255_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x(BITSELECT,27254)@192
    assign leftShiftStage2Idx1Rng8_uid27255_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_in = leftShiftStage1_uid27253_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27255_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27255_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27256_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x(BITJOIN,27255)@192
    assign leftShiftStage2Idx1_uid27256_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27255_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27250_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x(BITSELECT,27249)@192
    assign leftShiftStage1Idx1Rng4_uid27250_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_in = leftShiftStage0_uid27248_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27250_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27250_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27251_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x(BITJOIN,27250)@192
    assign leftShiftStage1Idx1_uid27251_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27250_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27245_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x(BITSELECT,27244)@192
    assign leftShiftStage0Idx1Rng1_uid27245_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_90_c_compstr2554_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27245_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27245_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27246_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x(BITJOIN,27245)@192
    assign leftShiftStage0Idx1_uid27246_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27245_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20493_dupName_357_i_unnamed_c_compstr0_shift_x(BITSELECT,20492)@191
    assign rightShiftStage2Idx1Rng8_uid20493_dupName_357_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20492_dupName_357_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20495_dupName_357_i_unnamed_c_compstr0_shift_x(BITJOIN,20494)@191
    assign rightShiftStage2Idx1_uid20495_dupName_357_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20493_dupName_357_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20488_dupName_357_i_unnamed_c_compstr0_shift_x(BITSELECT,20487)@191
    assign rightShiftStage1Idx1Rng4_uid20488_dupName_357_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20487_dupName_357_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20490_dupName_357_i_unnamed_c_compstr0_shift_x(BITJOIN,20489)@191
    assign rightShiftStage1Idx1_uid20490_dupName_357_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20488_dupName_357_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20483_dupName_357_i_unnamed_c_compstr0_shift_x(BITSELECT,20482)@191
    assign rightShiftStage0Idx1Rng1_uid20483_dupName_357_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_q[33:1];

    // rightShiftStage0Idx1_uid20485_dupName_357_i_unnamed_c_compstr0_shift_x(BITJOIN,20484)@191
    assign rightShiftStage0Idx1_uid20485_dupName_357_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20483_dupName_357_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27219_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x(BITSELECT,27218)@190
    assign leftShiftStage2Idx1Rng8_uid27219_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_in = leftShiftStage1_uid27217_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27219_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27219_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27220_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x(BITJOIN,27219)@190
    assign leftShiftStage2Idx1_uid27220_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27219_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27214_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x(BITSELECT,27213)@190
    assign leftShiftStage1Idx1Rng4_uid27214_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_in = leftShiftStage0_uid27212_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27214_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27214_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27215_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x(BITJOIN,27214)@190
    assign leftShiftStage1Idx1_uid27215_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27214_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27209_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x(BITSELECT,27208)@190
    assign leftShiftStage0Idx1Rng1_uid27209_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_89_c_compstr2526_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27209_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27209_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27210_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x(BITJOIN,27209)@190
    assign leftShiftStage0Idx1_uid27210_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27209_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20431_dupName_353_i_unnamed_c_compstr0_shift_x(BITSELECT,20430)@189
    assign rightShiftStage2Idx1Rng8_uid20431_dupName_353_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20430_dupName_353_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20433_dupName_353_i_unnamed_c_compstr0_shift_x(BITJOIN,20432)@189
    assign rightShiftStage2Idx1_uid20433_dupName_353_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20431_dupName_353_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20426_dupName_353_i_unnamed_c_compstr0_shift_x(BITSELECT,20425)@189
    assign rightShiftStage1Idx1Rng4_uid20426_dupName_353_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20425_dupName_353_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20428_dupName_353_i_unnamed_c_compstr0_shift_x(BITJOIN,20427)@189
    assign rightShiftStage1Idx1_uid20428_dupName_353_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20426_dupName_353_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20421_dupName_353_i_unnamed_c_compstr0_shift_x(BITSELECT,20420)@189
    assign rightShiftStage0Idx1Rng1_uid20421_dupName_353_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_q[33:1];

    // rightShiftStage0Idx1_uid20423_dupName_353_i_unnamed_c_compstr0_shift_x(BITJOIN,20422)@189
    assign rightShiftStage0Idx1_uid20423_dupName_353_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20421_dupName_353_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27201_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x(BITSELECT,27200)@188
    assign leftShiftStage2Idx1Rng8_uid27201_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_in = leftShiftStage1_uid27199_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27201_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27201_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27202_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x(BITJOIN,27201)@188
    assign leftShiftStage2Idx1_uid27202_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27201_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27196_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x(BITSELECT,27195)@188
    assign leftShiftStage1Idx1Rng4_uid27196_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_in = leftShiftStage0_uid27194_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27196_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27196_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27197_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x(BITJOIN,27196)@188
    assign leftShiftStage1Idx1_uid27197_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27196_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27191_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x(BITSELECT,27190)@188
    assign leftShiftStage0Idx1Rng1_uid27191_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_88_c_compstr2498_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27191_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27191_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27192_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x(BITJOIN,27191)@188
    assign leftShiftStage0Idx1_uid27192_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27191_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20369_dupName_349_i_unnamed_c_compstr0_shift_x(BITSELECT,20368)@187
    assign rightShiftStage2Idx1Rng8_uid20369_dupName_349_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20368_dupName_349_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20371_dupName_349_i_unnamed_c_compstr0_shift_x(BITJOIN,20370)@187
    assign rightShiftStage2Idx1_uid20371_dupName_349_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20369_dupName_349_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20364_dupName_349_i_unnamed_c_compstr0_shift_x(BITSELECT,20363)@187
    assign rightShiftStage1Idx1Rng4_uid20364_dupName_349_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20363_dupName_349_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20366_dupName_349_i_unnamed_c_compstr0_shift_x(BITJOIN,20365)@187
    assign rightShiftStage1Idx1_uid20366_dupName_349_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20364_dupName_349_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20359_dupName_349_i_unnamed_c_compstr0_shift_x(BITSELECT,20358)@187
    assign rightShiftStage0Idx1Rng1_uid20359_dupName_349_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_q[33:1];

    // rightShiftStage0Idx1_uid20361_dupName_349_i_unnamed_c_compstr0_shift_x(BITJOIN,20360)@187
    assign rightShiftStage0Idx1_uid20361_dupName_349_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20359_dupName_349_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27183_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x(BITSELECT,27182)@186
    assign leftShiftStage2Idx1Rng8_uid27183_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_in = leftShiftStage1_uid27181_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27183_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27183_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27184_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x(BITJOIN,27183)@186
    assign leftShiftStage2Idx1_uid27184_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27183_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27178_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x(BITSELECT,27177)@186
    assign leftShiftStage1Idx1Rng4_uid27178_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_in = leftShiftStage0_uid27176_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27178_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27178_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27179_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x(BITJOIN,27178)@186
    assign leftShiftStage1Idx1_uid27179_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27178_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27173_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x(BITSELECT,27172)@186
    assign leftShiftStage0Idx1Rng1_uid27173_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_87_c_compstr2470_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27173_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27173_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27174_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x(BITJOIN,27173)@186
    assign leftShiftStage0Idx1_uid27174_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27173_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20307_dupName_345_i_unnamed_c_compstr0_shift_x(BITSELECT,20306)@185
    assign rightShiftStage2Idx1Rng8_uid20307_dupName_345_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20306_dupName_345_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20309_dupName_345_i_unnamed_c_compstr0_shift_x(BITJOIN,20308)@185
    assign rightShiftStage2Idx1_uid20309_dupName_345_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20307_dupName_345_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20302_dupName_345_i_unnamed_c_compstr0_shift_x(BITSELECT,20301)@185
    assign rightShiftStage1Idx1Rng4_uid20302_dupName_345_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20301_dupName_345_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20304_dupName_345_i_unnamed_c_compstr0_shift_x(BITJOIN,20303)@185
    assign rightShiftStage1Idx1_uid20304_dupName_345_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20302_dupName_345_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20297_dupName_345_i_unnamed_c_compstr0_shift_x(BITSELECT,20296)@185
    assign rightShiftStage0Idx1Rng1_uid20297_dupName_345_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_q[33:1];

    // rightShiftStage0Idx1_uid20299_dupName_345_i_unnamed_c_compstr0_shift_x(BITJOIN,20298)@185
    assign rightShiftStage0Idx1_uid20299_dupName_345_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20297_dupName_345_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27165_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x(BITSELECT,27164)@184
    assign leftShiftStage2Idx1Rng8_uid27165_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_in = leftShiftStage1_uid27163_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27165_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27165_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27166_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x(BITJOIN,27165)@184
    assign leftShiftStage2Idx1_uid27166_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27165_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27160_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x(BITSELECT,27159)@184
    assign leftShiftStage1Idx1Rng4_uid27160_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_in = leftShiftStage0_uid27158_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27160_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27160_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27161_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x(BITJOIN,27160)@184
    assign leftShiftStage1Idx1_uid27161_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27160_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27155_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x(BITSELECT,27154)@184
    assign leftShiftStage0Idx1Rng1_uid27155_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_86_c_compstr2442_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27155_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27155_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27156_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x(BITJOIN,27155)@184
    assign leftShiftStage0Idx1_uid27156_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27155_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20245_dupName_341_i_unnamed_c_compstr0_shift_x(BITSELECT,20244)@183
    assign rightShiftStage2Idx1Rng8_uid20245_dupName_341_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20244_dupName_341_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20247_dupName_341_i_unnamed_c_compstr0_shift_x(BITJOIN,20246)@183
    assign rightShiftStage2Idx1_uid20247_dupName_341_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20245_dupName_341_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20240_dupName_341_i_unnamed_c_compstr0_shift_x(BITSELECT,20239)@183
    assign rightShiftStage1Idx1Rng4_uid20240_dupName_341_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20239_dupName_341_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20242_dupName_341_i_unnamed_c_compstr0_shift_x(BITJOIN,20241)@183
    assign rightShiftStage1Idx1_uid20242_dupName_341_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20240_dupName_341_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20235_dupName_341_i_unnamed_c_compstr0_shift_x(BITSELECT,20234)@183
    assign rightShiftStage0Idx1Rng1_uid20235_dupName_341_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_q[33:1];

    // rightShiftStage0Idx1_uid20237_dupName_341_i_unnamed_c_compstr0_shift_x(BITJOIN,20236)@183
    assign rightShiftStage0Idx1_uid20237_dupName_341_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20235_dupName_341_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27147_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x(BITSELECT,27146)@182
    assign leftShiftStage2Idx1Rng8_uid27147_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_in = leftShiftStage1_uid27145_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27147_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27147_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27148_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x(BITJOIN,27147)@182
    assign leftShiftStage2Idx1_uid27148_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27147_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27142_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x(BITSELECT,27141)@182
    assign leftShiftStage1Idx1Rng4_uid27142_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_in = leftShiftStage0_uid27140_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27142_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27142_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27143_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x(BITJOIN,27142)@182
    assign leftShiftStage1Idx1_uid27143_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27142_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27137_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x(BITSELECT,27136)@182
    assign leftShiftStage0Idx1Rng1_uid27137_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_85_c_compstr2414_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27137_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27137_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27138_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x(BITJOIN,27137)@182
    assign leftShiftStage0Idx1_uid27138_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27137_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20183_dupName_337_i_unnamed_c_compstr0_shift_x(BITSELECT,20182)@181
    assign rightShiftStage2Idx1Rng8_uid20183_dupName_337_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20182_dupName_337_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20185_dupName_337_i_unnamed_c_compstr0_shift_x(BITJOIN,20184)@181
    assign rightShiftStage2Idx1_uid20185_dupName_337_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20183_dupName_337_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20178_dupName_337_i_unnamed_c_compstr0_shift_x(BITSELECT,20177)@181
    assign rightShiftStage1Idx1Rng4_uid20178_dupName_337_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20177_dupName_337_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20180_dupName_337_i_unnamed_c_compstr0_shift_x(BITJOIN,20179)@181
    assign rightShiftStage1Idx1_uid20180_dupName_337_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20178_dupName_337_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20173_dupName_337_i_unnamed_c_compstr0_shift_x(BITSELECT,20172)@181
    assign rightShiftStage0Idx1Rng1_uid20173_dupName_337_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_q[33:1];

    // rightShiftStage0Idx1_uid20175_dupName_337_i_unnamed_c_compstr0_shift_x(BITJOIN,20174)@181
    assign rightShiftStage0Idx1_uid20175_dupName_337_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20173_dupName_337_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27129_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x(BITSELECT,27128)@180
    assign leftShiftStage2Idx1Rng8_uid27129_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_in = leftShiftStage1_uid27127_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27129_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27129_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27130_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x(BITJOIN,27129)@180
    assign leftShiftStage2Idx1_uid27130_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27129_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27124_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x(BITSELECT,27123)@180
    assign leftShiftStage1Idx1Rng4_uid27124_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_in = leftShiftStage0_uid27122_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27124_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27124_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27125_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x(BITJOIN,27124)@180
    assign leftShiftStage1Idx1_uid27125_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27124_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27119_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x(BITSELECT,27118)@180
    assign leftShiftStage0Idx1Rng1_uid27119_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_84_c_compstr2386_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27119_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27119_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27120_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x(BITJOIN,27119)@180
    assign leftShiftStage0Idx1_uid27120_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27119_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20121_dupName_333_i_unnamed_c_compstr0_shift_x(BITSELECT,20120)@179
    assign rightShiftStage2Idx1Rng8_uid20121_dupName_333_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20120_dupName_333_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20123_dupName_333_i_unnamed_c_compstr0_shift_x(BITJOIN,20122)@179
    assign rightShiftStage2Idx1_uid20123_dupName_333_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20121_dupName_333_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20116_dupName_333_i_unnamed_c_compstr0_shift_x(BITSELECT,20115)@179
    assign rightShiftStage1Idx1Rng4_uid20116_dupName_333_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20115_dupName_333_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20118_dupName_333_i_unnamed_c_compstr0_shift_x(BITJOIN,20117)@179
    assign rightShiftStage1Idx1_uid20118_dupName_333_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20116_dupName_333_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20111_dupName_333_i_unnamed_c_compstr0_shift_x(BITSELECT,20110)@179
    assign rightShiftStage0Idx1Rng1_uid20111_dupName_333_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_q[33:1];

    // rightShiftStage0Idx1_uid20113_dupName_333_i_unnamed_c_compstr0_shift_x(BITJOIN,20112)@179
    assign rightShiftStage0Idx1_uid20113_dupName_333_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20111_dupName_333_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27111_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x(BITSELECT,27110)@178
    assign leftShiftStage2Idx1Rng8_uid27111_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_in = leftShiftStage1_uid27109_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27111_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27111_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27112_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x(BITJOIN,27111)@178
    assign leftShiftStage2Idx1_uid27112_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27111_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27106_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x(BITSELECT,27105)@178
    assign leftShiftStage1Idx1Rng4_uid27106_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_in = leftShiftStage0_uid27104_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27106_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27106_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27107_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x(BITJOIN,27106)@178
    assign leftShiftStage1Idx1_uid27107_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27106_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27101_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x(BITSELECT,27100)@178
    assign leftShiftStage0Idx1Rng1_uid27101_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_83_c_compstr2358_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27101_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27101_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27102_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x(BITJOIN,27101)@178
    assign leftShiftStage0Idx1_uid27102_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27101_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20059_dupName_329_i_unnamed_c_compstr0_shift_x(BITSELECT,20058)@177
    assign rightShiftStage2Idx1Rng8_uid20059_dupName_329_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20058_dupName_329_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20061_dupName_329_i_unnamed_c_compstr0_shift_x(BITJOIN,20060)@177
    assign rightShiftStage2Idx1_uid20061_dupName_329_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20059_dupName_329_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20054_dupName_329_i_unnamed_c_compstr0_shift_x(BITSELECT,20053)@177
    assign rightShiftStage1Idx1Rng4_uid20054_dupName_329_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20053_dupName_329_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20056_dupName_329_i_unnamed_c_compstr0_shift_x(BITJOIN,20055)@177
    assign rightShiftStage1Idx1_uid20056_dupName_329_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20054_dupName_329_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20049_dupName_329_i_unnamed_c_compstr0_shift_x(BITSELECT,20048)@177
    assign rightShiftStage0Idx1Rng1_uid20049_dupName_329_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_q[33:1];

    // rightShiftStage0Idx1_uid20051_dupName_329_i_unnamed_c_compstr0_shift_x(BITJOIN,20050)@177
    assign rightShiftStage0Idx1_uid20051_dupName_329_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20049_dupName_329_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27093_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x(BITSELECT,27092)@176
    assign leftShiftStage2Idx1Rng8_uid27093_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_in = leftShiftStage1_uid27091_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27093_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27093_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27094_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x(BITJOIN,27093)@176
    assign leftShiftStage2Idx1_uid27094_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27093_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27088_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x(BITSELECT,27087)@176
    assign leftShiftStage1Idx1Rng4_uid27088_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_in = leftShiftStage0_uid27086_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27088_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27088_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27089_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x(BITJOIN,27088)@176
    assign leftShiftStage1Idx1_uid27089_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27088_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27083_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x(BITSELECT,27082)@176
    assign leftShiftStage0Idx1Rng1_uid27083_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_82_c_compstr2330_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27083_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27083_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27084_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x(BITJOIN,27083)@176
    assign leftShiftStage0Idx1_uid27084_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27083_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19997_dupName_325_i_unnamed_c_compstr0_shift_x(BITSELECT,19996)@175
    assign rightShiftStage2Idx1Rng8_uid19997_dupName_325_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19996_dupName_325_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19999_dupName_325_i_unnamed_c_compstr0_shift_x(BITJOIN,19998)@175
    assign rightShiftStage2Idx1_uid19999_dupName_325_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19997_dupName_325_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19992_dupName_325_i_unnamed_c_compstr0_shift_x(BITSELECT,19991)@175
    assign rightShiftStage1Idx1Rng4_uid19992_dupName_325_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19991_dupName_325_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19994_dupName_325_i_unnamed_c_compstr0_shift_x(BITJOIN,19993)@175
    assign rightShiftStage1Idx1_uid19994_dupName_325_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19992_dupName_325_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19987_dupName_325_i_unnamed_c_compstr0_shift_x(BITSELECT,19986)@175
    assign rightShiftStage0Idx1Rng1_uid19987_dupName_325_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_q[33:1];

    // rightShiftStage0Idx1_uid19989_dupName_325_i_unnamed_c_compstr0_shift_x(BITJOIN,19988)@175
    assign rightShiftStage0Idx1_uid19989_dupName_325_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19987_dupName_325_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27075_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x(BITSELECT,27074)@174
    assign leftShiftStage2Idx1Rng8_uid27075_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_in = leftShiftStage1_uid27073_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27075_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27075_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27076_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x(BITJOIN,27075)@174
    assign leftShiftStage2Idx1_uid27076_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27075_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27070_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x(BITSELECT,27069)@174
    assign leftShiftStage1Idx1Rng4_uid27070_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_in = leftShiftStage0_uid27068_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27070_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27070_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27071_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x(BITJOIN,27070)@174
    assign leftShiftStage1Idx1_uid27071_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27070_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27065_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x(BITSELECT,27064)@174
    assign leftShiftStage0Idx1Rng1_uid27065_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_81_c_compstr2302_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27065_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27065_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27066_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x(BITJOIN,27065)@174
    assign leftShiftStage0Idx1_uid27066_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27065_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19935_dupName_321_i_unnamed_c_compstr0_shift_x(BITSELECT,19934)@173
    assign rightShiftStage2Idx1Rng8_uid19935_dupName_321_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19934_dupName_321_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19937_dupName_321_i_unnamed_c_compstr0_shift_x(BITJOIN,19936)@173
    assign rightShiftStage2Idx1_uid19937_dupName_321_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19935_dupName_321_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19930_dupName_321_i_unnamed_c_compstr0_shift_x(BITSELECT,19929)@173
    assign rightShiftStage1Idx1Rng4_uid19930_dupName_321_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19929_dupName_321_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19932_dupName_321_i_unnamed_c_compstr0_shift_x(BITJOIN,19931)@173
    assign rightShiftStage1Idx1_uid19932_dupName_321_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19930_dupName_321_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19925_dupName_321_i_unnamed_c_compstr0_shift_x(BITSELECT,19924)@173
    assign rightShiftStage0Idx1Rng1_uid19925_dupName_321_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_q[33:1];

    // rightShiftStage0Idx1_uid19927_dupName_321_i_unnamed_c_compstr0_shift_x(BITJOIN,19926)@173
    assign rightShiftStage0Idx1_uid19927_dupName_321_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19925_dupName_321_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27057_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x(BITSELECT,27056)@172
    assign leftShiftStage2Idx1Rng8_uid27057_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_in = leftShiftStage1_uid27055_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27057_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27057_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27058_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x(BITJOIN,27057)@172
    assign leftShiftStage2Idx1_uid27058_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27057_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27052_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x(BITSELECT,27051)@172
    assign leftShiftStage1Idx1Rng4_uid27052_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_in = leftShiftStage0_uid27050_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27052_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27052_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27053_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x(BITJOIN,27052)@172
    assign leftShiftStage1Idx1_uid27053_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27052_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27047_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x(BITSELECT,27046)@172
    assign leftShiftStage0Idx1Rng1_uid27047_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_80_c_compstr2274_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27047_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27047_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27048_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x(BITJOIN,27047)@172
    assign leftShiftStage0Idx1_uid27048_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27047_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19873_dupName_317_i_unnamed_c_compstr0_shift_x(BITSELECT,19872)@171
    assign rightShiftStage2Idx1Rng8_uid19873_dupName_317_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19872_dupName_317_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19875_dupName_317_i_unnamed_c_compstr0_shift_x(BITJOIN,19874)@171
    assign rightShiftStage2Idx1_uid19875_dupName_317_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19873_dupName_317_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19868_dupName_317_i_unnamed_c_compstr0_shift_x(BITSELECT,19867)@171
    assign rightShiftStage1Idx1Rng4_uid19868_dupName_317_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19867_dupName_317_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19870_dupName_317_i_unnamed_c_compstr0_shift_x(BITJOIN,19869)@171
    assign rightShiftStage1Idx1_uid19870_dupName_317_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19868_dupName_317_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19863_dupName_317_i_unnamed_c_compstr0_shift_x(BITSELECT,19862)@171
    assign rightShiftStage0Idx1Rng1_uid19863_dupName_317_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_q[33:1];

    // rightShiftStage0Idx1_uid19865_dupName_317_i_unnamed_c_compstr0_shift_x(BITJOIN,19864)@171
    assign rightShiftStage0Idx1_uid19865_dupName_317_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19863_dupName_317_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27021_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x(BITSELECT,27020)@170
    assign leftShiftStage2Idx1Rng8_uid27021_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_in = leftShiftStage1_uid27019_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27021_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27021_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27022_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x(BITJOIN,27021)@170
    assign leftShiftStage2Idx1_uid27022_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27021_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27016_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x(BITSELECT,27015)@170
    assign leftShiftStage1Idx1Rng4_uid27016_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_in = leftShiftStage0_uid27014_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27016_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27016_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27017_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x(BITJOIN,27016)@170
    assign leftShiftStage1Idx1_uid27017_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27016_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27011_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x(BITSELECT,27010)@170
    assign leftShiftStage0Idx1Rng1_uid27011_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_79_c_compstr2246_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27011_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27011_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27012_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x(BITJOIN,27011)@170
    assign leftShiftStage0Idx1_uid27012_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27011_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19811_dupName_313_i_unnamed_c_compstr0_shift_x(BITSELECT,19810)@169
    assign rightShiftStage2Idx1Rng8_uid19811_dupName_313_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19810_dupName_313_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19813_dupName_313_i_unnamed_c_compstr0_shift_x(BITJOIN,19812)@169
    assign rightShiftStage2Idx1_uid19813_dupName_313_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19811_dupName_313_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19806_dupName_313_i_unnamed_c_compstr0_shift_x(BITSELECT,19805)@169
    assign rightShiftStage1Idx1Rng4_uid19806_dupName_313_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19805_dupName_313_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19808_dupName_313_i_unnamed_c_compstr0_shift_x(BITJOIN,19807)@169
    assign rightShiftStage1Idx1_uid19808_dupName_313_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19806_dupName_313_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19801_dupName_313_i_unnamed_c_compstr0_shift_x(BITSELECT,19800)@169
    assign rightShiftStage0Idx1Rng1_uid19801_dupName_313_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_q[33:1];

    // rightShiftStage0Idx1_uid19803_dupName_313_i_unnamed_c_compstr0_shift_x(BITJOIN,19802)@169
    assign rightShiftStage0Idx1_uid19803_dupName_313_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19801_dupName_313_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27003_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x(BITSELECT,27002)@168
    assign leftShiftStage2Idx1Rng8_uid27003_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_in = leftShiftStage1_uid27001_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27003_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27003_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27004_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x(BITJOIN,27003)@168
    assign leftShiftStage2Idx1_uid27004_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27003_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26998_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x(BITSELECT,26997)@168
    assign leftShiftStage1Idx1Rng4_uid26998_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_in = leftShiftStage0_uid26996_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26998_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26998_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26999_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x(BITJOIN,26998)@168
    assign leftShiftStage1Idx1_uid26999_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26998_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26993_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x(BITSELECT,26992)@168
    assign leftShiftStage0Idx1Rng1_uid26993_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_78_c_compstr2218_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26993_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26993_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26994_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x(BITJOIN,26993)@168
    assign leftShiftStage0Idx1_uid26994_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26993_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19749_dupName_309_i_unnamed_c_compstr0_shift_x(BITSELECT,19748)@167
    assign rightShiftStage2Idx1Rng8_uid19749_dupName_309_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19748_dupName_309_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19751_dupName_309_i_unnamed_c_compstr0_shift_x(BITJOIN,19750)@167
    assign rightShiftStage2Idx1_uid19751_dupName_309_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19749_dupName_309_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19744_dupName_309_i_unnamed_c_compstr0_shift_x(BITSELECT,19743)@167
    assign rightShiftStage1Idx1Rng4_uid19744_dupName_309_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19743_dupName_309_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19746_dupName_309_i_unnamed_c_compstr0_shift_x(BITJOIN,19745)@167
    assign rightShiftStage1Idx1_uid19746_dupName_309_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19744_dupName_309_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19739_dupName_309_i_unnamed_c_compstr0_shift_x(BITSELECT,19738)@167
    assign rightShiftStage0Idx1Rng1_uid19739_dupName_309_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_q[33:1];

    // rightShiftStage0Idx1_uid19741_dupName_309_i_unnamed_c_compstr0_shift_x(BITJOIN,19740)@167
    assign rightShiftStage0Idx1_uid19741_dupName_309_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19739_dupName_309_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26985_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x(BITSELECT,26984)@166
    assign leftShiftStage2Idx1Rng8_uid26985_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_in = leftShiftStage1_uid26983_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26985_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26985_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26986_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x(BITJOIN,26985)@166
    assign leftShiftStage2Idx1_uid26986_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26985_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26980_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x(BITSELECT,26979)@166
    assign leftShiftStage1Idx1Rng4_uid26980_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_in = leftShiftStage0_uid26978_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26980_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26980_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26981_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x(BITJOIN,26980)@166
    assign leftShiftStage1Idx1_uid26981_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26980_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26975_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x(BITSELECT,26974)@166
    assign leftShiftStage0Idx1Rng1_uid26975_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_77_c_compstr2190_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26975_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26975_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26976_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x(BITJOIN,26975)@166
    assign leftShiftStage0Idx1_uid26976_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26975_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19687_dupName_305_i_unnamed_c_compstr0_shift_x(BITSELECT,19686)@165
    assign rightShiftStage2Idx1Rng8_uid19687_dupName_305_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19686_dupName_305_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19689_dupName_305_i_unnamed_c_compstr0_shift_x(BITJOIN,19688)@165
    assign rightShiftStage2Idx1_uid19689_dupName_305_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19687_dupName_305_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19682_dupName_305_i_unnamed_c_compstr0_shift_x(BITSELECT,19681)@165
    assign rightShiftStage1Idx1Rng4_uid19682_dupName_305_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19681_dupName_305_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19684_dupName_305_i_unnamed_c_compstr0_shift_x(BITJOIN,19683)@165
    assign rightShiftStage1Idx1_uid19684_dupName_305_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19682_dupName_305_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19677_dupName_305_i_unnamed_c_compstr0_shift_x(BITSELECT,19676)@165
    assign rightShiftStage0Idx1Rng1_uid19677_dupName_305_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_q[33:1];

    // rightShiftStage0Idx1_uid19679_dupName_305_i_unnamed_c_compstr0_shift_x(BITJOIN,19678)@165
    assign rightShiftStage0Idx1_uid19679_dupName_305_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19677_dupName_305_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26967_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x(BITSELECT,26966)@164
    assign leftShiftStage2Idx1Rng8_uid26967_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_in = leftShiftStage1_uid26965_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26967_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26967_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26968_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x(BITJOIN,26967)@164
    assign leftShiftStage2Idx1_uid26968_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26967_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26962_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x(BITSELECT,26961)@164
    assign leftShiftStage1Idx1Rng4_uid26962_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_in = leftShiftStage0_uid26960_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26962_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26962_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26963_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x(BITJOIN,26962)@164
    assign leftShiftStage1Idx1_uid26963_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26962_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26957_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x(BITSELECT,26956)@164
    assign leftShiftStage0Idx1Rng1_uid26957_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_76_c_compstr2162_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26957_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26957_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26958_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x(BITJOIN,26957)@164
    assign leftShiftStage0Idx1_uid26958_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26957_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19625_dupName_301_i_unnamed_c_compstr0_shift_x(BITSELECT,19624)@163
    assign rightShiftStage2Idx1Rng8_uid19625_dupName_301_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19624_dupName_301_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19627_dupName_301_i_unnamed_c_compstr0_shift_x(BITJOIN,19626)@163
    assign rightShiftStage2Idx1_uid19627_dupName_301_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19625_dupName_301_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19620_dupName_301_i_unnamed_c_compstr0_shift_x(BITSELECT,19619)@163
    assign rightShiftStage1Idx1Rng4_uid19620_dupName_301_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19619_dupName_301_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19622_dupName_301_i_unnamed_c_compstr0_shift_x(BITJOIN,19621)@163
    assign rightShiftStage1Idx1_uid19622_dupName_301_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19620_dupName_301_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19615_dupName_301_i_unnamed_c_compstr0_shift_x(BITSELECT,19614)@163
    assign rightShiftStage0Idx1Rng1_uid19615_dupName_301_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_q[33:1];

    // rightShiftStage0Idx1_uid19617_dupName_301_i_unnamed_c_compstr0_shift_x(BITJOIN,19616)@163
    assign rightShiftStage0Idx1_uid19617_dupName_301_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19615_dupName_301_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26949_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x(BITSELECT,26948)@162
    assign leftShiftStage2Idx1Rng8_uid26949_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_in = leftShiftStage1_uid26947_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26949_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26949_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26950_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x(BITJOIN,26949)@162
    assign leftShiftStage2Idx1_uid26950_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26949_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26944_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x(BITSELECT,26943)@162
    assign leftShiftStage1Idx1Rng4_uid26944_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_in = leftShiftStage0_uid26942_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26944_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26944_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26945_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x(BITJOIN,26944)@162
    assign leftShiftStage1Idx1_uid26945_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26944_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26939_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x(BITSELECT,26938)@162
    assign leftShiftStage0Idx1Rng1_uid26939_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_75_c_compstr2134_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26939_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26939_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26940_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x(BITJOIN,26939)@162
    assign leftShiftStage0Idx1_uid26940_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26939_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19563_dupName_297_i_unnamed_c_compstr0_shift_x(BITSELECT,19562)@161
    assign rightShiftStage2Idx1Rng8_uid19563_dupName_297_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19562_dupName_297_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19565_dupName_297_i_unnamed_c_compstr0_shift_x(BITJOIN,19564)@161
    assign rightShiftStage2Idx1_uid19565_dupName_297_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19563_dupName_297_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19558_dupName_297_i_unnamed_c_compstr0_shift_x(BITSELECT,19557)@161
    assign rightShiftStage1Idx1Rng4_uid19558_dupName_297_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19557_dupName_297_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19560_dupName_297_i_unnamed_c_compstr0_shift_x(BITJOIN,19559)@161
    assign rightShiftStage1Idx1_uid19560_dupName_297_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19558_dupName_297_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19553_dupName_297_i_unnamed_c_compstr0_shift_x(BITSELECT,19552)@161
    assign rightShiftStage0Idx1Rng1_uid19553_dupName_297_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_q[33:1];

    // rightShiftStage0Idx1_uid19555_dupName_297_i_unnamed_c_compstr0_shift_x(BITJOIN,19554)@161
    assign rightShiftStage0Idx1_uid19555_dupName_297_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19553_dupName_297_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26931_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x(BITSELECT,26930)@160
    assign leftShiftStage2Idx1Rng8_uid26931_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_in = leftShiftStage1_uid26929_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26931_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26931_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26932_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x(BITJOIN,26931)@160
    assign leftShiftStage2Idx1_uid26932_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26931_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26926_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x(BITSELECT,26925)@160
    assign leftShiftStage1Idx1Rng4_uid26926_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_in = leftShiftStage0_uid26924_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26926_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26926_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26927_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x(BITJOIN,26926)@160
    assign leftShiftStage1Idx1_uid26927_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26926_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26921_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x(BITSELECT,26920)@160
    assign leftShiftStage0Idx1Rng1_uid26921_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_74_c_compstr2106_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26921_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26921_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26922_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x(BITJOIN,26921)@160
    assign leftShiftStage0Idx1_uid26922_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26921_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19501_dupName_293_i_unnamed_c_compstr0_shift_x(BITSELECT,19500)@159
    assign rightShiftStage2Idx1Rng8_uid19501_dupName_293_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19500_dupName_293_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19503_dupName_293_i_unnamed_c_compstr0_shift_x(BITJOIN,19502)@159
    assign rightShiftStage2Idx1_uid19503_dupName_293_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19501_dupName_293_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19496_dupName_293_i_unnamed_c_compstr0_shift_x(BITSELECT,19495)@159
    assign rightShiftStage1Idx1Rng4_uid19496_dupName_293_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19495_dupName_293_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19498_dupName_293_i_unnamed_c_compstr0_shift_x(BITJOIN,19497)@159
    assign rightShiftStage1Idx1_uid19498_dupName_293_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19496_dupName_293_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19491_dupName_293_i_unnamed_c_compstr0_shift_x(BITSELECT,19490)@159
    assign rightShiftStage0Idx1Rng1_uid19491_dupName_293_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_q[33:1];

    // rightShiftStage0Idx1_uid19493_dupName_293_i_unnamed_c_compstr0_shift_x(BITJOIN,19492)@159
    assign rightShiftStage0Idx1_uid19493_dupName_293_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19491_dupName_293_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26913_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x(BITSELECT,26912)@158
    assign leftShiftStage2Idx1Rng8_uid26913_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_in = leftShiftStage1_uid26911_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26913_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26913_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26914_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x(BITJOIN,26913)@158
    assign leftShiftStage2Idx1_uid26914_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26913_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26908_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x(BITSELECT,26907)@158
    assign leftShiftStage1Idx1Rng4_uid26908_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_in = leftShiftStage0_uid26906_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26908_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26908_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26909_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x(BITJOIN,26908)@158
    assign leftShiftStage1Idx1_uid26909_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26908_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26903_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x(BITSELECT,26902)@158
    assign leftShiftStage0Idx1Rng1_uid26903_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_73_c_compstr2078_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26903_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26903_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26904_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x(BITJOIN,26903)@158
    assign leftShiftStage0Idx1_uid26904_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26903_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19439_dupName_289_i_unnamed_c_compstr0_shift_x(BITSELECT,19438)@157
    assign rightShiftStage2Idx1Rng8_uid19439_dupName_289_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19438_dupName_289_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19441_dupName_289_i_unnamed_c_compstr0_shift_x(BITJOIN,19440)@157
    assign rightShiftStage2Idx1_uid19441_dupName_289_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19439_dupName_289_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19434_dupName_289_i_unnamed_c_compstr0_shift_x(BITSELECT,19433)@157
    assign rightShiftStage1Idx1Rng4_uid19434_dupName_289_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19433_dupName_289_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19436_dupName_289_i_unnamed_c_compstr0_shift_x(BITJOIN,19435)@157
    assign rightShiftStage1Idx1_uid19436_dupName_289_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19434_dupName_289_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19429_dupName_289_i_unnamed_c_compstr0_shift_x(BITSELECT,19428)@157
    assign rightShiftStage0Idx1Rng1_uid19429_dupName_289_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_q[33:1];

    // rightShiftStage0Idx1_uid19431_dupName_289_i_unnamed_c_compstr0_shift_x(BITJOIN,19430)@157
    assign rightShiftStage0Idx1_uid19431_dupName_289_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19429_dupName_289_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26895_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x(BITSELECT,26894)@156
    assign leftShiftStage2Idx1Rng8_uid26895_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_in = leftShiftStage1_uid26893_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26895_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26895_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26896_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x(BITJOIN,26895)@156
    assign leftShiftStage2Idx1_uid26896_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26895_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26890_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x(BITSELECT,26889)@156
    assign leftShiftStage1Idx1Rng4_uid26890_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_in = leftShiftStage0_uid26888_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26890_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26890_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26891_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x(BITJOIN,26890)@156
    assign leftShiftStage1Idx1_uid26891_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26890_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26885_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x(BITSELECT,26884)@156
    assign leftShiftStage0Idx1Rng1_uid26885_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_72_c_compstr2050_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26885_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26885_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26886_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x(BITJOIN,26885)@156
    assign leftShiftStage0Idx1_uid26886_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26885_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19377_dupName_285_i_unnamed_c_compstr0_shift_x(BITSELECT,19376)@155
    assign rightShiftStage2Idx1Rng8_uid19377_dupName_285_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19376_dupName_285_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19379_dupName_285_i_unnamed_c_compstr0_shift_x(BITJOIN,19378)@155
    assign rightShiftStage2Idx1_uid19379_dupName_285_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19377_dupName_285_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19372_dupName_285_i_unnamed_c_compstr0_shift_x(BITSELECT,19371)@155
    assign rightShiftStage1Idx1Rng4_uid19372_dupName_285_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19371_dupName_285_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19374_dupName_285_i_unnamed_c_compstr0_shift_x(BITJOIN,19373)@155
    assign rightShiftStage1Idx1_uid19374_dupName_285_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19372_dupName_285_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19367_dupName_285_i_unnamed_c_compstr0_shift_x(BITSELECT,19366)@155
    assign rightShiftStage0Idx1Rng1_uid19367_dupName_285_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_q[33:1];

    // rightShiftStage0Idx1_uid19369_dupName_285_i_unnamed_c_compstr0_shift_x(BITJOIN,19368)@155
    assign rightShiftStage0Idx1_uid19369_dupName_285_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19367_dupName_285_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26877_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x(BITSELECT,26876)@154
    assign leftShiftStage2Idx1Rng8_uid26877_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_in = leftShiftStage1_uid26875_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26877_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26877_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26878_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x(BITJOIN,26877)@154
    assign leftShiftStage2Idx1_uid26878_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26877_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26872_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x(BITSELECT,26871)@154
    assign leftShiftStage1Idx1Rng4_uid26872_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_in = leftShiftStage0_uid26870_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26872_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26872_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26873_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x(BITJOIN,26872)@154
    assign leftShiftStage1Idx1_uid26873_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26872_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26867_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x(BITSELECT,26866)@154
    assign leftShiftStage0Idx1Rng1_uid26867_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_71_c_compstr2022_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26867_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26867_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26868_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x(BITJOIN,26867)@154
    assign leftShiftStage0Idx1_uid26868_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26867_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19315_dupName_281_i_unnamed_c_compstr0_shift_x(BITSELECT,19314)@153
    assign rightShiftStage2Idx1Rng8_uid19315_dupName_281_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19314_dupName_281_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19317_dupName_281_i_unnamed_c_compstr0_shift_x(BITJOIN,19316)@153
    assign rightShiftStage2Idx1_uid19317_dupName_281_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19315_dupName_281_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19310_dupName_281_i_unnamed_c_compstr0_shift_x(BITSELECT,19309)@153
    assign rightShiftStage1Idx1Rng4_uid19310_dupName_281_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19309_dupName_281_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19312_dupName_281_i_unnamed_c_compstr0_shift_x(BITJOIN,19311)@153
    assign rightShiftStage1Idx1_uid19312_dupName_281_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19310_dupName_281_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19305_dupName_281_i_unnamed_c_compstr0_shift_x(BITSELECT,19304)@153
    assign rightShiftStage0Idx1Rng1_uid19305_dupName_281_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_q[33:1];

    // rightShiftStage0Idx1_uid19307_dupName_281_i_unnamed_c_compstr0_shift_x(BITJOIN,19306)@153
    assign rightShiftStage0Idx1_uid19307_dupName_281_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19305_dupName_281_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26859_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x(BITSELECT,26858)@152
    assign leftShiftStage2Idx1Rng8_uid26859_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_in = leftShiftStage1_uid26857_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26859_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26859_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26860_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x(BITJOIN,26859)@152
    assign leftShiftStage2Idx1_uid26860_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26859_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26854_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x(BITSELECT,26853)@152
    assign leftShiftStage1Idx1Rng4_uid26854_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_in = leftShiftStage0_uid26852_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26854_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26854_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26855_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x(BITJOIN,26854)@152
    assign leftShiftStage1Idx1_uid26855_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26854_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26849_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x(BITSELECT,26848)@152
    assign leftShiftStage0Idx1Rng1_uid26849_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_70_c_compstr1994_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26849_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26849_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26850_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x(BITJOIN,26849)@152
    assign leftShiftStage0Idx1_uid26850_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26849_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19253_dupName_277_i_unnamed_c_compstr0_shift_x(BITSELECT,19252)@151
    assign rightShiftStage2Idx1Rng8_uid19253_dupName_277_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19252_dupName_277_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19255_dupName_277_i_unnamed_c_compstr0_shift_x(BITJOIN,19254)@151
    assign rightShiftStage2Idx1_uid19255_dupName_277_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19253_dupName_277_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19248_dupName_277_i_unnamed_c_compstr0_shift_x(BITSELECT,19247)@151
    assign rightShiftStage1Idx1Rng4_uid19248_dupName_277_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19247_dupName_277_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19250_dupName_277_i_unnamed_c_compstr0_shift_x(BITJOIN,19249)@151
    assign rightShiftStage1Idx1_uid19250_dupName_277_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19248_dupName_277_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19243_dupName_277_i_unnamed_c_compstr0_shift_x(BITSELECT,19242)@151
    assign rightShiftStage0Idx1Rng1_uid19243_dupName_277_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_q[33:1];

    // rightShiftStage0Idx1_uid19245_dupName_277_i_unnamed_c_compstr0_shift_x(BITJOIN,19244)@151
    assign rightShiftStage0Idx1_uid19245_dupName_277_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19243_dupName_277_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26823_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x(BITSELECT,26822)@150
    assign leftShiftStage2Idx1Rng8_uid26823_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_in = leftShiftStage1_uid26821_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26823_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26823_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26824_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x(BITJOIN,26823)@150
    assign leftShiftStage2Idx1_uid26824_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26823_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26818_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x(BITSELECT,26817)@150
    assign leftShiftStage1Idx1Rng4_uid26818_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_in = leftShiftStage0_uid26816_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26818_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26818_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26819_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x(BITJOIN,26818)@150
    assign leftShiftStage1Idx1_uid26819_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26818_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26813_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x(BITSELECT,26812)@150
    assign leftShiftStage0Idx1Rng1_uid26813_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_69_c_compstr1966_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26813_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26813_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26814_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x(BITJOIN,26813)@150
    assign leftShiftStage0Idx1_uid26814_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26813_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19191_dupName_273_i_unnamed_c_compstr0_shift_x(BITSELECT,19190)@149
    assign rightShiftStage2Idx1Rng8_uid19191_dupName_273_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19190_dupName_273_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19193_dupName_273_i_unnamed_c_compstr0_shift_x(BITJOIN,19192)@149
    assign rightShiftStage2Idx1_uid19193_dupName_273_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19191_dupName_273_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19186_dupName_273_i_unnamed_c_compstr0_shift_x(BITSELECT,19185)@149
    assign rightShiftStage1Idx1Rng4_uid19186_dupName_273_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19185_dupName_273_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19188_dupName_273_i_unnamed_c_compstr0_shift_x(BITJOIN,19187)@149
    assign rightShiftStage1Idx1_uid19188_dupName_273_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19186_dupName_273_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19181_dupName_273_i_unnamed_c_compstr0_shift_x(BITSELECT,19180)@149
    assign rightShiftStage0Idx1Rng1_uid19181_dupName_273_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_q[33:1];

    // rightShiftStage0Idx1_uid19183_dupName_273_i_unnamed_c_compstr0_shift_x(BITJOIN,19182)@149
    assign rightShiftStage0Idx1_uid19183_dupName_273_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19181_dupName_273_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26805_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x(BITSELECT,26804)@148
    assign leftShiftStage2Idx1Rng8_uid26805_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_in = leftShiftStage1_uid26803_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26805_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26805_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26806_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x(BITJOIN,26805)@148
    assign leftShiftStage2Idx1_uid26806_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26805_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26800_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x(BITSELECT,26799)@148
    assign leftShiftStage1Idx1Rng4_uid26800_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_in = leftShiftStage0_uid26798_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26800_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26800_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26801_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x(BITJOIN,26800)@148
    assign leftShiftStage1Idx1_uid26801_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26800_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26795_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x(BITSELECT,26794)@148
    assign leftShiftStage0Idx1Rng1_uid26795_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_68_c_compstr1938_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26795_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26795_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26796_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x(BITJOIN,26795)@148
    assign leftShiftStage0Idx1_uid26796_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26795_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19129_dupName_269_i_unnamed_c_compstr0_shift_x(BITSELECT,19128)@147
    assign rightShiftStage2Idx1Rng8_uid19129_dupName_269_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19128_dupName_269_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19131_dupName_269_i_unnamed_c_compstr0_shift_x(BITJOIN,19130)@147
    assign rightShiftStage2Idx1_uid19131_dupName_269_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19129_dupName_269_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19124_dupName_269_i_unnamed_c_compstr0_shift_x(BITSELECT,19123)@147
    assign rightShiftStage1Idx1Rng4_uid19124_dupName_269_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19123_dupName_269_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19126_dupName_269_i_unnamed_c_compstr0_shift_x(BITJOIN,19125)@147
    assign rightShiftStage1Idx1_uid19126_dupName_269_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19124_dupName_269_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19119_dupName_269_i_unnamed_c_compstr0_shift_x(BITSELECT,19118)@147
    assign rightShiftStage0Idx1Rng1_uid19119_dupName_269_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_q[33:1];

    // rightShiftStage0Idx1_uid19121_dupName_269_i_unnamed_c_compstr0_shift_x(BITJOIN,19120)@147
    assign rightShiftStage0Idx1_uid19121_dupName_269_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19119_dupName_269_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26787_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x(BITSELECT,26786)@146
    assign leftShiftStage2Idx1Rng8_uid26787_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_in = leftShiftStage1_uid26785_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26787_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26787_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26788_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x(BITJOIN,26787)@146
    assign leftShiftStage2Idx1_uid26788_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26787_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26782_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x(BITSELECT,26781)@146
    assign leftShiftStage1Idx1Rng4_uid26782_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_in = leftShiftStage0_uid26780_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26782_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26782_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26783_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x(BITJOIN,26782)@146
    assign leftShiftStage1Idx1_uid26783_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26782_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26777_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x(BITSELECT,26776)@146
    assign leftShiftStage0Idx1Rng1_uid26777_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_67_c_compstr1910_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26777_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26777_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26778_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x(BITJOIN,26777)@146
    assign leftShiftStage0Idx1_uid26778_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26777_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19067_dupName_265_i_unnamed_c_compstr0_shift_x(BITSELECT,19066)@145
    assign rightShiftStage2Idx1Rng8_uid19067_dupName_265_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19066_dupName_265_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19069_dupName_265_i_unnamed_c_compstr0_shift_x(BITJOIN,19068)@145
    assign rightShiftStage2Idx1_uid19069_dupName_265_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19067_dupName_265_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19062_dupName_265_i_unnamed_c_compstr0_shift_x(BITSELECT,19061)@145
    assign rightShiftStage1Idx1Rng4_uid19062_dupName_265_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19061_dupName_265_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19064_dupName_265_i_unnamed_c_compstr0_shift_x(BITJOIN,19063)@145
    assign rightShiftStage1Idx1_uid19064_dupName_265_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19062_dupName_265_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19057_dupName_265_i_unnamed_c_compstr0_shift_x(BITSELECT,19056)@145
    assign rightShiftStage0Idx1Rng1_uid19057_dupName_265_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_q[33:1];

    // rightShiftStage0Idx1_uid19059_dupName_265_i_unnamed_c_compstr0_shift_x(BITJOIN,19058)@145
    assign rightShiftStage0Idx1_uid19059_dupName_265_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19057_dupName_265_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26769_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x(BITSELECT,26768)@144
    assign leftShiftStage2Idx1Rng8_uid26769_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_in = leftShiftStage1_uid26767_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26769_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26769_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26770_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x(BITJOIN,26769)@144
    assign leftShiftStage2Idx1_uid26770_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26769_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26764_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x(BITSELECT,26763)@144
    assign leftShiftStage1Idx1Rng4_uid26764_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_in = leftShiftStage0_uid26762_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26764_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26764_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26765_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x(BITJOIN,26764)@144
    assign leftShiftStage1Idx1_uid26765_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26764_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26759_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x(BITSELECT,26758)@144
    assign leftShiftStage0Idx1Rng1_uid26759_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_66_c_compstr1882_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26759_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26759_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26760_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x(BITJOIN,26759)@144
    assign leftShiftStage0Idx1_uid26760_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26759_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19005_dupName_261_i_unnamed_c_compstr0_shift_x(BITSELECT,19004)@143
    assign rightShiftStage2Idx1Rng8_uid19005_dupName_261_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19004_dupName_261_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19007_dupName_261_i_unnamed_c_compstr0_shift_x(BITJOIN,19006)@143
    assign rightShiftStage2Idx1_uid19007_dupName_261_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19005_dupName_261_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19000_dupName_261_i_unnamed_c_compstr0_shift_x(BITSELECT,18999)@143
    assign rightShiftStage1Idx1Rng4_uid19000_dupName_261_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18999_dupName_261_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19002_dupName_261_i_unnamed_c_compstr0_shift_x(BITJOIN,19001)@143
    assign rightShiftStage1Idx1_uid19002_dupName_261_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19000_dupName_261_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18995_dupName_261_i_unnamed_c_compstr0_shift_x(BITSELECT,18994)@143
    assign rightShiftStage0Idx1Rng1_uid18995_dupName_261_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_q[33:1];

    // rightShiftStage0Idx1_uid18997_dupName_261_i_unnamed_c_compstr0_shift_x(BITJOIN,18996)@143
    assign rightShiftStage0Idx1_uid18997_dupName_261_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18995_dupName_261_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26751_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x(BITSELECT,26750)@142
    assign leftShiftStage2Idx1Rng8_uid26751_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_in = leftShiftStage1_uid26749_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26751_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26751_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26752_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x(BITJOIN,26751)@142
    assign leftShiftStage2Idx1_uid26752_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26751_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26746_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x(BITSELECT,26745)@142
    assign leftShiftStage1Idx1Rng4_uid26746_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_in = leftShiftStage0_uid26744_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26746_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26746_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26747_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x(BITJOIN,26746)@142
    assign leftShiftStage1Idx1_uid26747_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26746_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26741_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x(BITSELECT,26740)@142
    assign leftShiftStage0Idx1Rng1_uid26741_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_65_c_compstr1854_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26741_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26741_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26742_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x(BITJOIN,26741)@142
    assign leftShiftStage0Idx1_uid26742_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26741_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18943_dupName_257_i_unnamed_c_compstr0_shift_x(BITSELECT,18942)@141
    assign rightShiftStage2Idx1Rng8_uid18943_dupName_257_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18942_dupName_257_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18945_dupName_257_i_unnamed_c_compstr0_shift_x(BITJOIN,18944)@141
    assign rightShiftStage2Idx1_uid18945_dupName_257_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18943_dupName_257_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18938_dupName_257_i_unnamed_c_compstr0_shift_x(BITSELECT,18937)@141
    assign rightShiftStage1Idx1Rng4_uid18938_dupName_257_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18937_dupName_257_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18940_dupName_257_i_unnamed_c_compstr0_shift_x(BITJOIN,18939)@141
    assign rightShiftStage1Idx1_uid18940_dupName_257_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18938_dupName_257_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18933_dupName_257_i_unnamed_c_compstr0_shift_x(BITSELECT,18932)@141
    assign rightShiftStage0Idx1Rng1_uid18933_dupName_257_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_q[33:1];

    // rightShiftStage0Idx1_uid18935_dupName_257_i_unnamed_c_compstr0_shift_x(BITJOIN,18934)@141
    assign rightShiftStage0Idx1_uid18935_dupName_257_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18933_dupName_257_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26733_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x(BITSELECT,26732)@140
    assign leftShiftStage2Idx1Rng8_uid26733_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_in = leftShiftStage1_uid26731_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26733_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26733_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26734_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x(BITJOIN,26733)@140
    assign leftShiftStage2Idx1_uid26734_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26733_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26728_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x(BITSELECT,26727)@140
    assign leftShiftStage1Idx1Rng4_uid26728_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_in = leftShiftStage0_uid26726_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26728_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26728_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26729_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x(BITJOIN,26728)@140
    assign leftShiftStage1Idx1_uid26729_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26728_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26723_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x(BITSELECT,26722)@140
    assign leftShiftStage0Idx1Rng1_uid26723_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_64_c_compstr1826_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26723_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26723_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26724_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x(BITJOIN,26723)@140
    assign leftShiftStage0Idx1_uid26724_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26723_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18881_dupName_253_i_unnamed_c_compstr0_shift_x(BITSELECT,18880)@139
    assign rightShiftStage2Idx1Rng8_uid18881_dupName_253_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18880_dupName_253_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18883_dupName_253_i_unnamed_c_compstr0_shift_x(BITJOIN,18882)@139
    assign rightShiftStage2Idx1_uid18883_dupName_253_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18881_dupName_253_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18876_dupName_253_i_unnamed_c_compstr0_shift_x(BITSELECT,18875)@139
    assign rightShiftStage1Idx1Rng4_uid18876_dupName_253_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18875_dupName_253_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18878_dupName_253_i_unnamed_c_compstr0_shift_x(BITJOIN,18877)@139
    assign rightShiftStage1Idx1_uid18878_dupName_253_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18876_dupName_253_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18871_dupName_253_i_unnamed_c_compstr0_shift_x(BITSELECT,18870)@139
    assign rightShiftStage0Idx1Rng1_uid18871_dupName_253_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_q[33:1];

    // rightShiftStage0Idx1_uid18873_dupName_253_i_unnamed_c_compstr0_shift_x(BITJOIN,18872)@139
    assign rightShiftStage0Idx1_uid18873_dupName_253_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18871_dupName_253_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26715_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x(BITSELECT,26714)@138
    assign leftShiftStage2Idx1Rng8_uid26715_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_in = leftShiftStage1_uid26713_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26715_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26715_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26716_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x(BITJOIN,26715)@138
    assign leftShiftStage2Idx1_uid26716_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26715_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26710_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x(BITSELECT,26709)@138
    assign leftShiftStage1Idx1Rng4_uid26710_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_in = leftShiftStage0_uid26708_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26710_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26710_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26711_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x(BITJOIN,26710)@138
    assign leftShiftStage1Idx1_uid26711_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26710_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26705_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x(BITSELECT,26704)@138
    assign leftShiftStage0Idx1Rng1_uid26705_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_63_c_compstr1798_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26705_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26705_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26706_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x(BITJOIN,26705)@138
    assign leftShiftStage0Idx1_uid26706_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26705_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18819_dupName_249_i_unnamed_c_compstr0_shift_x(BITSELECT,18818)@137
    assign rightShiftStage2Idx1Rng8_uid18819_dupName_249_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18818_dupName_249_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18821_dupName_249_i_unnamed_c_compstr0_shift_x(BITJOIN,18820)@137
    assign rightShiftStage2Idx1_uid18821_dupName_249_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18819_dupName_249_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18814_dupName_249_i_unnamed_c_compstr0_shift_x(BITSELECT,18813)@137
    assign rightShiftStage1Idx1Rng4_uid18814_dupName_249_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18813_dupName_249_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18816_dupName_249_i_unnamed_c_compstr0_shift_x(BITJOIN,18815)@137
    assign rightShiftStage1Idx1_uid18816_dupName_249_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18814_dupName_249_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18809_dupName_249_i_unnamed_c_compstr0_shift_x(BITSELECT,18808)@137
    assign rightShiftStage0Idx1Rng1_uid18809_dupName_249_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_q[33:1];

    // rightShiftStage0Idx1_uid18811_dupName_249_i_unnamed_c_compstr0_shift_x(BITJOIN,18810)@137
    assign rightShiftStage0Idx1_uid18811_dupName_249_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18809_dupName_249_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26697_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x(BITSELECT,26696)@136
    assign leftShiftStage2Idx1Rng8_uid26697_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_in = leftShiftStage1_uid26695_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26697_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26697_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26698_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x(BITJOIN,26697)@136
    assign leftShiftStage2Idx1_uid26698_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26697_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26692_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x(BITSELECT,26691)@136
    assign leftShiftStage1Idx1Rng4_uid26692_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_in = leftShiftStage0_uid26690_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26692_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26692_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26693_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x(BITJOIN,26692)@136
    assign leftShiftStage1Idx1_uid26693_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26692_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26687_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x(BITSELECT,26686)@136
    assign leftShiftStage0Idx1Rng1_uid26687_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_62_c_compstr1770_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26687_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26687_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26688_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x(BITJOIN,26687)@136
    assign leftShiftStage0Idx1_uid26688_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26687_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18757_dupName_245_i_unnamed_c_compstr0_shift_x(BITSELECT,18756)@135
    assign rightShiftStage2Idx1Rng8_uid18757_dupName_245_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18756_dupName_245_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18759_dupName_245_i_unnamed_c_compstr0_shift_x(BITJOIN,18758)@135
    assign rightShiftStage2Idx1_uid18759_dupName_245_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18757_dupName_245_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18752_dupName_245_i_unnamed_c_compstr0_shift_x(BITSELECT,18751)@135
    assign rightShiftStage1Idx1Rng4_uid18752_dupName_245_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18751_dupName_245_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18754_dupName_245_i_unnamed_c_compstr0_shift_x(BITJOIN,18753)@135
    assign rightShiftStage1Idx1_uid18754_dupName_245_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18752_dupName_245_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18747_dupName_245_i_unnamed_c_compstr0_shift_x(BITSELECT,18746)@135
    assign rightShiftStage0Idx1Rng1_uid18747_dupName_245_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_q[33:1];

    // rightShiftStage0Idx1_uid18749_dupName_245_i_unnamed_c_compstr0_shift_x(BITJOIN,18748)@135
    assign rightShiftStage0Idx1_uid18749_dupName_245_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18747_dupName_245_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26679_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x(BITSELECT,26678)@134
    assign leftShiftStage2Idx1Rng8_uid26679_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_in = leftShiftStage1_uid26677_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26679_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26679_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26680_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x(BITJOIN,26679)@134
    assign leftShiftStage2Idx1_uid26680_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26679_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26674_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x(BITSELECT,26673)@134
    assign leftShiftStage1Idx1Rng4_uid26674_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_in = leftShiftStage0_uid26672_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26674_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26674_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26675_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x(BITJOIN,26674)@134
    assign leftShiftStage1Idx1_uid26675_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26674_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26669_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x(BITSELECT,26668)@134
    assign leftShiftStage0Idx1Rng1_uid26669_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_61_c_compstr1742_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26669_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26669_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26670_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x(BITJOIN,26669)@134
    assign leftShiftStage0Idx1_uid26670_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26669_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18695_dupName_241_i_unnamed_c_compstr0_shift_x(BITSELECT,18694)@133
    assign rightShiftStage2Idx1Rng8_uid18695_dupName_241_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18694_dupName_241_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18697_dupName_241_i_unnamed_c_compstr0_shift_x(BITJOIN,18696)@133
    assign rightShiftStage2Idx1_uid18697_dupName_241_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18695_dupName_241_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18690_dupName_241_i_unnamed_c_compstr0_shift_x(BITSELECT,18689)@133
    assign rightShiftStage1Idx1Rng4_uid18690_dupName_241_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18689_dupName_241_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18692_dupName_241_i_unnamed_c_compstr0_shift_x(BITJOIN,18691)@133
    assign rightShiftStage1Idx1_uid18692_dupName_241_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18690_dupName_241_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18685_dupName_241_i_unnamed_c_compstr0_shift_x(BITSELECT,18684)@133
    assign rightShiftStage0Idx1Rng1_uid18685_dupName_241_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_q[33:1];

    // rightShiftStage0Idx1_uid18687_dupName_241_i_unnamed_c_compstr0_shift_x(BITJOIN,18686)@133
    assign rightShiftStage0Idx1_uid18687_dupName_241_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18685_dupName_241_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26661_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x(BITSELECT,26660)@132
    assign leftShiftStage2Idx1Rng8_uid26661_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_in = leftShiftStage1_uid26659_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26661_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26661_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26662_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x(BITJOIN,26661)@132
    assign leftShiftStage2Idx1_uid26662_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26661_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26656_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x(BITSELECT,26655)@132
    assign leftShiftStage1Idx1Rng4_uid26656_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_in = leftShiftStage0_uid26654_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26656_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26656_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26657_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x(BITJOIN,26656)@132
    assign leftShiftStage1Idx1_uid26657_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26656_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26651_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x(BITSELECT,26650)@132
    assign leftShiftStage0Idx1Rng1_uid26651_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_60_c_compstr1714_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26651_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26651_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26652_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x(BITJOIN,26651)@132
    assign leftShiftStage0Idx1_uid26652_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26651_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18633_dupName_237_i_unnamed_c_compstr0_shift_x(BITSELECT,18632)@131
    assign rightShiftStage2Idx1Rng8_uid18633_dupName_237_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18632_dupName_237_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18635_dupName_237_i_unnamed_c_compstr0_shift_x(BITJOIN,18634)@131
    assign rightShiftStage2Idx1_uid18635_dupName_237_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18633_dupName_237_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18628_dupName_237_i_unnamed_c_compstr0_shift_x(BITSELECT,18627)@131
    assign rightShiftStage1Idx1Rng4_uid18628_dupName_237_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18627_dupName_237_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18630_dupName_237_i_unnamed_c_compstr0_shift_x(BITJOIN,18629)@131
    assign rightShiftStage1Idx1_uid18630_dupName_237_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18628_dupName_237_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18623_dupName_237_i_unnamed_c_compstr0_shift_x(BITSELECT,18622)@131
    assign rightShiftStage0Idx1Rng1_uid18623_dupName_237_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_q[33:1];

    // rightShiftStage0Idx1_uid18625_dupName_237_i_unnamed_c_compstr0_shift_x(BITJOIN,18624)@131
    assign rightShiftStage0Idx1_uid18625_dupName_237_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18623_dupName_237_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26625_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x(BITSELECT,26624)@130
    assign leftShiftStage2Idx1Rng8_uid26625_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_in = leftShiftStage1_uid26623_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26625_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26625_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26626_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x(BITJOIN,26625)@130
    assign leftShiftStage2Idx1_uid26626_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26625_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26620_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x(BITSELECT,26619)@130
    assign leftShiftStage1Idx1Rng4_uid26620_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_in = leftShiftStage0_uid26618_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26620_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26620_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26621_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x(BITJOIN,26620)@130
    assign leftShiftStage1Idx1_uid26621_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26620_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26615_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x(BITSELECT,26614)@130
    assign leftShiftStage0Idx1Rng1_uid26615_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_59_c_compstr1686_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26615_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26615_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26616_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x(BITJOIN,26615)@130
    assign leftShiftStage0Idx1_uid26616_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26615_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18571_dupName_233_i_unnamed_c_compstr0_shift_x(BITSELECT,18570)@129
    assign rightShiftStage2Idx1Rng8_uid18571_dupName_233_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18570_dupName_233_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18573_dupName_233_i_unnamed_c_compstr0_shift_x(BITJOIN,18572)@129
    assign rightShiftStage2Idx1_uid18573_dupName_233_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18571_dupName_233_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18566_dupName_233_i_unnamed_c_compstr0_shift_x(BITSELECT,18565)@129
    assign rightShiftStage1Idx1Rng4_uid18566_dupName_233_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18565_dupName_233_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18568_dupName_233_i_unnamed_c_compstr0_shift_x(BITJOIN,18567)@129
    assign rightShiftStage1Idx1_uid18568_dupName_233_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18566_dupName_233_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18561_dupName_233_i_unnamed_c_compstr0_shift_x(BITSELECT,18560)@129
    assign rightShiftStage0Idx1Rng1_uid18561_dupName_233_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_q[33:1];

    // rightShiftStage0Idx1_uid18563_dupName_233_i_unnamed_c_compstr0_shift_x(BITJOIN,18562)@129
    assign rightShiftStage0Idx1_uid18563_dupName_233_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18561_dupName_233_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26607_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x(BITSELECT,26606)@128
    assign leftShiftStage2Idx1Rng8_uid26607_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_in = leftShiftStage1_uid26605_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26607_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26607_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26608_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x(BITJOIN,26607)@128
    assign leftShiftStage2Idx1_uid26608_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26607_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26602_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x(BITSELECT,26601)@128
    assign leftShiftStage1Idx1Rng4_uid26602_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_in = leftShiftStage0_uid26600_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26602_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26602_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26603_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x(BITJOIN,26602)@128
    assign leftShiftStage1Idx1_uid26603_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26602_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26597_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x(BITSELECT,26596)@128
    assign leftShiftStage0Idx1Rng1_uid26597_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_58_c_compstr1658_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26597_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26597_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26598_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x(BITJOIN,26597)@128
    assign leftShiftStage0Idx1_uid26598_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26597_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18509_dupName_229_i_unnamed_c_compstr0_shift_x(BITSELECT,18508)@127
    assign rightShiftStage2Idx1Rng8_uid18509_dupName_229_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18508_dupName_229_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18511_dupName_229_i_unnamed_c_compstr0_shift_x(BITJOIN,18510)@127
    assign rightShiftStage2Idx1_uid18511_dupName_229_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18509_dupName_229_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18504_dupName_229_i_unnamed_c_compstr0_shift_x(BITSELECT,18503)@127
    assign rightShiftStage1Idx1Rng4_uid18504_dupName_229_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18503_dupName_229_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18506_dupName_229_i_unnamed_c_compstr0_shift_x(BITJOIN,18505)@127
    assign rightShiftStage1Idx1_uid18506_dupName_229_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18504_dupName_229_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18499_dupName_229_i_unnamed_c_compstr0_shift_x(BITSELECT,18498)@127
    assign rightShiftStage0Idx1Rng1_uid18499_dupName_229_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_q[33:1];

    // rightShiftStage0Idx1_uid18501_dupName_229_i_unnamed_c_compstr0_shift_x(BITJOIN,18500)@127
    assign rightShiftStage0Idx1_uid18501_dupName_229_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18499_dupName_229_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26589_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x(BITSELECT,26588)@126
    assign leftShiftStage2Idx1Rng8_uid26589_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_in = leftShiftStage1_uid26587_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26589_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26589_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26590_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x(BITJOIN,26589)@126
    assign leftShiftStage2Idx1_uid26590_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26589_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26584_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x(BITSELECT,26583)@126
    assign leftShiftStage1Idx1Rng4_uid26584_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_in = leftShiftStage0_uid26582_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26584_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26584_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26585_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x(BITJOIN,26584)@126
    assign leftShiftStage1Idx1_uid26585_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26584_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26579_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x(BITSELECT,26578)@126
    assign leftShiftStage0Idx1Rng1_uid26579_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_57_c_compstr1630_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26579_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26579_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26580_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x(BITJOIN,26579)@126
    assign leftShiftStage0Idx1_uid26580_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26579_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18447_dupName_225_i_unnamed_c_compstr0_shift_x(BITSELECT,18446)@125
    assign rightShiftStage2Idx1Rng8_uid18447_dupName_225_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18446_dupName_225_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18449_dupName_225_i_unnamed_c_compstr0_shift_x(BITJOIN,18448)@125
    assign rightShiftStage2Idx1_uid18449_dupName_225_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18447_dupName_225_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18442_dupName_225_i_unnamed_c_compstr0_shift_x(BITSELECT,18441)@125
    assign rightShiftStage1Idx1Rng4_uid18442_dupName_225_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18441_dupName_225_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18444_dupName_225_i_unnamed_c_compstr0_shift_x(BITJOIN,18443)@125
    assign rightShiftStage1Idx1_uid18444_dupName_225_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18442_dupName_225_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18437_dupName_225_i_unnamed_c_compstr0_shift_x(BITSELECT,18436)@125
    assign rightShiftStage0Idx1Rng1_uid18437_dupName_225_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_q[33:1];

    // rightShiftStage0Idx1_uid18439_dupName_225_i_unnamed_c_compstr0_shift_x(BITJOIN,18438)@125
    assign rightShiftStage0Idx1_uid18439_dupName_225_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18437_dupName_225_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26571_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x(BITSELECT,26570)@124
    assign leftShiftStage2Idx1Rng8_uid26571_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_in = leftShiftStage1_uid26569_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26571_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26571_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26572_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x(BITJOIN,26571)@124
    assign leftShiftStage2Idx1_uid26572_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26571_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26566_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x(BITSELECT,26565)@124
    assign leftShiftStage1Idx1Rng4_uid26566_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_in = leftShiftStage0_uid26564_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26566_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26566_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26567_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x(BITJOIN,26566)@124
    assign leftShiftStage1Idx1_uid26567_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26566_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26561_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x(BITSELECT,26560)@124
    assign leftShiftStage0Idx1Rng1_uid26561_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_56_c_compstr1602_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26561_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26561_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26562_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x(BITJOIN,26561)@124
    assign leftShiftStage0Idx1_uid26562_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26561_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18385_dupName_221_i_unnamed_c_compstr0_shift_x(BITSELECT,18384)@123
    assign rightShiftStage2Idx1Rng8_uid18385_dupName_221_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18384_dupName_221_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18387_dupName_221_i_unnamed_c_compstr0_shift_x(BITJOIN,18386)@123
    assign rightShiftStage2Idx1_uid18387_dupName_221_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18385_dupName_221_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18380_dupName_221_i_unnamed_c_compstr0_shift_x(BITSELECT,18379)@123
    assign rightShiftStage1Idx1Rng4_uid18380_dupName_221_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18379_dupName_221_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18382_dupName_221_i_unnamed_c_compstr0_shift_x(BITJOIN,18381)@123
    assign rightShiftStage1Idx1_uid18382_dupName_221_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18380_dupName_221_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18375_dupName_221_i_unnamed_c_compstr0_shift_x(BITSELECT,18374)@123
    assign rightShiftStage0Idx1Rng1_uid18375_dupName_221_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_q[33:1];

    // rightShiftStage0Idx1_uid18377_dupName_221_i_unnamed_c_compstr0_shift_x(BITJOIN,18376)@123
    assign rightShiftStage0Idx1_uid18377_dupName_221_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18375_dupName_221_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26553_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x(BITSELECT,26552)@122
    assign leftShiftStage2Idx1Rng8_uid26553_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_in = leftShiftStage1_uid26551_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26553_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26553_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26554_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x(BITJOIN,26553)@122
    assign leftShiftStage2Idx1_uid26554_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26553_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26548_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x(BITSELECT,26547)@122
    assign leftShiftStage1Idx1Rng4_uid26548_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_in = leftShiftStage0_uid26546_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26548_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26548_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26549_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x(BITJOIN,26548)@122
    assign leftShiftStage1Idx1_uid26549_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26548_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26543_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x(BITSELECT,26542)@122
    assign leftShiftStage0Idx1Rng1_uid26543_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_55_c_compstr1574_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26543_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26543_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26544_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x(BITJOIN,26543)@122
    assign leftShiftStage0Idx1_uid26544_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26543_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18323_dupName_217_i_unnamed_c_compstr0_shift_x(BITSELECT,18322)@121
    assign rightShiftStage2Idx1Rng8_uid18323_dupName_217_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18322_dupName_217_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18325_dupName_217_i_unnamed_c_compstr0_shift_x(BITJOIN,18324)@121
    assign rightShiftStage2Idx1_uid18325_dupName_217_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18323_dupName_217_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18318_dupName_217_i_unnamed_c_compstr0_shift_x(BITSELECT,18317)@121
    assign rightShiftStage1Idx1Rng4_uid18318_dupName_217_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18317_dupName_217_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18320_dupName_217_i_unnamed_c_compstr0_shift_x(BITJOIN,18319)@121
    assign rightShiftStage1Idx1_uid18320_dupName_217_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18318_dupName_217_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18313_dupName_217_i_unnamed_c_compstr0_shift_x(BITSELECT,18312)@121
    assign rightShiftStage0Idx1Rng1_uid18313_dupName_217_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_q[33:1];

    // rightShiftStage0Idx1_uid18315_dupName_217_i_unnamed_c_compstr0_shift_x(BITJOIN,18314)@121
    assign rightShiftStage0Idx1_uid18315_dupName_217_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18313_dupName_217_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26535_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x(BITSELECT,26534)@120
    assign leftShiftStage2Idx1Rng8_uid26535_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_in = leftShiftStage1_uid26533_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26535_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26535_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26536_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x(BITJOIN,26535)@120
    assign leftShiftStage2Idx1_uid26536_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26535_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26530_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x(BITSELECT,26529)@120
    assign leftShiftStage1Idx1Rng4_uid26530_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_in = leftShiftStage0_uid26528_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26530_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26530_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26531_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x(BITJOIN,26530)@120
    assign leftShiftStage1Idx1_uid26531_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26530_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26525_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x(BITSELECT,26524)@120
    assign leftShiftStage0Idx1Rng1_uid26525_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_54_c_compstr1546_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26525_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26525_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26526_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x(BITJOIN,26525)@120
    assign leftShiftStage0Idx1_uid26526_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26525_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18261_dupName_213_i_unnamed_c_compstr0_shift_x(BITSELECT,18260)@119
    assign rightShiftStage2Idx1Rng8_uid18261_dupName_213_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18260_dupName_213_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18263_dupName_213_i_unnamed_c_compstr0_shift_x(BITJOIN,18262)@119
    assign rightShiftStage2Idx1_uid18263_dupName_213_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18261_dupName_213_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18256_dupName_213_i_unnamed_c_compstr0_shift_x(BITSELECT,18255)@119
    assign rightShiftStage1Idx1Rng4_uid18256_dupName_213_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18255_dupName_213_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18258_dupName_213_i_unnamed_c_compstr0_shift_x(BITJOIN,18257)@119
    assign rightShiftStage1Idx1_uid18258_dupName_213_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18256_dupName_213_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18251_dupName_213_i_unnamed_c_compstr0_shift_x(BITSELECT,18250)@119
    assign rightShiftStage0Idx1Rng1_uid18251_dupName_213_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_q[33:1];

    // rightShiftStage0Idx1_uid18253_dupName_213_i_unnamed_c_compstr0_shift_x(BITJOIN,18252)@119
    assign rightShiftStage0Idx1_uid18253_dupName_213_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18251_dupName_213_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26517_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x(BITSELECT,26516)@118
    assign leftShiftStage2Idx1Rng8_uid26517_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_in = leftShiftStage1_uid26515_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26517_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26517_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26518_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x(BITJOIN,26517)@118
    assign leftShiftStage2Idx1_uid26518_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26517_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26512_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x(BITSELECT,26511)@118
    assign leftShiftStage1Idx1Rng4_uid26512_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_in = leftShiftStage0_uid26510_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26512_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26512_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26513_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x(BITJOIN,26512)@118
    assign leftShiftStage1Idx1_uid26513_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26512_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26507_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x(BITSELECT,26506)@118
    assign leftShiftStage0Idx1Rng1_uid26507_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_53_c_compstr1518_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26507_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26507_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26508_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x(BITJOIN,26507)@118
    assign leftShiftStage0Idx1_uid26508_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26507_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18199_dupName_209_i_unnamed_c_compstr0_shift_x(BITSELECT,18198)@117
    assign rightShiftStage2Idx1Rng8_uid18199_dupName_209_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18198_dupName_209_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18201_dupName_209_i_unnamed_c_compstr0_shift_x(BITJOIN,18200)@117
    assign rightShiftStage2Idx1_uid18201_dupName_209_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18199_dupName_209_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18194_dupName_209_i_unnamed_c_compstr0_shift_x(BITSELECT,18193)@117
    assign rightShiftStage1Idx1Rng4_uid18194_dupName_209_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18193_dupName_209_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18196_dupName_209_i_unnamed_c_compstr0_shift_x(BITJOIN,18195)@117
    assign rightShiftStage1Idx1_uid18196_dupName_209_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18194_dupName_209_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18189_dupName_209_i_unnamed_c_compstr0_shift_x(BITSELECT,18188)@117
    assign rightShiftStage0Idx1Rng1_uid18189_dupName_209_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_q[33:1];

    // rightShiftStage0Idx1_uid18191_dupName_209_i_unnamed_c_compstr0_shift_x(BITJOIN,18190)@117
    assign rightShiftStage0Idx1_uid18191_dupName_209_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18189_dupName_209_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26499_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x(BITSELECT,26498)@116
    assign leftShiftStage2Idx1Rng8_uid26499_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_in = leftShiftStage1_uid26497_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26499_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26499_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26500_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x(BITJOIN,26499)@116
    assign leftShiftStage2Idx1_uid26500_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26499_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26494_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x(BITSELECT,26493)@116
    assign leftShiftStage1Idx1Rng4_uid26494_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_in = leftShiftStage0_uid26492_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26494_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26494_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26495_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x(BITJOIN,26494)@116
    assign leftShiftStage1Idx1_uid26495_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26494_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26489_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x(BITSELECT,26488)@116
    assign leftShiftStage0Idx1Rng1_uid26489_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_52_c_compstr1490_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26489_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26489_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26490_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x(BITJOIN,26489)@116
    assign leftShiftStage0Idx1_uid26490_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26489_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18137_dupName_205_i_unnamed_c_compstr0_shift_x(BITSELECT,18136)@115
    assign rightShiftStage2Idx1Rng8_uid18137_dupName_205_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18136_dupName_205_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18139_dupName_205_i_unnamed_c_compstr0_shift_x(BITJOIN,18138)@115
    assign rightShiftStage2Idx1_uid18139_dupName_205_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18137_dupName_205_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18132_dupName_205_i_unnamed_c_compstr0_shift_x(BITSELECT,18131)@115
    assign rightShiftStage1Idx1Rng4_uid18132_dupName_205_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18131_dupName_205_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18134_dupName_205_i_unnamed_c_compstr0_shift_x(BITJOIN,18133)@115
    assign rightShiftStage1Idx1_uid18134_dupName_205_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18132_dupName_205_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18127_dupName_205_i_unnamed_c_compstr0_shift_x(BITSELECT,18126)@115
    assign rightShiftStage0Idx1Rng1_uid18127_dupName_205_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_q[33:1];

    // rightShiftStage0Idx1_uid18129_dupName_205_i_unnamed_c_compstr0_shift_x(BITJOIN,18128)@115
    assign rightShiftStage0Idx1_uid18129_dupName_205_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18127_dupName_205_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26481_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x(BITSELECT,26480)@114
    assign leftShiftStage2Idx1Rng8_uid26481_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_in = leftShiftStage1_uid26479_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26481_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26481_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26482_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x(BITJOIN,26481)@114
    assign leftShiftStage2Idx1_uid26482_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26481_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26476_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x(BITSELECT,26475)@114
    assign leftShiftStage1Idx1Rng4_uid26476_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_in = leftShiftStage0_uid26474_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26476_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26476_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26477_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x(BITJOIN,26476)@114
    assign leftShiftStage1Idx1_uid26477_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26476_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26471_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x(BITSELECT,26470)@114
    assign leftShiftStage0Idx1Rng1_uid26471_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_51_c_compstr1462_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26471_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26471_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26472_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x(BITJOIN,26471)@114
    assign leftShiftStage0Idx1_uid26472_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26471_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18075_dupName_201_i_unnamed_c_compstr0_shift_x(BITSELECT,18074)@113
    assign rightShiftStage2Idx1Rng8_uid18075_dupName_201_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18074_dupName_201_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18077_dupName_201_i_unnamed_c_compstr0_shift_x(BITJOIN,18076)@113
    assign rightShiftStage2Idx1_uid18077_dupName_201_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18075_dupName_201_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18070_dupName_201_i_unnamed_c_compstr0_shift_x(BITSELECT,18069)@113
    assign rightShiftStage1Idx1Rng4_uid18070_dupName_201_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18069_dupName_201_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18072_dupName_201_i_unnamed_c_compstr0_shift_x(BITJOIN,18071)@113
    assign rightShiftStage1Idx1_uid18072_dupName_201_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18070_dupName_201_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18065_dupName_201_i_unnamed_c_compstr0_shift_x(BITSELECT,18064)@113
    assign rightShiftStage0Idx1Rng1_uid18065_dupName_201_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_q[33:1];

    // rightShiftStage0Idx1_uid18067_dupName_201_i_unnamed_c_compstr0_shift_x(BITJOIN,18066)@113
    assign rightShiftStage0Idx1_uid18067_dupName_201_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18065_dupName_201_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26463_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x(BITSELECT,26462)@112
    assign leftShiftStage2Idx1Rng8_uid26463_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_in = leftShiftStage1_uid26461_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26463_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26463_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26464_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x(BITJOIN,26463)@112
    assign leftShiftStage2Idx1_uid26464_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26463_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26458_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x(BITSELECT,26457)@112
    assign leftShiftStage1Idx1Rng4_uid26458_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_in = leftShiftStage0_uid26456_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26458_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26458_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26459_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x(BITJOIN,26458)@112
    assign leftShiftStage1Idx1_uid26459_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26458_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26453_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x(BITSELECT,26452)@112
    assign leftShiftStage0Idx1Rng1_uid26453_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_50_c_compstr1434_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26453_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26453_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26454_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x(BITJOIN,26453)@112
    assign leftShiftStage0Idx1_uid26454_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26453_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18013_dupName_197_i_unnamed_c_compstr0_shift_x(BITSELECT,18012)@111
    assign rightShiftStage2Idx1Rng8_uid18013_dupName_197_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18012_dupName_197_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18015_dupName_197_i_unnamed_c_compstr0_shift_x(BITJOIN,18014)@111
    assign rightShiftStage2Idx1_uid18015_dupName_197_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18013_dupName_197_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18008_dupName_197_i_unnamed_c_compstr0_shift_x(BITSELECT,18007)@111
    assign rightShiftStage1Idx1Rng4_uid18008_dupName_197_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18007_dupName_197_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18010_dupName_197_i_unnamed_c_compstr0_shift_x(BITJOIN,18009)@111
    assign rightShiftStage1Idx1_uid18010_dupName_197_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18008_dupName_197_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18003_dupName_197_i_unnamed_c_compstr0_shift_x(BITSELECT,18002)@111
    assign rightShiftStage0Idx1Rng1_uid18003_dupName_197_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_q[33:1];

    // rightShiftStage0Idx1_uid18005_dupName_197_i_unnamed_c_compstr0_shift_x(BITJOIN,18004)@111
    assign rightShiftStage0Idx1_uid18005_dupName_197_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18003_dupName_197_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26427_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x(BITSELECT,26426)@110
    assign leftShiftStage2Idx1Rng8_uid26427_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_in = leftShiftStage1_uid26425_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26427_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26427_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26428_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x(BITJOIN,26427)@110
    assign leftShiftStage2Idx1_uid26428_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26427_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26422_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x(BITSELECT,26421)@110
    assign leftShiftStage1Idx1Rng4_uid26422_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_in = leftShiftStage0_uid26420_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26422_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26422_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26423_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x(BITJOIN,26422)@110
    assign leftShiftStage1Idx1_uid26423_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26422_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26417_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x(BITSELECT,26416)@110
    assign leftShiftStage0Idx1Rng1_uid26417_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_49_c_compstr1406_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26417_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26417_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26418_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x(BITJOIN,26417)@110
    assign leftShiftStage0Idx1_uid26418_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26417_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17951_dupName_193_i_unnamed_c_compstr0_shift_x(BITSELECT,17950)@109
    assign rightShiftStage2Idx1Rng8_uid17951_dupName_193_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17950_dupName_193_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17953_dupName_193_i_unnamed_c_compstr0_shift_x(BITJOIN,17952)@109
    assign rightShiftStage2Idx1_uid17953_dupName_193_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17951_dupName_193_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17946_dupName_193_i_unnamed_c_compstr0_shift_x(BITSELECT,17945)@109
    assign rightShiftStage1Idx1Rng4_uid17946_dupName_193_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17945_dupName_193_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17948_dupName_193_i_unnamed_c_compstr0_shift_x(BITJOIN,17947)@109
    assign rightShiftStage1Idx1_uid17948_dupName_193_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17946_dupName_193_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17941_dupName_193_i_unnamed_c_compstr0_shift_x(BITSELECT,17940)@109
    assign rightShiftStage0Idx1Rng1_uid17941_dupName_193_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_q[33:1];

    // rightShiftStage0Idx1_uid17943_dupName_193_i_unnamed_c_compstr0_shift_x(BITJOIN,17942)@109
    assign rightShiftStage0Idx1_uid17943_dupName_193_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17941_dupName_193_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26409_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x(BITSELECT,26408)@108
    assign leftShiftStage2Idx1Rng8_uid26409_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_in = leftShiftStage1_uid26407_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26409_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26409_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26410_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x(BITJOIN,26409)@108
    assign leftShiftStage2Idx1_uid26410_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26409_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26404_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x(BITSELECT,26403)@108
    assign leftShiftStage1Idx1Rng4_uid26404_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_in = leftShiftStage0_uid26402_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26404_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26404_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26405_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x(BITJOIN,26404)@108
    assign leftShiftStage1Idx1_uid26405_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26404_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26399_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x(BITSELECT,26398)@108
    assign leftShiftStage0Idx1Rng1_uid26399_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_48_c_compstr1378_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26399_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26399_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26400_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x(BITJOIN,26399)@108
    assign leftShiftStage0Idx1_uid26400_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26399_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17889_dupName_189_i_unnamed_c_compstr0_shift_x(BITSELECT,17888)@107
    assign rightShiftStage2Idx1Rng8_uid17889_dupName_189_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17888_dupName_189_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17891_dupName_189_i_unnamed_c_compstr0_shift_x(BITJOIN,17890)@107
    assign rightShiftStage2Idx1_uid17891_dupName_189_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17889_dupName_189_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17884_dupName_189_i_unnamed_c_compstr0_shift_x(BITSELECT,17883)@107
    assign rightShiftStage1Idx1Rng4_uid17884_dupName_189_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17883_dupName_189_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17886_dupName_189_i_unnamed_c_compstr0_shift_x(BITJOIN,17885)@107
    assign rightShiftStage1Idx1_uid17886_dupName_189_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17884_dupName_189_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17879_dupName_189_i_unnamed_c_compstr0_shift_x(BITSELECT,17878)@107
    assign rightShiftStage0Idx1Rng1_uid17879_dupName_189_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_q[33:1];

    // rightShiftStage0Idx1_uid17881_dupName_189_i_unnamed_c_compstr0_shift_x(BITJOIN,17880)@107
    assign rightShiftStage0Idx1_uid17881_dupName_189_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17879_dupName_189_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26391_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x(BITSELECT,26390)@106
    assign leftShiftStage2Idx1Rng8_uid26391_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_in = leftShiftStage1_uid26389_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26391_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26391_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26392_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x(BITJOIN,26391)@106
    assign leftShiftStage2Idx1_uid26392_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26391_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26386_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x(BITSELECT,26385)@106
    assign leftShiftStage1Idx1Rng4_uid26386_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_in = leftShiftStage0_uid26384_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26386_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26386_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26387_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x(BITJOIN,26386)@106
    assign leftShiftStage1Idx1_uid26387_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26386_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26381_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x(BITSELECT,26380)@106
    assign leftShiftStage0Idx1Rng1_uid26381_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_47_c_compstr1350_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26381_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26381_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26382_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x(BITJOIN,26381)@106
    assign leftShiftStage0Idx1_uid26382_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26381_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17827_dupName_185_i_unnamed_c_compstr0_shift_x(BITSELECT,17826)@105
    assign rightShiftStage2Idx1Rng8_uid17827_dupName_185_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17826_dupName_185_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17829_dupName_185_i_unnamed_c_compstr0_shift_x(BITJOIN,17828)@105
    assign rightShiftStage2Idx1_uid17829_dupName_185_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17827_dupName_185_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17822_dupName_185_i_unnamed_c_compstr0_shift_x(BITSELECT,17821)@105
    assign rightShiftStage1Idx1Rng4_uid17822_dupName_185_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17821_dupName_185_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17824_dupName_185_i_unnamed_c_compstr0_shift_x(BITJOIN,17823)@105
    assign rightShiftStage1Idx1_uid17824_dupName_185_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17822_dupName_185_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17817_dupName_185_i_unnamed_c_compstr0_shift_x(BITSELECT,17816)@105
    assign rightShiftStage0Idx1Rng1_uid17817_dupName_185_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_q[33:1];

    // rightShiftStage0Idx1_uid17819_dupName_185_i_unnamed_c_compstr0_shift_x(BITJOIN,17818)@105
    assign rightShiftStage0Idx1_uid17819_dupName_185_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17817_dupName_185_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26373_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x(BITSELECT,26372)@104
    assign leftShiftStage2Idx1Rng8_uid26373_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_in = leftShiftStage1_uid26371_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26373_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26373_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26374_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x(BITJOIN,26373)@104
    assign leftShiftStage2Idx1_uid26374_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26373_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26368_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x(BITSELECT,26367)@104
    assign leftShiftStage1Idx1Rng4_uid26368_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_in = leftShiftStage0_uid26366_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26368_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26368_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26369_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x(BITJOIN,26368)@104
    assign leftShiftStage1Idx1_uid26369_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26368_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26363_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x(BITSELECT,26362)@104
    assign leftShiftStage0Idx1Rng1_uid26363_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_46_c_compstr1322_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26363_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26363_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26364_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x(BITJOIN,26363)@104
    assign leftShiftStage0Idx1_uid26364_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26363_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17765_dupName_181_i_unnamed_c_compstr0_shift_x(BITSELECT,17764)@103
    assign rightShiftStage2Idx1Rng8_uid17765_dupName_181_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17764_dupName_181_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17767_dupName_181_i_unnamed_c_compstr0_shift_x(BITJOIN,17766)@103
    assign rightShiftStage2Idx1_uid17767_dupName_181_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17765_dupName_181_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17760_dupName_181_i_unnamed_c_compstr0_shift_x(BITSELECT,17759)@103
    assign rightShiftStage1Idx1Rng4_uid17760_dupName_181_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17759_dupName_181_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17762_dupName_181_i_unnamed_c_compstr0_shift_x(BITJOIN,17761)@103
    assign rightShiftStage1Idx1_uid17762_dupName_181_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17760_dupName_181_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17755_dupName_181_i_unnamed_c_compstr0_shift_x(BITSELECT,17754)@103
    assign rightShiftStage0Idx1Rng1_uid17755_dupName_181_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_q[33:1];

    // rightShiftStage0Idx1_uid17757_dupName_181_i_unnamed_c_compstr0_shift_x(BITJOIN,17756)@103
    assign rightShiftStage0Idx1_uid17757_dupName_181_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17755_dupName_181_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26355_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x(BITSELECT,26354)@102
    assign leftShiftStage2Idx1Rng8_uid26355_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_in = leftShiftStage1_uid26353_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26355_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26355_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26356_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x(BITJOIN,26355)@102
    assign leftShiftStage2Idx1_uid26356_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26355_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26350_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x(BITSELECT,26349)@102
    assign leftShiftStage1Idx1Rng4_uid26350_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_in = leftShiftStage0_uid26348_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26350_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26350_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26351_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x(BITJOIN,26350)@102
    assign leftShiftStage1Idx1_uid26351_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26350_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26345_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x(BITSELECT,26344)@102
    assign leftShiftStage0Idx1Rng1_uid26345_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_45_c_compstr1294_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26345_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26345_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26346_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x(BITJOIN,26345)@102
    assign leftShiftStage0Idx1_uid26346_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26345_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17703_dupName_177_i_unnamed_c_compstr0_shift_x(BITSELECT,17702)@101
    assign rightShiftStage2Idx1Rng8_uid17703_dupName_177_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17702_dupName_177_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17705_dupName_177_i_unnamed_c_compstr0_shift_x(BITJOIN,17704)@101
    assign rightShiftStage2Idx1_uid17705_dupName_177_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17703_dupName_177_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17698_dupName_177_i_unnamed_c_compstr0_shift_x(BITSELECT,17697)@101
    assign rightShiftStage1Idx1Rng4_uid17698_dupName_177_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17697_dupName_177_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17700_dupName_177_i_unnamed_c_compstr0_shift_x(BITJOIN,17699)@101
    assign rightShiftStage1Idx1_uid17700_dupName_177_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17698_dupName_177_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17693_dupName_177_i_unnamed_c_compstr0_shift_x(BITSELECT,17692)@101
    assign rightShiftStage0Idx1Rng1_uid17693_dupName_177_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_q[33:1];

    // rightShiftStage0Idx1_uid17695_dupName_177_i_unnamed_c_compstr0_shift_x(BITJOIN,17694)@101
    assign rightShiftStage0Idx1_uid17695_dupName_177_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17693_dupName_177_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26337_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x(BITSELECT,26336)@100
    assign leftShiftStage2Idx1Rng8_uid26337_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_in = leftShiftStage1_uid26335_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26337_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26337_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26338_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x(BITJOIN,26337)@100
    assign leftShiftStage2Idx1_uid26338_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26337_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26332_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x(BITSELECT,26331)@100
    assign leftShiftStage1Idx1Rng4_uid26332_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_in = leftShiftStage0_uid26330_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26332_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26332_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26333_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x(BITJOIN,26332)@100
    assign leftShiftStage1Idx1_uid26333_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26332_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26327_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x(BITSELECT,26326)@100
    assign leftShiftStage0Idx1Rng1_uid26327_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_44_c_compstr1266_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26327_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26327_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26328_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x(BITJOIN,26327)@100
    assign leftShiftStage0Idx1_uid26328_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26327_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17641_dupName_173_i_unnamed_c_compstr0_shift_x(BITSELECT,17640)@99
    assign rightShiftStage2Idx1Rng8_uid17641_dupName_173_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17640_dupName_173_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17643_dupName_173_i_unnamed_c_compstr0_shift_x(BITJOIN,17642)@99
    assign rightShiftStage2Idx1_uid17643_dupName_173_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17641_dupName_173_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17636_dupName_173_i_unnamed_c_compstr0_shift_x(BITSELECT,17635)@99
    assign rightShiftStage1Idx1Rng4_uid17636_dupName_173_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17635_dupName_173_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17638_dupName_173_i_unnamed_c_compstr0_shift_x(BITJOIN,17637)@99
    assign rightShiftStage1Idx1_uid17638_dupName_173_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17636_dupName_173_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17631_dupName_173_i_unnamed_c_compstr0_shift_x(BITSELECT,17630)@99
    assign rightShiftStage0Idx1Rng1_uid17631_dupName_173_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_q[33:1];

    // rightShiftStage0Idx1_uid17633_dupName_173_i_unnamed_c_compstr0_shift_x(BITJOIN,17632)@99
    assign rightShiftStage0Idx1_uid17633_dupName_173_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17631_dupName_173_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26319_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x(BITSELECT,26318)@98
    assign leftShiftStage2Idx1Rng8_uid26319_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_in = leftShiftStage1_uid26317_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26319_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26319_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26320_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x(BITJOIN,26319)@98
    assign leftShiftStage2Idx1_uid26320_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26319_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26314_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x(BITSELECT,26313)@98
    assign leftShiftStage1Idx1Rng4_uid26314_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_in = leftShiftStage0_uid26312_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26314_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26314_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26315_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x(BITJOIN,26314)@98
    assign leftShiftStage1Idx1_uid26315_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26314_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26309_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x(BITSELECT,26308)@98
    assign leftShiftStage0Idx1Rng1_uid26309_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_43_c_compstr1238_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26309_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26309_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26310_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x(BITJOIN,26309)@98
    assign leftShiftStage0Idx1_uid26310_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26309_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17579_dupName_169_i_unnamed_c_compstr0_shift_x(BITSELECT,17578)@97
    assign rightShiftStage2Idx1Rng8_uid17579_dupName_169_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17578_dupName_169_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17581_dupName_169_i_unnamed_c_compstr0_shift_x(BITJOIN,17580)@97
    assign rightShiftStage2Idx1_uid17581_dupName_169_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17579_dupName_169_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17574_dupName_169_i_unnamed_c_compstr0_shift_x(BITSELECT,17573)@97
    assign rightShiftStage1Idx1Rng4_uid17574_dupName_169_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17573_dupName_169_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17576_dupName_169_i_unnamed_c_compstr0_shift_x(BITJOIN,17575)@97
    assign rightShiftStage1Idx1_uid17576_dupName_169_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17574_dupName_169_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17569_dupName_169_i_unnamed_c_compstr0_shift_x(BITSELECT,17568)@97
    assign rightShiftStage0Idx1Rng1_uid17569_dupName_169_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_q[33:1];

    // rightShiftStage0Idx1_uid17571_dupName_169_i_unnamed_c_compstr0_shift_x(BITJOIN,17570)@97
    assign rightShiftStage0Idx1_uid17571_dupName_169_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17569_dupName_169_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26301_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x(BITSELECT,26300)@96
    assign leftShiftStage2Idx1Rng8_uid26301_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_in = leftShiftStage1_uid26299_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26301_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26301_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26302_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x(BITJOIN,26301)@96
    assign leftShiftStage2Idx1_uid26302_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26301_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26296_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x(BITSELECT,26295)@96
    assign leftShiftStage1Idx1Rng4_uid26296_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_in = leftShiftStage0_uid26294_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26296_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26296_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26297_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x(BITJOIN,26296)@96
    assign leftShiftStage1Idx1_uid26297_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26296_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26291_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x(BITSELECT,26290)@96
    assign leftShiftStage0Idx1Rng1_uid26291_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_42_c_compstr1210_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26291_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26291_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26292_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x(BITJOIN,26291)@96
    assign leftShiftStage0Idx1_uid26292_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26291_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17517_dupName_165_i_unnamed_c_compstr0_shift_x(BITSELECT,17516)@95
    assign rightShiftStage2Idx1Rng8_uid17517_dupName_165_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17516_dupName_165_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17519_dupName_165_i_unnamed_c_compstr0_shift_x(BITJOIN,17518)@95
    assign rightShiftStage2Idx1_uid17519_dupName_165_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17517_dupName_165_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17512_dupName_165_i_unnamed_c_compstr0_shift_x(BITSELECT,17511)@95
    assign rightShiftStage1Idx1Rng4_uid17512_dupName_165_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17511_dupName_165_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17514_dupName_165_i_unnamed_c_compstr0_shift_x(BITJOIN,17513)@95
    assign rightShiftStage1Idx1_uid17514_dupName_165_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17512_dupName_165_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17507_dupName_165_i_unnamed_c_compstr0_shift_x(BITSELECT,17506)@95
    assign rightShiftStage0Idx1Rng1_uid17507_dupName_165_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_q[33:1];

    // rightShiftStage0Idx1_uid17509_dupName_165_i_unnamed_c_compstr0_shift_x(BITJOIN,17508)@95
    assign rightShiftStage0Idx1_uid17509_dupName_165_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17507_dupName_165_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26283_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x(BITSELECT,26282)@94
    assign leftShiftStage2Idx1Rng8_uid26283_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_in = leftShiftStage1_uid26281_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26283_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26283_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26284_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x(BITJOIN,26283)@94
    assign leftShiftStage2Idx1_uid26284_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26283_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26278_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x(BITSELECT,26277)@94
    assign leftShiftStage1Idx1Rng4_uid26278_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_in = leftShiftStage0_uid26276_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26278_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26278_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26279_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x(BITJOIN,26278)@94
    assign leftShiftStage1Idx1_uid26279_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26278_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26273_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x(BITSELECT,26272)@94
    assign leftShiftStage0Idx1Rng1_uid26273_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_41_c_compstr1182_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26273_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26273_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26274_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x(BITJOIN,26273)@94
    assign leftShiftStage0Idx1_uid26274_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26273_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17455_dupName_161_i_unnamed_c_compstr0_shift_x(BITSELECT,17454)@93
    assign rightShiftStage2Idx1Rng8_uid17455_dupName_161_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17454_dupName_161_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17457_dupName_161_i_unnamed_c_compstr0_shift_x(BITJOIN,17456)@93
    assign rightShiftStage2Idx1_uid17457_dupName_161_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17455_dupName_161_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17450_dupName_161_i_unnamed_c_compstr0_shift_x(BITSELECT,17449)@93
    assign rightShiftStage1Idx1Rng4_uid17450_dupName_161_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17449_dupName_161_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17452_dupName_161_i_unnamed_c_compstr0_shift_x(BITJOIN,17451)@93
    assign rightShiftStage1Idx1_uid17452_dupName_161_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17450_dupName_161_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17445_dupName_161_i_unnamed_c_compstr0_shift_x(BITSELECT,17444)@93
    assign rightShiftStage0Idx1Rng1_uid17445_dupName_161_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_q[33:1];

    // rightShiftStage0Idx1_uid17447_dupName_161_i_unnamed_c_compstr0_shift_x(BITJOIN,17446)@93
    assign rightShiftStage0Idx1_uid17447_dupName_161_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17445_dupName_161_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26265_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x(BITSELECT,26264)@92
    assign leftShiftStage2Idx1Rng8_uid26265_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_in = leftShiftStage1_uid26263_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26265_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26265_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26266_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x(BITJOIN,26265)@92
    assign leftShiftStage2Idx1_uid26266_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26265_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26260_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x(BITSELECT,26259)@92
    assign leftShiftStage1Idx1Rng4_uid26260_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_in = leftShiftStage0_uid26258_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26260_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26260_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26261_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x(BITJOIN,26260)@92
    assign leftShiftStage1Idx1_uid26261_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26260_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26255_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x(BITSELECT,26254)@92
    assign leftShiftStage0Idx1Rng1_uid26255_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_40_c_compstr1154_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26255_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26255_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26256_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x(BITJOIN,26255)@92
    assign leftShiftStage0Idx1_uid26256_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26255_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17393_dupName_157_i_unnamed_c_compstr0_shift_x(BITSELECT,17392)@91
    assign rightShiftStage2Idx1Rng8_uid17393_dupName_157_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17392_dupName_157_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17395_dupName_157_i_unnamed_c_compstr0_shift_x(BITJOIN,17394)@91
    assign rightShiftStage2Idx1_uid17395_dupName_157_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17393_dupName_157_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17388_dupName_157_i_unnamed_c_compstr0_shift_x(BITSELECT,17387)@91
    assign rightShiftStage1Idx1Rng4_uid17388_dupName_157_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17387_dupName_157_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17390_dupName_157_i_unnamed_c_compstr0_shift_x(BITJOIN,17389)@91
    assign rightShiftStage1Idx1_uid17390_dupName_157_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17388_dupName_157_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17383_dupName_157_i_unnamed_c_compstr0_shift_x(BITSELECT,17382)@91
    assign rightShiftStage0Idx1Rng1_uid17383_dupName_157_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_q[33:1];

    // rightShiftStage0Idx1_uid17385_dupName_157_i_unnamed_c_compstr0_shift_x(BITJOIN,17384)@91
    assign rightShiftStage0Idx1_uid17385_dupName_157_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17383_dupName_157_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26229_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x(BITSELECT,26228)@90
    assign leftShiftStage2Idx1Rng8_uid26229_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_in = leftShiftStage1_uid26227_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26229_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26229_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26230_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x(BITJOIN,26229)@90
    assign leftShiftStage2Idx1_uid26230_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26229_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26224_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x(BITSELECT,26223)@90
    assign leftShiftStage1Idx1Rng4_uid26224_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_in = leftShiftStage0_uid26222_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26224_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26224_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26225_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x(BITJOIN,26224)@90
    assign leftShiftStage1Idx1_uid26225_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26224_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26219_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x(BITSELECT,26218)@90
    assign leftShiftStage0Idx1Rng1_uid26219_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_39_c_compstr1126_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26219_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26219_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26220_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x(BITJOIN,26219)@90
    assign leftShiftStage0Idx1_uid26220_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26219_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17331_dupName_153_i_unnamed_c_compstr0_shift_x(BITSELECT,17330)@89
    assign rightShiftStage2Idx1Rng8_uid17331_dupName_153_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17330_dupName_153_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17333_dupName_153_i_unnamed_c_compstr0_shift_x(BITJOIN,17332)@89
    assign rightShiftStage2Idx1_uid17333_dupName_153_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17331_dupName_153_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17326_dupName_153_i_unnamed_c_compstr0_shift_x(BITSELECT,17325)@89
    assign rightShiftStage1Idx1Rng4_uid17326_dupName_153_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17325_dupName_153_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17328_dupName_153_i_unnamed_c_compstr0_shift_x(BITJOIN,17327)@89
    assign rightShiftStage1Idx1_uid17328_dupName_153_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17326_dupName_153_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17321_dupName_153_i_unnamed_c_compstr0_shift_x(BITSELECT,17320)@89
    assign rightShiftStage0Idx1Rng1_uid17321_dupName_153_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_q[33:1];

    // rightShiftStage0Idx1_uid17323_dupName_153_i_unnamed_c_compstr0_shift_x(BITJOIN,17322)@89
    assign rightShiftStage0Idx1_uid17323_dupName_153_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17321_dupName_153_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26211_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x(BITSELECT,26210)@88
    assign leftShiftStage2Idx1Rng8_uid26211_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_in = leftShiftStage1_uid26209_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26211_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26211_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26212_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x(BITJOIN,26211)@88
    assign leftShiftStage2Idx1_uid26212_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26211_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26206_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x(BITSELECT,26205)@88
    assign leftShiftStage1Idx1Rng4_uid26206_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_in = leftShiftStage0_uid26204_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26206_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26206_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26207_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x(BITJOIN,26206)@88
    assign leftShiftStage1Idx1_uid26207_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26206_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26201_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x(BITSELECT,26200)@88
    assign leftShiftStage0Idx1Rng1_uid26201_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_38_c_compstr1098_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26201_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26201_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26202_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x(BITJOIN,26201)@88
    assign leftShiftStage0Idx1_uid26202_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26201_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17269_dupName_149_i_unnamed_c_compstr0_shift_x(BITSELECT,17268)@87
    assign rightShiftStage2Idx1Rng8_uid17269_dupName_149_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17268_dupName_149_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17271_dupName_149_i_unnamed_c_compstr0_shift_x(BITJOIN,17270)@87
    assign rightShiftStage2Idx1_uid17271_dupName_149_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17269_dupName_149_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17264_dupName_149_i_unnamed_c_compstr0_shift_x(BITSELECT,17263)@87
    assign rightShiftStage1Idx1Rng4_uid17264_dupName_149_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17263_dupName_149_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17266_dupName_149_i_unnamed_c_compstr0_shift_x(BITJOIN,17265)@87
    assign rightShiftStage1Idx1_uid17266_dupName_149_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17264_dupName_149_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17259_dupName_149_i_unnamed_c_compstr0_shift_x(BITSELECT,17258)@87
    assign rightShiftStage0Idx1Rng1_uid17259_dupName_149_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_q[33:1];

    // rightShiftStage0Idx1_uid17261_dupName_149_i_unnamed_c_compstr0_shift_x(BITJOIN,17260)@87
    assign rightShiftStage0Idx1_uid17261_dupName_149_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17259_dupName_149_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26193_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x(BITSELECT,26192)@86
    assign leftShiftStage2Idx1Rng8_uid26193_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_in = leftShiftStage1_uid26191_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26193_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26193_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26194_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x(BITJOIN,26193)@86
    assign leftShiftStage2Idx1_uid26194_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26193_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26188_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x(BITSELECT,26187)@86
    assign leftShiftStage1Idx1Rng4_uid26188_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_in = leftShiftStage0_uid26186_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26188_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26188_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26189_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x(BITJOIN,26188)@86
    assign leftShiftStage1Idx1_uid26189_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26188_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26183_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x(BITSELECT,26182)@86
    assign leftShiftStage0Idx1Rng1_uid26183_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_37_c_compstr1070_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26183_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26183_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26184_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x(BITJOIN,26183)@86
    assign leftShiftStage0Idx1_uid26184_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26183_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17207_dupName_145_i_unnamed_c_compstr0_shift_x(BITSELECT,17206)@85
    assign rightShiftStage2Idx1Rng8_uid17207_dupName_145_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17206_dupName_145_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17209_dupName_145_i_unnamed_c_compstr0_shift_x(BITJOIN,17208)@85
    assign rightShiftStage2Idx1_uid17209_dupName_145_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17207_dupName_145_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17202_dupName_145_i_unnamed_c_compstr0_shift_x(BITSELECT,17201)@85
    assign rightShiftStage1Idx1Rng4_uid17202_dupName_145_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17201_dupName_145_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17204_dupName_145_i_unnamed_c_compstr0_shift_x(BITJOIN,17203)@85
    assign rightShiftStage1Idx1_uid17204_dupName_145_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17202_dupName_145_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17197_dupName_145_i_unnamed_c_compstr0_shift_x(BITSELECT,17196)@85
    assign rightShiftStage0Idx1Rng1_uid17197_dupName_145_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_q[33:1];

    // rightShiftStage0Idx1_uid17199_dupName_145_i_unnamed_c_compstr0_shift_x(BITJOIN,17198)@85
    assign rightShiftStage0Idx1_uid17199_dupName_145_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17197_dupName_145_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26175_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x(BITSELECT,26174)@84
    assign leftShiftStage2Idx1Rng8_uid26175_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_in = leftShiftStage1_uid26173_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26175_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26175_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26176_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x(BITJOIN,26175)@84
    assign leftShiftStage2Idx1_uid26176_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26175_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26170_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x(BITSELECT,26169)@84
    assign leftShiftStage1Idx1Rng4_uid26170_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_in = leftShiftStage0_uid26168_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26170_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26170_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26171_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x(BITJOIN,26170)@84
    assign leftShiftStage1Idx1_uid26171_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26170_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26165_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x(BITSELECT,26164)@84
    assign leftShiftStage0Idx1Rng1_uid26165_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_36_c_compstr1042_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26165_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26165_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26166_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x(BITJOIN,26165)@84
    assign leftShiftStage0Idx1_uid26166_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26165_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17145_dupName_141_i_unnamed_c_compstr0_shift_x(BITSELECT,17144)@83
    assign rightShiftStage2Idx1Rng8_uid17145_dupName_141_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17144_dupName_141_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17147_dupName_141_i_unnamed_c_compstr0_shift_x(BITJOIN,17146)@83
    assign rightShiftStage2Idx1_uid17147_dupName_141_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17145_dupName_141_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17140_dupName_141_i_unnamed_c_compstr0_shift_x(BITSELECT,17139)@83
    assign rightShiftStage1Idx1Rng4_uid17140_dupName_141_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17139_dupName_141_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17142_dupName_141_i_unnamed_c_compstr0_shift_x(BITJOIN,17141)@83
    assign rightShiftStage1Idx1_uid17142_dupName_141_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17140_dupName_141_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17135_dupName_141_i_unnamed_c_compstr0_shift_x(BITSELECT,17134)@83
    assign rightShiftStage0Idx1Rng1_uid17135_dupName_141_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_q[33:1];

    // rightShiftStage0Idx1_uid17137_dupName_141_i_unnamed_c_compstr0_shift_x(BITJOIN,17136)@83
    assign rightShiftStage0Idx1_uid17137_dupName_141_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17135_dupName_141_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26157_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x(BITSELECT,26156)@82
    assign leftShiftStage2Idx1Rng8_uid26157_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_in = leftShiftStage1_uid26155_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26157_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26157_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26158_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x(BITJOIN,26157)@82
    assign leftShiftStage2Idx1_uid26158_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26157_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26152_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x(BITSELECT,26151)@82
    assign leftShiftStage1Idx1Rng4_uid26152_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_in = leftShiftStage0_uid26150_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26152_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26152_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26153_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x(BITJOIN,26152)@82
    assign leftShiftStage1Idx1_uid26153_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26152_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26147_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x(BITSELECT,26146)@82
    assign leftShiftStage0Idx1Rng1_uid26147_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_35_c_compstr1014_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26147_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26147_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26148_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x(BITJOIN,26147)@82
    assign leftShiftStage0Idx1_uid26148_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26147_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17083_dupName_137_i_unnamed_c_compstr0_shift_x(BITSELECT,17082)@81
    assign rightShiftStage2Idx1Rng8_uid17083_dupName_137_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17082_dupName_137_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17085_dupName_137_i_unnamed_c_compstr0_shift_x(BITJOIN,17084)@81
    assign rightShiftStage2Idx1_uid17085_dupName_137_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17083_dupName_137_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17078_dupName_137_i_unnamed_c_compstr0_shift_x(BITSELECT,17077)@81
    assign rightShiftStage1Idx1Rng4_uid17078_dupName_137_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17077_dupName_137_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17080_dupName_137_i_unnamed_c_compstr0_shift_x(BITJOIN,17079)@81
    assign rightShiftStage1Idx1_uid17080_dupName_137_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17078_dupName_137_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17073_dupName_137_i_unnamed_c_compstr0_shift_x(BITSELECT,17072)@81
    assign rightShiftStage0Idx1Rng1_uid17073_dupName_137_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_q[33:1];

    // rightShiftStage0Idx1_uid17075_dupName_137_i_unnamed_c_compstr0_shift_x(BITJOIN,17074)@81
    assign rightShiftStage0Idx1_uid17075_dupName_137_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17073_dupName_137_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26139_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x(BITSELECT,26138)@80
    assign leftShiftStage2Idx1Rng8_uid26139_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_in = leftShiftStage1_uid26137_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26139_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26139_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26140_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x(BITJOIN,26139)@80
    assign leftShiftStage2Idx1_uid26140_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26139_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26134_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x(BITSELECT,26133)@80
    assign leftShiftStage1Idx1Rng4_uid26134_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_in = leftShiftStage0_uid26132_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26134_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26134_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26135_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x(BITJOIN,26134)@80
    assign leftShiftStage1Idx1_uid26135_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26134_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26129_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x(BITSELECT,26128)@80
    assign leftShiftStage0Idx1Rng1_uid26129_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_34_c_compstr986_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26129_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26129_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26130_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x(BITJOIN,26129)@80
    assign leftShiftStage0Idx1_uid26130_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26129_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17021_dupName_133_i_unnamed_c_compstr0_shift_x(BITSELECT,17020)@79
    assign rightShiftStage2Idx1Rng8_uid17021_dupName_133_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17020_dupName_133_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17023_dupName_133_i_unnamed_c_compstr0_shift_x(BITJOIN,17022)@79
    assign rightShiftStage2Idx1_uid17023_dupName_133_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17021_dupName_133_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17016_dupName_133_i_unnamed_c_compstr0_shift_x(BITSELECT,17015)@79
    assign rightShiftStage1Idx1Rng4_uid17016_dupName_133_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17015_dupName_133_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17018_dupName_133_i_unnamed_c_compstr0_shift_x(BITJOIN,17017)@79
    assign rightShiftStage1Idx1_uid17018_dupName_133_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17016_dupName_133_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17011_dupName_133_i_unnamed_c_compstr0_shift_x(BITSELECT,17010)@79
    assign rightShiftStage0Idx1Rng1_uid17011_dupName_133_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_q[33:1];

    // rightShiftStage0Idx1_uid17013_dupName_133_i_unnamed_c_compstr0_shift_x(BITJOIN,17012)@79
    assign rightShiftStage0Idx1_uid17013_dupName_133_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17011_dupName_133_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26121_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x(BITSELECT,26120)@78
    assign leftShiftStage2Idx1Rng8_uid26121_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_in = leftShiftStage1_uid26119_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26121_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26121_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26122_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x(BITJOIN,26121)@78
    assign leftShiftStage2Idx1_uid26122_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26121_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26116_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x(BITSELECT,26115)@78
    assign leftShiftStage1Idx1Rng4_uid26116_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_in = leftShiftStage0_uid26114_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26116_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26116_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26117_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x(BITJOIN,26116)@78
    assign leftShiftStage1Idx1_uid26117_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26116_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26111_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x(BITSELECT,26110)@78
    assign leftShiftStage0Idx1Rng1_uid26111_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_33_c_compstr958_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26111_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26111_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26112_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x(BITJOIN,26111)@78
    assign leftShiftStage0Idx1_uid26112_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26111_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16959_dupName_129_i_unnamed_c_compstr0_shift_x(BITSELECT,16958)@77
    assign rightShiftStage2Idx1Rng8_uid16959_dupName_129_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16958_dupName_129_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16961_dupName_129_i_unnamed_c_compstr0_shift_x(BITJOIN,16960)@77
    assign rightShiftStage2Idx1_uid16961_dupName_129_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16959_dupName_129_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16954_dupName_129_i_unnamed_c_compstr0_shift_x(BITSELECT,16953)@77
    assign rightShiftStage1Idx1Rng4_uid16954_dupName_129_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16953_dupName_129_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16956_dupName_129_i_unnamed_c_compstr0_shift_x(BITJOIN,16955)@77
    assign rightShiftStage1Idx1_uid16956_dupName_129_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16954_dupName_129_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16949_dupName_129_i_unnamed_c_compstr0_shift_x(BITSELECT,16948)@77
    assign rightShiftStage0Idx1Rng1_uid16949_dupName_129_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_q[33:1];

    // rightShiftStage0Idx1_uid16951_dupName_129_i_unnamed_c_compstr0_shift_x(BITJOIN,16950)@77
    assign rightShiftStage0Idx1_uid16951_dupName_129_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16949_dupName_129_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26103_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x(BITSELECT,26102)@76
    assign leftShiftStage2Idx1Rng8_uid26103_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_in = leftShiftStage1_uid26101_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26103_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26103_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26104_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x(BITJOIN,26103)@76
    assign leftShiftStage2Idx1_uid26104_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26103_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26098_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x(BITSELECT,26097)@76
    assign leftShiftStage1Idx1Rng4_uid26098_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_in = leftShiftStage0_uid26096_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26098_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26098_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26099_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x(BITJOIN,26098)@76
    assign leftShiftStage1Idx1_uid26099_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26098_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26093_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x(BITSELECT,26092)@76
    assign leftShiftStage0Idx1Rng1_uid26093_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_32_c_compstr930_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26093_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26093_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26094_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x(BITJOIN,26093)@76
    assign leftShiftStage0Idx1_uid26094_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26093_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16897_dupName_125_i_unnamed_c_compstr0_shift_x(BITSELECT,16896)@75
    assign rightShiftStage2Idx1Rng8_uid16897_dupName_125_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16896_dupName_125_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16899_dupName_125_i_unnamed_c_compstr0_shift_x(BITJOIN,16898)@75
    assign rightShiftStage2Idx1_uid16899_dupName_125_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16897_dupName_125_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16892_dupName_125_i_unnamed_c_compstr0_shift_x(BITSELECT,16891)@75
    assign rightShiftStage1Idx1Rng4_uid16892_dupName_125_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16891_dupName_125_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16894_dupName_125_i_unnamed_c_compstr0_shift_x(BITJOIN,16893)@75
    assign rightShiftStage1Idx1_uid16894_dupName_125_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16892_dupName_125_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16887_dupName_125_i_unnamed_c_compstr0_shift_x(BITSELECT,16886)@75
    assign rightShiftStage0Idx1Rng1_uid16887_dupName_125_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_q[33:1];

    // rightShiftStage0Idx1_uid16889_dupName_125_i_unnamed_c_compstr0_shift_x(BITJOIN,16888)@75
    assign rightShiftStage0Idx1_uid16889_dupName_125_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16887_dupName_125_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26085_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x(BITSELECT,26084)@74
    assign leftShiftStage2Idx1Rng8_uid26085_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_in = leftShiftStage1_uid26083_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26085_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26085_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26086_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x(BITJOIN,26085)@74
    assign leftShiftStage2Idx1_uid26086_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26085_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26080_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x(BITSELECT,26079)@74
    assign leftShiftStage1Idx1Rng4_uid26080_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_in = leftShiftStage0_uid26078_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26080_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26080_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26081_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x(BITJOIN,26080)@74
    assign leftShiftStage1Idx1_uid26081_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26080_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26075_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x(BITSELECT,26074)@74
    assign leftShiftStage0Idx1Rng1_uid26075_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_31_c_compstr902_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26075_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26075_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26076_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x(BITJOIN,26075)@74
    assign leftShiftStage0Idx1_uid26076_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26075_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16835_dupName_121_i_unnamed_c_compstr0_shift_x(BITSELECT,16834)@73
    assign rightShiftStage2Idx1Rng8_uid16835_dupName_121_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16834_dupName_121_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16837_dupName_121_i_unnamed_c_compstr0_shift_x(BITJOIN,16836)@73
    assign rightShiftStage2Idx1_uid16837_dupName_121_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16835_dupName_121_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16830_dupName_121_i_unnamed_c_compstr0_shift_x(BITSELECT,16829)@73
    assign rightShiftStage1Idx1Rng4_uid16830_dupName_121_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16829_dupName_121_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16832_dupName_121_i_unnamed_c_compstr0_shift_x(BITJOIN,16831)@73
    assign rightShiftStage1Idx1_uid16832_dupName_121_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16830_dupName_121_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16825_dupName_121_i_unnamed_c_compstr0_shift_x(BITSELECT,16824)@73
    assign rightShiftStage0Idx1Rng1_uid16825_dupName_121_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_q[33:1];

    // rightShiftStage0Idx1_uid16827_dupName_121_i_unnamed_c_compstr0_shift_x(BITJOIN,16826)@73
    assign rightShiftStage0Idx1_uid16827_dupName_121_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16825_dupName_121_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26067_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x(BITSELECT,26066)@72
    assign leftShiftStage2Idx1Rng8_uid26067_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_in = leftShiftStage1_uid26065_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26067_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26067_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26068_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x(BITJOIN,26067)@72
    assign leftShiftStage2Idx1_uid26068_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26067_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26062_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x(BITSELECT,26061)@72
    assign leftShiftStage1Idx1Rng4_uid26062_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_in = leftShiftStage0_uid26060_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26062_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26062_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26063_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x(BITJOIN,26062)@72
    assign leftShiftStage1Idx1_uid26063_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26062_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26057_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x(BITSELECT,26056)@72
    assign leftShiftStage0Idx1Rng1_uid26057_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_30_c_compstr874_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26057_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26057_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26058_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x(BITJOIN,26057)@72
    assign leftShiftStage0Idx1_uid26058_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26057_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16773_dupName_117_i_unnamed_c_compstr0_shift_x(BITSELECT,16772)@71
    assign rightShiftStage2Idx1Rng8_uid16773_dupName_117_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16772_dupName_117_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16775_dupName_117_i_unnamed_c_compstr0_shift_x(BITJOIN,16774)@71
    assign rightShiftStage2Idx1_uid16775_dupName_117_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16773_dupName_117_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16768_dupName_117_i_unnamed_c_compstr0_shift_x(BITSELECT,16767)@71
    assign rightShiftStage1Idx1Rng4_uid16768_dupName_117_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16767_dupName_117_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16770_dupName_117_i_unnamed_c_compstr0_shift_x(BITJOIN,16769)@71
    assign rightShiftStage1Idx1_uid16770_dupName_117_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16768_dupName_117_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16763_dupName_117_i_unnamed_c_compstr0_shift_x(BITSELECT,16762)@71
    assign rightShiftStage0Idx1Rng1_uid16763_dupName_117_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_q[33:1];

    // rightShiftStage0Idx1_uid16765_dupName_117_i_unnamed_c_compstr0_shift_x(BITJOIN,16764)@71
    assign rightShiftStage0Idx1_uid16765_dupName_117_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16763_dupName_117_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26031_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x(BITSELECT,26030)@70
    assign leftShiftStage2Idx1Rng8_uid26031_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_in = leftShiftStage1_uid26029_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26031_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26031_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26032_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x(BITJOIN,26031)@70
    assign leftShiftStage2Idx1_uid26032_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26031_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26026_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x(BITSELECT,26025)@70
    assign leftShiftStage1Idx1Rng4_uid26026_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_in = leftShiftStage0_uid26024_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26026_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26026_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26027_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x(BITJOIN,26026)@70
    assign leftShiftStage1Idx1_uid26027_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26026_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26021_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x(BITSELECT,26020)@70
    assign leftShiftStage0Idx1Rng1_uid26021_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_29_c_compstr846_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26021_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26021_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26022_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x(BITJOIN,26021)@70
    assign leftShiftStage0Idx1_uid26022_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26021_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16711_dupName_113_i_unnamed_c_compstr0_shift_x(BITSELECT,16710)@69
    assign rightShiftStage2Idx1Rng8_uid16711_dupName_113_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16710_dupName_113_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16713_dupName_113_i_unnamed_c_compstr0_shift_x(BITJOIN,16712)@69
    assign rightShiftStage2Idx1_uid16713_dupName_113_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16711_dupName_113_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16706_dupName_113_i_unnamed_c_compstr0_shift_x(BITSELECT,16705)@69
    assign rightShiftStage1Idx1Rng4_uid16706_dupName_113_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16705_dupName_113_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16708_dupName_113_i_unnamed_c_compstr0_shift_x(BITJOIN,16707)@69
    assign rightShiftStage1Idx1_uid16708_dupName_113_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16706_dupName_113_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16701_dupName_113_i_unnamed_c_compstr0_shift_x(BITSELECT,16700)@69
    assign rightShiftStage0Idx1Rng1_uid16701_dupName_113_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_q[33:1];

    // rightShiftStage0Idx1_uid16703_dupName_113_i_unnamed_c_compstr0_shift_x(BITJOIN,16702)@69
    assign rightShiftStage0Idx1_uid16703_dupName_113_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16701_dupName_113_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26013_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x(BITSELECT,26012)@68
    assign leftShiftStage2Idx1Rng8_uid26013_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_in = leftShiftStage1_uid26011_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26013_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26013_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26014_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x(BITJOIN,26013)@68
    assign leftShiftStage2Idx1_uid26014_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26013_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26008_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x(BITSELECT,26007)@68
    assign leftShiftStage1Idx1Rng4_uid26008_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_in = leftShiftStage0_uid26006_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26008_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26008_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26009_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x(BITJOIN,26008)@68
    assign leftShiftStage1Idx1_uid26009_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26008_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26003_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x(BITSELECT,26002)@68
    assign leftShiftStage0Idx1Rng1_uid26003_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_28_c_compstr818_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26003_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26003_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26004_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x(BITJOIN,26003)@68
    assign leftShiftStage0Idx1_uid26004_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26003_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16649_dupName_109_i_unnamed_c_compstr0_shift_x(BITSELECT,16648)@67
    assign rightShiftStage2Idx1Rng8_uid16649_dupName_109_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16648_dupName_109_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16651_dupName_109_i_unnamed_c_compstr0_shift_x(BITJOIN,16650)@67
    assign rightShiftStage2Idx1_uid16651_dupName_109_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16649_dupName_109_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16644_dupName_109_i_unnamed_c_compstr0_shift_x(BITSELECT,16643)@67
    assign rightShiftStage1Idx1Rng4_uid16644_dupName_109_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16643_dupName_109_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16646_dupName_109_i_unnamed_c_compstr0_shift_x(BITJOIN,16645)@67
    assign rightShiftStage1Idx1_uid16646_dupName_109_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16644_dupName_109_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16639_dupName_109_i_unnamed_c_compstr0_shift_x(BITSELECT,16638)@67
    assign rightShiftStage0Idx1Rng1_uid16639_dupName_109_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_q[33:1];

    // rightShiftStage0Idx1_uid16641_dupName_109_i_unnamed_c_compstr0_shift_x(BITJOIN,16640)@67
    assign rightShiftStage0Idx1_uid16641_dupName_109_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16639_dupName_109_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25995_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x(BITSELECT,25994)@66
    assign leftShiftStage2Idx1Rng8_uid25995_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_in = leftShiftStage1_uid25993_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25995_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25995_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25996_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x(BITJOIN,25995)@66
    assign leftShiftStage2Idx1_uid25996_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25995_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25990_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x(BITSELECT,25989)@66
    assign leftShiftStage1Idx1Rng4_uid25990_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_in = leftShiftStage0_uid25988_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25990_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25990_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25991_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x(BITJOIN,25990)@66
    assign leftShiftStage1Idx1_uid25991_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25990_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25985_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x(BITSELECT,25984)@66
    assign leftShiftStage0Idx1Rng1_uid25985_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_27_c_compstr790_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25985_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25985_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25986_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x(BITJOIN,25985)@66
    assign leftShiftStage0Idx1_uid25986_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25985_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16587_dupName_105_i_unnamed_c_compstr0_shift_x(BITSELECT,16586)@65
    assign rightShiftStage2Idx1Rng8_uid16587_dupName_105_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16586_dupName_105_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16589_dupName_105_i_unnamed_c_compstr0_shift_x(BITJOIN,16588)@65
    assign rightShiftStage2Idx1_uid16589_dupName_105_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16587_dupName_105_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16582_dupName_105_i_unnamed_c_compstr0_shift_x(BITSELECT,16581)@65
    assign rightShiftStage1Idx1Rng4_uid16582_dupName_105_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16581_dupName_105_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16584_dupName_105_i_unnamed_c_compstr0_shift_x(BITJOIN,16583)@65
    assign rightShiftStage1Idx1_uid16584_dupName_105_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16582_dupName_105_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16577_dupName_105_i_unnamed_c_compstr0_shift_x(BITSELECT,16576)@65
    assign rightShiftStage0Idx1Rng1_uid16577_dupName_105_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_q[33:1];

    // rightShiftStage0Idx1_uid16579_dupName_105_i_unnamed_c_compstr0_shift_x(BITJOIN,16578)@65
    assign rightShiftStage0Idx1_uid16579_dupName_105_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16577_dupName_105_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25977_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x(BITSELECT,25976)@64
    assign leftShiftStage2Idx1Rng8_uid25977_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_in = leftShiftStage1_uid25975_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25977_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25977_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25978_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x(BITJOIN,25977)@64
    assign leftShiftStage2Idx1_uid25978_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25977_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25972_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x(BITSELECT,25971)@64
    assign leftShiftStage1Idx1Rng4_uid25972_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_in = leftShiftStage0_uid25970_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25972_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25972_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25973_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x(BITJOIN,25972)@64
    assign leftShiftStage1Idx1_uid25973_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25972_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25967_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x(BITSELECT,25966)@64
    assign leftShiftStage0Idx1Rng1_uid25967_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_26_c_compstr762_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25967_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25967_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25968_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x(BITJOIN,25967)@64
    assign leftShiftStage0Idx1_uid25968_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25967_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16525_dupName_101_i_unnamed_c_compstr0_shift_x(BITSELECT,16524)@63
    assign rightShiftStage2Idx1Rng8_uid16525_dupName_101_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16524_dupName_101_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16527_dupName_101_i_unnamed_c_compstr0_shift_x(BITJOIN,16526)@63
    assign rightShiftStage2Idx1_uid16527_dupName_101_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16525_dupName_101_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16520_dupName_101_i_unnamed_c_compstr0_shift_x(BITSELECT,16519)@63
    assign rightShiftStage1Idx1Rng4_uid16520_dupName_101_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16519_dupName_101_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16522_dupName_101_i_unnamed_c_compstr0_shift_x(BITJOIN,16521)@63
    assign rightShiftStage1Idx1_uid16522_dupName_101_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16520_dupName_101_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16515_dupName_101_i_unnamed_c_compstr0_shift_x(BITSELECT,16514)@63
    assign rightShiftStage0Idx1Rng1_uid16515_dupName_101_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_q[33:1];

    // rightShiftStage0Idx1_uid16517_dupName_101_i_unnamed_c_compstr0_shift_x(BITJOIN,16516)@63
    assign rightShiftStage0Idx1_uid16517_dupName_101_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16515_dupName_101_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25959_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x(BITSELECT,25958)@62
    assign leftShiftStage2Idx1Rng8_uid25959_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_in = leftShiftStage1_uid25957_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25959_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25959_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25960_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x(BITJOIN,25959)@62
    assign leftShiftStage2Idx1_uid25960_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25959_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25954_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x(BITSELECT,25953)@62
    assign leftShiftStage1Idx1Rng4_uid25954_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_in = leftShiftStage0_uid25952_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25954_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25954_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25955_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x(BITJOIN,25954)@62
    assign leftShiftStage1Idx1_uid25955_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25954_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25949_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x(BITSELECT,25948)@62
    assign leftShiftStage0Idx1Rng1_uid25949_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_25_c_compstr734_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25949_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25949_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25950_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x(BITJOIN,25949)@62
    assign leftShiftStage0Idx1_uid25950_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25949_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16463_dupName_97_i_unnamed_c_compstr0_shift_x(BITSELECT,16462)@61
    assign rightShiftStage2Idx1Rng8_uid16463_dupName_97_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16462_dupName_97_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16465_dupName_97_i_unnamed_c_compstr0_shift_x(BITJOIN,16464)@61
    assign rightShiftStage2Idx1_uid16465_dupName_97_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16463_dupName_97_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16458_dupName_97_i_unnamed_c_compstr0_shift_x(BITSELECT,16457)@61
    assign rightShiftStage1Idx1Rng4_uid16458_dupName_97_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16457_dupName_97_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16460_dupName_97_i_unnamed_c_compstr0_shift_x(BITJOIN,16459)@61
    assign rightShiftStage1Idx1_uid16460_dupName_97_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16458_dupName_97_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16453_dupName_97_i_unnamed_c_compstr0_shift_x(BITSELECT,16452)@61
    assign rightShiftStage0Idx1Rng1_uid16453_dupName_97_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_q[33:1];

    // rightShiftStage0Idx1_uid16455_dupName_97_i_unnamed_c_compstr0_shift_x(BITJOIN,16454)@61
    assign rightShiftStage0Idx1_uid16455_dupName_97_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16453_dupName_97_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25941_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x(BITSELECT,25940)@60
    assign leftShiftStage2Idx1Rng8_uid25941_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_in = leftShiftStage1_uid25939_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25941_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25941_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25942_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x(BITJOIN,25941)@60
    assign leftShiftStage2Idx1_uid25942_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25941_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25936_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x(BITSELECT,25935)@60
    assign leftShiftStage1Idx1Rng4_uid25936_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_in = leftShiftStage0_uid25934_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25936_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25936_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25937_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x(BITJOIN,25936)@60
    assign leftShiftStage1Idx1_uid25937_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25936_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25931_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x(BITSELECT,25930)@60
    assign leftShiftStage0Idx1Rng1_uid25931_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_24_c_compstr706_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25931_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25931_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25932_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x(BITJOIN,25931)@60
    assign leftShiftStage0Idx1_uid25932_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25931_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16401_dupName_93_i_unnamed_c_compstr0_shift_x(BITSELECT,16400)@59
    assign rightShiftStage2Idx1Rng8_uid16401_dupName_93_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16400_dupName_93_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16403_dupName_93_i_unnamed_c_compstr0_shift_x(BITJOIN,16402)@59
    assign rightShiftStage2Idx1_uid16403_dupName_93_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16401_dupName_93_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16396_dupName_93_i_unnamed_c_compstr0_shift_x(BITSELECT,16395)@59
    assign rightShiftStage1Idx1Rng4_uid16396_dupName_93_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16395_dupName_93_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16398_dupName_93_i_unnamed_c_compstr0_shift_x(BITJOIN,16397)@59
    assign rightShiftStage1Idx1_uid16398_dupName_93_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16396_dupName_93_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16391_dupName_93_i_unnamed_c_compstr0_shift_x(BITSELECT,16390)@59
    assign rightShiftStage0Idx1Rng1_uid16391_dupName_93_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_q[33:1];

    // rightShiftStage0Idx1_uid16393_dupName_93_i_unnamed_c_compstr0_shift_x(BITJOIN,16392)@59
    assign rightShiftStage0Idx1_uid16393_dupName_93_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16391_dupName_93_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25923_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x(BITSELECT,25922)@58
    assign leftShiftStage2Idx1Rng8_uid25923_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_in = leftShiftStage1_uid25921_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25923_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25923_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25924_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x(BITJOIN,25923)@58
    assign leftShiftStage2Idx1_uid25924_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25923_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25918_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x(BITSELECT,25917)@58
    assign leftShiftStage1Idx1Rng4_uid25918_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_in = leftShiftStage0_uid25916_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25918_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25918_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25919_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x(BITJOIN,25918)@58
    assign leftShiftStage1Idx1_uid25919_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25918_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25913_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x(BITSELECT,25912)@58
    assign leftShiftStage0Idx1Rng1_uid25913_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_23_c_compstr678_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25913_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25913_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25914_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x(BITJOIN,25913)@58
    assign leftShiftStage0Idx1_uid25914_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25913_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16339_dupName_89_i_unnamed_c_compstr0_shift_x(BITSELECT,16338)@57
    assign rightShiftStage2Idx1Rng8_uid16339_dupName_89_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16338_dupName_89_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16341_dupName_89_i_unnamed_c_compstr0_shift_x(BITJOIN,16340)@57
    assign rightShiftStage2Idx1_uid16341_dupName_89_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16339_dupName_89_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16334_dupName_89_i_unnamed_c_compstr0_shift_x(BITSELECT,16333)@57
    assign rightShiftStage1Idx1Rng4_uid16334_dupName_89_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16333_dupName_89_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16336_dupName_89_i_unnamed_c_compstr0_shift_x(BITJOIN,16335)@57
    assign rightShiftStage1Idx1_uid16336_dupName_89_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16334_dupName_89_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16329_dupName_89_i_unnamed_c_compstr0_shift_x(BITSELECT,16328)@57
    assign rightShiftStage0Idx1Rng1_uid16329_dupName_89_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_q[33:1];

    // rightShiftStage0Idx1_uid16331_dupName_89_i_unnamed_c_compstr0_shift_x(BITJOIN,16330)@57
    assign rightShiftStage0Idx1_uid16331_dupName_89_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16329_dupName_89_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25905_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x(BITSELECT,25904)@56
    assign leftShiftStage2Idx1Rng8_uid25905_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_in = leftShiftStage1_uid25903_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25905_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25905_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25906_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x(BITJOIN,25905)@56
    assign leftShiftStage2Idx1_uid25906_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25905_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25900_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x(BITSELECT,25899)@56
    assign leftShiftStage1Idx1Rng4_uid25900_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_in = leftShiftStage0_uid25898_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25900_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25900_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25901_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x(BITJOIN,25900)@56
    assign leftShiftStage1Idx1_uid25901_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25900_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25895_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x(BITSELECT,25894)@56
    assign leftShiftStage0Idx1Rng1_uid25895_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_22_c_compstr650_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25895_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25895_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25896_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x(BITJOIN,25895)@56
    assign leftShiftStage0Idx1_uid25896_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25895_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16277_dupName_85_i_unnamed_c_compstr0_shift_x(BITSELECT,16276)@55
    assign rightShiftStage2Idx1Rng8_uid16277_dupName_85_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16276_dupName_85_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16279_dupName_85_i_unnamed_c_compstr0_shift_x(BITJOIN,16278)@55
    assign rightShiftStage2Idx1_uid16279_dupName_85_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16277_dupName_85_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16272_dupName_85_i_unnamed_c_compstr0_shift_x(BITSELECT,16271)@55
    assign rightShiftStage1Idx1Rng4_uid16272_dupName_85_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16271_dupName_85_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16274_dupName_85_i_unnamed_c_compstr0_shift_x(BITJOIN,16273)@55
    assign rightShiftStage1Idx1_uid16274_dupName_85_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16272_dupName_85_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16267_dupName_85_i_unnamed_c_compstr0_shift_x(BITSELECT,16266)@55
    assign rightShiftStage0Idx1Rng1_uid16267_dupName_85_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_q[33:1];

    // rightShiftStage0Idx1_uid16269_dupName_85_i_unnamed_c_compstr0_shift_x(BITJOIN,16268)@55
    assign rightShiftStage0Idx1_uid16269_dupName_85_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16267_dupName_85_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25887_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x(BITSELECT,25886)@54
    assign leftShiftStage2Idx1Rng8_uid25887_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_in = leftShiftStage1_uid25885_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25887_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25887_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25888_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x(BITJOIN,25887)@54
    assign leftShiftStage2Idx1_uid25888_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25887_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25882_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x(BITSELECT,25881)@54
    assign leftShiftStage1Idx1Rng4_uid25882_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_in = leftShiftStage0_uid25880_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25882_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25882_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25883_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x(BITJOIN,25882)@54
    assign leftShiftStage1Idx1_uid25883_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25882_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25877_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x(BITSELECT,25876)@54
    assign leftShiftStage0Idx1Rng1_uid25877_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_21_c_compstr622_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25877_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25877_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25878_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x(BITJOIN,25877)@54
    assign leftShiftStage0Idx1_uid25878_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25877_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16215_dupName_81_i_unnamed_c_compstr0_shift_x(BITSELECT,16214)@53
    assign rightShiftStage2Idx1Rng8_uid16215_dupName_81_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16214_dupName_81_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16217_dupName_81_i_unnamed_c_compstr0_shift_x(BITJOIN,16216)@53
    assign rightShiftStage2Idx1_uid16217_dupName_81_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16215_dupName_81_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16210_dupName_81_i_unnamed_c_compstr0_shift_x(BITSELECT,16209)@53
    assign rightShiftStage1Idx1Rng4_uid16210_dupName_81_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16209_dupName_81_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16212_dupName_81_i_unnamed_c_compstr0_shift_x(BITJOIN,16211)@53
    assign rightShiftStage1Idx1_uid16212_dupName_81_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16210_dupName_81_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16205_dupName_81_i_unnamed_c_compstr0_shift_x(BITSELECT,16204)@53
    assign rightShiftStage0Idx1Rng1_uid16205_dupName_81_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_q[33:1];

    // rightShiftStage0Idx1_uid16207_dupName_81_i_unnamed_c_compstr0_shift_x(BITJOIN,16206)@53
    assign rightShiftStage0Idx1_uid16207_dupName_81_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16205_dupName_81_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25869_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x(BITSELECT,25868)@52
    assign leftShiftStage2Idx1Rng8_uid25869_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_in = leftShiftStage1_uid25867_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25869_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25869_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25870_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x(BITJOIN,25869)@52
    assign leftShiftStage2Idx1_uid25870_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25869_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25864_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x(BITSELECT,25863)@52
    assign leftShiftStage1Idx1Rng4_uid25864_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_in = leftShiftStage0_uid25862_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25864_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25864_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25865_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x(BITJOIN,25864)@52
    assign leftShiftStage1Idx1_uid25865_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25864_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25859_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x(BITSELECT,25858)@52
    assign leftShiftStage0Idx1Rng1_uid25859_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_20_c_compstr594_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25859_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25859_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25860_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x(BITJOIN,25859)@52
    assign leftShiftStage0Idx1_uid25860_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25859_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16153_dupName_77_i_unnamed_c_compstr0_shift_x(BITSELECT,16152)@51
    assign rightShiftStage2Idx1Rng8_uid16153_dupName_77_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16152_dupName_77_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16155_dupName_77_i_unnamed_c_compstr0_shift_x(BITJOIN,16154)@51
    assign rightShiftStage2Idx1_uid16155_dupName_77_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16153_dupName_77_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16148_dupName_77_i_unnamed_c_compstr0_shift_x(BITSELECT,16147)@51
    assign rightShiftStage1Idx1Rng4_uid16148_dupName_77_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16147_dupName_77_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16150_dupName_77_i_unnamed_c_compstr0_shift_x(BITJOIN,16149)@51
    assign rightShiftStage1Idx1_uid16150_dupName_77_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16148_dupName_77_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16143_dupName_77_i_unnamed_c_compstr0_shift_x(BITSELECT,16142)@51
    assign rightShiftStage0Idx1Rng1_uid16143_dupName_77_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_q[33:1];

    // rightShiftStage0Idx1_uid16145_dupName_77_i_unnamed_c_compstr0_shift_x(BITJOIN,16144)@51
    assign rightShiftStage0Idx1_uid16145_dupName_77_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16143_dupName_77_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25833_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x(BITSELECT,25832)@50
    assign leftShiftStage2Idx1Rng8_uid25833_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_in = leftShiftStage1_uid25831_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25833_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25833_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25834_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x(BITJOIN,25833)@50
    assign leftShiftStage2Idx1_uid25834_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25833_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25828_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x(BITSELECT,25827)@50
    assign leftShiftStage1Idx1Rng4_uid25828_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_in = leftShiftStage0_uid25826_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25828_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25828_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25829_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x(BITJOIN,25828)@50
    assign leftShiftStage1Idx1_uid25829_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25828_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25823_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x(BITSELECT,25822)@50
    assign leftShiftStage0Idx1Rng1_uid25823_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_19_c_compstr566_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25823_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25823_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25824_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x(BITJOIN,25823)@50
    assign leftShiftStage0Idx1_uid25824_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25823_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16091_dupName_73_i_unnamed_c_compstr0_shift_x(BITSELECT,16090)@49
    assign rightShiftStage2Idx1Rng8_uid16091_dupName_73_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16090_dupName_73_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16093_dupName_73_i_unnamed_c_compstr0_shift_x(BITJOIN,16092)@49
    assign rightShiftStage2Idx1_uid16093_dupName_73_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16091_dupName_73_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16086_dupName_73_i_unnamed_c_compstr0_shift_x(BITSELECT,16085)@49
    assign rightShiftStage1Idx1Rng4_uid16086_dupName_73_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16085_dupName_73_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16088_dupName_73_i_unnamed_c_compstr0_shift_x(BITJOIN,16087)@49
    assign rightShiftStage1Idx1_uid16088_dupName_73_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16086_dupName_73_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16081_dupName_73_i_unnamed_c_compstr0_shift_x(BITSELECT,16080)@49
    assign rightShiftStage0Idx1Rng1_uid16081_dupName_73_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_q[33:1];

    // rightShiftStage0Idx1_uid16083_dupName_73_i_unnamed_c_compstr0_shift_x(BITJOIN,16082)@49
    assign rightShiftStage0Idx1_uid16083_dupName_73_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16081_dupName_73_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25815_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x(BITSELECT,25814)@48
    assign leftShiftStage2Idx1Rng8_uid25815_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_in = leftShiftStage1_uid25813_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25815_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25815_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25816_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x(BITJOIN,25815)@48
    assign leftShiftStage2Idx1_uid25816_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25815_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25810_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x(BITSELECT,25809)@48
    assign leftShiftStage1Idx1Rng4_uid25810_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_in = leftShiftStage0_uid25808_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25810_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25810_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25811_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x(BITJOIN,25810)@48
    assign leftShiftStage1Idx1_uid25811_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25810_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25805_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x(BITSELECT,25804)@48
    assign leftShiftStage0Idx1Rng1_uid25805_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_18_c_compstr538_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25805_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25805_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25806_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x(BITJOIN,25805)@48
    assign leftShiftStage0Idx1_uid25806_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25805_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16029_dupName_69_i_unnamed_c_compstr0_shift_x(BITSELECT,16028)@47
    assign rightShiftStage2Idx1Rng8_uid16029_dupName_69_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16028_dupName_69_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16031_dupName_69_i_unnamed_c_compstr0_shift_x(BITJOIN,16030)@47
    assign rightShiftStage2Idx1_uid16031_dupName_69_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16029_dupName_69_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16024_dupName_69_i_unnamed_c_compstr0_shift_x(BITSELECT,16023)@47
    assign rightShiftStage1Idx1Rng4_uid16024_dupName_69_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16023_dupName_69_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16026_dupName_69_i_unnamed_c_compstr0_shift_x(BITJOIN,16025)@47
    assign rightShiftStage1Idx1_uid16026_dupName_69_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16024_dupName_69_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16019_dupName_69_i_unnamed_c_compstr0_shift_x(BITSELECT,16018)@47
    assign rightShiftStage0Idx1Rng1_uid16019_dupName_69_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_q[33:1];

    // rightShiftStage0Idx1_uid16021_dupName_69_i_unnamed_c_compstr0_shift_x(BITJOIN,16020)@47
    assign rightShiftStage0Idx1_uid16021_dupName_69_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16019_dupName_69_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25797_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x(BITSELECT,25796)@46
    assign leftShiftStage2Idx1Rng8_uid25797_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_in = leftShiftStage1_uid25795_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25797_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25797_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25798_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x(BITJOIN,25797)@46
    assign leftShiftStage2Idx1_uid25798_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25797_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25792_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x(BITSELECT,25791)@46
    assign leftShiftStage1Idx1Rng4_uid25792_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_in = leftShiftStage0_uid25790_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25792_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25792_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25793_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x(BITJOIN,25792)@46
    assign leftShiftStage1Idx1_uid25793_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25792_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25787_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x(BITSELECT,25786)@46
    assign leftShiftStage0Idx1Rng1_uid25787_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_17_c_compstr510_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25787_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25787_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25788_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x(BITJOIN,25787)@46
    assign leftShiftStage0Idx1_uid25788_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25787_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15967_dupName_65_i_unnamed_c_compstr0_shift_x(BITSELECT,15966)@45
    assign rightShiftStage2Idx1Rng8_uid15967_dupName_65_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15966_dupName_65_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15969_dupName_65_i_unnamed_c_compstr0_shift_x(BITJOIN,15968)@45
    assign rightShiftStage2Idx1_uid15969_dupName_65_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15967_dupName_65_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15962_dupName_65_i_unnamed_c_compstr0_shift_x(BITSELECT,15961)@45
    assign rightShiftStage1Idx1Rng4_uid15962_dupName_65_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15961_dupName_65_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15964_dupName_65_i_unnamed_c_compstr0_shift_x(BITJOIN,15963)@45
    assign rightShiftStage1Idx1_uid15964_dupName_65_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15962_dupName_65_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15957_dupName_65_i_unnamed_c_compstr0_shift_x(BITSELECT,15956)@45
    assign rightShiftStage0Idx1Rng1_uid15957_dupName_65_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_q[33:1];

    // rightShiftStage0Idx1_uid15959_dupName_65_i_unnamed_c_compstr0_shift_x(BITJOIN,15958)@45
    assign rightShiftStage0Idx1_uid15959_dupName_65_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15957_dupName_65_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25779_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x(BITSELECT,25778)@44
    assign leftShiftStage2Idx1Rng8_uid25779_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_in = leftShiftStage1_uid25777_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25779_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25779_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25780_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x(BITJOIN,25779)@44
    assign leftShiftStage2Idx1_uid25780_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25779_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25774_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x(BITSELECT,25773)@44
    assign leftShiftStage1Idx1Rng4_uid25774_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_in = leftShiftStage0_uid25772_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25774_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25774_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25775_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x(BITJOIN,25774)@44
    assign leftShiftStage1Idx1_uid25775_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25774_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25769_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x(BITSELECT,25768)@44
    assign leftShiftStage0Idx1Rng1_uid25769_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_16_c_compstr482_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25769_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25769_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25770_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x(BITJOIN,25769)@44
    assign leftShiftStage0Idx1_uid25770_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25769_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15905_dupName_61_i_unnamed_c_compstr0_shift_x(BITSELECT,15904)@43
    assign rightShiftStage2Idx1Rng8_uid15905_dupName_61_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15904_dupName_61_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15907_dupName_61_i_unnamed_c_compstr0_shift_x(BITJOIN,15906)@43
    assign rightShiftStage2Idx1_uid15907_dupName_61_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15905_dupName_61_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15900_dupName_61_i_unnamed_c_compstr0_shift_x(BITSELECT,15899)@43
    assign rightShiftStage1Idx1Rng4_uid15900_dupName_61_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15899_dupName_61_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15902_dupName_61_i_unnamed_c_compstr0_shift_x(BITJOIN,15901)@43
    assign rightShiftStage1Idx1_uid15902_dupName_61_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15900_dupName_61_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15895_dupName_61_i_unnamed_c_compstr0_shift_x(BITSELECT,15894)@43
    assign rightShiftStage0Idx1Rng1_uid15895_dupName_61_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_q[33:1];

    // rightShiftStage0Idx1_uid15897_dupName_61_i_unnamed_c_compstr0_shift_x(BITJOIN,15896)@43
    assign rightShiftStage0Idx1_uid15897_dupName_61_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15895_dupName_61_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25761_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x(BITSELECT,25760)@42
    assign leftShiftStage2Idx1Rng8_uid25761_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_in = leftShiftStage1_uid25759_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25761_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25761_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25762_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x(BITJOIN,25761)@42
    assign leftShiftStage2Idx1_uid25762_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25761_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25756_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x(BITSELECT,25755)@42
    assign leftShiftStage1Idx1Rng4_uid25756_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_in = leftShiftStage0_uid25754_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25756_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25756_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25757_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x(BITJOIN,25756)@42
    assign leftShiftStage1Idx1_uid25757_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25756_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25751_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x(BITSELECT,25750)@42
    assign leftShiftStage0Idx1Rng1_uid25751_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_15_c_compstr454_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25751_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25751_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25752_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x(BITJOIN,25751)@42
    assign leftShiftStage0Idx1_uid25752_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25751_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15843_dupName_57_i_unnamed_c_compstr0_shift_x(BITSELECT,15842)@41
    assign rightShiftStage2Idx1Rng8_uid15843_dupName_57_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15842_dupName_57_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15845_dupName_57_i_unnamed_c_compstr0_shift_x(BITJOIN,15844)@41
    assign rightShiftStage2Idx1_uid15845_dupName_57_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15843_dupName_57_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15838_dupName_57_i_unnamed_c_compstr0_shift_x(BITSELECT,15837)@41
    assign rightShiftStage1Idx1Rng4_uid15838_dupName_57_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15837_dupName_57_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15840_dupName_57_i_unnamed_c_compstr0_shift_x(BITJOIN,15839)@41
    assign rightShiftStage1Idx1_uid15840_dupName_57_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15838_dupName_57_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15833_dupName_57_i_unnamed_c_compstr0_shift_x(BITSELECT,15832)@41
    assign rightShiftStage0Idx1Rng1_uid15833_dupName_57_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_q[33:1];

    // rightShiftStage0Idx1_uid15835_dupName_57_i_unnamed_c_compstr0_shift_x(BITJOIN,15834)@41
    assign rightShiftStage0Idx1_uid15835_dupName_57_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15833_dupName_57_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25743_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x(BITSELECT,25742)@40
    assign leftShiftStage2Idx1Rng8_uid25743_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_in = leftShiftStage1_uid25741_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25743_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25743_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25744_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x(BITJOIN,25743)@40
    assign leftShiftStage2Idx1_uid25744_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25743_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25738_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x(BITSELECT,25737)@40
    assign leftShiftStage1Idx1Rng4_uid25738_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_in = leftShiftStage0_uid25736_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25738_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25738_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25739_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x(BITJOIN,25738)@40
    assign leftShiftStage1Idx1_uid25739_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25738_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25733_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x(BITSELECT,25732)@40
    assign leftShiftStage0Idx1Rng1_uid25733_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_14_c_compstr426_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25733_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25733_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25734_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x(BITJOIN,25733)@40
    assign leftShiftStage0Idx1_uid25734_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25733_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15781_dupName_53_i_unnamed_c_compstr0_shift_x(BITSELECT,15780)@39
    assign rightShiftStage2Idx1Rng8_uid15781_dupName_53_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15780_dupName_53_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15783_dupName_53_i_unnamed_c_compstr0_shift_x(BITJOIN,15782)@39
    assign rightShiftStage2Idx1_uid15783_dupName_53_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15781_dupName_53_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15776_dupName_53_i_unnamed_c_compstr0_shift_x(BITSELECT,15775)@39
    assign rightShiftStage1Idx1Rng4_uid15776_dupName_53_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15775_dupName_53_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15778_dupName_53_i_unnamed_c_compstr0_shift_x(BITJOIN,15777)@39
    assign rightShiftStage1Idx1_uid15778_dupName_53_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15776_dupName_53_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15771_dupName_53_i_unnamed_c_compstr0_shift_x(BITSELECT,15770)@39
    assign rightShiftStage0Idx1Rng1_uid15771_dupName_53_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_q[33:1];

    // rightShiftStage0Idx1_uid15773_dupName_53_i_unnamed_c_compstr0_shift_x(BITJOIN,15772)@39
    assign rightShiftStage0Idx1_uid15773_dupName_53_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15771_dupName_53_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25725_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x(BITSELECT,25724)@38
    assign leftShiftStage2Idx1Rng8_uid25725_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_in = leftShiftStage1_uid25723_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25725_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25725_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25726_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x(BITJOIN,25725)@38
    assign leftShiftStage2Idx1_uid25726_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25725_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25720_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x(BITSELECT,25719)@38
    assign leftShiftStage1Idx1Rng4_uid25720_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_in = leftShiftStage0_uid25718_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25720_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25720_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25721_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x(BITJOIN,25720)@38
    assign leftShiftStage1Idx1_uid25721_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25720_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25715_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x(BITSELECT,25714)@38
    assign leftShiftStage0Idx1Rng1_uid25715_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_13_c_compstr398_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25715_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25715_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25716_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x(BITJOIN,25715)@38
    assign leftShiftStage0Idx1_uid25716_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25715_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15719_dupName_49_i_unnamed_c_compstr0_shift_x(BITSELECT,15718)@37
    assign rightShiftStage2Idx1Rng8_uid15719_dupName_49_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15718_dupName_49_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15721_dupName_49_i_unnamed_c_compstr0_shift_x(BITJOIN,15720)@37
    assign rightShiftStage2Idx1_uid15721_dupName_49_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15719_dupName_49_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15714_dupName_49_i_unnamed_c_compstr0_shift_x(BITSELECT,15713)@37
    assign rightShiftStage1Idx1Rng4_uid15714_dupName_49_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15713_dupName_49_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15716_dupName_49_i_unnamed_c_compstr0_shift_x(BITJOIN,15715)@37
    assign rightShiftStage1Idx1_uid15716_dupName_49_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15714_dupName_49_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15709_dupName_49_i_unnamed_c_compstr0_shift_x(BITSELECT,15708)@37
    assign rightShiftStage0Idx1Rng1_uid15709_dupName_49_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_q[33:1];

    // rightShiftStage0Idx1_uid15711_dupName_49_i_unnamed_c_compstr0_shift_x(BITJOIN,15710)@37
    assign rightShiftStage0Idx1_uid15711_dupName_49_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15709_dupName_49_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25707_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x(BITSELECT,25706)@36
    assign leftShiftStage2Idx1Rng8_uid25707_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_in = leftShiftStage1_uid25705_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25707_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25707_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25708_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x(BITJOIN,25707)@36
    assign leftShiftStage2Idx1_uid25708_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25707_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25702_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x(BITSELECT,25701)@36
    assign leftShiftStage1Idx1Rng4_uid25702_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_in = leftShiftStage0_uid25700_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25702_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25702_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25703_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x(BITJOIN,25702)@36
    assign leftShiftStage1Idx1_uid25703_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25702_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25697_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x(BITSELECT,25696)@36
    assign leftShiftStage0Idx1Rng1_uid25697_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_12_c_compstr370_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25697_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25697_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25698_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x(BITJOIN,25697)@36
    assign leftShiftStage0Idx1_uid25698_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25697_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15657_dupName_45_i_unnamed_c_compstr0_shift_x(BITSELECT,15656)@35
    assign rightShiftStage2Idx1Rng8_uid15657_dupName_45_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15656_dupName_45_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15659_dupName_45_i_unnamed_c_compstr0_shift_x(BITJOIN,15658)@35
    assign rightShiftStage2Idx1_uid15659_dupName_45_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15657_dupName_45_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15652_dupName_45_i_unnamed_c_compstr0_shift_x(BITSELECT,15651)@35
    assign rightShiftStage1Idx1Rng4_uid15652_dupName_45_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15651_dupName_45_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15654_dupName_45_i_unnamed_c_compstr0_shift_x(BITJOIN,15653)@35
    assign rightShiftStage1Idx1_uid15654_dupName_45_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15652_dupName_45_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15647_dupName_45_i_unnamed_c_compstr0_shift_x(BITSELECT,15646)@35
    assign rightShiftStage0Idx1Rng1_uid15647_dupName_45_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_q[33:1];

    // rightShiftStage0Idx1_uid15649_dupName_45_i_unnamed_c_compstr0_shift_x(BITJOIN,15648)@35
    assign rightShiftStage0Idx1_uid15649_dupName_45_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15647_dupName_45_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25545_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x(BITSELECT,25544)@34
    assign leftShiftStage2Idx1Rng8_uid25545_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_in = leftShiftStage1_uid25543_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25545_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25545_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25546_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x(BITJOIN,25545)@34
    assign leftShiftStage2Idx1_uid25546_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25545_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25540_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x(BITSELECT,25539)@34
    assign leftShiftStage1Idx1Rng4_uid25540_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_in = leftShiftStage0_uid25538_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25540_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25540_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25541_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x(BITJOIN,25540)@34
    assign leftShiftStage1Idx1_uid25541_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25540_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25535_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x(BITSELECT,25534)@34
    assign leftShiftStage0Idx1Rng1_uid25535_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_11_c_compstr342_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25535_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25535_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25536_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x(BITJOIN,25535)@34
    assign leftShiftStage0Idx1_uid25536_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25535_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15595_dupName_41_i_unnamed_c_compstr0_shift_x(BITSELECT,15594)@33
    assign rightShiftStage2Idx1Rng8_uid15595_dupName_41_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15594_dupName_41_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15597_dupName_41_i_unnamed_c_compstr0_shift_x(BITJOIN,15596)@33
    assign rightShiftStage2Idx1_uid15597_dupName_41_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15595_dupName_41_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15590_dupName_41_i_unnamed_c_compstr0_shift_x(BITSELECT,15589)@33
    assign rightShiftStage1Idx1Rng4_uid15590_dupName_41_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15589_dupName_41_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15592_dupName_41_i_unnamed_c_compstr0_shift_x(BITJOIN,15591)@33
    assign rightShiftStage1Idx1_uid15592_dupName_41_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15590_dupName_41_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15585_dupName_41_i_unnamed_c_compstr0_shift_x(BITSELECT,15584)@33
    assign rightShiftStage0Idx1Rng1_uid15585_dupName_41_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_q[33:1];

    // rightShiftStage0Idx1_uid15587_dupName_41_i_unnamed_c_compstr0_shift_x(BITJOIN,15586)@33
    assign rightShiftStage0Idx1_uid15587_dupName_41_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15585_dupName_41_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25347_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x(BITSELECT,25346)@32
    assign leftShiftStage2Idx1Rng8_uid25347_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_in = leftShiftStage1_uid25345_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25347_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25347_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25348_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x(BITJOIN,25347)@32
    assign leftShiftStage2Idx1_uid25348_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25347_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25342_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x(BITSELECT,25341)@32
    assign leftShiftStage1Idx1Rng4_uid25342_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_in = leftShiftStage0_uid25340_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25342_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25342_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25343_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x(BITJOIN,25342)@32
    assign leftShiftStage1Idx1_uid25343_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25342_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25337_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x(BITSELECT,25336)@32
    assign leftShiftStage0Idx1Rng1_uid25337_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_10_c_compstr314_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25337_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25337_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25338_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x(BITJOIN,25337)@32
    assign leftShiftStage0Idx1_uid25338_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25337_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15533_dupName_37_i_unnamed_c_compstr0_shift_x(BITSELECT,15532)@31
    assign rightShiftStage2Idx1Rng8_uid15533_dupName_37_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15532_dupName_37_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15535_dupName_37_i_unnamed_c_compstr0_shift_x(BITJOIN,15534)@31
    assign rightShiftStage2Idx1_uid15535_dupName_37_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15533_dupName_37_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15528_dupName_37_i_unnamed_c_compstr0_shift_x(BITSELECT,15527)@31
    assign rightShiftStage1Idx1Rng4_uid15528_dupName_37_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15527_dupName_37_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15530_dupName_37_i_unnamed_c_compstr0_shift_x(BITJOIN,15529)@31
    assign rightShiftStage1Idx1_uid15530_dupName_37_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15528_dupName_37_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15523_dupName_37_i_unnamed_c_compstr0_shift_x(BITSELECT,15522)@31
    assign rightShiftStage0Idx1Rng1_uid15523_dupName_37_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_q[33:1];

    // rightShiftStage0Idx1_uid15525_dupName_37_i_unnamed_c_compstr0_shift_x(BITJOIN,15524)@31
    assign rightShiftStage0Idx1_uid15525_dupName_37_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15523_dupName_37_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27435_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x(BITSELECT,27434)@30
    assign leftShiftStage2Idx1Rng8_uid27435_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_in = leftShiftStage1_uid27433_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27435_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27435_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27436_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x(BITJOIN,27435)@30
    assign leftShiftStage2Idx1_uid27436_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27435_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27430_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x(BITSELECT,27429)@30
    assign leftShiftStage1Idx1Rng4_uid27430_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_in = leftShiftStage0_uid27428_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27430_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27430_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27431_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x(BITJOIN,27430)@30
    assign leftShiftStage1Idx1_uid27431_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27430_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27425_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x(BITSELECT,27424)@30
    assign leftShiftStage0Idx1Rng1_uid27425_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_9_c_compstr286_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27425_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27425_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27426_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x(BITJOIN,27425)@30
    assign leftShiftStage0Idx1_uid27426_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27425_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15471_dupName_33_i_unnamed_c_compstr0_shift_x(BITSELECT,15470)@29
    assign rightShiftStage2Idx1Rng8_uid15471_dupName_33_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15470_dupName_33_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15473_dupName_33_i_unnamed_c_compstr0_shift_x(BITJOIN,15472)@29
    assign rightShiftStage2Idx1_uid15473_dupName_33_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15471_dupName_33_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15466_dupName_33_i_unnamed_c_compstr0_shift_x(BITSELECT,15465)@29
    assign rightShiftStage1Idx1Rng4_uid15466_dupName_33_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15465_dupName_33_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15468_dupName_33_i_unnamed_c_compstr0_shift_x(BITJOIN,15467)@29
    assign rightShiftStage1Idx1_uid15468_dupName_33_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15466_dupName_33_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15461_dupName_33_i_unnamed_c_compstr0_shift_x(BITSELECT,15460)@29
    assign rightShiftStage0Idx1Rng1_uid15461_dupName_33_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_q[33:1];

    // rightShiftStage0Idx1_uid15463_dupName_33_i_unnamed_c_compstr0_shift_x(BITJOIN,15462)@29
    assign rightShiftStage0Idx1_uid15463_dupName_33_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15461_dupName_33_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27237_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x(BITSELECT,27236)@28
    assign leftShiftStage2Idx1Rng8_uid27237_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_in = leftShiftStage1_uid27235_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27237_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27237_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27238_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x(BITJOIN,27237)@28
    assign leftShiftStage2Idx1_uid27238_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27237_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27232_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x(BITSELECT,27231)@28
    assign leftShiftStage1Idx1Rng4_uid27232_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_in = leftShiftStage0_uid27230_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27232_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27232_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27233_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x(BITJOIN,27232)@28
    assign leftShiftStage1Idx1_uid27233_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27232_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27227_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x(BITSELECT,27226)@28
    assign leftShiftStage0Idx1Rng1_uid27227_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_8_c_compstr258_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27227_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27227_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27228_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x(BITJOIN,27227)@28
    assign leftShiftStage0Idx1_uid27228_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27227_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15409_dupName_29_i_unnamed_c_compstr0_shift_x(BITSELECT,15408)@27
    assign rightShiftStage2Idx1Rng8_uid15409_dupName_29_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15408_dupName_29_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15411_dupName_29_i_unnamed_c_compstr0_shift_x(BITJOIN,15410)@27
    assign rightShiftStage2Idx1_uid15411_dupName_29_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15409_dupName_29_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15404_dupName_29_i_unnamed_c_compstr0_shift_x(BITSELECT,15403)@27
    assign rightShiftStage1Idx1Rng4_uid15404_dupName_29_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15403_dupName_29_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15406_dupName_29_i_unnamed_c_compstr0_shift_x(BITJOIN,15405)@27
    assign rightShiftStage1Idx1_uid15406_dupName_29_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15404_dupName_29_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15399_dupName_29_i_unnamed_c_compstr0_shift_x(BITSELECT,15398)@27
    assign rightShiftStage0Idx1Rng1_uid15399_dupName_29_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_q[33:1];

    // rightShiftStage0Idx1_uid15401_dupName_29_i_unnamed_c_compstr0_shift_x(BITJOIN,15400)@27
    assign rightShiftStage0Idx1_uid15401_dupName_29_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15399_dupName_29_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27039_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x(BITSELECT,27038)@26
    assign leftShiftStage2Idx1Rng8_uid27039_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_in = leftShiftStage1_uid27037_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27039_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid27039_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27040_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x(BITJOIN,27039)@26
    assign leftShiftStage2Idx1_uid27040_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27039_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27034_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x(BITSELECT,27033)@26
    assign leftShiftStage1Idx1Rng4_uid27034_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_in = leftShiftStage0_uid27032_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27034_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid27034_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27035_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x(BITJOIN,27034)@26
    assign leftShiftStage1Idx1_uid27035_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27034_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27029_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x(BITSELECT,27028)@26
    assign leftShiftStage0Idx1Rng1_uid27029_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_7_c_compstr230_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27029_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid27029_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27030_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x(BITJOIN,27029)@26
    assign leftShiftStage0Idx1_uid27030_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27029_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15347_dupName_25_i_unnamed_c_compstr0_shift_x(BITSELECT,15346)@25
    assign rightShiftStage2Idx1Rng8_uid15347_dupName_25_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15346_dupName_25_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15349_dupName_25_i_unnamed_c_compstr0_shift_x(BITJOIN,15348)@25
    assign rightShiftStage2Idx1_uid15349_dupName_25_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15347_dupName_25_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15342_dupName_25_i_unnamed_c_compstr0_shift_x(BITSELECT,15341)@25
    assign rightShiftStage1Idx1Rng4_uid15342_dupName_25_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15341_dupName_25_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15344_dupName_25_i_unnamed_c_compstr0_shift_x(BITJOIN,15343)@25
    assign rightShiftStage1Idx1_uid15344_dupName_25_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15342_dupName_25_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15337_dupName_25_i_unnamed_c_compstr0_shift_x(BITSELECT,15336)@25
    assign rightShiftStage0Idx1Rng1_uid15337_dupName_25_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_q[33:1];

    // rightShiftStage0Idx1_uid15339_dupName_25_i_unnamed_c_compstr0_shift_x(BITJOIN,15338)@25
    assign rightShiftStage0Idx1_uid15339_dupName_25_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15337_dupName_25_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26841_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x(BITSELECT,26840)@24
    assign leftShiftStage2Idx1Rng8_uid26841_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_in = leftShiftStage1_uid26839_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26841_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26841_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26842_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x(BITJOIN,26841)@24
    assign leftShiftStage2Idx1_uid26842_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26841_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26836_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x(BITSELECT,26835)@24
    assign leftShiftStage1Idx1Rng4_uid26836_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_in = leftShiftStage0_uid26834_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26836_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26836_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26837_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x(BITJOIN,26836)@24
    assign leftShiftStage1Idx1_uid26837_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26836_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26831_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x(BITSELECT,26830)@24
    assign leftShiftStage0Idx1Rng1_uid26831_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_6_c_compstr202_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26831_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26831_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26832_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x(BITJOIN,26831)@24
    assign leftShiftStage0Idx1_uid26832_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26831_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15285_dupName_21_i_unnamed_c_compstr0_shift_x(BITSELECT,15284)@23
    assign rightShiftStage2Idx1Rng8_uid15285_dupName_21_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15284_dupName_21_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15287_dupName_21_i_unnamed_c_compstr0_shift_x(BITJOIN,15286)@23
    assign rightShiftStage2Idx1_uid15287_dupName_21_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15285_dupName_21_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15280_dupName_21_i_unnamed_c_compstr0_shift_x(BITSELECT,15279)@23
    assign rightShiftStage1Idx1Rng4_uid15280_dupName_21_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15279_dupName_21_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15282_dupName_21_i_unnamed_c_compstr0_shift_x(BITJOIN,15281)@23
    assign rightShiftStage1Idx1_uid15282_dupName_21_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15280_dupName_21_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15275_dupName_21_i_unnamed_c_compstr0_shift_x(BITSELECT,15274)@23
    assign rightShiftStage0Idx1Rng1_uid15275_dupName_21_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_q[33:1];

    // rightShiftStage0Idx1_uid15277_dupName_21_i_unnamed_c_compstr0_shift_x(BITJOIN,15276)@23
    assign rightShiftStage0Idx1_uid15277_dupName_21_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15275_dupName_21_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26643_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x(BITSELECT,26642)@22
    assign leftShiftStage2Idx1Rng8_uid26643_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_in = leftShiftStage1_uid26641_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26643_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26643_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26644_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x(BITJOIN,26643)@22
    assign leftShiftStage2Idx1_uid26644_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26643_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26638_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x(BITSELECT,26637)@22
    assign leftShiftStage1Idx1Rng4_uid26638_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_in = leftShiftStage0_uid26636_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26638_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26638_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26639_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x(BITJOIN,26638)@22
    assign leftShiftStage1Idx1_uid26639_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26638_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26633_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x(BITSELECT,26632)@22
    assign leftShiftStage0Idx1Rng1_uid26633_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_5_c_compstr174_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26633_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26633_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26634_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x(BITJOIN,26633)@22
    assign leftShiftStage0Idx1_uid26634_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26633_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15223_dupName_17_i_unnamed_c_compstr0_shift_x(BITSELECT,15222)@21
    assign rightShiftStage2Idx1Rng8_uid15223_dupName_17_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15222_dupName_17_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15225_dupName_17_i_unnamed_c_compstr0_shift_x(BITJOIN,15224)@21
    assign rightShiftStage2Idx1_uid15225_dupName_17_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15223_dupName_17_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15218_dupName_17_i_unnamed_c_compstr0_shift_x(BITSELECT,15217)@21
    assign rightShiftStage1Idx1Rng4_uid15218_dupName_17_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15217_dupName_17_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15220_dupName_17_i_unnamed_c_compstr0_shift_x(BITJOIN,15219)@21
    assign rightShiftStage1Idx1_uid15220_dupName_17_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15218_dupName_17_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15213_dupName_17_i_unnamed_c_compstr0_shift_x(BITSELECT,15212)@21
    assign rightShiftStage0Idx1Rng1_uid15213_dupName_17_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_q[33:1];

    // rightShiftStage0Idx1_uid15215_dupName_17_i_unnamed_c_compstr0_shift_x(BITJOIN,15214)@21
    assign rightShiftStage0Idx1_uid15215_dupName_17_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15213_dupName_17_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26445_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x(BITSELECT,26444)@20
    assign leftShiftStage2Idx1Rng8_uid26445_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_in = leftShiftStage1_uid26443_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26445_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26445_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26446_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x(BITJOIN,26445)@20
    assign leftShiftStage2Idx1_uid26446_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26445_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26440_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x(BITSELECT,26439)@20
    assign leftShiftStage1Idx1Rng4_uid26440_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_in = leftShiftStage0_uid26438_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26440_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26440_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26441_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x(BITJOIN,26440)@20
    assign leftShiftStage1Idx1_uid26441_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26440_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26435_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x(BITSELECT,26434)@20
    assign leftShiftStage0Idx1Rng1_uid26435_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_4_c_compstr146_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26435_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26435_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26436_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x(BITJOIN,26435)@20
    assign leftShiftStage0Idx1_uid26436_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26435_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15161_dupName_13_i_unnamed_c_compstr0_shift_x(BITSELECT,15160)@19
    assign rightShiftStage2Idx1Rng8_uid15161_dupName_13_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15160_dupName_13_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15163_dupName_13_i_unnamed_c_compstr0_shift_x(BITJOIN,15162)@19
    assign rightShiftStage2Idx1_uid15163_dupName_13_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15161_dupName_13_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15156_dupName_13_i_unnamed_c_compstr0_shift_x(BITSELECT,15155)@19
    assign rightShiftStage1Idx1Rng4_uid15156_dupName_13_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15155_dupName_13_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15158_dupName_13_i_unnamed_c_compstr0_shift_x(BITJOIN,15157)@19
    assign rightShiftStage1Idx1_uid15158_dupName_13_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15156_dupName_13_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15151_dupName_13_i_unnamed_c_compstr0_shift_x(BITSELECT,15150)@19
    assign rightShiftStage0Idx1Rng1_uid15151_dupName_13_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_q[33:1];

    // rightShiftStage0Idx1_uid15153_dupName_13_i_unnamed_c_compstr0_shift_x(BITJOIN,15152)@19
    assign rightShiftStage0Idx1_uid15153_dupName_13_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15151_dupName_13_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26247_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x(BITSELECT,26246)@18
    assign leftShiftStage2Idx1Rng8_uid26247_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_in = leftShiftStage1_uid26245_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26247_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26247_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26248_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x(BITJOIN,26247)@18
    assign leftShiftStage2Idx1_uid26248_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26247_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26242_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x(BITSELECT,26241)@18
    assign leftShiftStage1Idx1Rng4_uid26242_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_in = leftShiftStage0_uid26240_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26242_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26242_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26243_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x(BITJOIN,26242)@18
    assign leftShiftStage1Idx1_uid26243_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26242_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26237_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x(BITSELECT,26236)@18
    assign leftShiftStage0Idx1Rng1_uid26237_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_3_c_compstr118_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26237_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26237_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26238_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x(BITJOIN,26237)@18
    assign leftShiftStage0Idx1_uid26238_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26237_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15099_dupName_9_i_unnamed_c_compstr0_shift_x(BITSELECT,15098)@17
    assign rightShiftStage2Idx1Rng8_uid15099_dupName_9_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15098_dupName_9_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15101_dupName_9_i_unnamed_c_compstr0_shift_x(BITJOIN,15100)@17
    assign rightShiftStage2Idx1_uid15101_dupName_9_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15099_dupName_9_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15094_dupName_9_i_unnamed_c_compstr0_shift_x(BITSELECT,15093)@17
    assign rightShiftStage1Idx1Rng4_uid15094_dupName_9_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15093_dupName_9_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15096_dupName_9_i_unnamed_c_compstr0_shift_x(BITJOIN,15095)@17
    assign rightShiftStage1Idx1_uid15096_dupName_9_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15094_dupName_9_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15089_dupName_9_i_unnamed_c_compstr0_shift_x(BITSELECT,15088)@17
    assign rightShiftStage0Idx1Rng1_uid15089_dupName_9_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_q[33:1];

    // rightShiftStage0Idx1_uid15091_dupName_9_i_unnamed_c_compstr0_shift_x(BITJOIN,15090)@17
    assign rightShiftStage0Idx1_uid15091_dupName_9_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15089_dupName_9_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26049_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x(BITSELECT,26048)@16
    assign leftShiftStage2Idx1Rng8_uid26049_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_in = leftShiftStage1_uid26047_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26049_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid26049_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26050_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x(BITJOIN,26049)@16
    assign leftShiftStage2Idx1_uid26050_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26049_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26044_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x(BITSELECT,26043)@16
    assign leftShiftStage1Idx1Rng4_uid26044_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_in = leftShiftStage0_uid26042_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26044_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid26044_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26045_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x(BITJOIN,26044)@16
    assign leftShiftStage1Idx1_uid26045_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26044_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26039_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x(BITSELECT,26038)@16
    assign leftShiftStage0Idx1Rng1_uid26039_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_2_c_compstr90_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26039_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid26039_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26040_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x(BITJOIN,26039)@16
    assign leftShiftStage0Idx1_uid26040_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26039_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15037_dupName_5_i_unnamed_c_compstr0_shift_x(BITSELECT,15036)@15
    assign rightShiftStage2Idx1Rng8_uid15037_dupName_5_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15036_dupName_5_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15039_dupName_5_i_unnamed_c_compstr0_shift_x(BITJOIN,15038)@15
    assign rightShiftStage2Idx1_uid15039_dupName_5_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15037_dupName_5_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15032_dupName_5_i_unnamed_c_compstr0_shift_x(BITSELECT,15031)@15
    assign rightShiftStage1Idx1Rng4_uid15032_dupName_5_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15031_dupName_5_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15034_dupName_5_i_unnamed_c_compstr0_shift_x(BITJOIN,15033)@15
    assign rightShiftStage1Idx1_uid15034_dupName_5_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15032_dupName_5_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15027_dupName_5_i_unnamed_c_compstr0_shift_x(BITSELECT,15026)@15
    assign rightShiftStage0Idx1Rng1_uid15027_dupName_5_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_q[33:1];

    // rightShiftStage0Idx1_uid15029_dupName_5_i_unnamed_c_compstr0_shift_x(BITJOIN,15028)@15
    assign rightShiftStage0Idx1_uid15029_dupName_5_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15027_dupName_5_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25851_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x(BITSELECT,25850)@14
    assign leftShiftStage2Idx1Rng8_uid25851_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_in = leftShiftStage1_uid25849_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25851_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25851_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25852_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x(BITJOIN,25851)@14
    assign leftShiftStage2Idx1_uid25852_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25851_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25846_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x(BITSELECT,25845)@14
    assign leftShiftStage1Idx1Rng4_uid25846_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_in = leftShiftStage0_uid25844_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25846_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25846_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25847_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x(BITJOIN,25846)@14
    assign leftShiftStage1Idx1_uid25847_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25846_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25841_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x(BITSELECT,25840)@14
    assign leftShiftStage0Idx1Rng1_uid25841_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_in = i_conv_i_i_i_i_i_i279_1_c_compstr62_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25841_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25841_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25842_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x(BITJOIN,25841)@14
    assign leftShiftStage0Idx1_uid25842_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25841_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid14975_dupName_1_i_unnamed_c_compstr0_shift_x(BITSELECT,14974)@14
    assign rightShiftStage2Idx1Rng8_uid14975_dupName_1_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid14974_dupName_1_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid14977_dupName_1_i_unnamed_c_compstr0_shift_x(BITJOIN,14976)@14
    assign rightShiftStage2Idx1_uid14977_dupName_1_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid14975_dupName_1_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid14970_dupName_1_i_unnamed_c_compstr0_shift_x(BITSELECT,14969)@14
    assign rightShiftStage1Idx1Rng4_uid14970_dupName_1_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid14969_dupName_1_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid14972_dupName_1_i_unnamed_c_compstr0_shift_x(BITJOIN,14971)@14
    assign rightShiftStage1Idx1_uid14972_dupName_1_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid14970_dupName_1_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid14965_dupName_1_i_unnamed_c_compstr0_shift_x(BITSELECT,14964)@14
    assign rightShiftStage0Idx1Rng1_uid14965_dupName_1_i_unnamed_c_compstr0_shift_x_b = i_conv_i_i_i_i_c_compstr36_sel_x_b[33:1];

    // rightShiftStage0Idx1_uid14967_dupName_1_i_unnamed_c_compstr0_shift_x(BITJOIN,14966)@14
    assign rightShiftStage0Idx1_uid14967_dupName_1_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid14965_dupName_1_i_unnamed_c_compstr0_shift_x_b};

    // valid_fanout_reg6(REG,12634)@3 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg6_q <= $unsigned(redist514_sync_together3657_aunroll_x_in_i_valid_3_q);
        end
    end

    // c_i64_46297004169368698883637(CONSTANT,6849)
    assign c_i64_46297004169368698883637_q = $unsigned(64'b0100000001000000000000000000000000000000000000000000000000000000);

    // i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x(BLACKBOX,4993)@4
    // out out_o_readdata_0_tpl@8
    // out out_o_readdata_1_tpl@8
    // out out_o_readdata_2_tpl@8
    // out out_o_readdata_3_tpl@8
    // out out_o_readdata_4_tpl@8
    // out out_o_readdata_5_tpl@8
    // out out_o_readdata_6_tpl@8
    // out out_o_readdata_7_tpl@8
    // out out_o_readdata_8_tpl@8
    // out out_o_readdata_9_tpl@8
    // out out_o_readdata_10_tpl@8
    // out out_o_readdata_11_tpl@8
    // out out_o_readdata_12_tpl@8
    // out out_o_readdata_13_tpl@8
    // out out_o_readdata_14_tpl@8
    // out out_o_readdata_15_tpl@8
    // out out_o_readdata_16_tpl@8
    // out out_o_readdata_17_tpl@8
    // out out_o_readdata_18_tpl@8
    // out out_o_readdata_19_tpl@8
    // out out_o_readdata_20_tpl@8
    // out out_o_readdata_21_tpl@8
    // out out_o_readdata_22_tpl@8
    // out out_o_readdata_23_tpl@8
    // out out_o_readdata_24_tpl@8
    // out out_o_readdata_25_tpl@8
    // out out_o_readdata_26_tpl@8
    // out out_o_readdata_27_tpl@8
    // out out_o_readdata_28_tpl@8
    // out out_o_readdata_29_tpl@8
    // out out_o_readdata_30_tpl@8
    // out out_o_readdata_31_tpl@8
    // out out_o_readdata_32_tpl@8
    // out out_o_readdata_33_tpl@8
    // out out_o_readdata_34_tpl@8
    // out out_o_readdata_35_tpl@8
    // out out_o_readdata_36_tpl@8
    // out out_o_readdata_37_tpl@8
    // out out_o_readdata_38_tpl@8
    // out out_o_readdata_39_tpl@8
    // out out_o_readdata_40_tpl@8
    // out out_o_readdata_41_tpl@8
    // out out_o_readdata_42_tpl@8
    // out out_o_readdata_43_tpl@8
    // out out_o_readdata_44_tpl@8
    // out out_o_readdata_45_tpl@8
    // out out_o_readdata_46_tpl@8
    // out out_o_readdata_47_tpl@8
    // out out_o_readdata_48_tpl@8
    // out out_o_readdata_49_tpl@8
    // out out_o_readdata_50_tpl@8
    // out out_o_readdata_51_tpl@8
    // out out_o_readdata_52_tpl@8
    // out out_o_readdata_53_tpl@8
    // out out_o_readdata_54_tpl@8
    // out out_o_readdata_55_tpl@8
    // out out_o_readdata_56_tpl@8
    // out out_o_readdata_57_tpl@8
    // out out_o_readdata_58_tpl@8
    // out out_o_readdata_59_tpl@8
    // out out_o_readdata_60_tpl@8
    // out out_o_readdata_61_tpl@8
    // out out_o_readdata_62_tpl@8
    // out out_o_readdata_63_tpl@8
    // out out_o_readdata_64_tpl@8
    // out out_o_readdata_65_tpl@8
    // out out_o_readdata_66_tpl@8
    // out out_o_readdata_67_tpl@8
    // out out_o_readdata_68_tpl@8
    // out out_o_readdata_69_tpl@8
    // out out_o_readdata_70_tpl@8
    // out out_o_readdata_71_tpl@8
    // out out_o_readdata_72_tpl@8
    // out out_o_readdata_73_tpl@8
    // out out_o_readdata_74_tpl@8
    // out out_o_readdata_75_tpl@8
    // out out_o_readdata_76_tpl@8
    // out out_o_readdata_77_tpl@8
    // out out_o_readdata_78_tpl@8
    // out out_o_readdata_79_tpl@8
    // out out_o_readdata_80_tpl@8
    // out out_o_readdata_81_tpl@8
    // out out_o_readdata_82_tpl@8
    // out out_o_readdata_83_tpl@8
    // out out_o_readdata_84_tpl@8
    // out out_o_readdata_85_tpl@8
    // out out_o_readdata_86_tpl@8
    // out out_o_readdata_87_tpl@8
    // out out_o_readdata_88_tpl@8
    // out out_o_readdata_89_tpl@8
    // out out_o_readdata_90_tpl@8
    // out out_o_readdata_91_tpl@8
    // out out_o_readdata_92_tpl@8
    // out out_o_readdata_93_tpl@8
    // out out_o_readdata_94_tpl@8
    // out out_o_readdata_95_tpl@8
    // out out_o_readdata_96_tpl@8
    // out out_o_readdata_97_tpl@8
    // out out_o_readdata_98_tpl@8
    // out out_o_readdata_99_tpl@8
    // out out_o_readdata_100_tpl@8
    // out out_o_readdata_101_tpl@8
    // out out_o_readdata_102_tpl@8
    // out out_o_readdata_103_tpl@8
    // out out_o_readdata_104_tpl@8
    // out out_o_readdata_105_tpl@8
    // out out_o_readdata_106_tpl@8
    // out out_o_readdata_107_tpl@8
    // out out_o_readdata_108_tpl@8
    // out out_o_readdata_109_tpl@8
    // out out_o_readdata_110_tpl@8
    // out out_o_readdata_111_tpl@8
    // out out_o_readdata_112_tpl@8
    // out out_o_readdata_113_tpl@8
    // out out_o_readdata_114_tpl@8
    // out out_o_readdata_115_tpl@8
    // out out_o_readdata_116_tpl@8
    // out out_o_readdata_117_tpl@8
    // out out_o_readdata_118_tpl@8
    // out out_o_readdata_119_tpl@8
    // out out_o_readdata_120_tpl@8
    // out out_o_readdata_121_tpl@8
    // out out_o_readdata_122_tpl@8
    // out out_o_readdata_123_tpl@8
    // out out_o_readdata_124_tpl@8
    // out out_o_readdata_125_tpl@8
    // out out_o_readdata_126_tpl@8
    // out out_o_readdata_127_tpl@8
    // out out_o_readdata_128_tpl@8
    // out out_o_readdata_129_tpl@8
    // out out_o_readdata_130_tpl@8
    // out out_o_readdata_131_tpl@8
    // out out_o_readdata_132_tpl@8
    // out out_o_readdata_133_tpl@8
    // out out_o_readdata_134_tpl@8
    // out out_o_readdata_135_tpl@8
    // out out_o_readdata_136_tpl@8
    // out out_o_readdata_137_tpl@8
    // out out_o_readdata_138_tpl@8
    // out out_o_readdata_139_tpl@8
    // out out_o_readdata_140_tpl@8
    // out out_o_readdata_141_tpl@8
    // out out_o_readdata_142_tpl@8
    // out out_o_readdata_143_tpl@8
    // out out_o_readdata_144_tpl@8
    // out out_o_readdata_145_tpl@8
    // out out_o_readdata_146_tpl@8
    // out out_o_readdata_147_tpl@8
    // out out_o_readdata_148_tpl@8
    // out out_o_readdata_149_tpl@8
    // out out_o_readdata_150_tpl@8
    // out out_o_readdata_151_tpl@8
    // out out_o_readdata_152_tpl@8
    // out out_o_readdata_153_tpl@8
    // out out_o_readdata_154_tpl@8
    // out out_o_readdata_155_tpl@8
    // out out_o_readdata_156_tpl@8
    // out out_o_readdata_157_tpl@8
    // out out_o_readdata_158_tpl@8
    // out out_o_readdata_159_tpl@8
    // out out_o_readdata_160_tpl@8
    // out out_o_readdata_161_tpl@8
    // out out_o_readdata_162_tpl@8
    // out out_o_readdata_163_tpl@8
    // out out_o_readdata_164_tpl@8
    // out out_o_readdata_165_tpl@8
    // out out_o_readdata_166_tpl@8
    // out out_o_readdata_167_tpl@8
    // out out_o_readdata_168_tpl@8
    // out out_o_readdata_169_tpl@8
    // out out_o_readdata_170_tpl@8
    // out out_o_readdata_171_tpl@8
    // out out_o_readdata_172_tpl@8
    // out out_o_readdata_173_tpl@8
    // out out_o_readdata_174_tpl@8
    // out out_o_readdata_175_tpl@8
    // out out_o_readdata_176_tpl@8
    // out out_o_readdata_177_tpl@8
    // out out_o_readdata_178_tpl@8
    // out out_o_readdata_179_tpl@8
    // out out_o_readdata_180_tpl@8
    // out out_o_readdata_181_tpl@8
    // out out_o_readdata_182_tpl@8
    // out out_o_readdata_183_tpl@8
    // out out_o_readdata_184_tpl@8
    // out out_o_readdata_185_tpl@8
    // out out_o_readdata_186_tpl@8
    // out out_o_readdata_187_tpl@8
    // out out_o_readdata_188_tpl@8
    // out out_o_readdata_189_tpl@8
    // out out_o_readdata_190_tpl@8
    // out out_o_readdata_191_tpl@8
    // out out_o_readdata_192_tpl@8
    // out out_o_readdata_193_tpl@8
    // out out_o_readdata_194_tpl@8
    // out out_o_readdata_195_tpl@8
    // out out_o_readdata_196_tpl@8
    // out out_o_readdata_197_tpl@8
    // out out_o_readdata_198_tpl@8
    // out out_o_readdata_199_tpl@8
    // out out_o_readdata_200_tpl@8
    // out out_o_readdata_201_tpl@8
    // out out_o_readdata_202_tpl@8
    // out out_o_readdata_203_tpl@8
    // out out_o_readdata_204_tpl@8
    // out out_o_readdata_205_tpl@8
    // out out_o_readdata_206_tpl@8
    // out out_o_readdata_207_tpl@8
    // out out_o_readdata_208_tpl@8
    // out out_o_readdata_209_tpl@8
    // out out_o_readdata_210_tpl@8
    // out out_o_readdata_211_tpl@8
    // out out_o_readdata_212_tpl@8
    // out out_o_readdata_213_tpl@8
    // out out_o_readdata_214_tpl@8
    // out out_o_readdata_215_tpl@8
    // out out_o_readdata_216_tpl@8
    // out out_o_readdata_217_tpl@8
    // out out_o_readdata_218_tpl@8
    // out out_o_readdata_219_tpl@8
    // out out_o_readdata_220_tpl@8
    // out out_o_readdata_221_tpl@8
    // out out_o_readdata_222_tpl@8
    // out out_o_readdata_223_tpl@8
    // out out_o_readdata_224_tpl@8
    // out out_o_readdata_225_tpl@8
    // out out_o_readdata_226_tpl@8
    // out out_o_readdata_227_tpl@8
    // out out_o_readdata_228_tpl@8
    // out out_o_readdata_229_tpl@8
    // out out_o_readdata_230_tpl@8
    // out out_o_readdata_231_tpl@8
    // out out_o_readdata_232_tpl@8
    // out out_o_readdata_233_tpl@8
    // out out_o_readdata_234_tpl@8
    // out out_o_readdata_235_tpl@8
    // out out_o_readdata_236_tpl@8
    // out out_o_readdata_237_tpl@8
    // out out_o_readdata_238_tpl@8
    // out out_o_readdata_239_tpl@8
    // out out_o_readdata_240_tpl@8
    // out out_o_readdata_241_tpl@8
    // out out_o_readdata_242_tpl@8
    // out out_o_readdata_243_tpl@8
    // out out_o_readdata_244_tpl@8
    // out out_o_readdata_245_tpl@8
    // out out_o_readdata_246_tpl@8
    // out out_o_readdata_247_tpl@8
    // out out_o_readdata_248_tpl@8
    // out out_o_readdata_249_tpl@8
    // out out_o_readdata_250_tpl@8
    // out out_o_readdata_251_tpl@8
    // out out_o_readdata_252_tpl@8
    // out out_o_readdata_253_tpl@8
    // out out_o_readdata_254_tpl@8
    // out out_o_readdata_255_tpl@8
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata@20000000
    // out out_o_almost_empty@8
    // out out_o_empty@8
    // out out_o_stall@8
    // out out_o_valid@8
    c_compSTR_i_llvm_fpga_mem_memcoalesce_lo0000ique_5126_c_compstr0 thei_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x (
        .in_almost_empty_in(GND_q),
        .in_empty_in(GND_q),
        .in_flush(in_flush),
        .in_i_address(c_i64_46297004169368698883637_q),
        .in_i_predicate(i_c_compstr_b7_current_iter_isspec_c_compstr5_q),
        .in_i_stall(GND_q),
        .in_i_valid(valid_fanout_reg6_q),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdata(in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdata),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdatavalid(in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdatavalid),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_waitrequest(in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_waitrequest),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writeack(in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writeack),
        .out_o_readdata_0_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_0_tpl),
        .out_o_readdata_1_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_1_tpl),
        .out_o_readdata_2_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_2_tpl),
        .out_o_readdata_3_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_3_tpl),
        .out_o_readdata_4_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_4_tpl),
        .out_o_readdata_5_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_5_tpl),
        .out_o_readdata_6_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl),
        .out_o_readdata_7_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl),
        .out_o_readdata_8_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl),
        .out_o_readdata_9_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl),
        .out_o_readdata_10_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl),
        .out_o_readdata_11_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl),
        .out_o_readdata_12_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl),
        .out_o_readdata_13_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl),
        .out_o_readdata_14_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl),
        .out_o_readdata_15_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl),
        .out_o_readdata_16_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl),
        .out_o_readdata_17_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl),
        .out_o_readdata_18_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl),
        .out_o_readdata_19_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl),
        .out_o_readdata_20_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl),
        .out_o_readdata_21_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl),
        .out_o_readdata_22_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl),
        .out_o_readdata_23_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl),
        .out_o_readdata_24_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl),
        .out_o_readdata_25_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl),
        .out_o_readdata_26_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl),
        .out_o_readdata_27_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl),
        .out_o_readdata_28_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl),
        .out_o_readdata_29_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl),
        .out_o_readdata_30_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl),
        .out_o_readdata_31_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl),
        .out_o_readdata_32_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl),
        .out_o_readdata_33_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl),
        .out_o_readdata_34_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl),
        .out_o_readdata_35_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl),
        .out_o_readdata_36_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl),
        .out_o_readdata_37_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl),
        .out_o_readdata_38_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl),
        .out_o_readdata_39_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl),
        .out_o_readdata_40_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl),
        .out_o_readdata_41_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl),
        .out_o_readdata_42_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl),
        .out_o_readdata_43_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl),
        .out_o_readdata_44_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl),
        .out_o_readdata_45_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl),
        .out_o_readdata_46_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl),
        .out_o_readdata_47_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl),
        .out_o_readdata_48_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl),
        .out_o_readdata_49_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl),
        .out_o_readdata_50_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl),
        .out_o_readdata_51_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl),
        .out_o_readdata_52_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl),
        .out_o_readdata_53_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl),
        .out_o_readdata_54_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl),
        .out_o_readdata_55_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl),
        .out_o_readdata_56_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl),
        .out_o_readdata_57_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl),
        .out_o_readdata_58_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl),
        .out_o_readdata_59_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl),
        .out_o_readdata_60_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl),
        .out_o_readdata_61_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl),
        .out_o_readdata_62_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl),
        .out_o_readdata_63_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl),
        .out_o_readdata_64_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl),
        .out_o_readdata_65_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl),
        .out_o_readdata_66_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl),
        .out_o_readdata_67_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl),
        .out_o_readdata_68_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl),
        .out_o_readdata_69_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl),
        .out_o_readdata_70_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl),
        .out_o_readdata_71_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl),
        .out_o_readdata_72_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl),
        .out_o_readdata_73_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl),
        .out_o_readdata_74_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl),
        .out_o_readdata_75_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl),
        .out_o_readdata_76_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl),
        .out_o_readdata_77_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl),
        .out_o_readdata_78_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl),
        .out_o_readdata_79_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl),
        .out_o_readdata_80_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl),
        .out_o_readdata_81_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl),
        .out_o_readdata_82_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl),
        .out_o_readdata_83_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl),
        .out_o_readdata_84_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl),
        .out_o_readdata_85_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl),
        .out_o_readdata_86_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl),
        .out_o_readdata_87_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl),
        .out_o_readdata_88_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl),
        .out_o_readdata_89_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl),
        .out_o_readdata_90_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl),
        .out_o_readdata_91_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl),
        .out_o_readdata_92_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl),
        .out_o_readdata_93_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl),
        .out_o_readdata_94_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl),
        .out_o_readdata_95_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl),
        .out_o_readdata_96_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl),
        .out_o_readdata_97_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl),
        .out_o_readdata_98_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl),
        .out_o_readdata_99_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl),
        .out_o_readdata_100_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl),
        .out_o_readdata_101_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl),
        .out_o_readdata_102_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl),
        .out_o_readdata_103_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl),
        .out_o_readdata_104_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl),
        .out_o_readdata_105_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl),
        .out_o_readdata_106_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl),
        .out_o_readdata_107_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl),
        .out_o_readdata_108_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl),
        .out_o_readdata_109_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl),
        .out_o_readdata_110_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl),
        .out_o_readdata_111_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl),
        .out_o_readdata_112_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl),
        .out_o_readdata_113_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl),
        .out_o_readdata_114_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl),
        .out_o_readdata_115_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl),
        .out_o_readdata_116_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl),
        .out_o_readdata_117_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl),
        .out_o_readdata_118_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl),
        .out_o_readdata_119_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl),
        .out_o_readdata_120_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl),
        .out_o_readdata_121_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl),
        .out_o_readdata_122_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl),
        .out_o_readdata_123_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl),
        .out_o_readdata_124_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl),
        .out_o_readdata_125_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl),
        .out_o_readdata_126_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl),
        .out_o_readdata_127_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl),
        .out_o_readdata_128_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl),
        .out_o_readdata_129_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl),
        .out_o_readdata_130_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl),
        .out_o_readdata_131_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl),
        .out_o_readdata_132_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl),
        .out_o_readdata_133_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl),
        .out_o_readdata_134_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl),
        .out_o_readdata_135_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl),
        .out_o_readdata_136_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl),
        .out_o_readdata_137_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl),
        .out_o_readdata_138_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl),
        .out_o_readdata_139_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl),
        .out_o_readdata_140_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl),
        .out_o_readdata_141_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl),
        .out_o_readdata_142_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl),
        .out_o_readdata_143_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl),
        .out_o_readdata_144_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl),
        .out_o_readdata_145_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl),
        .out_o_readdata_146_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl),
        .out_o_readdata_147_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl),
        .out_o_readdata_148_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl),
        .out_o_readdata_149_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl),
        .out_o_readdata_150_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl),
        .out_o_readdata_151_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl),
        .out_o_readdata_152_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl),
        .out_o_readdata_153_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl),
        .out_o_readdata_154_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl),
        .out_o_readdata_155_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl),
        .out_o_readdata_156_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl),
        .out_o_readdata_157_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl),
        .out_o_readdata_158_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl),
        .out_o_readdata_159_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl),
        .out_o_readdata_160_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl),
        .out_o_readdata_161_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl),
        .out_o_readdata_162_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl),
        .out_o_readdata_163_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl),
        .out_o_readdata_164_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl),
        .out_o_readdata_165_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl),
        .out_o_readdata_166_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl),
        .out_o_readdata_167_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl),
        .out_o_readdata_168_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl),
        .out_o_readdata_169_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl),
        .out_o_readdata_170_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl),
        .out_o_readdata_171_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl),
        .out_o_readdata_172_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl),
        .out_o_readdata_173_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl),
        .out_o_readdata_174_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl),
        .out_o_readdata_175_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl),
        .out_o_readdata_176_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl),
        .out_o_readdata_177_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl),
        .out_o_readdata_178_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl),
        .out_o_readdata_179_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl),
        .out_o_readdata_180_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl),
        .out_o_readdata_181_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl),
        .out_o_readdata_182_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl),
        .out_o_readdata_183_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl),
        .out_o_readdata_184_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl),
        .out_o_readdata_185_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl),
        .out_o_readdata_186_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl),
        .out_o_readdata_187_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl),
        .out_o_readdata_188_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl),
        .out_o_readdata_189_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl),
        .out_o_readdata_190_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl),
        .out_o_readdata_191_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl),
        .out_o_readdata_192_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl),
        .out_o_readdata_193_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl),
        .out_o_readdata_194_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl),
        .out_o_readdata_195_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl),
        .out_o_readdata_196_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl),
        .out_o_readdata_197_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl),
        .out_o_readdata_198_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl),
        .out_o_readdata_199_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl),
        .out_o_readdata_200_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl),
        .out_o_readdata_201_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl),
        .out_o_readdata_202_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl),
        .out_o_readdata_203_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl),
        .out_o_readdata_204_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl),
        .out_o_readdata_205_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl),
        .out_o_readdata_206_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl),
        .out_o_readdata_207_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl),
        .out_o_readdata_208_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl),
        .out_o_readdata_209_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl),
        .out_o_readdata_210_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl),
        .out_o_readdata_211_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl),
        .out_o_readdata_212_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl),
        .out_o_readdata_213_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl),
        .out_o_readdata_214_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl),
        .out_o_readdata_215_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl),
        .out_o_readdata_216_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl),
        .out_o_readdata_217_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl),
        .out_o_readdata_218_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl),
        .out_o_readdata_219_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl),
        .out_o_readdata_220_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl),
        .out_o_readdata_221_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl),
        .out_o_readdata_222_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl),
        .out_o_readdata_223_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl),
        .out_o_readdata_224_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl),
        .out_o_readdata_225_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl),
        .out_o_readdata_226_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl),
        .out_o_readdata_227_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl),
        .out_o_readdata_228_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl),
        .out_o_readdata_229_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl),
        .out_o_readdata_230_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl),
        .out_o_readdata_231_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl),
        .out_o_readdata_232_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl),
        .out_o_readdata_233_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl),
        .out_o_readdata_234_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl),
        .out_o_readdata_235_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl),
        .out_o_readdata_236_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl),
        .out_o_readdata_237_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl),
        .out_o_readdata_238_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl),
        .out_o_readdata_239_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl),
        .out_o_readdata_240_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl),
        .out_o_readdata_241_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl),
        .out_o_readdata_242_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl),
        .out_o_readdata_243_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl),
        .out_o_readdata_244_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl),
        .out_o_readdata_245_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl),
        .out_o_readdata_246_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl),
        .out_o_readdata_247_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl),
        .out_o_readdata_248_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl),
        .out_o_readdata_249_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl),
        .out_o_readdata_250_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl),
        .out_o_readdata_251_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl),
        .out_o_readdata_252_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl),
        .out_o_readdata_253_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl),
        .out_o_readdata_254_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl),
        .out_o_readdata_255_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata),
        .out_o_almost_empty(),
        .out_o_empty(),
        .out_o_stall(),
        .out_o_valid(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28098)@8 + 5
    // out q@14
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_0_tpl;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_0_tpl;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_1_tpl;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_1_tpl;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_conv_i_i_i_i_c_compstr36_sel_x(BITSELECT,3585)@14
    assign i_conv_i_i_i_i_c_compstr36_sel_x_b = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32:0]});

    // rightShiftStage0_uid14969_dupName_1_i_unnamed_c_compstr0_shift_x(MUX,14968)@14
    assign rightShiftStage0_uid14969_dupName_1_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid14969_dupName_1_i_unnamed_c_compstr0_shift_x_s or i_conv_i_i_i_i_c_compstr36_sel_x_b or rightShiftStage0Idx1_uid14967_dupName_1_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid14969_dupName_1_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid14969_dupName_1_i_unnamed_c_compstr0_shift_x_q = i_conv_i_i_i_i_c_compstr36_sel_x_b;
            1'b1 : rightShiftStage0_uid14969_dupName_1_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid14967_dupName_1_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid14969_dupName_1_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid14974_dupName_1_i_unnamed_c_compstr0_shift_x(MUX,14973)@14
    assign rightShiftStage1_uid14974_dupName_1_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid14974_dupName_1_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid14969_dupName_1_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid14972_dupName_1_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid14974_dupName_1_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid14974_dupName_1_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid14969_dupName_1_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid14974_dupName_1_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid14972_dupName_1_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid14974_dupName_1_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid14979_dupName_1_i_unnamed_c_compstr0_shift_x(MUX,14978)@14
    assign rightShiftStage2_uid14979_dupName_1_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid14979_dupName_1_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid14974_dupName_1_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid14977_dupName_1_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid14979_dupName_1_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid14979_dupName_1_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid14974_dupName_1_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid14979_dupName_1_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid14977_dupName_1_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid14979_dupName_1_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr37_vt_select_20(BITSELECT,12082)@14
    assign i_unnamed_c_compstr37_vt_select_20_b = rightShiftStage2_uid14979_dupName_1_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr37_vt_join(BITJOIN,12081)@14
    assign i_unnamed_c_compstr37_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr37_vt_select_20_b};

    // i_conv_i_i_i_i_i_c_compstr38_sel_x(BITSELECT,3840)@14
    assign i_conv_i_i_i_i_i_c_compstr38_sel_x_b = i_unnamed_c_compstr37_vt_join_q[15:0];

    // i_unnamed_c_compstr1005_vt_const_15(CONSTANT,9811)
    assign i_unnamed_c_compstr1005_vt_const_15_q = $unsigned(15'b000000000000000);

    // i_unnamed_c_compstr1003_vt_const_33(CONSTANT,9806)
    assign i_unnamed_c_compstr1003_vt_const_33_q = $unsigned(12'b000000000000);

    // rightShiftStage1Idx1Rng8_uid14988_dupName_2_i_unnamed_c_compstr0_shift_x(BITSELECT,14987)@14
    assign rightShiftStage1Idx1Rng8_uid14988_dupName_2_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid14987_dupName_2_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid14990_dupName_2_i_unnamed_c_compstr0_shift_x(BITJOIN,14989)@14
    assign rightShiftStage1Idx1_uid14990_dupName_2_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid14988_dupName_2_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid14983_dupName_2_i_unnamed_c_compstr0_shift_x(BITSELECT,14982)@14
    assign rightShiftStage0Idx1Rng4_uid14983_dupName_2_i_unnamed_c_compstr0_shift_x_b = i_conv_i_i_i_i_c_compstr36_sel_x_b[33:4];

    // rightShiftStage0Idx1_uid14985_dupName_2_i_unnamed_c_compstr0_shift_x(BITJOIN,14984)@14
    assign rightShiftStage0Idx1_uid14985_dupName_2_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid14983_dupName_2_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid14987_dupName_2_i_unnamed_c_compstr0_shift_x(MUX,14986)@14
    assign rightShiftStage0_uid14987_dupName_2_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid14987_dupName_2_i_unnamed_c_compstr0_shift_x_s or i_conv_i_i_i_i_c_compstr36_sel_x_b or rightShiftStage0Idx1_uid14985_dupName_2_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid14987_dupName_2_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid14987_dupName_2_i_unnamed_c_compstr0_shift_x_q = i_conv_i_i_i_i_c_compstr36_sel_x_b;
            1'b1 : rightShiftStage0_uid14987_dupName_2_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid14985_dupName_2_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid14987_dupName_2_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid14992_dupName_2_i_unnamed_c_compstr0_shift_x(MUX,14991)@14
    assign rightShiftStage1_uid14992_dupName_2_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid14992_dupName_2_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid14987_dupName_2_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid14990_dupName_2_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid14992_dupName_2_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid14992_dupName_2_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid14987_dupName_2_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid14992_dupName_2_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid14990_dupName_2_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid14992_dupName_2_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr39_vt_select_21(BITSELECT,12096)@14
    assign i_unnamed_c_compstr39_vt_select_21_b = rightShiftStage1_uid14992_dupName_2_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr39_vt_join(BITJOIN,12095)@14
    assign i_unnamed_c_compstr39_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr39_vt_select_21_b};

    // i_unnamed_c_compstr40_sel_x(BITSELECT,6243)@14
    assign i_unnamed_c_compstr40_sel_x_b = i_unnamed_c_compstr39_vt_join_q[15:0];

    // i_unnamed_c_compstr41_BitSelect_for_a(BITSELECT,27877)@14
    assign i_unnamed_c_compstr41_BitSelect_for_a_b = i_unnamed_c_compstr40_sel_x_b[0:0];

    // i_unnamed_c_compstr41_join(BITJOIN,27878)@14
    assign i_unnamed_c_compstr41_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr41_BitSelect_for_a_b};

    // i_unnamed_c_compstr41_vt_select_0(BITSELECT,12123)@14
    assign i_unnamed_c_compstr41_vt_select_0_b = i_unnamed_c_compstr41_join_q[0:0];

    // i_unnamed_c_compstr41_vt_join(BITJOIN,12122)@14
    assign i_unnamed_c_compstr41_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, i_unnamed_c_compstr41_vt_select_0_b};

    // i_add_i_i_i_i_i_i_c_compstr42(ADD,7107)@14
    assign i_add_i_i_i_i_i_i_c_compstr42_a = {1'b0, i_unnamed_c_compstr41_vt_join_q};
    assign i_add_i_i_i_i_i_i_c_compstr42_b = {1'b0, i_conv_i_i_i_i_i_c_compstr38_sel_x_b};
    assign i_add_i_i_i_i_i_i_c_compstr42_o = $unsigned(i_add_i_i_i_i_i_i_c_compstr42_a) + $unsigned(i_add_i_i_i_i_i_i_c_compstr42_b);
    assign i_add_i_i_i_i_i_i_c_compstr42_q = i_add_i_i_i_i_i_i_c_compstr42_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_c_compstr42_sel_x(BITSELECT,2301)@14
    assign bgTrunc_i_add_i_i_i_i_i_i_c_compstr42_sel_x_b = i_add_i_i_i_i_i_i_c_compstr42_q[15:0];

    // i_conv_i_i_i_i_i_i279_1_c_compstr62_sel_x(BITSELECT,3879)@14
    assign i_conv_i_i_i_i_i_i279_1_c_compstr62_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_c_compstr42_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_1_c_compstr62_vt_select_15(BITSELECT,8033)@14
    assign i_conv_i_i_i_i_i_i279_1_c_compstr62_vt_select_15_b = i_conv_i_i_i_i_i_i279_1_c_compstr62_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_1_c_compstr62_vt_join(BITJOIN,8032)@14
    assign i_conv_i_i_i_i_i_i279_1_c_compstr62_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_1_c_compstr62_vt_select_15_b};

    // leftShiftStage0_uid25844_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x(MUX,25843)@14
    assign leftShiftStage0_uid25844_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25844_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_1_c_compstr62_vt_join_q or leftShiftStage0Idx1_uid25842_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25844_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25844_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_1_c_compstr62_vt_join_q;
            1'b1 : leftShiftStage0_uid25844_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25842_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25844_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25849_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x(MUX,25848)@14
    assign leftShiftStage1_uid25849_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25849_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_s or leftShiftStage0_uid25844_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25847_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25849_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25849_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q = leftShiftStage0_uid25844_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25849_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25847_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25849_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25854_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x(MUX,25853)@14
    assign leftShiftStage2_uid25854_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25854_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_s or leftShiftStage1_uid25849_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25852_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25854_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25854_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q = leftShiftStage1_uid25849_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25854_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25852_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25854_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_1_c_compstr63_vt_select_28(BITSELECT,9538)@14
    assign i_shl_i_i_i_i_i_i_1_c_compstr63_vt_select_28_b = leftShiftStage2_uid25854_i_shl_i_i_i_i_i_i_1_c_compstr0_shift_x_q[28:13];

    // redist344_i_shl_i_i_i_i_i_i_1_c_compstr63_vt_select_28_b_1(DELAY,28572)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist344_i_shl_i_i_i_i_i_i_1_c_compstr63_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_1_c_compstr63_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_1_c_compstr63_vt_join(BITJOIN,9537)@15
    assign i_shl_i_i_i_i_i_i_1_c_compstr63_vt_join_q = {redist344_i_shl_i_i_i_i_i_i_1_c_compstr63_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist773_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_3_tpl_1(DELAY,29001)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist773_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_3_tpl_1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_3_tpl);
        end
    end

    // redist518_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_2_tpl_1(DELAY,28746)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist518_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_2_tpl_1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_2_tpl);
        end
    end

    // redist519_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_3_tpl_1(DELAY,28747)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist519_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_3_tpl_1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_3_tpl);
        end
    end

    // redist772_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_2_tpl_1(DELAY,29000)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist772_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_2_tpl_1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_2_tpl);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28045)@9 + 5
    // out q@15
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist772_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_2_tpl_1_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist518_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_2_tpl_1_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist519_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_3_tpl_1_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist773_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_3_tpl_1_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64(ADD,8560)@15
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod46_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_b = $unsigned({{5{i_shl_i_i_i_i_i_i_1_c_compstr63_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_1_c_compstr63_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_o[33:0];

    // rightShiftStage0_uid15031_dupName_5_i_unnamed_c_compstr0_shift_x(MUX,15030)@15
    assign rightShiftStage0_uid15031_dupName_5_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15031_dupName_5_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_q or rightShiftStage0Idx1_uid15029_dupName_5_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15031_dupName_5_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15031_dupName_5_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_q;
            1'b1 : rightShiftStage0_uid15031_dupName_5_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15029_dupName_5_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15031_dupName_5_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15036_dupName_5_i_unnamed_c_compstr0_shift_x(MUX,15035)@15
    assign rightShiftStage1_uid15036_dupName_5_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15036_dupName_5_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15031_dupName_5_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15034_dupName_5_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15036_dupName_5_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15036_dupName_5_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15031_dupName_5_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15036_dupName_5_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15034_dupName_5_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15036_dupName_5_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15041_dupName_5_i_unnamed_c_compstr0_shift_x(MUX,15040)@15
    assign rightShiftStage2_uid15041_dupName_5_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15041_dupName_5_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15036_dupName_5_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15039_dupName_5_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15041_dupName_5_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15041_dupName_5_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15036_dupName_5_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15041_dupName_5_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15039_dupName_5_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15041_dupName_5_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr65_vt_select_20(BITSELECT,12324)@15
    assign i_unnamed_c_compstr65_vt_select_20_b = rightShiftStage2_uid15041_dupName_5_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr65_vt_join(BITJOIN,12323)@15
    assign i_unnamed_c_compstr65_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr65_vt_select_20_b};

    // i_conv_i_i_i_i_i_1_c_compstr66_sel_x(BITSELECT,3751)@15
    assign i_conv_i_i_i_i_i_1_c_compstr66_sel_x_b = i_unnamed_c_compstr65_vt_join_q[15:0];

    // redist1114_i_conv_i_i_i_i_i_1_c_compstr66_sel_x_b_1(DELAY,29342)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1114_i_conv_i_i_i_i_i_1_c_compstr66_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_1_c_compstr66_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15050_dupName_6_i_unnamed_c_compstr0_shift_x(BITSELECT,15049)@15
    assign rightShiftStage1Idx1Rng8_uid15050_dupName_6_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15049_dupName_6_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15052_dupName_6_i_unnamed_c_compstr0_shift_x(BITJOIN,15051)@15
    assign rightShiftStage1Idx1_uid15052_dupName_6_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15050_dupName_6_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15045_dupName_6_i_unnamed_c_compstr0_shift_x(BITSELECT,15044)@15
    assign rightShiftStage0Idx1Rng4_uid15045_dupName_6_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_q[33:4];

    // rightShiftStage0Idx1_uid15047_dupName_6_i_unnamed_c_compstr0_shift_x(BITJOIN,15046)@15
    assign rightShiftStage0Idx1_uid15047_dupName_6_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15045_dupName_6_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15049_dupName_6_i_unnamed_c_compstr0_shift_x(MUX,15048)@15
    assign rightShiftStage0_uid15049_dupName_6_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15049_dupName_6_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_q or rightShiftStage0Idx1_uid15047_dupName_6_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15049_dupName_6_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15049_dupName_6_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compstr64_q;
            1'b1 : rightShiftStage0_uid15049_dupName_6_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15047_dupName_6_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15049_dupName_6_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15054_dupName_6_i_unnamed_c_compstr0_shift_x(MUX,15053)@15
    assign rightShiftStage1_uid15054_dupName_6_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15054_dupName_6_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15049_dupName_6_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15052_dupName_6_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15054_dupName_6_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15054_dupName_6_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15049_dupName_6_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15054_dupName_6_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15052_dupName_6_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15054_dupName_6_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr67_vt_select_21(BITSELECT,12338)@15
    assign i_unnamed_c_compstr67_vt_select_21_b = rightShiftStage1_uid15054_dupName_6_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr67_vt_join(BITJOIN,12337)@15
    assign i_unnamed_c_compstr67_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr67_vt_select_21_b};

    // i_unnamed_c_compstr68_sel_x(BITSELECT,6265)@15
    assign i_unnamed_c_compstr68_sel_x_b = i_unnamed_c_compstr67_vt_join_q[15:0];

    // i_unnamed_c_compstr69_BitSelect_for_a(BITSELECT,27921)@15
    assign i_unnamed_c_compstr69_BitSelect_for_a_b = i_unnamed_c_compstr68_sel_x_b[0:0];

    // i_unnamed_c_compstr69_join(BITJOIN,27922)@15
    assign i_unnamed_c_compstr69_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr69_BitSelect_for_a_b};

    // i_unnamed_c_compstr69_vt_select_0(BITSELECT,12365)@15
    assign i_unnamed_c_compstr69_vt_select_0_b = i_unnamed_c_compstr69_join_q[0:0];

    // redist25_i_unnamed_c_compstr69_vt_select_0_b_1(DELAY,28253)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist25_i_unnamed_c_compstr69_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr69_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr69_vt_join(BITJOIN,12364)@16
    assign i_unnamed_c_compstr69_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist25_i_unnamed_c_compstr69_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_1_c_compstr70(ADD,7018)@16
    assign i_add_i_i_i_i_i_i_1_c_compstr70_a = {1'b0, i_unnamed_c_compstr69_vt_join_q};
    assign i_add_i_i_i_i_i_i_1_c_compstr70_b = {1'b0, redist1114_i_conv_i_i_i_i_i_1_c_compstr66_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_1_c_compstr70_o = $unsigned(i_add_i_i_i_i_i_i_1_c_compstr70_a) + $unsigned(i_add_i_i_i_i_i_i_1_c_compstr70_b);
    assign i_add_i_i_i_i_i_i_1_c_compstr70_q = i_add_i_i_i_i_i_i_1_c_compstr70_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_1_c_compstr70_sel_x(BITSELECT,2212)@16
    assign bgTrunc_i_add_i_i_i_i_i_i_1_c_compstr70_sel_x_b = i_add_i_i_i_i_i_i_1_c_compstr70_q[15:0];

    // i_conv_i_i_i_i_i_i279_2_c_compstr90_sel_x(BITSELECT,3890)@16
    assign i_conv_i_i_i_i_i_i279_2_c_compstr90_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_1_c_compstr70_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_2_c_compstr90_vt_select_15(BITSELECT,8077)@16
    assign i_conv_i_i_i_i_i_i279_2_c_compstr90_vt_select_15_b = i_conv_i_i_i_i_i_i279_2_c_compstr90_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_2_c_compstr90_vt_join(BITJOIN,8076)@16
    assign i_conv_i_i_i_i_i_i279_2_c_compstr90_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_2_c_compstr90_vt_select_15_b};

    // leftShiftStage0_uid26042_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x(MUX,26041)@16
    assign leftShiftStage0_uid26042_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26042_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_2_c_compstr90_vt_join_q or leftShiftStage0Idx1_uid26040_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26042_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26042_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_2_c_compstr90_vt_join_q;
            1'b1 : leftShiftStage0_uid26042_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26040_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26042_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26047_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x(MUX,26046)@16
    assign leftShiftStage1_uid26047_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26047_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_s or leftShiftStage0_uid26042_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26045_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26047_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26047_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q = leftShiftStage0_uid26042_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26047_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26045_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26047_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26052_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x(MUX,26051)@16
    assign leftShiftStage2_uid26052_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26052_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_s or leftShiftStage1_uid26047_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26050_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26052_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26052_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q = leftShiftStage1_uid26047_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26052_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26050_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26052_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_2_c_compstr91_vt_select_28(BITSELECT,9571)@16
    assign i_shl_i_i_i_i_i_i_2_c_compstr91_vt_select_28_b = leftShiftStage2_uid26052_i_shl_i_i_i_i_i_i_2_c_compstr0_shift_x_q[28:13];

    // redist333_i_shl_i_i_i_i_i_i_2_c_compstr91_vt_select_28_b_1(DELAY,28561)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist333_i_shl_i_i_i_i_i_i_2_c_compstr91_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_2_c_compstr91_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_2_c_compstr91_vt_join(BITJOIN,9570)@17
    assign i_shl_i_i_i_i_i_i_2_c_compstr91_vt_join_q = {redist333_i_shl_i_i_i_i_i_i_2_c_compstr91_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist775_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_5_tpl_3(DELAY,29003)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist775_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_5_tpl_3_delay_0 <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_5_tpl);
            redist775_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_5_tpl_3_delay_1 <= redist775_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_5_tpl_3_delay_0;
            redist775_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_5_tpl_3_q <= redist775_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_5_tpl_3_delay_1;
        end
    end

    // redist520_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_4_tpl_3(DELAY,28748)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist520_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_4_tpl_3_delay_0 <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_4_tpl);
            redist520_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_4_tpl_3_delay_1 <= redist520_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_4_tpl_3_delay_0;
            redist520_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_4_tpl_3_q <= redist520_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_4_tpl_3_delay_1;
        end
    end

    // redist521_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_5_tpl_3(DELAY,28749)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist521_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_5_tpl_3_delay_0 <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_5_tpl);
            redist521_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_5_tpl_3_delay_1 <= redist521_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_5_tpl_3_delay_0;
            redist521_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_5_tpl_3_q <= redist521_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_5_tpl_3_delay_1;
        end
    end

    // redist774_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_4_tpl_3(DELAY,29002)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist774_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_4_tpl_3_delay_0 <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_4_tpl);
            redist774_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_4_tpl_3_delay_1 <= redist774_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_4_tpl_3_delay_0;
            redist774_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_4_tpl_3_q <= redist774_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_4_tpl_3_delay_1;
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28056)@11 + 5
    // out q@17
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist774_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_4_tpl_3_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist520_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_4_tpl_3_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist521_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_5_tpl_3_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist775_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_5_tpl_3_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92(ADD,8571)@17
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod51_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_b = $unsigned({{5{i_shl_i_i_i_i_i_i_2_c_compstr91_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_2_c_compstr91_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_o[33:0];

    // rightShiftStage0_uid15093_dupName_9_i_unnamed_c_compstr0_shift_x(MUX,15092)@17
    assign rightShiftStage0_uid15093_dupName_9_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15093_dupName_9_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_q or rightShiftStage0Idx1_uid15091_dupName_9_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15093_dupName_9_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15093_dupName_9_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_q;
            1'b1 : rightShiftStage0_uid15093_dupName_9_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15091_dupName_9_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15093_dupName_9_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15098_dupName_9_i_unnamed_c_compstr0_shift_x(MUX,15097)@17
    assign rightShiftStage1_uid15098_dupName_9_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15098_dupName_9_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15093_dupName_9_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15096_dupName_9_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15098_dupName_9_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15098_dupName_9_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15093_dupName_9_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15098_dupName_9_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15096_dupName_9_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15098_dupName_9_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15103_dupName_9_i_unnamed_c_compstr0_shift_x(MUX,15102)@17
    assign rightShiftStage2_uid15103_dupName_9_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15103_dupName_9_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15098_dupName_9_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15101_dupName_9_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15103_dupName_9_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15103_dupName_9_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15098_dupName_9_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15103_dupName_9_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15101_dupName_9_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15103_dupName_9_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr93_vt_select_20(BITSELECT,12566)@17
    assign i_unnamed_c_compstr93_vt_select_20_b = rightShiftStage2_uid15103_dupName_9_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr93_vt_join(BITJOIN,12565)@17
    assign i_unnamed_c_compstr93_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr93_vt_select_20_b};

    // i_conv_i_i_i_i_i_2_c_compstr94_sel_x(BITSELECT,3762)@17
    assign i_conv_i_i_i_i_i_2_c_compstr94_sel_x_b = i_unnamed_c_compstr93_vt_join_q[15:0];

    // redist1103_i_conv_i_i_i_i_i_2_c_compstr94_sel_x_b_1(DELAY,29331)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1103_i_conv_i_i_i_i_i_2_c_compstr94_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_2_c_compstr94_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15112_dupName_10_i_unnamed_c_compstr0_shift_x(BITSELECT,15111)@17
    assign rightShiftStage1Idx1Rng8_uid15112_dupName_10_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15111_dupName_10_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15114_dupName_10_i_unnamed_c_compstr0_shift_x(BITJOIN,15113)@17
    assign rightShiftStage1Idx1_uid15114_dupName_10_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15112_dupName_10_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15107_dupName_10_i_unnamed_c_compstr0_shift_x(BITSELECT,15106)@17
    assign rightShiftStage0Idx1Rng4_uid15107_dupName_10_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_q[33:4];

    // rightShiftStage0Idx1_uid15109_dupName_10_i_unnamed_c_compstr0_shift_x(BITJOIN,15108)@17
    assign rightShiftStage0Idx1_uid15109_dupName_10_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15107_dupName_10_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15111_dupName_10_i_unnamed_c_compstr0_shift_x(MUX,15110)@17
    assign rightShiftStage0_uid15111_dupName_10_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15111_dupName_10_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_q or rightShiftStage0Idx1_uid15109_dupName_10_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15111_dupName_10_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15111_dupName_10_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compstr92_q;
            1'b1 : rightShiftStage0_uid15111_dupName_10_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15109_dupName_10_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15111_dupName_10_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15116_dupName_10_i_unnamed_c_compstr0_shift_x(MUX,15115)@17
    assign rightShiftStage1_uid15116_dupName_10_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15116_dupName_10_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15111_dupName_10_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15114_dupName_10_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15116_dupName_10_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15116_dupName_10_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15111_dupName_10_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15116_dupName_10_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15114_dupName_10_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15116_dupName_10_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr95_vt_select_21(BITSELECT,12580)@17
    assign i_unnamed_c_compstr95_vt_select_21_b = rightShiftStage1_uid15116_dupName_10_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr95_vt_join(BITJOIN,12579)@17
    assign i_unnamed_c_compstr95_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr95_vt_select_21_b};

    // i_unnamed_c_compstr96_sel_x(BITSELECT,6287)@17
    assign i_unnamed_c_compstr96_sel_x_b = i_unnamed_c_compstr95_vt_join_q[15:0];

    // i_unnamed_c_compstr97_BitSelect_for_a(BITSELECT,27965)@17
    assign i_unnamed_c_compstr97_BitSelect_for_a_b = i_unnamed_c_compstr96_sel_x_b[0:0];

    // i_unnamed_c_compstr97_join(BITJOIN,27966)@17
    assign i_unnamed_c_compstr97_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr97_BitSelect_for_a_b};

    // i_unnamed_c_compstr97_vt_select_0(BITSELECT,12607)@17
    assign i_unnamed_c_compstr97_vt_select_0_b = i_unnamed_c_compstr97_join_q[0:0];

    // redist3_i_unnamed_c_compstr97_vt_select_0_b_1(DELAY,28231)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist3_i_unnamed_c_compstr97_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr97_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr97_vt_join(BITJOIN,12606)@18
    assign i_unnamed_c_compstr97_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist3_i_unnamed_c_compstr97_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_2_c_compstr98(ADD,7029)@18
    assign i_add_i_i_i_i_i_i_2_c_compstr98_a = {1'b0, i_unnamed_c_compstr97_vt_join_q};
    assign i_add_i_i_i_i_i_i_2_c_compstr98_b = {1'b0, redist1103_i_conv_i_i_i_i_i_2_c_compstr94_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_2_c_compstr98_o = $unsigned(i_add_i_i_i_i_i_i_2_c_compstr98_a) + $unsigned(i_add_i_i_i_i_i_i_2_c_compstr98_b);
    assign i_add_i_i_i_i_i_i_2_c_compstr98_q = i_add_i_i_i_i_i_i_2_c_compstr98_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_2_c_compstr98_sel_x(BITSELECT,2223)@18
    assign bgTrunc_i_add_i_i_i_i_i_i_2_c_compstr98_sel_x_b = i_add_i_i_i_i_i_i_2_c_compstr98_q[15:0];

    // i_conv_i_i_i_i_i_i279_3_c_compstr118_sel_x(BITSELECT,3901)@18
    assign i_conv_i_i_i_i_i_i279_3_c_compstr118_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_2_c_compstr98_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_3_c_compstr118_vt_select_15(BITSELECT,8121)@18
    assign i_conv_i_i_i_i_i_i279_3_c_compstr118_vt_select_15_b = i_conv_i_i_i_i_i_i279_3_c_compstr118_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_3_c_compstr118_vt_join(BITJOIN,8120)@18
    assign i_conv_i_i_i_i_i_i279_3_c_compstr118_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_3_c_compstr118_vt_select_15_b};

    // leftShiftStage0_uid26240_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x(MUX,26239)@18
    assign leftShiftStage0_uid26240_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26240_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_3_c_compstr118_vt_join_q or leftShiftStage0Idx1_uid26238_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26240_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26240_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_3_c_compstr118_vt_join_q;
            1'b1 : leftShiftStage0_uid26240_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26238_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26240_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26245_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x(MUX,26244)@18
    assign leftShiftStage1_uid26245_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26245_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_s or leftShiftStage0_uid26240_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26243_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26245_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26245_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q = leftShiftStage0_uid26240_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26245_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26243_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26245_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26250_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x(MUX,26249)@18
    assign leftShiftStage2_uid26250_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26250_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_s or leftShiftStage1_uid26245_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26248_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26250_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26250_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q = leftShiftStage1_uid26245_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26250_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26248_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26250_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_3_c_compstr119_vt_select_28(BITSELECT,9604)@18
    assign i_shl_i_i_i_i_i_i_3_c_compstr119_vt_select_28_b = leftShiftStage2_uid26250_i_shl_i_i_i_i_i_i_3_c_compstr0_shift_x_q[28:13];

    // redist322_i_shl_i_i_i_i_i_i_3_c_compstr119_vt_select_28_b_1(DELAY,28550)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist322_i_shl_i_i_i_i_i_i_3_c_compstr119_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_3_c_compstr119_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_3_c_compstr119_vt_join(BITJOIN,9603)@19
    assign i_shl_i_i_i_i_i_i_3_c_compstr119_vt_join_q = {redist322_i_shl_i_i_i_i_i_i_3_c_compstr119_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_inputreg0(DELAY,31072)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl);
        end
    end

    // redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5(DELAY,29005)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_delay_0 <= $unsigned(redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_inputreg0_q);
            redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_delay_1 <= redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_delay_0;
            redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_q <= redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_delay_1;
        end
    end

    // redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_outputreg0(DELAY,31073)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_outputreg0_q <= $unsigned(redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_q);
        end
    end

    // redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_inputreg0(DELAY,29628)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl);
        end
    end

    // redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5(DELAY,28750)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_delay_0 <= $unsigned(redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_inputreg0_q);
            redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_delay_1 <= redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_delay_0;
            redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_q <= redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_delay_1;
        end
    end

    // redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_outputreg0(DELAY,29629)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_outputreg0_q <= $unsigned(redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_q);
        end
    end

    // redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_inputreg0(DELAY,29630)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl);
        end
    end

    // redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5(DELAY,28751)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_delay_0 <= $unsigned(redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_inputreg0_q);
            redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_delay_1 <= redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_delay_0;
            redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_q <= redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_delay_1;
        end
    end

    // redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_outputreg0(DELAY,29631)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_outputreg0_q <= $unsigned(redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_q);
        end
    end

    // redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_inputreg0(DELAY,31070)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl);
        end
    end

    // redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5(DELAY,29004)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_delay_0 <= $unsigned(redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_inputreg0_q);
            redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_delay_1 <= redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_delay_0;
            redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_q <= redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_delay_1;
        end
    end

    // redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_outputreg0(DELAY,31071)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_outputreg0_q <= $unsigned(redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28067)@13 + 5
    // out q@19
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120(ADD,8582)@19
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod56_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_b = $unsigned({{5{i_shl_i_i_i_i_i_i_3_c_compstr119_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_3_c_compstr119_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_o[33:0];

    // rightShiftStage0_uid15155_dupName_13_i_unnamed_c_compstr0_shift_x(MUX,15154)@19
    assign rightShiftStage0_uid15155_dupName_13_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15155_dupName_13_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_q or rightShiftStage0Idx1_uid15153_dupName_13_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15155_dupName_13_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15155_dupName_13_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_q;
            1'b1 : rightShiftStage0_uid15155_dupName_13_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15153_dupName_13_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15155_dupName_13_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15160_dupName_13_i_unnamed_c_compstr0_shift_x(MUX,15159)@19
    assign rightShiftStage1_uid15160_dupName_13_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15160_dupName_13_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15155_dupName_13_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15158_dupName_13_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15160_dupName_13_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15160_dupName_13_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15155_dupName_13_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15160_dupName_13_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15158_dupName_13_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15160_dupName_13_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15165_dupName_13_i_unnamed_c_compstr0_shift_x(MUX,15164)@19
    assign rightShiftStage2_uid15165_dupName_13_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15165_dupName_13_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15160_dupName_13_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15163_dupName_13_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15165_dupName_13_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15165_dupName_13_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15160_dupName_13_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15165_dupName_13_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15163_dupName_13_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15165_dupName_13_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr121_vt_select_20(BITSELECT,9992)@19
    assign i_unnamed_c_compstr121_vt_select_20_b = rightShiftStage2_uid15165_dupName_13_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr121_vt_join(BITJOIN,9991)@19
    assign i_unnamed_c_compstr121_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr121_vt_select_20_b};

    // i_conv_i_i_i_i_i_3_c_compstr122_sel_x(BITSELECT,3773)@19
    assign i_conv_i_i_i_i_i_3_c_compstr122_sel_x_b = i_unnamed_c_compstr121_vt_join_q[15:0];

    // redist1092_i_conv_i_i_i_i_i_3_c_compstr122_sel_x_b_1(DELAY,29320)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1092_i_conv_i_i_i_i_i_3_c_compstr122_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_3_c_compstr122_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15174_dupName_14_i_unnamed_c_compstr0_shift_x(BITSELECT,15173)@19
    assign rightShiftStage1Idx1Rng8_uid15174_dupName_14_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15173_dupName_14_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15176_dupName_14_i_unnamed_c_compstr0_shift_x(BITJOIN,15175)@19
    assign rightShiftStage1Idx1_uid15176_dupName_14_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15174_dupName_14_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15169_dupName_14_i_unnamed_c_compstr0_shift_x(BITSELECT,15168)@19
    assign rightShiftStage0Idx1Rng4_uid15169_dupName_14_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_q[33:4];

    // rightShiftStage0Idx1_uid15171_dupName_14_i_unnamed_c_compstr0_shift_x(BITJOIN,15170)@19
    assign rightShiftStage0Idx1_uid15171_dupName_14_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15169_dupName_14_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15173_dupName_14_i_unnamed_c_compstr0_shift_x(MUX,15172)@19
    assign rightShiftStage0_uid15173_dupName_14_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15173_dupName_14_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_q or rightShiftStage0Idx1_uid15171_dupName_14_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15173_dupName_14_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15173_dupName_14_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compstr120_q;
            1'b1 : rightShiftStage0_uid15173_dupName_14_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15171_dupName_14_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15173_dupName_14_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15178_dupName_14_i_unnamed_c_compstr0_shift_x(MUX,15177)@19
    assign rightShiftStage1_uid15178_dupName_14_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15178_dupName_14_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15173_dupName_14_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15176_dupName_14_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15178_dupName_14_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15178_dupName_14_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15173_dupName_14_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15178_dupName_14_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15176_dupName_14_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15178_dupName_14_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr123_vt_select_21(BITSELECT,10006)@19
    assign i_unnamed_c_compstr123_vt_select_21_b = rightShiftStage1_uid15178_dupName_14_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr123_vt_join(BITJOIN,10005)@19
    assign i_unnamed_c_compstr123_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr123_vt_select_21_b};

    // i_unnamed_c_compstr124_sel_x(BITSELECT,6053)@19
    assign i_unnamed_c_compstr124_sel_x_b = i_unnamed_c_compstr123_vt_join_q[15:0];

    // i_unnamed_c_compstr125_BitSelect_for_a(BITSELECT,27497)@19
    assign i_unnamed_c_compstr125_BitSelect_for_a_b = i_unnamed_c_compstr124_sel_x_b[0:0];

    // i_unnamed_c_compstr125_join(BITJOIN,27498)@19
    assign i_unnamed_c_compstr125_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr125_BitSelect_for_a_b};

    // i_unnamed_c_compstr125_vt_select_0(BITSELECT,10033)@19
    assign i_unnamed_c_compstr125_vt_select_0_b = i_unnamed_c_compstr125_join_q[0:0];

    // redist235_i_unnamed_c_compstr125_vt_select_0_b_1(DELAY,28463)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist235_i_unnamed_c_compstr125_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr125_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr125_vt_join(BITJOIN,10032)@20
    assign i_unnamed_c_compstr125_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist235_i_unnamed_c_compstr125_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_3_c_compstr126(ADD,7040)@20
    assign i_add_i_i_i_i_i_i_3_c_compstr126_a = {1'b0, i_unnamed_c_compstr125_vt_join_q};
    assign i_add_i_i_i_i_i_i_3_c_compstr126_b = {1'b0, redist1092_i_conv_i_i_i_i_i_3_c_compstr122_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_3_c_compstr126_o = $unsigned(i_add_i_i_i_i_i_i_3_c_compstr126_a) + $unsigned(i_add_i_i_i_i_i_i_3_c_compstr126_b);
    assign i_add_i_i_i_i_i_i_3_c_compstr126_q = i_add_i_i_i_i_i_i_3_c_compstr126_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_3_c_compstr126_sel_x(BITSELECT,2234)@20
    assign bgTrunc_i_add_i_i_i_i_i_i_3_c_compstr126_sel_x_b = i_add_i_i_i_i_i_i_3_c_compstr126_q[15:0];

    // i_conv_i_i_i_i_i_i279_4_c_compstr146_sel_x(BITSELECT,3912)@20
    assign i_conv_i_i_i_i_i_i279_4_c_compstr146_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_3_c_compstr126_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_4_c_compstr146_vt_select_15(BITSELECT,8165)@20
    assign i_conv_i_i_i_i_i_i279_4_c_compstr146_vt_select_15_b = i_conv_i_i_i_i_i_i279_4_c_compstr146_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_4_c_compstr146_vt_join(BITJOIN,8164)@20
    assign i_conv_i_i_i_i_i_i279_4_c_compstr146_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_4_c_compstr146_vt_select_15_b};

    // leftShiftStage0_uid26438_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x(MUX,26437)@20
    assign leftShiftStage0_uid26438_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26438_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_4_c_compstr146_vt_join_q or leftShiftStage0Idx1_uid26436_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26438_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26438_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_4_c_compstr146_vt_join_q;
            1'b1 : leftShiftStage0_uid26438_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26436_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26438_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26443_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x(MUX,26442)@20
    assign leftShiftStage1_uid26443_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26443_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_s or leftShiftStage0_uid26438_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26441_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26443_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26443_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q = leftShiftStage0_uid26438_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26443_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26441_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26443_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26448_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x(MUX,26447)@20
    assign leftShiftStage2_uid26448_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26448_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_s or leftShiftStage1_uid26443_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26446_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26448_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26448_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q = leftShiftStage1_uid26443_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26448_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26446_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26448_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_4_c_compstr147_vt_select_28(BITSELECT,9637)@20
    assign i_shl_i_i_i_i_i_i_4_c_compstr147_vt_select_28_b = leftShiftStage2_uid26448_i_shl_i_i_i_i_i_i_4_c_compstr0_shift_x_q[28:13];

    // redist311_i_shl_i_i_i_i_i_i_4_c_compstr147_vt_select_28_b_1(DELAY,28539)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist311_i_shl_i_i_i_i_i_i_4_c_compstr147_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_4_c_compstr147_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_4_c_compstr147_vt_join(BITJOIN,9636)@21
    assign i_shl_i_i_i_i_i_i_4_c_compstr147_vt_join_q = {redist311_i_shl_i_i_i_i_i_i_4_c_compstr147_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_offset(CONSTANT,29636)
    assign redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_offset_q = $unsigned(2'b10);

    // redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_rdcnt(ADD,31085)
    assign redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_a = {1'b0, redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_wraddr_q};
    assign redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_b = {1'b0, redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_o <= $unsigned(redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_a) + $unsigned(redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_b);
        end
    end
    assign redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_q = redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_o[2:0];

    // redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_inputreg0(DELAY,31080)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl);
        end
    end

    // redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_wraddr(COUNTER,31083)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_wraddr_i <= $unsigned(redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_wraddr_q = redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_wraddr_i[1:0];

    // redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem(DUALMEM,31082)
    assign redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_ia = $unsigned(redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_inputreg0_q);
    assign redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_aa = redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_wraddr_q;
    assign redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_ab = redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_aa),
        .data_a(redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_ab),
        .q_b(redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_q = redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_iq[15:0];

    // redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_outputreg0(DELAY,31081)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_outputreg0_q <= $unsigned(redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_mem_q);
        end
    end

    // redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_rdcnt(ADD,29637)
    assign redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_a = {1'b0, redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_wraddr_q};
    assign redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_b = {1'b0, redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_o <= $unsigned(redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_a) + $unsigned(redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_b);
        end
    end
    assign redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_q = redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_o[2:0];

    // redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_inputreg0(DELAY,29632)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl);
        end
    end

    // redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_wraddr(COUNTER,29635)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_wraddr_i <= $unsigned(redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_wraddr_q = redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_wraddr_i[1:0];

    // redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem(DUALMEM,29634)
    assign redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_ia = $unsigned(redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_inputreg0_q);
    assign redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_aa = redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_wraddr_q;
    assign redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_ab = redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_aa),
        .data_a(redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_ab),
        .q_b(redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_q = redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_iq[15:0];

    // redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_outputreg0(DELAY,29633)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_outputreg0_q <= $unsigned(redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_mem_q);
        end
    end

    // redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_rdcnt(ADD,29643)
    assign redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_a = {1'b0, redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_wraddr_q};
    assign redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_b = {1'b0, redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_o <= $unsigned(redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_a) + $unsigned(redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_b);
        end
    end
    assign redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_q = redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_o[2:0];

    // redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_inputreg0(DELAY,29638)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl);
        end
    end

    // redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_wraddr(COUNTER,29641)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_wraddr_i <= $unsigned(redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_wraddr_q = redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_wraddr_i[1:0];

    // redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem(DUALMEM,29640)
    assign redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_ia = $unsigned(redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_inputreg0_q);
    assign redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_aa = redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_wraddr_q;
    assign redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_ab = redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_aa),
        .data_a(redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_ab),
        .q_b(redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_q = redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_iq[15:0];

    // redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_outputreg0(DELAY,29639)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_outputreg0_q <= $unsigned(redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_mem_q);
        end
    end

    // redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_rdcnt(ADD,31079)
    assign redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_a = {1'b0, redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_wraddr_q};
    assign redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_b = {1'b0, redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_o <= $unsigned(redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_a) + $unsigned(redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_b);
        end
    end
    assign redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_q = redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_o[2:0];

    // redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_inputreg0(DELAY,31074)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl);
        end
    end

    // redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_wraddr(COUNTER,31077)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_wraddr_i <= $unsigned(redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_wraddr_q = redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_wraddr_i[1:0];

    // redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem(DUALMEM,31076)
    assign redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_ia = $unsigned(redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_inputreg0_q);
    assign redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_aa = redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_wraddr_q;
    assign redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_ab = redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_aa),
        .data_a(redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_ab),
        .q_b(redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_q = redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_iq[15:0];

    // redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_outputreg0(DELAY,31075)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_outputreg0_q <= $unsigned(redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28078)@15 + 5
    // out q@21
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148(ADD,8593)@21
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod61_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_b = $unsigned({{5{i_shl_i_i_i_i_i_i_4_c_compstr147_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_4_c_compstr147_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_o[33:0];

    // rightShiftStage0_uid15217_dupName_17_i_unnamed_c_compstr0_shift_x(MUX,15216)@21
    assign rightShiftStage0_uid15217_dupName_17_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15217_dupName_17_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_q or rightShiftStage0Idx1_uid15215_dupName_17_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15217_dupName_17_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15217_dupName_17_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_q;
            1'b1 : rightShiftStage0_uid15217_dupName_17_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15215_dupName_17_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15217_dupName_17_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15222_dupName_17_i_unnamed_c_compstr0_shift_x(MUX,15221)@21
    assign rightShiftStage1_uid15222_dupName_17_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15222_dupName_17_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15217_dupName_17_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15220_dupName_17_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15222_dupName_17_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15222_dupName_17_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15217_dupName_17_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15222_dupName_17_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15220_dupName_17_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15222_dupName_17_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15227_dupName_17_i_unnamed_c_compstr0_shift_x(MUX,15226)@21
    assign rightShiftStage2_uid15227_dupName_17_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15227_dupName_17_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15222_dupName_17_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15225_dupName_17_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15227_dupName_17_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15227_dupName_17_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15222_dupName_17_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15227_dupName_17_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15225_dupName_17_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15227_dupName_17_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr149_vt_select_20(BITSELECT,10234)@21
    assign i_unnamed_c_compstr149_vt_select_20_b = rightShiftStage2_uid15227_dupName_17_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr149_vt_join(BITJOIN,10233)@21
    assign i_unnamed_c_compstr149_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr149_vt_select_20_b};

    // i_conv_i_i_i_i_i_4_c_compstr150_sel_x(BITSELECT,3784)@21
    assign i_conv_i_i_i_i_i_4_c_compstr150_sel_x_b = i_unnamed_c_compstr149_vt_join_q[15:0];

    // redist1081_i_conv_i_i_i_i_i_4_c_compstr150_sel_x_b_1(DELAY,29309)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1081_i_conv_i_i_i_i_i_4_c_compstr150_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_4_c_compstr150_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15236_dupName_18_i_unnamed_c_compstr0_shift_x(BITSELECT,15235)@21
    assign rightShiftStage1Idx1Rng8_uid15236_dupName_18_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15235_dupName_18_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15238_dupName_18_i_unnamed_c_compstr0_shift_x(BITJOIN,15237)@21
    assign rightShiftStage1Idx1_uid15238_dupName_18_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15236_dupName_18_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15231_dupName_18_i_unnamed_c_compstr0_shift_x(BITSELECT,15230)@21
    assign rightShiftStage0Idx1Rng4_uid15231_dupName_18_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_q[33:4];

    // rightShiftStage0Idx1_uid15233_dupName_18_i_unnamed_c_compstr0_shift_x(BITJOIN,15232)@21
    assign rightShiftStage0Idx1_uid15233_dupName_18_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15231_dupName_18_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15235_dupName_18_i_unnamed_c_compstr0_shift_x(MUX,15234)@21
    assign rightShiftStage0_uid15235_dupName_18_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15235_dupName_18_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_q or rightShiftStage0Idx1_uid15233_dupName_18_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15235_dupName_18_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15235_dupName_18_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compstr148_q;
            1'b1 : rightShiftStage0_uid15235_dupName_18_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15233_dupName_18_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15235_dupName_18_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15240_dupName_18_i_unnamed_c_compstr0_shift_x(MUX,15239)@21
    assign rightShiftStage1_uid15240_dupName_18_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15240_dupName_18_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15235_dupName_18_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15238_dupName_18_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15240_dupName_18_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15240_dupName_18_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15235_dupName_18_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15240_dupName_18_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15238_dupName_18_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15240_dupName_18_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr151_vt_select_21(BITSELECT,10248)@21
    assign i_unnamed_c_compstr151_vt_select_21_b = rightShiftStage1_uid15240_dupName_18_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr151_vt_join(BITJOIN,10247)@21
    assign i_unnamed_c_compstr151_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr151_vt_select_21_b};

    // i_unnamed_c_compstr152_sel_x(BITSELECT,6075)@21
    assign i_unnamed_c_compstr152_sel_x_b = i_unnamed_c_compstr151_vt_join_q[15:0];

    // i_unnamed_c_compstr153_BitSelect_for_a(BITSELECT,27541)@21
    assign i_unnamed_c_compstr153_BitSelect_for_a_b = i_unnamed_c_compstr152_sel_x_b[0:0];

    // i_unnamed_c_compstr153_join(BITJOIN,27542)@21
    assign i_unnamed_c_compstr153_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr153_BitSelect_for_a_b};

    // i_unnamed_c_compstr153_vt_select_0(BITSELECT,10275)@21
    assign i_unnamed_c_compstr153_vt_select_0_b = i_unnamed_c_compstr153_join_q[0:0];

    // redist213_i_unnamed_c_compstr153_vt_select_0_b_1(DELAY,28441)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist213_i_unnamed_c_compstr153_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr153_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr153_vt_join(BITJOIN,10274)@22
    assign i_unnamed_c_compstr153_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist213_i_unnamed_c_compstr153_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_4_c_compstr154(ADD,7051)@22
    assign i_add_i_i_i_i_i_i_4_c_compstr154_a = {1'b0, i_unnamed_c_compstr153_vt_join_q};
    assign i_add_i_i_i_i_i_i_4_c_compstr154_b = {1'b0, redist1081_i_conv_i_i_i_i_i_4_c_compstr150_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_4_c_compstr154_o = $unsigned(i_add_i_i_i_i_i_i_4_c_compstr154_a) + $unsigned(i_add_i_i_i_i_i_i_4_c_compstr154_b);
    assign i_add_i_i_i_i_i_i_4_c_compstr154_q = i_add_i_i_i_i_i_i_4_c_compstr154_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_4_c_compstr154_sel_x(BITSELECT,2245)@22
    assign bgTrunc_i_add_i_i_i_i_i_i_4_c_compstr154_sel_x_b = i_add_i_i_i_i_i_i_4_c_compstr154_q[15:0];

    // i_conv_i_i_i_i_i_i279_5_c_compstr174_sel_x(BITSELECT,3923)@22
    assign i_conv_i_i_i_i_i_i279_5_c_compstr174_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_4_c_compstr154_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_5_c_compstr174_vt_select_15(BITSELECT,8209)@22
    assign i_conv_i_i_i_i_i_i279_5_c_compstr174_vt_select_15_b = i_conv_i_i_i_i_i_i279_5_c_compstr174_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_5_c_compstr174_vt_join(BITJOIN,8208)@22
    assign i_conv_i_i_i_i_i_i279_5_c_compstr174_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_5_c_compstr174_vt_select_15_b};

    // leftShiftStage0_uid26636_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x(MUX,26635)@22
    assign leftShiftStage0_uid26636_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26636_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_5_c_compstr174_vt_join_q or leftShiftStage0Idx1_uid26634_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26636_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26636_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_5_c_compstr174_vt_join_q;
            1'b1 : leftShiftStage0_uid26636_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26634_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26636_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26641_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x(MUX,26640)@22
    assign leftShiftStage1_uid26641_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26641_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_s or leftShiftStage0_uid26636_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26639_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26641_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26641_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q = leftShiftStage0_uid26636_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26641_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26639_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26641_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26646_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x(MUX,26645)@22
    assign leftShiftStage2_uid26646_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26646_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_s or leftShiftStage1_uid26641_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26644_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26646_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26646_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q = leftShiftStage1_uid26641_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26646_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26644_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26646_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_5_c_compstr175_vt_select_28(BITSELECT,9670)@22
    assign i_shl_i_i_i_i_i_i_5_c_compstr175_vt_select_28_b = leftShiftStage2_uid26646_i_shl_i_i_i_i_i_i_5_c_compstr0_shift_x_q[28:13];

    // redist300_i_shl_i_i_i_i_i_i_5_c_compstr175_vt_select_28_b_1(DELAY,28528)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist300_i_shl_i_i_i_i_i_i_5_c_compstr175_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_5_c_compstr175_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_5_c_compstr175_vt_join(BITJOIN,9669)@23
    assign i_shl_i_i_i_i_i_i_5_c_compstr175_vt_join_q = {redist300_i_shl_i_i_i_i_i_i_5_c_compstr175_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_offset(CONSTANT,29648)
    assign redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_offset_q = $unsigned(3'b100);

    // redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_rdcnt(ADD,31097)
    assign redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_a = {1'b0, redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_wraddr_q};
    assign redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_b = {1'b0, redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_o <= $unsigned(redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_a) + $unsigned(redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_b);
        end
    end
    assign redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_q = redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_o[3:0];

    // redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_inputreg0(DELAY,31092)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl);
        end
    end

    // redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_wraddr(COUNTER,31095)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_wraddr_i <= $unsigned(redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_wraddr_q = redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_wraddr_i[2:0];

    // redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem(DUALMEM,31094)
    assign redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_ia = $unsigned(redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_inputreg0_q);
    assign redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_aa = redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_wraddr_q;
    assign redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_ab = redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_aa),
        .data_a(redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_ab),
        .q_b(redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_q = redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_iq[15:0];

    // redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_outputreg0(DELAY,31093)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_outputreg0_q <= $unsigned(redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_mem_q);
        end
    end

    // redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_rdcnt(ADD,29649)
    assign redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_a = {1'b0, redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_wraddr_q};
    assign redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_b = {1'b0, redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_o <= $unsigned(redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_a) + $unsigned(redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_b);
        end
    end
    assign redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_q = redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_o[3:0];

    // redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_inputreg0(DELAY,29644)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl);
        end
    end

    // redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_wraddr(COUNTER,29647)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_wraddr_i <= $unsigned(redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_wraddr_q = redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_wraddr_i[2:0];

    // redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem(DUALMEM,29646)
    assign redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_ia = $unsigned(redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_inputreg0_q);
    assign redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_aa = redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_wraddr_q;
    assign redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_ab = redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_aa),
        .data_a(redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_ab),
        .q_b(redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_q = redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_iq[15:0];

    // redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_outputreg0(DELAY,29645)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_outputreg0_q <= $unsigned(redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_mem_q);
        end
    end

    // redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_rdcnt(ADD,29655)
    assign redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_a = {1'b0, redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_wraddr_q};
    assign redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_b = {1'b0, redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_o <= $unsigned(redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_a) + $unsigned(redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_b);
        end
    end
    assign redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_q = redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_o[3:0];

    // redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_inputreg0(DELAY,29650)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl);
        end
    end

    // redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_wraddr(COUNTER,29653)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_wraddr_i <= $unsigned(redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_wraddr_q = redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_wraddr_i[2:0];

    // redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem(DUALMEM,29652)
    assign redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_ia = $unsigned(redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_inputreg0_q);
    assign redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_aa = redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_wraddr_q;
    assign redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_ab = redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_aa),
        .data_a(redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_ab),
        .q_b(redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_q = redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_iq[15:0];

    // redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_outputreg0(DELAY,29651)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_outputreg0_q <= $unsigned(redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_mem_q);
        end
    end

    // redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_rdcnt(ADD,31091)
    assign redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_a = {1'b0, redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_wraddr_q};
    assign redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_b = {1'b0, redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_o <= $unsigned(redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_a) + $unsigned(redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_b);
        end
    end
    assign redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_q = redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_o[3:0];

    // redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_inputreg0(DELAY,31086)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl);
        end
    end

    // redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_wraddr(COUNTER,31089)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_wraddr_i <= $unsigned(redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_wraddr_q = redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_wraddr_i[2:0];

    // redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem(DUALMEM,31088)
    assign redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_ia = $unsigned(redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_inputreg0_q);
    assign redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_aa = redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_wraddr_q;
    assign redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_ab = redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_aa),
        .data_a(redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_ab),
        .q_b(redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_q = redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_iq[15:0];

    // redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_outputreg0(DELAY,31087)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_outputreg0_q <= $unsigned(redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28089)@17 + 5
    // out q@23
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176(ADD,8604)@23
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod66_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_b = $unsigned({{5{i_shl_i_i_i_i_i_i_5_c_compstr175_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_5_c_compstr175_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_o[33:0];

    // rightShiftStage0_uid15279_dupName_21_i_unnamed_c_compstr0_shift_x(MUX,15278)@23
    assign rightShiftStage0_uid15279_dupName_21_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15279_dupName_21_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_q or rightShiftStage0Idx1_uid15277_dupName_21_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15279_dupName_21_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15279_dupName_21_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_q;
            1'b1 : rightShiftStage0_uid15279_dupName_21_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15277_dupName_21_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15279_dupName_21_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15284_dupName_21_i_unnamed_c_compstr0_shift_x(MUX,15283)@23
    assign rightShiftStage1_uid15284_dupName_21_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15284_dupName_21_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15279_dupName_21_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15282_dupName_21_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15284_dupName_21_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15284_dupName_21_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15279_dupName_21_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15284_dupName_21_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15282_dupName_21_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15284_dupName_21_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15289_dupName_21_i_unnamed_c_compstr0_shift_x(MUX,15288)@23
    assign rightShiftStage2_uid15289_dupName_21_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15289_dupName_21_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15284_dupName_21_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15287_dupName_21_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15289_dupName_21_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15289_dupName_21_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15284_dupName_21_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15289_dupName_21_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15287_dupName_21_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15289_dupName_21_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr177_vt_select_20(BITSELECT,10476)@23
    assign i_unnamed_c_compstr177_vt_select_20_b = rightShiftStage2_uid15289_dupName_21_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr177_vt_join(BITJOIN,10475)@23
    assign i_unnamed_c_compstr177_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr177_vt_select_20_b};

    // i_conv_i_i_i_i_i_5_c_compstr178_sel_x(BITSELECT,3795)@23
    assign i_conv_i_i_i_i_i_5_c_compstr178_sel_x_b = i_unnamed_c_compstr177_vt_join_q[15:0];

    // redist1070_i_conv_i_i_i_i_i_5_c_compstr178_sel_x_b_1(DELAY,29298)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1070_i_conv_i_i_i_i_i_5_c_compstr178_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_5_c_compstr178_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15298_dupName_22_i_unnamed_c_compstr0_shift_x(BITSELECT,15297)@23
    assign rightShiftStage1Idx1Rng8_uid15298_dupName_22_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15297_dupName_22_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15300_dupName_22_i_unnamed_c_compstr0_shift_x(BITJOIN,15299)@23
    assign rightShiftStage1Idx1_uid15300_dupName_22_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15298_dupName_22_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15293_dupName_22_i_unnamed_c_compstr0_shift_x(BITSELECT,15292)@23
    assign rightShiftStage0Idx1Rng4_uid15293_dupName_22_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_q[33:4];

    // rightShiftStage0Idx1_uid15295_dupName_22_i_unnamed_c_compstr0_shift_x(BITJOIN,15294)@23
    assign rightShiftStage0Idx1_uid15295_dupName_22_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15293_dupName_22_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15297_dupName_22_i_unnamed_c_compstr0_shift_x(MUX,15296)@23
    assign rightShiftStage0_uid15297_dupName_22_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15297_dupName_22_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_q or rightShiftStage0Idx1_uid15295_dupName_22_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15297_dupName_22_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15297_dupName_22_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compstr176_q;
            1'b1 : rightShiftStage0_uid15297_dupName_22_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15295_dupName_22_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15297_dupName_22_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15302_dupName_22_i_unnamed_c_compstr0_shift_x(MUX,15301)@23
    assign rightShiftStage1_uid15302_dupName_22_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15302_dupName_22_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15297_dupName_22_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15300_dupName_22_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15302_dupName_22_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15302_dupName_22_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15297_dupName_22_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15302_dupName_22_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15300_dupName_22_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15302_dupName_22_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr179_vt_select_21(BITSELECT,10490)@23
    assign i_unnamed_c_compstr179_vt_select_21_b = rightShiftStage1_uid15302_dupName_22_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr179_vt_join(BITJOIN,10489)@23
    assign i_unnamed_c_compstr179_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr179_vt_select_21_b};

    // i_unnamed_c_compstr180_sel_x(BITSELECT,6097)@23
    assign i_unnamed_c_compstr180_sel_x_b = i_unnamed_c_compstr179_vt_join_q[15:0];

    // i_unnamed_c_compstr181_BitSelect_for_a(BITSELECT,27585)@23
    assign i_unnamed_c_compstr181_BitSelect_for_a_b = i_unnamed_c_compstr180_sel_x_b[0:0];

    // i_unnamed_c_compstr181_join(BITJOIN,27586)@23
    assign i_unnamed_c_compstr181_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr181_BitSelect_for_a_b};

    // i_unnamed_c_compstr181_vt_select_0(BITSELECT,10517)@23
    assign i_unnamed_c_compstr181_vt_select_0_b = i_unnamed_c_compstr181_join_q[0:0];

    // redist191_i_unnamed_c_compstr181_vt_select_0_b_1(DELAY,28419)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist191_i_unnamed_c_compstr181_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr181_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr181_vt_join(BITJOIN,10516)@24
    assign i_unnamed_c_compstr181_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist191_i_unnamed_c_compstr181_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_5_c_compstr182(ADD,7062)@24
    assign i_add_i_i_i_i_i_i_5_c_compstr182_a = {1'b0, i_unnamed_c_compstr181_vt_join_q};
    assign i_add_i_i_i_i_i_i_5_c_compstr182_b = {1'b0, redist1070_i_conv_i_i_i_i_i_5_c_compstr178_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_5_c_compstr182_o = $unsigned(i_add_i_i_i_i_i_i_5_c_compstr182_a) + $unsigned(i_add_i_i_i_i_i_i_5_c_compstr182_b);
    assign i_add_i_i_i_i_i_i_5_c_compstr182_q = i_add_i_i_i_i_i_i_5_c_compstr182_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_5_c_compstr182_sel_x(BITSELECT,2256)@24
    assign bgTrunc_i_add_i_i_i_i_i_i_5_c_compstr182_sel_x_b = i_add_i_i_i_i_i_i_5_c_compstr182_q[15:0];

    // i_conv_i_i_i_i_i_i279_6_c_compstr202_sel_x(BITSELECT,3934)@24
    assign i_conv_i_i_i_i_i_i279_6_c_compstr202_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_5_c_compstr182_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_6_c_compstr202_vt_select_15(BITSELECT,8253)@24
    assign i_conv_i_i_i_i_i_i279_6_c_compstr202_vt_select_15_b = i_conv_i_i_i_i_i_i279_6_c_compstr202_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_6_c_compstr202_vt_join(BITJOIN,8252)@24
    assign i_conv_i_i_i_i_i_i279_6_c_compstr202_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_6_c_compstr202_vt_select_15_b};

    // leftShiftStage0_uid26834_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x(MUX,26833)@24
    assign leftShiftStage0_uid26834_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26834_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_6_c_compstr202_vt_join_q or leftShiftStage0Idx1_uid26832_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26834_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26834_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_6_c_compstr202_vt_join_q;
            1'b1 : leftShiftStage0_uid26834_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26832_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26834_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26839_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x(MUX,26838)@24
    assign leftShiftStage1_uid26839_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26839_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_s or leftShiftStage0_uid26834_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26837_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26839_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26839_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q = leftShiftStage0_uid26834_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26839_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26837_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26839_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26844_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x(MUX,26843)@24
    assign leftShiftStage2_uid26844_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26844_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_s or leftShiftStage1_uid26839_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26842_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26844_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26844_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q = leftShiftStage1_uid26839_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26844_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26842_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26844_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_6_c_compstr203_vt_select_28(BITSELECT,9703)@24
    assign i_shl_i_i_i_i_i_i_6_c_compstr203_vt_select_28_b = leftShiftStage2_uid26844_i_shl_i_i_i_i_i_i_6_c_compstr0_shift_x_q[28:13];

    // redist289_i_shl_i_i_i_i_i_i_6_c_compstr203_vt_select_28_b_1(DELAY,28517)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist289_i_shl_i_i_i_i_i_i_6_c_compstr203_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_6_c_compstr203_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_6_c_compstr203_vt_join(BITJOIN,9702)@25
    assign i_shl_i_i_i_i_i_i_6_c_compstr203_vt_join_q = {redist289_i_shl_i_i_i_i_i_i_6_c_compstr203_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_offset(CONSTANT,29660)
    assign redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_offset_q = $unsigned(3'b010);

    // redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_rdcnt(ADD,31109)
    assign redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_a = {1'b0, redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_wraddr_q};
    assign redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_b = {1'b0, redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_o <= $unsigned(redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_a) + $unsigned(redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_b);
        end
    end
    assign redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_q = redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_o[3:0];

    // redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_inputreg0(DELAY,31104)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl);
        end
    end

    // redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_wraddr(COUNTER,31107)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_wraddr_i <= $unsigned(redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_wraddr_q = redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_wraddr_i[2:0];

    // redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem(DUALMEM,31106)
    assign redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_ia = $unsigned(redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_inputreg0_q);
    assign redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_aa = redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_wraddr_q;
    assign redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_ab = redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_aa),
        .data_a(redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_ab),
        .q_b(redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_q = redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_iq[15:0];

    // redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_outputreg0(DELAY,31105)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_outputreg0_q <= $unsigned(redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_mem_q);
        end
    end

    // redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_rdcnt(ADD,29661)
    assign redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_a = {1'b0, redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_wraddr_q};
    assign redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_b = {1'b0, redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_o <= $unsigned(redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_a) + $unsigned(redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_b);
        end
    end
    assign redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_q = redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_o[3:0];

    // redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_inputreg0(DELAY,29656)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl);
        end
    end

    // redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_wraddr(COUNTER,29659)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_wraddr_i <= $unsigned(redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_wraddr_q = redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_wraddr_i[2:0];

    // redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem(DUALMEM,29658)
    assign redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_ia = $unsigned(redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_inputreg0_q);
    assign redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_aa = redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_wraddr_q;
    assign redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_ab = redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_aa),
        .data_a(redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_ab),
        .q_b(redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_q = redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_iq[15:0];

    // redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_outputreg0(DELAY,29657)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_outputreg0_q <= $unsigned(redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_mem_q);
        end
    end

    // redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_rdcnt(ADD,29667)
    assign redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_a = {1'b0, redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_wraddr_q};
    assign redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_b = {1'b0, redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_o <= $unsigned(redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_a) + $unsigned(redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_b);
        end
    end
    assign redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_q = redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_o[3:0];

    // redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_inputreg0(DELAY,29662)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl);
        end
    end

    // redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_wraddr(COUNTER,29665)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_wraddr_i <= $unsigned(redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_wraddr_q = redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_wraddr_i[2:0];

    // redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem(DUALMEM,29664)
    assign redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_ia = $unsigned(redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_inputreg0_q);
    assign redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_aa = redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_wraddr_q;
    assign redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_ab = redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_aa),
        .data_a(redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_ab),
        .q_b(redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_q = redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_iq[15:0];

    // redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_outputreg0(DELAY,29663)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_outputreg0_q <= $unsigned(redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_mem_q);
        end
    end

    // redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_rdcnt(ADD,31103)
    assign redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_a = {1'b0, redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_wraddr_q};
    assign redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_b = {1'b0, redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_o <= $unsigned(redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_a) + $unsigned(redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_b);
        end
    end
    assign redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_q = redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_o[3:0];

    // redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_inputreg0(DELAY,31098)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl);
        end
    end

    // redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_wraddr(COUNTER,31101)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_wraddr_i <= $unsigned(redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_wraddr_q = redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_wraddr_i[2:0];

    // redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem(DUALMEM,31100)
    assign redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_ia = $unsigned(redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_inputreg0_q);
    assign redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_aa = redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_wraddr_q;
    assign redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_ab = redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_aa),
        .data_a(redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_ab),
        .q_b(redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_q = redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_iq[15:0];

    // redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_outputreg0(DELAY,31099)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_outputreg0_q <= $unsigned(redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28092)@19 + 5
    // out q@25
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204(ADD,8615)@25
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod71_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_b = $unsigned({{5{i_shl_i_i_i_i_i_i_6_c_compstr203_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_6_c_compstr203_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_o[33:0];

    // rightShiftStage0_uid15341_dupName_25_i_unnamed_c_compstr0_shift_x(MUX,15340)@25
    assign rightShiftStage0_uid15341_dupName_25_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15341_dupName_25_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_q or rightShiftStage0Idx1_uid15339_dupName_25_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15341_dupName_25_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15341_dupName_25_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_q;
            1'b1 : rightShiftStage0_uid15341_dupName_25_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15339_dupName_25_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15341_dupName_25_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15346_dupName_25_i_unnamed_c_compstr0_shift_x(MUX,15345)@25
    assign rightShiftStage1_uid15346_dupName_25_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15346_dupName_25_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15341_dupName_25_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15344_dupName_25_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15346_dupName_25_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15346_dupName_25_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15341_dupName_25_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15346_dupName_25_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15344_dupName_25_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15346_dupName_25_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15351_dupName_25_i_unnamed_c_compstr0_shift_x(MUX,15350)@25
    assign rightShiftStage2_uid15351_dupName_25_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15351_dupName_25_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15346_dupName_25_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15349_dupName_25_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15351_dupName_25_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15351_dupName_25_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15346_dupName_25_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15351_dupName_25_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15349_dupName_25_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15351_dupName_25_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr205_vt_select_20(BITSELECT,10718)@25
    assign i_unnamed_c_compstr205_vt_select_20_b = rightShiftStage2_uid15351_dupName_25_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr205_vt_join(BITJOIN,10717)@25
    assign i_unnamed_c_compstr205_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr205_vt_select_20_b};

    // i_conv_i_i_i_i_i_6_c_compstr206_sel_x(BITSELECT,3806)@25
    assign i_conv_i_i_i_i_i_6_c_compstr206_sel_x_b = i_unnamed_c_compstr205_vt_join_q[15:0];

    // redist1059_i_conv_i_i_i_i_i_6_c_compstr206_sel_x_b_1(DELAY,29287)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1059_i_conv_i_i_i_i_i_6_c_compstr206_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_6_c_compstr206_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15360_dupName_26_i_unnamed_c_compstr0_shift_x(BITSELECT,15359)@25
    assign rightShiftStage1Idx1Rng8_uid15360_dupName_26_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15359_dupName_26_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15362_dupName_26_i_unnamed_c_compstr0_shift_x(BITJOIN,15361)@25
    assign rightShiftStage1Idx1_uid15362_dupName_26_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15360_dupName_26_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15355_dupName_26_i_unnamed_c_compstr0_shift_x(BITSELECT,15354)@25
    assign rightShiftStage0Idx1Rng4_uid15355_dupName_26_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_q[33:4];

    // rightShiftStage0Idx1_uid15357_dupName_26_i_unnamed_c_compstr0_shift_x(BITJOIN,15356)@25
    assign rightShiftStage0Idx1_uid15357_dupName_26_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15355_dupName_26_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15359_dupName_26_i_unnamed_c_compstr0_shift_x(MUX,15358)@25
    assign rightShiftStage0_uid15359_dupName_26_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15359_dupName_26_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_q or rightShiftStage0Idx1_uid15357_dupName_26_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15359_dupName_26_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15359_dupName_26_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compstr204_q;
            1'b1 : rightShiftStage0_uid15359_dupName_26_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15357_dupName_26_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15359_dupName_26_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15364_dupName_26_i_unnamed_c_compstr0_shift_x(MUX,15363)@25
    assign rightShiftStage1_uid15364_dupName_26_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15364_dupName_26_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15359_dupName_26_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15362_dupName_26_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15364_dupName_26_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15364_dupName_26_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15359_dupName_26_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15364_dupName_26_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15362_dupName_26_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15364_dupName_26_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr207_vt_select_21(BITSELECT,10732)@25
    assign i_unnamed_c_compstr207_vt_select_21_b = rightShiftStage1_uid15364_dupName_26_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr207_vt_join(BITJOIN,10731)@25
    assign i_unnamed_c_compstr207_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr207_vt_select_21_b};

    // i_unnamed_c_compstr208_sel_x(BITSELECT,6119)@25
    assign i_unnamed_c_compstr208_sel_x_b = i_unnamed_c_compstr207_vt_join_q[15:0];

    // i_unnamed_c_compstr209_BitSelect_for_a(BITSELECT,27629)@25
    assign i_unnamed_c_compstr209_BitSelect_for_a_b = i_unnamed_c_compstr208_sel_x_b[0:0];

    // i_unnamed_c_compstr209_join(BITJOIN,27630)@25
    assign i_unnamed_c_compstr209_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr209_BitSelect_for_a_b};

    // i_unnamed_c_compstr209_vt_select_0(BITSELECT,10759)@25
    assign i_unnamed_c_compstr209_vt_select_0_b = i_unnamed_c_compstr209_join_q[0:0];

    // redist169_i_unnamed_c_compstr209_vt_select_0_b_1(DELAY,28397)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist169_i_unnamed_c_compstr209_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr209_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr209_vt_join(BITJOIN,10758)@26
    assign i_unnamed_c_compstr209_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist169_i_unnamed_c_compstr209_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_6_c_compstr210(ADD,7073)@26
    assign i_add_i_i_i_i_i_i_6_c_compstr210_a = {1'b0, i_unnamed_c_compstr209_vt_join_q};
    assign i_add_i_i_i_i_i_i_6_c_compstr210_b = {1'b0, redist1059_i_conv_i_i_i_i_i_6_c_compstr206_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_6_c_compstr210_o = $unsigned(i_add_i_i_i_i_i_i_6_c_compstr210_a) + $unsigned(i_add_i_i_i_i_i_i_6_c_compstr210_b);
    assign i_add_i_i_i_i_i_i_6_c_compstr210_q = i_add_i_i_i_i_i_i_6_c_compstr210_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_6_c_compstr210_sel_x(BITSELECT,2267)@26
    assign bgTrunc_i_add_i_i_i_i_i_i_6_c_compstr210_sel_x_b = i_add_i_i_i_i_i_i_6_c_compstr210_q[15:0];

    // i_conv_i_i_i_i_i_i279_7_c_compstr230_sel_x(BITSELECT,3945)@26
    assign i_conv_i_i_i_i_i_i279_7_c_compstr230_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_6_c_compstr210_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_7_c_compstr230_vt_select_15(BITSELECT,8297)@26
    assign i_conv_i_i_i_i_i_i279_7_c_compstr230_vt_select_15_b = i_conv_i_i_i_i_i_i279_7_c_compstr230_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_7_c_compstr230_vt_join(BITJOIN,8296)@26
    assign i_conv_i_i_i_i_i_i279_7_c_compstr230_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_7_c_compstr230_vt_select_15_b};

    // leftShiftStage0_uid27032_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x(MUX,27031)@26
    assign leftShiftStage0_uid27032_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27032_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_7_c_compstr230_vt_join_q or leftShiftStage0Idx1_uid27030_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27032_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27032_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_7_c_compstr230_vt_join_q;
            1'b1 : leftShiftStage0_uid27032_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27030_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27032_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27037_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x(MUX,27036)@26
    assign leftShiftStage1_uid27037_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27037_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_s or leftShiftStage0_uid27032_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27035_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27037_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27037_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q = leftShiftStage0_uid27032_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27037_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27035_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27037_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27042_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x(MUX,27041)@26
    assign leftShiftStage2_uid27042_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27042_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_s or leftShiftStage1_uid27037_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27040_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27042_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27042_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q = leftShiftStage1_uid27037_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27042_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27040_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27042_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_7_c_compstr231_vt_select_28(BITSELECT,9736)@26
    assign i_shl_i_i_i_i_i_i_7_c_compstr231_vt_select_28_b = leftShiftStage2_uid27042_i_shl_i_i_i_i_i_i_7_c_compstr0_shift_x_q[28:13];

    // redist278_i_shl_i_i_i_i_i_i_7_c_compstr231_vt_select_28_b_1(DELAY,28506)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist278_i_shl_i_i_i_i_i_i_7_c_compstr231_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_7_c_compstr231_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_7_c_compstr231_vt_join(BITJOIN,9735)@27
    assign i_shl_i_i_i_i_i_i_7_c_compstr231_vt_join_q = {redist278_i_shl_i_i_i_i_i_i_7_c_compstr231_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_offset(CONSTANT,29672)
    assign redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_offset_q = $unsigned(4'b1000);

    // redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_rdcnt(ADD,31121)
    assign redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_a = {1'b0, redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_wraddr_q};
    assign redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_b = {1'b0, redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_o <= $unsigned(redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_a) + $unsigned(redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_b);
        end
    end
    assign redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_q = redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_o[4:0];

    // redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_inputreg0(DELAY,31116)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl);
        end
    end

    // redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_wraddr(COUNTER,31119)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_wraddr_i <= $unsigned(redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_wraddr_q = redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_wraddr_i[3:0];

    // redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem(DUALMEM,31118)
    assign redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_ia = $unsigned(redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_inputreg0_q);
    assign redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_aa = redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_wraddr_q;
    assign redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_ab = redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_aa),
        .data_a(redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_ab),
        .q_b(redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_q = redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_iq[15:0];

    // redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_outputreg0(DELAY,31117)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_outputreg0_q <= $unsigned(redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_mem_q);
        end
    end

    // redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_rdcnt(ADD,29673)
    assign redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_a = {1'b0, redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_wraddr_q};
    assign redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_b = {1'b0, redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_o <= $unsigned(redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_a) + $unsigned(redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_b);
        end
    end
    assign redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_q = redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_o[4:0];

    // redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_inputreg0(DELAY,29668)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl);
        end
    end

    // redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_wraddr(COUNTER,29671)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_wraddr_i <= $unsigned(redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_wraddr_q = redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_wraddr_i[3:0];

    // redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem(DUALMEM,29670)
    assign redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_ia = $unsigned(redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_inputreg0_q);
    assign redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_aa = redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_wraddr_q;
    assign redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_ab = redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_aa),
        .data_a(redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_ab),
        .q_b(redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_q = redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_iq[15:0];

    // redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_outputreg0(DELAY,29669)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_outputreg0_q <= $unsigned(redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_mem_q);
        end
    end

    // redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_rdcnt(ADD,29679)
    assign redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_a = {1'b0, redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_wraddr_q};
    assign redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_b = {1'b0, redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_o <= $unsigned(redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_a) + $unsigned(redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_b);
        end
    end
    assign redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_q = redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_o[4:0];

    // redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_inputreg0(DELAY,29674)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl);
        end
    end

    // redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_wraddr(COUNTER,29677)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_wraddr_i <= $unsigned(redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_wraddr_q = redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_wraddr_i[3:0];

    // redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem(DUALMEM,29676)
    assign redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_ia = $unsigned(redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_inputreg0_q);
    assign redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_aa = redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_wraddr_q;
    assign redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_ab = redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_aa),
        .data_a(redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_ab),
        .q_b(redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_q = redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_iq[15:0];

    // redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_outputreg0(DELAY,29675)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_outputreg0_q <= $unsigned(redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_mem_q);
        end
    end

    // redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_rdcnt(ADD,31115)
    assign redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_a = {1'b0, redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_wraddr_q};
    assign redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_b = {1'b0, redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_o <= $unsigned(redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_a) + $unsigned(redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_b);
        end
    end
    assign redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_q = redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_o[4:0];

    // redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_inputreg0(DELAY,31110)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl);
        end
    end

    // redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_wraddr(COUNTER,31113)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_wraddr_i <= $unsigned(redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_wraddr_q = redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_wraddr_i[3:0];

    // redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem(DUALMEM,31112)
    assign redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_ia = $unsigned(redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_inputreg0_q);
    assign redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_aa = redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_wraddr_q;
    assign redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_ab = redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_aa),
        .data_a(redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_ab),
        .q_b(redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_q = redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_iq[15:0];

    // redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_outputreg0(DELAY,31111)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_outputreg0_q <= $unsigned(redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28093)@21 + 5
    // out q@27
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232(ADD,8626)@27
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod76_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_b = $unsigned({{5{i_shl_i_i_i_i_i_i_7_c_compstr231_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_7_c_compstr231_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_o[33:0];

    // rightShiftStage0_uid15403_dupName_29_i_unnamed_c_compstr0_shift_x(MUX,15402)@27
    assign rightShiftStage0_uid15403_dupName_29_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15403_dupName_29_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_q or rightShiftStage0Idx1_uid15401_dupName_29_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15403_dupName_29_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15403_dupName_29_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_q;
            1'b1 : rightShiftStage0_uid15403_dupName_29_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15401_dupName_29_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15403_dupName_29_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15408_dupName_29_i_unnamed_c_compstr0_shift_x(MUX,15407)@27
    assign rightShiftStage1_uid15408_dupName_29_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15408_dupName_29_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15403_dupName_29_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15406_dupName_29_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15408_dupName_29_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15408_dupName_29_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15403_dupName_29_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15408_dupName_29_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15406_dupName_29_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15408_dupName_29_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15413_dupName_29_i_unnamed_c_compstr0_shift_x(MUX,15412)@27
    assign rightShiftStage2_uid15413_dupName_29_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15413_dupName_29_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15408_dupName_29_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15411_dupName_29_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15413_dupName_29_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15413_dupName_29_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15408_dupName_29_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15413_dupName_29_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15411_dupName_29_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15413_dupName_29_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr233_vt_select_20(BITSELECT,10960)@27
    assign i_unnamed_c_compstr233_vt_select_20_b = rightShiftStage2_uid15413_dupName_29_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr233_vt_join(BITJOIN,10959)@27
    assign i_unnamed_c_compstr233_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr233_vt_select_20_b};

    // i_conv_i_i_i_i_i_7_c_compstr234_sel_x(BITSELECT,3817)@27
    assign i_conv_i_i_i_i_i_7_c_compstr234_sel_x_b = i_unnamed_c_compstr233_vt_join_q[15:0];

    // redist1048_i_conv_i_i_i_i_i_7_c_compstr234_sel_x_b_1(DELAY,29276)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1048_i_conv_i_i_i_i_i_7_c_compstr234_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_7_c_compstr234_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15422_dupName_30_i_unnamed_c_compstr0_shift_x(BITSELECT,15421)@27
    assign rightShiftStage1Idx1Rng8_uid15422_dupName_30_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15421_dupName_30_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15424_dupName_30_i_unnamed_c_compstr0_shift_x(BITJOIN,15423)@27
    assign rightShiftStage1Idx1_uid15424_dupName_30_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15422_dupName_30_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15417_dupName_30_i_unnamed_c_compstr0_shift_x(BITSELECT,15416)@27
    assign rightShiftStage0Idx1Rng4_uid15417_dupName_30_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_q[33:4];

    // rightShiftStage0Idx1_uid15419_dupName_30_i_unnamed_c_compstr0_shift_x(BITJOIN,15418)@27
    assign rightShiftStage0Idx1_uid15419_dupName_30_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15417_dupName_30_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15421_dupName_30_i_unnamed_c_compstr0_shift_x(MUX,15420)@27
    assign rightShiftStage0_uid15421_dupName_30_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15421_dupName_30_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_q or rightShiftStage0Idx1_uid15419_dupName_30_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15421_dupName_30_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15421_dupName_30_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compstr232_q;
            1'b1 : rightShiftStage0_uid15421_dupName_30_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15419_dupName_30_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15421_dupName_30_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15426_dupName_30_i_unnamed_c_compstr0_shift_x(MUX,15425)@27
    assign rightShiftStage1_uid15426_dupName_30_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15426_dupName_30_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15421_dupName_30_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15424_dupName_30_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15426_dupName_30_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15426_dupName_30_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15421_dupName_30_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15426_dupName_30_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15424_dupName_30_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15426_dupName_30_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr235_vt_select_21(BITSELECT,10974)@27
    assign i_unnamed_c_compstr235_vt_select_21_b = rightShiftStage1_uid15426_dupName_30_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr235_vt_join(BITJOIN,10973)@27
    assign i_unnamed_c_compstr235_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr235_vt_select_21_b};

    // i_unnamed_c_compstr236_sel_x(BITSELECT,6141)@27
    assign i_unnamed_c_compstr236_sel_x_b = i_unnamed_c_compstr235_vt_join_q[15:0];

    // i_unnamed_c_compstr237_BitSelect_for_a(BITSELECT,27673)@27
    assign i_unnamed_c_compstr237_BitSelect_for_a_b = i_unnamed_c_compstr236_sel_x_b[0:0];

    // i_unnamed_c_compstr237_join(BITJOIN,27674)@27
    assign i_unnamed_c_compstr237_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr237_BitSelect_for_a_b};

    // i_unnamed_c_compstr237_vt_select_0(BITSELECT,11001)@27
    assign i_unnamed_c_compstr237_vt_select_0_b = i_unnamed_c_compstr237_join_q[0:0];

    // redist147_i_unnamed_c_compstr237_vt_select_0_b_1(DELAY,28375)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist147_i_unnamed_c_compstr237_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr237_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr237_vt_join(BITJOIN,11000)@28
    assign i_unnamed_c_compstr237_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist147_i_unnamed_c_compstr237_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_7_c_compstr238(ADD,7084)@28
    assign i_add_i_i_i_i_i_i_7_c_compstr238_a = {1'b0, i_unnamed_c_compstr237_vt_join_q};
    assign i_add_i_i_i_i_i_i_7_c_compstr238_b = {1'b0, redist1048_i_conv_i_i_i_i_i_7_c_compstr234_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_7_c_compstr238_o = $unsigned(i_add_i_i_i_i_i_i_7_c_compstr238_a) + $unsigned(i_add_i_i_i_i_i_i_7_c_compstr238_b);
    assign i_add_i_i_i_i_i_i_7_c_compstr238_q = i_add_i_i_i_i_i_i_7_c_compstr238_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_7_c_compstr238_sel_x(BITSELECT,2278)@28
    assign bgTrunc_i_add_i_i_i_i_i_i_7_c_compstr238_sel_x_b = i_add_i_i_i_i_i_i_7_c_compstr238_q[15:0];

    // i_conv_i_i_i_i_i_i279_8_c_compstr258_sel_x(BITSELECT,3956)@28
    assign i_conv_i_i_i_i_i_i279_8_c_compstr258_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_7_c_compstr238_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_8_c_compstr258_vt_select_15(BITSELECT,8341)@28
    assign i_conv_i_i_i_i_i_i279_8_c_compstr258_vt_select_15_b = i_conv_i_i_i_i_i_i279_8_c_compstr258_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_8_c_compstr258_vt_join(BITJOIN,8340)@28
    assign i_conv_i_i_i_i_i_i279_8_c_compstr258_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_8_c_compstr258_vt_select_15_b};

    // leftShiftStage0_uid27230_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x(MUX,27229)@28
    assign leftShiftStage0_uid27230_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27230_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_8_c_compstr258_vt_join_q or leftShiftStage0Idx1_uid27228_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27230_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27230_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_8_c_compstr258_vt_join_q;
            1'b1 : leftShiftStage0_uid27230_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27228_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27230_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27235_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x(MUX,27234)@28
    assign leftShiftStage1_uid27235_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27235_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_s or leftShiftStage0_uid27230_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27233_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27235_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27235_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q = leftShiftStage0_uid27230_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27235_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27233_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27235_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27240_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x(MUX,27239)@28
    assign leftShiftStage2_uid27240_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27240_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_s or leftShiftStage1_uid27235_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27238_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27240_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27240_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q = leftShiftStage1_uid27235_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27240_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27238_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27240_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_8_c_compstr259_vt_select_28(BITSELECT,9769)@28
    assign i_shl_i_i_i_i_i_i_8_c_compstr259_vt_select_28_b = leftShiftStage2_uid27240_i_shl_i_i_i_i_i_i_8_c_compstr0_shift_x_q[28:13];

    // redist267_i_shl_i_i_i_i_i_i_8_c_compstr259_vt_select_28_b_1(DELAY,28495)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist267_i_shl_i_i_i_i_i_i_8_c_compstr259_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_8_c_compstr259_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_8_c_compstr259_vt_join(BITJOIN,9768)@29
    assign i_shl_i_i_i_i_i_i_8_c_compstr259_vt_join_q = {redist267_i_shl_i_i_i_i_i_i_8_c_compstr259_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_offset(CONSTANT,29684)
    assign redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_offset_q = $unsigned(4'b0110);

    // redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_rdcnt(ADD,31133)
    assign redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_a = {1'b0, redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_wraddr_q};
    assign redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_b = {1'b0, redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_o <= $unsigned(redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_a) + $unsigned(redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_b);
        end
    end
    assign redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_q = redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_o[4:0];

    // redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_inputreg0(DELAY,31128)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl);
        end
    end

    // redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_wraddr(COUNTER,31131)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_wraddr_i <= $unsigned(redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_wraddr_q = redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_wraddr_i[3:0];

    // redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem(DUALMEM,31130)
    assign redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_ia = $unsigned(redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_inputreg0_q);
    assign redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_aa = redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_wraddr_q;
    assign redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_ab = redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_aa),
        .data_a(redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_ab),
        .q_b(redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_q = redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_iq[15:0];

    // redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_outputreg0(DELAY,31129)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_outputreg0_q <= $unsigned(redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_mem_q);
        end
    end

    // redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_rdcnt(ADD,29685)
    assign redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_a = {1'b0, redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_wraddr_q};
    assign redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_b = {1'b0, redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_o <= $unsigned(redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_a) + $unsigned(redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_b);
        end
    end
    assign redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_q = redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_o[4:0];

    // redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_inputreg0(DELAY,29680)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl);
        end
    end

    // redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_wraddr(COUNTER,29683)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_wraddr_i <= $unsigned(redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_wraddr_q = redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_wraddr_i[3:0];

    // redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem(DUALMEM,29682)
    assign redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_ia = $unsigned(redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_inputreg0_q);
    assign redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_aa = redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_wraddr_q;
    assign redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_ab = redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_aa),
        .data_a(redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_ab),
        .q_b(redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_q = redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_iq[15:0];

    // redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_outputreg0(DELAY,29681)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_outputreg0_q <= $unsigned(redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_mem_q);
        end
    end

    // redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_rdcnt(ADD,29691)
    assign redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_a = {1'b0, redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_wraddr_q};
    assign redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_b = {1'b0, redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_o <= $unsigned(redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_a) + $unsigned(redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_b);
        end
    end
    assign redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_q = redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_o[4:0];

    // redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_inputreg0(DELAY,29686)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl);
        end
    end

    // redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_wraddr(COUNTER,29689)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_wraddr_i <= $unsigned(redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_wraddr_q = redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_wraddr_i[3:0];

    // redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem(DUALMEM,29688)
    assign redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_ia = $unsigned(redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_inputreg0_q);
    assign redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_aa = redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_wraddr_q;
    assign redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_ab = redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_aa),
        .data_a(redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_ab),
        .q_b(redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_q = redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_iq[15:0];

    // redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_outputreg0(DELAY,29687)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_outputreg0_q <= $unsigned(redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_mem_q);
        end
    end

    // redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_rdcnt(ADD,31127)
    assign redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_a = {1'b0, redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_wraddr_q};
    assign redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_b = {1'b0, redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_o <= $unsigned(redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_a) + $unsigned(redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_b);
        end
    end
    assign redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_q = redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_o[4:0];

    // redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_inputreg0(DELAY,31122)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl);
        end
    end

    // redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_wraddr(COUNTER,31125)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_wraddr_i <= $unsigned(redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_wraddr_q = redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_wraddr_i[3:0];

    // redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem(DUALMEM,31124)
    assign redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_ia = $unsigned(redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_inputreg0_q);
    assign redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_aa = redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_wraddr_q;
    assign redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_ab = redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_aa),
        .data_a(redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_ab),
        .q_b(redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_q = redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_iq[15:0];

    // redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_outputreg0(DELAY,31123)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_outputreg0_q <= $unsigned(redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28094)@23 + 5
    // out q@29
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260(ADD,8637)@29
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod81_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_b = $unsigned({{5{i_shl_i_i_i_i_i_i_8_c_compstr259_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_8_c_compstr259_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_o[33:0];

    // rightShiftStage0_uid15465_dupName_33_i_unnamed_c_compstr0_shift_x(MUX,15464)@29
    assign rightShiftStage0_uid15465_dupName_33_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15465_dupName_33_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_q or rightShiftStage0Idx1_uid15463_dupName_33_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15465_dupName_33_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15465_dupName_33_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_q;
            1'b1 : rightShiftStage0_uid15465_dupName_33_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15463_dupName_33_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15465_dupName_33_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15470_dupName_33_i_unnamed_c_compstr0_shift_x(MUX,15469)@29
    assign rightShiftStage1_uid15470_dupName_33_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15470_dupName_33_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15465_dupName_33_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15468_dupName_33_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15470_dupName_33_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15470_dupName_33_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15465_dupName_33_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15470_dupName_33_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15468_dupName_33_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15470_dupName_33_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15475_dupName_33_i_unnamed_c_compstr0_shift_x(MUX,15474)@29
    assign rightShiftStage2_uid15475_dupName_33_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15475_dupName_33_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15470_dupName_33_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15473_dupName_33_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15475_dupName_33_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15475_dupName_33_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15470_dupName_33_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15475_dupName_33_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15473_dupName_33_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15475_dupName_33_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr261_vt_select_20(BITSELECT,11208)@29
    assign i_unnamed_c_compstr261_vt_select_20_b = rightShiftStage2_uid15475_dupName_33_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr261_vt_join(BITJOIN,11207)@29
    assign i_unnamed_c_compstr261_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr261_vt_select_20_b};

    // i_conv_i_i_i_i_i_8_c_compstr262_sel_x(BITSELECT,3828)@29
    assign i_conv_i_i_i_i_i_8_c_compstr262_sel_x_b = i_unnamed_c_compstr261_vt_join_q[15:0];

    // redist1037_i_conv_i_i_i_i_i_8_c_compstr262_sel_x_b_1(DELAY,29265)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1037_i_conv_i_i_i_i_i_8_c_compstr262_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_8_c_compstr262_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15484_dupName_34_i_unnamed_c_compstr0_shift_x(BITSELECT,15483)@29
    assign rightShiftStage1Idx1Rng8_uid15484_dupName_34_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15483_dupName_34_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15486_dupName_34_i_unnamed_c_compstr0_shift_x(BITJOIN,15485)@29
    assign rightShiftStage1Idx1_uid15486_dupName_34_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15484_dupName_34_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15479_dupName_34_i_unnamed_c_compstr0_shift_x(BITSELECT,15478)@29
    assign rightShiftStage0Idx1Rng4_uid15479_dupName_34_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_q[33:4];

    // rightShiftStage0Idx1_uid15481_dupName_34_i_unnamed_c_compstr0_shift_x(BITJOIN,15480)@29
    assign rightShiftStage0Idx1_uid15481_dupName_34_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15479_dupName_34_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15483_dupName_34_i_unnamed_c_compstr0_shift_x(MUX,15482)@29
    assign rightShiftStage0_uid15483_dupName_34_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15483_dupName_34_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_q or rightShiftStage0Idx1_uid15481_dupName_34_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15483_dupName_34_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15483_dupName_34_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compstr260_q;
            1'b1 : rightShiftStage0_uid15483_dupName_34_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15481_dupName_34_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15483_dupName_34_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15488_dupName_34_i_unnamed_c_compstr0_shift_x(MUX,15487)@29
    assign rightShiftStage1_uid15488_dupName_34_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15488_dupName_34_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15483_dupName_34_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15486_dupName_34_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15488_dupName_34_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15488_dupName_34_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15483_dupName_34_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15488_dupName_34_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15486_dupName_34_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15488_dupName_34_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr263_vt_select_21(BITSELECT,11222)@29
    assign i_unnamed_c_compstr263_vt_select_21_b = rightShiftStage1_uid15488_dupName_34_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr263_vt_join(BITJOIN,11221)@29
    assign i_unnamed_c_compstr263_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr263_vt_select_21_b};

    // i_unnamed_c_compstr264_sel_x(BITSELECT,6164)@29
    assign i_unnamed_c_compstr264_sel_x_b = i_unnamed_c_compstr263_vt_join_q[15:0];

    // i_unnamed_c_compstr265_BitSelect_for_a(BITSELECT,27717)@29
    assign i_unnamed_c_compstr265_BitSelect_for_a_b = i_unnamed_c_compstr264_sel_x_b[0:0];

    // i_unnamed_c_compstr265_join(BITJOIN,27718)@29
    assign i_unnamed_c_compstr265_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr265_BitSelect_for_a_b};

    // i_unnamed_c_compstr265_vt_select_0(BITSELECT,11249)@29
    assign i_unnamed_c_compstr265_vt_select_0_b = i_unnamed_c_compstr265_join_q[0:0];

    // redist125_i_unnamed_c_compstr265_vt_select_0_b_1(DELAY,28353)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist125_i_unnamed_c_compstr265_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr265_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr265_vt_join(BITJOIN,11248)@30
    assign i_unnamed_c_compstr265_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist125_i_unnamed_c_compstr265_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_8_c_compstr266(ADD,7095)@30
    assign i_add_i_i_i_i_i_i_8_c_compstr266_a = {1'b0, i_unnamed_c_compstr265_vt_join_q};
    assign i_add_i_i_i_i_i_i_8_c_compstr266_b = {1'b0, redist1037_i_conv_i_i_i_i_i_8_c_compstr262_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_8_c_compstr266_o = $unsigned(i_add_i_i_i_i_i_i_8_c_compstr266_a) + $unsigned(i_add_i_i_i_i_i_i_8_c_compstr266_b);
    assign i_add_i_i_i_i_i_i_8_c_compstr266_q = i_add_i_i_i_i_i_i_8_c_compstr266_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_8_c_compstr266_sel_x(BITSELECT,2289)@30
    assign bgTrunc_i_add_i_i_i_i_i_i_8_c_compstr266_sel_x_b = i_add_i_i_i_i_i_i_8_c_compstr266_q[15:0];

    // i_conv_i_i_i_i_i_i279_9_c_compstr286_sel_x(BITSELECT,3967)@30
    assign i_conv_i_i_i_i_i_i279_9_c_compstr286_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_8_c_compstr266_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_9_c_compstr286_vt_select_15(BITSELECT,8385)@30
    assign i_conv_i_i_i_i_i_i279_9_c_compstr286_vt_select_15_b = i_conv_i_i_i_i_i_i279_9_c_compstr286_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_9_c_compstr286_vt_join(BITJOIN,8384)@30
    assign i_conv_i_i_i_i_i_i279_9_c_compstr286_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_9_c_compstr286_vt_select_15_b};

    // leftShiftStage0_uid27428_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x(MUX,27427)@30
    assign leftShiftStage0_uid27428_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27428_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_9_c_compstr286_vt_join_q or leftShiftStage0Idx1_uid27426_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27428_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27428_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_9_c_compstr286_vt_join_q;
            1'b1 : leftShiftStage0_uid27428_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27426_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27428_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27433_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x(MUX,27432)@30
    assign leftShiftStage1_uid27433_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27433_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_s or leftShiftStage0_uid27428_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27431_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27433_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27433_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q = leftShiftStage0_uid27428_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27433_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27431_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27433_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27438_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x(MUX,27437)@30
    assign leftShiftStage2_uid27438_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27438_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_s or leftShiftStage1_uid27433_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27436_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27438_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27438_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q = leftShiftStage1_uid27433_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27438_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27436_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27438_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_9_c_compstr287_vt_select_28(BITSELECT,9802)@30
    assign i_shl_i_i_i_i_i_i_9_c_compstr287_vt_select_28_b = leftShiftStage2_uid27438_i_shl_i_i_i_i_i_i_9_c_compstr0_shift_x_q[28:13];

    // redist256_i_shl_i_i_i_i_i_i_9_c_compstr287_vt_select_28_b_1(DELAY,28484)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist256_i_shl_i_i_i_i_i_i_9_c_compstr287_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_9_c_compstr287_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_9_c_compstr287_vt_join(BITJOIN,9801)@31
    assign i_shl_i_i_i_i_i_i_9_c_compstr287_vt_join_q = {redist256_i_shl_i_i_i_i_i_i_9_c_compstr287_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_offset(CONSTANT,29696)
    assign redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_offset_q = $unsigned(4'b0100);

    // redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_rdcnt(ADD,31145)
    assign redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_a = {1'b0, redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_wraddr_q};
    assign redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_b = {1'b0, redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_o <= $unsigned(redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_a) + $unsigned(redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_b);
        end
    end
    assign redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_q = redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_o[4:0];

    // redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_inputreg0(DELAY,31140)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl);
        end
    end

    // redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_wraddr(COUNTER,31143)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_wraddr_i <= $unsigned(redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_wraddr_q = redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_wraddr_i[3:0];

    // redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem(DUALMEM,31142)
    assign redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_ia = $unsigned(redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_inputreg0_q);
    assign redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_aa = redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_wraddr_q;
    assign redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_ab = redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_aa),
        .data_a(redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_ab),
        .q_b(redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_q = redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_iq[15:0];

    // redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_outputreg0(DELAY,31141)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_outputreg0_q <= $unsigned(redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_mem_q);
        end
    end

    // redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_rdcnt(ADD,29697)
    assign redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_a = {1'b0, redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_wraddr_q};
    assign redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_b = {1'b0, redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_o <= $unsigned(redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_a) + $unsigned(redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_b);
        end
    end
    assign redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_q = redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_o[4:0];

    // redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_inputreg0(DELAY,29692)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl);
        end
    end

    // redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_wraddr(COUNTER,29695)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_wraddr_i <= $unsigned(redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_wraddr_q = redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_wraddr_i[3:0];

    // redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem(DUALMEM,29694)
    assign redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_ia = $unsigned(redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_inputreg0_q);
    assign redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_aa = redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_wraddr_q;
    assign redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_ab = redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_aa),
        .data_a(redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_ab),
        .q_b(redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_q = redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_iq[15:0];

    // redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_outputreg0(DELAY,29693)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_outputreg0_q <= $unsigned(redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_mem_q);
        end
    end

    // redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_rdcnt(ADD,29703)
    assign redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_a = {1'b0, redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_wraddr_q};
    assign redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_b = {1'b0, redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_o <= $unsigned(redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_a) + $unsigned(redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_b);
        end
    end
    assign redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_q = redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_o[4:0];

    // redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_inputreg0(DELAY,29698)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl);
        end
    end

    // redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_wraddr(COUNTER,29701)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_wraddr_i <= $unsigned(redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_wraddr_q = redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_wraddr_i[3:0];

    // redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem(DUALMEM,29700)
    assign redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_ia = $unsigned(redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_inputreg0_q);
    assign redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_aa = redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_wraddr_q;
    assign redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_ab = redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_aa),
        .data_a(redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_ab),
        .q_b(redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_q = redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_iq[15:0];

    // redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_outputreg0(DELAY,29699)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_outputreg0_q <= $unsigned(redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_mem_q);
        end
    end

    // redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_rdcnt(ADD,31139)
    assign redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_a = {1'b0, redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_wraddr_q};
    assign redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_b = {1'b0, redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_o <= $unsigned(redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_a) + $unsigned(redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_b);
        end
    end
    assign redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_q = redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_o[4:0];

    // redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_inputreg0(DELAY,31134)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl);
        end
    end

    // redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_wraddr(COUNTER,31137)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_wraddr_i <= $unsigned(redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_wraddr_q = redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_wraddr_i[3:0];

    // redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem(DUALMEM,31136)
    assign redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_ia = $unsigned(redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_inputreg0_q);
    assign redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_aa = redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_wraddr_q;
    assign redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_ab = redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_aa),
        .data_a(redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_ab),
        .q_b(redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_q = redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_iq[15:0];

    // redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_outputreg0(DELAY,31135)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_outputreg0_q <= $unsigned(redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28095)@25 + 5
    // out q@31
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288(ADD,8648)@31
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod86_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_b = $unsigned({{5{i_shl_i_i_i_i_i_i_9_c_compstr287_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_9_c_compstr287_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_o[33:0];

    // rightShiftStage0_uid15527_dupName_37_i_unnamed_c_compstr0_shift_x(MUX,15526)@31
    assign rightShiftStage0_uid15527_dupName_37_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15527_dupName_37_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_q or rightShiftStage0Idx1_uid15525_dupName_37_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15527_dupName_37_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15527_dupName_37_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_q;
            1'b1 : rightShiftStage0_uid15527_dupName_37_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15525_dupName_37_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15527_dupName_37_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15532_dupName_37_i_unnamed_c_compstr0_shift_x(MUX,15531)@31
    assign rightShiftStage1_uid15532_dupName_37_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15532_dupName_37_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15527_dupName_37_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15530_dupName_37_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15532_dupName_37_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15532_dupName_37_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15527_dupName_37_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15532_dupName_37_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15530_dupName_37_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15532_dupName_37_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15537_dupName_37_i_unnamed_c_compstr0_shift_x(MUX,15536)@31
    assign rightShiftStage2_uid15537_dupName_37_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15537_dupName_37_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15532_dupName_37_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15535_dupName_37_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15537_dupName_37_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15537_dupName_37_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15532_dupName_37_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15537_dupName_37_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15535_dupName_37_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15537_dupName_37_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr289_vt_select_20(BITSELECT,11455)@31
    assign i_unnamed_c_compstr289_vt_select_20_b = rightShiftStage2_uid15537_dupName_37_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr289_vt_join(BITJOIN,11454)@31
    assign i_unnamed_c_compstr289_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr289_vt_select_20_b};

    // i_conv_i_i_i_i_i_9_c_compstr290_sel_x(BITSELECT,3839)@31
    assign i_conv_i_i_i_i_i_9_c_compstr290_sel_x_b = i_unnamed_c_compstr289_vt_join_q[15:0];

    // redist1026_i_conv_i_i_i_i_i_9_c_compstr290_sel_x_b_1(DELAY,29254)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1026_i_conv_i_i_i_i_i_9_c_compstr290_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_9_c_compstr290_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15546_dupName_38_i_unnamed_c_compstr0_shift_x(BITSELECT,15545)@31
    assign rightShiftStage1Idx1Rng8_uid15546_dupName_38_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15545_dupName_38_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15548_dupName_38_i_unnamed_c_compstr0_shift_x(BITJOIN,15547)@31
    assign rightShiftStage1Idx1_uid15548_dupName_38_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15546_dupName_38_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15541_dupName_38_i_unnamed_c_compstr0_shift_x(BITSELECT,15540)@31
    assign rightShiftStage0Idx1Rng4_uid15541_dupName_38_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_q[33:4];

    // rightShiftStage0Idx1_uid15543_dupName_38_i_unnamed_c_compstr0_shift_x(BITJOIN,15542)@31
    assign rightShiftStage0Idx1_uid15543_dupName_38_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15541_dupName_38_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15545_dupName_38_i_unnamed_c_compstr0_shift_x(MUX,15544)@31
    assign rightShiftStage0_uid15545_dupName_38_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15545_dupName_38_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_q or rightShiftStage0Idx1_uid15543_dupName_38_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15545_dupName_38_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15545_dupName_38_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compstr288_q;
            1'b1 : rightShiftStage0_uid15545_dupName_38_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15543_dupName_38_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15545_dupName_38_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15550_dupName_38_i_unnamed_c_compstr0_shift_x(MUX,15549)@31
    assign rightShiftStage1_uid15550_dupName_38_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15550_dupName_38_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15545_dupName_38_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15548_dupName_38_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15550_dupName_38_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15550_dupName_38_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15545_dupName_38_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15550_dupName_38_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15548_dupName_38_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15550_dupName_38_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr291_vt_select_21(BITSELECT,11469)@31
    assign i_unnamed_c_compstr291_vt_select_21_b = rightShiftStage1_uid15550_dupName_38_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr291_vt_join(BITJOIN,11468)@31
    assign i_unnamed_c_compstr291_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr291_vt_select_21_b};

    // i_unnamed_c_compstr292_sel_x(BITSELECT,6186)@31
    assign i_unnamed_c_compstr292_sel_x_b = i_unnamed_c_compstr291_vt_join_q[15:0];

    // i_unnamed_c_compstr293_BitSelect_for_a(BITSELECT,27763)@31
    assign i_unnamed_c_compstr293_BitSelect_for_a_b = i_unnamed_c_compstr292_sel_x_b[0:0];

    // i_unnamed_c_compstr293_join(BITJOIN,27764)@31
    assign i_unnamed_c_compstr293_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr293_BitSelect_for_a_b};

    // i_unnamed_c_compstr293_vt_select_0(BITSELECT,11496)@31
    assign i_unnamed_c_compstr293_vt_select_0_b = i_unnamed_c_compstr293_join_q[0:0];

    // redist103_i_unnamed_c_compstr293_vt_select_0_b_1(DELAY,28331)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist103_i_unnamed_c_compstr293_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr293_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr293_vt_join(BITJOIN,11495)@32
    assign i_unnamed_c_compstr293_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist103_i_unnamed_c_compstr293_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_9_c_compstr294(ADD,7106)@32
    assign i_add_i_i_i_i_i_i_9_c_compstr294_a = {1'b0, i_unnamed_c_compstr293_vt_join_q};
    assign i_add_i_i_i_i_i_i_9_c_compstr294_b = {1'b0, redist1026_i_conv_i_i_i_i_i_9_c_compstr290_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_9_c_compstr294_o = $unsigned(i_add_i_i_i_i_i_i_9_c_compstr294_a) + $unsigned(i_add_i_i_i_i_i_i_9_c_compstr294_b);
    assign i_add_i_i_i_i_i_i_9_c_compstr294_q = i_add_i_i_i_i_i_i_9_c_compstr294_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_9_c_compstr294_sel_x(BITSELECT,2300)@32
    assign bgTrunc_i_add_i_i_i_i_i_i_9_c_compstr294_sel_x_b = i_add_i_i_i_i_i_i_9_c_compstr294_q[15:0];

    // i_conv_i_i_i_i_i_i279_10_c_compstr314_sel_x(BITSELECT,3851)@32
    assign i_conv_i_i_i_i_i_i279_10_c_compstr314_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_9_c_compstr294_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_10_c_compstr314_vt_select_15(BITSELECT,7921)@32
    assign i_conv_i_i_i_i_i_i279_10_c_compstr314_vt_select_15_b = i_conv_i_i_i_i_i_i279_10_c_compstr314_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_10_c_compstr314_vt_join(BITJOIN,7920)@32
    assign i_conv_i_i_i_i_i_i279_10_c_compstr314_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_10_c_compstr314_vt_select_15_b};

    // leftShiftStage0_uid25340_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x(MUX,25339)@32
    assign leftShiftStage0_uid25340_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25340_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_10_c_compstr314_vt_join_q or leftShiftStage0Idx1_uid25338_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25340_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25340_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_10_c_compstr314_vt_join_q;
            1'b1 : leftShiftStage0_uid25340_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25338_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25340_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25345_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x(MUX,25344)@32
    assign leftShiftStage1_uid25345_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25345_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_s or leftShiftStage0_uid25340_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25343_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25345_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25345_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q = leftShiftStage0_uid25340_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25345_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25343_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25345_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25350_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x(MUX,25349)@32
    assign leftShiftStage2_uid25350_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25350_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_s or leftShiftStage1_uid25345_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25348_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25350_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25350_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q = leftShiftStage1_uid25345_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25350_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25348_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25350_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_10_c_compstr315_vt_select_28(BITSELECT,9454)@32
    assign i_shl_i_i_i_i_i_i_10_c_compstr315_vt_select_28_b = leftShiftStage2_uid25350_i_shl_i_i_i_i_i_i_10_c_compstr0_shift_x_q[28:13];

    // redist372_i_shl_i_i_i_i_i_i_10_c_compstr315_vt_select_28_b_1(DELAY,28600)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist372_i_shl_i_i_i_i_i_i_10_c_compstr315_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_10_c_compstr315_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_10_c_compstr315_vt_join(BITJOIN,9453)@33
    assign i_shl_i_i_i_i_i_i_10_c_compstr315_vt_join_q = {redist372_i_shl_i_i_i_i_i_i_10_c_compstr315_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_offset(CONSTANT,29708)
    assign redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_offset_q = $unsigned(4'b0010);

    // redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_rdcnt(ADD,31157)
    assign redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_a = {1'b0, redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_wraddr_q};
    assign redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_b = {1'b0, redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_o <= $unsigned(redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_a) + $unsigned(redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_b);
        end
    end
    assign redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_q = redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_o[4:0];

    // redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_inputreg0(DELAY,31152)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl);
        end
    end

    // redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_wraddr(COUNTER,31155)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_wraddr_i <= $unsigned(redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_wraddr_q = redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_wraddr_i[3:0];

    // redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem(DUALMEM,31154)
    assign redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_ia = $unsigned(redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_inputreg0_q);
    assign redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_aa = redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_wraddr_q;
    assign redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_ab = redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_aa),
        .data_a(redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_ab),
        .q_b(redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_q = redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_iq[15:0];

    // redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_outputreg0(DELAY,31153)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_outputreg0_q <= $unsigned(redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_mem_q);
        end
    end

    // redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_rdcnt(ADD,29709)
    assign redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_a = {1'b0, redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_wraddr_q};
    assign redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_b = {1'b0, redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_o <= $unsigned(redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_a) + $unsigned(redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_b);
        end
    end
    assign redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_q = redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_o[4:0];

    // redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_inputreg0(DELAY,29704)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl);
        end
    end

    // redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_wraddr(COUNTER,29707)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_wraddr_i <= $unsigned(redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_wraddr_q = redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_wraddr_i[3:0];

    // redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem(DUALMEM,29706)
    assign redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_ia = $unsigned(redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_inputreg0_q);
    assign redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_aa = redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_wraddr_q;
    assign redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_ab = redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_aa),
        .data_a(redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_ab),
        .q_b(redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_q = redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_iq[15:0];

    // redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_outputreg0(DELAY,29705)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_outputreg0_q <= $unsigned(redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_mem_q);
        end
    end

    // redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_rdcnt(ADD,29715)
    assign redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_a = {1'b0, redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_wraddr_q};
    assign redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_b = {1'b0, redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_o <= $unsigned(redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_a) + $unsigned(redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_b);
        end
    end
    assign redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_q = redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_o[4:0];

    // redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_inputreg0(DELAY,29710)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl);
        end
    end

    // redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_wraddr(COUNTER,29713)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_wraddr_i <= $unsigned(redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_wraddr_q = redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_wraddr_i[3:0];

    // redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem(DUALMEM,29712)
    assign redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_ia = $unsigned(redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_inputreg0_q);
    assign redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_aa = redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_wraddr_q;
    assign redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_ab = redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_aa),
        .data_a(redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_ab),
        .q_b(redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_q = redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_iq[15:0];

    // redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_outputreg0(DELAY,29711)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_outputreg0_q <= $unsigned(redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_mem_q);
        end
    end

    // redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_rdcnt(ADD,31151)
    assign redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_a = {1'b0, redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_wraddr_q};
    assign redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_b = {1'b0, redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_o <= $unsigned(redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_a) + $unsigned(redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_b);
        end
    end
    assign redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_q = redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_o[4:0];

    // redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_inputreg0(DELAY,31146)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl);
        end
    end

    // redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_wraddr(COUNTER,31149)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_wraddr_i <= $unsigned(redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_wraddr_q = redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_wraddr_i[3:0];

    // redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem(DUALMEM,31148)
    assign redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_ia = $unsigned(redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_inputreg0_q);
    assign redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_aa = redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_wraddr_q;
    assign redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_ab = redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_aa),
        .data_a(redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_ab),
        .q_b(redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_q = redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_iq[15:0];

    // redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_outputreg0(DELAY,31147)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_outputreg0_q <= $unsigned(redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28096)@27 + 5
    // out q@33
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316(ADD,8532)@33
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod91_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_b = $unsigned({{5{i_shl_i_i_i_i_i_i_10_c_compstr315_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_10_c_compstr315_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_o[33:0];

    // rightShiftStage0_uid15589_dupName_41_i_unnamed_c_compstr0_shift_x(MUX,15588)@33
    assign rightShiftStage0_uid15589_dupName_41_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15589_dupName_41_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_q or rightShiftStage0Idx1_uid15587_dupName_41_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15589_dupName_41_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15589_dupName_41_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_q;
            1'b1 : rightShiftStage0_uid15589_dupName_41_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15587_dupName_41_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15589_dupName_41_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15594_dupName_41_i_unnamed_c_compstr0_shift_x(MUX,15593)@33
    assign rightShiftStage1_uid15594_dupName_41_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15594_dupName_41_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15589_dupName_41_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15592_dupName_41_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15594_dupName_41_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15594_dupName_41_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15589_dupName_41_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15594_dupName_41_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15592_dupName_41_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15594_dupName_41_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15599_dupName_41_i_unnamed_c_compstr0_shift_x(MUX,15598)@33
    assign rightShiftStage2_uid15599_dupName_41_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15599_dupName_41_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15594_dupName_41_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15597_dupName_41_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15599_dupName_41_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15599_dupName_41_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15594_dupName_41_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15599_dupName_41_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15597_dupName_41_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15599_dupName_41_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr317_vt_select_20(BITSELECT,11697)@33
    assign i_unnamed_c_compstr317_vt_select_20_b = rightShiftStage2_uid15599_dupName_41_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr317_vt_join(BITJOIN,11696)@33
    assign i_unnamed_c_compstr317_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr317_vt_select_20_b};

    // i_conv_i_i_i_i_i_10_c_compstr318_sel_x(BITSELECT,3723)@33
    assign i_conv_i_i_i_i_i_10_c_compstr318_sel_x_b = i_unnamed_c_compstr317_vt_join_q[15:0];

    // redist1142_i_conv_i_i_i_i_i_10_c_compstr318_sel_x_b_1(DELAY,29370)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1142_i_conv_i_i_i_i_i_10_c_compstr318_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_10_c_compstr318_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15608_dupName_42_i_unnamed_c_compstr0_shift_x(BITSELECT,15607)@33
    assign rightShiftStage1Idx1Rng8_uid15608_dupName_42_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15607_dupName_42_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15610_dupName_42_i_unnamed_c_compstr0_shift_x(BITJOIN,15609)@33
    assign rightShiftStage1Idx1_uid15610_dupName_42_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15608_dupName_42_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15603_dupName_42_i_unnamed_c_compstr0_shift_x(BITSELECT,15602)@33
    assign rightShiftStage0Idx1Rng4_uid15603_dupName_42_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_q[33:4];

    // rightShiftStage0Idx1_uid15605_dupName_42_i_unnamed_c_compstr0_shift_x(BITJOIN,15604)@33
    assign rightShiftStage0Idx1_uid15605_dupName_42_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15603_dupName_42_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15607_dupName_42_i_unnamed_c_compstr0_shift_x(MUX,15606)@33
    assign rightShiftStage0_uid15607_dupName_42_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15607_dupName_42_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_q or rightShiftStage0Idx1_uid15605_dupName_42_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15607_dupName_42_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15607_dupName_42_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compstr316_q;
            1'b1 : rightShiftStage0_uid15607_dupName_42_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15605_dupName_42_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15607_dupName_42_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15612_dupName_42_i_unnamed_c_compstr0_shift_x(MUX,15611)@33
    assign rightShiftStage1_uid15612_dupName_42_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15612_dupName_42_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15607_dupName_42_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15610_dupName_42_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15612_dupName_42_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15612_dupName_42_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15607_dupName_42_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15612_dupName_42_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15610_dupName_42_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15612_dupName_42_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr319_vt_select_21(BITSELECT,11711)@33
    assign i_unnamed_c_compstr319_vt_select_21_b = rightShiftStage1_uid15612_dupName_42_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr319_vt_join(BITJOIN,11710)@33
    assign i_unnamed_c_compstr319_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr319_vt_select_21_b};

    // i_unnamed_c_compstr320_sel_x(BITSELECT,6208)@33
    assign i_unnamed_c_compstr320_sel_x_b = i_unnamed_c_compstr319_vt_join_q[15:0];

    // i_unnamed_c_compstr321_BitSelect_for_a(BITSELECT,27807)@33
    assign i_unnamed_c_compstr321_BitSelect_for_a_b = i_unnamed_c_compstr320_sel_x_b[0:0];

    // i_unnamed_c_compstr321_join(BITJOIN,27808)@33
    assign i_unnamed_c_compstr321_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr321_BitSelect_for_a_b};

    // i_unnamed_c_compstr321_vt_select_0(BITSELECT,11738)@33
    assign i_unnamed_c_compstr321_vt_select_0_b = i_unnamed_c_compstr321_join_q[0:0];

    // redist81_i_unnamed_c_compstr321_vt_select_0_b_1(DELAY,28309)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist81_i_unnamed_c_compstr321_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr321_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr321_vt_join(BITJOIN,11737)@34
    assign i_unnamed_c_compstr321_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist81_i_unnamed_c_compstr321_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_10_c_compstr322(ADD,6990)@34
    assign i_add_i_i_i_i_i_i_10_c_compstr322_a = {1'b0, i_unnamed_c_compstr321_vt_join_q};
    assign i_add_i_i_i_i_i_i_10_c_compstr322_b = {1'b0, redist1142_i_conv_i_i_i_i_i_10_c_compstr318_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_10_c_compstr322_o = $unsigned(i_add_i_i_i_i_i_i_10_c_compstr322_a) + $unsigned(i_add_i_i_i_i_i_i_10_c_compstr322_b);
    assign i_add_i_i_i_i_i_i_10_c_compstr322_q = i_add_i_i_i_i_i_i_10_c_compstr322_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_10_c_compstr322_sel_x(BITSELECT,2184)@34
    assign bgTrunc_i_add_i_i_i_i_i_i_10_c_compstr322_sel_x_b = i_add_i_i_i_i_i_i_10_c_compstr322_q[15:0];

    // i_conv_i_i_i_i_i_i279_11_c_compstr342_sel_x(BITSELECT,3862)@34
    assign i_conv_i_i_i_i_i_i279_11_c_compstr342_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_10_c_compstr322_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_11_c_compstr342_vt_select_15(BITSELECT,7965)@34
    assign i_conv_i_i_i_i_i_i279_11_c_compstr342_vt_select_15_b = i_conv_i_i_i_i_i_i279_11_c_compstr342_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_11_c_compstr342_vt_join(BITJOIN,7964)@34
    assign i_conv_i_i_i_i_i_i279_11_c_compstr342_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_11_c_compstr342_vt_select_15_b};

    // leftShiftStage0_uid25538_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x(MUX,25537)@34
    assign leftShiftStage0_uid25538_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25538_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_11_c_compstr342_vt_join_q or leftShiftStage0Idx1_uid25536_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25538_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25538_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_11_c_compstr342_vt_join_q;
            1'b1 : leftShiftStage0_uid25538_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25536_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25538_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25543_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x(MUX,25542)@34
    assign leftShiftStage1_uid25543_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25543_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_s or leftShiftStage0_uid25538_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25541_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25543_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25543_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q = leftShiftStage0_uid25538_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25543_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25541_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25543_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25548_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x(MUX,25547)@34
    assign leftShiftStage2_uid25548_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25548_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_s or leftShiftStage1_uid25543_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25546_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25548_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25548_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q = leftShiftStage1_uid25543_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25548_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25546_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25548_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_11_c_compstr343_vt_select_28(BITSELECT,9487)@34
    assign i_shl_i_i_i_i_i_i_11_c_compstr343_vt_select_28_b = leftShiftStage2_uid25548_i_shl_i_i_i_i_i_i_11_c_compstr0_shift_x_q[28:13];

    // redist361_i_shl_i_i_i_i_i_i_11_c_compstr343_vt_select_28_b_1(DELAY,28589)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist361_i_shl_i_i_i_i_i_i_11_c_compstr343_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_11_c_compstr343_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_11_c_compstr343_vt_join(BITJOIN,9486)@35
    assign i_shl_i_i_i_i_i_i_11_c_compstr343_vt_join_q = {redist361_i_shl_i_i_i_i_i_i_11_c_compstr343_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_offset(CONSTANT,29720)
    assign redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_offset_q = $unsigned(5'b10000);

    // redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_rdcnt(ADD,31169)
    assign redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_a = {1'b0, redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_wraddr_q};
    assign redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_b = {1'b0, redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_o <= $unsigned(redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_a) + $unsigned(redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_b);
        end
    end
    assign redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_q = redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_o[5:0];

    // redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_inputreg0(DELAY,31164)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl);
        end
    end

    // redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_wraddr(COUNTER,31167)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_wraddr_i <= $unsigned(redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_wraddr_q = redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_wraddr_i[4:0];

    // redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem(DUALMEM,31166)
    assign redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_ia = $unsigned(redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_inputreg0_q);
    assign redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_aa = redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_wraddr_q;
    assign redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_ab = redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_aa),
        .data_a(redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_ab),
        .q_b(redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_q = redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_iq[15:0];

    // redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_outputreg0(DELAY,31165)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_outputreg0_q <= $unsigned(redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_mem_q);
        end
    end

    // redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_rdcnt(ADD,29721)
    assign redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_a = {1'b0, redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_wraddr_q};
    assign redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_b = {1'b0, redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_o <= $unsigned(redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_a) + $unsigned(redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_b);
        end
    end
    assign redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_q = redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_o[5:0];

    // redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_inputreg0(DELAY,29716)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl);
        end
    end

    // redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_wraddr(COUNTER,29719)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_wraddr_i <= $unsigned(redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_wraddr_q = redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_wraddr_i[4:0];

    // redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem(DUALMEM,29718)
    assign redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_ia = $unsigned(redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_inputreg0_q);
    assign redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_aa = redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_wraddr_q;
    assign redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_ab = redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_aa),
        .data_a(redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_ab),
        .q_b(redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_q = redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_iq[15:0];

    // redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_outputreg0(DELAY,29717)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_outputreg0_q <= $unsigned(redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_mem_q);
        end
    end

    // redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_rdcnt(ADD,29727)
    assign redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_a = {1'b0, redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_wraddr_q};
    assign redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_b = {1'b0, redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_o <= $unsigned(redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_a) + $unsigned(redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_b);
        end
    end
    assign redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_q = redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_o[5:0];

    // redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_inputreg0(DELAY,29722)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl);
        end
    end

    // redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_wraddr(COUNTER,29725)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_wraddr_i <= $unsigned(redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_wraddr_q = redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_wraddr_i[4:0];

    // redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem(DUALMEM,29724)
    assign redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_ia = $unsigned(redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_inputreg0_q);
    assign redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_aa = redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_wraddr_q;
    assign redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_ab = redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_aa),
        .data_a(redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_ab),
        .q_b(redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_q = redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_iq[15:0];

    // redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_outputreg0(DELAY,29723)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_outputreg0_q <= $unsigned(redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_mem_q);
        end
    end

    // redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_rdcnt(ADD,31163)
    assign redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_a = {1'b0, redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_wraddr_q};
    assign redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_b = {1'b0, redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_o <= $unsigned(redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_a) + $unsigned(redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_b);
        end
    end
    assign redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_q = redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_o[5:0];

    // redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_inputreg0(DELAY,31158)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl);
        end
    end

    // redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_wraddr(COUNTER,31161)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_wraddr_i <= $unsigned(redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_wraddr_q = redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_wraddr_i[4:0];

    // redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem(DUALMEM,31160)
    assign redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_ia = $unsigned(redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_inputreg0_q);
    assign redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_aa = redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_wraddr_q;
    assign redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_ab = redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_aa),
        .data_a(redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_ab),
        .q_b(redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_q = redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_iq[15:0];

    // redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_outputreg0(DELAY,31159)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_outputreg0_q <= $unsigned(redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28097)@29 + 5
    // out q@35
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344(ADD,8543)@35
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod96_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_b = $unsigned({{5{i_shl_i_i_i_i_i_i_11_c_compstr343_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_11_c_compstr343_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_o[33:0];

    // rightShiftStage0_uid15651_dupName_45_i_unnamed_c_compstr0_shift_x(MUX,15650)@35
    assign rightShiftStage0_uid15651_dupName_45_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15651_dupName_45_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_q or rightShiftStage0Idx1_uid15649_dupName_45_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15651_dupName_45_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15651_dupName_45_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_q;
            1'b1 : rightShiftStage0_uid15651_dupName_45_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15649_dupName_45_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15651_dupName_45_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15656_dupName_45_i_unnamed_c_compstr0_shift_x(MUX,15655)@35
    assign rightShiftStage1_uid15656_dupName_45_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15656_dupName_45_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15651_dupName_45_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15654_dupName_45_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15656_dupName_45_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15656_dupName_45_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15651_dupName_45_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15656_dupName_45_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15654_dupName_45_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15656_dupName_45_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15661_dupName_45_i_unnamed_c_compstr0_shift_x(MUX,15660)@35
    assign rightShiftStage2_uid15661_dupName_45_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15661_dupName_45_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15656_dupName_45_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15659_dupName_45_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15661_dupName_45_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15661_dupName_45_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15656_dupName_45_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15661_dupName_45_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15659_dupName_45_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15661_dupName_45_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr345_vt_select_20(BITSELECT,11939)@35
    assign i_unnamed_c_compstr345_vt_select_20_b = rightShiftStage2_uid15661_dupName_45_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr345_vt_join(BITJOIN,11938)@35
    assign i_unnamed_c_compstr345_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr345_vt_select_20_b};

    // i_conv_i_i_i_i_i_11_c_compstr346_sel_x(BITSELECT,3734)@35
    assign i_conv_i_i_i_i_i_11_c_compstr346_sel_x_b = i_unnamed_c_compstr345_vt_join_q[15:0];

    // redist1131_i_conv_i_i_i_i_i_11_c_compstr346_sel_x_b_1(DELAY,29359)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1131_i_conv_i_i_i_i_i_11_c_compstr346_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_11_c_compstr346_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15670_dupName_46_i_unnamed_c_compstr0_shift_x(BITSELECT,15669)@35
    assign rightShiftStage1Idx1Rng8_uid15670_dupName_46_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15669_dupName_46_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15672_dupName_46_i_unnamed_c_compstr0_shift_x(BITJOIN,15671)@35
    assign rightShiftStage1Idx1_uid15672_dupName_46_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15670_dupName_46_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15665_dupName_46_i_unnamed_c_compstr0_shift_x(BITSELECT,15664)@35
    assign rightShiftStage0Idx1Rng4_uid15665_dupName_46_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_q[33:4];

    // rightShiftStage0Idx1_uid15667_dupName_46_i_unnamed_c_compstr0_shift_x(BITJOIN,15666)@35
    assign rightShiftStage0Idx1_uid15667_dupName_46_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15665_dupName_46_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15669_dupName_46_i_unnamed_c_compstr0_shift_x(MUX,15668)@35
    assign rightShiftStage0_uid15669_dupName_46_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15669_dupName_46_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_q or rightShiftStage0Idx1_uid15667_dupName_46_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15669_dupName_46_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15669_dupName_46_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compstr344_q;
            1'b1 : rightShiftStage0_uid15669_dupName_46_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15667_dupName_46_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15669_dupName_46_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15674_dupName_46_i_unnamed_c_compstr0_shift_x(MUX,15673)@35
    assign rightShiftStage1_uid15674_dupName_46_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15674_dupName_46_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15669_dupName_46_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15672_dupName_46_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15674_dupName_46_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15674_dupName_46_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15669_dupName_46_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15674_dupName_46_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15672_dupName_46_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15674_dupName_46_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr347_vt_select_21(BITSELECT,11953)@35
    assign i_unnamed_c_compstr347_vt_select_21_b = rightShiftStage1_uid15674_dupName_46_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr347_vt_join(BITJOIN,11952)@35
    assign i_unnamed_c_compstr347_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr347_vt_select_21_b};

    // i_unnamed_c_compstr348_sel_x(BITSELECT,6230)@35
    assign i_unnamed_c_compstr348_sel_x_b = i_unnamed_c_compstr347_vt_join_q[15:0];

    // i_unnamed_c_compstr349_BitSelect_for_a(BITSELECT,27851)@35
    assign i_unnamed_c_compstr349_BitSelect_for_a_b = i_unnamed_c_compstr348_sel_x_b[0:0];

    // i_unnamed_c_compstr349_join(BITJOIN,27852)@35
    assign i_unnamed_c_compstr349_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr349_BitSelect_for_a_b};

    // i_unnamed_c_compstr349_vt_select_0(BITSELECT,11980)@35
    assign i_unnamed_c_compstr349_vt_select_0_b = i_unnamed_c_compstr349_join_q[0:0];

    // redist59_i_unnamed_c_compstr349_vt_select_0_b_1(DELAY,28287)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist59_i_unnamed_c_compstr349_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr349_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr349_vt_join(BITJOIN,11979)@36
    assign i_unnamed_c_compstr349_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist59_i_unnamed_c_compstr349_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_11_c_compstr350(ADD,7001)@36
    assign i_add_i_i_i_i_i_i_11_c_compstr350_a = {1'b0, i_unnamed_c_compstr349_vt_join_q};
    assign i_add_i_i_i_i_i_i_11_c_compstr350_b = {1'b0, redist1131_i_conv_i_i_i_i_i_11_c_compstr346_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_11_c_compstr350_o = $unsigned(i_add_i_i_i_i_i_i_11_c_compstr350_a) + $unsigned(i_add_i_i_i_i_i_i_11_c_compstr350_b);
    assign i_add_i_i_i_i_i_i_11_c_compstr350_q = i_add_i_i_i_i_i_i_11_c_compstr350_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_11_c_compstr350_sel_x(BITSELECT,2195)@36
    assign bgTrunc_i_add_i_i_i_i_i_i_11_c_compstr350_sel_x_b = i_add_i_i_i_i_i_i_11_c_compstr350_q[15:0];

    // i_conv_i_i_i_i_i_i279_12_c_compstr370_sel_x(BITSELECT,3871)@36
    assign i_conv_i_i_i_i_i_i279_12_c_compstr370_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_11_c_compstr350_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_12_c_compstr370_vt_select_15(BITSELECT,8001)@36
    assign i_conv_i_i_i_i_i_i279_12_c_compstr370_vt_select_15_b = i_conv_i_i_i_i_i_i279_12_c_compstr370_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_12_c_compstr370_vt_join(BITJOIN,8000)@36
    assign i_conv_i_i_i_i_i_i279_12_c_compstr370_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_12_c_compstr370_vt_select_15_b};

    // leftShiftStage0_uid25700_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x(MUX,25699)@36
    assign leftShiftStage0_uid25700_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25700_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_12_c_compstr370_vt_join_q or leftShiftStage0Idx1_uid25698_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25700_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25700_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_12_c_compstr370_vt_join_q;
            1'b1 : leftShiftStage0_uid25700_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25698_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25700_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25705_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x(MUX,25704)@36
    assign leftShiftStage1_uid25705_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25705_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_s or leftShiftStage0_uid25700_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25703_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25705_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25705_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q = leftShiftStage0_uid25700_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25705_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25703_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25705_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25710_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x(MUX,25709)@36
    assign leftShiftStage2_uid25710_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25710_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_s or leftShiftStage1_uid25705_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25708_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25710_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25710_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q = leftShiftStage1_uid25705_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25710_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25708_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25710_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_12_c_compstr371_vt_select_28(BITSELECT,9514)@36
    assign i_shl_i_i_i_i_i_i_12_c_compstr371_vt_select_28_b = leftShiftStage2_uid25710_i_shl_i_i_i_i_i_i_12_c_compstr0_shift_x_q[28:13];

    // redist352_i_shl_i_i_i_i_i_i_12_c_compstr371_vt_select_28_b_1(DELAY,28580)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist352_i_shl_i_i_i_i_i_i_12_c_compstr371_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_12_c_compstr371_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_12_c_compstr371_vt_join(BITJOIN,9513)@37
    assign i_shl_i_i_i_i_i_i_12_c_compstr371_vt_join_q = {redist352_i_shl_i_i_i_i_i_i_12_c_compstr371_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_rdcnt(ADD,31181)
    assign redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_a = {1'b0, redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_wraddr_q};
    assign redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_b = {1'b0, c_i5_143648_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_o <= $unsigned(redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_a) + $unsigned(redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_b);
        end
    end
    assign redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_q = redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_o[5:0];

    // redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_inputreg0(DELAY,31176)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl);
        end
    end

    // redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_wraddr(COUNTER,31179)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_wraddr_i <= $unsigned(redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_wraddr_q = redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_wraddr_i[4:0];

    // redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem(DUALMEM,31178)
    assign redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_ia = $unsigned(redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_inputreg0_q);
    assign redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_aa = redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_wraddr_q;
    assign redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_ab = redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_aa),
        .data_a(redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_ab),
        .q_b(redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_q = redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_iq[15:0];

    // redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_outputreg0(DELAY,31177)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_outputreg0_q <= $unsigned(redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_mem_q);
        end
    end

    // redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_rdcnt(ADD,29733)
    assign redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_a = {1'b0, redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_wraddr_q};
    assign redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_b = {1'b0, c_i5_143648_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_o <= $unsigned(redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_a) + $unsigned(redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_b);
        end
    end
    assign redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_q = redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_o[5:0];

    // redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_inputreg0(DELAY,29728)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl);
        end
    end

    // redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_wraddr(COUNTER,29731)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_wraddr_i <= $unsigned(redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_wraddr_q = redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_wraddr_i[4:0];

    // redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem(DUALMEM,29730)
    assign redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_ia = $unsigned(redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_inputreg0_q);
    assign redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_aa = redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_wraddr_q;
    assign redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_ab = redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_aa),
        .data_a(redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_ab),
        .q_b(redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_q = redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_iq[15:0];

    // redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_outputreg0(DELAY,29729)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_outputreg0_q <= $unsigned(redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_mem_q);
        end
    end

    // redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_rdcnt(ADD,29739)
    assign redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_a = {1'b0, redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_wraddr_q};
    assign redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_b = {1'b0, c_i5_143648_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_o <= $unsigned(redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_a) + $unsigned(redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_b);
        end
    end
    assign redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_q = redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_o[5:0];

    // redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_inputreg0(DELAY,29734)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl);
        end
    end

    // redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_wraddr(COUNTER,29737)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_wraddr_i <= $unsigned(redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_wraddr_q = redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_wraddr_i[4:0];

    // redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem(DUALMEM,29736)
    assign redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_ia = $unsigned(redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_inputreg0_q);
    assign redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_aa = redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_wraddr_q;
    assign redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_ab = redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_aa),
        .data_a(redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_ab),
        .q_b(redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_q = redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_iq[15:0];

    // redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_outputreg0(DELAY,29735)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_outputreg0_q <= $unsigned(redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_mem_q);
        end
    end

    // redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_rdcnt(ADD,31175)
    assign redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_a = {1'b0, redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_wraddr_q};
    assign redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_b = {1'b0, c_i5_143648_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_o <= $unsigned(redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_a) + $unsigned(redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_b);
        end
    end
    assign redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_q = redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_o[5:0];

    // redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_inputreg0(DELAY,31170)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl);
        end
    end

    // redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_wraddr(COUNTER,31173)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_wraddr_i <= $unsigned(redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_wraddr_q = redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_wraddr_i[4:0];

    // redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem(DUALMEM,31172)
    assign redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_ia = $unsigned(redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_inputreg0_q);
    assign redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_aa = redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_wraddr_q;
    assign redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_ab = redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_aa),
        .data_a(redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_ab),
        .q_b(redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_q = redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_iq[15:0];

    // redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_outputreg0(DELAY,31171)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_outputreg0_q <= $unsigned(redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27971)@31 + 5
    // out q@37
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372(ADD,8552)@37
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod101_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_b = $unsigned({{5{i_shl_i_i_i_i_i_i_12_c_compstr371_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_12_c_compstr371_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_o[33:0];

    // rightShiftStage0_uid15713_dupName_49_i_unnamed_c_compstr0_shift_x(MUX,15712)@37
    assign rightShiftStage0_uid15713_dupName_49_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15713_dupName_49_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_q or rightShiftStage0Idx1_uid15711_dupName_49_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15713_dupName_49_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15713_dupName_49_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_q;
            1'b1 : rightShiftStage0_uid15713_dupName_49_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15711_dupName_49_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15713_dupName_49_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15718_dupName_49_i_unnamed_c_compstr0_shift_x(MUX,15717)@37
    assign rightShiftStage1_uid15718_dupName_49_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15718_dupName_49_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15713_dupName_49_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15716_dupName_49_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15718_dupName_49_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15718_dupName_49_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15713_dupName_49_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15718_dupName_49_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15716_dupName_49_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15718_dupName_49_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15723_dupName_49_i_unnamed_c_compstr0_shift_x(MUX,15722)@37
    assign rightShiftStage2_uid15723_dupName_49_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15723_dupName_49_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15718_dupName_49_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15721_dupName_49_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15723_dupName_49_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15723_dupName_49_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15718_dupName_49_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15723_dupName_49_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15721_dupName_49_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15723_dupName_49_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr373_vt_select_20(BITSELECT,12071)@37
    assign i_unnamed_c_compstr373_vt_select_20_b = rightShiftStage2_uid15723_dupName_49_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr373_vt_join(BITJOIN,12070)@37
    assign i_unnamed_c_compstr373_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr373_vt_select_20_b};

    // i_conv_i_i_i_i_i_12_c_compstr374_sel_x(BITSELECT,3743)@37
    assign i_conv_i_i_i_i_i_12_c_compstr374_sel_x_b = i_unnamed_c_compstr373_vt_join_q[15:0];

    // redist1122_i_conv_i_i_i_i_i_12_c_compstr374_sel_x_b_1(DELAY,29350)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1122_i_conv_i_i_i_i_i_12_c_compstr374_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_12_c_compstr374_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15732_dupName_50_i_unnamed_c_compstr0_shift_x(BITSELECT,15731)@37
    assign rightShiftStage1Idx1Rng8_uid15732_dupName_50_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15731_dupName_50_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15734_dupName_50_i_unnamed_c_compstr0_shift_x(BITJOIN,15733)@37
    assign rightShiftStage1Idx1_uid15734_dupName_50_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15732_dupName_50_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15727_dupName_50_i_unnamed_c_compstr0_shift_x(BITSELECT,15726)@37
    assign rightShiftStage0Idx1Rng4_uid15727_dupName_50_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_q[33:4];

    // rightShiftStage0Idx1_uid15729_dupName_50_i_unnamed_c_compstr0_shift_x(BITJOIN,15728)@37
    assign rightShiftStage0Idx1_uid15729_dupName_50_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15727_dupName_50_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15731_dupName_50_i_unnamed_c_compstr0_shift_x(MUX,15730)@37
    assign rightShiftStage0_uid15731_dupName_50_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15731_dupName_50_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_q or rightShiftStage0Idx1_uid15729_dupName_50_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15731_dupName_50_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15731_dupName_50_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compstr372_q;
            1'b1 : rightShiftStage0_uid15731_dupName_50_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15729_dupName_50_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15731_dupName_50_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15736_dupName_50_i_unnamed_c_compstr0_shift_x(MUX,15735)@37
    assign rightShiftStage1_uid15736_dupName_50_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15736_dupName_50_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15731_dupName_50_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15734_dupName_50_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15736_dupName_50_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15736_dupName_50_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15731_dupName_50_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15736_dupName_50_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15734_dupName_50_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15736_dupName_50_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr375_vt_select_21(BITSELECT,12074)@37
    assign i_unnamed_c_compstr375_vt_select_21_b = rightShiftStage1_uid15736_dupName_50_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr375_vt_join(BITJOIN,12073)@37
    assign i_unnamed_c_compstr375_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr375_vt_select_21_b};

    // i_unnamed_c_compstr376_sel_x(BITSELECT,6241)@37
    assign i_unnamed_c_compstr376_sel_x_b = i_unnamed_c_compstr375_vt_join_q[15:0];

    // i_unnamed_c_compstr377_BitSelect_for_a(BITSELECT,27871)@37
    assign i_unnamed_c_compstr377_BitSelect_for_a_b = i_unnamed_c_compstr376_sel_x_b[0:0];

    // i_unnamed_c_compstr377_join(BITJOIN,27872)@37
    assign i_unnamed_c_compstr377_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr377_BitSelect_for_a_b};

    // i_unnamed_c_compstr377_vt_select_0(BITSELECT,12079)@37
    assign i_unnamed_c_compstr377_vt_select_0_b = i_unnamed_c_compstr377_join_q[0:0];

    // redist50_i_unnamed_c_compstr377_vt_select_0_b_1(DELAY,28278)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist50_i_unnamed_c_compstr377_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr377_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr377_vt_join(BITJOIN,12078)@38
    assign i_unnamed_c_compstr377_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist50_i_unnamed_c_compstr377_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_12_c_compstr378(ADD,7010)@38
    assign i_add_i_i_i_i_i_i_12_c_compstr378_a = {1'b0, i_unnamed_c_compstr377_vt_join_q};
    assign i_add_i_i_i_i_i_i_12_c_compstr378_b = {1'b0, redist1122_i_conv_i_i_i_i_i_12_c_compstr374_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_12_c_compstr378_o = $unsigned(i_add_i_i_i_i_i_i_12_c_compstr378_a) + $unsigned(i_add_i_i_i_i_i_i_12_c_compstr378_b);
    assign i_add_i_i_i_i_i_i_12_c_compstr378_q = i_add_i_i_i_i_i_i_12_c_compstr378_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_12_c_compstr378_sel_x(BITSELECT,2204)@38
    assign bgTrunc_i_add_i_i_i_i_i_i_12_c_compstr378_sel_x_b = i_add_i_i_i_i_i_i_12_c_compstr378_q[15:0];

    // i_conv_i_i_i_i_i_i279_13_c_compstr398_sel_x(BITSELECT,3872)@38
    assign i_conv_i_i_i_i_i_i279_13_c_compstr398_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_12_c_compstr378_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_13_c_compstr398_vt_select_15(BITSELECT,8005)@38
    assign i_conv_i_i_i_i_i_i279_13_c_compstr398_vt_select_15_b = i_conv_i_i_i_i_i_i279_13_c_compstr398_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_13_c_compstr398_vt_join(BITJOIN,8004)@38
    assign i_conv_i_i_i_i_i_i279_13_c_compstr398_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_13_c_compstr398_vt_select_15_b};

    // leftShiftStage0_uid25718_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x(MUX,25717)@38
    assign leftShiftStage0_uid25718_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25718_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_13_c_compstr398_vt_join_q or leftShiftStage0Idx1_uid25716_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25718_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25718_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_13_c_compstr398_vt_join_q;
            1'b1 : leftShiftStage0_uid25718_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25716_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25718_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25723_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x(MUX,25722)@38
    assign leftShiftStage1_uid25723_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25723_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_s or leftShiftStage0_uid25718_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25721_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25723_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25723_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q = leftShiftStage0_uid25718_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25723_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25721_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25723_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25728_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x(MUX,25727)@38
    assign leftShiftStage2_uid25728_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25728_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_s or leftShiftStage1_uid25723_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25726_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25728_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25728_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q = leftShiftStage1_uid25723_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25728_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25726_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25728_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_13_c_compstr399_vt_select_28(BITSELECT,9517)@38
    assign i_shl_i_i_i_i_i_i_13_c_compstr399_vt_select_28_b = leftShiftStage2_uid25728_i_shl_i_i_i_i_i_i_13_c_compstr0_shift_x_q[28:13];

    // redist351_i_shl_i_i_i_i_i_i_13_c_compstr399_vt_select_28_b_1(DELAY,28579)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist351_i_shl_i_i_i_i_i_i_13_c_compstr399_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_13_c_compstr399_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_13_c_compstr399_vt_join(BITJOIN,9516)@39
    assign i_shl_i_i_i_i_i_i_13_c_compstr399_vt_join_q = {redist351_i_shl_i_i_i_i_i_i_13_c_compstr399_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_offset(CONSTANT,29744)
    assign redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_offset_q = $unsigned(5'b01100);

    // redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_rdcnt(ADD,31193)
    assign redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_a = {1'b0, redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_wraddr_q};
    assign redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_b = {1'b0, redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_o <= $unsigned(redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_a) + $unsigned(redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_b);
        end
    end
    assign redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_q = redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_o[5:0];

    // redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_inputreg0(DELAY,31188)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl);
        end
    end

    // redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_wraddr(COUNTER,31191)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_wraddr_i <= $unsigned(redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_wraddr_q = redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_wraddr_i[4:0];

    // redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem(DUALMEM,31190)
    assign redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_ia = $unsigned(redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_inputreg0_q);
    assign redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_aa = redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_wraddr_q;
    assign redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_ab = redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_aa),
        .data_a(redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_ab),
        .q_b(redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_q = redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_iq[15:0];

    // redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_outputreg0(DELAY,31189)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_outputreg0_q <= $unsigned(redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_mem_q);
        end
    end

    // redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_rdcnt(ADD,29745)
    assign redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_a = {1'b0, redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_wraddr_q};
    assign redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_b = {1'b0, redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_o <= $unsigned(redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_a) + $unsigned(redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_b);
        end
    end
    assign redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_q = redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_o[5:0];

    // redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_inputreg0(DELAY,29740)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl);
        end
    end

    // redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_wraddr(COUNTER,29743)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_wraddr_i <= $unsigned(redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_wraddr_q = redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_wraddr_i[4:0];

    // redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem(DUALMEM,29742)
    assign redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_ia = $unsigned(redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_inputreg0_q);
    assign redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_aa = redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_wraddr_q;
    assign redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_ab = redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_aa),
        .data_a(redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_ab),
        .q_b(redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_q = redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_iq[15:0];

    // redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_outputreg0(DELAY,29741)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_outputreg0_q <= $unsigned(redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_mem_q);
        end
    end

    // redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_rdcnt(ADD,29751)
    assign redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_a = {1'b0, redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_wraddr_q};
    assign redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_b = {1'b0, redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_o <= $unsigned(redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_a) + $unsigned(redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_b);
        end
    end
    assign redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_q = redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_o[5:0];

    // redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_inputreg0(DELAY,29746)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl);
        end
    end

    // redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_wraddr(COUNTER,29749)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_wraddr_i <= $unsigned(redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_wraddr_q = redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_wraddr_i[4:0];

    // redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem(DUALMEM,29748)
    assign redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_ia = $unsigned(redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_inputreg0_q);
    assign redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_aa = redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_wraddr_q;
    assign redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_ab = redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_aa),
        .data_a(redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_ab),
        .q_b(redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_q = redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_iq[15:0];

    // redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_outputreg0(DELAY,29747)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_outputreg0_q <= $unsigned(redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_mem_q);
        end
    end

    // redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_rdcnt(ADD,31187)
    assign redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_a = {1'b0, redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_wraddr_q};
    assign redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_b = {1'b0, redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_o <= $unsigned(redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_a) + $unsigned(redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_b);
        end
    end
    assign redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_q = redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_o[5:0];

    // redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_inputreg0(DELAY,31182)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl);
        end
    end

    // redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_wraddr(COUNTER,31185)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_wraddr_i <= $unsigned(redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_wraddr_q = redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_wraddr_i[4:0];

    // redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem(DUALMEM,31184)
    assign redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_ia = $unsigned(redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_inputreg0_q);
    assign redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_aa = redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_wraddr_q;
    assign redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_ab = redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_aa),
        .data_a(redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_ab),
        .q_b(redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_q = redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_iq[15:0];

    // redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_outputreg0(DELAY,31183)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_outputreg0_q <= $unsigned(redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27972)@33 + 5
    // out q@39
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400(ADD,8553)@39
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod106_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_b = $unsigned({{5{i_shl_i_i_i_i_i_i_13_c_compstr399_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_13_c_compstr399_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_o[33:0];

    // rightShiftStage0_uid15775_dupName_53_i_unnamed_c_compstr0_shift_x(MUX,15774)@39
    assign rightShiftStage0_uid15775_dupName_53_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15775_dupName_53_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_q or rightShiftStage0Idx1_uid15773_dupName_53_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15775_dupName_53_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15775_dupName_53_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_q;
            1'b1 : rightShiftStage0_uid15775_dupName_53_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15773_dupName_53_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15775_dupName_53_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15780_dupName_53_i_unnamed_c_compstr0_shift_x(MUX,15779)@39
    assign rightShiftStage1_uid15780_dupName_53_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15780_dupName_53_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15775_dupName_53_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15778_dupName_53_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15780_dupName_53_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15780_dupName_53_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15775_dupName_53_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15780_dupName_53_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15778_dupName_53_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15780_dupName_53_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15785_dupName_53_i_unnamed_c_compstr0_shift_x(MUX,15784)@39
    assign rightShiftStage2_uid15785_dupName_53_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15785_dupName_53_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15780_dupName_53_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15783_dupName_53_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15785_dupName_53_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15785_dupName_53_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15780_dupName_53_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15785_dupName_53_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15783_dupName_53_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15785_dupName_53_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr401_vt_select_20(BITSELECT,12099)@39
    assign i_unnamed_c_compstr401_vt_select_20_b = rightShiftStage2_uid15785_dupName_53_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr401_vt_join(BITJOIN,12098)@39
    assign i_unnamed_c_compstr401_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr401_vt_select_20_b};

    // i_conv_i_i_i_i_i_13_c_compstr402_sel_x(BITSELECT,3744)@39
    assign i_conv_i_i_i_i_i_13_c_compstr402_sel_x_b = i_unnamed_c_compstr401_vt_join_q[15:0];

    // redist1121_i_conv_i_i_i_i_i_13_c_compstr402_sel_x_b_1(DELAY,29349)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1121_i_conv_i_i_i_i_i_13_c_compstr402_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_13_c_compstr402_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15794_dupName_54_i_unnamed_c_compstr0_shift_x(BITSELECT,15793)@39
    assign rightShiftStage1Idx1Rng8_uid15794_dupName_54_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15793_dupName_54_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15796_dupName_54_i_unnamed_c_compstr0_shift_x(BITJOIN,15795)@39
    assign rightShiftStage1Idx1_uid15796_dupName_54_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15794_dupName_54_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15789_dupName_54_i_unnamed_c_compstr0_shift_x(BITSELECT,15788)@39
    assign rightShiftStage0Idx1Rng4_uid15789_dupName_54_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_q[33:4];

    // rightShiftStage0Idx1_uid15791_dupName_54_i_unnamed_c_compstr0_shift_x(BITJOIN,15790)@39
    assign rightShiftStage0Idx1_uid15791_dupName_54_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15789_dupName_54_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15793_dupName_54_i_unnamed_c_compstr0_shift_x(MUX,15792)@39
    assign rightShiftStage0_uid15793_dupName_54_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15793_dupName_54_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_q or rightShiftStage0Idx1_uid15791_dupName_54_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15793_dupName_54_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15793_dupName_54_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compstr400_q;
            1'b1 : rightShiftStage0_uid15793_dupName_54_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15791_dupName_54_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15793_dupName_54_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15798_dupName_54_i_unnamed_c_compstr0_shift_x(MUX,15797)@39
    assign rightShiftStage1_uid15798_dupName_54_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15798_dupName_54_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15793_dupName_54_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15796_dupName_54_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15798_dupName_54_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15798_dupName_54_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15793_dupName_54_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15798_dupName_54_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15796_dupName_54_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15798_dupName_54_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr403_vt_select_21(BITSELECT,12102)@39
    assign i_unnamed_c_compstr403_vt_select_21_b = rightShiftStage1_uid15798_dupName_54_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr403_vt_join(BITJOIN,12101)@39
    assign i_unnamed_c_compstr403_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr403_vt_select_21_b};

    // i_unnamed_c_compstr404_sel_x(BITSELECT,6244)@39
    assign i_unnamed_c_compstr404_sel_x_b = i_unnamed_c_compstr403_vt_join_q[15:0];

    // i_unnamed_c_compstr405_BitSelect_for_a(BITSELECT,27875)@39
    assign i_unnamed_c_compstr405_BitSelect_for_a_b = i_unnamed_c_compstr404_sel_x_b[0:0];

    // i_unnamed_c_compstr405_join(BITJOIN,27876)@39
    assign i_unnamed_c_compstr405_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr405_BitSelect_for_a_b};

    // i_unnamed_c_compstr405_vt_select_0(BITSELECT,12107)@39
    assign i_unnamed_c_compstr405_vt_select_0_b = i_unnamed_c_compstr405_join_q[0:0];

    // redist48_i_unnamed_c_compstr405_vt_select_0_b_1(DELAY,28276)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist48_i_unnamed_c_compstr405_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr405_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr405_vt_join(BITJOIN,12106)@40
    assign i_unnamed_c_compstr405_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist48_i_unnamed_c_compstr405_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_13_c_compstr406(ADD,7011)@40
    assign i_add_i_i_i_i_i_i_13_c_compstr406_a = {1'b0, i_unnamed_c_compstr405_vt_join_q};
    assign i_add_i_i_i_i_i_i_13_c_compstr406_b = {1'b0, redist1121_i_conv_i_i_i_i_i_13_c_compstr402_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_13_c_compstr406_o = $unsigned(i_add_i_i_i_i_i_i_13_c_compstr406_a) + $unsigned(i_add_i_i_i_i_i_i_13_c_compstr406_b);
    assign i_add_i_i_i_i_i_i_13_c_compstr406_q = i_add_i_i_i_i_i_i_13_c_compstr406_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_13_c_compstr406_sel_x(BITSELECT,2205)@40
    assign bgTrunc_i_add_i_i_i_i_i_i_13_c_compstr406_sel_x_b = i_add_i_i_i_i_i_i_13_c_compstr406_q[15:0];

    // i_conv_i_i_i_i_i_i279_14_c_compstr426_sel_x(BITSELECT,3873)@40
    assign i_conv_i_i_i_i_i_i279_14_c_compstr426_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_13_c_compstr406_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_14_c_compstr426_vt_select_15(BITSELECT,8009)@40
    assign i_conv_i_i_i_i_i_i279_14_c_compstr426_vt_select_15_b = i_conv_i_i_i_i_i_i279_14_c_compstr426_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_14_c_compstr426_vt_join(BITJOIN,8008)@40
    assign i_conv_i_i_i_i_i_i279_14_c_compstr426_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_14_c_compstr426_vt_select_15_b};

    // leftShiftStage0_uid25736_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x(MUX,25735)@40
    assign leftShiftStage0_uid25736_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25736_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_14_c_compstr426_vt_join_q or leftShiftStage0Idx1_uid25734_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25736_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25736_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_14_c_compstr426_vt_join_q;
            1'b1 : leftShiftStage0_uid25736_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25734_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25736_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25741_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x(MUX,25740)@40
    assign leftShiftStage1_uid25741_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25741_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_s or leftShiftStage0_uid25736_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25739_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25741_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25741_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q = leftShiftStage0_uid25736_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25741_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25739_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25741_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25746_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x(MUX,25745)@40
    assign leftShiftStage2_uid25746_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25746_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_s or leftShiftStage1_uid25741_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25744_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25746_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25746_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q = leftShiftStage1_uid25741_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25746_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25744_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25746_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_14_c_compstr427_vt_select_28(BITSELECT,9520)@40
    assign i_shl_i_i_i_i_i_i_14_c_compstr427_vt_select_28_b = leftShiftStage2_uid25746_i_shl_i_i_i_i_i_i_14_c_compstr0_shift_x_q[28:13];

    // redist350_i_shl_i_i_i_i_i_i_14_c_compstr427_vt_select_28_b_1(DELAY,28578)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist350_i_shl_i_i_i_i_i_i_14_c_compstr427_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_14_c_compstr427_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_14_c_compstr427_vt_join(BITJOIN,9519)@41
    assign i_shl_i_i_i_i_i_i_14_c_compstr427_vt_join_q = {redist350_i_shl_i_i_i_i_i_i_14_c_compstr427_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_offset(CONSTANT,29756)
    assign redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_offset_q = $unsigned(5'b01010);

    // redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_rdcnt(ADD,31205)
    assign redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_a = {1'b0, redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_wraddr_q};
    assign redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_b = {1'b0, redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_o <= $unsigned(redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_a) + $unsigned(redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_b);
        end
    end
    assign redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_q = redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_o[5:0];

    // redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_inputreg0(DELAY,31200)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl);
        end
    end

    // redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_wraddr(COUNTER,31203)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_wraddr_i <= $unsigned(redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_wraddr_q = redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_wraddr_i[4:0];

    // redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem(DUALMEM,31202)
    assign redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_ia = $unsigned(redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_inputreg0_q);
    assign redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_aa = redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_wraddr_q;
    assign redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_ab = redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_aa),
        .data_a(redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_ab),
        .q_b(redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_q = redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_iq[15:0];

    // redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_outputreg0(DELAY,31201)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_outputreg0_q <= $unsigned(redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_mem_q);
        end
    end

    // redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_rdcnt(ADD,29757)
    assign redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_a = {1'b0, redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_wraddr_q};
    assign redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_b = {1'b0, redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_o <= $unsigned(redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_a) + $unsigned(redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_b);
        end
    end
    assign redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_q = redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_o[5:0];

    // redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_inputreg0(DELAY,29752)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl);
        end
    end

    // redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_wraddr(COUNTER,29755)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_wraddr_i <= $unsigned(redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_wraddr_q = redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_wraddr_i[4:0];

    // redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem(DUALMEM,29754)
    assign redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_ia = $unsigned(redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_inputreg0_q);
    assign redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_aa = redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_wraddr_q;
    assign redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_ab = redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_aa),
        .data_a(redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_ab),
        .q_b(redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_q = redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_iq[15:0];

    // redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_outputreg0(DELAY,29753)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_outputreg0_q <= $unsigned(redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_mem_q);
        end
    end

    // redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_rdcnt(ADD,29763)
    assign redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_a = {1'b0, redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_wraddr_q};
    assign redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_b = {1'b0, redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_o <= $unsigned(redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_a) + $unsigned(redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_b);
        end
    end
    assign redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_q = redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_o[5:0];

    // redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_inputreg0(DELAY,29758)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl);
        end
    end

    // redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_wraddr(COUNTER,29761)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_wraddr_i <= $unsigned(redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_wraddr_q = redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_wraddr_i[4:0];

    // redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem(DUALMEM,29760)
    assign redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_ia = $unsigned(redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_inputreg0_q);
    assign redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_aa = redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_wraddr_q;
    assign redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_ab = redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_aa),
        .data_a(redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_ab),
        .q_b(redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_q = redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_iq[15:0];

    // redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_outputreg0(DELAY,29759)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_outputreg0_q <= $unsigned(redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_mem_q);
        end
    end

    // redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_rdcnt(ADD,31199)
    assign redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_a = {1'b0, redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_wraddr_q};
    assign redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_b = {1'b0, redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_o <= $unsigned(redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_a) + $unsigned(redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_b);
        end
    end
    assign redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_q = redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_o[5:0];

    // redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_inputreg0(DELAY,31194)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl);
        end
    end

    // redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_wraddr(COUNTER,31197)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_wraddr_i <= $unsigned(redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_wraddr_q = redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_wraddr_i[4:0];

    // redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem(DUALMEM,31196)
    assign redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_ia = $unsigned(redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_inputreg0_q);
    assign redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_aa = redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_wraddr_q;
    assign redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_ab = redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_aa),
        .data_a(redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_ab),
        .q_b(redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_q = redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_iq[15:0];

    // redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_outputreg0(DELAY,31195)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_outputreg0_q <= $unsigned(redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27973)@35 + 5
    // out q@41
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428(ADD,8554)@41
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod111_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_b = $unsigned({{5{i_shl_i_i_i_i_i_i_14_c_compstr427_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_14_c_compstr427_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_o[33:0];

    // rightShiftStage0_uid15837_dupName_57_i_unnamed_c_compstr0_shift_x(MUX,15836)@41
    assign rightShiftStage0_uid15837_dupName_57_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15837_dupName_57_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_q or rightShiftStage0Idx1_uid15835_dupName_57_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15837_dupName_57_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15837_dupName_57_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_q;
            1'b1 : rightShiftStage0_uid15837_dupName_57_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15835_dupName_57_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15837_dupName_57_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15842_dupName_57_i_unnamed_c_compstr0_shift_x(MUX,15841)@41
    assign rightShiftStage1_uid15842_dupName_57_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15842_dupName_57_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15837_dupName_57_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15840_dupName_57_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15842_dupName_57_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15842_dupName_57_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15837_dupName_57_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15842_dupName_57_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15840_dupName_57_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15842_dupName_57_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15847_dupName_57_i_unnamed_c_compstr0_shift_x(MUX,15846)@41
    assign rightShiftStage2_uid15847_dupName_57_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15847_dupName_57_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15842_dupName_57_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15845_dupName_57_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15847_dupName_57_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15847_dupName_57_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15842_dupName_57_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15847_dupName_57_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15845_dupName_57_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15847_dupName_57_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr429_vt_select_20(BITSELECT,12126)@41
    assign i_unnamed_c_compstr429_vt_select_20_b = rightShiftStage2_uid15847_dupName_57_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr429_vt_join(BITJOIN,12125)@41
    assign i_unnamed_c_compstr429_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr429_vt_select_20_b};

    // i_conv_i_i_i_i_i_14_c_compstr430_sel_x(BITSELECT,3745)@41
    assign i_conv_i_i_i_i_i_14_c_compstr430_sel_x_b = i_unnamed_c_compstr429_vt_join_q[15:0];

    // redist1120_i_conv_i_i_i_i_i_14_c_compstr430_sel_x_b_1(DELAY,29348)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1120_i_conv_i_i_i_i_i_14_c_compstr430_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_14_c_compstr430_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15856_dupName_58_i_unnamed_c_compstr0_shift_x(BITSELECT,15855)@41
    assign rightShiftStage1Idx1Rng8_uid15856_dupName_58_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15855_dupName_58_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15858_dupName_58_i_unnamed_c_compstr0_shift_x(BITJOIN,15857)@41
    assign rightShiftStage1Idx1_uid15858_dupName_58_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15856_dupName_58_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15851_dupName_58_i_unnamed_c_compstr0_shift_x(BITSELECT,15850)@41
    assign rightShiftStage0Idx1Rng4_uid15851_dupName_58_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_q[33:4];

    // rightShiftStage0Idx1_uid15853_dupName_58_i_unnamed_c_compstr0_shift_x(BITJOIN,15852)@41
    assign rightShiftStage0Idx1_uid15853_dupName_58_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15851_dupName_58_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15855_dupName_58_i_unnamed_c_compstr0_shift_x(MUX,15854)@41
    assign rightShiftStage0_uid15855_dupName_58_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15855_dupName_58_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_q or rightShiftStage0Idx1_uid15853_dupName_58_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15855_dupName_58_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15855_dupName_58_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compstr428_q;
            1'b1 : rightShiftStage0_uid15855_dupName_58_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15853_dupName_58_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15855_dupName_58_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15860_dupName_58_i_unnamed_c_compstr0_shift_x(MUX,15859)@41
    assign rightShiftStage1_uid15860_dupName_58_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15860_dupName_58_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15855_dupName_58_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15858_dupName_58_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15860_dupName_58_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15860_dupName_58_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15855_dupName_58_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15860_dupName_58_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15858_dupName_58_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15860_dupName_58_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr431_vt_select_21(BITSELECT,12129)@41
    assign i_unnamed_c_compstr431_vt_select_21_b = rightShiftStage1_uid15860_dupName_58_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr431_vt_join(BITJOIN,12128)@41
    assign i_unnamed_c_compstr431_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr431_vt_select_21_b};

    // i_unnamed_c_compstr432_sel_x(BITSELECT,6246)@41
    assign i_unnamed_c_compstr432_sel_x_b = i_unnamed_c_compstr431_vt_join_q[15:0];

    // i_unnamed_c_compstr433_BitSelect_for_a(BITSELECT,27881)@41
    assign i_unnamed_c_compstr433_BitSelect_for_a_b = i_unnamed_c_compstr432_sel_x_b[0:0];

    // i_unnamed_c_compstr433_join(BITJOIN,27882)@41
    assign i_unnamed_c_compstr433_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr433_BitSelect_for_a_b};

    // i_unnamed_c_compstr433_vt_select_0(BITSELECT,12134)@41
    assign i_unnamed_c_compstr433_vt_select_0_b = i_unnamed_c_compstr433_join_q[0:0];

    // redist46_i_unnamed_c_compstr433_vt_select_0_b_1(DELAY,28274)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist46_i_unnamed_c_compstr433_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr433_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr433_vt_join(BITJOIN,12133)@42
    assign i_unnamed_c_compstr433_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist46_i_unnamed_c_compstr433_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_14_c_compstr434(ADD,7012)@42
    assign i_add_i_i_i_i_i_i_14_c_compstr434_a = {1'b0, i_unnamed_c_compstr433_vt_join_q};
    assign i_add_i_i_i_i_i_i_14_c_compstr434_b = {1'b0, redist1120_i_conv_i_i_i_i_i_14_c_compstr430_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_14_c_compstr434_o = $unsigned(i_add_i_i_i_i_i_i_14_c_compstr434_a) + $unsigned(i_add_i_i_i_i_i_i_14_c_compstr434_b);
    assign i_add_i_i_i_i_i_i_14_c_compstr434_q = i_add_i_i_i_i_i_i_14_c_compstr434_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_14_c_compstr434_sel_x(BITSELECT,2206)@42
    assign bgTrunc_i_add_i_i_i_i_i_i_14_c_compstr434_sel_x_b = i_add_i_i_i_i_i_i_14_c_compstr434_q[15:0];

    // i_conv_i_i_i_i_i_i279_15_c_compstr454_sel_x(BITSELECT,3874)@42
    assign i_conv_i_i_i_i_i_i279_15_c_compstr454_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_14_c_compstr434_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_15_c_compstr454_vt_select_15(BITSELECT,8013)@42
    assign i_conv_i_i_i_i_i_i279_15_c_compstr454_vt_select_15_b = i_conv_i_i_i_i_i_i279_15_c_compstr454_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_15_c_compstr454_vt_join(BITJOIN,8012)@42
    assign i_conv_i_i_i_i_i_i279_15_c_compstr454_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_15_c_compstr454_vt_select_15_b};

    // leftShiftStage0_uid25754_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x(MUX,25753)@42
    assign leftShiftStage0_uid25754_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25754_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_15_c_compstr454_vt_join_q or leftShiftStage0Idx1_uid25752_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25754_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25754_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_15_c_compstr454_vt_join_q;
            1'b1 : leftShiftStage0_uid25754_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25752_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25754_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25759_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x(MUX,25758)@42
    assign leftShiftStage1_uid25759_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25759_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_s or leftShiftStage0_uid25754_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25757_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25759_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25759_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q = leftShiftStage0_uid25754_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25759_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25757_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25759_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25764_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x(MUX,25763)@42
    assign leftShiftStage2_uid25764_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25764_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_s or leftShiftStage1_uid25759_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25762_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25764_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25764_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q = leftShiftStage1_uid25759_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25764_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25762_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25764_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_15_c_compstr455_vt_select_28(BITSELECT,9523)@42
    assign i_shl_i_i_i_i_i_i_15_c_compstr455_vt_select_28_b = leftShiftStage2_uid25764_i_shl_i_i_i_i_i_i_15_c_compstr0_shift_x_q[28:13];

    // redist349_i_shl_i_i_i_i_i_i_15_c_compstr455_vt_select_28_b_1(DELAY,28577)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist349_i_shl_i_i_i_i_i_i_15_c_compstr455_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_15_c_compstr455_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_15_c_compstr455_vt_join(BITJOIN,9522)@43
    assign i_shl_i_i_i_i_i_i_15_c_compstr455_vt_join_q = {redist349_i_shl_i_i_i_i_i_i_15_c_compstr455_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_offset(CONSTANT,29768)
    assign redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_offset_q = $unsigned(5'b01000);

    // redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_rdcnt(ADD,31217)
    assign redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_a = {1'b0, redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_wraddr_q};
    assign redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_b = {1'b0, redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_o <= $unsigned(redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_a) + $unsigned(redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_b);
        end
    end
    assign redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_q = redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_o[5:0];

    // redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_inputreg0(DELAY,31212)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl);
        end
    end

    // redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_wraddr(COUNTER,31215)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_wraddr_i <= $unsigned(redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_wraddr_q = redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_wraddr_i[4:0];

    // redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem(DUALMEM,31214)
    assign redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_ia = $unsigned(redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_inputreg0_q);
    assign redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_aa = redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_wraddr_q;
    assign redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_ab = redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_aa),
        .data_a(redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_ab),
        .q_b(redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_q = redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_iq[15:0];

    // redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_outputreg0(DELAY,31213)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_outputreg0_q <= $unsigned(redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_mem_q);
        end
    end

    // redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_rdcnt(ADD,29769)
    assign redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_a = {1'b0, redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_wraddr_q};
    assign redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_b = {1'b0, redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_o <= $unsigned(redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_a) + $unsigned(redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_b);
        end
    end
    assign redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_q = redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_o[5:0];

    // redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_inputreg0(DELAY,29764)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl);
        end
    end

    // redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_wraddr(COUNTER,29767)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_wraddr_i <= $unsigned(redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_wraddr_q = redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_wraddr_i[4:0];

    // redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem(DUALMEM,29766)
    assign redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_ia = $unsigned(redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_inputreg0_q);
    assign redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_aa = redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_wraddr_q;
    assign redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_ab = redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_aa),
        .data_a(redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_ab),
        .q_b(redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_q = redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_iq[15:0];

    // redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_outputreg0(DELAY,29765)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_outputreg0_q <= $unsigned(redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_mem_q);
        end
    end

    // redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_rdcnt(ADD,29775)
    assign redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_a = {1'b0, redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_wraddr_q};
    assign redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_b = {1'b0, redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_o <= $unsigned(redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_a) + $unsigned(redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_b);
        end
    end
    assign redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_q = redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_o[5:0];

    // redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_inputreg0(DELAY,29770)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl);
        end
    end

    // redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_wraddr(COUNTER,29773)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_wraddr_i <= $unsigned(redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_wraddr_q = redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_wraddr_i[4:0];

    // redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem(DUALMEM,29772)
    assign redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_ia = $unsigned(redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_inputreg0_q);
    assign redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_aa = redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_wraddr_q;
    assign redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_ab = redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_aa),
        .data_a(redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_ab),
        .q_b(redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_q = redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_iq[15:0];

    // redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_outputreg0(DELAY,29771)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_outputreg0_q <= $unsigned(redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_mem_q);
        end
    end

    // redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_rdcnt(ADD,31211)
    assign redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_a = {1'b0, redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_wraddr_q};
    assign redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_b = {1'b0, redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_o <= $unsigned(redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_a) + $unsigned(redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_b);
        end
    end
    assign redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_q = redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_o[5:0];

    // redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_inputreg0(DELAY,31206)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl);
        end
    end

    // redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_wraddr(COUNTER,31209)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_wraddr_i <= $unsigned(redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_wraddr_q = redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_wraddr_i[4:0];

    // redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem(DUALMEM,31208)
    assign redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_ia = $unsigned(redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_inputreg0_q);
    assign redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_aa = redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_wraddr_q;
    assign redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_ab = redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_aa),
        .data_a(redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_ab),
        .q_b(redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_q = redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_iq[15:0];

    // redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_outputreg0(DELAY,31207)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_outputreg0_q <= $unsigned(redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27974)@37 + 5
    // out q@43
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456(ADD,8555)@43
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod116_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_b = $unsigned({{5{i_shl_i_i_i_i_i_i_15_c_compstr455_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_15_c_compstr455_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_o[33:0];

    // rightShiftStage0_uid15899_dupName_61_i_unnamed_c_compstr0_shift_x(MUX,15898)@43
    assign rightShiftStage0_uid15899_dupName_61_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15899_dupName_61_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_q or rightShiftStage0Idx1_uid15897_dupName_61_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15899_dupName_61_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15899_dupName_61_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_q;
            1'b1 : rightShiftStage0_uid15899_dupName_61_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15897_dupName_61_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15899_dupName_61_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15904_dupName_61_i_unnamed_c_compstr0_shift_x(MUX,15903)@43
    assign rightShiftStage1_uid15904_dupName_61_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15904_dupName_61_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15899_dupName_61_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15902_dupName_61_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15904_dupName_61_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15904_dupName_61_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15899_dupName_61_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15904_dupName_61_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15902_dupName_61_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15904_dupName_61_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15909_dupName_61_i_unnamed_c_compstr0_shift_x(MUX,15908)@43
    assign rightShiftStage2_uid15909_dupName_61_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15909_dupName_61_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15904_dupName_61_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15907_dupName_61_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15909_dupName_61_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15909_dupName_61_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15904_dupName_61_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15909_dupName_61_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15907_dupName_61_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15909_dupName_61_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr457_vt_select_20(BITSELECT,12148)@43
    assign i_unnamed_c_compstr457_vt_select_20_b = rightShiftStage2_uid15909_dupName_61_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr457_vt_join(BITJOIN,12147)@43
    assign i_unnamed_c_compstr457_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr457_vt_select_20_b};

    // i_conv_i_i_i_i_i_15_c_compstr458_sel_x(BITSELECT,3746)@43
    assign i_conv_i_i_i_i_i_15_c_compstr458_sel_x_b = i_unnamed_c_compstr457_vt_join_q[15:0];

    // redist1119_i_conv_i_i_i_i_i_15_c_compstr458_sel_x_b_1(DELAY,29347)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1119_i_conv_i_i_i_i_i_15_c_compstr458_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_15_c_compstr458_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15918_dupName_62_i_unnamed_c_compstr0_shift_x(BITSELECT,15917)@43
    assign rightShiftStage1Idx1Rng8_uid15918_dupName_62_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15917_dupName_62_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15920_dupName_62_i_unnamed_c_compstr0_shift_x(BITJOIN,15919)@43
    assign rightShiftStage1Idx1_uid15920_dupName_62_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15918_dupName_62_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15913_dupName_62_i_unnamed_c_compstr0_shift_x(BITSELECT,15912)@43
    assign rightShiftStage0Idx1Rng4_uid15913_dupName_62_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_q[33:4];

    // rightShiftStage0Idx1_uid15915_dupName_62_i_unnamed_c_compstr0_shift_x(BITJOIN,15914)@43
    assign rightShiftStage0Idx1_uid15915_dupName_62_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15913_dupName_62_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15917_dupName_62_i_unnamed_c_compstr0_shift_x(MUX,15916)@43
    assign rightShiftStage0_uid15917_dupName_62_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15917_dupName_62_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_q or rightShiftStage0Idx1_uid15915_dupName_62_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15917_dupName_62_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15917_dupName_62_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compstr456_q;
            1'b1 : rightShiftStage0_uid15917_dupName_62_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15915_dupName_62_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15917_dupName_62_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15922_dupName_62_i_unnamed_c_compstr0_shift_x(MUX,15921)@43
    assign rightShiftStage1_uid15922_dupName_62_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15922_dupName_62_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15917_dupName_62_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15920_dupName_62_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15922_dupName_62_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15922_dupName_62_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15917_dupName_62_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15922_dupName_62_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15920_dupName_62_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15922_dupName_62_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr459_vt_select_21(BITSELECT,12151)@43
    assign i_unnamed_c_compstr459_vt_select_21_b = rightShiftStage1_uid15922_dupName_62_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr459_vt_join(BITJOIN,12150)@43
    assign i_unnamed_c_compstr459_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr459_vt_select_21_b};

    // i_unnamed_c_compstr460_sel_x(BITSELECT,6248)@43
    assign i_unnamed_c_compstr460_sel_x_b = i_unnamed_c_compstr459_vt_join_q[15:0];

    // i_unnamed_c_compstr461_BitSelect_for_a(BITSELECT,27885)@43
    assign i_unnamed_c_compstr461_BitSelect_for_a_b = i_unnamed_c_compstr460_sel_x_b[0:0];

    // i_unnamed_c_compstr461_join(BITJOIN,27886)@43
    assign i_unnamed_c_compstr461_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr461_BitSelect_for_a_b};

    // i_unnamed_c_compstr461_vt_select_0(BITSELECT,12156)@43
    assign i_unnamed_c_compstr461_vt_select_0_b = i_unnamed_c_compstr461_join_q[0:0];

    // redist44_i_unnamed_c_compstr461_vt_select_0_b_1(DELAY,28272)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist44_i_unnamed_c_compstr461_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr461_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr461_vt_join(BITJOIN,12155)@44
    assign i_unnamed_c_compstr461_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist44_i_unnamed_c_compstr461_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_15_c_compstr462(ADD,7013)@44
    assign i_add_i_i_i_i_i_i_15_c_compstr462_a = {1'b0, i_unnamed_c_compstr461_vt_join_q};
    assign i_add_i_i_i_i_i_i_15_c_compstr462_b = {1'b0, redist1119_i_conv_i_i_i_i_i_15_c_compstr458_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_15_c_compstr462_o = $unsigned(i_add_i_i_i_i_i_i_15_c_compstr462_a) + $unsigned(i_add_i_i_i_i_i_i_15_c_compstr462_b);
    assign i_add_i_i_i_i_i_i_15_c_compstr462_q = i_add_i_i_i_i_i_i_15_c_compstr462_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_15_c_compstr462_sel_x(BITSELECT,2207)@44
    assign bgTrunc_i_add_i_i_i_i_i_i_15_c_compstr462_sel_x_b = i_add_i_i_i_i_i_i_15_c_compstr462_q[15:0];

    // i_conv_i_i_i_i_i_i279_16_c_compstr482_sel_x(BITSELECT,3875)@44
    assign i_conv_i_i_i_i_i_i279_16_c_compstr482_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_15_c_compstr462_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_16_c_compstr482_vt_select_15(BITSELECT,8017)@44
    assign i_conv_i_i_i_i_i_i279_16_c_compstr482_vt_select_15_b = i_conv_i_i_i_i_i_i279_16_c_compstr482_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_16_c_compstr482_vt_join(BITJOIN,8016)@44
    assign i_conv_i_i_i_i_i_i279_16_c_compstr482_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_16_c_compstr482_vt_select_15_b};

    // leftShiftStage0_uid25772_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x(MUX,25771)@44
    assign leftShiftStage0_uid25772_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25772_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_16_c_compstr482_vt_join_q or leftShiftStage0Idx1_uid25770_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25772_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25772_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_16_c_compstr482_vt_join_q;
            1'b1 : leftShiftStage0_uid25772_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25770_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25772_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25777_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x(MUX,25776)@44
    assign leftShiftStage1_uid25777_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25777_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_s or leftShiftStage0_uid25772_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25775_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25777_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25777_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q = leftShiftStage0_uid25772_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25777_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25775_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25777_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25782_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x(MUX,25781)@44
    assign leftShiftStage2_uid25782_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25782_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_s or leftShiftStage1_uid25777_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25780_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25782_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25782_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q = leftShiftStage1_uid25777_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25782_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25780_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25782_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_16_c_compstr483_vt_select_28(BITSELECT,9526)@44
    assign i_shl_i_i_i_i_i_i_16_c_compstr483_vt_select_28_b = leftShiftStage2_uid25782_i_shl_i_i_i_i_i_i_16_c_compstr0_shift_x_q[28:13];

    // redist348_i_shl_i_i_i_i_i_i_16_c_compstr483_vt_select_28_b_1(DELAY,28576)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist348_i_shl_i_i_i_i_i_i_16_c_compstr483_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_16_c_compstr483_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_16_c_compstr483_vt_join(BITJOIN,9525)@45
    assign i_shl_i_i_i_i_i_i_16_c_compstr483_vt_join_q = {redist348_i_shl_i_i_i_i_i_i_16_c_compstr483_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_offset(CONSTANT,29780)
    assign redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_offset_q = $unsigned(5'b00110);

    // redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_rdcnt(ADD,31229)
    assign redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_a = {1'b0, redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_wraddr_q};
    assign redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_b = {1'b0, redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_o <= $unsigned(redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_a) + $unsigned(redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_b);
        end
    end
    assign redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_q = redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_o[5:0];

    // redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_inputreg0(DELAY,31224)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl);
        end
    end

    // redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_wraddr(COUNTER,31227)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_wraddr_i <= $unsigned(redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_wraddr_q = redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_wraddr_i[4:0];

    // redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem(DUALMEM,31226)
    assign redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_ia = $unsigned(redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_inputreg0_q);
    assign redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_aa = redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_wraddr_q;
    assign redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_ab = redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_aa),
        .data_a(redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_ab),
        .q_b(redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_q = redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_iq[15:0];

    // redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_outputreg0(DELAY,31225)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_outputreg0_q <= $unsigned(redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_mem_q);
        end
    end

    // redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_rdcnt(ADD,29781)
    assign redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_a = {1'b0, redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_wraddr_q};
    assign redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_b = {1'b0, redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_o <= $unsigned(redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_a) + $unsigned(redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_b);
        end
    end
    assign redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_q = redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_o[5:0];

    // redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_inputreg0(DELAY,29776)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl);
        end
    end

    // redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_wraddr(COUNTER,29779)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_wraddr_i <= $unsigned(redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_wraddr_q = redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_wraddr_i[4:0];

    // redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem(DUALMEM,29778)
    assign redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_ia = $unsigned(redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_inputreg0_q);
    assign redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_aa = redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_wraddr_q;
    assign redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_ab = redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_aa),
        .data_a(redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_ab),
        .q_b(redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_q = redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_iq[15:0];

    // redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_outputreg0(DELAY,29777)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_outputreg0_q <= $unsigned(redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_mem_q);
        end
    end

    // redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_rdcnt(ADD,29787)
    assign redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_a = {1'b0, redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_wraddr_q};
    assign redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_b = {1'b0, redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_o <= $unsigned(redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_a) + $unsigned(redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_b);
        end
    end
    assign redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_q = redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_o[5:0];

    // redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_inputreg0(DELAY,29782)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl);
        end
    end

    // redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_wraddr(COUNTER,29785)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_wraddr_i <= $unsigned(redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_wraddr_q = redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_wraddr_i[4:0];

    // redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem(DUALMEM,29784)
    assign redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_ia = $unsigned(redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_inputreg0_q);
    assign redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_aa = redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_wraddr_q;
    assign redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_ab = redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_aa),
        .data_a(redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_ab),
        .q_b(redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_q = redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_iq[15:0];

    // redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_outputreg0(DELAY,29783)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_outputreg0_q <= $unsigned(redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_mem_q);
        end
    end

    // redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_rdcnt(ADD,31223)
    assign redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_a = {1'b0, redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_wraddr_q};
    assign redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_b = {1'b0, redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_o <= $unsigned(redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_a) + $unsigned(redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_b);
        end
    end
    assign redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_q = redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_o[5:0];

    // redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_inputreg0(DELAY,31218)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl);
        end
    end

    // redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_wraddr(COUNTER,31221)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_wraddr_i <= $unsigned(redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_wraddr_q = redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_wraddr_i[4:0];

    // redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem(DUALMEM,31220)
    assign redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_ia = $unsigned(redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_inputreg0_q);
    assign redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_aa = redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_wraddr_q;
    assign redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_ab = redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_aa),
        .data_a(redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_ab),
        .q_b(redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_q = redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_iq[15:0];

    // redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_outputreg0(DELAY,31219)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_outputreg0_q <= $unsigned(redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27975)@39 + 5
    // out q@45
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484(ADD,8556)@45
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod121_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_b = $unsigned({{5{i_shl_i_i_i_i_i_i_16_c_compstr483_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_16_c_compstr483_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_o[33:0];

    // rightShiftStage0_uid15961_dupName_65_i_unnamed_c_compstr0_shift_x(MUX,15960)@45
    assign rightShiftStage0_uid15961_dupName_65_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15961_dupName_65_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_q or rightShiftStage0Idx1_uid15959_dupName_65_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15961_dupName_65_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15961_dupName_65_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_q;
            1'b1 : rightShiftStage0_uid15961_dupName_65_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15959_dupName_65_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15961_dupName_65_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15966_dupName_65_i_unnamed_c_compstr0_shift_x(MUX,15965)@45
    assign rightShiftStage1_uid15966_dupName_65_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15966_dupName_65_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15961_dupName_65_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15964_dupName_65_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15966_dupName_65_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15966_dupName_65_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15961_dupName_65_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15966_dupName_65_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15964_dupName_65_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15966_dupName_65_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15971_dupName_65_i_unnamed_c_compstr0_shift_x(MUX,15970)@45
    assign rightShiftStage2_uid15971_dupName_65_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15971_dupName_65_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15966_dupName_65_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15969_dupName_65_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15971_dupName_65_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15971_dupName_65_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15966_dupName_65_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15971_dupName_65_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15969_dupName_65_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15971_dupName_65_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr485_vt_select_20(BITSELECT,12170)@45
    assign i_unnamed_c_compstr485_vt_select_20_b = rightShiftStage2_uid15971_dupName_65_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr485_vt_join(BITJOIN,12169)@45
    assign i_unnamed_c_compstr485_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr485_vt_select_20_b};

    // i_conv_i_i_i_i_i_16_c_compstr486_sel_x(BITSELECT,3747)@45
    assign i_conv_i_i_i_i_i_16_c_compstr486_sel_x_b = i_unnamed_c_compstr485_vt_join_q[15:0];

    // redist1118_i_conv_i_i_i_i_i_16_c_compstr486_sel_x_b_1(DELAY,29346)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1118_i_conv_i_i_i_i_i_16_c_compstr486_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_16_c_compstr486_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15980_dupName_66_i_unnamed_c_compstr0_shift_x(BITSELECT,15979)@45
    assign rightShiftStage1Idx1Rng8_uid15980_dupName_66_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15979_dupName_66_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15982_dupName_66_i_unnamed_c_compstr0_shift_x(BITJOIN,15981)@45
    assign rightShiftStage1Idx1_uid15982_dupName_66_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15980_dupName_66_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15975_dupName_66_i_unnamed_c_compstr0_shift_x(BITSELECT,15974)@45
    assign rightShiftStage0Idx1Rng4_uid15975_dupName_66_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_q[33:4];

    // rightShiftStage0Idx1_uid15977_dupName_66_i_unnamed_c_compstr0_shift_x(BITJOIN,15976)@45
    assign rightShiftStage0Idx1_uid15977_dupName_66_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15975_dupName_66_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15979_dupName_66_i_unnamed_c_compstr0_shift_x(MUX,15978)@45
    assign rightShiftStage0_uid15979_dupName_66_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15979_dupName_66_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_q or rightShiftStage0Idx1_uid15977_dupName_66_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15979_dupName_66_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15979_dupName_66_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compstr484_q;
            1'b1 : rightShiftStage0_uid15979_dupName_66_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15977_dupName_66_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15979_dupName_66_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15984_dupName_66_i_unnamed_c_compstr0_shift_x(MUX,15983)@45
    assign rightShiftStage1_uid15984_dupName_66_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15984_dupName_66_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15979_dupName_66_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15982_dupName_66_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15984_dupName_66_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15984_dupName_66_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15979_dupName_66_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15984_dupName_66_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15982_dupName_66_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15984_dupName_66_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr487_vt_select_21(BITSELECT,12173)@45
    assign i_unnamed_c_compstr487_vt_select_21_b = rightShiftStage1_uid15984_dupName_66_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr487_vt_join(BITJOIN,12172)@45
    assign i_unnamed_c_compstr487_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr487_vt_select_21_b};

    // i_unnamed_c_compstr488_sel_x(BITSELECT,6250)@45
    assign i_unnamed_c_compstr488_sel_x_b = i_unnamed_c_compstr487_vt_join_q[15:0];

    // i_unnamed_c_compstr489_BitSelect_for_a(BITSELECT,27889)@45
    assign i_unnamed_c_compstr489_BitSelect_for_a_b = i_unnamed_c_compstr488_sel_x_b[0:0];

    // i_unnamed_c_compstr489_join(BITJOIN,27890)@45
    assign i_unnamed_c_compstr489_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr489_BitSelect_for_a_b};

    // i_unnamed_c_compstr489_vt_select_0(BITSELECT,12178)@45
    assign i_unnamed_c_compstr489_vt_select_0_b = i_unnamed_c_compstr489_join_q[0:0];

    // redist42_i_unnamed_c_compstr489_vt_select_0_b_1(DELAY,28270)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist42_i_unnamed_c_compstr489_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr489_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr489_vt_join(BITJOIN,12177)@46
    assign i_unnamed_c_compstr489_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist42_i_unnamed_c_compstr489_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_16_c_compstr490(ADD,7014)@46
    assign i_add_i_i_i_i_i_i_16_c_compstr490_a = {1'b0, i_unnamed_c_compstr489_vt_join_q};
    assign i_add_i_i_i_i_i_i_16_c_compstr490_b = {1'b0, redist1118_i_conv_i_i_i_i_i_16_c_compstr486_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_16_c_compstr490_o = $unsigned(i_add_i_i_i_i_i_i_16_c_compstr490_a) + $unsigned(i_add_i_i_i_i_i_i_16_c_compstr490_b);
    assign i_add_i_i_i_i_i_i_16_c_compstr490_q = i_add_i_i_i_i_i_i_16_c_compstr490_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_16_c_compstr490_sel_x(BITSELECT,2208)@46
    assign bgTrunc_i_add_i_i_i_i_i_i_16_c_compstr490_sel_x_b = i_add_i_i_i_i_i_i_16_c_compstr490_q[15:0];

    // i_conv_i_i_i_i_i_i279_17_c_compstr510_sel_x(BITSELECT,3876)@46
    assign i_conv_i_i_i_i_i_i279_17_c_compstr510_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_16_c_compstr490_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_17_c_compstr510_vt_select_15(BITSELECT,8021)@46
    assign i_conv_i_i_i_i_i_i279_17_c_compstr510_vt_select_15_b = i_conv_i_i_i_i_i_i279_17_c_compstr510_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_17_c_compstr510_vt_join(BITJOIN,8020)@46
    assign i_conv_i_i_i_i_i_i279_17_c_compstr510_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_17_c_compstr510_vt_select_15_b};

    // leftShiftStage0_uid25790_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x(MUX,25789)@46
    assign leftShiftStage0_uid25790_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25790_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_17_c_compstr510_vt_join_q or leftShiftStage0Idx1_uid25788_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25790_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25790_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_17_c_compstr510_vt_join_q;
            1'b1 : leftShiftStage0_uid25790_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25788_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25790_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25795_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x(MUX,25794)@46
    assign leftShiftStage1_uid25795_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25795_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_s or leftShiftStage0_uid25790_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25793_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25795_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25795_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q = leftShiftStage0_uid25790_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25795_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25793_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25795_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25800_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x(MUX,25799)@46
    assign leftShiftStage2_uid25800_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25800_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_s or leftShiftStage1_uid25795_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25798_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25800_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25800_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q = leftShiftStage1_uid25795_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25800_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25798_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25800_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_17_c_compstr511_vt_select_28(BITSELECT,9529)@46
    assign i_shl_i_i_i_i_i_i_17_c_compstr511_vt_select_28_b = leftShiftStage2_uid25800_i_shl_i_i_i_i_i_i_17_c_compstr0_shift_x_q[28:13];

    // redist347_i_shl_i_i_i_i_i_i_17_c_compstr511_vt_select_28_b_1(DELAY,28575)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist347_i_shl_i_i_i_i_i_i_17_c_compstr511_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_17_c_compstr511_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_17_c_compstr511_vt_join(BITJOIN,9528)@47
    assign i_shl_i_i_i_i_i_i_17_c_compstr511_vt_join_q = {redist347_i_shl_i_i_i_i_i_i_17_c_compstr511_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset(CONSTANT,29792)
    assign redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q = $unsigned(5'b00100);

    // redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_rdcnt(ADD,31241)
    assign redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_a = {1'b0, redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_wraddr_q};
    assign redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_o <= $unsigned(redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_a) + $unsigned(redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_b);
        end
    end
    assign redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_q = redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_o[5:0];

    // redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_inputreg0(DELAY,31236)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl);
        end
    end

    // redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_wraddr(COUNTER,31239)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_wraddr_i <= $unsigned(redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_wraddr_q = redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_wraddr_i[4:0];

    // redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem(DUALMEM,31238)
    assign redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_ia = $unsigned(redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_inputreg0_q);
    assign redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_aa = redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_wraddr_q;
    assign redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_ab = redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_aa),
        .data_a(redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_ab),
        .q_b(redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_q = redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_iq[15:0];

    // redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_outputreg0(DELAY,31237)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_outputreg0_q <= $unsigned(redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_mem_q);
        end
    end

    // redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_rdcnt(ADD,29793)
    assign redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_a = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_wraddr_q};
    assign redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_o <= $unsigned(redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_a) + $unsigned(redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_b);
        end
    end
    assign redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_q = redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_o[5:0];

    // redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_inputreg0(DELAY,29788)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl);
        end
    end

    // redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_wraddr(COUNTER,29791)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_wraddr_i <= $unsigned(redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_wraddr_q = redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_wraddr_i[4:0];

    // redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem(DUALMEM,29790)
    assign redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_ia = $unsigned(redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_inputreg0_q);
    assign redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_aa = redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_wraddr_q;
    assign redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_ab = redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_aa),
        .data_a(redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_ab),
        .q_b(redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_q = redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_iq[15:0];

    // redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_outputreg0(DELAY,29789)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_outputreg0_q <= $unsigned(redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_mem_q);
        end
    end

    // redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_rdcnt(ADD,29799)
    assign redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_a = {1'b0, redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_wraddr_q};
    assign redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_o <= $unsigned(redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_a) + $unsigned(redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_b);
        end
    end
    assign redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_q = redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_o[5:0];

    // redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_inputreg0(DELAY,29794)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl);
        end
    end

    // redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_wraddr(COUNTER,29797)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_wraddr_i <= $unsigned(redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_wraddr_q = redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_wraddr_i[4:0];

    // redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem(DUALMEM,29796)
    assign redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_ia = $unsigned(redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_inputreg0_q);
    assign redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_aa = redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_wraddr_q;
    assign redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_ab = redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_aa),
        .data_a(redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_ab),
        .q_b(redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_q = redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_iq[15:0];

    // redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_outputreg0(DELAY,29795)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_outputreg0_q <= $unsigned(redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_mem_q);
        end
    end

    // redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_rdcnt(ADD,31235)
    assign redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_a = {1'b0, redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_wraddr_q};
    assign redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_o <= $unsigned(redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_a) + $unsigned(redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_b);
        end
    end
    assign redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_q = redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_o[5:0];

    // redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_inputreg0(DELAY,31230)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl);
        end
    end

    // redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_wraddr(COUNTER,31233)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_wraddr_i <= $unsigned(redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_wraddr_q = redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_wraddr_i[4:0];

    // redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem(DUALMEM,31232)
    assign redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_ia = $unsigned(redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_inputreg0_q);
    assign redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_aa = redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_wraddr_q;
    assign redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_ab = redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_aa),
        .data_a(redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_ab),
        .q_b(redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_q = redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_iq[15:0];

    // redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_outputreg0(DELAY,31231)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_outputreg0_q <= $unsigned(redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27976)@41 + 5
    // out q@47
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512(ADD,8557)@47
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod126_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_b = $unsigned({{5{i_shl_i_i_i_i_i_i_17_c_compstr511_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_17_c_compstr511_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_o[33:0];

    // rightShiftStage0_uid16023_dupName_69_i_unnamed_c_compstr0_shift_x(MUX,16022)@47
    assign rightShiftStage0_uid16023_dupName_69_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16023_dupName_69_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_q or rightShiftStage0Idx1_uid16021_dupName_69_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16023_dupName_69_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16023_dupName_69_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_q;
            1'b1 : rightShiftStage0_uid16023_dupName_69_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16021_dupName_69_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16023_dupName_69_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16028_dupName_69_i_unnamed_c_compstr0_shift_x(MUX,16027)@47
    assign rightShiftStage1_uid16028_dupName_69_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16028_dupName_69_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16023_dupName_69_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16026_dupName_69_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16028_dupName_69_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16028_dupName_69_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16023_dupName_69_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16028_dupName_69_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16026_dupName_69_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16028_dupName_69_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16033_dupName_69_i_unnamed_c_compstr0_shift_x(MUX,16032)@47
    assign rightShiftStage2_uid16033_dupName_69_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16033_dupName_69_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16028_dupName_69_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16031_dupName_69_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16033_dupName_69_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16033_dupName_69_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16028_dupName_69_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16033_dupName_69_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16031_dupName_69_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16033_dupName_69_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr513_vt_select_20(BITSELECT,12195)@47
    assign i_unnamed_c_compstr513_vt_select_20_b = rightShiftStage2_uid16033_dupName_69_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr513_vt_join(BITJOIN,12194)@47
    assign i_unnamed_c_compstr513_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr513_vt_select_20_b};

    // i_conv_i_i_i_i_i_17_c_compstr514_sel_x(BITSELECT,3748)@47
    assign i_conv_i_i_i_i_i_17_c_compstr514_sel_x_b = i_unnamed_c_compstr513_vt_join_q[15:0];

    // redist1117_i_conv_i_i_i_i_i_17_c_compstr514_sel_x_b_1(DELAY,29345)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1117_i_conv_i_i_i_i_i_17_c_compstr514_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_17_c_compstr514_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16042_dupName_70_i_unnamed_c_compstr0_shift_x(BITSELECT,16041)@47
    assign rightShiftStage1Idx1Rng8_uid16042_dupName_70_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16041_dupName_70_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16044_dupName_70_i_unnamed_c_compstr0_shift_x(BITJOIN,16043)@47
    assign rightShiftStage1Idx1_uid16044_dupName_70_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16042_dupName_70_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16037_dupName_70_i_unnamed_c_compstr0_shift_x(BITSELECT,16036)@47
    assign rightShiftStage0Idx1Rng4_uid16037_dupName_70_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_q[33:4];

    // rightShiftStage0Idx1_uid16039_dupName_70_i_unnamed_c_compstr0_shift_x(BITJOIN,16038)@47
    assign rightShiftStage0Idx1_uid16039_dupName_70_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16037_dupName_70_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16041_dupName_70_i_unnamed_c_compstr0_shift_x(MUX,16040)@47
    assign rightShiftStage0_uid16041_dupName_70_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16041_dupName_70_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_q or rightShiftStage0Idx1_uid16039_dupName_70_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16041_dupName_70_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16041_dupName_70_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compstr512_q;
            1'b1 : rightShiftStage0_uid16041_dupName_70_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16039_dupName_70_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16041_dupName_70_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16046_dupName_70_i_unnamed_c_compstr0_shift_x(MUX,16045)@47
    assign rightShiftStage1_uid16046_dupName_70_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16046_dupName_70_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16041_dupName_70_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16044_dupName_70_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16046_dupName_70_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16046_dupName_70_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16041_dupName_70_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16046_dupName_70_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16044_dupName_70_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16046_dupName_70_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr515_vt_select_21(BITSELECT,12198)@47
    assign i_unnamed_c_compstr515_vt_select_21_b = rightShiftStage1_uid16046_dupName_70_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr515_vt_join(BITJOIN,12197)@47
    assign i_unnamed_c_compstr515_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr515_vt_select_21_b};

    // i_unnamed_c_compstr516_sel_x(BITSELECT,6252)@47
    assign i_unnamed_c_compstr516_sel_x_b = i_unnamed_c_compstr515_vt_join_q[15:0];

    // i_unnamed_c_compstr517_BitSelect_for_a(BITSELECT,27893)@47
    assign i_unnamed_c_compstr517_BitSelect_for_a_b = i_unnamed_c_compstr516_sel_x_b[0:0];

    // i_unnamed_c_compstr517_join(BITJOIN,27894)@47
    assign i_unnamed_c_compstr517_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr517_BitSelect_for_a_b};

    // i_unnamed_c_compstr517_vt_select_0(BITSELECT,12203)@47
    assign i_unnamed_c_compstr517_vt_select_0_b = i_unnamed_c_compstr517_join_q[0:0];

    // redist40_i_unnamed_c_compstr517_vt_select_0_b_1(DELAY,28268)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist40_i_unnamed_c_compstr517_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr517_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr517_vt_join(BITJOIN,12202)@48
    assign i_unnamed_c_compstr517_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist40_i_unnamed_c_compstr517_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_17_c_compstr518(ADD,7015)@48
    assign i_add_i_i_i_i_i_i_17_c_compstr518_a = {1'b0, i_unnamed_c_compstr517_vt_join_q};
    assign i_add_i_i_i_i_i_i_17_c_compstr518_b = {1'b0, redist1117_i_conv_i_i_i_i_i_17_c_compstr514_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_17_c_compstr518_o = $unsigned(i_add_i_i_i_i_i_i_17_c_compstr518_a) + $unsigned(i_add_i_i_i_i_i_i_17_c_compstr518_b);
    assign i_add_i_i_i_i_i_i_17_c_compstr518_q = i_add_i_i_i_i_i_i_17_c_compstr518_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_17_c_compstr518_sel_x(BITSELECT,2209)@48
    assign bgTrunc_i_add_i_i_i_i_i_i_17_c_compstr518_sel_x_b = i_add_i_i_i_i_i_i_17_c_compstr518_q[15:0];

    // i_conv_i_i_i_i_i_i279_18_c_compstr538_sel_x(BITSELECT,3877)@48
    assign i_conv_i_i_i_i_i_i279_18_c_compstr538_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_17_c_compstr518_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_18_c_compstr538_vt_select_15(BITSELECT,8025)@48
    assign i_conv_i_i_i_i_i_i279_18_c_compstr538_vt_select_15_b = i_conv_i_i_i_i_i_i279_18_c_compstr538_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_18_c_compstr538_vt_join(BITJOIN,8024)@48
    assign i_conv_i_i_i_i_i_i279_18_c_compstr538_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_18_c_compstr538_vt_select_15_b};

    // leftShiftStage0_uid25808_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x(MUX,25807)@48
    assign leftShiftStage0_uid25808_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25808_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_18_c_compstr538_vt_join_q or leftShiftStage0Idx1_uid25806_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25808_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25808_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_18_c_compstr538_vt_join_q;
            1'b1 : leftShiftStage0_uid25808_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25806_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25808_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25813_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x(MUX,25812)@48
    assign leftShiftStage1_uid25813_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25813_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_s or leftShiftStage0_uid25808_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25811_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25813_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25813_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q = leftShiftStage0_uid25808_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25813_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25811_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25813_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25818_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x(MUX,25817)@48
    assign leftShiftStage2_uid25818_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25818_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_s or leftShiftStage1_uid25813_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25816_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25818_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25818_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q = leftShiftStage1_uid25813_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25818_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25816_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25818_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_18_c_compstr539_vt_select_28(BITSELECT,9532)@48
    assign i_shl_i_i_i_i_i_i_18_c_compstr539_vt_select_28_b = leftShiftStage2_uid25818_i_shl_i_i_i_i_i_i_18_c_compstr0_shift_x_q[28:13];

    // redist346_i_shl_i_i_i_i_i_i_18_c_compstr539_vt_select_28_b_1(DELAY,28574)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist346_i_shl_i_i_i_i_i_i_18_c_compstr539_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_18_c_compstr539_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_18_c_compstr539_vt_join(BITJOIN,9531)@49
    assign i_shl_i_i_i_i_i_i_18_c_compstr539_vt_join_q = {redist346_i_shl_i_i_i_i_i_i_18_c_compstr539_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt(ADD,32883)
    assign redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_a = {1'b0, redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_q};
    assign redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_o <= $unsigned(redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_a) + $unsigned(redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_b);
        end
    end
    assign redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_q = redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_o[5:0];

    // redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_inputreg0(DELAY,32878)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl);
        end
    end

    // redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr(COUNTER,32881)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_i <= $unsigned(redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_q = redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_i[4:0];

    // redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem(DUALMEM,32880)
    assign redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_ia = $unsigned(redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_inputreg0_q);
    assign redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_aa = redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_q;
    assign redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_ab = redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_aa),
        .data_a(redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_ab),
        .q_b(redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_q = redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_iq[15:0];

    // redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_outputreg0(DELAY,32879)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_outputreg0_q <= $unsigned(redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_q);
        end
    end

    // redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35(DELAY,29035)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_delay_0 <= $unsigned(redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_split_0_outputreg0_q);
            redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_q <= redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_delay_0;
        end
    end

    // redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt(ADD,32517)
    assign redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_a = {1'b0, redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_q};
    assign redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_o <= $unsigned(redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_a) + $unsigned(redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_b);
        end
    end
    assign redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_q = redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_o[5:0];

    // redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_inputreg0(DELAY,32512)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl);
        end
    end

    // redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr(COUNTER,32515)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_i <= $unsigned(redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_q = redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_i[4:0];

    // redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem(DUALMEM,32514)
    assign redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_ia = $unsigned(redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_inputreg0_q);
    assign redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_aa = redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_q;
    assign redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_ab = redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_aa),
        .data_a(redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_ab),
        .q_b(redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_q = redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_iq[15:0];

    // redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_outputreg0(DELAY,32513)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_outputreg0_q <= $unsigned(redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_q);
        end
    end

    // redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35(DELAY,28780)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_delay_0 <= $unsigned(redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_split_0_outputreg0_q);
            redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_q <= redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_delay_0;
        end
    end

    // redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt(ADD,32523)
    assign redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_a = {1'b0, redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_q};
    assign redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_o <= $unsigned(redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_a) + $unsigned(redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_b);
        end
    end
    assign redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_q = redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_o[5:0];

    // redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_inputreg0(DELAY,32518)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl);
        end
    end

    // redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr(COUNTER,32521)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_i <= $unsigned(redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_q = redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_i[4:0];

    // redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem(DUALMEM,32520)
    assign redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_ia = $unsigned(redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_inputreg0_q);
    assign redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_aa = redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_wraddr_q;
    assign redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_ab = redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_aa),
        .data_a(redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_ab),
        .q_b(redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_q = redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_iq[15:0];

    // redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_outputreg0(DELAY,32519)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_outputreg0_q <= $unsigned(redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_mem_q);
        end
    end

    // redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35(DELAY,28781)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_delay_0 <= $unsigned(redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_split_0_outputreg0_q);
            redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_q <= redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_delay_0;
        end
    end

    // redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt(ADD,32877)
    assign redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_a = {1'b0, redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_q};
    assign redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_o <= $unsigned(redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_a) + $unsigned(redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_b);
        end
    end
    assign redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_q = redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_o[5:0];

    // redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_inputreg0(DELAY,32872)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl);
        end
    end

    // redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr(COUNTER,32875)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_i <= $unsigned(redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_q = redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_i[4:0];

    // redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem(DUALMEM,32874)
    assign redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_ia = $unsigned(redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_inputreg0_q);
    assign redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_aa = redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_wraddr_q;
    assign redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_ab = redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_aa),
        .data_a(redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_ab),
        .q_b(redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_q = redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_iq[15:0];

    // redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_outputreg0(DELAY,32873)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_outputreg0_q <= $unsigned(redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_mem_q);
        end
    end

    // redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35(DELAY,29034)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_delay_0 <= $unsigned(redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_split_0_outputreg0_q);
            redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_q <= redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_delay_0;
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27977)@43 + 5
    // out q@49
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540(ADD,8558)@49
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod131_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_b = $unsigned({{5{i_shl_i_i_i_i_i_i_18_c_compstr539_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_18_c_compstr539_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_o[33:0];

    // rightShiftStage0_uid16085_dupName_73_i_unnamed_c_compstr0_shift_x(MUX,16084)@49
    assign rightShiftStage0_uid16085_dupName_73_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16085_dupName_73_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_q or rightShiftStage0Idx1_uid16083_dupName_73_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16085_dupName_73_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16085_dupName_73_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_q;
            1'b1 : rightShiftStage0_uid16085_dupName_73_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16083_dupName_73_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16085_dupName_73_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16090_dupName_73_i_unnamed_c_compstr0_shift_x(MUX,16089)@49
    assign rightShiftStage1_uid16090_dupName_73_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16090_dupName_73_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16085_dupName_73_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16088_dupName_73_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16090_dupName_73_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16090_dupName_73_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16085_dupName_73_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16090_dupName_73_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16088_dupName_73_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16090_dupName_73_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16095_dupName_73_i_unnamed_c_compstr0_shift_x(MUX,16094)@49
    assign rightShiftStage2_uid16095_dupName_73_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16095_dupName_73_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16090_dupName_73_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16093_dupName_73_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16095_dupName_73_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16095_dupName_73_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16090_dupName_73_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16095_dupName_73_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16093_dupName_73_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16095_dupName_73_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr541_vt_select_20(BITSELECT,12225)@49
    assign i_unnamed_c_compstr541_vt_select_20_b = rightShiftStage2_uid16095_dupName_73_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr541_vt_join(BITJOIN,12224)@49
    assign i_unnamed_c_compstr541_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr541_vt_select_20_b};

    // i_conv_i_i_i_i_i_18_c_compstr542_sel_x(BITSELECT,3749)@49
    assign i_conv_i_i_i_i_i_18_c_compstr542_sel_x_b = i_unnamed_c_compstr541_vt_join_q[15:0];

    // redist1116_i_conv_i_i_i_i_i_18_c_compstr542_sel_x_b_1(DELAY,29344)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1116_i_conv_i_i_i_i_i_18_c_compstr542_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_18_c_compstr542_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16104_dupName_74_i_unnamed_c_compstr0_shift_x(BITSELECT,16103)@49
    assign rightShiftStage1Idx1Rng8_uid16104_dupName_74_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16103_dupName_74_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16106_dupName_74_i_unnamed_c_compstr0_shift_x(BITJOIN,16105)@49
    assign rightShiftStage1Idx1_uid16106_dupName_74_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16104_dupName_74_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16099_dupName_74_i_unnamed_c_compstr0_shift_x(BITSELECT,16098)@49
    assign rightShiftStage0Idx1Rng4_uid16099_dupName_74_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_q[33:4];

    // rightShiftStage0Idx1_uid16101_dupName_74_i_unnamed_c_compstr0_shift_x(BITJOIN,16100)@49
    assign rightShiftStage0Idx1_uid16101_dupName_74_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16099_dupName_74_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16103_dupName_74_i_unnamed_c_compstr0_shift_x(MUX,16102)@49
    assign rightShiftStage0_uid16103_dupName_74_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16103_dupName_74_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_q or rightShiftStage0Idx1_uid16101_dupName_74_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16103_dupName_74_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16103_dupName_74_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compstr540_q;
            1'b1 : rightShiftStage0_uid16103_dupName_74_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16101_dupName_74_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16103_dupName_74_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16108_dupName_74_i_unnamed_c_compstr0_shift_x(MUX,16107)@49
    assign rightShiftStage1_uid16108_dupName_74_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16108_dupName_74_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16103_dupName_74_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16106_dupName_74_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16108_dupName_74_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16108_dupName_74_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16103_dupName_74_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16108_dupName_74_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16106_dupName_74_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16108_dupName_74_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr543_vt_select_21(BITSELECT,12228)@49
    assign i_unnamed_c_compstr543_vt_select_21_b = rightShiftStage1_uid16108_dupName_74_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr543_vt_join(BITJOIN,12227)@49
    assign i_unnamed_c_compstr543_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr543_vt_select_21_b};

    // i_unnamed_c_compstr544_sel_x(BITSELECT,6255)@49
    assign i_unnamed_c_compstr544_sel_x_b = i_unnamed_c_compstr543_vt_join_q[15:0];

    // i_unnamed_c_compstr545_BitSelect_for_a(BITSELECT,27899)@49
    assign i_unnamed_c_compstr545_BitSelect_for_a_b = i_unnamed_c_compstr544_sel_x_b[0:0];

    // i_unnamed_c_compstr545_join(BITJOIN,27900)@49
    assign i_unnamed_c_compstr545_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr545_BitSelect_for_a_b};

    // i_unnamed_c_compstr545_vt_select_0(BITSELECT,12233)@49
    assign i_unnamed_c_compstr545_vt_select_0_b = i_unnamed_c_compstr545_join_q[0:0];

    // redist37_i_unnamed_c_compstr545_vt_select_0_b_1(DELAY,28265)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist37_i_unnamed_c_compstr545_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr545_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr545_vt_join(BITJOIN,12232)@50
    assign i_unnamed_c_compstr545_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist37_i_unnamed_c_compstr545_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_18_c_compstr546(ADD,7016)@50
    assign i_add_i_i_i_i_i_i_18_c_compstr546_a = {1'b0, i_unnamed_c_compstr545_vt_join_q};
    assign i_add_i_i_i_i_i_i_18_c_compstr546_b = {1'b0, redist1116_i_conv_i_i_i_i_i_18_c_compstr542_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_18_c_compstr546_o = $unsigned(i_add_i_i_i_i_i_i_18_c_compstr546_a) + $unsigned(i_add_i_i_i_i_i_i_18_c_compstr546_b);
    assign i_add_i_i_i_i_i_i_18_c_compstr546_q = i_add_i_i_i_i_i_i_18_c_compstr546_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_18_c_compstr546_sel_x(BITSELECT,2210)@50
    assign bgTrunc_i_add_i_i_i_i_i_i_18_c_compstr546_sel_x_b = i_add_i_i_i_i_i_i_18_c_compstr546_q[15:0];

    // i_conv_i_i_i_i_i_i279_19_c_compstr566_sel_x(BITSELECT,3878)@50
    assign i_conv_i_i_i_i_i_i279_19_c_compstr566_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_18_c_compstr546_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_19_c_compstr566_vt_select_15(BITSELECT,8029)@50
    assign i_conv_i_i_i_i_i_i279_19_c_compstr566_vt_select_15_b = i_conv_i_i_i_i_i_i279_19_c_compstr566_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_19_c_compstr566_vt_join(BITJOIN,8028)@50
    assign i_conv_i_i_i_i_i_i279_19_c_compstr566_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_19_c_compstr566_vt_select_15_b};

    // leftShiftStage0_uid25826_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x(MUX,25825)@50
    assign leftShiftStage0_uid25826_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25826_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_19_c_compstr566_vt_join_q or leftShiftStage0Idx1_uid25824_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25826_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25826_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_19_c_compstr566_vt_join_q;
            1'b1 : leftShiftStage0_uid25826_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25824_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25826_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25831_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x(MUX,25830)@50
    assign leftShiftStage1_uid25831_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25831_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_s or leftShiftStage0_uid25826_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25829_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25831_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25831_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q = leftShiftStage0_uid25826_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25831_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25829_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25831_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25836_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x(MUX,25835)@50
    assign leftShiftStage2_uid25836_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25836_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_s or leftShiftStage1_uid25831_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25834_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25836_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25836_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q = leftShiftStage1_uid25831_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25836_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25834_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25836_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_19_c_compstr567_vt_select_28(BITSELECT,9535)@50
    assign i_shl_i_i_i_i_i_i_19_c_compstr567_vt_select_28_b = leftShiftStage2_uid25836_i_shl_i_i_i_i_i_i_19_c_compstr0_shift_x_q[28:13];

    // redist345_i_shl_i_i_i_i_i_i_19_c_compstr567_vt_select_28_b_1(DELAY,28573)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist345_i_shl_i_i_i_i_i_i_19_c_compstr567_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_19_c_compstr567_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_19_c_compstr567_vt_join(BITJOIN,9534)@51
    assign i_shl_i_i_i_i_i_i_19_c_compstr567_vt_join_q = {redist345_i_shl_i_i_i_i_i_i_19_c_compstr567_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt(ADD,32895)
    assign redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_a = {1'b0, redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_q};
    assign redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_o <= $unsigned(redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_a) + $unsigned(redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_b);
        end
    end
    assign redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_q = redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_o[5:0];

    // redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_inputreg0(DELAY,32890)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl);
        end
    end

    // redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr(COUNTER,32893)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_i <= $unsigned(redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_q = redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_i[4:0];

    // redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem(DUALMEM,32892)
    assign redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_ia = $unsigned(redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_inputreg0_q);
    assign redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_aa = redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_q;
    assign redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_ab = redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_aa),
        .data_a(redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_ab),
        .q_b(redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_q = redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_iq[15:0];

    // redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_outputreg0(DELAY,32891)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_outputreg0_q <= $unsigned(redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_q);
        end
    end

    // redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_inputreg0(DELAY,31243)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_inputreg0_q <= $unsigned(redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_split_0_outputreg0_q);
        end
    end

    // redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37(DELAY,29037)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_delay_0 <= $unsigned(redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_inputreg0_q);
            redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_delay_1 <= redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_delay_0;
            redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_q <= redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_delay_1;
        end
    end

    // redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt(ADD,32529)
    assign redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_a = {1'b0, redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_q};
    assign redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_o <= $unsigned(redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_a) + $unsigned(redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_b);
        end
    end
    assign redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_q = redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_o[5:0];

    // redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_inputreg0(DELAY,32524)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl);
        end
    end

    // redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr(COUNTER,32527)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_i <= $unsigned(redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_q = redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_i[4:0];

    // redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem(DUALMEM,32526)
    assign redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_ia = $unsigned(redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_inputreg0_q);
    assign redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_aa = redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_q;
    assign redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_ab = redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_aa),
        .data_a(redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_ab),
        .q_b(redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_q = redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_iq[15:0];

    // redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_outputreg0(DELAY,32525)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_outputreg0_q <= $unsigned(redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_q);
        end
    end

    // redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_inputreg0(DELAY,29800)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_inputreg0_q <= $unsigned(redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_split_0_outputreg0_q);
        end
    end

    // redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37(DELAY,28782)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_delay_0 <= $unsigned(redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_inputreg0_q);
            redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_delay_1 <= redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_delay_0;
            redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_q <= redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_delay_1;
        end
    end

    // redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt(ADD,32535)
    assign redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_a = {1'b0, redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_q};
    assign redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_o <= $unsigned(redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_a) + $unsigned(redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_b);
        end
    end
    assign redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_q = redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_o[5:0];

    // redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_inputreg0(DELAY,32530)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl);
        end
    end

    // redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr(COUNTER,32533)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_i <= $unsigned(redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_q = redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_i[4:0];

    // redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem(DUALMEM,32532)
    assign redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_ia = $unsigned(redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_inputreg0_q);
    assign redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_aa = redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_wraddr_q;
    assign redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_ab = redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_aa),
        .data_a(redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_ab),
        .q_b(redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_q = redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_iq[15:0];

    // redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_outputreg0(DELAY,32531)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_outputreg0_q <= $unsigned(redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_mem_q);
        end
    end

    // redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_inputreg0(DELAY,29801)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_inputreg0_q <= $unsigned(redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_split_0_outputreg0_q);
        end
    end

    // redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37(DELAY,28783)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_delay_0 <= $unsigned(redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_inputreg0_q);
            redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_delay_1 <= redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_delay_0;
            redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_q <= redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_delay_1;
        end
    end

    // redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt(ADD,32889)
    assign redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_a = {1'b0, redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_q};
    assign redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_o <= $unsigned(redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_a) + $unsigned(redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_b);
        end
    end
    assign redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_q = redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_o[5:0];

    // redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_inputreg0(DELAY,32884)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl);
        end
    end

    // redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr(COUNTER,32887)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_i <= $unsigned(redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_q = redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_i[4:0];

    // redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem(DUALMEM,32886)
    assign redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_ia = $unsigned(redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_inputreg0_q);
    assign redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_aa = redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_wraddr_q;
    assign redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_ab = redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_aa),
        .data_a(redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_ab),
        .q_b(redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_q = redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_iq[15:0];

    // redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_outputreg0(DELAY,32885)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_outputreg0_q <= $unsigned(redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_mem_q);
        end
    end

    // redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_inputreg0(DELAY,31242)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_inputreg0_q <= $unsigned(redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_split_0_outputreg0_q);
        end
    end

    // redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37(DELAY,29036)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_delay_0 <= $unsigned(redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_inputreg0_q);
            redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_delay_1 <= redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_delay_0;
            redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_q <= redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_delay_1;
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27978)@45 + 5
    // out q@51
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568(ADD,8559)@51
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod136_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_b = $unsigned({{5{i_shl_i_i_i_i_i_i_19_c_compstr567_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_19_c_compstr567_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_o[33:0];

    // rightShiftStage0_uid16147_dupName_77_i_unnamed_c_compstr0_shift_x(MUX,16146)@51
    assign rightShiftStage0_uid16147_dupName_77_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16147_dupName_77_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_q or rightShiftStage0Idx1_uid16145_dupName_77_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16147_dupName_77_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16147_dupName_77_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_q;
            1'b1 : rightShiftStage0_uid16147_dupName_77_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16145_dupName_77_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16147_dupName_77_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16152_dupName_77_i_unnamed_c_compstr0_shift_x(MUX,16151)@51
    assign rightShiftStage1_uid16152_dupName_77_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16152_dupName_77_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16147_dupName_77_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16150_dupName_77_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16152_dupName_77_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16152_dupName_77_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16147_dupName_77_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16152_dupName_77_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16150_dupName_77_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16152_dupName_77_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16157_dupName_77_i_unnamed_c_compstr0_shift_x(MUX,16156)@51
    assign rightShiftStage2_uid16157_dupName_77_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16157_dupName_77_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16152_dupName_77_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16155_dupName_77_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16157_dupName_77_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16157_dupName_77_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16152_dupName_77_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16157_dupName_77_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16155_dupName_77_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16157_dupName_77_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr569_vt_select_20(BITSELECT,12247)@51
    assign i_unnamed_c_compstr569_vt_select_20_b = rightShiftStage2_uid16157_dupName_77_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr569_vt_join(BITJOIN,12246)@51
    assign i_unnamed_c_compstr569_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr569_vt_select_20_b};

    // i_conv_i_i_i_i_i_19_c_compstr570_sel_x(BITSELECT,3750)@51
    assign i_conv_i_i_i_i_i_19_c_compstr570_sel_x_b = i_unnamed_c_compstr569_vt_join_q[15:0];

    // redist1115_i_conv_i_i_i_i_i_19_c_compstr570_sel_x_b_1(DELAY,29343)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1115_i_conv_i_i_i_i_i_19_c_compstr570_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_19_c_compstr570_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16166_dupName_78_i_unnamed_c_compstr0_shift_x(BITSELECT,16165)@51
    assign rightShiftStage1Idx1Rng8_uid16166_dupName_78_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16165_dupName_78_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16168_dupName_78_i_unnamed_c_compstr0_shift_x(BITJOIN,16167)@51
    assign rightShiftStage1Idx1_uid16168_dupName_78_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16166_dupName_78_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16161_dupName_78_i_unnamed_c_compstr0_shift_x(BITSELECT,16160)@51
    assign rightShiftStage0Idx1Rng4_uid16161_dupName_78_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_q[33:4];

    // rightShiftStage0Idx1_uid16163_dupName_78_i_unnamed_c_compstr0_shift_x(BITJOIN,16162)@51
    assign rightShiftStage0Idx1_uid16163_dupName_78_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16161_dupName_78_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16165_dupName_78_i_unnamed_c_compstr0_shift_x(MUX,16164)@51
    assign rightShiftStage0_uid16165_dupName_78_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16165_dupName_78_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_q or rightShiftStage0Idx1_uid16163_dupName_78_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16165_dupName_78_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16165_dupName_78_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compstr568_q;
            1'b1 : rightShiftStage0_uid16165_dupName_78_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16163_dupName_78_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16165_dupName_78_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16170_dupName_78_i_unnamed_c_compstr0_shift_x(MUX,16169)@51
    assign rightShiftStage1_uid16170_dupName_78_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16170_dupName_78_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16165_dupName_78_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16168_dupName_78_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16170_dupName_78_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16170_dupName_78_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16165_dupName_78_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16170_dupName_78_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16168_dupName_78_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16170_dupName_78_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr571_vt_select_21(BITSELECT,12250)@51
    assign i_unnamed_c_compstr571_vt_select_21_b = rightShiftStage1_uid16170_dupName_78_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr571_vt_join(BITJOIN,12249)@51
    assign i_unnamed_c_compstr571_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr571_vt_select_21_b};

    // i_unnamed_c_compstr572_sel_x(BITSELECT,6257)@51
    assign i_unnamed_c_compstr572_sel_x_b = i_unnamed_c_compstr571_vt_join_q[15:0];

    // i_unnamed_c_compstr573_BitSelect_for_a(BITSELECT,27903)@51
    assign i_unnamed_c_compstr573_BitSelect_for_a_b = i_unnamed_c_compstr572_sel_x_b[0:0];

    // i_unnamed_c_compstr573_join(BITJOIN,27904)@51
    assign i_unnamed_c_compstr573_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr573_BitSelect_for_a_b};

    // i_unnamed_c_compstr573_vt_select_0(BITSELECT,12255)@51
    assign i_unnamed_c_compstr573_vt_select_0_b = i_unnamed_c_compstr573_join_q[0:0];

    // redist35_i_unnamed_c_compstr573_vt_select_0_b_1(DELAY,28263)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist35_i_unnamed_c_compstr573_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr573_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr573_vt_join(BITJOIN,12254)@52
    assign i_unnamed_c_compstr573_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist35_i_unnamed_c_compstr573_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_19_c_compstr574(ADD,7017)@52
    assign i_add_i_i_i_i_i_i_19_c_compstr574_a = {1'b0, i_unnamed_c_compstr573_vt_join_q};
    assign i_add_i_i_i_i_i_i_19_c_compstr574_b = {1'b0, redist1115_i_conv_i_i_i_i_i_19_c_compstr570_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_19_c_compstr574_o = $unsigned(i_add_i_i_i_i_i_i_19_c_compstr574_a) + $unsigned(i_add_i_i_i_i_i_i_19_c_compstr574_b);
    assign i_add_i_i_i_i_i_i_19_c_compstr574_q = i_add_i_i_i_i_i_i_19_c_compstr574_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_19_c_compstr574_sel_x(BITSELECT,2211)@52
    assign bgTrunc_i_add_i_i_i_i_i_i_19_c_compstr574_sel_x_b = i_add_i_i_i_i_i_i_19_c_compstr574_q[15:0];

    // i_conv_i_i_i_i_i_i279_20_c_compstr594_sel_x(BITSELECT,3880)@52
    assign i_conv_i_i_i_i_i_i279_20_c_compstr594_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_19_c_compstr574_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_20_c_compstr594_vt_select_15(BITSELECT,8037)@52
    assign i_conv_i_i_i_i_i_i279_20_c_compstr594_vt_select_15_b = i_conv_i_i_i_i_i_i279_20_c_compstr594_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_20_c_compstr594_vt_join(BITJOIN,8036)@52
    assign i_conv_i_i_i_i_i_i279_20_c_compstr594_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_20_c_compstr594_vt_select_15_b};

    // leftShiftStage0_uid25862_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x(MUX,25861)@52
    assign leftShiftStage0_uid25862_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25862_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_20_c_compstr594_vt_join_q or leftShiftStage0Idx1_uid25860_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25862_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25862_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_20_c_compstr594_vt_join_q;
            1'b1 : leftShiftStage0_uid25862_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25860_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25862_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25867_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x(MUX,25866)@52
    assign leftShiftStage1_uid25867_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25867_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_s or leftShiftStage0_uid25862_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25865_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25867_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25867_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q = leftShiftStage0_uid25862_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25867_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25865_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25867_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25872_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x(MUX,25871)@52
    assign leftShiftStage2_uid25872_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25872_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_s or leftShiftStage1_uid25867_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25870_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25872_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25872_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q = leftShiftStage1_uid25867_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25872_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25870_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25872_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_20_c_compstr595_vt_select_28(BITSELECT,9541)@52
    assign i_shl_i_i_i_i_i_i_20_c_compstr595_vt_select_28_b = leftShiftStage2_uid25872_i_shl_i_i_i_i_i_i_20_c_compstr0_shift_x_q[28:13];

    // redist343_i_shl_i_i_i_i_i_i_20_c_compstr595_vt_select_28_b_1(DELAY,28571)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist343_i_shl_i_i_i_i_i_i_20_c_compstr595_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_20_c_compstr595_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_20_c_compstr595_vt_join(BITJOIN,9540)@53
    assign i_shl_i_i_i_i_i_i_20_c_compstr595_vt_join_q = {redist343_i_shl_i_i_i_i_i_i_20_c_compstr595_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_offset(CONSTANT,29806)
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_offset_q = $unsigned(2'b11);

    // redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_rdcnt(ADD,31255)
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_a = {1'b0, redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_wraddr_q};
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_b = {1'b0, redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_o <= $unsigned(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_a) + $unsigned(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_b);
        end
    end
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_q = redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_o[2:0];

    // redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt(ADD,32907)
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_a = {1'b0, redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_q};
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_o <= $unsigned(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_a) + $unsigned(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_b);
        end
    end
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_q = redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_o[5:0];

    // redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_inputreg0(DELAY,32902)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl);
        end
    end

    // redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr(COUNTER,32905)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_i <= $unsigned(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_q = redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_i[4:0];

    // redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem(DUALMEM,32904)
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_ia = $unsigned(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_inputreg0_q);
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_aa = redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_q;
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_ab = redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_aa),
        .data_a(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_ab),
        .q_b(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_q = redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_iq[15:0];

    // redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_outputreg0(DELAY,32903)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_outputreg0_q <= $unsigned(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_q);
        end
    end

    // redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_inputreg0(DELAY,31250)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_inputreg0_q <= $unsigned(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_split_0_outputreg0_q);
        end
    end

    // redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_wraddr(COUNTER,31253)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_wraddr_i <= $unsigned(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_wraddr_q = redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_wraddr_i[1:0];

    // redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem(DUALMEM,31252)
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_ia = $unsigned(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_inputreg0_q);
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_aa = redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_wraddr_q;
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_ab = redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_aa),
        .data_a(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_ab),
        .q_b(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_q = redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_iq[15:0];

    // redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_outputreg0(DELAY,31251)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_outputreg0_q <= $unsigned(redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_mem_q);
        end
    end

    // redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_rdcnt(ADD,29807)
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_a = {1'b0, redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_wraddr_q};
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_b = {1'b0, redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_o <= $unsigned(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_a) + $unsigned(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_b);
        end
    end
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_q = redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_o[2:0];

    // redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt(ADD,32541)
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_a = {1'b0, redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_q};
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_o <= $unsigned(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_a) + $unsigned(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_b);
        end
    end
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_q = redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_o[5:0];

    // redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_inputreg0(DELAY,32536)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl);
        end
    end

    // redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr(COUNTER,32539)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_i <= $unsigned(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_q = redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_i[4:0];

    // redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem(DUALMEM,32538)
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_ia = $unsigned(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_inputreg0_q);
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_aa = redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_q;
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_ab = redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_aa),
        .data_a(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_ab),
        .q_b(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_q = redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_iq[15:0];

    // redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_outputreg0(DELAY,32537)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_outputreg0_q <= $unsigned(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_q);
        end
    end

    // redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_inputreg0(DELAY,29802)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_inputreg0_q <= $unsigned(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_split_0_outputreg0_q);
        end
    end

    // redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_wraddr(COUNTER,29805)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_wraddr_i <= $unsigned(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_wraddr_q = redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_wraddr_i[1:0];

    // redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem(DUALMEM,29804)
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_ia = $unsigned(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_inputreg0_q);
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_aa = redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_wraddr_q;
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_ab = redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_aa),
        .data_a(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_ab),
        .q_b(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_q = redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_iq[15:0];

    // redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_outputreg0(DELAY,29803)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_outputreg0_q <= $unsigned(redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_mem_q);
        end
    end

    // redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_rdcnt(ADD,29813)
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_a = {1'b0, redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_wraddr_q};
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_b = {1'b0, redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_o <= $unsigned(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_a) + $unsigned(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_b);
        end
    end
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_q = redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_o[2:0];

    // redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt(ADD,32547)
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_a = {1'b0, redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_q};
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_o <= $unsigned(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_a) + $unsigned(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_b);
        end
    end
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_q = redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_o[5:0];

    // redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_inputreg0(DELAY,32542)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl);
        end
    end

    // redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr(COUNTER,32545)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_i <= $unsigned(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_q = redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_i[4:0];

    // redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem(DUALMEM,32544)
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_ia = $unsigned(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_inputreg0_q);
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_aa = redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_wraddr_q;
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_ab = redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_aa),
        .data_a(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_ab),
        .q_b(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_q = redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_iq[15:0];

    // redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_outputreg0(DELAY,32543)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_outputreg0_q <= $unsigned(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_mem_q);
        end
    end

    // redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_inputreg0(DELAY,29808)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_inputreg0_q <= $unsigned(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_split_0_outputreg0_q);
        end
    end

    // redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_wraddr(COUNTER,29811)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_wraddr_i <= $unsigned(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_wraddr_q = redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_wraddr_i[1:0];

    // redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem(DUALMEM,29810)
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_ia = $unsigned(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_inputreg0_q);
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_aa = redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_wraddr_q;
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_ab = redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_aa),
        .data_a(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_ab),
        .q_b(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_q = redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_iq[15:0];

    // redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_outputreg0(DELAY,29809)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_outputreg0_q <= $unsigned(redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_mem_q);
        end
    end

    // redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_rdcnt(ADD,31249)
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_a = {1'b0, redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_wraddr_q};
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_b = {1'b0, redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_o <= $unsigned(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_a) + $unsigned(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_b);
        end
    end
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_q = redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_o[2:0];

    // redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt(ADD,32901)
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_a = {1'b0, redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_q};
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_o <= $unsigned(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_a) + $unsigned(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_b);
        end
    end
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_q = redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_o[5:0];

    // redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_inputreg0(DELAY,32896)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl);
        end
    end

    // redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr(COUNTER,32899)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_i <= $unsigned(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_q = redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_i[4:0];

    // redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem(DUALMEM,32898)
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_ia = $unsigned(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_inputreg0_q);
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_aa = redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_wraddr_q;
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_ab = redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_aa),
        .data_a(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_ab),
        .q_b(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_q = redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_iq[15:0];

    // redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_outputreg0(DELAY,32897)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_outputreg0_q <= $unsigned(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_mem_q);
        end
    end

    // redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_inputreg0(DELAY,31244)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_inputreg0_q <= $unsigned(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_split_0_outputreg0_q);
        end
    end

    // redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_wraddr(COUNTER,31247)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_wraddr_i <= $unsigned(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_wraddr_q = redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_wraddr_i[1:0];

    // redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem(DUALMEM,31246)
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_ia = $unsigned(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_inputreg0_q);
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_aa = redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_wraddr_q;
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_ab = redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_aa),
        .data_a(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_ab),
        .q_b(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_q = redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_iq[15:0];

    // redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_outputreg0(DELAY,31245)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_outputreg0_q <= $unsigned(redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27979)@47 + 5
    // out q@53
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596(ADD,8561)@53
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod141_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_b = $unsigned({{5{i_shl_i_i_i_i_i_i_20_c_compstr595_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_20_c_compstr595_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_o[33:0];

    // rightShiftStage0_uid16209_dupName_81_i_unnamed_c_compstr0_shift_x(MUX,16208)@53
    assign rightShiftStage0_uid16209_dupName_81_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16209_dupName_81_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_q or rightShiftStage0Idx1_uid16207_dupName_81_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16209_dupName_81_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16209_dupName_81_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_q;
            1'b1 : rightShiftStage0_uid16209_dupName_81_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16207_dupName_81_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16209_dupName_81_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16214_dupName_81_i_unnamed_c_compstr0_shift_x(MUX,16213)@53
    assign rightShiftStage1_uid16214_dupName_81_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16214_dupName_81_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16209_dupName_81_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16212_dupName_81_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16214_dupName_81_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16214_dupName_81_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16209_dupName_81_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16214_dupName_81_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16212_dupName_81_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16214_dupName_81_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16219_dupName_81_i_unnamed_c_compstr0_shift_x(MUX,16218)@53
    assign rightShiftStage2_uid16219_dupName_81_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16219_dupName_81_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16214_dupName_81_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16217_dupName_81_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16219_dupName_81_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16219_dupName_81_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16214_dupName_81_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16219_dupName_81_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16217_dupName_81_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16219_dupName_81_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr597_vt_select_20(BITSELECT,12269)@53
    assign i_unnamed_c_compstr597_vt_select_20_b = rightShiftStage2_uid16219_dupName_81_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr597_vt_join(BITJOIN,12268)@53
    assign i_unnamed_c_compstr597_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr597_vt_select_20_b};

    // i_conv_i_i_i_i_i_20_c_compstr598_sel_x(BITSELECT,3752)@53
    assign i_conv_i_i_i_i_i_20_c_compstr598_sel_x_b = i_unnamed_c_compstr597_vt_join_q[15:0];

    // redist1113_i_conv_i_i_i_i_i_20_c_compstr598_sel_x_b_1(DELAY,29341)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1113_i_conv_i_i_i_i_i_20_c_compstr598_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_20_c_compstr598_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16228_dupName_82_i_unnamed_c_compstr0_shift_x(BITSELECT,16227)@53
    assign rightShiftStage1Idx1Rng8_uid16228_dupName_82_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16227_dupName_82_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16230_dupName_82_i_unnamed_c_compstr0_shift_x(BITJOIN,16229)@53
    assign rightShiftStage1Idx1_uid16230_dupName_82_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16228_dupName_82_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16223_dupName_82_i_unnamed_c_compstr0_shift_x(BITSELECT,16222)@53
    assign rightShiftStage0Idx1Rng4_uid16223_dupName_82_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_q[33:4];

    // rightShiftStage0Idx1_uid16225_dupName_82_i_unnamed_c_compstr0_shift_x(BITJOIN,16224)@53
    assign rightShiftStage0Idx1_uid16225_dupName_82_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16223_dupName_82_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16227_dupName_82_i_unnamed_c_compstr0_shift_x(MUX,16226)@53
    assign rightShiftStage0_uid16227_dupName_82_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16227_dupName_82_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_q or rightShiftStage0Idx1_uid16225_dupName_82_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16227_dupName_82_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16227_dupName_82_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compstr596_q;
            1'b1 : rightShiftStage0_uid16227_dupName_82_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16225_dupName_82_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16227_dupName_82_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16232_dupName_82_i_unnamed_c_compstr0_shift_x(MUX,16231)@53
    assign rightShiftStage1_uid16232_dupName_82_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16232_dupName_82_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16227_dupName_82_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16230_dupName_82_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16232_dupName_82_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16232_dupName_82_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16227_dupName_82_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16232_dupName_82_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16230_dupName_82_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16232_dupName_82_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr599_vt_select_21(BITSELECT,12272)@53
    assign i_unnamed_c_compstr599_vt_select_21_b = rightShiftStage1_uid16232_dupName_82_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr599_vt_join(BITJOIN,12271)@53
    assign i_unnamed_c_compstr599_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr599_vt_select_21_b};

    // i_unnamed_c_compstr600_sel_x(BITSELECT,6259)@53
    assign i_unnamed_c_compstr600_sel_x_b = i_unnamed_c_compstr599_vt_join_q[15:0];

    // i_unnamed_c_compstr601_BitSelect_for_a(BITSELECT,27907)@53
    assign i_unnamed_c_compstr601_BitSelect_for_a_b = i_unnamed_c_compstr600_sel_x_b[0:0];

    // i_unnamed_c_compstr601_join(BITJOIN,27908)@53
    assign i_unnamed_c_compstr601_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr601_BitSelect_for_a_b};

    // i_unnamed_c_compstr601_vt_select_0(BITSELECT,12277)@53
    assign i_unnamed_c_compstr601_vt_select_0_b = i_unnamed_c_compstr601_join_q[0:0];

    // redist33_i_unnamed_c_compstr601_vt_select_0_b_1(DELAY,28261)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist33_i_unnamed_c_compstr601_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr601_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr601_vt_join(BITJOIN,12276)@54
    assign i_unnamed_c_compstr601_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist33_i_unnamed_c_compstr601_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_20_c_compstr602(ADD,7019)@54
    assign i_add_i_i_i_i_i_i_20_c_compstr602_a = {1'b0, i_unnamed_c_compstr601_vt_join_q};
    assign i_add_i_i_i_i_i_i_20_c_compstr602_b = {1'b0, redist1113_i_conv_i_i_i_i_i_20_c_compstr598_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_20_c_compstr602_o = $unsigned(i_add_i_i_i_i_i_i_20_c_compstr602_a) + $unsigned(i_add_i_i_i_i_i_i_20_c_compstr602_b);
    assign i_add_i_i_i_i_i_i_20_c_compstr602_q = i_add_i_i_i_i_i_i_20_c_compstr602_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_20_c_compstr602_sel_x(BITSELECT,2213)@54
    assign bgTrunc_i_add_i_i_i_i_i_i_20_c_compstr602_sel_x_b = i_add_i_i_i_i_i_i_20_c_compstr602_q[15:0];

    // i_conv_i_i_i_i_i_i279_21_c_compstr622_sel_x(BITSELECT,3881)@54
    assign i_conv_i_i_i_i_i_i279_21_c_compstr622_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_20_c_compstr602_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_21_c_compstr622_vt_select_15(BITSELECT,8041)@54
    assign i_conv_i_i_i_i_i_i279_21_c_compstr622_vt_select_15_b = i_conv_i_i_i_i_i_i279_21_c_compstr622_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_21_c_compstr622_vt_join(BITJOIN,8040)@54
    assign i_conv_i_i_i_i_i_i279_21_c_compstr622_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_21_c_compstr622_vt_select_15_b};

    // leftShiftStage0_uid25880_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x(MUX,25879)@54
    assign leftShiftStage0_uid25880_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25880_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_21_c_compstr622_vt_join_q or leftShiftStage0Idx1_uid25878_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25880_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25880_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_21_c_compstr622_vt_join_q;
            1'b1 : leftShiftStage0_uid25880_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25878_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25880_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25885_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x(MUX,25884)@54
    assign leftShiftStage1_uid25885_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25885_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_s or leftShiftStage0_uid25880_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25883_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25885_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25885_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q = leftShiftStage0_uid25880_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25885_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25883_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25885_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25890_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x(MUX,25889)@54
    assign leftShiftStage2_uid25890_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25890_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_s or leftShiftStage1_uid25885_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25888_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25890_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25890_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q = leftShiftStage1_uid25885_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25890_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25888_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25890_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_21_c_compstr623_vt_select_28(BITSELECT,9544)@54
    assign i_shl_i_i_i_i_i_i_21_c_compstr623_vt_select_28_b = leftShiftStage2_uid25890_i_shl_i_i_i_i_i_i_21_c_compstr0_shift_x_q[28:13];

    // redist342_i_shl_i_i_i_i_i_i_21_c_compstr623_vt_select_28_b_1(DELAY,28570)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist342_i_shl_i_i_i_i_i_i_21_c_compstr623_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_21_c_compstr623_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_21_c_compstr623_vt_join(BITJOIN,9543)@55
    assign i_shl_i_i_i_i_i_i_21_c_compstr623_vt_join_q = {redist342_i_shl_i_i_i_i_i_i_21_c_compstr623_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_offset(CONSTANT,29818)
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_offset_q = $unsigned(3'b101);

    // redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_rdcnt(ADD,31267)
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_a = {1'b0, redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_wraddr_q};
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_b = {1'b0, redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_o <= $unsigned(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_a) + $unsigned(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_b);
        end
    end
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_q = redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_o[3:0];

    // redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt(ADD,32919)
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_a = {1'b0, redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_q};
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_o <= $unsigned(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_a) + $unsigned(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_b);
        end
    end
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_q = redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_o[5:0];

    // redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_inputreg0(DELAY,32914)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl);
        end
    end

    // redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr(COUNTER,32917)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_i <= $unsigned(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_q = redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_i[4:0];

    // redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem(DUALMEM,32916)
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_ia = $unsigned(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_inputreg0_q);
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_aa = redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_q;
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_ab = redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_aa),
        .data_a(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_ab),
        .q_b(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_q = redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_iq[15:0];

    // redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_outputreg0(DELAY,32915)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_outputreg0_q <= $unsigned(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_q);
        end
    end

    // redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_inputreg0(DELAY,31262)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_inputreg0_q <= $unsigned(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_split_0_outputreg0_q);
        end
    end

    // redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_wraddr(COUNTER,31265)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_wraddr_i <= $unsigned(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_wraddr_q = redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_wraddr_i[2:0];

    // redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem(DUALMEM,31264)
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_ia = $unsigned(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_inputreg0_q);
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_aa = redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_wraddr_q;
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_ab = redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_aa),
        .data_a(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_ab),
        .q_b(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_q = redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_iq[15:0];

    // redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_outputreg0(DELAY,31263)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_outputreg0_q <= $unsigned(redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_mem_q);
        end
    end

    // redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_rdcnt(ADD,29819)
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_a = {1'b0, redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_wraddr_q};
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_b = {1'b0, redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_o <= $unsigned(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_a) + $unsigned(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_b);
        end
    end
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_q = redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_o[3:0];

    // redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt(ADD,32553)
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_a = {1'b0, redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_q};
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_o <= $unsigned(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_a) + $unsigned(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_b);
        end
    end
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_q = redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_o[5:0];

    // redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_inputreg0(DELAY,32548)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl);
        end
    end

    // redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr(COUNTER,32551)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_i <= $unsigned(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_q = redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_i[4:0];

    // redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem(DUALMEM,32550)
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_ia = $unsigned(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_inputreg0_q);
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_aa = redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_q;
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_ab = redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_aa),
        .data_a(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_ab),
        .q_b(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_q = redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_iq[15:0];

    // redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_outputreg0(DELAY,32549)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_outputreg0_q <= $unsigned(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_q);
        end
    end

    // redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_inputreg0(DELAY,29814)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_inputreg0_q <= $unsigned(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_split_0_outputreg0_q);
        end
    end

    // redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_wraddr(COUNTER,29817)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_wraddr_i <= $unsigned(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_wraddr_q = redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_wraddr_i[2:0];

    // redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem(DUALMEM,29816)
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_ia = $unsigned(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_inputreg0_q);
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_aa = redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_wraddr_q;
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_ab = redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_aa),
        .data_a(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_ab),
        .q_b(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_q = redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_iq[15:0];

    // redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_outputreg0(DELAY,29815)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_outputreg0_q <= $unsigned(redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_mem_q);
        end
    end

    // redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_rdcnt(ADD,29825)
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_a = {1'b0, redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_wraddr_q};
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_b = {1'b0, redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_o <= $unsigned(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_a) + $unsigned(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_b);
        end
    end
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_q = redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_o[3:0];

    // redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt(ADD,32559)
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_a = {1'b0, redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_q};
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_o <= $unsigned(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_a) + $unsigned(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_b);
        end
    end
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_q = redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_o[5:0];

    // redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_inputreg0(DELAY,32554)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl);
        end
    end

    // redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr(COUNTER,32557)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_i <= $unsigned(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_q = redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_i[4:0];

    // redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem(DUALMEM,32556)
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_ia = $unsigned(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_inputreg0_q);
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_aa = redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_wraddr_q;
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_ab = redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_aa),
        .data_a(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_ab),
        .q_b(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_q = redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_iq[15:0];

    // redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_outputreg0(DELAY,32555)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_outputreg0_q <= $unsigned(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_mem_q);
        end
    end

    // redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_inputreg0(DELAY,29820)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_inputreg0_q <= $unsigned(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_split_0_outputreg0_q);
        end
    end

    // redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_wraddr(COUNTER,29823)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_wraddr_i <= $unsigned(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_wraddr_q = redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_wraddr_i[2:0];

    // redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem(DUALMEM,29822)
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_ia = $unsigned(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_inputreg0_q);
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_aa = redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_wraddr_q;
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_ab = redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_aa),
        .data_a(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_ab),
        .q_b(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_q = redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_iq[15:0];

    // redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_outputreg0(DELAY,29821)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_outputreg0_q <= $unsigned(redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_mem_q);
        end
    end

    // redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_rdcnt(ADD,31261)
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_a = {1'b0, redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_wraddr_q};
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_b = {1'b0, redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_o <= $unsigned(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_a) + $unsigned(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_b);
        end
    end
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_q = redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_o[3:0];

    // redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt(ADD,32913)
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_a = {1'b0, redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_q};
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_o <= $unsigned(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_a) + $unsigned(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_b);
        end
    end
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_q = redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_o[5:0];

    // redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_inputreg0(DELAY,32908)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl);
        end
    end

    // redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr(COUNTER,32911)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_i <= $unsigned(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_q = redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_i[4:0];

    // redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem(DUALMEM,32910)
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_ia = $unsigned(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_inputreg0_q);
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_aa = redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_wraddr_q;
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_ab = redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_aa),
        .data_a(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_ab),
        .q_b(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_q = redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_iq[15:0];

    // redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_outputreg0(DELAY,32909)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_outputreg0_q <= $unsigned(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_mem_q);
        end
    end

    // redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_inputreg0(DELAY,31256)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_inputreg0_q <= $unsigned(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_split_0_outputreg0_q);
        end
    end

    // redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_wraddr(COUNTER,31259)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_wraddr_i <= $unsigned(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_wraddr_q = redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_wraddr_i[2:0];

    // redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem(DUALMEM,31258)
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_ia = $unsigned(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_inputreg0_q);
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_aa = redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_wraddr_q;
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_ab = redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_aa),
        .data_a(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_ab),
        .q_b(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_q = redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_iq[15:0];

    // redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_outputreg0(DELAY,31257)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_outputreg0_q <= $unsigned(redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27980)@49 + 5
    // out q@55
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624(ADD,8562)@55
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod146_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_b = $unsigned({{5{i_shl_i_i_i_i_i_i_21_c_compstr623_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_21_c_compstr623_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_o[33:0];

    // rightShiftStage0_uid16271_dupName_85_i_unnamed_c_compstr0_shift_x(MUX,16270)@55
    assign rightShiftStage0_uid16271_dupName_85_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16271_dupName_85_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_q or rightShiftStage0Idx1_uid16269_dupName_85_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16271_dupName_85_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16271_dupName_85_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_q;
            1'b1 : rightShiftStage0_uid16271_dupName_85_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16269_dupName_85_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16271_dupName_85_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16276_dupName_85_i_unnamed_c_compstr0_shift_x(MUX,16275)@55
    assign rightShiftStage1_uid16276_dupName_85_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16276_dupName_85_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16271_dupName_85_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16274_dupName_85_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16276_dupName_85_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16276_dupName_85_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16271_dupName_85_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16276_dupName_85_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16274_dupName_85_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16276_dupName_85_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16281_dupName_85_i_unnamed_c_compstr0_shift_x(MUX,16280)@55
    assign rightShiftStage2_uid16281_dupName_85_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16281_dupName_85_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16276_dupName_85_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16279_dupName_85_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16281_dupName_85_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16281_dupName_85_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16276_dupName_85_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16281_dupName_85_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16279_dupName_85_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16281_dupName_85_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr625_vt_select_20(BITSELECT,12291)@55
    assign i_unnamed_c_compstr625_vt_select_20_b = rightShiftStage2_uid16281_dupName_85_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr625_vt_join(BITJOIN,12290)@55
    assign i_unnamed_c_compstr625_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr625_vt_select_20_b};

    // i_conv_i_i_i_i_i_21_c_compstr626_sel_x(BITSELECT,3753)@55
    assign i_conv_i_i_i_i_i_21_c_compstr626_sel_x_b = i_unnamed_c_compstr625_vt_join_q[15:0];

    // redist1112_i_conv_i_i_i_i_i_21_c_compstr626_sel_x_b_1(DELAY,29340)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1112_i_conv_i_i_i_i_i_21_c_compstr626_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_21_c_compstr626_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16290_dupName_86_i_unnamed_c_compstr0_shift_x(BITSELECT,16289)@55
    assign rightShiftStage1Idx1Rng8_uid16290_dupName_86_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16289_dupName_86_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16292_dupName_86_i_unnamed_c_compstr0_shift_x(BITJOIN,16291)@55
    assign rightShiftStage1Idx1_uid16292_dupName_86_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16290_dupName_86_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16285_dupName_86_i_unnamed_c_compstr0_shift_x(BITSELECT,16284)@55
    assign rightShiftStage0Idx1Rng4_uid16285_dupName_86_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_q[33:4];

    // rightShiftStage0Idx1_uid16287_dupName_86_i_unnamed_c_compstr0_shift_x(BITJOIN,16286)@55
    assign rightShiftStage0Idx1_uid16287_dupName_86_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16285_dupName_86_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16289_dupName_86_i_unnamed_c_compstr0_shift_x(MUX,16288)@55
    assign rightShiftStage0_uid16289_dupName_86_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16289_dupName_86_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_q or rightShiftStage0Idx1_uid16287_dupName_86_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16289_dupName_86_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16289_dupName_86_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compstr624_q;
            1'b1 : rightShiftStage0_uid16289_dupName_86_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16287_dupName_86_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16289_dupName_86_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16294_dupName_86_i_unnamed_c_compstr0_shift_x(MUX,16293)@55
    assign rightShiftStage1_uid16294_dupName_86_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16294_dupName_86_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16289_dupName_86_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16292_dupName_86_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16294_dupName_86_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16294_dupName_86_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16289_dupName_86_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16294_dupName_86_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16292_dupName_86_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16294_dupName_86_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr627_vt_select_21(BITSELECT,12294)@55
    assign i_unnamed_c_compstr627_vt_select_21_b = rightShiftStage1_uid16294_dupName_86_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr627_vt_join(BITJOIN,12293)@55
    assign i_unnamed_c_compstr627_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr627_vt_select_21_b};

    // i_unnamed_c_compstr628_sel_x(BITSELECT,6261)@55
    assign i_unnamed_c_compstr628_sel_x_b = i_unnamed_c_compstr627_vt_join_q[15:0];

    // i_unnamed_c_compstr629_BitSelect_for_a(BITSELECT,27911)@55
    assign i_unnamed_c_compstr629_BitSelect_for_a_b = i_unnamed_c_compstr628_sel_x_b[0:0];

    // i_unnamed_c_compstr629_join(BITJOIN,27912)@55
    assign i_unnamed_c_compstr629_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr629_BitSelect_for_a_b};

    // i_unnamed_c_compstr629_vt_select_0(BITSELECT,12299)@55
    assign i_unnamed_c_compstr629_vt_select_0_b = i_unnamed_c_compstr629_join_q[0:0];

    // redist31_i_unnamed_c_compstr629_vt_select_0_b_1(DELAY,28259)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist31_i_unnamed_c_compstr629_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr629_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr629_vt_join(BITJOIN,12298)@56
    assign i_unnamed_c_compstr629_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist31_i_unnamed_c_compstr629_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_21_c_compstr630(ADD,7020)@56
    assign i_add_i_i_i_i_i_i_21_c_compstr630_a = {1'b0, i_unnamed_c_compstr629_vt_join_q};
    assign i_add_i_i_i_i_i_i_21_c_compstr630_b = {1'b0, redist1112_i_conv_i_i_i_i_i_21_c_compstr626_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_21_c_compstr630_o = $unsigned(i_add_i_i_i_i_i_i_21_c_compstr630_a) + $unsigned(i_add_i_i_i_i_i_i_21_c_compstr630_b);
    assign i_add_i_i_i_i_i_i_21_c_compstr630_q = i_add_i_i_i_i_i_i_21_c_compstr630_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_21_c_compstr630_sel_x(BITSELECT,2214)@56
    assign bgTrunc_i_add_i_i_i_i_i_i_21_c_compstr630_sel_x_b = i_add_i_i_i_i_i_i_21_c_compstr630_q[15:0];

    // i_conv_i_i_i_i_i_i279_22_c_compstr650_sel_x(BITSELECT,3882)@56
    assign i_conv_i_i_i_i_i_i279_22_c_compstr650_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_21_c_compstr630_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_22_c_compstr650_vt_select_15(BITSELECT,8045)@56
    assign i_conv_i_i_i_i_i_i279_22_c_compstr650_vt_select_15_b = i_conv_i_i_i_i_i_i279_22_c_compstr650_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_22_c_compstr650_vt_join(BITJOIN,8044)@56
    assign i_conv_i_i_i_i_i_i279_22_c_compstr650_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_22_c_compstr650_vt_select_15_b};

    // leftShiftStage0_uid25898_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x(MUX,25897)@56
    assign leftShiftStage0_uid25898_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25898_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_22_c_compstr650_vt_join_q or leftShiftStage0Idx1_uid25896_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25898_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25898_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_22_c_compstr650_vt_join_q;
            1'b1 : leftShiftStage0_uid25898_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25896_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25898_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25903_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x(MUX,25902)@56
    assign leftShiftStage1_uid25903_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25903_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_s or leftShiftStage0_uid25898_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25901_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25903_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25903_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q = leftShiftStage0_uid25898_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25903_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25901_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25903_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25908_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x(MUX,25907)@56
    assign leftShiftStage2_uid25908_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25908_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_s or leftShiftStage1_uid25903_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25906_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25908_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25908_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q = leftShiftStage1_uid25903_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25908_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25906_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25908_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_22_c_compstr651_vt_select_28(BITSELECT,9547)@56
    assign i_shl_i_i_i_i_i_i_22_c_compstr651_vt_select_28_b = leftShiftStage2_uid25908_i_shl_i_i_i_i_i_i_22_c_compstr0_shift_x_q[28:13];

    // redist341_i_shl_i_i_i_i_i_i_22_c_compstr651_vt_select_28_b_1(DELAY,28569)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist341_i_shl_i_i_i_i_i_i_22_c_compstr651_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_22_c_compstr651_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_22_c_compstr651_vt_join(BITJOIN,9546)@57
    assign i_shl_i_i_i_i_i_i_22_c_compstr651_vt_join_q = {redist341_i_shl_i_i_i_i_i_i_22_c_compstr651_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_offset(CONSTANT,29830)
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_offset_q = $unsigned(3'b011);

    // redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_rdcnt(ADD,31279)
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_a = {1'b0, redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_wraddr_q};
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_b = {1'b0, redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_o <= $unsigned(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_a) + $unsigned(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_b);
        end
    end
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_q = redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_o[3:0];

    // redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt(ADD,32931)
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_a = {1'b0, redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_q};
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_o <= $unsigned(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_a) + $unsigned(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_b);
        end
    end
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_q = redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_o[5:0];

    // redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_inputreg0(DELAY,32926)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl);
        end
    end

    // redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr(COUNTER,32929)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_i <= $unsigned(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_q = redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_i[4:0];

    // redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem(DUALMEM,32928)
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_ia = $unsigned(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_inputreg0_q);
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_aa = redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_q;
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_ab = redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_aa),
        .data_a(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_ab),
        .q_b(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_q = redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_iq[15:0];

    // redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_outputreg0(DELAY,32927)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_outputreg0_q <= $unsigned(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_q);
        end
    end

    // redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_inputreg0(DELAY,31274)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_inputreg0_q <= $unsigned(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_split_0_outputreg0_q);
        end
    end

    // redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_wraddr(COUNTER,31277)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_wraddr_i <= $unsigned(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_wraddr_q = redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_wraddr_i[2:0];

    // redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem(DUALMEM,31276)
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_ia = $unsigned(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_inputreg0_q);
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_aa = redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_wraddr_q;
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_ab = redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_aa),
        .data_a(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_ab),
        .q_b(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_q = redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_iq[15:0];

    // redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_outputreg0(DELAY,31275)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_outputreg0_q <= $unsigned(redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_mem_q);
        end
    end

    // redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_rdcnt(ADD,29831)
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_a = {1'b0, redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_wraddr_q};
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_b = {1'b0, redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_o <= $unsigned(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_a) + $unsigned(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_b);
        end
    end
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_q = redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_o[3:0];

    // redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt(ADD,32565)
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_a = {1'b0, redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_q};
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_o <= $unsigned(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_a) + $unsigned(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_b);
        end
    end
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_q = redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_o[5:0];

    // redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_inputreg0(DELAY,32560)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl);
        end
    end

    // redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr(COUNTER,32563)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_i <= $unsigned(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_q = redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_i[4:0];

    // redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem(DUALMEM,32562)
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_ia = $unsigned(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_inputreg0_q);
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_aa = redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_q;
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_ab = redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_aa),
        .data_a(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_ab),
        .q_b(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_q = redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_iq[15:0];

    // redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_outputreg0(DELAY,32561)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_outputreg0_q <= $unsigned(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_q);
        end
    end

    // redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_inputreg0(DELAY,29826)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_inputreg0_q <= $unsigned(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_split_0_outputreg0_q);
        end
    end

    // redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_wraddr(COUNTER,29829)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_wraddr_i <= $unsigned(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_wraddr_q = redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_wraddr_i[2:0];

    // redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem(DUALMEM,29828)
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_ia = $unsigned(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_inputreg0_q);
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_aa = redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_wraddr_q;
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_ab = redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_aa),
        .data_a(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_ab),
        .q_b(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_q = redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_iq[15:0];

    // redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_outputreg0(DELAY,29827)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_outputreg0_q <= $unsigned(redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_mem_q);
        end
    end

    // redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_rdcnt(ADD,29837)
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_a = {1'b0, redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_wraddr_q};
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_b = {1'b0, redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_o <= $unsigned(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_a) + $unsigned(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_b);
        end
    end
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_q = redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_o[3:0];

    // redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt(ADD,32571)
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_a = {1'b0, redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_q};
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_o <= $unsigned(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_a) + $unsigned(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_b);
        end
    end
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_q = redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_o[5:0];

    // redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_inputreg0(DELAY,32566)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl);
        end
    end

    // redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr(COUNTER,32569)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_i <= $unsigned(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_q = redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_i[4:0];

    // redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem(DUALMEM,32568)
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_ia = $unsigned(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_inputreg0_q);
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_aa = redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_wraddr_q;
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_ab = redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_aa),
        .data_a(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_ab),
        .q_b(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_q = redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_iq[15:0];

    // redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_outputreg0(DELAY,32567)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_outputreg0_q <= $unsigned(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_mem_q);
        end
    end

    // redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_inputreg0(DELAY,29832)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_inputreg0_q <= $unsigned(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_split_0_outputreg0_q);
        end
    end

    // redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_wraddr(COUNTER,29835)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_wraddr_i <= $unsigned(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_wraddr_q = redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_wraddr_i[2:0];

    // redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem(DUALMEM,29834)
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_ia = $unsigned(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_inputreg0_q);
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_aa = redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_wraddr_q;
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_ab = redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_aa),
        .data_a(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_ab),
        .q_b(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_q = redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_iq[15:0];

    // redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_outputreg0(DELAY,29833)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_outputreg0_q <= $unsigned(redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_mem_q);
        end
    end

    // redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_rdcnt(ADD,31273)
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_a = {1'b0, redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_wraddr_q};
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_b = {1'b0, redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_o <= $unsigned(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_a) + $unsigned(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_b);
        end
    end
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_q = redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_o[3:0];

    // redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt(ADD,32925)
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_a = {1'b0, redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_q};
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_o <= $unsigned(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_a) + $unsigned(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_b);
        end
    end
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_q = redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_o[5:0];

    // redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_inputreg0(DELAY,32920)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl);
        end
    end

    // redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr(COUNTER,32923)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_i <= $unsigned(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_q = redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_i[4:0];

    // redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem(DUALMEM,32922)
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_ia = $unsigned(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_inputreg0_q);
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_aa = redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_wraddr_q;
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_ab = redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_aa),
        .data_a(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_ab),
        .q_b(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_q = redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_iq[15:0];

    // redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_outputreg0(DELAY,32921)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_outputreg0_q <= $unsigned(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_mem_q);
        end
    end

    // redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_inputreg0(DELAY,31268)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_inputreg0_q <= $unsigned(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_split_0_outputreg0_q);
        end
    end

    // redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_wraddr(COUNTER,31271)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_wraddr_i <= $unsigned(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_wraddr_q = redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_wraddr_i[2:0];

    // redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem(DUALMEM,31270)
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_ia = $unsigned(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_inputreg0_q);
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_aa = redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_wraddr_q;
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_ab = redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_aa),
        .data_a(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_ab),
        .q_b(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_q = redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_iq[15:0];

    // redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_outputreg0(DELAY,31269)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_outputreg0_q <= $unsigned(redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27981)@51 + 5
    // out q@57
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652(ADD,8563)@57
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod151_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_b = $unsigned({{5{i_shl_i_i_i_i_i_i_22_c_compstr651_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_22_c_compstr651_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_o[33:0];

    // rightShiftStage0_uid16333_dupName_89_i_unnamed_c_compstr0_shift_x(MUX,16332)@57
    assign rightShiftStage0_uid16333_dupName_89_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16333_dupName_89_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_q or rightShiftStage0Idx1_uid16331_dupName_89_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16333_dupName_89_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16333_dupName_89_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_q;
            1'b1 : rightShiftStage0_uid16333_dupName_89_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16331_dupName_89_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16333_dupName_89_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16338_dupName_89_i_unnamed_c_compstr0_shift_x(MUX,16337)@57
    assign rightShiftStage1_uid16338_dupName_89_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16338_dupName_89_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16333_dupName_89_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16336_dupName_89_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16338_dupName_89_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16338_dupName_89_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16333_dupName_89_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16338_dupName_89_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16336_dupName_89_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16338_dupName_89_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16343_dupName_89_i_unnamed_c_compstr0_shift_x(MUX,16342)@57
    assign rightShiftStage2_uid16343_dupName_89_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16343_dupName_89_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16338_dupName_89_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16341_dupName_89_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16343_dupName_89_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16343_dupName_89_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16338_dupName_89_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16343_dupName_89_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16341_dupName_89_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16343_dupName_89_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr653_vt_select_20(BITSELECT,12313)@57
    assign i_unnamed_c_compstr653_vt_select_20_b = rightShiftStage2_uid16343_dupName_89_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr653_vt_join(BITJOIN,12312)@57
    assign i_unnamed_c_compstr653_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr653_vt_select_20_b};

    // i_conv_i_i_i_i_i_22_c_compstr654_sel_x(BITSELECT,3754)@57
    assign i_conv_i_i_i_i_i_22_c_compstr654_sel_x_b = i_unnamed_c_compstr653_vt_join_q[15:0];

    // redist1111_i_conv_i_i_i_i_i_22_c_compstr654_sel_x_b_1(DELAY,29339)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1111_i_conv_i_i_i_i_i_22_c_compstr654_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_22_c_compstr654_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16352_dupName_90_i_unnamed_c_compstr0_shift_x(BITSELECT,16351)@57
    assign rightShiftStage1Idx1Rng8_uid16352_dupName_90_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16351_dupName_90_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16354_dupName_90_i_unnamed_c_compstr0_shift_x(BITJOIN,16353)@57
    assign rightShiftStage1Idx1_uid16354_dupName_90_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16352_dupName_90_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16347_dupName_90_i_unnamed_c_compstr0_shift_x(BITSELECT,16346)@57
    assign rightShiftStage0Idx1Rng4_uid16347_dupName_90_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_q[33:4];

    // rightShiftStage0Idx1_uid16349_dupName_90_i_unnamed_c_compstr0_shift_x(BITJOIN,16348)@57
    assign rightShiftStage0Idx1_uid16349_dupName_90_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16347_dupName_90_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16351_dupName_90_i_unnamed_c_compstr0_shift_x(MUX,16350)@57
    assign rightShiftStage0_uid16351_dupName_90_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16351_dupName_90_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_q or rightShiftStage0Idx1_uid16349_dupName_90_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16351_dupName_90_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16351_dupName_90_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compstr652_q;
            1'b1 : rightShiftStage0_uid16351_dupName_90_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16349_dupName_90_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16351_dupName_90_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16356_dupName_90_i_unnamed_c_compstr0_shift_x(MUX,16355)@57
    assign rightShiftStage1_uid16356_dupName_90_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16356_dupName_90_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16351_dupName_90_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16354_dupName_90_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16356_dupName_90_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16356_dupName_90_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16351_dupName_90_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16356_dupName_90_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16354_dupName_90_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16356_dupName_90_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr655_vt_select_21(BITSELECT,12316)@57
    assign i_unnamed_c_compstr655_vt_select_21_b = rightShiftStage1_uid16356_dupName_90_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr655_vt_join(BITJOIN,12315)@57
    assign i_unnamed_c_compstr655_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr655_vt_select_21_b};

    // i_unnamed_c_compstr656_sel_x(BITSELECT,6263)@57
    assign i_unnamed_c_compstr656_sel_x_b = i_unnamed_c_compstr655_vt_join_q[15:0];

    // i_unnamed_c_compstr657_BitSelect_for_a(BITSELECT,27915)@57
    assign i_unnamed_c_compstr657_BitSelect_for_a_b = i_unnamed_c_compstr656_sel_x_b[0:0];

    // i_unnamed_c_compstr657_join(BITJOIN,27916)@57
    assign i_unnamed_c_compstr657_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr657_BitSelect_for_a_b};

    // i_unnamed_c_compstr657_vt_select_0(BITSELECT,12321)@57
    assign i_unnamed_c_compstr657_vt_select_0_b = i_unnamed_c_compstr657_join_q[0:0];

    // redist29_i_unnamed_c_compstr657_vt_select_0_b_1(DELAY,28257)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist29_i_unnamed_c_compstr657_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr657_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr657_vt_join(BITJOIN,12320)@58
    assign i_unnamed_c_compstr657_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist29_i_unnamed_c_compstr657_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_22_c_compstr658(ADD,7021)@58
    assign i_add_i_i_i_i_i_i_22_c_compstr658_a = {1'b0, i_unnamed_c_compstr657_vt_join_q};
    assign i_add_i_i_i_i_i_i_22_c_compstr658_b = {1'b0, redist1111_i_conv_i_i_i_i_i_22_c_compstr654_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_22_c_compstr658_o = $unsigned(i_add_i_i_i_i_i_i_22_c_compstr658_a) + $unsigned(i_add_i_i_i_i_i_i_22_c_compstr658_b);
    assign i_add_i_i_i_i_i_i_22_c_compstr658_q = i_add_i_i_i_i_i_i_22_c_compstr658_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_22_c_compstr658_sel_x(BITSELECT,2215)@58
    assign bgTrunc_i_add_i_i_i_i_i_i_22_c_compstr658_sel_x_b = i_add_i_i_i_i_i_i_22_c_compstr658_q[15:0];

    // i_conv_i_i_i_i_i_i279_23_c_compstr678_sel_x(BITSELECT,3883)@58
    assign i_conv_i_i_i_i_i_i279_23_c_compstr678_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_22_c_compstr658_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_23_c_compstr678_vt_select_15(BITSELECT,8049)@58
    assign i_conv_i_i_i_i_i_i279_23_c_compstr678_vt_select_15_b = i_conv_i_i_i_i_i_i279_23_c_compstr678_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_23_c_compstr678_vt_join(BITJOIN,8048)@58
    assign i_conv_i_i_i_i_i_i279_23_c_compstr678_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_23_c_compstr678_vt_select_15_b};

    // leftShiftStage0_uid25916_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x(MUX,25915)@58
    assign leftShiftStage0_uid25916_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25916_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_23_c_compstr678_vt_join_q or leftShiftStage0Idx1_uid25914_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25916_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25916_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_23_c_compstr678_vt_join_q;
            1'b1 : leftShiftStage0_uid25916_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25914_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25916_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25921_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x(MUX,25920)@58
    assign leftShiftStage1_uid25921_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25921_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_s or leftShiftStage0_uid25916_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25919_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25921_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25921_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q = leftShiftStage0_uid25916_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25921_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25919_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25921_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25926_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x(MUX,25925)@58
    assign leftShiftStage2_uid25926_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25926_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_s or leftShiftStage1_uid25921_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25924_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25926_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25926_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q = leftShiftStage1_uid25921_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25926_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25924_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25926_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_23_c_compstr679_vt_select_28(BITSELECT,9550)@58
    assign i_shl_i_i_i_i_i_i_23_c_compstr679_vt_select_28_b = leftShiftStage2_uid25926_i_shl_i_i_i_i_i_i_23_c_compstr0_shift_x_q[28:13];

    // redist340_i_shl_i_i_i_i_i_i_23_c_compstr679_vt_select_28_b_1(DELAY,28568)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist340_i_shl_i_i_i_i_i_i_23_c_compstr679_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_23_c_compstr679_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_23_c_compstr679_vt_join(BITJOIN,9549)@59
    assign i_shl_i_i_i_i_i_i_23_c_compstr679_vt_join_q = {redist340_i_shl_i_i_i_i_i_i_23_c_compstr679_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_offset(CONSTANT,29842)
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_offset_q = $unsigned(4'b1001);

    // redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_rdcnt(ADD,31291)
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_a = {1'b0, redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_wraddr_q};
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_b = {1'b0, redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_o <= $unsigned(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_a) + $unsigned(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_b);
        end
    end
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_q = redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_o[4:0];

    // redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt(ADD,32943)
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_a = {1'b0, redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_q};
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_o <= $unsigned(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_a) + $unsigned(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_b);
        end
    end
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_q = redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_o[5:0];

    // redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_inputreg0(DELAY,32938)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl);
        end
    end

    // redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr(COUNTER,32941)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_i <= $unsigned(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_q = redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_i[4:0];

    // redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem(DUALMEM,32940)
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_ia = $unsigned(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_inputreg0_q);
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_aa = redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_q;
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_ab = redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_aa),
        .data_a(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_ab),
        .q_b(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_q = redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_iq[15:0];

    // redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_outputreg0(DELAY,32939)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_outputreg0_q <= $unsigned(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_q);
        end
    end

    // redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_inputreg0(DELAY,31286)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_inputreg0_q <= $unsigned(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_split_0_outputreg0_q);
        end
    end

    // redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_wraddr(COUNTER,31289)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_wraddr_i <= $unsigned(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_wraddr_q = redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_wraddr_i[3:0];

    // redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem(DUALMEM,31288)
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_ia = $unsigned(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_inputreg0_q);
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_aa = redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_wraddr_q;
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_ab = redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_aa),
        .data_a(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_ab),
        .q_b(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_q = redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_iq[15:0];

    // redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_outputreg0(DELAY,31287)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_outputreg0_q <= $unsigned(redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_mem_q);
        end
    end

    // redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_rdcnt(ADD,29843)
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_a = {1'b0, redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_wraddr_q};
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_b = {1'b0, redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_o <= $unsigned(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_a) + $unsigned(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_b);
        end
    end
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_q = redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_o[4:0];

    // redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt(ADD,32577)
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_a = {1'b0, redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_q};
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_o <= $unsigned(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_a) + $unsigned(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_b);
        end
    end
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_q = redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_o[5:0];

    // redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_inputreg0(DELAY,32572)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl);
        end
    end

    // redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr(COUNTER,32575)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_i <= $unsigned(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_q = redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_i[4:0];

    // redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem(DUALMEM,32574)
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_ia = $unsigned(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_inputreg0_q);
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_aa = redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_q;
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_ab = redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_aa),
        .data_a(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_ab),
        .q_b(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_q = redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_iq[15:0];

    // redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_outputreg0(DELAY,32573)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_outputreg0_q <= $unsigned(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_q);
        end
    end

    // redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_inputreg0(DELAY,29838)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_inputreg0_q <= $unsigned(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_split_0_outputreg0_q);
        end
    end

    // redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_wraddr(COUNTER,29841)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_wraddr_i <= $unsigned(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_wraddr_q = redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_wraddr_i[3:0];

    // redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem(DUALMEM,29840)
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_ia = $unsigned(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_inputreg0_q);
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_aa = redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_wraddr_q;
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_ab = redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_aa),
        .data_a(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_ab),
        .q_b(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_q = redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_iq[15:0];

    // redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_outputreg0(DELAY,29839)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_outputreg0_q <= $unsigned(redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_mem_q);
        end
    end

    // redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_rdcnt(ADD,29849)
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_a = {1'b0, redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_wraddr_q};
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_b = {1'b0, redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_o <= $unsigned(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_a) + $unsigned(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_b);
        end
    end
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_q = redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_o[4:0];

    // redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt(ADD,32583)
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_a = {1'b0, redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_q};
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_o <= $unsigned(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_a) + $unsigned(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_b);
        end
    end
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_q = redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_o[5:0];

    // redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_inputreg0(DELAY,32578)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl);
        end
    end

    // redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr(COUNTER,32581)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_i <= $unsigned(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_q = redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_i[4:0];

    // redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem(DUALMEM,32580)
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_ia = $unsigned(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_inputreg0_q);
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_aa = redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_wraddr_q;
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_ab = redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_aa),
        .data_a(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_ab),
        .q_b(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_q = redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_iq[15:0];

    // redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_outputreg0(DELAY,32579)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_outputreg0_q <= $unsigned(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_mem_q);
        end
    end

    // redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_inputreg0(DELAY,29844)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_inputreg0_q <= $unsigned(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_split_0_outputreg0_q);
        end
    end

    // redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_wraddr(COUNTER,29847)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_wraddr_i <= $unsigned(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_wraddr_q = redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_wraddr_i[3:0];

    // redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem(DUALMEM,29846)
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_ia = $unsigned(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_inputreg0_q);
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_aa = redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_wraddr_q;
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_ab = redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_aa),
        .data_a(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_ab),
        .q_b(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_q = redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_iq[15:0];

    // redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_outputreg0(DELAY,29845)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_outputreg0_q <= $unsigned(redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_mem_q);
        end
    end

    // redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_rdcnt(ADD,31285)
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_a = {1'b0, redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_wraddr_q};
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_b = {1'b0, redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_o <= $unsigned(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_a) + $unsigned(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_b);
        end
    end
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_q = redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_o[4:0];

    // redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt(ADD,32937)
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_a = {1'b0, redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_q};
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_o <= $unsigned(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_a) + $unsigned(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_b);
        end
    end
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_q = redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_o[5:0];

    // redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_inputreg0(DELAY,32932)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl);
        end
    end

    // redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr(COUNTER,32935)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_i <= $unsigned(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_q = redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_i[4:0];

    // redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem(DUALMEM,32934)
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_ia = $unsigned(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_inputreg0_q);
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_aa = redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_wraddr_q;
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_ab = redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_aa),
        .data_a(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_ab),
        .q_b(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_q = redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_iq[15:0];

    // redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_outputreg0(DELAY,32933)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_outputreg0_q <= $unsigned(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_mem_q);
        end
    end

    // redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_inputreg0(DELAY,31280)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_inputreg0_q <= $unsigned(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_split_0_outputreg0_q);
        end
    end

    // redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_wraddr(COUNTER,31283)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_wraddr_i <= $unsigned(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_wraddr_q = redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_wraddr_i[3:0];

    // redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem(DUALMEM,31282)
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_ia = $unsigned(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_inputreg0_q);
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_aa = redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_wraddr_q;
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_ab = redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_aa),
        .data_a(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_ab),
        .q_b(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_q = redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_iq[15:0];

    // redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_outputreg0(DELAY,31281)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_outputreg0_q <= $unsigned(redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27982)@53 + 5
    // out q@59
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680(ADD,8564)@59
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod156_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_b = $unsigned({{5{i_shl_i_i_i_i_i_i_23_c_compstr679_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_23_c_compstr679_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_o[33:0];

    // rightShiftStage0_uid16395_dupName_93_i_unnamed_c_compstr0_shift_x(MUX,16394)@59
    assign rightShiftStage0_uid16395_dupName_93_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16395_dupName_93_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_q or rightShiftStage0Idx1_uid16393_dupName_93_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16395_dupName_93_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16395_dupName_93_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_q;
            1'b1 : rightShiftStage0_uid16395_dupName_93_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16393_dupName_93_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16395_dupName_93_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16400_dupName_93_i_unnamed_c_compstr0_shift_x(MUX,16399)@59
    assign rightShiftStage1_uid16400_dupName_93_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16400_dupName_93_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16395_dupName_93_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16398_dupName_93_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16400_dupName_93_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16400_dupName_93_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16395_dupName_93_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16400_dupName_93_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16398_dupName_93_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16400_dupName_93_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16405_dupName_93_i_unnamed_c_compstr0_shift_x(MUX,16404)@59
    assign rightShiftStage2_uid16405_dupName_93_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16405_dupName_93_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16400_dupName_93_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16403_dupName_93_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16405_dupName_93_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16405_dupName_93_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16400_dupName_93_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16405_dupName_93_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16403_dupName_93_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16405_dupName_93_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr681_vt_select_20(BITSELECT,12341)@59
    assign i_unnamed_c_compstr681_vt_select_20_b = rightShiftStage2_uid16405_dupName_93_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr681_vt_join(BITJOIN,12340)@59
    assign i_unnamed_c_compstr681_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr681_vt_select_20_b};

    // i_conv_i_i_i_i_i_23_c_compstr682_sel_x(BITSELECT,3755)@59
    assign i_conv_i_i_i_i_i_23_c_compstr682_sel_x_b = i_unnamed_c_compstr681_vt_join_q[15:0];

    // redist1110_i_conv_i_i_i_i_i_23_c_compstr682_sel_x_b_1(DELAY,29338)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1110_i_conv_i_i_i_i_i_23_c_compstr682_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_23_c_compstr682_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16414_dupName_94_i_unnamed_c_compstr0_shift_x(BITSELECT,16413)@59
    assign rightShiftStage1Idx1Rng8_uid16414_dupName_94_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16413_dupName_94_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16416_dupName_94_i_unnamed_c_compstr0_shift_x(BITJOIN,16415)@59
    assign rightShiftStage1Idx1_uid16416_dupName_94_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16414_dupName_94_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16409_dupName_94_i_unnamed_c_compstr0_shift_x(BITSELECT,16408)@59
    assign rightShiftStage0Idx1Rng4_uid16409_dupName_94_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_q[33:4];

    // rightShiftStage0Idx1_uid16411_dupName_94_i_unnamed_c_compstr0_shift_x(BITJOIN,16410)@59
    assign rightShiftStage0Idx1_uid16411_dupName_94_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16409_dupName_94_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16413_dupName_94_i_unnamed_c_compstr0_shift_x(MUX,16412)@59
    assign rightShiftStage0_uid16413_dupName_94_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16413_dupName_94_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_q or rightShiftStage0Idx1_uid16411_dupName_94_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16413_dupName_94_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16413_dupName_94_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compstr680_q;
            1'b1 : rightShiftStage0_uid16413_dupName_94_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16411_dupName_94_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16413_dupName_94_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16418_dupName_94_i_unnamed_c_compstr0_shift_x(MUX,16417)@59
    assign rightShiftStage1_uid16418_dupName_94_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16418_dupName_94_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16413_dupName_94_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16416_dupName_94_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16418_dupName_94_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16418_dupName_94_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16413_dupName_94_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16418_dupName_94_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16416_dupName_94_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16418_dupName_94_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr683_vt_select_21(BITSELECT,12344)@59
    assign i_unnamed_c_compstr683_vt_select_21_b = rightShiftStage1_uid16418_dupName_94_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr683_vt_join(BITJOIN,12343)@59
    assign i_unnamed_c_compstr683_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr683_vt_select_21_b};

    // i_unnamed_c_compstr684_sel_x(BITSELECT,6266)@59
    assign i_unnamed_c_compstr684_sel_x_b = i_unnamed_c_compstr683_vt_join_q[15:0];

    // i_unnamed_c_compstr685_BitSelect_for_a(BITSELECT,27919)@59
    assign i_unnamed_c_compstr685_BitSelect_for_a_b = i_unnamed_c_compstr684_sel_x_b[0:0];

    // i_unnamed_c_compstr685_join(BITJOIN,27920)@59
    assign i_unnamed_c_compstr685_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr685_BitSelect_for_a_b};

    // i_unnamed_c_compstr685_vt_select_0(BITSELECT,12349)@59
    assign i_unnamed_c_compstr685_vt_select_0_b = i_unnamed_c_compstr685_join_q[0:0];

    // redist27_i_unnamed_c_compstr685_vt_select_0_b_1(DELAY,28255)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist27_i_unnamed_c_compstr685_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr685_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr685_vt_join(BITJOIN,12348)@60
    assign i_unnamed_c_compstr685_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist27_i_unnamed_c_compstr685_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_23_c_compstr686(ADD,7022)@60
    assign i_add_i_i_i_i_i_i_23_c_compstr686_a = {1'b0, i_unnamed_c_compstr685_vt_join_q};
    assign i_add_i_i_i_i_i_i_23_c_compstr686_b = {1'b0, redist1110_i_conv_i_i_i_i_i_23_c_compstr682_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_23_c_compstr686_o = $unsigned(i_add_i_i_i_i_i_i_23_c_compstr686_a) + $unsigned(i_add_i_i_i_i_i_i_23_c_compstr686_b);
    assign i_add_i_i_i_i_i_i_23_c_compstr686_q = i_add_i_i_i_i_i_i_23_c_compstr686_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_23_c_compstr686_sel_x(BITSELECT,2216)@60
    assign bgTrunc_i_add_i_i_i_i_i_i_23_c_compstr686_sel_x_b = i_add_i_i_i_i_i_i_23_c_compstr686_q[15:0];

    // i_conv_i_i_i_i_i_i279_24_c_compstr706_sel_x(BITSELECT,3884)@60
    assign i_conv_i_i_i_i_i_i279_24_c_compstr706_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_23_c_compstr686_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_24_c_compstr706_vt_select_15(BITSELECT,8053)@60
    assign i_conv_i_i_i_i_i_i279_24_c_compstr706_vt_select_15_b = i_conv_i_i_i_i_i_i279_24_c_compstr706_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_24_c_compstr706_vt_join(BITJOIN,8052)@60
    assign i_conv_i_i_i_i_i_i279_24_c_compstr706_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_24_c_compstr706_vt_select_15_b};

    // leftShiftStage0_uid25934_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x(MUX,25933)@60
    assign leftShiftStage0_uid25934_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25934_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_24_c_compstr706_vt_join_q or leftShiftStage0Idx1_uid25932_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25934_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25934_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_24_c_compstr706_vt_join_q;
            1'b1 : leftShiftStage0_uid25934_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25932_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25934_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25939_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x(MUX,25938)@60
    assign leftShiftStage1_uid25939_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25939_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_s or leftShiftStage0_uid25934_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25937_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25939_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25939_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q = leftShiftStage0_uid25934_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25939_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25937_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25939_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25944_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x(MUX,25943)@60
    assign leftShiftStage2_uid25944_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25944_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_s or leftShiftStage1_uid25939_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25942_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25944_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25944_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q = leftShiftStage1_uid25939_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25944_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25942_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25944_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_24_c_compstr707_vt_select_28(BITSELECT,9553)@60
    assign i_shl_i_i_i_i_i_i_24_c_compstr707_vt_select_28_b = leftShiftStage2_uid25944_i_shl_i_i_i_i_i_i_24_c_compstr0_shift_x_q[28:13];

    // redist339_i_shl_i_i_i_i_i_i_24_c_compstr707_vt_select_28_b_1(DELAY,28567)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist339_i_shl_i_i_i_i_i_i_24_c_compstr707_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_24_c_compstr707_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_24_c_compstr707_vt_join(BITJOIN,9552)@61
    assign i_shl_i_i_i_i_i_i_24_c_compstr707_vt_join_q = {redist339_i_shl_i_i_i_i_i_i_24_c_compstr707_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_offset(CONSTANT,29854)
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_offset_q = $unsigned(4'b0111);

    // redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_rdcnt(ADD,31303)
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_a = {1'b0, redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_wraddr_q};
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_b = {1'b0, redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_o <= $unsigned(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_a) + $unsigned(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_b);
        end
    end
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_q = redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_o[4:0];

    // redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt(ADD,32955)
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_a = {1'b0, redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_q};
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_o <= $unsigned(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_a) + $unsigned(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_b);
        end
    end
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_q = redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_o[5:0];

    // redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_inputreg0(DELAY,32950)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl);
        end
    end

    // redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr(COUNTER,32953)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_i <= $unsigned(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_q = redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_i[4:0];

    // redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem(DUALMEM,32952)
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_ia = $unsigned(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_inputreg0_q);
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_aa = redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_q;
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_ab = redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_aa),
        .data_a(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_ab),
        .q_b(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_q = redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_iq[15:0];

    // redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_outputreg0(DELAY,32951)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_outputreg0_q <= $unsigned(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_q);
        end
    end

    // redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_inputreg0(DELAY,31298)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_inputreg0_q <= $unsigned(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_split_0_outputreg0_q);
        end
    end

    // redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_wraddr(COUNTER,31301)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_wraddr_i <= $unsigned(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_wraddr_q = redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_wraddr_i[3:0];

    // redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem(DUALMEM,31300)
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_ia = $unsigned(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_inputreg0_q);
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_aa = redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_wraddr_q;
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_ab = redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_aa),
        .data_a(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_ab),
        .q_b(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_q = redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_iq[15:0];

    // redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_outputreg0(DELAY,31299)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_outputreg0_q <= $unsigned(redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_mem_q);
        end
    end

    // redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_rdcnt(ADD,29855)
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_a = {1'b0, redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_wraddr_q};
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_b = {1'b0, redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_o <= $unsigned(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_a) + $unsigned(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_b);
        end
    end
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_q = redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_o[4:0];

    // redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt(ADD,32589)
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_a = {1'b0, redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_q};
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_o <= $unsigned(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_a) + $unsigned(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_b);
        end
    end
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_q = redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_o[5:0];

    // redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_inputreg0(DELAY,32584)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl);
        end
    end

    // redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr(COUNTER,32587)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_i <= $unsigned(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_q = redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_i[4:0];

    // redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem(DUALMEM,32586)
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_ia = $unsigned(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_inputreg0_q);
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_aa = redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_q;
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_ab = redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_aa),
        .data_a(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_ab),
        .q_b(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_q = redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_iq[15:0];

    // redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_outputreg0(DELAY,32585)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_outputreg0_q <= $unsigned(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_q);
        end
    end

    // redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_inputreg0(DELAY,29850)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_inputreg0_q <= $unsigned(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_split_0_outputreg0_q);
        end
    end

    // redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_wraddr(COUNTER,29853)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_wraddr_i <= $unsigned(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_wraddr_q = redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_wraddr_i[3:0];

    // redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem(DUALMEM,29852)
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_ia = $unsigned(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_inputreg0_q);
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_aa = redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_wraddr_q;
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_ab = redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_aa),
        .data_a(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_ab),
        .q_b(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_q = redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_iq[15:0];

    // redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_outputreg0(DELAY,29851)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_outputreg0_q <= $unsigned(redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_mem_q);
        end
    end

    // redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_rdcnt(ADD,29861)
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_a = {1'b0, redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_wraddr_q};
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_b = {1'b0, redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_o <= $unsigned(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_a) + $unsigned(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_b);
        end
    end
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_q = redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_o[4:0];

    // redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt(ADD,32595)
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_a = {1'b0, redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_q};
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_o <= $unsigned(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_a) + $unsigned(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_b);
        end
    end
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_q = redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_o[5:0];

    // redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_inputreg0(DELAY,32590)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl);
        end
    end

    // redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr(COUNTER,32593)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_i <= $unsigned(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_q = redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_i[4:0];

    // redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem(DUALMEM,32592)
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_ia = $unsigned(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_inputreg0_q);
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_aa = redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_wraddr_q;
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_ab = redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_aa),
        .data_a(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_ab),
        .q_b(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_q = redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_iq[15:0];

    // redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_outputreg0(DELAY,32591)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_outputreg0_q <= $unsigned(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_mem_q);
        end
    end

    // redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_inputreg0(DELAY,29856)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_inputreg0_q <= $unsigned(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_split_0_outputreg0_q);
        end
    end

    // redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_wraddr(COUNTER,29859)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_wraddr_i <= $unsigned(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_wraddr_q = redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_wraddr_i[3:0];

    // redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem(DUALMEM,29858)
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_ia = $unsigned(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_inputreg0_q);
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_aa = redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_wraddr_q;
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_ab = redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_aa),
        .data_a(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_ab),
        .q_b(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_q = redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_iq[15:0];

    // redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_outputreg0(DELAY,29857)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_outputreg0_q <= $unsigned(redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_mem_q);
        end
    end

    // redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_rdcnt(ADD,31297)
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_a = {1'b0, redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_wraddr_q};
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_b = {1'b0, redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_o <= $unsigned(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_a) + $unsigned(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_b);
        end
    end
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_q = redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_o[4:0];

    // redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt(ADD,32949)
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_a = {1'b0, redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_q};
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_o <= $unsigned(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_a) + $unsigned(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_b);
        end
    end
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_q = redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_o[5:0];

    // redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_inputreg0(DELAY,32944)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl);
        end
    end

    // redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr(COUNTER,32947)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_i <= $unsigned(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_q = redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_i[4:0];

    // redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem(DUALMEM,32946)
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_ia = $unsigned(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_inputreg0_q);
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_aa = redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_wraddr_q;
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_ab = redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_aa),
        .data_a(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_ab),
        .q_b(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_q = redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_iq[15:0];

    // redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_outputreg0(DELAY,32945)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_outputreg0_q <= $unsigned(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_mem_q);
        end
    end

    // redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_inputreg0(DELAY,31292)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_inputreg0_q <= $unsigned(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_split_0_outputreg0_q);
        end
    end

    // redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_wraddr(COUNTER,31295)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_wraddr_i <= $unsigned(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_wraddr_q = redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_wraddr_i[3:0];

    // redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem(DUALMEM,31294)
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_ia = $unsigned(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_inputreg0_q);
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_aa = redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_wraddr_q;
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_ab = redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_aa),
        .data_a(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_ab),
        .q_b(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_q = redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_iq[15:0];

    // redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_outputreg0(DELAY,31293)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_outputreg0_q <= $unsigned(redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27983)@55 + 5
    // out q@61
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708(ADD,8565)@61
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod161_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_b = $unsigned({{5{i_shl_i_i_i_i_i_i_24_c_compstr707_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_24_c_compstr707_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_o[33:0];

    // rightShiftStage0_uid16457_dupName_97_i_unnamed_c_compstr0_shift_x(MUX,16456)@61
    assign rightShiftStage0_uid16457_dupName_97_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16457_dupName_97_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_q or rightShiftStage0Idx1_uid16455_dupName_97_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16457_dupName_97_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16457_dupName_97_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_q;
            1'b1 : rightShiftStage0_uid16457_dupName_97_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16455_dupName_97_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16457_dupName_97_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16462_dupName_97_i_unnamed_c_compstr0_shift_x(MUX,16461)@61
    assign rightShiftStage1_uid16462_dupName_97_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16462_dupName_97_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16457_dupName_97_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16460_dupName_97_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16462_dupName_97_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16462_dupName_97_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16457_dupName_97_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16462_dupName_97_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16460_dupName_97_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16462_dupName_97_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16467_dupName_97_i_unnamed_c_compstr0_shift_x(MUX,16466)@61
    assign rightShiftStage2_uid16467_dupName_97_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16467_dupName_97_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16462_dupName_97_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16465_dupName_97_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16467_dupName_97_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16467_dupName_97_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16462_dupName_97_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16467_dupName_97_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16465_dupName_97_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16467_dupName_97_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr709_vt_select_20(BITSELECT,12368)@61
    assign i_unnamed_c_compstr709_vt_select_20_b = rightShiftStage2_uid16467_dupName_97_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr709_vt_join(BITJOIN,12367)@61
    assign i_unnamed_c_compstr709_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr709_vt_select_20_b};

    // i_conv_i_i_i_i_i_24_c_compstr710_sel_x(BITSELECT,3756)@61
    assign i_conv_i_i_i_i_i_24_c_compstr710_sel_x_b = i_unnamed_c_compstr709_vt_join_q[15:0];

    // redist1109_i_conv_i_i_i_i_i_24_c_compstr710_sel_x_b_1(DELAY,29337)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1109_i_conv_i_i_i_i_i_24_c_compstr710_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_24_c_compstr710_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16476_dupName_98_i_unnamed_c_compstr0_shift_x(BITSELECT,16475)@61
    assign rightShiftStage1Idx1Rng8_uid16476_dupName_98_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16475_dupName_98_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16478_dupName_98_i_unnamed_c_compstr0_shift_x(BITJOIN,16477)@61
    assign rightShiftStage1Idx1_uid16478_dupName_98_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16476_dupName_98_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16471_dupName_98_i_unnamed_c_compstr0_shift_x(BITSELECT,16470)@61
    assign rightShiftStage0Idx1Rng4_uid16471_dupName_98_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_q[33:4];

    // rightShiftStage0Idx1_uid16473_dupName_98_i_unnamed_c_compstr0_shift_x(BITJOIN,16472)@61
    assign rightShiftStage0Idx1_uid16473_dupName_98_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16471_dupName_98_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16475_dupName_98_i_unnamed_c_compstr0_shift_x(MUX,16474)@61
    assign rightShiftStage0_uid16475_dupName_98_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16475_dupName_98_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_q or rightShiftStage0Idx1_uid16473_dupName_98_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16475_dupName_98_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16475_dupName_98_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compstr708_q;
            1'b1 : rightShiftStage0_uid16475_dupName_98_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16473_dupName_98_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16475_dupName_98_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16480_dupName_98_i_unnamed_c_compstr0_shift_x(MUX,16479)@61
    assign rightShiftStage1_uid16480_dupName_98_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16480_dupName_98_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16475_dupName_98_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16478_dupName_98_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16480_dupName_98_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16480_dupName_98_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16475_dupName_98_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16480_dupName_98_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16478_dupName_98_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16480_dupName_98_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr711_vt_select_21(BITSELECT,12371)@61
    assign i_unnamed_c_compstr711_vt_select_21_b = rightShiftStage1_uid16480_dupName_98_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr711_vt_join(BITJOIN,12370)@61
    assign i_unnamed_c_compstr711_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr711_vt_select_21_b};

    // i_unnamed_c_compstr712_sel_x(BITSELECT,6268)@61
    assign i_unnamed_c_compstr712_sel_x_b = i_unnamed_c_compstr711_vt_join_q[15:0];

    // i_unnamed_c_compstr713_BitSelect_for_a(BITSELECT,27925)@61
    assign i_unnamed_c_compstr713_BitSelect_for_a_b = i_unnamed_c_compstr712_sel_x_b[0:0];

    // i_unnamed_c_compstr713_join(BITJOIN,27926)@61
    assign i_unnamed_c_compstr713_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr713_BitSelect_for_a_b};

    // i_unnamed_c_compstr713_vt_select_0(BITSELECT,12376)@61
    assign i_unnamed_c_compstr713_vt_select_0_b = i_unnamed_c_compstr713_join_q[0:0];

    // redist24_i_unnamed_c_compstr713_vt_select_0_b_1(DELAY,28252)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist24_i_unnamed_c_compstr713_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr713_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr713_vt_join(BITJOIN,12375)@62
    assign i_unnamed_c_compstr713_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist24_i_unnamed_c_compstr713_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_24_c_compstr714(ADD,7023)@62
    assign i_add_i_i_i_i_i_i_24_c_compstr714_a = {1'b0, i_unnamed_c_compstr713_vt_join_q};
    assign i_add_i_i_i_i_i_i_24_c_compstr714_b = {1'b0, redist1109_i_conv_i_i_i_i_i_24_c_compstr710_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_24_c_compstr714_o = $unsigned(i_add_i_i_i_i_i_i_24_c_compstr714_a) + $unsigned(i_add_i_i_i_i_i_i_24_c_compstr714_b);
    assign i_add_i_i_i_i_i_i_24_c_compstr714_q = i_add_i_i_i_i_i_i_24_c_compstr714_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_24_c_compstr714_sel_x(BITSELECT,2217)@62
    assign bgTrunc_i_add_i_i_i_i_i_i_24_c_compstr714_sel_x_b = i_add_i_i_i_i_i_i_24_c_compstr714_q[15:0];

    // i_conv_i_i_i_i_i_i279_25_c_compstr734_sel_x(BITSELECT,3885)@62
    assign i_conv_i_i_i_i_i_i279_25_c_compstr734_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_24_c_compstr714_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_25_c_compstr734_vt_select_15(BITSELECT,8057)@62
    assign i_conv_i_i_i_i_i_i279_25_c_compstr734_vt_select_15_b = i_conv_i_i_i_i_i_i279_25_c_compstr734_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_25_c_compstr734_vt_join(BITJOIN,8056)@62
    assign i_conv_i_i_i_i_i_i279_25_c_compstr734_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_25_c_compstr734_vt_select_15_b};

    // leftShiftStage0_uid25952_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x(MUX,25951)@62
    assign leftShiftStage0_uid25952_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25952_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_25_c_compstr734_vt_join_q or leftShiftStage0Idx1_uid25950_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25952_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25952_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_25_c_compstr734_vt_join_q;
            1'b1 : leftShiftStage0_uid25952_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25950_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25952_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25957_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x(MUX,25956)@62
    assign leftShiftStage1_uid25957_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25957_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_s or leftShiftStage0_uid25952_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25955_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25957_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25957_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q = leftShiftStage0_uid25952_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25957_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25955_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25957_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25962_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x(MUX,25961)@62
    assign leftShiftStage2_uid25962_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25962_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_s or leftShiftStage1_uid25957_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25960_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25962_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25962_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q = leftShiftStage1_uid25957_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25962_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25960_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25962_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_25_c_compstr735_vt_select_28(BITSELECT,9556)@62
    assign i_shl_i_i_i_i_i_i_25_c_compstr735_vt_select_28_b = leftShiftStage2_uid25962_i_shl_i_i_i_i_i_i_25_c_compstr0_shift_x_q[28:13];

    // redist338_i_shl_i_i_i_i_i_i_25_c_compstr735_vt_select_28_b_1(DELAY,28566)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist338_i_shl_i_i_i_i_i_i_25_c_compstr735_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_25_c_compstr735_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_25_c_compstr735_vt_join(BITJOIN,9555)@63
    assign i_shl_i_i_i_i_i_i_25_c_compstr735_vt_join_q = {redist338_i_shl_i_i_i_i_i_i_25_c_compstr735_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_offset(CONSTANT,29866)
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_offset_q = $unsigned(4'b0101);

    // redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_rdcnt(ADD,31315)
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_a = {1'b0, redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_wraddr_q};
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_b = {1'b0, redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_o <= $unsigned(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_a) + $unsigned(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_b);
        end
    end
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_q = redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_o[4:0];

    // redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt(ADD,32967)
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_a = {1'b0, redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_q};
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_o <= $unsigned(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_a) + $unsigned(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_b);
        end
    end
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_q = redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_o[5:0];

    // redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_inputreg0(DELAY,32962)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl);
        end
    end

    // redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr(COUNTER,32965)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_i <= $unsigned(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_q = redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_i[4:0];

    // redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem(DUALMEM,32964)
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_ia = $unsigned(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_inputreg0_q);
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_aa = redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_q;
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_ab = redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_aa),
        .data_a(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_ab),
        .q_b(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_q = redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_iq[15:0];

    // redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_outputreg0(DELAY,32963)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_outputreg0_q <= $unsigned(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_q);
        end
    end

    // redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_inputreg0(DELAY,31310)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_inputreg0_q <= $unsigned(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_split_0_outputreg0_q);
        end
    end

    // redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_wraddr(COUNTER,31313)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_wraddr_i <= $unsigned(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_wraddr_q = redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_wraddr_i[3:0];

    // redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem(DUALMEM,31312)
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_ia = $unsigned(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_inputreg0_q);
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_aa = redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_wraddr_q;
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_ab = redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_aa),
        .data_a(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_ab),
        .q_b(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_q = redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_iq[15:0];

    // redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_outputreg0(DELAY,31311)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_outputreg0_q <= $unsigned(redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_mem_q);
        end
    end

    // redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_rdcnt(ADD,29867)
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_a = {1'b0, redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_wraddr_q};
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_b = {1'b0, redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_o <= $unsigned(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_a) + $unsigned(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_b);
        end
    end
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_q = redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_o[4:0];

    // redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt(ADD,32601)
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_a = {1'b0, redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_q};
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_o <= $unsigned(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_a) + $unsigned(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_b);
        end
    end
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_q = redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_o[5:0];

    // redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_inputreg0(DELAY,32596)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl);
        end
    end

    // redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr(COUNTER,32599)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_i <= $unsigned(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_q = redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_i[4:0];

    // redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem(DUALMEM,32598)
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_ia = $unsigned(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_inputreg0_q);
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_aa = redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_q;
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_ab = redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_aa),
        .data_a(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_ab),
        .q_b(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_q = redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_iq[15:0];

    // redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_outputreg0(DELAY,32597)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_outputreg0_q <= $unsigned(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_q);
        end
    end

    // redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_inputreg0(DELAY,29862)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_inputreg0_q <= $unsigned(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_split_0_outputreg0_q);
        end
    end

    // redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_wraddr(COUNTER,29865)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_wraddr_i <= $unsigned(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_wraddr_q = redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_wraddr_i[3:0];

    // redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem(DUALMEM,29864)
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_ia = $unsigned(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_inputreg0_q);
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_aa = redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_wraddr_q;
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_ab = redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_aa),
        .data_a(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_ab),
        .q_b(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_q = redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_iq[15:0];

    // redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_outputreg0(DELAY,29863)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_outputreg0_q <= $unsigned(redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_mem_q);
        end
    end

    // redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_rdcnt(ADD,29873)
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_a = {1'b0, redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_wraddr_q};
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_b = {1'b0, redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_o <= $unsigned(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_a) + $unsigned(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_b);
        end
    end
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_q = redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_o[4:0];

    // redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt(ADD,32607)
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_a = {1'b0, redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_q};
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_o <= $unsigned(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_a) + $unsigned(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_b);
        end
    end
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_q = redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_o[5:0];

    // redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_inputreg0(DELAY,32602)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl);
        end
    end

    // redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr(COUNTER,32605)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_i <= $unsigned(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_q = redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_i[4:0];

    // redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem(DUALMEM,32604)
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_ia = $unsigned(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_inputreg0_q);
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_aa = redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_wraddr_q;
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_ab = redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_aa),
        .data_a(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_ab),
        .q_b(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_q = redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_iq[15:0];

    // redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_outputreg0(DELAY,32603)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_outputreg0_q <= $unsigned(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_mem_q);
        end
    end

    // redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_inputreg0(DELAY,29868)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_inputreg0_q <= $unsigned(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_split_0_outputreg0_q);
        end
    end

    // redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_wraddr(COUNTER,29871)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_wraddr_i <= $unsigned(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_wraddr_q = redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_wraddr_i[3:0];

    // redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem(DUALMEM,29870)
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_ia = $unsigned(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_inputreg0_q);
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_aa = redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_wraddr_q;
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_ab = redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_aa),
        .data_a(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_ab),
        .q_b(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_q = redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_iq[15:0];

    // redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_outputreg0(DELAY,29869)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_outputreg0_q <= $unsigned(redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_mem_q);
        end
    end

    // redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_rdcnt(ADD,31309)
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_a = {1'b0, redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_wraddr_q};
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_b = {1'b0, redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_o <= $unsigned(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_a) + $unsigned(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_b);
        end
    end
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_q = redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_o[4:0];

    // redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt(ADD,32961)
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_a = {1'b0, redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_q};
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_o <= $unsigned(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_a) + $unsigned(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_b);
        end
    end
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_q = redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_o[5:0];

    // redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_inputreg0(DELAY,32956)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl);
        end
    end

    // redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr(COUNTER,32959)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_i <= $unsigned(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_q = redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_i[4:0];

    // redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem(DUALMEM,32958)
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_ia = $unsigned(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_inputreg0_q);
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_aa = redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_wraddr_q;
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_ab = redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_aa),
        .data_a(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_ab),
        .q_b(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_q = redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_iq[15:0];

    // redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_outputreg0(DELAY,32957)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_outputreg0_q <= $unsigned(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_mem_q);
        end
    end

    // redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_inputreg0(DELAY,31304)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_inputreg0_q <= $unsigned(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_split_0_outputreg0_q);
        end
    end

    // redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_wraddr(COUNTER,31307)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_wraddr_i <= $unsigned(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_wraddr_q = redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_wraddr_i[3:0];

    // redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem(DUALMEM,31306)
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_ia = $unsigned(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_inputreg0_q);
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_aa = redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_wraddr_q;
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_ab = redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_aa),
        .data_a(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_ab),
        .q_b(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_q = redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_iq[15:0];

    // redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_outputreg0(DELAY,31305)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_outputreg0_q <= $unsigned(redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27984)@57 + 5
    // out q@63
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736(ADD,8566)@63
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod166_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_b = $unsigned({{5{i_shl_i_i_i_i_i_i_25_c_compstr735_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_25_c_compstr735_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_o[33:0];

    // rightShiftStage0_uid16519_dupName_101_i_unnamed_c_compstr0_shift_x(MUX,16518)@63
    assign rightShiftStage0_uid16519_dupName_101_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16519_dupName_101_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_q or rightShiftStage0Idx1_uid16517_dupName_101_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16519_dupName_101_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16519_dupName_101_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_q;
            1'b1 : rightShiftStage0_uid16519_dupName_101_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16517_dupName_101_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16519_dupName_101_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16524_dupName_101_i_unnamed_c_compstr0_shift_x(MUX,16523)@63
    assign rightShiftStage1_uid16524_dupName_101_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16524_dupName_101_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16519_dupName_101_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16522_dupName_101_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16524_dupName_101_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16524_dupName_101_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16519_dupName_101_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16524_dupName_101_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16522_dupName_101_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16524_dupName_101_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16529_dupName_101_i_unnamed_c_compstr0_shift_x(MUX,16528)@63
    assign rightShiftStage2_uid16529_dupName_101_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16529_dupName_101_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16524_dupName_101_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16527_dupName_101_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16529_dupName_101_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16529_dupName_101_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16524_dupName_101_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16529_dupName_101_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16527_dupName_101_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16529_dupName_101_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr737_vt_select_20(BITSELECT,12390)@63
    assign i_unnamed_c_compstr737_vt_select_20_b = rightShiftStage2_uid16529_dupName_101_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr737_vt_join(BITJOIN,12389)@63
    assign i_unnamed_c_compstr737_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr737_vt_select_20_b};

    // i_conv_i_i_i_i_i_25_c_compstr738_sel_x(BITSELECT,3757)@63
    assign i_conv_i_i_i_i_i_25_c_compstr738_sel_x_b = i_unnamed_c_compstr737_vt_join_q[15:0];

    // redist1108_i_conv_i_i_i_i_i_25_c_compstr738_sel_x_b_1(DELAY,29336)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1108_i_conv_i_i_i_i_i_25_c_compstr738_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_25_c_compstr738_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16538_dupName_102_i_unnamed_c_compstr0_shift_x(BITSELECT,16537)@63
    assign rightShiftStage1Idx1Rng8_uid16538_dupName_102_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16537_dupName_102_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16540_dupName_102_i_unnamed_c_compstr0_shift_x(BITJOIN,16539)@63
    assign rightShiftStage1Idx1_uid16540_dupName_102_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16538_dupName_102_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16533_dupName_102_i_unnamed_c_compstr0_shift_x(BITSELECT,16532)@63
    assign rightShiftStage0Idx1Rng4_uid16533_dupName_102_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_q[33:4];

    // rightShiftStage0Idx1_uid16535_dupName_102_i_unnamed_c_compstr0_shift_x(BITJOIN,16534)@63
    assign rightShiftStage0Idx1_uid16535_dupName_102_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16533_dupName_102_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16537_dupName_102_i_unnamed_c_compstr0_shift_x(MUX,16536)@63
    assign rightShiftStage0_uid16537_dupName_102_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16537_dupName_102_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_q or rightShiftStage0Idx1_uid16535_dupName_102_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16537_dupName_102_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16537_dupName_102_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compstr736_q;
            1'b1 : rightShiftStage0_uid16537_dupName_102_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16535_dupName_102_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16537_dupName_102_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16542_dupName_102_i_unnamed_c_compstr0_shift_x(MUX,16541)@63
    assign rightShiftStage1_uid16542_dupName_102_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16542_dupName_102_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16537_dupName_102_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16540_dupName_102_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16542_dupName_102_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16542_dupName_102_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16537_dupName_102_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16542_dupName_102_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16540_dupName_102_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16542_dupName_102_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr739_vt_select_21(BITSELECT,12393)@63
    assign i_unnamed_c_compstr739_vt_select_21_b = rightShiftStage1_uid16542_dupName_102_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr739_vt_join(BITJOIN,12392)@63
    assign i_unnamed_c_compstr739_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr739_vt_select_21_b};

    // i_unnamed_c_compstr740_sel_x(BITSELECT,6270)@63
    assign i_unnamed_c_compstr740_sel_x_b = i_unnamed_c_compstr739_vt_join_q[15:0];

    // i_unnamed_c_compstr741_BitSelect_for_a(BITSELECT,27929)@63
    assign i_unnamed_c_compstr741_BitSelect_for_a_b = i_unnamed_c_compstr740_sel_x_b[0:0];

    // i_unnamed_c_compstr741_join(BITJOIN,27930)@63
    assign i_unnamed_c_compstr741_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr741_BitSelect_for_a_b};

    // i_unnamed_c_compstr741_vt_select_0(BITSELECT,12398)@63
    assign i_unnamed_c_compstr741_vt_select_0_b = i_unnamed_c_compstr741_join_q[0:0];

    // redist22_i_unnamed_c_compstr741_vt_select_0_b_1(DELAY,28250)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist22_i_unnamed_c_compstr741_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr741_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr741_vt_join(BITJOIN,12397)@64
    assign i_unnamed_c_compstr741_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist22_i_unnamed_c_compstr741_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_25_c_compstr742(ADD,7024)@64
    assign i_add_i_i_i_i_i_i_25_c_compstr742_a = {1'b0, i_unnamed_c_compstr741_vt_join_q};
    assign i_add_i_i_i_i_i_i_25_c_compstr742_b = {1'b0, redist1108_i_conv_i_i_i_i_i_25_c_compstr738_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_25_c_compstr742_o = $unsigned(i_add_i_i_i_i_i_i_25_c_compstr742_a) + $unsigned(i_add_i_i_i_i_i_i_25_c_compstr742_b);
    assign i_add_i_i_i_i_i_i_25_c_compstr742_q = i_add_i_i_i_i_i_i_25_c_compstr742_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_25_c_compstr742_sel_x(BITSELECT,2218)@64
    assign bgTrunc_i_add_i_i_i_i_i_i_25_c_compstr742_sel_x_b = i_add_i_i_i_i_i_i_25_c_compstr742_q[15:0];

    // i_conv_i_i_i_i_i_i279_26_c_compstr762_sel_x(BITSELECT,3886)@64
    assign i_conv_i_i_i_i_i_i279_26_c_compstr762_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_25_c_compstr742_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_26_c_compstr762_vt_select_15(BITSELECT,8061)@64
    assign i_conv_i_i_i_i_i_i279_26_c_compstr762_vt_select_15_b = i_conv_i_i_i_i_i_i279_26_c_compstr762_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_26_c_compstr762_vt_join(BITJOIN,8060)@64
    assign i_conv_i_i_i_i_i_i279_26_c_compstr762_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_26_c_compstr762_vt_select_15_b};

    // leftShiftStage0_uid25970_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x(MUX,25969)@64
    assign leftShiftStage0_uid25970_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25970_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_26_c_compstr762_vt_join_q or leftShiftStage0Idx1_uid25968_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25970_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25970_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_26_c_compstr762_vt_join_q;
            1'b1 : leftShiftStage0_uid25970_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25968_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25970_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25975_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x(MUX,25974)@64
    assign leftShiftStage1_uid25975_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25975_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_s or leftShiftStage0_uid25970_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25973_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25975_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25975_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q = leftShiftStage0_uid25970_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25975_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25973_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25975_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25980_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x(MUX,25979)@64
    assign leftShiftStage2_uid25980_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25980_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_s or leftShiftStage1_uid25975_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25978_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25980_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25980_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q = leftShiftStage1_uid25975_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25980_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25978_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25980_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_26_c_compstr763_vt_select_28(BITSELECT,9559)@64
    assign i_shl_i_i_i_i_i_i_26_c_compstr763_vt_select_28_b = leftShiftStage2_uid25980_i_shl_i_i_i_i_i_i_26_c_compstr0_shift_x_q[28:13];

    // redist337_i_shl_i_i_i_i_i_i_26_c_compstr763_vt_select_28_b_1(DELAY,28565)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist337_i_shl_i_i_i_i_i_i_26_c_compstr763_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_26_c_compstr763_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_26_c_compstr763_vt_join(BITJOIN,9558)@65
    assign i_shl_i_i_i_i_i_i_26_c_compstr763_vt_join_q = {redist337_i_shl_i_i_i_i_i_i_26_c_compstr763_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_offset(CONSTANT,29878)
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_offset_q = $unsigned(4'b0011);

    // redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_rdcnt(ADD,31327)
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_a = {1'b0, redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_wraddr_q};
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_b = {1'b0, redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_o <= $unsigned(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_a) + $unsigned(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_b);
        end
    end
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_q = redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_o[4:0];

    // redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt(ADD,32979)
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_a = {1'b0, redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_q};
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_o <= $unsigned(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_a) + $unsigned(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_b);
        end
    end
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_q = redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_o[5:0];

    // redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_inputreg0(DELAY,32974)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl);
        end
    end

    // redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr(COUNTER,32977)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_i <= $unsigned(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_q = redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_i[4:0];

    // redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem(DUALMEM,32976)
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_ia = $unsigned(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_inputreg0_q);
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_aa = redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_q;
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_ab = redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_aa),
        .data_a(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_ab),
        .q_b(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_q = redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_iq[15:0];

    // redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_outputreg0(DELAY,32975)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_outputreg0_q <= $unsigned(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_q);
        end
    end

    // redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_inputreg0(DELAY,31322)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_inputreg0_q <= $unsigned(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_split_0_outputreg0_q);
        end
    end

    // redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_wraddr(COUNTER,31325)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_wraddr_i <= $unsigned(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_wraddr_q = redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_wraddr_i[3:0];

    // redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem(DUALMEM,31324)
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_ia = $unsigned(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_inputreg0_q);
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_aa = redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_wraddr_q;
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_ab = redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_aa),
        .data_a(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_ab),
        .q_b(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_q = redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_iq[15:0];

    // redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_outputreg0(DELAY,31323)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_outputreg0_q <= $unsigned(redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_mem_q);
        end
    end

    // redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_rdcnt(ADD,29879)
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_a = {1'b0, redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_wraddr_q};
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_b = {1'b0, redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_o <= $unsigned(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_a) + $unsigned(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_b);
        end
    end
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_q = redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_o[4:0];

    // redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt(ADD,32613)
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_a = {1'b0, redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_q};
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_o <= $unsigned(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_a) + $unsigned(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_b);
        end
    end
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_q = redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_o[5:0];

    // redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_inputreg0(DELAY,32608)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl);
        end
    end

    // redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr(COUNTER,32611)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_i <= $unsigned(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_q = redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_i[4:0];

    // redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem(DUALMEM,32610)
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_ia = $unsigned(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_inputreg0_q);
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_aa = redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_q;
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_ab = redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_aa),
        .data_a(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_ab),
        .q_b(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_q = redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_iq[15:0];

    // redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_outputreg0(DELAY,32609)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_outputreg0_q <= $unsigned(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_q);
        end
    end

    // redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_inputreg0(DELAY,29874)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_inputreg0_q <= $unsigned(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_split_0_outputreg0_q);
        end
    end

    // redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_wraddr(COUNTER,29877)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_wraddr_i <= $unsigned(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_wraddr_q = redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_wraddr_i[3:0];

    // redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem(DUALMEM,29876)
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_ia = $unsigned(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_inputreg0_q);
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_aa = redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_wraddr_q;
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_ab = redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_aa),
        .data_a(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_ab),
        .q_b(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_q = redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_iq[15:0];

    // redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_outputreg0(DELAY,29875)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_outputreg0_q <= $unsigned(redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_mem_q);
        end
    end

    // redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_rdcnt(ADD,29885)
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_a = {1'b0, redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_wraddr_q};
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_b = {1'b0, redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_o <= $unsigned(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_a) + $unsigned(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_b);
        end
    end
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_q = redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_o[4:0];

    // redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt(ADD,32619)
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_a = {1'b0, redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_q};
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_o <= $unsigned(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_a) + $unsigned(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_b);
        end
    end
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_q = redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_o[5:0];

    // redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_inputreg0(DELAY,32614)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl);
        end
    end

    // redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr(COUNTER,32617)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_i <= $unsigned(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_q = redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_i[4:0];

    // redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem(DUALMEM,32616)
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_ia = $unsigned(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_inputreg0_q);
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_aa = redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_wraddr_q;
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_ab = redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_aa),
        .data_a(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_ab),
        .q_b(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_q = redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_iq[15:0];

    // redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_outputreg0(DELAY,32615)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_outputreg0_q <= $unsigned(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_mem_q);
        end
    end

    // redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_inputreg0(DELAY,29880)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_inputreg0_q <= $unsigned(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_split_0_outputreg0_q);
        end
    end

    // redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_wraddr(COUNTER,29883)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_wraddr_i <= $unsigned(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_wraddr_q = redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_wraddr_i[3:0];

    // redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem(DUALMEM,29882)
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_ia = $unsigned(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_inputreg0_q);
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_aa = redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_wraddr_q;
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_ab = redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_aa),
        .data_a(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_ab),
        .q_b(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_q = redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_iq[15:0];

    // redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_outputreg0(DELAY,29881)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_outputreg0_q <= $unsigned(redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_mem_q);
        end
    end

    // redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_rdcnt(ADD,31321)
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_a = {1'b0, redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_wraddr_q};
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_b = {1'b0, redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_o <= $unsigned(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_a) + $unsigned(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_b);
        end
    end
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_q = redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_o[4:0];

    // redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt(ADD,32973)
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_a = {1'b0, redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_q};
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_o <= $unsigned(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_a) + $unsigned(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_b);
        end
    end
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_q = redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_o[5:0];

    // redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_inputreg0(DELAY,32968)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl);
        end
    end

    // redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr(COUNTER,32971)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_i <= $unsigned(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_q = redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_i[4:0];

    // redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem(DUALMEM,32970)
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_ia = $unsigned(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_inputreg0_q);
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_aa = redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_wraddr_q;
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_ab = redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_aa),
        .data_a(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_ab),
        .q_b(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_q = redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_iq[15:0];

    // redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_outputreg0(DELAY,32969)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_outputreg0_q <= $unsigned(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_mem_q);
        end
    end

    // redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_inputreg0(DELAY,31316)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_inputreg0_q <= $unsigned(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_split_0_outputreg0_q);
        end
    end

    // redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_wraddr(COUNTER,31319)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_wraddr_i <= $unsigned(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_wraddr_q = redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_wraddr_i[3:0];

    // redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem(DUALMEM,31318)
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_ia = $unsigned(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_inputreg0_q);
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_aa = redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_wraddr_q;
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_ab = redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_aa),
        .data_a(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_ab),
        .q_b(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_q = redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_iq[15:0];

    // redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_outputreg0(DELAY,31317)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_outputreg0_q <= $unsigned(redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27985)@59 + 5
    // out q@65
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764(ADD,8567)@65
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod171_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_b = $unsigned({{5{i_shl_i_i_i_i_i_i_26_c_compstr763_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_26_c_compstr763_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_o[33:0];

    // rightShiftStage0_uid16581_dupName_105_i_unnamed_c_compstr0_shift_x(MUX,16580)@65
    assign rightShiftStage0_uid16581_dupName_105_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16581_dupName_105_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_q or rightShiftStage0Idx1_uid16579_dupName_105_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16581_dupName_105_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16581_dupName_105_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_q;
            1'b1 : rightShiftStage0_uid16581_dupName_105_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16579_dupName_105_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16581_dupName_105_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16586_dupName_105_i_unnamed_c_compstr0_shift_x(MUX,16585)@65
    assign rightShiftStage1_uid16586_dupName_105_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16586_dupName_105_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16581_dupName_105_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16584_dupName_105_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16586_dupName_105_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16586_dupName_105_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16581_dupName_105_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16586_dupName_105_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16584_dupName_105_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16586_dupName_105_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16591_dupName_105_i_unnamed_c_compstr0_shift_x(MUX,16590)@65
    assign rightShiftStage2_uid16591_dupName_105_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16591_dupName_105_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16586_dupName_105_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16589_dupName_105_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16591_dupName_105_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16591_dupName_105_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16586_dupName_105_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16591_dupName_105_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16589_dupName_105_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16591_dupName_105_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr765_vt_select_20(BITSELECT,12412)@65
    assign i_unnamed_c_compstr765_vt_select_20_b = rightShiftStage2_uid16591_dupName_105_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr765_vt_join(BITJOIN,12411)@65
    assign i_unnamed_c_compstr765_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr765_vt_select_20_b};

    // i_conv_i_i_i_i_i_26_c_compstr766_sel_x(BITSELECT,3758)@65
    assign i_conv_i_i_i_i_i_26_c_compstr766_sel_x_b = i_unnamed_c_compstr765_vt_join_q[15:0];

    // redist1107_i_conv_i_i_i_i_i_26_c_compstr766_sel_x_b_1(DELAY,29335)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1107_i_conv_i_i_i_i_i_26_c_compstr766_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_26_c_compstr766_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16600_dupName_106_i_unnamed_c_compstr0_shift_x(BITSELECT,16599)@65
    assign rightShiftStage1Idx1Rng8_uid16600_dupName_106_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16599_dupName_106_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16602_dupName_106_i_unnamed_c_compstr0_shift_x(BITJOIN,16601)@65
    assign rightShiftStage1Idx1_uid16602_dupName_106_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16600_dupName_106_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16595_dupName_106_i_unnamed_c_compstr0_shift_x(BITSELECT,16594)@65
    assign rightShiftStage0Idx1Rng4_uid16595_dupName_106_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_q[33:4];

    // rightShiftStage0Idx1_uid16597_dupName_106_i_unnamed_c_compstr0_shift_x(BITJOIN,16596)@65
    assign rightShiftStage0Idx1_uid16597_dupName_106_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16595_dupName_106_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16599_dupName_106_i_unnamed_c_compstr0_shift_x(MUX,16598)@65
    assign rightShiftStage0_uid16599_dupName_106_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16599_dupName_106_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_q or rightShiftStage0Idx1_uid16597_dupName_106_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16599_dupName_106_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16599_dupName_106_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compstr764_q;
            1'b1 : rightShiftStage0_uid16599_dupName_106_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16597_dupName_106_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16599_dupName_106_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16604_dupName_106_i_unnamed_c_compstr0_shift_x(MUX,16603)@65
    assign rightShiftStage1_uid16604_dupName_106_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16604_dupName_106_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16599_dupName_106_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16602_dupName_106_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16604_dupName_106_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16604_dupName_106_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16599_dupName_106_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16604_dupName_106_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16602_dupName_106_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16604_dupName_106_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr767_vt_select_21(BITSELECT,12415)@65
    assign i_unnamed_c_compstr767_vt_select_21_b = rightShiftStage1_uid16604_dupName_106_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr767_vt_join(BITJOIN,12414)@65
    assign i_unnamed_c_compstr767_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr767_vt_select_21_b};

    // i_unnamed_c_compstr768_sel_x(BITSELECT,6272)@65
    assign i_unnamed_c_compstr768_sel_x_b = i_unnamed_c_compstr767_vt_join_q[15:0];

    // i_unnamed_c_compstr769_BitSelect_for_a(BITSELECT,27933)@65
    assign i_unnamed_c_compstr769_BitSelect_for_a_b = i_unnamed_c_compstr768_sel_x_b[0:0];

    // i_unnamed_c_compstr769_join(BITJOIN,27934)@65
    assign i_unnamed_c_compstr769_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr769_BitSelect_for_a_b};

    // i_unnamed_c_compstr769_vt_select_0(BITSELECT,12420)@65
    assign i_unnamed_c_compstr769_vt_select_0_b = i_unnamed_c_compstr769_join_q[0:0];

    // redist20_i_unnamed_c_compstr769_vt_select_0_b_1(DELAY,28248)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist20_i_unnamed_c_compstr769_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr769_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr769_vt_join(BITJOIN,12419)@66
    assign i_unnamed_c_compstr769_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist20_i_unnamed_c_compstr769_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_26_c_compstr770(ADD,7025)@66
    assign i_add_i_i_i_i_i_i_26_c_compstr770_a = {1'b0, i_unnamed_c_compstr769_vt_join_q};
    assign i_add_i_i_i_i_i_i_26_c_compstr770_b = {1'b0, redist1107_i_conv_i_i_i_i_i_26_c_compstr766_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_26_c_compstr770_o = $unsigned(i_add_i_i_i_i_i_i_26_c_compstr770_a) + $unsigned(i_add_i_i_i_i_i_i_26_c_compstr770_b);
    assign i_add_i_i_i_i_i_i_26_c_compstr770_q = i_add_i_i_i_i_i_i_26_c_compstr770_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_26_c_compstr770_sel_x(BITSELECT,2219)@66
    assign bgTrunc_i_add_i_i_i_i_i_i_26_c_compstr770_sel_x_b = i_add_i_i_i_i_i_i_26_c_compstr770_q[15:0];

    // i_conv_i_i_i_i_i_i279_27_c_compstr790_sel_x(BITSELECT,3887)@66
    assign i_conv_i_i_i_i_i_i279_27_c_compstr790_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_26_c_compstr770_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_27_c_compstr790_vt_select_15(BITSELECT,8065)@66
    assign i_conv_i_i_i_i_i_i279_27_c_compstr790_vt_select_15_b = i_conv_i_i_i_i_i_i279_27_c_compstr790_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_27_c_compstr790_vt_join(BITJOIN,8064)@66
    assign i_conv_i_i_i_i_i_i279_27_c_compstr790_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_27_c_compstr790_vt_select_15_b};

    // leftShiftStage0_uid25988_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x(MUX,25987)@66
    assign leftShiftStage0_uid25988_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25988_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_27_c_compstr790_vt_join_q or leftShiftStage0Idx1_uid25986_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25988_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25988_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_27_c_compstr790_vt_join_q;
            1'b1 : leftShiftStage0_uid25988_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25986_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25988_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25993_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x(MUX,25992)@66
    assign leftShiftStage1_uid25993_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25993_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_s or leftShiftStage0_uid25988_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25991_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25993_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25993_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q = leftShiftStage0_uid25988_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25993_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25991_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25993_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25998_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x(MUX,25997)@66
    assign leftShiftStage2_uid25998_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25998_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_s or leftShiftStage1_uid25993_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25996_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25998_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25998_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q = leftShiftStage1_uid25993_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25998_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25996_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25998_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_27_c_compstr791_vt_select_28(BITSELECT,9562)@66
    assign i_shl_i_i_i_i_i_i_27_c_compstr791_vt_select_28_b = leftShiftStage2_uid25998_i_shl_i_i_i_i_i_i_27_c_compstr0_shift_x_q[28:13];

    // redist336_i_shl_i_i_i_i_i_i_27_c_compstr791_vt_select_28_b_1(DELAY,28564)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist336_i_shl_i_i_i_i_i_i_27_c_compstr791_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_27_c_compstr791_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_27_c_compstr791_vt_join(BITJOIN,9561)@67
    assign i_shl_i_i_i_i_i_i_27_c_compstr791_vt_join_q = {redist336_i_shl_i_i_i_i_i_i_27_c_compstr791_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_offset(CONSTANT,29890)
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_offset_q = $unsigned(5'b10001);

    // redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_rdcnt(ADD,31339)
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_a = {1'b0, redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_wraddr_q};
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_b = {1'b0, redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_o <= $unsigned(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_a) + $unsigned(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_b);
        end
    end
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_q = redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_o[5:0];

    // redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt(ADD,32991)
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_a = {1'b0, redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_wraddr_q};
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_o <= $unsigned(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_a) + $unsigned(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_b);
        end
    end
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_q = redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_o[5:0];

    // redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_inputreg0(DELAY,32986)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl);
        end
    end

    // redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem(DUALMEM,32988)
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_ia = $unsigned(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_inputreg0_q);
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_aa = redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_wraddr_q;
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_ab = redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_aa),
        .data_a(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_ab),
        .q_b(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_q = redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_iq[15:0];

    // redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_outputreg0(DELAY,32987)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_outputreg0_q <= $unsigned(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_q);
        end
    end

    // redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_inputreg0(DELAY,31334)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_inputreg0_q <= $unsigned(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_split_0_outputreg0_q);
        end
    end

    // redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_wraddr(COUNTER,31337)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_wraddr_i <= $unsigned(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_wraddr_q = redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_wraddr_i[4:0];

    // redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem(DUALMEM,31336)
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_ia = $unsigned(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_inputreg0_q);
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_aa = redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_wraddr_q;
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_ab = redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_aa),
        .data_a(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_ab),
        .q_b(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_q = redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_iq[15:0];

    // redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_outputreg0(DELAY,31335)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_outputreg0_q <= $unsigned(redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_mem_q);
        end
    end

    // redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_rdcnt(ADD,29891)
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_a = {1'b0, redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_wraddr_q};
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_b = {1'b0, redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_o <= $unsigned(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_a) + $unsigned(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_b);
        end
    end
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_q = redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_o[5:0];

    // redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt(ADD,32625)
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_a = {1'b0, redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_wraddr_q};
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_o <= $unsigned(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_a) + $unsigned(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_b);
        end
    end
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_q = redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_o[5:0];

    // redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_inputreg0(DELAY,32620)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl);
        end
    end

    // redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem(DUALMEM,32622)
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_ia = $unsigned(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_inputreg0_q);
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_aa = redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_wraddr_q;
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_ab = redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_aa),
        .data_a(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_ab),
        .q_b(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_q = redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_iq[15:0];

    // redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_outputreg0(DELAY,32621)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_outputreg0_q <= $unsigned(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_q);
        end
    end

    // redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_inputreg0(DELAY,29886)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_inputreg0_q <= $unsigned(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_split_0_outputreg0_q);
        end
    end

    // redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_wraddr(COUNTER,29889)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_wraddr_i <= $unsigned(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_wraddr_q = redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_wraddr_i[4:0];

    // redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem(DUALMEM,29888)
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_ia = $unsigned(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_inputreg0_q);
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_aa = redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_wraddr_q;
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_ab = redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_aa),
        .data_a(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_ab),
        .q_b(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_q = redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_iq[15:0];

    // redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_outputreg0(DELAY,29887)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_outputreg0_q <= $unsigned(redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_mem_q);
        end
    end

    // redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_rdcnt(ADD,29897)
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_a = {1'b0, redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_wraddr_q};
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_b = {1'b0, redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_o <= $unsigned(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_a) + $unsigned(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_b);
        end
    end
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_q = redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_o[5:0];

    // redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt(ADD,32631)
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_a = {1'b0, redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_wraddr_q};
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_o <= $unsigned(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_a) + $unsigned(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_b);
        end
    end
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_q = redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_o[5:0];

    // redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_inputreg0(DELAY,32626)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl);
        end
    end

    // redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem(DUALMEM,32628)
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_ia = $unsigned(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_inputreg0_q);
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_aa = redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_wraddr_q;
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_ab = redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_aa),
        .data_a(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_ab),
        .q_b(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_q = redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_iq[15:0];

    // redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_outputreg0(DELAY,32627)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_outputreg0_q <= $unsigned(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_mem_q);
        end
    end

    // redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_inputreg0(DELAY,29892)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_inputreg0_q <= $unsigned(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_split_0_outputreg0_q);
        end
    end

    // redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_wraddr(COUNTER,29895)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_wraddr_i <= $unsigned(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_wraddr_q = redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_wraddr_i[4:0];

    // redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem(DUALMEM,29894)
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_ia = $unsigned(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_inputreg0_q);
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_aa = redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_wraddr_q;
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_ab = redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_aa),
        .data_a(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_ab),
        .q_b(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_q = redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_iq[15:0];

    // redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_outputreg0(DELAY,29893)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_outputreg0_q <= $unsigned(redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_mem_q);
        end
    end

    // redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_rdcnt(ADD,31333)
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_a = {1'b0, redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_wraddr_q};
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_b = {1'b0, redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_o <= $unsigned(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_a) + $unsigned(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_b);
        end
    end
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_q = redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_o[5:0];

    // redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt(ADD,32985)
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_a = {1'b0, redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_wraddr_q};
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_o <= $unsigned(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_a) + $unsigned(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_b);
        end
    end
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_q = redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_o[5:0];

    // redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_inputreg0(DELAY,32980)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl);
        end
    end

    // redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem(DUALMEM,32982)
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_ia = $unsigned(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_inputreg0_q);
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_aa = redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_wraddr_q;
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_ab = redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_aa),
        .data_a(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_ab),
        .q_b(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_q = redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_iq[15:0];

    // redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_outputreg0(DELAY,32981)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_outputreg0_q <= $unsigned(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_mem_q);
        end
    end

    // redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_inputreg0(DELAY,31328)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_inputreg0_q <= $unsigned(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_split_0_outputreg0_q);
        end
    end

    // redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_wraddr(COUNTER,31331)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_wraddr_i <= $unsigned(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_wraddr_q = redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_wraddr_i[4:0];

    // redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem(DUALMEM,31330)
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_ia = $unsigned(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_inputreg0_q);
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_aa = redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_wraddr_q;
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_ab = redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_aa),
        .data_a(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_ab),
        .q_b(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_q = redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_iq[15:0];

    // redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_outputreg0(DELAY,31329)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_outputreg0_q <= $unsigned(redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27986)@61 + 5
    // out q@67
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792(ADD,8568)@67
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod176_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_b = $unsigned({{5{i_shl_i_i_i_i_i_i_27_c_compstr791_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_27_c_compstr791_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_o[33:0];

    // rightShiftStage0_uid16643_dupName_109_i_unnamed_c_compstr0_shift_x(MUX,16642)@67
    assign rightShiftStage0_uid16643_dupName_109_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16643_dupName_109_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_q or rightShiftStage0Idx1_uid16641_dupName_109_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16643_dupName_109_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16643_dupName_109_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_q;
            1'b1 : rightShiftStage0_uid16643_dupName_109_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16641_dupName_109_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16643_dupName_109_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16648_dupName_109_i_unnamed_c_compstr0_shift_x(MUX,16647)@67
    assign rightShiftStage1_uid16648_dupName_109_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16648_dupName_109_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16643_dupName_109_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16646_dupName_109_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16648_dupName_109_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16648_dupName_109_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16643_dupName_109_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16648_dupName_109_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16646_dupName_109_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16648_dupName_109_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16653_dupName_109_i_unnamed_c_compstr0_shift_x(MUX,16652)@67
    assign rightShiftStage2_uid16653_dupName_109_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16653_dupName_109_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16648_dupName_109_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16651_dupName_109_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16653_dupName_109_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16653_dupName_109_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16648_dupName_109_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16653_dupName_109_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16651_dupName_109_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16653_dupName_109_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr793_vt_select_20(BITSELECT,12437)@67
    assign i_unnamed_c_compstr793_vt_select_20_b = rightShiftStage2_uid16653_dupName_109_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr793_vt_join(BITJOIN,12436)@67
    assign i_unnamed_c_compstr793_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr793_vt_select_20_b};

    // i_conv_i_i_i_i_i_27_c_compstr794_sel_x(BITSELECT,3759)@67
    assign i_conv_i_i_i_i_i_27_c_compstr794_sel_x_b = i_unnamed_c_compstr793_vt_join_q[15:0];

    // redist1106_i_conv_i_i_i_i_i_27_c_compstr794_sel_x_b_1(DELAY,29334)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1106_i_conv_i_i_i_i_i_27_c_compstr794_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_27_c_compstr794_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16662_dupName_110_i_unnamed_c_compstr0_shift_x(BITSELECT,16661)@67
    assign rightShiftStage1Idx1Rng8_uid16662_dupName_110_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16661_dupName_110_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16664_dupName_110_i_unnamed_c_compstr0_shift_x(BITJOIN,16663)@67
    assign rightShiftStage1Idx1_uid16664_dupName_110_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16662_dupName_110_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16657_dupName_110_i_unnamed_c_compstr0_shift_x(BITSELECT,16656)@67
    assign rightShiftStage0Idx1Rng4_uid16657_dupName_110_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_q[33:4];

    // rightShiftStage0Idx1_uid16659_dupName_110_i_unnamed_c_compstr0_shift_x(BITJOIN,16658)@67
    assign rightShiftStage0Idx1_uid16659_dupName_110_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16657_dupName_110_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16661_dupName_110_i_unnamed_c_compstr0_shift_x(MUX,16660)@67
    assign rightShiftStage0_uid16661_dupName_110_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16661_dupName_110_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_q or rightShiftStage0Idx1_uid16659_dupName_110_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16661_dupName_110_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16661_dupName_110_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compstr792_q;
            1'b1 : rightShiftStage0_uid16661_dupName_110_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16659_dupName_110_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16661_dupName_110_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16666_dupName_110_i_unnamed_c_compstr0_shift_x(MUX,16665)@67
    assign rightShiftStage1_uid16666_dupName_110_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16666_dupName_110_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16661_dupName_110_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16664_dupName_110_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16666_dupName_110_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16666_dupName_110_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16661_dupName_110_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16666_dupName_110_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16664_dupName_110_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16666_dupName_110_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr795_vt_select_21(BITSELECT,12440)@67
    assign i_unnamed_c_compstr795_vt_select_21_b = rightShiftStage1_uid16666_dupName_110_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr795_vt_join(BITJOIN,12439)@67
    assign i_unnamed_c_compstr795_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr795_vt_select_21_b};

    // i_unnamed_c_compstr796_sel_x(BITSELECT,6274)@67
    assign i_unnamed_c_compstr796_sel_x_b = i_unnamed_c_compstr795_vt_join_q[15:0];

    // i_unnamed_c_compstr797_BitSelect_for_a(BITSELECT,27937)@67
    assign i_unnamed_c_compstr797_BitSelect_for_a_b = i_unnamed_c_compstr796_sel_x_b[0:0];

    // i_unnamed_c_compstr797_join(BITJOIN,27938)@67
    assign i_unnamed_c_compstr797_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr797_BitSelect_for_a_b};

    // i_unnamed_c_compstr797_vt_select_0(BITSELECT,12445)@67
    assign i_unnamed_c_compstr797_vt_select_0_b = i_unnamed_c_compstr797_join_q[0:0];

    // redist18_i_unnamed_c_compstr797_vt_select_0_b_1(DELAY,28246)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist18_i_unnamed_c_compstr797_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr797_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr797_vt_join(BITJOIN,12444)@68
    assign i_unnamed_c_compstr797_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist18_i_unnamed_c_compstr797_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_27_c_compstr798(ADD,7026)@68
    assign i_add_i_i_i_i_i_i_27_c_compstr798_a = {1'b0, i_unnamed_c_compstr797_vt_join_q};
    assign i_add_i_i_i_i_i_i_27_c_compstr798_b = {1'b0, redist1106_i_conv_i_i_i_i_i_27_c_compstr794_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_27_c_compstr798_o = $unsigned(i_add_i_i_i_i_i_i_27_c_compstr798_a) + $unsigned(i_add_i_i_i_i_i_i_27_c_compstr798_b);
    assign i_add_i_i_i_i_i_i_27_c_compstr798_q = i_add_i_i_i_i_i_i_27_c_compstr798_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_27_c_compstr798_sel_x(BITSELECT,2220)@68
    assign bgTrunc_i_add_i_i_i_i_i_i_27_c_compstr798_sel_x_b = i_add_i_i_i_i_i_i_27_c_compstr798_q[15:0];

    // i_conv_i_i_i_i_i_i279_28_c_compstr818_sel_x(BITSELECT,3888)@68
    assign i_conv_i_i_i_i_i_i279_28_c_compstr818_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_27_c_compstr798_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_28_c_compstr818_vt_select_15(BITSELECT,8069)@68
    assign i_conv_i_i_i_i_i_i279_28_c_compstr818_vt_select_15_b = i_conv_i_i_i_i_i_i279_28_c_compstr818_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_28_c_compstr818_vt_join(BITJOIN,8068)@68
    assign i_conv_i_i_i_i_i_i279_28_c_compstr818_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_28_c_compstr818_vt_select_15_b};

    // leftShiftStage0_uid26006_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x(MUX,26005)@68
    assign leftShiftStage0_uid26006_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26006_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_28_c_compstr818_vt_join_q or leftShiftStage0Idx1_uid26004_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26006_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26006_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_28_c_compstr818_vt_join_q;
            1'b1 : leftShiftStage0_uid26006_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26004_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26006_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26011_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x(MUX,26010)@68
    assign leftShiftStage1_uid26011_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26011_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_s or leftShiftStage0_uid26006_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26009_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26011_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26011_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q = leftShiftStage0_uid26006_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26011_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26009_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26011_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26016_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x(MUX,26015)@68
    assign leftShiftStage2_uid26016_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26016_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_s or leftShiftStage1_uid26011_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26014_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26016_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26016_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q = leftShiftStage1_uid26011_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26016_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26014_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26016_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_28_c_compstr819_vt_select_28(BITSELECT,9565)@68
    assign i_shl_i_i_i_i_i_i_28_c_compstr819_vt_select_28_b = leftShiftStage2_uid26016_i_shl_i_i_i_i_i_i_28_c_compstr0_shift_x_q[28:13];

    // redist335_i_shl_i_i_i_i_i_i_28_c_compstr819_vt_select_28_b_1(DELAY,28563)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist335_i_shl_i_i_i_i_i_i_28_c_compstr819_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_28_c_compstr819_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_28_c_compstr819_vt_join(BITJOIN,9564)@69
    assign i_shl_i_i_i_i_i_i_28_c_compstr819_vt_join_q = {redist335_i_shl_i_i_i_i_i_i_28_c_compstr819_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_offset(CONSTANT,29902)
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_offset_q = $unsigned(5'b01111);

    // redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_rdcnt(ADD,31351)
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_a = {1'b0, redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_wraddr_q};
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_b = {1'b0, redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_o <= $unsigned(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_a) + $unsigned(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_b);
        end
    end
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_q = redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_o[5:0];

    // redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt(ADD,33003)
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_a = {1'b0, redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_wraddr_q};
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_o <= $unsigned(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_a) + $unsigned(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_b);
        end
    end
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_q = redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_o[5:0];

    // redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_inputreg0(DELAY,32998)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl);
        end
    end

    // redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem(DUALMEM,33000)
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_ia = $unsigned(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_inputreg0_q);
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_aa = redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_wraddr_q;
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_ab = redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_aa),
        .data_a(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_ab),
        .q_b(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_q = redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_iq[15:0];

    // redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_outputreg0(DELAY,32999)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_outputreg0_q <= $unsigned(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_q);
        end
    end

    // redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_inputreg0(DELAY,31346)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_inputreg0_q <= $unsigned(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_split_0_outputreg0_q);
        end
    end

    // redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_wraddr(COUNTER,31349)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_wraddr_i <= $unsigned(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_wraddr_q = redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_wraddr_i[4:0];

    // redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem(DUALMEM,31348)
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_ia = $unsigned(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_inputreg0_q);
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_aa = redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_wraddr_q;
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_ab = redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_aa),
        .data_a(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_ab),
        .q_b(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_q = redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_iq[15:0];

    // redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_outputreg0(DELAY,31347)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_outputreg0_q <= $unsigned(redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_mem_q);
        end
    end

    // redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_rdcnt(ADD,29903)
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_a = {1'b0, redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_wraddr_q};
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_b = {1'b0, redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_o <= $unsigned(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_a) + $unsigned(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_b);
        end
    end
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_q = redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_o[5:0];

    // redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt(ADD,32637)
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_a = {1'b0, redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_wraddr_q};
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_o <= $unsigned(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_a) + $unsigned(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_b);
        end
    end
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_q = redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_o[5:0];

    // redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_inputreg0(DELAY,32632)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl);
        end
    end

    // redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem(DUALMEM,32634)
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_ia = $unsigned(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_inputreg0_q);
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_aa = redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_wraddr_q;
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_ab = redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_aa),
        .data_a(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_ab),
        .q_b(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_q = redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_iq[15:0];

    // redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_outputreg0(DELAY,32633)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_outputreg0_q <= $unsigned(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_q);
        end
    end

    // redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_inputreg0(DELAY,29898)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_inputreg0_q <= $unsigned(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_split_0_outputreg0_q);
        end
    end

    // redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_wraddr(COUNTER,29901)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_wraddr_i <= $unsigned(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_wraddr_q = redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_wraddr_i[4:0];

    // redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem(DUALMEM,29900)
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_ia = $unsigned(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_inputreg0_q);
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_aa = redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_wraddr_q;
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_ab = redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_aa),
        .data_a(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_ab),
        .q_b(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_q = redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_iq[15:0];

    // redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_outputreg0(DELAY,29899)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_outputreg0_q <= $unsigned(redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_mem_q);
        end
    end

    // redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_rdcnt(ADD,29909)
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_a = {1'b0, redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_wraddr_q};
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_b = {1'b0, redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_o <= $unsigned(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_a) + $unsigned(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_b);
        end
    end
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_q = redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_o[5:0];

    // redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt(ADD,32643)
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_a = {1'b0, redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_wraddr_q};
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_o <= $unsigned(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_a) + $unsigned(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_b);
        end
    end
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_q = redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_o[5:0];

    // redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_inputreg0(DELAY,32638)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl);
        end
    end

    // redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem(DUALMEM,32640)
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_ia = $unsigned(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_inputreg0_q);
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_aa = redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_wraddr_q;
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_ab = redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_aa),
        .data_a(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_ab),
        .q_b(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_q = redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_iq[15:0];

    // redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_outputreg0(DELAY,32639)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_outputreg0_q <= $unsigned(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_mem_q);
        end
    end

    // redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_inputreg0(DELAY,29904)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_inputreg0_q <= $unsigned(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_split_0_outputreg0_q);
        end
    end

    // redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_wraddr(COUNTER,29907)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_wraddr_i <= $unsigned(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_wraddr_q = redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_wraddr_i[4:0];

    // redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem(DUALMEM,29906)
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_ia = $unsigned(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_inputreg0_q);
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_aa = redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_wraddr_q;
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_ab = redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_aa),
        .data_a(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_ab),
        .q_b(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_q = redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_iq[15:0];

    // redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_outputreg0(DELAY,29905)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_outputreg0_q <= $unsigned(redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_mem_q);
        end
    end

    // redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_rdcnt(ADD,31345)
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_a = {1'b0, redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_wraddr_q};
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_b = {1'b0, redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_o <= $unsigned(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_a) + $unsigned(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_b);
        end
    end
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_q = redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_o[5:0];

    // redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt(ADD,32997)
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_a = {1'b0, redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_wraddr_q};
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_o <= $unsigned(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_a) + $unsigned(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_b);
        end
    end
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_q = redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_o[5:0];

    // redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_inputreg0(DELAY,32992)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl);
        end
    end

    // redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem(DUALMEM,32994)
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_ia = $unsigned(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_inputreg0_q);
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_aa = redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_wraddr_q;
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_ab = redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_aa),
        .data_a(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_ab),
        .q_b(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_q = redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_iq[15:0];

    // redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_outputreg0(DELAY,32993)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_outputreg0_q <= $unsigned(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_mem_q);
        end
    end

    // redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_inputreg0(DELAY,31340)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_inputreg0_q <= $unsigned(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_split_0_outputreg0_q);
        end
    end

    // redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_wraddr(COUNTER,31343)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_wraddr_i <= $unsigned(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_wraddr_q = redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_wraddr_i[4:0];

    // redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem(DUALMEM,31342)
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_ia = $unsigned(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_inputreg0_q);
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_aa = redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_wraddr_q;
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_ab = redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_aa),
        .data_a(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_ab),
        .q_b(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_q = redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_iq[15:0];

    // redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_outputreg0(DELAY,31341)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_outputreg0_q <= $unsigned(redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27987)@63 + 5
    // out q@69
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820(ADD,8569)@69
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod181_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_b = $unsigned({{5{i_shl_i_i_i_i_i_i_28_c_compstr819_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_28_c_compstr819_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_o[33:0];

    // rightShiftStage0_uid16705_dupName_113_i_unnamed_c_compstr0_shift_x(MUX,16704)@69
    assign rightShiftStage0_uid16705_dupName_113_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16705_dupName_113_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_q or rightShiftStage0Idx1_uid16703_dupName_113_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16705_dupName_113_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16705_dupName_113_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_q;
            1'b1 : rightShiftStage0_uid16705_dupName_113_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16703_dupName_113_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16705_dupName_113_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16710_dupName_113_i_unnamed_c_compstr0_shift_x(MUX,16709)@69
    assign rightShiftStage1_uid16710_dupName_113_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16710_dupName_113_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16705_dupName_113_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16708_dupName_113_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16710_dupName_113_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16710_dupName_113_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16705_dupName_113_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16710_dupName_113_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16708_dupName_113_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16710_dupName_113_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16715_dupName_113_i_unnamed_c_compstr0_shift_x(MUX,16714)@69
    assign rightShiftStage2_uid16715_dupName_113_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16715_dupName_113_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16710_dupName_113_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16713_dupName_113_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16715_dupName_113_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16715_dupName_113_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16710_dupName_113_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16715_dupName_113_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16713_dupName_113_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16715_dupName_113_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr821_vt_select_20(BITSELECT,12467)@69
    assign i_unnamed_c_compstr821_vt_select_20_b = rightShiftStage2_uid16715_dupName_113_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr821_vt_join(BITJOIN,12466)@69
    assign i_unnamed_c_compstr821_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr821_vt_select_20_b};

    // i_conv_i_i_i_i_i_28_c_compstr822_sel_x(BITSELECT,3760)@69
    assign i_conv_i_i_i_i_i_28_c_compstr822_sel_x_b = i_unnamed_c_compstr821_vt_join_q[15:0];

    // redist1105_i_conv_i_i_i_i_i_28_c_compstr822_sel_x_b_1(DELAY,29333)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1105_i_conv_i_i_i_i_i_28_c_compstr822_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_28_c_compstr822_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16724_dupName_114_i_unnamed_c_compstr0_shift_x(BITSELECT,16723)@69
    assign rightShiftStage1Idx1Rng8_uid16724_dupName_114_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16723_dupName_114_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16726_dupName_114_i_unnamed_c_compstr0_shift_x(BITJOIN,16725)@69
    assign rightShiftStage1Idx1_uid16726_dupName_114_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16724_dupName_114_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16719_dupName_114_i_unnamed_c_compstr0_shift_x(BITSELECT,16718)@69
    assign rightShiftStage0Idx1Rng4_uid16719_dupName_114_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_q[33:4];

    // rightShiftStage0Idx1_uid16721_dupName_114_i_unnamed_c_compstr0_shift_x(BITJOIN,16720)@69
    assign rightShiftStage0Idx1_uid16721_dupName_114_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16719_dupName_114_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16723_dupName_114_i_unnamed_c_compstr0_shift_x(MUX,16722)@69
    assign rightShiftStage0_uid16723_dupName_114_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16723_dupName_114_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_q or rightShiftStage0Idx1_uid16721_dupName_114_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16723_dupName_114_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16723_dupName_114_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compstr820_q;
            1'b1 : rightShiftStage0_uid16723_dupName_114_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16721_dupName_114_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16723_dupName_114_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16728_dupName_114_i_unnamed_c_compstr0_shift_x(MUX,16727)@69
    assign rightShiftStage1_uid16728_dupName_114_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16728_dupName_114_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16723_dupName_114_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16726_dupName_114_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16728_dupName_114_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16728_dupName_114_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16723_dupName_114_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16728_dupName_114_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16726_dupName_114_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16728_dupName_114_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr823_vt_select_21(BITSELECT,12470)@69
    assign i_unnamed_c_compstr823_vt_select_21_b = rightShiftStage1_uid16728_dupName_114_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr823_vt_join(BITJOIN,12469)@69
    assign i_unnamed_c_compstr823_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr823_vt_select_21_b};

    // i_unnamed_c_compstr824_sel_x(BITSELECT,6277)@69
    assign i_unnamed_c_compstr824_sel_x_b = i_unnamed_c_compstr823_vt_join_q[15:0];

    // i_unnamed_c_compstr825_BitSelect_for_a(BITSELECT,27943)@69
    assign i_unnamed_c_compstr825_BitSelect_for_a_b = i_unnamed_c_compstr824_sel_x_b[0:0];

    // i_unnamed_c_compstr825_join(BITJOIN,27944)@69
    assign i_unnamed_c_compstr825_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr825_BitSelect_for_a_b};

    // i_unnamed_c_compstr825_vt_select_0(BITSELECT,12475)@69
    assign i_unnamed_c_compstr825_vt_select_0_b = i_unnamed_c_compstr825_join_q[0:0];

    // redist15_i_unnamed_c_compstr825_vt_select_0_b_1(DELAY,28243)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist15_i_unnamed_c_compstr825_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr825_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr825_vt_join(BITJOIN,12474)@70
    assign i_unnamed_c_compstr825_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist15_i_unnamed_c_compstr825_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_28_c_compstr826(ADD,7027)@70
    assign i_add_i_i_i_i_i_i_28_c_compstr826_a = {1'b0, i_unnamed_c_compstr825_vt_join_q};
    assign i_add_i_i_i_i_i_i_28_c_compstr826_b = {1'b0, redist1105_i_conv_i_i_i_i_i_28_c_compstr822_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_28_c_compstr826_o = $unsigned(i_add_i_i_i_i_i_i_28_c_compstr826_a) + $unsigned(i_add_i_i_i_i_i_i_28_c_compstr826_b);
    assign i_add_i_i_i_i_i_i_28_c_compstr826_q = i_add_i_i_i_i_i_i_28_c_compstr826_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_28_c_compstr826_sel_x(BITSELECT,2221)@70
    assign bgTrunc_i_add_i_i_i_i_i_i_28_c_compstr826_sel_x_b = i_add_i_i_i_i_i_i_28_c_compstr826_q[15:0];

    // i_conv_i_i_i_i_i_i279_29_c_compstr846_sel_x(BITSELECT,3889)@70
    assign i_conv_i_i_i_i_i_i279_29_c_compstr846_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_28_c_compstr826_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_29_c_compstr846_vt_select_15(BITSELECT,8073)@70
    assign i_conv_i_i_i_i_i_i279_29_c_compstr846_vt_select_15_b = i_conv_i_i_i_i_i_i279_29_c_compstr846_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_29_c_compstr846_vt_join(BITJOIN,8072)@70
    assign i_conv_i_i_i_i_i_i279_29_c_compstr846_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_29_c_compstr846_vt_select_15_b};

    // leftShiftStage0_uid26024_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x(MUX,26023)@70
    assign leftShiftStage0_uid26024_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26024_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_29_c_compstr846_vt_join_q or leftShiftStage0Idx1_uid26022_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26024_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26024_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_29_c_compstr846_vt_join_q;
            1'b1 : leftShiftStage0_uid26024_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26022_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26024_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26029_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x(MUX,26028)@70
    assign leftShiftStage1_uid26029_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26029_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_s or leftShiftStage0_uid26024_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26027_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26029_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26029_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q = leftShiftStage0_uid26024_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26029_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26027_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26029_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26034_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x(MUX,26033)@70
    assign leftShiftStage2_uid26034_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26034_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_s or leftShiftStage1_uid26029_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26032_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26034_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26034_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q = leftShiftStage1_uid26029_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26034_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26032_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26034_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_29_c_compstr847_vt_select_28(BITSELECT,9568)@70
    assign i_shl_i_i_i_i_i_i_29_c_compstr847_vt_select_28_b = leftShiftStage2_uid26034_i_shl_i_i_i_i_i_i_29_c_compstr0_shift_x_q[28:13];

    // redist334_i_shl_i_i_i_i_i_i_29_c_compstr847_vt_select_28_b_1(DELAY,28562)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist334_i_shl_i_i_i_i_i_i_29_c_compstr847_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_29_c_compstr847_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_29_c_compstr847_vt_join(BITJOIN,9567)@71
    assign i_shl_i_i_i_i_i_i_29_c_compstr847_vt_join_q = {redist334_i_shl_i_i_i_i_i_i_29_c_compstr847_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_offset(CONSTANT,29914)
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_offset_q = $unsigned(5'b01101);

    // redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_rdcnt(ADD,31363)
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_a = {1'b0, redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_wraddr_q};
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_b = {1'b0, redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_o <= $unsigned(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_a) + $unsigned(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_b);
        end
    end
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_q = redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_o[5:0];

    // redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt(ADD,33015)
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_a = {1'b0, redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_wraddr_q};
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_o <= $unsigned(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_a) + $unsigned(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_b);
        end
    end
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_q = redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_o[5:0];

    // redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_inputreg0(DELAY,33010)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl);
        end
    end

    // redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem(DUALMEM,33012)
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_ia = $unsigned(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_inputreg0_q);
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_aa = redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_wraddr_q;
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_ab = redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_aa),
        .data_a(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_ab),
        .q_b(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_q = redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_iq[15:0];

    // redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_outputreg0(DELAY,33011)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_outputreg0_q <= $unsigned(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_q);
        end
    end

    // redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_inputreg0(DELAY,31358)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_inputreg0_q <= $unsigned(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_split_0_outputreg0_q);
        end
    end

    // redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_wraddr(COUNTER,31361)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_wraddr_i <= $unsigned(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_wraddr_q = redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_wraddr_i[4:0];

    // redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem(DUALMEM,31360)
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_ia = $unsigned(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_inputreg0_q);
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_aa = redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_wraddr_q;
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_ab = redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_aa),
        .data_a(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_ab),
        .q_b(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_q = redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_iq[15:0];

    // redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_outputreg0(DELAY,31359)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_outputreg0_q <= $unsigned(redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_mem_q);
        end
    end

    // redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_rdcnt(ADD,29915)
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_a = {1'b0, redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_wraddr_q};
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_b = {1'b0, redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_o <= $unsigned(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_a) + $unsigned(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_b);
        end
    end
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_q = redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_o[5:0];

    // redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt(ADD,32649)
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_a = {1'b0, redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_wraddr_q};
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_o <= $unsigned(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_a) + $unsigned(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_b);
        end
    end
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_q = redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_o[5:0];

    // redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_inputreg0(DELAY,32644)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl);
        end
    end

    // redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem(DUALMEM,32646)
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_ia = $unsigned(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_inputreg0_q);
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_aa = redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_wraddr_q;
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_ab = redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_aa),
        .data_a(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_ab),
        .q_b(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_q = redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_iq[15:0];

    // redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_outputreg0(DELAY,32645)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_outputreg0_q <= $unsigned(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_q);
        end
    end

    // redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_inputreg0(DELAY,29910)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_inputreg0_q <= $unsigned(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_split_0_outputreg0_q);
        end
    end

    // redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_wraddr(COUNTER,29913)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_wraddr_i <= $unsigned(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_wraddr_q = redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_wraddr_i[4:0];

    // redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem(DUALMEM,29912)
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_ia = $unsigned(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_inputreg0_q);
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_aa = redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_wraddr_q;
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_ab = redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_aa),
        .data_a(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_ab),
        .q_b(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_q = redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_iq[15:0];

    // redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_outputreg0(DELAY,29911)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_outputreg0_q <= $unsigned(redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_mem_q);
        end
    end

    // redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_rdcnt(ADD,29921)
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_a = {1'b0, redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_wraddr_q};
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_b = {1'b0, redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_o <= $unsigned(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_a) + $unsigned(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_b);
        end
    end
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_q = redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_o[5:0];

    // redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt(ADD,32655)
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_a = {1'b0, redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_wraddr_q};
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_o <= $unsigned(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_a) + $unsigned(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_b);
        end
    end
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_q = redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_o[5:0];

    // redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_inputreg0(DELAY,32650)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl);
        end
    end

    // redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem(DUALMEM,32652)
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_ia = $unsigned(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_inputreg0_q);
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_aa = redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_wraddr_q;
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_ab = redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_aa),
        .data_a(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_ab),
        .q_b(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_q = redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_iq[15:0];

    // redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_outputreg0(DELAY,32651)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_outputreg0_q <= $unsigned(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_mem_q);
        end
    end

    // redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_inputreg0(DELAY,29916)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_inputreg0_q <= $unsigned(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_split_0_outputreg0_q);
        end
    end

    // redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_wraddr(COUNTER,29919)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_wraddr_i <= $unsigned(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_wraddr_q = redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_wraddr_i[4:0];

    // redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem(DUALMEM,29918)
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_ia = $unsigned(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_inputreg0_q);
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_aa = redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_wraddr_q;
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_ab = redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_aa),
        .data_a(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_ab),
        .q_b(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_q = redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_iq[15:0];

    // redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_outputreg0(DELAY,29917)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_outputreg0_q <= $unsigned(redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_mem_q);
        end
    end

    // redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_rdcnt(ADD,31357)
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_a = {1'b0, redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_wraddr_q};
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_b = {1'b0, redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_o <= $unsigned(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_a) + $unsigned(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_b);
        end
    end
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_q = redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_o[5:0];

    // redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt(ADD,33009)
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_a = {1'b0, redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_wraddr_q};
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_o <= $unsigned(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_a) + $unsigned(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_b);
        end
    end
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_q = redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_o[5:0];

    // redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_inputreg0(DELAY,33004)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl);
        end
    end

    // redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem(DUALMEM,33006)
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_ia = $unsigned(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_inputreg0_q);
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_aa = redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_wraddr_q;
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_ab = redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_aa),
        .data_a(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_ab),
        .q_b(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_q = redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_iq[15:0];

    // redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_outputreg0(DELAY,33005)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_outputreg0_q <= $unsigned(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_mem_q);
        end
    end

    // redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_inputreg0(DELAY,31352)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_inputreg0_q <= $unsigned(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_split_0_outputreg0_q);
        end
    end

    // redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_wraddr(COUNTER,31355)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_wraddr_i <= $unsigned(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_wraddr_q = redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_wraddr_i[4:0];

    // redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem(DUALMEM,31354)
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_ia = $unsigned(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_inputreg0_q);
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_aa = redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_wraddr_q;
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_ab = redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_aa),
        .data_a(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_ab),
        .q_b(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_q = redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_iq[15:0];

    // redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_outputreg0(DELAY,31353)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_outputreg0_q <= $unsigned(redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27988)@65 + 5
    // out q@71
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848(ADD,8570)@71
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod186_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_b = $unsigned({{5{i_shl_i_i_i_i_i_i_29_c_compstr847_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_29_c_compstr847_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_o[33:0];

    // rightShiftStage0_uid16767_dupName_117_i_unnamed_c_compstr0_shift_x(MUX,16766)@71
    assign rightShiftStage0_uid16767_dupName_117_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16767_dupName_117_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_q or rightShiftStage0Idx1_uid16765_dupName_117_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16767_dupName_117_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16767_dupName_117_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_q;
            1'b1 : rightShiftStage0_uid16767_dupName_117_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16765_dupName_117_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16767_dupName_117_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16772_dupName_117_i_unnamed_c_compstr0_shift_x(MUX,16771)@71
    assign rightShiftStage1_uid16772_dupName_117_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16772_dupName_117_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16767_dupName_117_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16770_dupName_117_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16772_dupName_117_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16772_dupName_117_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16767_dupName_117_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16772_dupName_117_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16770_dupName_117_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16772_dupName_117_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16777_dupName_117_i_unnamed_c_compstr0_shift_x(MUX,16776)@71
    assign rightShiftStage2_uid16777_dupName_117_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16777_dupName_117_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16772_dupName_117_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16775_dupName_117_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16777_dupName_117_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16777_dupName_117_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16772_dupName_117_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16777_dupName_117_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16775_dupName_117_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16777_dupName_117_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr849_vt_select_20(BITSELECT,12489)@71
    assign i_unnamed_c_compstr849_vt_select_20_b = rightShiftStage2_uid16777_dupName_117_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr849_vt_join(BITJOIN,12488)@71
    assign i_unnamed_c_compstr849_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr849_vt_select_20_b};

    // i_conv_i_i_i_i_i_29_c_compstr850_sel_x(BITSELECT,3761)@71
    assign i_conv_i_i_i_i_i_29_c_compstr850_sel_x_b = i_unnamed_c_compstr849_vt_join_q[15:0];

    // redist1104_i_conv_i_i_i_i_i_29_c_compstr850_sel_x_b_1(DELAY,29332)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1104_i_conv_i_i_i_i_i_29_c_compstr850_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_29_c_compstr850_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16786_dupName_118_i_unnamed_c_compstr0_shift_x(BITSELECT,16785)@71
    assign rightShiftStage1Idx1Rng8_uid16786_dupName_118_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16785_dupName_118_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16788_dupName_118_i_unnamed_c_compstr0_shift_x(BITJOIN,16787)@71
    assign rightShiftStage1Idx1_uid16788_dupName_118_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16786_dupName_118_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16781_dupName_118_i_unnamed_c_compstr0_shift_x(BITSELECT,16780)@71
    assign rightShiftStage0Idx1Rng4_uid16781_dupName_118_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_q[33:4];

    // rightShiftStage0Idx1_uid16783_dupName_118_i_unnamed_c_compstr0_shift_x(BITJOIN,16782)@71
    assign rightShiftStage0Idx1_uid16783_dupName_118_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16781_dupName_118_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16785_dupName_118_i_unnamed_c_compstr0_shift_x(MUX,16784)@71
    assign rightShiftStage0_uid16785_dupName_118_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16785_dupName_118_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_q or rightShiftStage0Idx1_uid16783_dupName_118_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16785_dupName_118_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16785_dupName_118_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compstr848_q;
            1'b1 : rightShiftStage0_uid16785_dupName_118_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16783_dupName_118_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16785_dupName_118_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16790_dupName_118_i_unnamed_c_compstr0_shift_x(MUX,16789)@71
    assign rightShiftStage1_uid16790_dupName_118_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16790_dupName_118_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16785_dupName_118_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16788_dupName_118_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16790_dupName_118_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16790_dupName_118_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16785_dupName_118_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16790_dupName_118_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16788_dupName_118_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16790_dupName_118_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr851_vt_select_21(BITSELECT,12492)@71
    assign i_unnamed_c_compstr851_vt_select_21_b = rightShiftStage1_uid16790_dupName_118_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr851_vt_join(BITJOIN,12491)@71
    assign i_unnamed_c_compstr851_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr851_vt_select_21_b};

    // i_unnamed_c_compstr852_sel_x(BITSELECT,6279)@71
    assign i_unnamed_c_compstr852_sel_x_b = i_unnamed_c_compstr851_vt_join_q[15:0];

    // i_unnamed_c_compstr853_BitSelect_for_a(BITSELECT,27947)@71
    assign i_unnamed_c_compstr853_BitSelect_for_a_b = i_unnamed_c_compstr852_sel_x_b[0:0];

    // i_unnamed_c_compstr853_join(BITJOIN,27948)@71
    assign i_unnamed_c_compstr853_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr853_BitSelect_for_a_b};

    // i_unnamed_c_compstr853_vt_select_0(BITSELECT,12497)@71
    assign i_unnamed_c_compstr853_vt_select_0_b = i_unnamed_c_compstr853_join_q[0:0];

    // redist13_i_unnamed_c_compstr853_vt_select_0_b_1(DELAY,28241)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist13_i_unnamed_c_compstr853_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr853_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr853_vt_join(BITJOIN,12496)@72
    assign i_unnamed_c_compstr853_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist13_i_unnamed_c_compstr853_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_29_c_compstr854(ADD,7028)@72
    assign i_add_i_i_i_i_i_i_29_c_compstr854_a = {1'b0, i_unnamed_c_compstr853_vt_join_q};
    assign i_add_i_i_i_i_i_i_29_c_compstr854_b = {1'b0, redist1104_i_conv_i_i_i_i_i_29_c_compstr850_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_29_c_compstr854_o = $unsigned(i_add_i_i_i_i_i_i_29_c_compstr854_a) + $unsigned(i_add_i_i_i_i_i_i_29_c_compstr854_b);
    assign i_add_i_i_i_i_i_i_29_c_compstr854_q = i_add_i_i_i_i_i_i_29_c_compstr854_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_29_c_compstr854_sel_x(BITSELECT,2222)@72
    assign bgTrunc_i_add_i_i_i_i_i_i_29_c_compstr854_sel_x_b = i_add_i_i_i_i_i_i_29_c_compstr854_q[15:0];

    // i_conv_i_i_i_i_i_i279_30_c_compstr874_sel_x(BITSELECT,3891)@72
    assign i_conv_i_i_i_i_i_i279_30_c_compstr874_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_29_c_compstr854_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_30_c_compstr874_vt_select_15(BITSELECT,8081)@72
    assign i_conv_i_i_i_i_i_i279_30_c_compstr874_vt_select_15_b = i_conv_i_i_i_i_i_i279_30_c_compstr874_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_30_c_compstr874_vt_join(BITJOIN,8080)@72
    assign i_conv_i_i_i_i_i_i279_30_c_compstr874_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_30_c_compstr874_vt_select_15_b};

    // leftShiftStage0_uid26060_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x(MUX,26059)@72
    assign leftShiftStage0_uid26060_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26060_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_30_c_compstr874_vt_join_q or leftShiftStage0Idx1_uid26058_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26060_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26060_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_30_c_compstr874_vt_join_q;
            1'b1 : leftShiftStage0_uid26060_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26058_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26060_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26065_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x(MUX,26064)@72
    assign leftShiftStage1_uid26065_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26065_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_s or leftShiftStage0_uid26060_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26063_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26065_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26065_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q = leftShiftStage0_uid26060_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26065_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26063_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26065_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26070_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x(MUX,26069)@72
    assign leftShiftStage2_uid26070_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26070_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_s or leftShiftStage1_uid26065_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26068_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26070_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26070_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q = leftShiftStage1_uid26065_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26070_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26068_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26070_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_30_c_compstr875_vt_select_28(BITSELECT,9574)@72
    assign i_shl_i_i_i_i_i_i_30_c_compstr875_vt_select_28_b = leftShiftStage2_uid26070_i_shl_i_i_i_i_i_i_30_c_compstr0_shift_x_q[28:13];

    // redist332_i_shl_i_i_i_i_i_i_30_c_compstr875_vt_select_28_b_1(DELAY,28560)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist332_i_shl_i_i_i_i_i_i_30_c_compstr875_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_30_c_compstr875_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_30_c_compstr875_vt_join(BITJOIN,9573)@73
    assign i_shl_i_i_i_i_i_i_30_c_compstr875_vt_join_q = {redist332_i_shl_i_i_i_i_i_i_30_c_compstr875_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_offset(CONSTANT,29926)
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_offset_q = $unsigned(5'b01011);

    // redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_rdcnt(ADD,31375)
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_a = {1'b0, redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_wraddr_q};
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_b = {1'b0, redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_o <= $unsigned(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_a) + $unsigned(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_b);
        end
    end
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_q = redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_o[5:0];

    // redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt(ADD,33027)
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_a = {1'b0, redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_wraddr_q};
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_o <= $unsigned(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_a) + $unsigned(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_b);
        end
    end
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_q = redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_o[5:0];

    // redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_inputreg0(DELAY,33022)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl);
        end
    end

    // redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem(DUALMEM,33024)
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_ia = $unsigned(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_inputreg0_q);
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_aa = redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_wraddr_q;
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_ab = redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_aa),
        .data_a(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_ab),
        .q_b(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_q = redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_iq[15:0];

    // redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_outputreg0(DELAY,33023)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_outputreg0_q <= $unsigned(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_q);
        end
    end

    // redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_inputreg0(DELAY,31370)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_inputreg0_q <= $unsigned(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_split_0_outputreg0_q);
        end
    end

    // redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_wraddr(COUNTER,31373)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_wraddr_i <= $unsigned(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_wraddr_q = redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_wraddr_i[4:0];

    // redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem(DUALMEM,31372)
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_ia = $unsigned(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_inputreg0_q);
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_aa = redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_wraddr_q;
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_ab = redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_aa),
        .data_a(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_ab),
        .q_b(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_q = redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_iq[15:0];

    // redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_outputreg0(DELAY,31371)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_outputreg0_q <= $unsigned(redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_mem_q);
        end
    end

    // redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_rdcnt(ADD,29927)
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_a = {1'b0, redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_wraddr_q};
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_b = {1'b0, redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_o <= $unsigned(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_a) + $unsigned(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_b);
        end
    end
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_q = redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_o[5:0];

    // redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt(ADD,32661)
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_a = {1'b0, redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_wraddr_q};
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_o <= $unsigned(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_a) + $unsigned(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_b);
        end
    end
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_q = redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_o[5:0];

    // redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_inputreg0(DELAY,32656)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl);
        end
    end

    // redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem(DUALMEM,32658)
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_ia = $unsigned(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_inputreg0_q);
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_aa = redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_wraddr_q;
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_ab = redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_aa),
        .data_a(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_ab),
        .q_b(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_q = redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_iq[15:0];

    // redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_outputreg0(DELAY,32657)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_outputreg0_q <= $unsigned(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_q);
        end
    end

    // redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_inputreg0(DELAY,29922)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_inputreg0_q <= $unsigned(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_split_0_outputreg0_q);
        end
    end

    // redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_wraddr(COUNTER,29925)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_wraddr_i <= $unsigned(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_wraddr_q = redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_wraddr_i[4:0];

    // redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem(DUALMEM,29924)
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_ia = $unsigned(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_inputreg0_q);
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_aa = redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_wraddr_q;
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_ab = redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_aa),
        .data_a(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_ab),
        .q_b(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_q = redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_iq[15:0];

    // redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_outputreg0(DELAY,29923)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_outputreg0_q <= $unsigned(redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_mem_q);
        end
    end

    // redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_rdcnt(ADD,29933)
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_a = {1'b0, redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_wraddr_q};
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_b = {1'b0, redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_o <= $unsigned(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_a) + $unsigned(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_b);
        end
    end
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_q = redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_o[5:0];

    // redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt(ADD,32667)
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_a = {1'b0, redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_wraddr_q};
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_o <= $unsigned(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_a) + $unsigned(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_b);
        end
    end
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_q = redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_o[5:0];

    // redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_inputreg0(DELAY,32662)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl);
        end
    end

    // redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem(DUALMEM,32664)
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_ia = $unsigned(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_inputreg0_q);
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_aa = redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_wraddr_q;
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_ab = redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_aa),
        .data_a(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_ab),
        .q_b(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_q = redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_iq[15:0];

    // redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_outputreg0(DELAY,32663)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_outputreg0_q <= $unsigned(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_mem_q);
        end
    end

    // redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_inputreg0(DELAY,29928)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_inputreg0_q <= $unsigned(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_split_0_outputreg0_q);
        end
    end

    // redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_wraddr(COUNTER,29931)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_wraddr_i <= $unsigned(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_wraddr_q = redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_wraddr_i[4:0];

    // redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem(DUALMEM,29930)
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_ia = $unsigned(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_inputreg0_q);
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_aa = redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_wraddr_q;
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_ab = redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_aa),
        .data_a(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_ab),
        .q_b(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_q = redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_iq[15:0];

    // redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_outputreg0(DELAY,29929)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_outputreg0_q <= $unsigned(redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_mem_q);
        end
    end

    // redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_rdcnt(ADD,31369)
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_a = {1'b0, redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_wraddr_q};
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_b = {1'b0, redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_o <= $unsigned(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_a) + $unsigned(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_b);
        end
    end
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_q = redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_o[5:0];

    // redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt(ADD,33021)
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_a = {1'b0, redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_wraddr_q};
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_o <= $unsigned(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_a) + $unsigned(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_b);
        end
    end
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_q = redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_o[5:0];

    // redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_inputreg0(DELAY,33016)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl);
        end
    end

    // redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem(DUALMEM,33018)
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_ia = $unsigned(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_inputreg0_q);
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_aa = redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_wraddr_q;
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_ab = redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_aa),
        .data_a(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_ab),
        .q_b(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_q = redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_iq[15:0];

    // redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_outputreg0(DELAY,33017)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_outputreg0_q <= $unsigned(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_mem_q);
        end
    end

    // redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_inputreg0(DELAY,31364)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_inputreg0_q <= $unsigned(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_split_0_outputreg0_q);
        end
    end

    // redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_wraddr(COUNTER,31367)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_wraddr_i <= $unsigned(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_wraddr_q = redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_wraddr_i[4:0];

    // redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem(DUALMEM,31366)
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_ia = $unsigned(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_inputreg0_q);
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_aa = redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_wraddr_q;
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_ab = redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_aa),
        .data_a(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_ab),
        .q_b(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_q = redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_iq[15:0];

    // redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_outputreg0(DELAY,31365)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_outputreg0_q <= $unsigned(redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27989)@67 + 5
    // out q@73
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876(ADD,8572)@73
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod191_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_b = $unsigned({{5{i_shl_i_i_i_i_i_i_30_c_compstr875_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_30_c_compstr875_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_o[33:0];

    // rightShiftStage0_uid16829_dupName_121_i_unnamed_c_compstr0_shift_x(MUX,16828)@73
    assign rightShiftStage0_uid16829_dupName_121_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16829_dupName_121_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_q or rightShiftStage0Idx1_uid16827_dupName_121_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16829_dupName_121_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16829_dupName_121_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_q;
            1'b1 : rightShiftStage0_uid16829_dupName_121_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16827_dupName_121_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16829_dupName_121_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16834_dupName_121_i_unnamed_c_compstr0_shift_x(MUX,16833)@73
    assign rightShiftStage1_uid16834_dupName_121_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16834_dupName_121_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16829_dupName_121_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16832_dupName_121_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16834_dupName_121_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16834_dupName_121_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16829_dupName_121_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16834_dupName_121_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16832_dupName_121_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16834_dupName_121_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16839_dupName_121_i_unnamed_c_compstr0_shift_x(MUX,16838)@73
    assign rightShiftStage2_uid16839_dupName_121_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16839_dupName_121_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16834_dupName_121_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16837_dupName_121_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16839_dupName_121_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16839_dupName_121_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16834_dupName_121_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16839_dupName_121_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16837_dupName_121_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16839_dupName_121_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr877_vt_select_20(BITSELECT,12511)@73
    assign i_unnamed_c_compstr877_vt_select_20_b = rightShiftStage2_uid16839_dupName_121_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr877_vt_join(BITJOIN,12510)@73
    assign i_unnamed_c_compstr877_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr877_vt_select_20_b};

    // i_conv_i_i_i_i_i_30_c_compstr878_sel_x(BITSELECT,3763)@73
    assign i_conv_i_i_i_i_i_30_c_compstr878_sel_x_b = i_unnamed_c_compstr877_vt_join_q[15:0];

    // redist1102_i_conv_i_i_i_i_i_30_c_compstr878_sel_x_b_1(DELAY,29330)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1102_i_conv_i_i_i_i_i_30_c_compstr878_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_30_c_compstr878_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16848_dupName_122_i_unnamed_c_compstr0_shift_x(BITSELECT,16847)@73
    assign rightShiftStage1Idx1Rng8_uid16848_dupName_122_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16847_dupName_122_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16850_dupName_122_i_unnamed_c_compstr0_shift_x(BITJOIN,16849)@73
    assign rightShiftStage1Idx1_uid16850_dupName_122_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16848_dupName_122_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16843_dupName_122_i_unnamed_c_compstr0_shift_x(BITSELECT,16842)@73
    assign rightShiftStage0Idx1Rng4_uid16843_dupName_122_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_q[33:4];

    // rightShiftStage0Idx1_uid16845_dupName_122_i_unnamed_c_compstr0_shift_x(BITJOIN,16844)@73
    assign rightShiftStage0Idx1_uid16845_dupName_122_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16843_dupName_122_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16847_dupName_122_i_unnamed_c_compstr0_shift_x(MUX,16846)@73
    assign rightShiftStage0_uid16847_dupName_122_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16847_dupName_122_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_q or rightShiftStage0Idx1_uid16845_dupName_122_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16847_dupName_122_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16847_dupName_122_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compstr876_q;
            1'b1 : rightShiftStage0_uid16847_dupName_122_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16845_dupName_122_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16847_dupName_122_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16852_dupName_122_i_unnamed_c_compstr0_shift_x(MUX,16851)@73
    assign rightShiftStage1_uid16852_dupName_122_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16852_dupName_122_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16847_dupName_122_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16850_dupName_122_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16852_dupName_122_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16852_dupName_122_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16847_dupName_122_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16852_dupName_122_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16850_dupName_122_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16852_dupName_122_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr879_vt_select_21(BITSELECT,12514)@73
    assign i_unnamed_c_compstr879_vt_select_21_b = rightShiftStage1_uid16852_dupName_122_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr879_vt_join(BITJOIN,12513)@73
    assign i_unnamed_c_compstr879_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr879_vt_select_21_b};

    // i_unnamed_c_compstr880_sel_x(BITSELECT,6281)@73
    assign i_unnamed_c_compstr880_sel_x_b = i_unnamed_c_compstr879_vt_join_q[15:0];

    // i_unnamed_c_compstr881_BitSelect_for_a(BITSELECT,27951)@73
    assign i_unnamed_c_compstr881_BitSelect_for_a_b = i_unnamed_c_compstr880_sel_x_b[0:0];

    // i_unnamed_c_compstr881_join(BITJOIN,27952)@73
    assign i_unnamed_c_compstr881_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr881_BitSelect_for_a_b};

    // i_unnamed_c_compstr881_vt_select_0(BITSELECT,12519)@73
    assign i_unnamed_c_compstr881_vt_select_0_b = i_unnamed_c_compstr881_join_q[0:0];

    // redist11_i_unnamed_c_compstr881_vt_select_0_b_1(DELAY,28239)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist11_i_unnamed_c_compstr881_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr881_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr881_vt_join(BITJOIN,12518)@74
    assign i_unnamed_c_compstr881_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist11_i_unnamed_c_compstr881_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_30_c_compstr882(ADD,7030)@74
    assign i_add_i_i_i_i_i_i_30_c_compstr882_a = {1'b0, i_unnamed_c_compstr881_vt_join_q};
    assign i_add_i_i_i_i_i_i_30_c_compstr882_b = {1'b0, redist1102_i_conv_i_i_i_i_i_30_c_compstr878_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_30_c_compstr882_o = $unsigned(i_add_i_i_i_i_i_i_30_c_compstr882_a) + $unsigned(i_add_i_i_i_i_i_i_30_c_compstr882_b);
    assign i_add_i_i_i_i_i_i_30_c_compstr882_q = i_add_i_i_i_i_i_i_30_c_compstr882_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_30_c_compstr882_sel_x(BITSELECT,2224)@74
    assign bgTrunc_i_add_i_i_i_i_i_i_30_c_compstr882_sel_x_b = i_add_i_i_i_i_i_i_30_c_compstr882_q[15:0];

    // i_conv_i_i_i_i_i_i279_31_c_compstr902_sel_x(BITSELECT,3892)@74
    assign i_conv_i_i_i_i_i_i279_31_c_compstr902_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_30_c_compstr882_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_31_c_compstr902_vt_select_15(BITSELECT,8085)@74
    assign i_conv_i_i_i_i_i_i279_31_c_compstr902_vt_select_15_b = i_conv_i_i_i_i_i_i279_31_c_compstr902_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_31_c_compstr902_vt_join(BITJOIN,8084)@74
    assign i_conv_i_i_i_i_i_i279_31_c_compstr902_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_31_c_compstr902_vt_select_15_b};

    // leftShiftStage0_uid26078_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x(MUX,26077)@74
    assign leftShiftStage0_uid26078_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26078_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_31_c_compstr902_vt_join_q or leftShiftStage0Idx1_uid26076_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26078_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26078_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_31_c_compstr902_vt_join_q;
            1'b1 : leftShiftStage0_uid26078_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26076_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26078_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26083_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x(MUX,26082)@74
    assign leftShiftStage1_uid26083_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26083_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_s or leftShiftStage0_uid26078_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26081_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26083_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26083_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q = leftShiftStage0_uid26078_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26083_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26081_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26083_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26088_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x(MUX,26087)@74
    assign leftShiftStage2_uid26088_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26088_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_s or leftShiftStage1_uid26083_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26086_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26088_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26088_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q = leftShiftStage1_uid26083_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26088_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26086_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26088_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_31_c_compstr903_vt_select_28(BITSELECT,9577)@74
    assign i_shl_i_i_i_i_i_i_31_c_compstr903_vt_select_28_b = leftShiftStage2_uid26088_i_shl_i_i_i_i_i_i_31_c_compstr0_shift_x_q[28:13];

    // redist331_i_shl_i_i_i_i_i_i_31_c_compstr903_vt_select_28_b_1(DELAY,28559)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist331_i_shl_i_i_i_i_i_i_31_c_compstr903_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_31_c_compstr903_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_31_c_compstr903_vt_join(BITJOIN,9576)@75
    assign i_shl_i_i_i_i_i_i_31_c_compstr903_vt_join_q = {redist331_i_shl_i_i_i_i_i_i_31_c_compstr903_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_offset(CONSTANT,29938)
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_offset_q = $unsigned(5'b01001);

    // redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_rdcnt(ADD,31387)
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_a = {1'b0, redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_wraddr_q};
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_b = {1'b0, redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_o <= $unsigned(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_a) + $unsigned(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_b);
        end
    end
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_q = redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_o[5:0];

    // redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt(ADD,33039)
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_a = {1'b0, redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_wraddr_q};
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_o <= $unsigned(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_a) + $unsigned(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_b);
        end
    end
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_q = redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_o[5:0];

    // redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_inputreg0(DELAY,33034)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl);
        end
    end

    // redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem(DUALMEM,33036)
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_ia = $unsigned(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_inputreg0_q);
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_aa = redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_wraddr_q;
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_ab = redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_aa),
        .data_a(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_ab),
        .q_b(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_q = redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_iq[15:0];

    // redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_outputreg0(DELAY,33035)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_outputreg0_q <= $unsigned(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_q);
        end
    end

    // redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_inputreg0(DELAY,31382)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_inputreg0_q <= $unsigned(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_split_0_outputreg0_q);
        end
    end

    // redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_wraddr(COUNTER,31385)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_wraddr_i <= $unsigned(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_wraddr_q = redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_wraddr_i[4:0];

    // redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem(DUALMEM,31384)
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_ia = $unsigned(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_inputreg0_q);
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_aa = redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_wraddr_q;
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_ab = redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_aa),
        .data_a(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_ab),
        .q_b(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_q = redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_iq[15:0];

    // redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_outputreg0(DELAY,31383)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_outputreg0_q <= $unsigned(redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_mem_q);
        end
    end

    // redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_rdcnt(ADD,29939)
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_a = {1'b0, redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_wraddr_q};
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_b = {1'b0, redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_o <= $unsigned(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_a) + $unsigned(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_b);
        end
    end
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_q = redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_o[5:0];

    // redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt(ADD,32673)
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_a = {1'b0, redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_wraddr_q};
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_o <= $unsigned(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_a) + $unsigned(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_b);
        end
    end
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_q = redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_o[5:0];

    // redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_inputreg0(DELAY,32668)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl);
        end
    end

    // redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem(DUALMEM,32670)
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_ia = $unsigned(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_inputreg0_q);
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_aa = redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_wraddr_q;
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_ab = redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_aa),
        .data_a(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_ab),
        .q_b(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_q = redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_iq[15:0];

    // redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_outputreg0(DELAY,32669)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_outputreg0_q <= $unsigned(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_q);
        end
    end

    // redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_inputreg0(DELAY,29934)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_inputreg0_q <= $unsigned(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_split_0_outputreg0_q);
        end
    end

    // redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_wraddr(COUNTER,29937)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_wraddr_i <= $unsigned(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_wraddr_q = redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_wraddr_i[4:0];

    // redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem(DUALMEM,29936)
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_ia = $unsigned(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_inputreg0_q);
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_aa = redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_wraddr_q;
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_ab = redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_aa),
        .data_a(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_ab),
        .q_b(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_q = redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_iq[15:0];

    // redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_outputreg0(DELAY,29935)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_outputreg0_q <= $unsigned(redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_mem_q);
        end
    end

    // redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_rdcnt(ADD,29945)
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_a = {1'b0, redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_wraddr_q};
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_b = {1'b0, redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_o <= $unsigned(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_a) + $unsigned(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_b);
        end
    end
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_q = redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_o[5:0];

    // redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt(ADD,32679)
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_a = {1'b0, redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_wraddr_q};
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_o <= $unsigned(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_a) + $unsigned(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_b);
        end
    end
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_q = redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_o[5:0];

    // redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_inputreg0(DELAY,32674)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl);
        end
    end

    // redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem(DUALMEM,32676)
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_ia = $unsigned(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_inputreg0_q);
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_aa = redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_wraddr_q;
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_ab = redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_aa),
        .data_a(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_ab),
        .q_b(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_q = redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_iq[15:0];

    // redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_outputreg0(DELAY,32675)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_outputreg0_q <= $unsigned(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_mem_q);
        end
    end

    // redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_inputreg0(DELAY,29940)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_inputreg0_q <= $unsigned(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_split_0_outputreg0_q);
        end
    end

    // redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_wraddr(COUNTER,29943)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_wraddr_i <= $unsigned(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_wraddr_q = redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_wraddr_i[4:0];

    // redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem(DUALMEM,29942)
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_ia = $unsigned(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_inputreg0_q);
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_aa = redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_wraddr_q;
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_ab = redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_aa),
        .data_a(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_ab),
        .q_b(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_q = redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_iq[15:0];

    // redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_outputreg0(DELAY,29941)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_outputreg0_q <= $unsigned(redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_mem_q);
        end
    end

    // redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_rdcnt(ADD,31381)
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_a = {1'b0, redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_wraddr_q};
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_b = {1'b0, redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_o <= $unsigned(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_a) + $unsigned(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_b);
        end
    end
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_q = redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_o[5:0];

    // redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt(ADD,33033)
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_a = {1'b0, redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_wraddr_q};
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_o <= $unsigned(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_a) + $unsigned(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_b);
        end
    end
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_q = redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_o[5:0];

    // redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_inputreg0(DELAY,33028)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl);
        end
    end

    // redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem(DUALMEM,33030)
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_ia = $unsigned(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_inputreg0_q);
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_aa = redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_wraddr_q;
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_ab = redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_aa),
        .data_a(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_ab),
        .q_b(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_q = redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_iq[15:0];

    // redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_outputreg0(DELAY,33029)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_outputreg0_q <= $unsigned(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_mem_q);
        end
    end

    // redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_inputreg0(DELAY,31376)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_inputreg0_q <= $unsigned(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_split_0_outputreg0_q);
        end
    end

    // redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_wraddr(COUNTER,31379)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_wraddr_i <= $unsigned(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_wraddr_q = redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_wraddr_i[4:0];

    // redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem(DUALMEM,31378)
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_ia = $unsigned(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_inputreg0_q);
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_aa = redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_wraddr_q;
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_ab = redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_aa),
        .data_a(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_ab),
        .q_b(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_q = redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_iq[15:0];

    // redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_outputreg0(DELAY,31377)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_outputreg0_q <= $unsigned(redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27990)@69 + 5
    // out q@75
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904(ADD,8573)@75
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod196_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_b = $unsigned({{5{i_shl_i_i_i_i_i_i_31_c_compstr903_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_31_c_compstr903_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_o[33:0];

    // rightShiftStage0_uid16891_dupName_125_i_unnamed_c_compstr0_shift_x(MUX,16890)@75
    assign rightShiftStage0_uid16891_dupName_125_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16891_dupName_125_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_q or rightShiftStage0Idx1_uid16889_dupName_125_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16891_dupName_125_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16891_dupName_125_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_q;
            1'b1 : rightShiftStage0_uid16891_dupName_125_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16889_dupName_125_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16891_dupName_125_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16896_dupName_125_i_unnamed_c_compstr0_shift_x(MUX,16895)@75
    assign rightShiftStage1_uid16896_dupName_125_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16896_dupName_125_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16891_dupName_125_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16894_dupName_125_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16896_dupName_125_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16896_dupName_125_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16891_dupName_125_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16896_dupName_125_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16894_dupName_125_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16896_dupName_125_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16901_dupName_125_i_unnamed_c_compstr0_shift_x(MUX,16900)@75
    assign rightShiftStage2_uid16901_dupName_125_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16901_dupName_125_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16896_dupName_125_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16899_dupName_125_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16901_dupName_125_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16901_dupName_125_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16896_dupName_125_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16901_dupName_125_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16899_dupName_125_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16901_dupName_125_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr905_vt_select_20(BITSELECT,12533)@75
    assign i_unnamed_c_compstr905_vt_select_20_b = rightShiftStage2_uid16901_dupName_125_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr905_vt_join(BITJOIN,12532)@75
    assign i_unnamed_c_compstr905_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr905_vt_select_20_b};

    // i_conv_i_i_i_i_i_31_c_compstr906_sel_x(BITSELECT,3764)@75
    assign i_conv_i_i_i_i_i_31_c_compstr906_sel_x_b = i_unnamed_c_compstr905_vt_join_q[15:0];

    // redist1101_i_conv_i_i_i_i_i_31_c_compstr906_sel_x_b_1(DELAY,29329)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1101_i_conv_i_i_i_i_i_31_c_compstr906_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_31_c_compstr906_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16910_dupName_126_i_unnamed_c_compstr0_shift_x(BITSELECT,16909)@75
    assign rightShiftStage1Idx1Rng8_uid16910_dupName_126_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16909_dupName_126_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16912_dupName_126_i_unnamed_c_compstr0_shift_x(BITJOIN,16911)@75
    assign rightShiftStage1Idx1_uid16912_dupName_126_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16910_dupName_126_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16905_dupName_126_i_unnamed_c_compstr0_shift_x(BITSELECT,16904)@75
    assign rightShiftStage0Idx1Rng4_uid16905_dupName_126_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_q[33:4];

    // rightShiftStage0Idx1_uid16907_dupName_126_i_unnamed_c_compstr0_shift_x(BITJOIN,16906)@75
    assign rightShiftStage0Idx1_uid16907_dupName_126_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16905_dupName_126_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16909_dupName_126_i_unnamed_c_compstr0_shift_x(MUX,16908)@75
    assign rightShiftStage0_uid16909_dupName_126_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16909_dupName_126_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_q or rightShiftStage0Idx1_uid16907_dupName_126_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16909_dupName_126_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16909_dupName_126_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compstr904_q;
            1'b1 : rightShiftStage0_uid16909_dupName_126_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16907_dupName_126_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16909_dupName_126_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16914_dupName_126_i_unnamed_c_compstr0_shift_x(MUX,16913)@75
    assign rightShiftStage1_uid16914_dupName_126_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16914_dupName_126_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16909_dupName_126_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16912_dupName_126_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16914_dupName_126_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16914_dupName_126_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16909_dupName_126_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16914_dupName_126_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16912_dupName_126_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16914_dupName_126_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr907_vt_select_21(BITSELECT,12536)@75
    assign i_unnamed_c_compstr907_vt_select_21_b = rightShiftStage1_uid16914_dupName_126_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr907_vt_join(BITJOIN,12535)@75
    assign i_unnamed_c_compstr907_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr907_vt_select_21_b};

    // i_unnamed_c_compstr908_sel_x(BITSELECT,6283)@75
    assign i_unnamed_c_compstr908_sel_x_b = i_unnamed_c_compstr907_vt_join_q[15:0];

    // i_unnamed_c_compstr909_BitSelect_for_a(BITSELECT,27955)@75
    assign i_unnamed_c_compstr909_BitSelect_for_a_b = i_unnamed_c_compstr908_sel_x_b[0:0];

    // i_unnamed_c_compstr909_join(BITJOIN,27956)@75
    assign i_unnamed_c_compstr909_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr909_BitSelect_for_a_b};

    // i_unnamed_c_compstr909_vt_select_0(BITSELECT,12541)@75
    assign i_unnamed_c_compstr909_vt_select_0_b = i_unnamed_c_compstr909_join_q[0:0];

    // redist9_i_unnamed_c_compstr909_vt_select_0_b_1(DELAY,28237)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist9_i_unnamed_c_compstr909_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr909_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr909_vt_join(BITJOIN,12540)@76
    assign i_unnamed_c_compstr909_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist9_i_unnamed_c_compstr909_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_31_c_compstr910(ADD,7031)@76
    assign i_add_i_i_i_i_i_i_31_c_compstr910_a = {1'b0, i_unnamed_c_compstr909_vt_join_q};
    assign i_add_i_i_i_i_i_i_31_c_compstr910_b = {1'b0, redist1101_i_conv_i_i_i_i_i_31_c_compstr906_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_31_c_compstr910_o = $unsigned(i_add_i_i_i_i_i_i_31_c_compstr910_a) + $unsigned(i_add_i_i_i_i_i_i_31_c_compstr910_b);
    assign i_add_i_i_i_i_i_i_31_c_compstr910_q = i_add_i_i_i_i_i_i_31_c_compstr910_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_31_c_compstr910_sel_x(BITSELECT,2225)@76
    assign bgTrunc_i_add_i_i_i_i_i_i_31_c_compstr910_sel_x_b = i_add_i_i_i_i_i_i_31_c_compstr910_q[15:0];

    // i_conv_i_i_i_i_i_i279_32_c_compstr930_sel_x(BITSELECT,3893)@76
    assign i_conv_i_i_i_i_i_i279_32_c_compstr930_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_31_c_compstr910_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_32_c_compstr930_vt_select_15(BITSELECT,8089)@76
    assign i_conv_i_i_i_i_i_i279_32_c_compstr930_vt_select_15_b = i_conv_i_i_i_i_i_i279_32_c_compstr930_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_32_c_compstr930_vt_join(BITJOIN,8088)@76
    assign i_conv_i_i_i_i_i_i279_32_c_compstr930_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_32_c_compstr930_vt_select_15_b};

    // leftShiftStage0_uid26096_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x(MUX,26095)@76
    assign leftShiftStage0_uid26096_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26096_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_32_c_compstr930_vt_join_q or leftShiftStage0Idx1_uid26094_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26096_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26096_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_32_c_compstr930_vt_join_q;
            1'b1 : leftShiftStage0_uid26096_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26094_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26096_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26101_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x(MUX,26100)@76
    assign leftShiftStage1_uid26101_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26101_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_s or leftShiftStage0_uid26096_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26099_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26101_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26101_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q = leftShiftStage0_uid26096_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26101_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26099_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26101_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26106_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x(MUX,26105)@76
    assign leftShiftStage2_uid26106_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26106_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_s or leftShiftStage1_uid26101_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26104_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26106_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26106_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q = leftShiftStage1_uid26101_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26106_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26104_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26106_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_32_c_compstr931_vt_select_28(BITSELECT,9580)@76
    assign i_shl_i_i_i_i_i_i_32_c_compstr931_vt_select_28_b = leftShiftStage2_uid26106_i_shl_i_i_i_i_i_i_32_c_compstr0_shift_x_q[28:13];

    // redist330_i_shl_i_i_i_i_i_i_32_c_compstr931_vt_select_28_b_1(DELAY,28558)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist330_i_shl_i_i_i_i_i_i_32_c_compstr931_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_32_c_compstr931_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_32_c_compstr931_vt_join(BITJOIN,9579)@77
    assign i_shl_i_i_i_i_i_i_32_c_compstr931_vt_join_q = {redist330_i_shl_i_i_i_i_i_i_32_c_compstr931_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_offset(CONSTANT,29950)
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_offset_q = $unsigned(5'b00111);

    // redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_rdcnt(ADD,31399)
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_a = {1'b0, redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_wraddr_q};
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_b = {1'b0, redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_o <= $unsigned(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_a) + $unsigned(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_b);
        end
    end
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_q = redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_o[5:0];

    // redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt(ADD,33051)
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_a = {1'b0, redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_wraddr_q};
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_o <= $unsigned(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_a) + $unsigned(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_b);
        end
    end
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_q = redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_o[5:0];

    // redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_inputreg0(DELAY,33046)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl);
        end
    end

    // redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem(DUALMEM,33048)
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_ia = $unsigned(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_inputreg0_q);
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_aa = redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_wraddr_q;
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_ab = redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_aa),
        .data_a(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_ab),
        .q_b(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_q = redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_iq[15:0];

    // redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_outputreg0(DELAY,33047)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_outputreg0_q <= $unsigned(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_q);
        end
    end

    // redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_inputreg0(DELAY,31394)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_inputreg0_q <= $unsigned(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_split_0_outputreg0_q);
        end
    end

    // redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_wraddr(COUNTER,31397)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_wraddr_i <= $unsigned(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_wraddr_q = redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_wraddr_i[4:0];

    // redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem(DUALMEM,31396)
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_ia = $unsigned(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_inputreg0_q);
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_aa = redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_wraddr_q;
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_ab = redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_aa),
        .data_a(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_ab),
        .q_b(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_q = redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_iq[15:0];

    // redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_outputreg0(DELAY,31395)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_outputreg0_q <= $unsigned(redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_mem_q);
        end
    end

    // redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_rdcnt(ADD,29951)
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_a = {1'b0, redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_wraddr_q};
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_b = {1'b0, redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_o <= $unsigned(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_a) + $unsigned(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_b);
        end
    end
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_q = redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_o[5:0];

    // redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt(ADD,32685)
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_a = {1'b0, redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_wraddr_q};
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_o <= $unsigned(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_a) + $unsigned(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_b);
        end
    end
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_q = redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_o[5:0];

    // redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_inputreg0(DELAY,32680)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl);
        end
    end

    // redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem(DUALMEM,32682)
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_ia = $unsigned(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_inputreg0_q);
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_aa = redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_wraddr_q;
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_ab = redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_aa),
        .data_a(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_ab),
        .q_b(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_q = redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_iq[15:0];

    // redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_outputreg0(DELAY,32681)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_outputreg0_q <= $unsigned(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_q);
        end
    end

    // redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_inputreg0(DELAY,29946)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_inputreg0_q <= $unsigned(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_split_0_outputreg0_q);
        end
    end

    // redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_wraddr(COUNTER,29949)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_wraddr_i <= $unsigned(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_wraddr_q = redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_wraddr_i[4:0];

    // redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem(DUALMEM,29948)
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_ia = $unsigned(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_inputreg0_q);
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_aa = redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_wraddr_q;
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_ab = redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_aa),
        .data_a(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_ab),
        .q_b(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_q = redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_iq[15:0];

    // redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_outputreg0(DELAY,29947)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_outputreg0_q <= $unsigned(redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_mem_q);
        end
    end

    // redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_rdcnt(ADD,29957)
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_a = {1'b0, redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_wraddr_q};
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_b = {1'b0, redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_o <= $unsigned(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_a) + $unsigned(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_b);
        end
    end
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_q = redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_o[5:0];

    // redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt(ADD,32691)
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_a = {1'b0, redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_wraddr_q};
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_o <= $unsigned(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_a) + $unsigned(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_b);
        end
    end
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_q = redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_o[5:0];

    // redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_inputreg0(DELAY,32686)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl);
        end
    end

    // redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem(DUALMEM,32688)
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_ia = $unsigned(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_inputreg0_q);
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_aa = redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_wraddr_q;
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_ab = redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_aa),
        .data_a(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_ab),
        .q_b(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_q = redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_iq[15:0];

    // redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_outputreg0(DELAY,32687)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_outputreg0_q <= $unsigned(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_mem_q);
        end
    end

    // redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_inputreg0(DELAY,29952)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_inputreg0_q <= $unsigned(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_split_0_outputreg0_q);
        end
    end

    // redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_wraddr(COUNTER,29955)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_wraddr_i <= $unsigned(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_wraddr_q = redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_wraddr_i[4:0];

    // redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem(DUALMEM,29954)
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_ia = $unsigned(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_inputreg0_q);
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_aa = redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_wraddr_q;
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_ab = redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_aa),
        .data_a(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_ab),
        .q_b(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_q = redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_iq[15:0];

    // redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_outputreg0(DELAY,29953)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_outputreg0_q <= $unsigned(redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_mem_q);
        end
    end

    // redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_rdcnt(ADD,31393)
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_a = {1'b0, redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_wraddr_q};
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_b = {1'b0, redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_o <= $unsigned(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_a) + $unsigned(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_b);
        end
    end
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_q = redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_o[5:0];

    // redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt(ADD,33045)
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_a = {1'b0, redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_wraddr_q};
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_o <= $unsigned(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_a) + $unsigned(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_b);
        end
    end
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_q = redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_o[5:0];

    // redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_inputreg0(DELAY,33040)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl);
        end
    end

    // redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem(DUALMEM,33042)
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_ia = $unsigned(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_inputreg0_q);
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_aa = redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_wraddr_q;
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_ab = redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_aa),
        .data_a(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_ab),
        .q_b(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_q = redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_iq[15:0];

    // redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_outputreg0(DELAY,33041)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_outputreg0_q <= $unsigned(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_mem_q);
        end
    end

    // redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_inputreg0(DELAY,31388)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_inputreg0_q <= $unsigned(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_split_0_outputreg0_q);
        end
    end

    // redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_wraddr(COUNTER,31391)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_wraddr_i <= $unsigned(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_wraddr_q = redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_wraddr_i[4:0];

    // redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem(DUALMEM,31390)
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_ia = $unsigned(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_inputreg0_q);
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_aa = redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_wraddr_q;
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_ab = redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_aa),
        .data_a(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_ab),
        .q_b(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_q = redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_iq[15:0];

    // redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_outputreg0(DELAY,31389)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_outputreg0_q <= $unsigned(redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27991)@71 + 5
    // out q@77
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932(ADD,8574)@77
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod201_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_b = $unsigned({{5{i_shl_i_i_i_i_i_i_32_c_compstr931_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_32_c_compstr931_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_o[33:0];

    // rightShiftStage0_uid16953_dupName_129_i_unnamed_c_compstr0_shift_x(MUX,16952)@77
    assign rightShiftStage0_uid16953_dupName_129_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16953_dupName_129_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_q or rightShiftStage0Idx1_uid16951_dupName_129_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16953_dupName_129_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16953_dupName_129_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_q;
            1'b1 : rightShiftStage0_uid16953_dupName_129_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16951_dupName_129_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16953_dupName_129_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16958_dupName_129_i_unnamed_c_compstr0_shift_x(MUX,16957)@77
    assign rightShiftStage1_uid16958_dupName_129_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16958_dupName_129_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16953_dupName_129_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16956_dupName_129_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16958_dupName_129_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16958_dupName_129_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16953_dupName_129_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16958_dupName_129_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16956_dupName_129_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16958_dupName_129_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16963_dupName_129_i_unnamed_c_compstr0_shift_x(MUX,16962)@77
    assign rightShiftStage2_uid16963_dupName_129_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16963_dupName_129_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16958_dupName_129_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16961_dupName_129_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16963_dupName_129_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16963_dupName_129_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16958_dupName_129_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16963_dupName_129_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16961_dupName_129_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16963_dupName_129_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr933_vt_select_20(BITSELECT,12555)@77
    assign i_unnamed_c_compstr933_vt_select_20_b = rightShiftStage2_uid16963_dupName_129_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr933_vt_join(BITJOIN,12554)@77
    assign i_unnamed_c_compstr933_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr933_vt_select_20_b};

    // i_conv_i_i_i_i_i_32_c_compstr934_sel_x(BITSELECT,3765)@77
    assign i_conv_i_i_i_i_i_32_c_compstr934_sel_x_b = i_unnamed_c_compstr933_vt_join_q[15:0];

    // redist1100_i_conv_i_i_i_i_i_32_c_compstr934_sel_x_b_1(DELAY,29328)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1100_i_conv_i_i_i_i_i_32_c_compstr934_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_32_c_compstr934_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16972_dupName_130_i_unnamed_c_compstr0_shift_x(BITSELECT,16971)@77
    assign rightShiftStage1Idx1Rng8_uid16972_dupName_130_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16971_dupName_130_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16974_dupName_130_i_unnamed_c_compstr0_shift_x(BITJOIN,16973)@77
    assign rightShiftStage1Idx1_uid16974_dupName_130_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16972_dupName_130_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16967_dupName_130_i_unnamed_c_compstr0_shift_x(BITSELECT,16966)@77
    assign rightShiftStage0Idx1Rng4_uid16967_dupName_130_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_q[33:4];

    // rightShiftStage0Idx1_uid16969_dupName_130_i_unnamed_c_compstr0_shift_x(BITJOIN,16968)@77
    assign rightShiftStage0Idx1_uid16969_dupName_130_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16967_dupName_130_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16971_dupName_130_i_unnamed_c_compstr0_shift_x(MUX,16970)@77
    assign rightShiftStage0_uid16971_dupName_130_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16971_dupName_130_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_q or rightShiftStage0Idx1_uid16969_dupName_130_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16971_dupName_130_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16971_dupName_130_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compstr932_q;
            1'b1 : rightShiftStage0_uid16971_dupName_130_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16969_dupName_130_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16971_dupName_130_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16976_dupName_130_i_unnamed_c_compstr0_shift_x(MUX,16975)@77
    assign rightShiftStage1_uid16976_dupName_130_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16976_dupName_130_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16971_dupName_130_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16974_dupName_130_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16976_dupName_130_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16976_dupName_130_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16971_dupName_130_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16976_dupName_130_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16974_dupName_130_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16976_dupName_130_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr935_vt_select_21(BITSELECT,12558)@77
    assign i_unnamed_c_compstr935_vt_select_21_b = rightShiftStage1_uid16976_dupName_130_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr935_vt_join(BITJOIN,12557)@77
    assign i_unnamed_c_compstr935_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr935_vt_select_21_b};

    // i_unnamed_c_compstr936_sel_x(BITSELECT,6285)@77
    assign i_unnamed_c_compstr936_sel_x_b = i_unnamed_c_compstr935_vt_join_q[15:0];

    // i_unnamed_c_compstr937_BitSelect_for_a(BITSELECT,27959)@77
    assign i_unnamed_c_compstr937_BitSelect_for_a_b = i_unnamed_c_compstr936_sel_x_b[0:0];

    // i_unnamed_c_compstr937_join(BITJOIN,27960)@77
    assign i_unnamed_c_compstr937_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr937_BitSelect_for_a_b};

    // i_unnamed_c_compstr937_vt_select_0(BITSELECT,12563)@77
    assign i_unnamed_c_compstr937_vt_select_0_b = i_unnamed_c_compstr937_join_q[0:0];

    // redist7_i_unnamed_c_compstr937_vt_select_0_b_1(DELAY,28235)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist7_i_unnamed_c_compstr937_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr937_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr937_vt_join(BITJOIN,12562)@78
    assign i_unnamed_c_compstr937_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist7_i_unnamed_c_compstr937_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_32_c_compstr938(ADD,7032)@78
    assign i_add_i_i_i_i_i_i_32_c_compstr938_a = {1'b0, i_unnamed_c_compstr937_vt_join_q};
    assign i_add_i_i_i_i_i_i_32_c_compstr938_b = {1'b0, redist1100_i_conv_i_i_i_i_i_32_c_compstr934_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_32_c_compstr938_o = $unsigned(i_add_i_i_i_i_i_i_32_c_compstr938_a) + $unsigned(i_add_i_i_i_i_i_i_32_c_compstr938_b);
    assign i_add_i_i_i_i_i_i_32_c_compstr938_q = i_add_i_i_i_i_i_i_32_c_compstr938_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_32_c_compstr938_sel_x(BITSELECT,2226)@78
    assign bgTrunc_i_add_i_i_i_i_i_i_32_c_compstr938_sel_x_b = i_add_i_i_i_i_i_i_32_c_compstr938_q[15:0];

    // i_conv_i_i_i_i_i_i279_33_c_compstr958_sel_x(BITSELECT,3894)@78
    assign i_conv_i_i_i_i_i_i279_33_c_compstr958_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_32_c_compstr938_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_33_c_compstr958_vt_select_15(BITSELECT,8093)@78
    assign i_conv_i_i_i_i_i_i279_33_c_compstr958_vt_select_15_b = i_conv_i_i_i_i_i_i279_33_c_compstr958_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_33_c_compstr958_vt_join(BITJOIN,8092)@78
    assign i_conv_i_i_i_i_i_i279_33_c_compstr958_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_33_c_compstr958_vt_select_15_b};

    // leftShiftStage0_uid26114_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x(MUX,26113)@78
    assign leftShiftStage0_uid26114_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26114_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_33_c_compstr958_vt_join_q or leftShiftStage0Idx1_uid26112_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26114_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26114_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_33_c_compstr958_vt_join_q;
            1'b1 : leftShiftStage0_uid26114_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26112_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26114_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26119_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x(MUX,26118)@78
    assign leftShiftStage1_uid26119_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26119_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_s or leftShiftStage0_uid26114_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26117_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26119_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26119_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q = leftShiftStage0_uid26114_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26119_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26117_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26119_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26124_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x(MUX,26123)@78
    assign leftShiftStage2_uid26124_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26124_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_s or leftShiftStage1_uid26119_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26122_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26124_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26124_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q = leftShiftStage1_uid26119_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26124_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26122_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26124_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_33_c_compstr959_vt_select_28(BITSELECT,9583)@78
    assign i_shl_i_i_i_i_i_i_33_c_compstr959_vt_select_28_b = leftShiftStage2_uid26124_i_shl_i_i_i_i_i_i_33_c_compstr0_shift_x_q[28:13];

    // redist329_i_shl_i_i_i_i_i_i_33_c_compstr959_vt_select_28_b_1(DELAY,28557)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist329_i_shl_i_i_i_i_i_i_33_c_compstr959_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_33_c_compstr959_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_33_c_compstr959_vt_join(BITJOIN,9582)@79
    assign i_shl_i_i_i_i_i_i_33_c_compstr959_vt_join_q = {redist329_i_shl_i_i_i_i_i_i_33_c_compstr959_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_offset(CONSTANT,29962)
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_offset_q = $unsigned(5'b00101);

    // redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_rdcnt(ADD,31411)
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_a = {1'b0, redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_wraddr_q};
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_b = {1'b0, redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_o <= $unsigned(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_a) + $unsigned(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_b);
        end
    end
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_q = redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_o[5:0];

    // redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt(ADD,33063)
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_a = {1'b0, redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_wraddr_q};
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_o <= $unsigned(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_a) + $unsigned(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_b);
        end
    end
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_q = redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_o[5:0];

    // redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_inputreg0(DELAY,33058)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl);
        end
    end

    // redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem(DUALMEM,33060)
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_ia = $unsigned(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_inputreg0_q);
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_aa = redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_wraddr_q;
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_ab = redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_aa),
        .data_a(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_ab),
        .q_b(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_q = redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_iq[15:0];

    // redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_outputreg0(DELAY,33059)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_outputreg0_q <= $unsigned(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_q);
        end
    end

    // redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_inputreg0(DELAY,31406)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_inputreg0_q <= $unsigned(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_split_0_outputreg0_q);
        end
    end

    // redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_wraddr(COUNTER,31409)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_wraddr_i <= $unsigned(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_wraddr_q = redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_wraddr_i[4:0];

    // redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem(DUALMEM,31408)
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_ia = $unsigned(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_inputreg0_q);
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_aa = redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_wraddr_q;
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_ab = redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_aa),
        .data_a(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_ab),
        .q_b(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_q = redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_iq[15:0];

    // redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_outputreg0(DELAY,31407)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_outputreg0_q <= $unsigned(redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_mem_q);
        end
    end

    // redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_rdcnt(ADD,29963)
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_a = {1'b0, redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_wraddr_q};
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_b = {1'b0, redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_o <= $unsigned(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_a) + $unsigned(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_b);
        end
    end
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_q = redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_o[5:0];

    // redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt(ADD,32697)
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_a = {1'b0, redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_wraddr_q};
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_o <= $unsigned(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_a) + $unsigned(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_b);
        end
    end
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_q = redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_o[5:0];

    // redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_inputreg0(DELAY,32692)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl);
        end
    end

    // redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem(DUALMEM,32694)
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_ia = $unsigned(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_inputreg0_q);
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_aa = redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_wraddr_q;
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_ab = redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_aa),
        .data_a(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_ab),
        .q_b(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_q = redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_iq[15:0];

    // redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_outputreg0(DELAY,32693)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_outputreg0_q <= $unsigned(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_q);
        end
    end

    // redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_inputreg0(DELAY,29958)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_inputreg0_q <= $unsigned(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_split_0_outputreg0_q);
        end
    end

    // redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_wraddr(COUNTER,29961)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_wraddr_i <= $unsigned(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_wraddr_q = redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_wraddr_i[4:0];

    // redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem(DUALMEM,29960)
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_ia = $unsigned(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_inputreg0_q);
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_aa = redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_wraddr_q;
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_ab = redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_aa),
        .data_a(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_ab),
        .q_b(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_q = redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_iq[15:0];

    // redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_outputreg0(DELAY,29959)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_outputreg0_q <= $unsigned(redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_mem_q);
        end
    end

    // redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_rdcnt(ADD,29969)
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_a = {1'b0, redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_wraddr_q};
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_b = {1'b0, redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_o <= $unsigned(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_a) + $unsigned(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_b);
        end
    end
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_q = redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_o[5:0];

    // redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt(ADD,32703)
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_a = {1'b0, redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_wraddr_q};
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_o <= $unsigned(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_a) + $unsigned(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_b);
        end
    end
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_q = redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_o[5:0];

    // redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_inputreg0(DELAY,32698)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl);
        end
    end

    // redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem(DUALMEM,32700)
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_ia = $unsigned(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_inputreg0_q);
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_aa = redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_wraddr_q;
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_ab = redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_aa),
        .data_a(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_ab),
        .q_b(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_q = redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_iq[15:0];

    // redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_outputreg0(DELAY,32699)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_outputreg0_q <= $unsigned(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_mem_q);
        end
    end

    // redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_inputreg0(DELAY,29964)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_inputreg0_q <= $unsigned(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_split_0_outputreg0_q);
        end
    end

    // redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_wraddr(COUNTER,29967)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_wraddr_i <= $unsigned(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_wraddr_q = redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_wraddr_i[4:0];

    // redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem(DUALMEM,29966)
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_ia = $unsigned(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_inputreg0_q);
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_aa = redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_wraddr_q;
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_ab = redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_aa),
        .data_a(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_ab),
        .q_b(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_q = redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_iq[15:0];

    // redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_outputreg0(DELAY,29965)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_outputreg0_q <= $unsigned(redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_mem_q);
        end
    end

    // redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_rdcnt(ADD,31405)
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_a = {1'b0, redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_wraddr_q};
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_b = {1'b0, redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_o <= $unsigned(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_a) + $unsigned(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_b);
        end
    end
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_q = redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_o[5:0];

    // redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt(ADD,33057)
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_a = {1'b0, redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_wraddr_q};
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_o <= $unsigned(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_a) + $unsigned(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_b);
        end
    end
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_q = redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_o[5:0];

    // redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_inputreg0(DELAY,33052)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl);
        end
    end

    // redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem(DUALMEM,33054)
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_ia = $unsigned(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_inputreg0_q);
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_aa = redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_wraddr_q;
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_ab = redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_aa),
        .data_a(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_ab),
        .q_b(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_q = redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_iq[15:0];

    // redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_outputreg0(DELAY,33053)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_outputreg0_q <= $unsigned(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_mem_q);
        end
    end

    // redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_inputreg0(DELAY,31400)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_inputreg0_q <= $unsigned(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_split_0_outputreg0_q);
        end
    end

    // redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_wraddr(COUNTER,31403)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_wraddr_i <= $unsigned(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_wraddr_q = redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_wraddr_i[4:0];

    // redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem(DUALMEM,31402)
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_ia = $unsigned(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_inputreg0_q);
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_aa = redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_wraddr_q;
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_ab = redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_aa),
        .data_a(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_ab),
        .q_b(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_q = redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_iq[15:0];

    // redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_outputreg0(DELAY,31401)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_outputreg0_q <= $unsigned(redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27992)@73 + 5
    // out q@79
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960(ADD,8575)@79
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod206_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_b = $unsigned({{5{i_shl_i_i_i_i_i_i_33_c_compstr959_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_33_c_compstr959_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_o[33:0];

    // rightShiftStage0_uid17015_dupName_133_i_unnamed_c_compstr0_shift_x(MUX,17014)@79
    assign rightShiftStage0_uid17015_dupName_133_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17015_dupName_133_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_q or rightShiftStage0Idx1_uid17013_dupName_133_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17015_dupName_133_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17015_dupName_133_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_q;
            1'b1 : rightShiftStage0_uid17015_dupName_133_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17013_dupName_133_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17015_dupName_133_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17020_dupName_133_i_unnamed_c_compstr0_shift_x(MUX,17019)@79
    assign rightShiftStage1_uid17020_dupName_133_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17020_dupName_133_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17015_dupName_133_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17018_dupName_133_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17020_dupName_133_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17020_dupName_133_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17015_dupName_133_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17020_dupName_133_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17018_dupName_133_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17020_dupName_133_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17025_dupName_133_i_unnamed_c_compstr0_shift_x(MUX,17024)@79
    assign rightShiftStage2_uid17025_dupName_133_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17025_dupName_133_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17020_dupName_133_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17023_dupName_133_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17025_dupName_133_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17025_dupName_133_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17020_dupName_133_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17025_dupName_133_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17023_dupName_133_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17025_dupName_133_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr961_vt_select_20(BITSELECT,12583)@79
    assign i_unnamed_c_compstr961_vt_select_20_b = rightShiftStage2_uid17025_dupName_133_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr961_vt_join(BITJOIN,12582)@79
    assign i_unnamed_c_compstr961_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr961_vt_select_20_b};

    // i_conv_i_i_i_i_i_33_c_compstr962_sel_x(BITSELECT,3766)@79
    assign i_conv_i_i_i_i_i_33_c_compstr962_sel_x_b = i_unnamed_c_compstr961_vt_join_q[15:0];

    // redist1099_i_conv_i_i_i_i_i_33_c_compstr962_sel_x_b_1(DELAY,29327)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1099_i_conv_i_i_i_i_i_33_c_compstr962_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_33_c_compstr962_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17034_dupName_134_i_unnamed_c_compstr0_shift_x(BITSELECT,17033)@79
    assign rightShiftStage1Idx1Rng8_uid17034_dupName_134_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17033_dupName_134_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17036_dupName_134_i_unnamed_c_compstr0_shift_x(BITJOIN,17035)@79
    assign rightShiftStage1Idx1_uid17036_dupName_134_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17034_dupName_134_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17029_dupName_134_i_unnamed_c_compstr0_shift_x(BITSELECT,17028)@79
    assign rightShiftStage0Idx1Rng4_uid17029_dupName_134_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_q[33:4];

    // rightShiftStage0Idx1_uid17031_dupName_134_i_unnamed_c_compstr0_shift_x(BITJOIN,17030)@79
    assign rightShiftStage0Idx1_uid17031_dupName_134_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17029_dupName_134_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17033_dupName_134_i_unnamed_c_compstr0_shift_x(MUX,17032)@79
    assign rightShiftStage0_uid17033_dupName_134_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17033_dupName_134_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_q or rightShiftStage0Idx1_uid17031_dupName_134_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17033_dupName_134_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17033_dupName_134_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compstr960_q;
            1'b1 : rightShiftStage0_uid17033_dupName_134_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17031_dupName_134_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17033_dupName_134_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17038_dupName_134_i_unnamed_c_compstr0_shift_x(MUX,17037)@79
    assign rightShiftStage1_uid17038_dupName_134_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17038_dupName_134_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17033_dupName_134_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17036_dupName_134_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17038_dupName_134_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17038_dupName_134_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17033_dupName_134_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17038_dupName_134_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17036_dupName_134_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17038_dupName_134_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr963_vt_select_21(BITSELECT,12586)@79
    assign i_unnamed_c_compstr963_vt_select_21_b = rightShiftStage1_uid17038_dupName_134_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr963_vt_join(BITJOIN,12585)@79
    assign i_unnamed_c_compstr963_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr963_vt_select_21_b};

    // i_unnamed_c_compstr964_sel_x(BITSELECT,6288)@79
    assign i_unnamed_c_compstr964_sel_x_b = i_unnamed_c_compstr963_vt_join_q[15:0];

    // i_unnamed_c_compstr965_BitSelect_for_a(BITSELECT,27963)@79
    assign i_unnamed_c_compstr965_BitSelect_for_a_b = i_unnamed_c_compstr964_sel_x_b[0:0];

    // i_unnamed_c_compstr965_join(BITJOIN,27964)@79
    assign i_unnamed_c_compstr965_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr965_BitSelect_for_a_b};

    // i_unnamed_c_compstr965_vt_select_0(BITSELECT,12591)@79
    assign i_unnamed_c_compstr965_vt_select_0_b = i_unnamed_c_compstr965_join_q[0:0];

    // redist5_i_unnamed_c_compstr965_vt_select_0_b_1(DELAY,28233)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist5_i_unnamed_c_compstr965_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr965_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr965_vt_join(BITJOIN,12590)@80
    assign i_unnamed_c_compstr965_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist5_i_unnamed_c_compstr965_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_33_c_compstr966(ADD,7033)@80
    assign i_add_i_i_i_i_i_i_33_c_compstr966_a = {1'b0, i_unnamed_c_compstr965_vt_join_q};
    assign i_add_i_i_i_i_i_i_33_c_compstr966_b = {1'b0, redist1099_i_conv_i_i_i_i_i_33_c_compstr962_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_33_c_compstr966_o = $unsigned(i_add_i_i_i_i_i_i_33_c_compstr966_a) + $unsigned(i_add_i_i_i_i_i_i_33_c_compstr966_b);
    assign i_add_i_i_i_i_i_i_33_c_compstr966_q = i_add_i_i_i_i_i_i_33_c_compstr966_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_33_c_compstr966_sel_x(BITSELECT,2227)@80
    assign bgTrunc_i_add_i_i_i_i_i_i_33_c_compstr966_sel_x_b = i_add_i_i_i_i_i_i_33_c_compstr966_q[15:0];

    // i_conv_i_i_i_i_i_i279_34_c_compstr986_sel_x(BITSELECT,3895)@80
    assign i_conv_i_i_i_i_i_i279_34_c_compstr986_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_33_c_compstr966_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_34_c_compstr986_vt_select_15(BITSELECT,8097)@80
    assign i_conv_i_i_i_i_i_i279_34_c_compstr986_vt_select_15_b = i_conv_i_i_i_i_i_i279_34_c_compstr986_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_34_c_compstr986_vt_join(BITJOIN,8096)@80
    assign i_conv_i_i_i_i_i_i279_34_c_compstr986_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_34_c_compstr986_vt_select_15_b};

    // leftShiftStage0_uid26132_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x(MUX,26131)@80
    assign leftShiftStage0_uid26132_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26132_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_34_c_compstr986_vt_join_q or leftShiftStage0Idx1_uid26130_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26132_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26132_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_34_c_compstr986_vt_join_q;
            1'b1 : leftShiftStage0_uid26132_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26130_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26132_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26137_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x(MUX,26136)@80
    assign leftShiftStage1_uid26137_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26137_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_s or leftShiftStage0_uid26132_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26135_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26137_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26137_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q = leftShiftStage0_uid26132_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26137_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26135_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26137_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26142_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x(MUX,26141)@80
    assign leftShiftStage2_uid26142_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26142_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_s or leftShiftStage1_uid26137_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26140_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26142_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26142_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q = leftShiftStage1_uid26137_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26142_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26140_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26142_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_34_c_compstr987_vt_select_28(BITSELECT,9586)@80
    assign i_shl_i_i_i_i_i_i_34_c_compstr987_vt_select_28_b = leftShiftStage2_uid26142_i_shl_i_i_i_i_i_i_34_c_compstr0_shift_x_q[28:13];

    // redist328_i_shl_i_i_i_i_i_i_34_c_compstr987_vt_select_28_b_1(DELAY,28556)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist328_i_shl_i_i_i_i_i_i_34_c_compstr987_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_34_c_compstr987_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_34_c_compstr987_vt_join(BITJOIN,9585)@81
    assign i_shl_i_i_i_i_i_i_34_c_compstr987_vt_join_q = {redist328_i_shl_i_i_i_i_i_i_34_c_compstr987_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt(ADD,33081)
    assign redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_a = {1'b0, redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_q};
    assign redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_o <= $unsigned(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_a) + $unsigned(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_b);
        end
    end
    assign redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_q = redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_o[5:0];

    // redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_inputreg0(DELAY,33076)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl);
        end
    end

    // redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem(DUALMEM,33078)
    assign redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_ia = $unsigned(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_inputreg0_q);
    assign redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_aa = redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_q;
    assign redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_ab = redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_aa),
        .data_a(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_ab),
        .q_b(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_q = redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_iq[15:0];

    // redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_outputreg0(DELAY,33077)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_outputreg0_q <= $unsigned(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_q);
        end
    end

    // redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_inputreg0(DELAY,33082)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_inputreg0_q <= $unsigned(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_outputreg0_q);
        end
    end

    // redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr(COUNTER,33079)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_i <= $unsigned(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_q = redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_i[4:0];

    // redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem(DUALMEM,33084)
    assign redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_ia = $unsigned(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_inputreg0_q);
    assign redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_aa = redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_q;
    assign redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_ab = redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_aa),
        .data_a(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_ab),
        .q_b(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_q = redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_iq[15:0];

    // redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_outputreg0(DELAY,33083)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_outputreg0_q <= $unsigned(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_q);
        end
    end

    // redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67(DELAY,29067)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_q <= $unsigned(redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_split_1_outputreg0_q);
        end
    end

    // redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt(ADD,32709)
    assign redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_a = {1'b0, redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_q};
    assign redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_o <= $unsigned(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_a) + $unsigned(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_b);
        end
    end
    assign redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_q = redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_o[5:0];

    // redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_inputreg0(DELAY,32704)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl);
        end
    end

    // redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem(DUALMEM,32706)
    assign redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_ia = $unsigned(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_inputreg0_q);
    assign redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_aa = redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_q;
    assign redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_ab = redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_aa),
        .data_a(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_ab),
        .q_b(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_q = redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_iq[15:0];

    // redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_outputreg0(DELAY,32705)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_outputreg0_q <= $unsigned(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_q);
        end
    end

    // redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_inputreg0(DELAY,32710)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_inputreg0_q <= $unsigned(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_outputreg0_q);
        end
    end

    // redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr(COUNTER,32707)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_i <= $unsigned(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_q = redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_i[4:0];

    // redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem(DUALMEM,32712)
    assign redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_ia = $unsigned(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_inputreg0_q);
    assign redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_aa = redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_q;
    assign redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_ab = redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_aa),
        .data_a(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_ab),
        .q_b(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_q = redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_iq[15:0];

    // redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_outputreg0(DELAY,32711)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_outputreg0_q <= $unsigned(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_q);
        end
    end

    // redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67(DELAY,28812)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_q <= $unsigned(redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_split_1_outputreg0_q);
        end
    end

    // redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt(ADD,32721)
    assign redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_a = {1'b0, redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_q};
    assign redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_o <= $unsigned(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_a) + $unsigned(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_b);
        end
    end
    assign redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_q = redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_o[5:0];

    // redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_inputreg0(DELAY,32716)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl);
        end
    end

    // redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem(DUALMEM,32718)
    assign redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_ia = $unsigned(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_inputreg0_q);
    assign redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_aa = redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_q;
    assign redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_ab = redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_aa),
        .data_a(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_ab),
        .q_b(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_q = redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_iq[15:0];

    // redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_outputreg0(DELAY,32717)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_outputreg0_q <= $unsigned(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_mem_q);
        end
    end

    // redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_inputreg0(DELAY,32722)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_inputreg0_q <= $unsigned(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_outputreg0_q);
        end
    end

    // redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr(COUNTER,32719)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_i <= $unsigned(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_q = redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_i[4:0];

    // redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem(DUALMEM,32724)
    assign redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_ia = $unsigned(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_inputreg0_q);
    assign redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_aa = redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_wraddr_q;
    assign redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_ab = redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_aa),
        .data_a(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_ab),
        .q_b(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_q = redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_iq[15:0];

    // redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_outputreg0(DELAY,32723)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_outputreg0_q <= $unsigned(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_mem_q);
        end
    end

    // redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67(DELAY,28813)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_q <= $unsigned(redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_split_1_outputreg0_q);
        end
    end

    // redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt(ADD,33069)
    assign redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_a = {1'b0, redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_q};
    assign redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_o <= $unsigned(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_a) + $unsigned(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_b);
        end
    end
    assign redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_q = redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_o[5:0];

    // redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_inputreg0(DELAY,33064)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl);
        end
    end

    // redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem(DUALMEM,33066)
    assign redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_ia = $unsigned(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_inputreg0_q);
    assign redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_aa = redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_q;
    assign redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_ab = redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_aa),
        .data_a(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_ab),
        .q_b(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_q = redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_iq[15:0];

    // redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_outputreg0(DELAY,33065)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_outputreg0_q <= $unsigned(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_mem_q);
        end
    end

    // redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_inputreg0(DELAY,33070)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_inputreg0_q <= $unsigned(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_outputreg0_q);
        end
    end

    // redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr(COUNTER,33067)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_i <= $unsigned(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_q = redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_i[4:0];

    // redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem(DUALMEM,33072)
    assign redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_ia = $unsigned(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_inputreg0_q);
    assign redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_aa = redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_wraddr_q;
    assign redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_ab = redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_aa),
        .data_a(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_ab),
        .q_b(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_q = redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_iq[15:0];

    // redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_outputreg0(DELAY,33071)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_outputreg0_q <= $unsigned(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_mem_q);
        end
    end

    // redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67(DELAY,29066)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_q <= $unsigned(redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_split_1_outputreg0_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27993)@75 + 5
    // out q@81
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988(ADD,8576)@81
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod211_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_b = $unsigned({{5{i_shl_i_i_i_i_i_i_34_c_compstr987_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_34_c_compstr987_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_o[33:0];

    // rightShiftStage0_uid17077_dupName_137_i_unnamed_c_compstr0_shift_x(MUX,17076)@81
    assign rightShiftStage0_uid17077_dupName_137_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17077_dupName_137_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_q or rightShiftStage0Idx1_uid17075_dupName_137_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17077_dupName_137_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17077_dupName_137_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_q;
            1'b1 : rightShiftStage0_uid17077_dupName_137_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17075_dupName_137_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17077_dupName_137_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17082_dupName_137_i_unnamed_c_compstr0_shift_x(MUX,17081)@81
    assign rightShiftStage1_uid17082_dupName_137_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17082_dupName_137_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17077_dupName_137_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17080_dupName_137_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17082_dupName_137_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17082_dupName_137_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17077_dupName_137_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17082_dupName_137_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17080_dupName_137_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17082_dupName_137_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17087_dupName_137_i_unnamed_c_compstr0_shift_x(MUX,17086)@81
    assign rightShiftStage2_uid17087_dupName_137_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17087_dupName_137_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17082_dupName_137_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17085_dupName_137_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17087_dupName_137_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17087_dupName_137_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17082_dupName_137_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17087_dupName_137_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17085_dupName_137_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17087_dupName_137_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr989_vt_select_20(BITSELECT,12610)@81
    assign i_unnamed_c_compstr989_vt_select_20_b = rightShiftStage2_uid17087_dupName_137_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr989_vt_join(BITJOIN,12609)@81
    assign i_unnamed_c_compstr989_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr989_vt_select_20_b};

    // i_conv_i_i_i_i_i_34_c_compstr990_sel_x(BITSELECT,3767)@81
    assign i_conv_i_i_i_i_i_34_c_compstr990_sel_x_b = i_unnamed_c_compstr989_vt_join_q[15:0];

    // redist1098_i_conv_i_i_i_i_i_34_c_compstr990_sel_x_b_1(DELAY,29326)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1098_i_conv_i_i_i_i_i_34_c_compstr990_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_34_c_compstr990_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17096_dupName_138_i_unnamed_c_compstr0_shift_x(BITSELECT,17095)@81
    assign rightShiftStage1Idx1Rng8_uid17096_dupName_138_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17095_dupName_138_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17098_dupName_138_i_unnamed_c_compstr0_shift_x(BITJOIN,17097)@81
    assign rightShiftStage1Idx1_uid17098_dupName_138_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17096_dupName_138_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17091_dupName_138_i_unnamed_c_compstr0_shift_x(BITSELECT,17090)@81
    assign rightShiftStage0Idx1Rng4_uid17091_dupName_138_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_q[33:4];

    // rightShiftStage0Idx1_uid17093_dupName_138_i_unnamed_c_compstr0_shift_x(BITJOIN,17092)@81
    assign rightShiftStage0Idx1_uid17093_dupName_138_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17091_dupName_138_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17095_dupName_138_i_unnamed_c_compstr0_shift_x(MUX,17094)@81
    assign rightShiftStage0_uid17095_dupName_138_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17095_dupName_138_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_q or rightShiftStage0Idx1_uid17093_dupName_138_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17095_dupName_138_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17095_dupName_138_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compstr988_q;
            1'b1 : rightShiftStage0_uid17095_dupName_138_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17093_dupName_138_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17095_dupName_138_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17100_dupName_138_i_unnamed_c_compstr0_shift_x(MUX,17099)@81
    assign rightShiftStage1_uid17100_dupName_138_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17100_dupName_138_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17095_dupName_138_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17098_dupName_138_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17100_dupName_138_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17100_dupName_138_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17095_dupName_138_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17100_dupName_138_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17098_dupName_138_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17100_dupName_138_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr991_vt_select_21(BITSELECT,12613)@81
    assign i_unnamed_c_compstr991_vt_select_21_b = rightShiftStage1_uid17100_dupName_138_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr991_vt_join(BITJOIN,12612)@81
    assign i_unnamed_c_compstr991_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr991_vt_select_21_b};

    // i_unnamed_c_compstr992_sel_x(BITSELECT,6290)@81
    assign i_unnamed_c_compstr992_sel_x_b = i_unnamed_c_compstr991_vt_join_q[15:0];

    // i_unnamed_c_compstr993_BitSelect_for_a(BITSELECT,27969)@81
    assign i_unnamed_c_compstr993_BitSelect_for_a_b = i_unnamed_c_compstr992_sel_x_b[0:0];

    // i_unnamed_c_compstr993_join(BITJOIN,27970)@81
    assign i_unnamed_c_compstr993_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr993_BitSelect_for_a_b};

    // i_unnamed_c_compstr993_vt_select_0(BITSELECT,12618)@81
    assign i_unnamed_c_compstr993_vt_select_0_b = i_unnamed_c_compstr993_join_q[0:0];

    // redist2_i_unnamed_c_compstr993_vt_select_0_b_1(DELAY,28230)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist2_i_unnamed_c_compstr993_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr993_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr993_vt_join(BITJOIN,12617)@82
    assign i_unnamed_c_compstr993_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist2_i_unnamed_c_compstr993_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_34_c_compstr994(ADD,7034)@82
    assign i_add_i_i_i_i_i_i_34_c_compstr994_a = {1'b0, i_unnamed_c_compstr993_vt_join_q};
    assign i_add_i_i_i_i_i_i_34_c_compstr994_b = {1'b0, redist1098_i_conv_i_i_i_i_i_34_c_compstr990_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_34_c_compstr994_o = $unsigned(i_add_i_i_i_i_i_i_34_c_compstr994_a) + $unsigned(i_add_i_i_i_i_i_i_34_c_compstr994_b);
    assign i_add_i_i_i_i_i_i_34_c_compstr994_q = i_add_i_i_i_i_i_i_34_c_compstr994_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_34_c_compstr994_sel_x(BITSELECT,2228)@82
    assign bgTrunc_i_add_i_i_i_i_i_i_34_c_compstr994_sel_x_b = i_add_i_i_i_i_i_i_34_c_compstr994_q[15:0];

    // i_conv_i_i_i_i_i_i279_35_c_compstr1014_sel_x(BITSELECT,3896)@82
    assign i_conv_i_i_i_i_i_i279_35_c_compstr1014_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_34_c_compstr994_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_35_c_compstr1014_vt_select_15(BITSELECT,8101)@82
    assign i_conv_i_i_i_i_i_i279_35_c_compstr1014_vt_select_15_b = i_conv_i_i_i_i_i_i279_35_c_compstr1014_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_35_c_compstr1014_vt_join(BITJOIN,8100)@82
    assign i_conv_i_i_i_i_i_i279_35_c_compstr1014_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_35_c_compstr1014_vt_select_15_b};

    // leftShiftStage0_uid26150_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x(MUX,26149)@82
    assign leftShiftStage0_uid26150_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26150_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_35_c_compstr1014_vt_join_q or leftShiftStage0Idx1_uid26148_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26150_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26150_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_35_c_compstr1014_vt_join_q;
            1'b1 : leftShiftStage0_uid26150_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26148_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26150_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26155_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x(MUX,26154)@82
    assign leftShiftStage1_uid26155_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26155_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_s or leftShiftStage0_uid26150_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26153_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26155_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26155_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q = leftShiftStage0_uid26150_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26155_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26153_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26155_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26160_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x(MUX,26159)@82
    assign leftShiftStage2_uid26160_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26160_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_s or leftShiftStage1_uid26155_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26158_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26160_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26160_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q = leftShiftStage1_uid26155_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26160_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26158_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26160_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_35_c_compstr1015_vt_select_28(BITSELECT,9589)@82
    assign i_shl_i_i_i_i_i_i_35_c_compstr1015_vt_select_28_b = leftShiftStage2_uid26160_i_shl_i_i_i_i_i_i_35_c_compstr0_shift_x_q[28:13];

    // redist327_i_shl_i_i_i_i_i_i_35_c_compstr1015_vt_select_28_b_1(DELAY,28555)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist327_i_shl_i_i_i_i_i_i_35_c_compstr1015_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_35_c_compstr1015_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_35_c_compstr1015_vt_join(BITJOIN,9588)@83
    assign i_shl_i_i_i_i_i_i_35_c_compstr1015_vt_join_q = {redist327_i_shl_i_i_i_i_i_i_35_c_compstr1015_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt(ADD,33105)
    assign redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_a = {1'b0, redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_q};
    assign redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_o <= $unsigned(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_a) + $unsigned(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_b);
        end
    end
    assign redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_q = redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_o[5:0];

    // redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_inputreg0(DELAY,33100)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl);
        end
    end

    // redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem(DUALMEM,33102)
    assign redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_ia = $unsigned(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_inputreg0_q);
    assign redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_aa = redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_q;
    assign redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_ab = redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_aa),
        .data_a(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_ab),
        .q_b(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_q = redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_iq[15:0];

    // redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_outputreg0(DELAY,33101)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_outputreg0_q <= $unsigned(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_q);
        end
    end

    // redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_inputreg0(DELAY,33106)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_inputreg0_q <= $unsigned(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_outputreg0_q);
        end
    end

    // redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr(COUNTER,33103)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_i <= $unsigned(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_q = redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_i[4:0];

    // redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem(DUALMEM,33108)
    assign redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_ia = $unsigned(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_inputreg0_q);
    assign redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_aa = redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_q;
    assign redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_ab = redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_aa),
        .data_a(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_ab),
        .q_b(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_q = redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_iq[15:0];

    // redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_outputreg0(DELAY,33107)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_outputreg0_q <= $unsigned(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_q);
        end
    end

    // redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69(DELAY,29069)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_delay_0 <= $unsigned(redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_split_1_outputreg0_q);
            redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_delay_1 <= redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_delay_0;
            redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_q <= redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_delay_1;
        end
    end

    // redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt(ADD,32733)
    assign redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_a = {1'b0, redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_q};
    assign redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_o <= $unsigned(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_a) + $unsigned(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_b);
        end
    end
    assign redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_q = redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_o[5:0];

    // redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_inputreg0(DELAY,32728)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl);
        end
    end

    // redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem(DUALMEM,32730)
    assign redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_ia = $unsigned(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_inputreg0_q);
    assign redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_aa = redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_q;
    assign redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_ab = redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_aa),
        .data_a(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_ab),
        .q_b(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_q = redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_iq[15:0];

    // redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_outputreg0(DELAY,32729)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_outputreg0_q <= $unsigned(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_q);
        end
    end

    // redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_inputreg0(DELAY,32734)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_inputreg0_q <= $unsigned(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_outputreg0_q);
        end
    end

    // redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr(COUNTER,32731)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_i <= $unsigned(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_q = redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_i[4:0];

    // redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem(DUALMEM,32736)
    assign redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_ia = $unsigned(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_inputreg0_q);
    assign redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_aa = redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_q;
    assign redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_ab = redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_aa),
        .data_a(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_ab),
        .q_b(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_q = redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_iq[15:0];

    // redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_outputreg0(DELAY,32735)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_outputreg0_q <= $unsigned(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_q);
        end
    end

    // redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69(DELAY,28814)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_delay_0 <= $unsigned(redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_split_1_outputreg0_q);
            redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_delay_1 <= redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_delay_0;
            redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_q <= redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_delay_1;
        end
    end

    // redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt(ADD,32745)
    assign redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_a = {1'b0, redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_q};
    assign redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_o <= $unsigned(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_a) + $unsigned(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_b);
        end
    end
    assign redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_q = redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_o[5:0];

    // redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_inputreg0(DELAY,32740)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl);
        end
    end

    // redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem(DUALMEM,32742)
    assign redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_ia = $unsigned(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_inputreg0_q);
    assign redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_aa = redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_q;
    assign redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_ab = redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_aa),
        .data_a(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_ab),
        .q_b(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_q = redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_iq[15:0];

    // redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_outputreg0(DELAY,32741)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_outputreg0_q <= $unsigned(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_mem_q);
        end
    end

    // redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_inputreg0(DELAY,32746)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_inputreg0_q <= $unsigned(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_outputreg0_q);
        end
    end

    // redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr(COUNTER,32743)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_i <= $unsigned(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_q = redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_i[4:0];

    // redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem(DUALMEM,32748)
    assign redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_ia = $unsigned(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_inputreg0_q);
    assign redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_aa = redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_wraddr_q;
    assign redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_ab = redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_aa),
        .data_a(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_ab),
        .q_b(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_q = redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_iq[15:0];

    // redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_outputreg0(DELAY,32747)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_outputreg0_q <= $unsigned(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_mem_q);
        end
    end

    // redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69(DELAY,28815)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_delay_0 <= $unsigned(redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_split_1_outputreg0_q);
            redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_delay_1 <= redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_delay_0;
            redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_q <= redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_delay_1;
        end
    end

    // redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt(ADD,33093)
    assign redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_a = {1'b0, redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_q};
    assign redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_o <= $unsigned(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_a) + $unsigned(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_b);
        end
    end
    assign redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_q = redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_o[5:0];

    // redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_inputreg0(DELAY,33088)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl);
        end
    end

    // redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem(DUALMEM,33090)
    assign redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_ia = $unsigned(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_inputreg0_q);
    assign redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_aa = redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_q;
    assign redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_ab = redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_aa),
        .data_a(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_ab),
        .q_b(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_q = redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_iq[15:0];

    // redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_outputreg0(DELAY,33089)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_outputreg0_q <= $unsigned(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_mem_q);
        end
    end

    // redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_inputreg0(DELAY,33094)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_inputreg0_q <= $unsigned(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_outputreg0_q);
        end
    end

    // redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr(COUNTER,33091)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_i <= $unsigned(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_q = redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_i[4:0];

    // redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem(DUALMEM,33096)
    assign redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_ia = $unsigned(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_inputreg0_q);
    assign redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_aa = redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_wraddr_q;
    assign redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_ab = redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_aa),
        .data_a(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_ab),
        .q_b(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_q = redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_iq[15:0];

    // redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_outputreg0(DELAY,33095)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_outputreg0_q <= $unsigned(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_mem_q);
        end
    end

    // redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69(DELAY,29068)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_delay_0 <= $unsigned(redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_split_1_outputreg0_q);
            redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_delay_1 <= redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_delay_0;
            redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_q <= redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_delay_1;
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27994)@77 + 5
    // out q@83
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016(ADD,8577)@83
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod216_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_b = $unsigned({{5{i_shl_i_i_i_i_i_i_35_c_compstr1015_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_35_c_compstr1015_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_o[33:0];

    // rightShiftStage0_uid17139_dupName_141_i_unnamed_c_compstr0_shift_x(MUX,17138)@83
    assign rightShiftStage0_uid17139_dupName_141_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17139_dupName_141_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_q or rightShiftStage0Idx1_uid17137_dupName_141_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17139_dupName_141_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17139_dupName_141_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_q;
            1'b1 : rightShiftStage0_uid17139_dupName_141_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17137_dupName_141_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17139_dupName_141_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17144_dupName_141_i_unnamed_c_compstr0_shift_x(MUX,17143)@83
    assign rightShiftStage1_uid17144_dupName_141_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17144_dupName_141_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17139_dupName_141_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17142_dupName_141_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17144_dupName_141_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17144_dupName_141_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17139_dupName_141_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17144_dupName_141_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17142_dupName_141_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17144_dupName_141_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17149_dupName_141_i_unnamed_c_compstr0_shift_x(MUX,17148)@83
    assign rightShiftStage2_uid17149_dupName_141_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17149_dupName_141_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17144_dupName_141_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17147_dupName_141_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17149_dupName_141_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17149_dupName_141_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17144_dupName_141_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17149_dupName_141_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17147_dupName_141_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17149_dupName_141_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1017_vt_select_20(BITSELECT,9816)@83
    assign i_unnamed_c_compstr1017_vt_select_20_b = rightShiftStage2_uid17149_dupName_141_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1017_vt_join(BITJOIN,9815)@83
    assign i_unnamed_c_compstr1017_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1017_vt_select_20_b};

    // i_conv_i_i_i_i_i_35_c_compstr1018_sel_x(BITSELECT,3768)@83
    assign i_conv_i_i_i_i_i_35_c_compstr1018_sel_x_b = i_unnamed_c_compstr1017_vt_join_q[15:0];

    // redist1097_i_conv_i_i_i_i_i_35_c_compstr1018_sel_x_b_1(DELAY,29325)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1097_i_conv_i_i_i_i_i_35_c_compstr1018_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_35_c_compstr1018_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17158_dupName_142_i_unnamed_c_compstr0_shift_x(BITSELECT,17157)@83
    assign rightShiftStage1Idx1Rng8_uid17158_dupName_142_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17157_dupName_142_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17160_dupName_142_i_unnamed_c_compstr0_shift_x(BITJOIN,17159)@83
    assign rightShiftStage1Idx1_uid17160_dupName_142_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17158_dupName_142_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17153_dupName_142_i_unnamed_c_compstr0_shift_x(BITSELECT,17152)@83
    assign rightShiftStage0Idx1Rng4_uid17153_dupName_142_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_q[33:4];

    // rightShiftStage0Idx1_uid17155_dupName_142_i_unnamed_c_compstr0_shift_x(BITJOIN,17154)@83
    assign rightShiftStage0Idx1_uid17155_dupName_142_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17153_dupName_142_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17157_dupName_142_i_unnamed_c_compstr0_shift_x(MUX,17156)@83
    assign rightShiftStage0_uid17157_dupName_142_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17157_dupName_142_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_q or rightShiftStage0Idx1_uid17155_dupName_142_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17157_dupName_142_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17157_dupName_142_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compstr1016_q;
            1'b1 : rightShiftStage0_uid17157_dupName_142_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17155_dupName_142_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17157_dupName_142_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17162_dupName_142_i_unnamed_c_compstr0_shift_x(MUX,17161)@83
    assign rightShiftStage1_uid17162_dupName_142_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17162_dupName_142_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17157_dupName_142_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17160_dupName_142_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17162_dupName_142_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17162_dupName_142_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17157_dupName_142_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17162_dupName_142_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17160_dupName_142_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17162_dupName_142_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1019_vt_select_21(BITSELECT,9819)@83
    assign i_unnamed_c_compstr1019_vt_select_21_b = rightShiftStage1_uid17162_dupName_142_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1019_vt_join(BITJOIN,9818)@83
    assign i_unnamed_c_compstr1019_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1019_vt_select_21_b};

    // i_unnamed_c_compstr1020_sel_x(BITSELECT,6036)@83
    assign i_unnamed_c_compstr1020_sel_x_b = i_unnamed_c_compstr1019_vt_join_q[15:0];

    // i_unnamed_c_compstr1021_BitSelect_for_a(BITSELECT,27461)@83
    assign i_unnamed_c_compstr1021_BitSelect_for_a_b = i_unnamed_c_compstr1020_sel_x_b[0:0];

    // i_unnamed_c_compstr1021_join(BITJOIN,27462)@83
    assign i_unnamed_c_compstr1021_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1021_BitSelect_for_a_b};

    // i_unnamed_c_compstr1021_vt_select_0(BITSELECT,9824)@83
    assign i_unnamed_c_compstr1021_vt_select_0_b = i_unnamed_c_compstr1021_join_q[0:0];

    // redist254_i_unnamed_c_compstr1021_vt_select_0_b_1(DELAY,28482)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist254_i_unnamed_c_compstr1021_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1021_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1021_vt_join(BITJOIN,9823)@84
    assign i_unnamed_c_compstr1021_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist254_i_unnamed_c_compstr1021_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_35_c_compstr1022(ADD,7035)@84
    assign i_add_i_i_i_i_i_i_35_c_compstr1022_a = {1'b0, i_unnamed_c_compstr1021_vt_join_q};
    assign i_add_i_i_i_i_i_i_35_c_compstr1022_b = {1'b0, redist1097_i_conv_i_i_i_i_i_35_c_compstr1018_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_35_c_compstr1022_o = $unsigned(i_add_i_i_i_i_i_i_35_c_compstr1022_a) + $unsigned(i_add_i_i_i_i_i_i_35_c_compstr1022_b);
    assign i_add_i_i_i_i_i_i_35_c_compstr1022_q = i_add_i_i_i_i_i_i_35_c_compstr1022_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_35_c_compstr1022_sel_x(BITSELECT,2229)@84
    assign bgTrunc_i_add_i_i_i_i_i_i_35_c_compstr1022_sel_x_b = i_add_i_i_i_i_i_i_35_c_compstr1022_q[15:0];

    // i_conv_i_i_i_i_i_i279_36_c_compstr1042_sel_x(BITSELECT,3897)@84
    assign i_conv_i_i_i_i_i_i279_36_c_compstr1042_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_35_c_compstr1022_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_36_c_compstr1042_vt_select_15(BITSELECT,8105)@84
    assign i_conv_i_i_i_i_i_i279_36_c_compstr1042_vt_select_15_b = i_conv_i_i_i_i_i_i279_36_c_compstr1042_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_36_c_compstr1042_vt_join(BITJOIN,8104)@84
    assign i_conv_i_i_i_i_i_i279_36_c_compstr1042_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_36_c_compstr1042_vt_select_15_b};

    // leftShiftStage0_uid26168_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x(MUX,26167)@84
    assign leftShiftStage0_uid26168_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26168_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_36_c_compstr1042_vt_join_q or leftShiftStage0Idx1_uid26166_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26168_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26168_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_36_c_compstr1042_vt_join_q;
            1'b1 : leftShiftStage0_uid26168_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26166_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26168_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26173_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x(MUX,26172)@84
    assign leftShiftStage1_uid26173_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26173_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_s or leftShiftStage0_uid26168_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26171_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26173_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26173_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q = leftShiftStage0_uid26168_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26173_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26171_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26173_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26178_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x(MUX,26177)@84
    assign leftShiftStage2_uid26178_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26178_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_s or leftShiftStage1_uid26173_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26176_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26178_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26178_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q = leftShiftStage1_uid26173_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26178_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26176_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26178_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_36_c_compstr1043_vt_select_28(BITSELECT,9592)@84
    assign i_shl_i_i_i_i_i_i_36_c_compstr1043_vt_select_28_b = leftShiftStage2_uid26178_i_shl_i_i_i_i_i_i_36_c_compstr0_shift_x_q[28:13];

    // redist326_i_shl_i_i_i_i_i_i_36_c_compstr1043_vt_select_28_b_1(DELAY,28554)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist326_i_shl_i_i_i_i_i_i_36_c_compstr1043_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_36_c_compstr1043_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_36_c_compstr1043_vt_join(BITJOIN,9591)@85
    assign i_shl_i_i_i_i_i_i_36_c_compstr1043_vt_join_q = {redist326_i_shl_i_i_i_i_i_i_36_c_compstr1043_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt(ADD,33129)
    assign redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_a = {1'b0, redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_q};
    assign redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_o <= $unsigned(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_a) + $unsigned(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_b);
        end
    end
    assign redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_q = redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_o[5:0];

    // redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_inputreg0(DELAY,33124)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl);
        end
    end

    // redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem(DUALMEM,33126)
    assign redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_ia = $unsigned(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_inputreg0_q);
    assign redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_aa = redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_q;
    assign redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_ab = redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_aa),
        .data_a(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_ab),
        .q_b(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_q = redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_iq[15:0];

    // redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_outputreg0(DELAY,33125)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_outputreg0_q <= $unsigned(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_q);
        end
    end

    // redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_inputreg0(DELAY,33130)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_inputreg0_q <= $unsigned(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_outputreg0_q);
        end
    end

    // redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr(COUNTER,33127)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_i <= $unsigned(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_q = redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_i[4:0];

    // redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem(DUALMEM,33132)
    assign redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_ia = $unsigned(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_inputreg0_q);
    assign redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_aa = redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_q;
    assign redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_ab = redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_aa),
        .data_a(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_ab),
        .q_b(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_q = redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_iq[15:0];

    // redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_outputreg0(DELAY,33131)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_outputreg0_q <= $unsigned(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_q);
        end
    end

    // redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_inputreg0(DELAY,31414)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_inputreg0_q <= $unsigned(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_split_1_outputreg0_q);
        end
    end

    // redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71(DELAY,29071)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_delay_0 <= $unsigned(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_inputreg0_q);
            redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_delay_1 <= redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_delay_0;
            redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_q <= redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_delay_1;
        end
    end

    // redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_outputreg0(DELAY,31415)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_outputreg0_q <= $unsigned(redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_q);
        end
    end

    // redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt(ADD,32757)
    assign redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_a = {1'b0, redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_q};
    assign redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_o <= $unsigned(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_a) + $unsigned(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_b);
        end
    end
    assign redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_q = redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_o[5:0];

    // redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_inputreg0(DELAY,32752)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl);
        end
    end

    // redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem(DUALMEM,32754)
    assign redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_ia = $unsigned(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_inputreg0_q);
    assign redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_aa = redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_q;
    assign redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_ab = redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_aa),
        .data_a(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_ab),
        .q_b(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_q = redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_iq[15:0];

    // redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_outputreg0(DELAY,32753)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_outputreg0_q <= $unsigned(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_q);
        end
    end

    // redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_inputreg0(DELAY,32758)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_inputreg0_q <= $unsigned(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_outputreg0_q);
        end
    end

    // redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr(COUNTER,32755)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_i <= $unsigned(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_q = redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_i[4:0];

    // redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem(DUALMEM,32760)
    assign redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_ia = $unsigned(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_inputreg0_q);
    assign redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_aa = redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_q;
    assign redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_ab = redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_aa),
        .data_a(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_ab),
        .q_b(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_q = redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_iq[15:0];

    // redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_outputreg0(DELAY,32759)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_outputreg0_q <= $unsigned(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_q);
        end
    end

    // redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_inputreg0(DELAY,29970)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_inputreg0_q <= $unsigned(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_split_1_outputreg0_q);
        end
    end

    // redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71(DELAY,28816)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_delay_0 <= $unsigned(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_inputreg0_q);
            redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_delay_1 <= redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_delay_0;
            redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_q <= redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_delay_1;
        end
    end

    // redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_outputreg0(DELAY,29971)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_outputreg0_q <= $unsigned(redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_q);
        end
    end

    // redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt(ADD,32769)
    assign redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_a = {1'b0, redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_q};
    assign redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_o <= $unsigned(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_a) + $unsigned(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_b);
        end
    end
    assign redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_q = redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_o[5:0];

    // redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_inputreg0(DELAY,32764)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl);
        end
    end

    // redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem(DUALMEM,32766)
    assign redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_ia = $unsigned(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_inputreg0_q);
    assign redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_aa = redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_q;
    assign redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_ab = redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_aa),
        .data_a(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_ab),
        .q_b(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_q = redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_iq[15:0];

    // redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_outputreg0(DELAY,32765)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_outputreg0_q <= $unsigned(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_mem_q);
        end
    end

    // redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_inputreg0(DELAY,32770)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_inputreg0_q <= $unsigned(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_outputreg0_q);
        end
    end

    // redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr(COUNTER,32767)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_i <= $unsigned(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_q = redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_i[4:0];

    // redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem(DUALMEM,32772)
    assign redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_ia = $unsigned(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_inputreg0_q);
    assign redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_aa = redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_wraddr_q;
    assign redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_ab = redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_aa),
        .data_a(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_ab),
        .q_b(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_q = redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_iq[15:0];

    // redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_outputreg0(DELAY,32771)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_outputreg0_q <= $unsigned(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_mem_q);
        end
    end

    // redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_inputreg0(DELAY,29972)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_inputreg0_q <= $unsigned(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_split_1_outputreg0_q);
        end
    end

    // redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71(DELAY,28817)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_delay_0 <= $unsigned(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_inputreg0_q);
            redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_delay_1 <= redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_delay_0;
            redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_q <= redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_delay_1;
        end
    end

    // redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_outputreg0(DELAY,29973)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_outputreg0_q <= $unsigned(redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_q);
        end
    end

    // redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt(ADD,33117)
    assign redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_a = {1'b0, redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_q};
    assign redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_o <= $unsigned(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_a) + $unsigned(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_b);
        end
    end
    assign redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_q = redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_o[5:0];

    // redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_inputreg0(DELAY,33112)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl);
        end
    end

    // redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem(DUALMEM,33114)
    assign redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_ia = $unsigned(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_inputreg0_q);
    assign redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_aa = redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_q;
    assign redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_ab = redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_aa),
        .data_a(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_ab),
        .q_b(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_q = redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_iq[15:0];

    // redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_outputreg0(DELAY,33113)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_outputreg0_q <= $unsigned(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_mem_q);
        end
    end

    // redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_inputreg0(DELAY,33118)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_inputreg0_q <= $unsigned(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_outputreg0_q);
        end
    end

    // redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr(COUNTER,33115)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_i <= $unsigned(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_q = redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_i[4:0];

    // redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem(DUALMEM,33120)
    assign redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_ia = $unsigned(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_inputreg0_q);
    assign redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_aa = redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_wraddr_q;
    assign redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_ab = redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_aa),
        .data_a(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_ab),
        .q_b(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_q = redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_iq[15:0];

    // redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_outputreg0(DELAY,33119)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_outputreg0_q <= $unsigned(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_mem_q);
        end
    end

    // redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_inputreg0(DELAY,31412)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_inputreg0_q <= $unsigned(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_split_1_outputreg0_q);
        end
    end

    // redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71(DELAY,29070)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_delay_0 <= $unsigned(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_inputreg0_q);
            redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_delay_1 <= redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_delay_0;
            redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_q <= redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_delay_1;
        end
    end

    // redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_outputreg0(DELAY,31413)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_outputreg0_q <= $unsigned(redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27995)@79 + 5
    // out q@85
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044(ADD,8578)@85
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod221_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_b = $unsigned({{5{i_shl_i_i_i_i_i_i_36_c_compstr1043_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_36_c_compstr1043_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_o[33:0];

    // rightShiftStage0_uid17201_dupName_145_i_unnamed_c_compstr0_shift_x(MUX,17200)@85
    assign rightShiftStage0_uid17201_dupName_145_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17201_dupName_145_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_q or rightShiftStage0Idx1_uid17199_dupName_145_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17201_dupName_145_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17201_dupName_145_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_q;
            1'b1 : rightShiftStage0_uid17201_dupName_145_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17199_dupName_145_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17201_dupName_145_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17206_dupName_145_i_unnamed_c_compstr0_shift_x(MUX,17205)@85
    assign rightShiftStage1_uid17206_dupName_145_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17206_dupName_145_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17201_dupName_145_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17204_dupName_145_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17206_dupName_145_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17206_dupName_145_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17201_dupName_145_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17206_dupName_145_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17204_dupName_145_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17206_dupName_145_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17211_dupName_145_i_unnamed_c_compstr0_shift_x(MUX,17210)@85
    assign rightShiftStage2_uid17211_dupName_145_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17211_dupName_145_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17206_dupName_145_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17209_dupName_145_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17211_dupName_145_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17211_dupName_145_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17206_dupName_145_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17211_dupName_145_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17209_dupName_145_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17211_dupName_145_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1045_vt_select_20(BITSELECT,9838)@85
    assign i_unnamed_c_compstr1045_vt_select_20_b = rightShiftStage2_uid17211_dupName_145_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1045_vt_join(BITJOIN,9837)@85
    assign i_unnamed_c_compstr1045_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1045_vt_select_20_b};

    // i_conv_i_i_i_i_i_36_c_compstr1046_sel_x(BITSELECT,3769)@85
    assign i_conv_i_i_i_i_i_36_c_compstr1046_sel_x_b = i_unnamed_c_compstr1045_vt_join_q[15:0];

    // redist1096_i_conv_i_i_i_i_i_36_c_compstr1046_sel_x_b_1(DELAY,29324)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1096_i_conv_i_i_i_i_i_36_c_compstr1046_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_36_c_compstr1046_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17220_dupName_146_i_unnamed_c_compstr0_shift_x(BITSELECT,17219)@85
    assign rightShiftStage1Idx1Rng8_uid17220_dupName_146_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17219_dupName_146_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17222_dupName_146_i_unnamed_c_compstr0_shift_x(BITJOIN,17221)@85
    assign rightShiftStage1Idx1_uid17222_dupName_146_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17220_dupName_146_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17215_dupName_146_i_unnamed_c_compstr0_shift_x(BITSELECT,17214)@85
    assign rightShiftStage0Idx1Rng4_uid17215_dupName_146_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_q[33:4];

    // rightShiftStage0Idx1_uid17217_dupName_146_i_unnamed_c_compstr0_shift_x(BITJOIN,17216)@85
    assign rightShiftStage0Idx1_uid17217_dupName_146_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17215_dupName_146_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17219_dupName_146_i_unnamed_c_compstr0_shift_x(MUX,17218)@85
    assign rightShiftStage0_uid17219_dupName_146_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17219_dupName_146_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_q or rightShiftStage0Idx1_uid17217_dupName_146_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17219_dupName_146_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17219_dupName_146_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compstr1044_q;
            1'b1 : rightShiftStage0_uid17219_dupName_146_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17217_dupName_146_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17219_dupName_146_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17224_dupName_146_i_unnamed_c_compstr0_shift_x(MUX,17223)@85
    assign rightShiftStage1_uid17224_dupName_146_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17224_dupName_146_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17219_dupName_146_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17222_dupName_146_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17224_dupName_146_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17224_dupName_146_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17219_dupName_146_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17224_dupName_146_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17222_dupName_146_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17224_dupName_146_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1047_vt_select_21(BITSELECT,9841)@85
    assign i_unnamed_c_compstr1047_vt_select_21_b = rightShiftStage1_uid17224_dupName_146_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1047_vt_join(BITJOIN,9840)@85
    assign i_unnamed_c_compstr1047_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1047_vt_select_21_b};

    // i_unnamed_c_compstr1048_sel_x(BITSELECT,6038)@85
    assign i_unnamed_c_compstr1048_sel_x_b = i_unnamed_c_compstr1047_vt_join_q[15:0];

    // i_unnamed_c_compstr1049_BitSelect_for_a(BITSELECT,27465)@85
    assign i_unnamed_c_compstr1049_BitSelect_for_a_b = i_unnamed_c_compstr1048_sel_x_b[0:0];

    // i_unnamed_c_compstr1049_join(BITJOIN,27466)@85
    assign i_unnamed_c_compstr1049_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1049_BitSelect_for_a_b};

    // i_unnamed_c_compstr1049_vt_select_0(BITSELECT,9846)@85
    assign i_unnamed_c_compstr1049_vt_select_0_b = i_unnamed_c_compstr1049_join_q[0:0];

    // redist252_i_unnamed_c_compstr1049_vt_select_0_b_1(DELAY,28480)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist252_i_unnamed_c_compstr1049_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1049_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1049_vt_join(BITJOIN,9845)@86
    assign i_unnamed_c_compstr1049_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist252_i_unnamed_c_compstr1049_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_36_c_compstr1050(ADD,7036)@86
    assign i_add_i_i_i_i_i_i_36_c_compstr1050_a = {1'b0, i_unnamed_c_compstr1049_vt_join_q};
    assign i_add_i_i_i_i_i_i_36_c_compstr1050_b = {1'b0, redist1096_i_conv_i_i_i_i_i_36_c_compstr1046_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_36_c_compstr1050_o = $unsigned(i_add_i_i_i_i_i_i_36_c_compstr1050_a) + $unsigned(i_add_i_i_i_i_i_i_36_c_compstr1050_b);
    assign i_add_i_i_i_i_i_i_36_c_compstr1050_q = i_add_i_i_i_i_i_i_36_c_compstr1050_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_36_c_compstr1050_sel_x(BITSELECT,2230)@86
    assign bgTrunc_i_add_i_i_i_i_i_i_36_c_compstr1050_sel_x_b = i_add_i_i_i_i_i_i_36_c_compstr1050_q[15:0];

    // i_conv_i_i_i_i_i_i279_37_c_compstr1070_sel_x(BITSELECT,3898)@86
    assign i_conv_i_i_i_i_i_i279_37_c_compstr1070_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_36_c_compstr1050_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_37_c_compstr1070_vt_select_15(BITSELECT,8109)@86
    assign i_conv_i_i_i_i_i_i279_37_c_compstr1070_vt_select_15_b = i_conv_i_i_i_i_i_i279_37_c_compstr1070_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_37_c_compstr1070_vt_join(BITJOIN,8108)@86
    assign i_conv_i_i_i_i_i_i279_37_c_compstr1070_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_37_c_compstr1070_vt_select_15_b};

    // leftShiftStage0_uid26186_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x(MUX,26185)@86
    assign leftShiftStage0_uid26186_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26186_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_37_c_compstr1070_vt_join_q or leftShiftStage0Idx1_uid26184_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26186_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26186_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_37_c_compstr1070_vt_join_q;
            1'b1 : leftShiftStage0_uid26186_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26184_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26186_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26191_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x(MUX,26190)@86
    assign leftShiftStage1_uid26191_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26191_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_s or leftShiftStage0_uid26186_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26189_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26191_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26191_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q = leftShiftStage0_uid26186_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26191_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26189_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26191_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26196_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x(MUX,26195)@86
    assign leftShiftStage2_uid26196_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26196_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_s or leftShiftStage1_uid26191_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26194_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26196_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26196_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q = leftShiftStage1_uid26191_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26196_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26194_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26196_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_37_c_compstr1071_vt_select_28(BITSELECT,9595)@86
    assign i_shl_i_i_i_i_i_i_37_c_compstr1071_vt_select_28_b = leftShiftStage2_uid26196_i_shl_i_i_i_i_i_i_37_c_compstr0_shift_x_q[28:13];

    // redist325_i_shl_i_i_i_i_i_i_37_c_compstr1071_vt_select_28_b_1(DELAY,28553)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist325_i_shl_i_i_i_i_i_i_37_c_compstr1071_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_37_c_compstr1071_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_37_c_compstr1071_vt_join(BITJOIN,9594)@87
    assign i_shl_i_i_i_i_i_i_37_c_compstr1071_vt_join_q = {redist325_i_shl_i_i_i_i_i_i_37_c_compstr1071_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_rdcnt(ADD,31427)
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_a = {1'b0, redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_wraddr_q};
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_b = {1'b0, redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_o <= $unsigned(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_a) + $unsigned(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_b);
        end
    end
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_q = redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_o[2:0];

    // redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt(ADD,33153)
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_a = {1'b0, redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_q};
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_o <= $unsigned(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_a) + $unsigned(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_b);
        end
    end
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_q = redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_o[5:0];

    // redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_inputreg0(DELAY,33148)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl);
        end
    end

    // redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem(DUALMEM,33150)
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_ia = $unsigned(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_inputreg0_q);
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_aa = redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_q;
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_ab = redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_aa),
        .data_a(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_ab),
        .q_b(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_q = redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_iq[15:0];

    // redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_outputreg0(DELAY,33149)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_outputreg0_q <= $unsigned(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_q);
        end
    end

    // redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_inputreg0(DELAY,33154)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_inputreg0_q <= $unsigned(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_outputreg0_q);
        end
    end

    // redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr(COUNTER,33151)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_i <= $unsigned(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_q = redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_i[4:0];

    // redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem(DUALMEM,33156)
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_ia = $unsigned(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_inputreg0_q);
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_aa = redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_q;
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_ab = redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_aa),
        .data_a(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_ab),
        .q_b(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_q = redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_iq[15:0];

    // redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_outputreg0(DELAY,33155)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_outputreg0_q <= $unsigned(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_q);
        end
    end

    // redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_inputreg0(DELAY,31422)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_inputreg0_q <= $unsigned(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_split_1_outputreg0_q);
        end
    end

    // redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_wraddr(COUNTER,31425)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_wraddr_i <= $unsigned(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_wraddr_q = redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_wraddr_i[1:0];

    // redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem(DUALMEM,31424)
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_ia = $unsigned(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_inputreg0_q);
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_aa = redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_wraddr_q;
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_ab = redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_aa),
        .data_a(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_ab),
        .q_b(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_q = redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_iq[15:0];

    // redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_outputreg0(DELAY,31423)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_outputreg0_q <= $unsigned(redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_mem_q);
        end
    end

    // redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_rdcnt(ADD,29979)
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_a = {1'b0, redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_wraddr_q};
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_b = {1'b0, redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_o <= $unsigned(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_a) + $unsigned(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_b);
        end
    end
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_q = redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_o[2:0];

    // redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt(ADD,32781)
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_a = {1'b0, redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_q};
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_o <= $unsigned(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_a) + $unsigned(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_b);
        end
    end
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_q = redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_o[5:0];

    // redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_inputreg0(DELAY,32776)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl);
        end
    end

    // redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem(DUALMEM,32778)
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_ia = $unsigned(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_inputreg0_q);
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_aa = redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_q;
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_ab = redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_aa),
        .data_a(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_ab),
        .q_b(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_q = redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_iq[15:0];

    // redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_outputreg0(DELAY,32777)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_outputreg0_q <= $unsigned(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_q);
        end
    end

    // redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_inputreg0(DELAY,32782)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_inputreg0_q <= $unsigned(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_outputreg0_q);
        end
    end

    // redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr(COUNTER,32779)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_i <= $unsigned(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_q = redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_i[4:0];

    // redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem(DUALMEM,32784)
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_ia = $unsigned(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_inputreg0_q);
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_aa = redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_q;
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_ab = redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_aa),
        .data_a(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_ab),
        .q_b(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_q = redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_iq[15:0];

    // redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_outputreg0(DELAY,32783)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_outputreg0_q <= $unsigned(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_q);
        end
    end

    // redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_inputreg0(DELAY,29974)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_inputreg0_q <= $unsigned(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_split_1_outputreg0_q);
        end
    end

    // redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_wraddr(COUNTER,29977)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_wraddr_i <= $unsigned(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_wraddr_q = redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_wraddr_i[1:0];

    // redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem(DUALMEM,29976)
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_ia = $unsigned(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_inputreg0_q);
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_aa = redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_wraddr_q;
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_ab = redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_aa),
        .data_a(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_ab),
        .q_b(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_q = redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_iq[15:0];

    // redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_outputreg0(DELAY,29975)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_outputreg0_q <= $unsigned(redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_mem_q);
        end
    end

    // redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_rdcnt(ADD,29985)
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_a = {1'b0, redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_wraddr_q};
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_b = {1'b0, redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_o <= $unsigned(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_a) + $unsigned(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_b);
        end
    end
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_q = redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_o[2:0];

    // redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt(ADD,32793)
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_a = {1'b0, redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_q};
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_o <= $unsigned(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_a) + $unsigned(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_b);
        end
    end
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_q = redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_o[5:0];

    // redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_inputreg0(DELAY,32788)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl);
        end
    end

    // redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem(DUALMEM,32790)
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_ia = $unsigned(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_inputreg0_q);
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_aa = redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_q;
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_ab = redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_aa),
        .data_a(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_ab),
        .q_b(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_q = redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_iq[15:0];

    // redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_outputreg0(DELAY,32789)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_outputreg0_q <= $unsigned(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_mem_q);
        end
    end

    // redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_inputreg0(DELAY,32794)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_inputreg0_q <= $unsigned(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_outputreg0_q);
        end
    end

    // redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr(COUNTER,32791)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_i <= $unsigned(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_q = redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_i[4:0];

    // redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem(DUALMEM,32796)
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_ia = $unsigned(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_inputreg0_q);
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_aa = redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_wraddr_q;
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_ab = redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_aa),
        .data_a(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_ab),
        .q_b(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_q = redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_iq[15:0];

    // redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_outputreg0(DELAY,32795)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_outputreg0_q <= $unsigned(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_mem_q);
        end
    end

    // redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_inputreg0(DELAY,29980)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_inputreg0_q <= $unsigned(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_split_1_outputreg0_q);
        end
    end

    // redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_wraddr(COUNTER,29983)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_wraddr_i <= $unsigned(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_wraddr_q = redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_wraddr_i[1:0];

    // redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem(DUALMEM,29982)
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_ia = $unsigned(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_inputreg0_q);
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_aa = redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_wraddr_q;
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_ab = redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_aa),
        .data_a(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_ab),
        .q_b(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_q = redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_iq[15:0];

    // redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_outputreg0(DELAY,29981)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_outputreg0_q <= $unsigned(redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_mem_q);
        end
    end

    // redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_rdcnt(ADD,31421)
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_a = {1'b0, redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_wraddr_q};
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_b = {1'b0, redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_o <= $unsigned(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_a) + $unsigned(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_b);
        end
    end
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_q = redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_o[2:0];

    // redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt(ADD,33141)
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_a = {1'b0, redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_q};
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_o <= $unsigned(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_a) + $unsigned(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_b);
        end
    end
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_q = redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_o[5:0];

    // redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_inputreg0(DELAY,33136)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl);
        end
    end

    // redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem(DUALMEM,33138)
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_ia = $unsigned(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_inputreg0_q);
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_aa = redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_q;
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_ab = redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_aa),
        .data_a(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_ab),
        .q_b(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_q = redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_iq[15:0];

    // redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_outputreg0(DELAY,33137)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_outputreg0_q <= $unsigned(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_mem_q);
        end
    end

    // redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_inputreg0(DELAY,33142)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_inputreg0_q <= $unsigned(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_outputreg0_q);
        end
    end

    // redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr(COUNTER,33139)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_i <= $unsigned(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_q = redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_i[4:0];

    // redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem(DUALMEM,33144)
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_ia = $unsigned(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_inputreg0_q);
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_aa = redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_wraddr_q;
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_ab = redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_aa),
        .data_a(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_ab),
        .q_b(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_q = redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_iq[15:0];

    // redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_outputreg0(DELAY,33143)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_outputreg0_q <= $unsigned(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_mem_q);
        end
    end

    // redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_inputreg0(DELAY,31416)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_inputreg0_q <= $unsigned(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_split_1_outputreg0_q);
        end
    end

    // redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_wraddr(COUNTER,31419)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_wraddr_i <= $unsigned(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_wraddr_q = redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_wraddr_i[1:0];

    // redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem(DUALMEM,31418)
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_ia = $unsigned(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_inputreg0_q);
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_aa = redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_wraddr_q;
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_ab = redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_aa),
        .data_a(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_ab),
        .q_b(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_q = redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_iq[15:0];

    // redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_outputreg0(DELAY,31417)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_outputreg0_q <= $unsigned(redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27996)@81 + 5
    // out q@87
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072(ADD,8579)@87
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod226_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_b = $unsigned({{5{i_shl_i_i_i_i_i_i_37_c_compstr1071_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_37_c_compstr1071_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_o[33:0];

    // rightShiftStage0_uid17263_dupName_149_i_unnamed_c_compstr0_shift_x(MUX,17262)@87
    assign rightShiftStage0_uid17263_dupName_149_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17263_dupName_149_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_q or rightShiftStage0Idx1_uid17261_dupName_149_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17263_dupName_149_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17263_dupName_149_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_q;
            1'b1 : rightShiftStage0_uid17263_dupName_149_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17261_dupName_149_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17263_dupName_149_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17268_dupName_149_i_unnamed_c_compstr0_shift_x(MUX,17267)@87
    assign rightShiftStage1_uid17268_dupName_149_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17268_dupName_149_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17263_dupName_149_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17266_dupName_149_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17268_dupName_149_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17268_dupName_149_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17263_dupName_149_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17268_dupName_149_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17266_dupName_149_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17268_dupName_149_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17273_dupName_149_i_unnamed_c_compstr0_shift_x(MUX,17272)@87
    assign rightShiftStage2_uid17273_dupName_149_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17273_dupName_149_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17268_dupName_149_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17271_dupName_149_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17273_dupName_149_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17273_dupName_149_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17268_dupName_149_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17273_dupName_149_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17271_dupName_149_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17273_dupName_149_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1073_vt_select_20(BITSELECT,9863)@87
    assign i_unnamed_c_compstr1073_vt_select_20_b = rightShiftStage2_uid17273_dupName_149_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1073_vt_join(BITJOIN,9862)@87
    assign i_unnamed_c_compstr1073_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1073_vt_select_20_b};

    // i_conv_i_i_i_i_i_37_c_compstr1074_sel_x(BITSELECT,3770)@87
    assign i_conv_i_i_i_i_i_37_c_compstr1074_sel_x_b = i_unnamed_c_compstr1073_vt_join_q[15:0];

    // redist1095_i_conv_i_i_i_i_i_37_c_compstr1074_sel_x_b_1(DELAY,29323)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1095_i_conv_i_i_i_i_i_37_c_compstr1074_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_37_c_compstr1074_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17282_dupName_150_i_unnamed_c_compstr0_shift_x(BITSELECT,17281)@87
    assign rightShiftStage1Idx1Rng8_uid17282_dupName_150_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17281_dupName_150_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17284_dupName_150_i_unnamed_c_compstr0_shift_x(BITJOIN,17283)@87
    assign rightShiftStage1Idx1_uid17284_dupName_150_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17282_dupName_150_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17277_dupName_150_i_unnamed_c_compstr0_shift_x(BITSELECT,17276)@87
    assign rightShiftStage0Idx1Rng4_uid17277_dupName_150_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_q[33:4];

    // rightShiftStage0Idx1_uid17279_dupName_150_i_unnamed_c_compstr0_shift_x(BITJOIN,17278)@87
    assign rightShiftStage0Idx1_uid17279_dupName_150_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17277_dupName_150_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17281_dupName_150_i_unnamed_c_compstr0_shift_x(MUX,17280)@87
    assign rightShiftStage0_uid17281_dupName_150_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17281_dupName_150_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_q or rightShiftStage0Idx1_uid17279_dupName_150_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17281_dupName_150_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17281_dupName_150_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compstr1072_q;
            1'b1 : rightShiftStage0_uid17281_dupName_150_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17279_dupName_150_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17281_dupName_150_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17286_dupName_150_i_unnamed_c_compstr0_shift_x(MUX,17285)@87
    assign rightShiftStage1_uid17286_dupName_150_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17286_dupName_150_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17281_dupName_150_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17284_dupName_150_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17286_dupName_150_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17286_dupName_150_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17281_dupName_150_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17286_dupName_150_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17284_dupName_150_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17286_dupName_150_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1075_vt_select_21(BITSELECT,9866)@87
    assign i_unnamed_c_compstr1075_vt_select_21_b = rightShiftStage1_uid17286_dupName_150_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1075_vt_join(BITJOIN,9865)@87
    assign i_unnamed_c_compstr1075_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1075_vt_select_21_b};

    // i_unnamed_c_compstr1076_sel_x(BITSELECT,6040)@87
    assign i_unnamed_c_compstr1076_sel_x_b = i_unnamed_c_compstr1075_vt_join_q[15:0];

    // i_unnamed_c_compstr1077_BitSelect_for_a(BITSELECT,27469)@87
    assign i_unnamed_c_compstr1077_BitSelect_for_a_b = i_unnamed_c_compstr1076_sel_x_b[0:0];

    // i_unnamed_c_compstr1077_join(BITJOIN,27470)@87
    assign i_unnamed_c_compstr1077_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1077_BitSelect_for_a_b};

    // i_unnamed_c_compstr1077_vt_select_0(BITSELECT,9871)@87
    assign i_unnamed_c_compstr1077_vt_select_0_b = i_unnamed_c_compstr1077_join_q[0:0];

    // redist250_i_unnamed_c_compstr1077_vt_select_0_b_1(DELAY,28478)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist250_i_unnamed_c_compstr1077_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1077_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1077_vt_join(BITJOIN,9870)@88
    assign i_unnamed_c_compstr1077_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist250_i_unnamed_c_compstr1077_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_37_c_compstr1078(ADD,7037)@88
    assign i_add_i_i_i_i_i_i_37_c_compstr1078_a = {1'b0, i_unnamed_c_compstr1077_vt_join_q};
    assign i_add_i_i_i_i_i_i_37_c_compstr1078_b = {1'b0, redist1095_i_conv_i_i_i_i_i_37_c_compstr1074_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_37_c_compstr1078_o = $unsigned(i_add_i_i_i_i_i_i_37_c_compstr1078_a) + $unsigned(i_add_i_i_i_i_i_i_37_c_compstr1078_b);
    assign i_add_i_i_i_i_i_i_37_c_compstr1078_q = i_add_i_i_i_i_i_i_37_c_compstr1078_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_37_c_compstr1078_sel_x(BITSELECT,2231)@88
    assign bgTrunc_i_add_i_i_i_i_i_i_37_c_compstr1078_sel_x_b = i_add_i_i_i_i_i_i_37_c_compstr1078_q[15:0];

    // i_conv_i_i_i_i_i_i279_38_c_compstr1098_sel_x(BITSELECT,3899)@88
    assign i_conv_i_i_i_i_i_i279_38_c_compstr1098_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_37_c_compstr1078_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_38_c_compstr1098_vt_select_15(BITSELECT,8113)@88
    assign i_conv_i_i_i_i_i_i279_38_c_compstr1098_vt_select_15_b = i_conv_i_i_i_i_i_i279_38_c_compstr1098_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_38_c_compstr1098_vt_join(BITJOIN,8112)@88
    assign i_conv_i_i_i_i_i_i279_38_c_compstr1098_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_38_c_compstr1098_vt_select_15_b};

    // leftShiftStage0_uid26204_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x(MUX,26203)@88
    assign leftShiftStage0_uid26204_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26204_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_38_c_compstr1098_vt_join_q or leftShiftStage0Idx1_uid26202_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26204_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26204_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_38_c_compstr1098_vt_join_q;
            1'b1 : leftShiftStage0_uid26204_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26202_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26204_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26209_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x(MUX,26208)@88
    assign leftShiftStage1_uid26209_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26209_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_s or leftShiftStage0_uid26204_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26207_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26209_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26209_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q = leftShiftStage0_uid26204_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26209_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26207_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26209_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26214_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x(MUX,26213)@88
    assign leftShiftStage2_uid26214_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26214_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_s or leftShiftStage1_uid26209_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26212_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26214_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26214_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q = leftShiftStage1_uid26209_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26214_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26212_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26214_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_38_c_compstr1099_vt_select_28(BITSELECT,9598)@88
    assign i_shl_i_i_i_i_i_i_38_c_compstr1099_vt_select_28_b = leftShiftStage2_uid26214_i_shl_i_i_i_i_i_i_38_c_compstr0_shift_x_q[28:13];

    // redist324_i_shl_i_i_i_i_i_i_38_c_compstr1099_vt_select_28_b_1(DELAY,28552)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist324_i_shl_i_i_i_i_i_i_38_c_compstr1099_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_38_c_compstr1099_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_38_c_compstr1099_vt_join(BITJOIN,9597)@89
    assign i_shl_i_i_i_i_i_i_38_c_compstr1099_vt_join_q = {redist324_i_shl_i_i_i_i_i_i_38_c_compstr1099_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_rdcnt(ADD,31439)
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_a = {1'b0, redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_wraddr_q};
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_b = {1'b0, redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_o <= $unsigned(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_a) + $unsigned(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_b);
        end
    end
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_q = redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_o[3:0];

    // redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt(ADD,33177)
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_a = {1'b0, redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_q};
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_o <= $unsigned(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_a) + $unsigned(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_b);
        end
    end
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_q = redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_o[5:0];

    // redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_inputreg0(DELAY,33172)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl);
        end
    end

    // redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem(DUALMEM,33174)
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_ia = $unsigned(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_inputreg0_q);
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_aa = redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_q;
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_ab = redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_aa),
        .data_a(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_ab),
        .q_b(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_q = redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_iq[15:0];

    // redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_outputreg0(DELAY,33173)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_outputreg0_q <= $unsigned(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_q);
        end
    end

    // redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_inputreg0(DELAY,33178)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_inputreg0_q <= $unsigned(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_outputreg0_q);
        end
    end

    // redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr(COUNTER,33175)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_i <= $unsigned(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_q = redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_i[4:0];

    // redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem(DUALMEM,33180)
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_ia = $unsigned(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_inputreg0_q);
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_aa = redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_q;
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_ab = redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_aa),
        .data_a(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_ab),
        .q_b(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_q = redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_iq[15:0];

    // redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_outputreg0(DELAY,33179)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_outputreg0_q <= $unsigned(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_q);
        end
    end

    // redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_inputreg0(DELAY,31434)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_inputreg0_q <= $unsigned(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_split_1_outputreg0_q);
        end
    end

    // redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_wraddr(COUNTER,31437)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_wraddr_i <= $unsigned(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_wraddr_q = redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_wraddr_i[2:0];

    // redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem(DUALMEM,31436)
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_ia = $unsigned(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_inputreg0_q);
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_aa = redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_wraddr_q;
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_ab = redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_aa),
        .data_a(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_ab),
        .q_b(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_q = redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_iq[15:0];

    // redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_outputreg0(DELAY,31435)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_outputreg0_q <= $unsigned(redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_mem_q);
        end
    end

    // redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_rdcnt(ADD,29991)
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_a = {1'b0, redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_wraddr_q};
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_b = {1'b0, redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_o <= $unsigned(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_a) + $unsigned(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_b);
        end
    end
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_q = redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_o[3:0];

    // redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt(ADD,32805)
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_a = {1'b0, redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_q};
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_o <= $unsigned(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_a) + $unsigned(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_b);
        end
    end
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_q = redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_o[5:0];

    // redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_inputreg0(DELAY,32800)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl);
        end
    end

    // redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem(DUALMEM,32802)
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_ia = $unsigned(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_inputreg0_q);
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_aa = redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_q;
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_ab = redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_aa),
        .data_a(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_ab),
        .q_b(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_q = redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_iq[15:0];

    // redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_outputreg0(DELAY,32801)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_outputreg0_q <= $unsigned(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_q);
        end
    end

    // redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_inputreg0(DELAY,32806)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_inputreg0_q <= $unsigned(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_outputreg0_q);
        end
    end

    // redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr(COUNTER,32803)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_i <= $unsigned(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_q = redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_i[4:0];

    // redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem(DUALMEM,32808)
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_ia = $unsigned(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_inputreg0_q);
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_aa = redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_q;
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_ab = redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_aa),
        .data_a(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_ab),
        .q_b(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_q = redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_iq[15:0];

    // redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_outputreg0(DELAY,32807)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_outputreg0_q <= $unsigned(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_q);
        end
    end

    // redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_inputreg0(DELAY,29986)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_inputreg0_q <= $unsigned(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_split_1_outputreg0_q);
        end
    end

    // redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_wraddr(COUNTER,29989)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_wraddr_i <= $unsigned(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_wraddr_q = redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_wraddr_i[2:0];

    // redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem(DUALMEM,29988)
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_ia = $unsigned(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_inputreg0_q);
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_aa = redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_wraddr_q;
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_ab = redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_aa),
        .data_a(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_ab),
        .q_b(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_q = redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_iq[15:0];

    // redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_outputreg0(DELAY,29987)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_outputreg0_q <= $unsigned(redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_mem_q);
        end
    end

    // redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_rdcnt(ADD,29997)
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_a = {1'b0, redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_wraddr_q};
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_b = {1'b0, redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_o <= $unsigned(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_a) + $unsigned(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_b);
        end
    end
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_q = redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_o[3:0];

    // redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt(ADD,32817)
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_a = {1'b0, redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_q};
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_o <= $unsigned(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_a) + $unsigned(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_b);
        end
    end
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_q = redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_o[5:0];

    // redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_inputreg0(DELAY,32812)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl);
        end
    end

    // redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem(DUALMEM,32814)
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_ia = $unsigned(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_inputreg0_q);
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_aa = redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_q;
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_ab = redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_aa),
        .data_a(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_ab),
        .q_b(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_q = redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_iq[15:0];

    // redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_outputreg0(DELAY,32813)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_outputreg0_q <= $unsigned(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_mem_q);
        end
    end

    // redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_inputreg0(DELAY,32818)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_inputreg0_q <= $unsigned(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_outputreg0_q);
        end
    end

    // redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr(COUNTER,32815)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_i <= $unsigned(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_q = redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_i[4:0];

    // redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem(DUALMEM,32820)
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_ia = $unsigned(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_inputreg0_q);
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_aa = redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_wraddr_q;
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_ab = redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_aa),
        .data_a(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_ab),
        .q_b(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_q = redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_iq[15:0];

    // redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_outputreg0(DELAY,32819)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_outputreg0_q <= $unsigned(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_mem_q);
        end
    end

    // redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_inputreg0(DELAY,29992)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_inputreg0_q <= $unsigned(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_split_1_outputreg0_q);
        end
    end

    // redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_wraddr(COUNTER,29995)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_wraddr_i <= $unsigned(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_wraddr_q = redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_wraddr_i[2:0];

    // redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem(DUALMEM,29994)
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_ia = $unsigned(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_inputreg0_q);
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_aa = redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_wraddr_q;
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_ab = redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_aa),
        .data_a(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_ab),
        .q_b(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_q = redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_iq[15:0];

    // redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_outputreg0(DELAY,29993)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_outputreg0_q <= $unsigned(redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_mem_q);
        end
    end

    // redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_rdcnt(ADD,31433)
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_a = {1'b0, redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_wraddr_q};
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_b = {1'b0, redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_o <= $unsigned(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_a) + $unsigned(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_b);
        end
    end
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_q = redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_o[3:0];

    // redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt(ADD,33165)
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_a = {1'b0, redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_q};
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_o <= $unsigned(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_a) + $unsigned(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_b);
        end
    end
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_q = redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_o[5:0];

    // redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_inputreg0(DELAY,33160)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl);
        end
    end

    // redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem(DUALMEM,33162)
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_ia = $unsigned(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_inputreg0_q);
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_aa = redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_q;
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_ab = redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_aa),
        .data_a(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_ab),
        .q_b(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_q = redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_iq[15:0];

    // redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_outputreg0(DELAY,33161)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_outputreg0_q <= $unsigned(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_mem_q);
        end
    end

    // redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_inputreg0(DELAY,33166)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_inputreg0_q <= $unsigned(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_outputreg0_q);
        end
    end

    // redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr(COUNTER,33163)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_i <= $unsigned(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_q = redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_i[4:0];

    // redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem(DUALMEM,33168)
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_ia = $unsigned(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_inputreg0_q);
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_aa = redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_wraddr_q;
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_ab = redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_aa),
        .data_a(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_ab),
        .q_b(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_q = redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_iq[15:0];

    // redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_outputreg0(DELAY,33167)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_outputreg0_q <= $unsigned(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_mem_q);
        end
    end

    // redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_inputreg0(DELAY,31428)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_inputreg0_q <= $unsigned(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_split_1_outputreg0_q);
        end
    end

    // redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_wraddr(COUNTER,31431)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_wraddr_i <= $unsigned(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_wraddr_q = redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_wraddr_i[2:0];

    // redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem(DUALMEM,31430)
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_ia = $unsigned(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_inputreg0_q);
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_aa = redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_wraddr_q;
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_ab = redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_aa),
        .data_a(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_ab),
        .q_b(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_q = redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_iq[15:0];

    // redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_outputreg0(DELAY,31429)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_outputreg0_q <= $unsigned(redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27997)@83 + 5
    // out q@89
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100(ADD,8580)@89
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod231_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_b = $unsigned({{5{i_shl_i_i_i_i_i_i_38_c_compstr1099_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_38_c_compstr1099_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_o[33:0];

    // rightShiftStage0_uid17325_dupName_153_i_unnamed_c_compstr0_shift_x(MUX,17324)@89
    assign rightShiftStage0_uid17325_dupName_153_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17325_dupName_153_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_q or rightShiftStage0Idx1_uid17323_dupName_153_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17325_dupName_153_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17325_dupName_153_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_q;
            1'b1 : rightShiftStage0_uid17325_dupName_153_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17323_dupName_153_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17325_dupName_153_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17330_dupName_153_i_unnamed_c_compstr0_shift_x(MUX,17329)@89
    assign rightShiftStage1_uid17330_dupName_153_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17330_dupName_153_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17325_dupName_153_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17328_dupName_153_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17330_dupName_153_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17330_dupName_153_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17325_dupName_153_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17330_dupName_153_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17328_dupName_153_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17330_dupName_153_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17335_dupName_153_i_unnamed_c_compstr0_shift_x(MUX,17334)@89
    assign rightShiftStage2_uid17335_dupName_153_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17335_dupName_153_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17330_dupName_153_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17333_dupName_153_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17335_dupName_153_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17335_dupName_153_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17330_dupName_153_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17335_dupName_153_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17333_dupName_153_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17335_dupName_153_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1101_vt_select_20(BITSELECT,9893)@89
    assign i_unnamed_c_compstr1101_vt_select_20_b = rightShiftStage2_uid17335_dupName_153_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1101_vt_join(BITJOIN,9892)@89
    assign i_unnamed_c_compstr1101_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1101_vt_select_20_b};

    // i_conv_i_i_i_i_i_38_c_compstr1102_sel_x(BITSELECT,3771)@89
    assign i_conv_i_i_i_i_i_38_c_compstr1102_sel_x_b = i_unnamed_c_compstr1101_vt_join_q[15:0];

    // redist1094_i_conv_i_i_i_i_i_38_c_compstr1102_sel_x_b_1(DELAY,29322)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1094_i_conv_i_i_i_i_i_38_c_compstr1102_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_38_c_compstr1102_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17344_dupName_154_i_unnamed_c_compstr0_shift_x(BITSELECT,17343)@89
    assign rightShiftStage1Idx1Rng8_uid17344_dupName_154_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17343_dupName_154_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17346_dupName_154_i_unnamed_c_compstr0_shift_x(BITJOIN,17345)@89
    assign rightShiftStage1Idx1_uid17346_dupName_154_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17344_dupName_154_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17339_dupName_154_i_unnamed_c_compstr0_shift_x(BITSELECT,17338)@89
    assign rightShiftStage0Idx1Rng4_uid17339_dupName_154_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_q[33:4];

    // rightShiftStage0Idx1_uid17341_dupName_154_i_unnamed_c_compstr0_shift_x(BITJOIN,17340)@89
    assign rightShiftStage0Idx1_uid17341_dupName_154_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17339_dupName_154_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17343_dupName_154_i_unnamed_c_compstr0_shift_x(MUX,17342)@89
    assign rightShiftStage0_uid17343_dupName_154_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17343_dupName_154_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_q or rightShiftStage0Idx1_uid17341_dupName_154_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17343_dupName_154_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17343_dupName_154_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compstr1100_q;
            1'b1 : rightShiftStage0_uid17343_dupName_154_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17341_dupName_154_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17343_dupName_154_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17348_dupName_154_i_unnamed_c_compstr0_shift_x(MUX,17347)@89
    assign rightShiftStage1_uid17348_dupName_154_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17348_dupName_154_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17343_dupName_154_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17346_dupName_154_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17348_dupName_154_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17348_dupName_154_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17343_dupName_154_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17348_dupName_154_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17346_dupName_154_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17348_dupName_154_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1103_vt_select_21(BITSELECT,9896)@89
    assign i_unnamed_c_compstr1103_vt_select_21_b = rightShiftStage1_uid17348_dupName_154_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1103_vt_join(BITJOIN,9895)@89
    assign i_unnamed_c_compstr1103_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1103_vt_select_21_b};

    // i_unnamed_c_compstr1104_sel_x(BITSELECT,6043)@89
    assign i_unnamed_c_compstr1104_sel_x_b = i_unnamed_c_compstr1103_vt_join_q[15:0];

    // i_unnamed_c_compstr1105_BitSelect_for_a(BITSELECT,27475)@89
    assign i_unnamed_c_compstr1105_BitSelect_for_a_b = i_unnamed_c_compstr1104_sel_x_b[0:0];

    // i_unnamed_c_compstr1105_join(BITJOIN,27476)@89
    assign i_unnamed_c_compstr1105_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1105_BitSelect_for_a_b};

    // i_unnamed_c_compstr1105_vt_select_0(BITSELECT,9901)@89
    assign i_unnamed_c_compstr1105_vt_select_0_b = i_unnamed_c_compstr1105_join_q[0:0];

    // redist247_i_unnamed_c_compstr1105_vt_select_0_b_1(DELAY,28475)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist247_i_unnamed_c_compstr1105_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1105_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1105_vt_join(BITJOIN,9900)@90
    assign i_unnamed_c_compstr1105_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist247_i_unnamed_c_compstr1105_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_38_c_compstr1106(ADD,7038)@90
    assign i_add_i_i_i_i_i_i_38_c_compstr1106_a = {1'b0, i_unnamed_c_compstr1105_vt_join_q};
    assign i_add_i_i_i_i_i_i_38_c_compstr1106_b = {1'b0, redist1094_i_conv_i_i_i_i_i_38_c_compstr1102_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_38_c_compstr1106_o = $unsigned(i_add_i_i_i_i_i_i_38_c_compstr1106_a) + $unsigned(i_add_i_i_i_i_i_i_38_c_compstr1106_b);
    assign i_add_i_i_i_i_i_i_38_c_compstr1106_q = i_add_i_i_i_i_i_i_38_c_compstr1106_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_38_c_compstr1106_sel_x(BITSELECT,2232)@90
    assign bgTrunc_i_add_i_i_i_i_i_i_38_c_compstr1106_sel_x_b = i_add_i_i_i_i_i_i_38_c_compstr1106_q[15:0];

    // i_conv_i_i_i_i_i_i279_39_c_compstr1126_sel_x(BITSELECT,3900)@90
    assign i_conv_i_i_i_i_i_i279_39_c_compstr1126_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_38_c_compstr1106_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_39_c_compstr1126_vt_select_15(BITSELECT,8117)@90
    assign i_conv_i_i_i_i_i_i279_39_c_compstr1126_vt_select_15_b = i_conv_i_i_i_i_i_i279_39_c_compstr1126_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_39_c_compstr1126_vt_join(BITJOIN,8116)@90
    assign i_conv_i_i_i_i_i_i279_39_c_compstr1126_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_39_c_compstr1126_vt_select_15_b};

    // leftShiftStage0_uid26222_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x(MUX,26221)@90
    assign leftShiftStage0_uid26222_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26222_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_39_c_compstr1126_vt_join_q or leftShiftStage0Idx1_uid26220_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26222_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26222_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_39_c_compstr1126_vt_join_q;
            1'b1 : leftShiftStage0_uid26222_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26220_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26222_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26227_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x(MUX,26226)@90
    assign leftShiftStage1_uid26227_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26227_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_s or leftShiftStage0_uid26222_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26225_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26227_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26227_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q = leftShiftStage0_uid26222_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26227_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26225_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26227_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26232_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x(MUX,26231)@90
    assign leftShiftStage2_uid26232_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26232_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_s or leftShiftStage1_uid26227_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26230_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26232_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26232_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q = leftShiftStage1_uid26227_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26232_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26230_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26232_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_39_c_compstr1127_vt_select_28(BITSELECT,9601)@90
    assign i_shl_i_i_i_i_i_i_39_c_compstr1127_vt_select_28_b = leftShiftStage2_uid26232_i_shl_i_i_i_i_i_i_39_c_compstr0_shift_x_q[28:13];

    // redist323_i_shl_i_i_i_i_i_i_39_c_compstr1127_vt_select_28_b_1(DELAY,28551)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist323_i_shl_i_i_i_i_i_i_39_c_compstr1127_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_39_c_compstr1127_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_39_c_compstr1127_vt_join(BITJOIN,9600)@91
    assign i_shl_i_i_i_i_i_i_39_c_compstr1127_vt_join_q = {redist323_i_shl_i_i_i_i_i_i_39_c_compstr1127_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_rdcnt(ADD,31451)
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_a = {1'b0, redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_wraddr_q};
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_b = {1'b0, redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_o <= $unsigned(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_a) + $unsigned(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_b);
        end
    end
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_q = redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_o[3:0];

    // redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt(ADD,33201)
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_a = {1'b0, redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_q};
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_o <= $unsigned(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_a) + $unsigned(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_b);
        end
    end
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_q = redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_o[5:0];

    // redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_inputreg0(DELAY,33196)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl);
        end
    end

    // redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem(DUALMEM,33198)
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_ia = $unsigned(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_inputreg0_q);
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_aa = redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_q;
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_ab = redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_aa),
        .data_a(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_ab),
        .q_b(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_q = redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_iq[15:0];

    // redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_outputreg0(DELAY,33197)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_outputreg0_q <= $unsigned(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_q);
        end
    end

    // redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_inputreg0(DELAY,33202)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_inputreg0_q <= $unsigned(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_outputreg0_q);
        end
    end

    // redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr(COUNTER,33199)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_i <= $unsigned(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_q = redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_i[4:0];

    // redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem(DUALMEM,33204)
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_ia = $unsigned(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_inputreg0_q);
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_aa = redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_q;
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_ab = redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_aa),
        .data_a(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_ab),
        .q_b(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_q = redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_iq[15:0];

    // redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_outputreg0(DELAY,33203)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_outputreg0_q <= $unsigned(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_q);
        end
    end

    // redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_inputreg0(DELAY,31446)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_inputreg0_q <= $unsigned(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_split_1_outputreg0_q);
        end
    end

    // redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_wraddr(COUNTER,31449)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_wraddr_i <= $unsigned(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_wraddr_q = redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_wraddr_i[2:0];

    // redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem(DUALMEM,31448)
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_ia = $unsigned(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_inputreg0_q);
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_aa = redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_wraddr_q;
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_ab = redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_aa),
        .data_a(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_ab),
        .q_b(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_q = redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_iq[15:0];

    // redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_outputreg0(DELAY,31447)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_outputreg0_q <= $unsigned(redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_mem_q);
        end
    end

    // redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_rdcnt(ADD,30003)
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_a = {1'b0, redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_wraddr_q};
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_b = {1'b0, redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_o <= $unsigned(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_a) + $unsigned(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_b);
        end
    end
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_q = redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_o[3:0];

    // redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt(ADD,32829)
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_a = {1'b0, redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_q};
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_o <= $unsigned(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_a) + $unsigned(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_b);
        end
    end
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_q = redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_o[5:0];

    // redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_inputreg0(DELAY,32824)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl);
        end
    end

    // redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem(DUALMEM,32826)
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_ia = $unsigned(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_inputreg0_q);
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_aa = redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_q;
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_ab = redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_aa),
        .data_a(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_ab),
        .q_b(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_q = redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_iq[15:0];

    // redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_outputreg0(DELAY,32825)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_outputreg0_q <= $unsigned(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_q);
        end
    end

    // redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_inputreg0(DELAY,32830)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_inputreg0_q <= $unsigned(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_outputreg0_q);
        end
    end

    // redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr(COUNTER,32827)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_i <= $unsigned(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_q = redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_i[4:0];

    // redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem(DUALMEM,32832)
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_ia = $unsigned(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_inputreg0_q);
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_aa = redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_q;
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_ab = redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_aa),
        .data_a(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_ab),
        .q_b(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_q = redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_iq[15:0];

    // redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_outputreg0(DELAY,32831)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_outputreg0_q <= $unsigned(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_q);
        end
    end

    // redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_inputreg0(DELAY,29998)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_inputreg0_q <= $unsigned(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_split_1_outputreg0_q);
        end
    end

    // redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_wraddr(COUNTER,30001)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_wraddr_i <= $unsigned(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_wraddr_q = redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_wraddr_i[2:0];

    // redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem(DUALMEM,30000)
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_ia = $unsigned(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_inputreg0_q);
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_aa = redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_wraddr_q;
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_ab = redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_aa),
        .data_a(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_ab),
        .q_b(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_q = redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_iq[15:0];

    // redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_outputreg0(DELAY,29999)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_outputreg0_q <= $unsigned(redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_mem_q);
        end
    end

    // redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_rdcnt(ADD,30009)
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_a = {1'b0, redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_wraddr_q};
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_b = {1'b0, redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_o <= $unsigned(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_a) + $unsigned(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_b);
        end
    end
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_q = redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_o[3:0];

    // redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt(ADD,32841)
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_a = {1'b0, redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_q};
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_o <= $unsigned(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_a) + $unsigned(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_b);
        end
    end
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_q = redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_o[5:0];

    // redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_inputreg0(DELAY,32836)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl);
        end
    end

    // redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem(DUALMEM,32838)
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_ia = $unsigned(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_inputreg0_q);
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_aa = redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_q;
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_ab = redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_aa),
        .data_a(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_ab),
        .q_b(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_q = redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_iq[15:0];

    // redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_outputreg0(DELAY,32837)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_outputreg0_q <= $unsigned(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_mem_q);
        end
    end

    // redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_inputreg0(DELAY,32842)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_inputreg0_q <= $unsigned(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_outputreg0_q);
        end
    end

    // redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr(COUNTER,32839)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_i <= $unsigned(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_q = redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_i[4:0];

    // redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem(DUALMEM,32844)
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_ia = $unsigned(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_inputreg0_q);
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_aa = redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_wraddr_q;
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_ab = redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_aa),
        .data_a(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_ab),
        .q_b(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_q = redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_iq[15:0];

    // redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_outputreg0(DELAY,32843)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_outputreg0_q <= $unsigned(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_mem_q);
        end
    end

    // redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_inputreg0(DELAY,30004)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_inputreg0_q <= $unsigned(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_split_1_outputreg0_q);
        end
    end

    // redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_wraddr(COUNTER,30007)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_wraddr_i <= $unsigned(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_wraddr_q = redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_wraddr_i[2:0];

    // redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem(DUALMEM,30006)
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_ia = $unsigned(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_inputreg0_q);
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_aa = redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_wraddr_q;
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_ab = redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_aa),
        .data_a(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_ab),
        .q_b(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_q = redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_iq[15:0];

    // redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_outputreg0(DELAY,30005)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_outputreg0_q <= $unsigned(redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_mem_q);
        end
    end

    // redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_rdcnt(ADD,31445)
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_a = {1'b0, redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_wraddr_q};
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_b = {1'b0, redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_o <= $unsigned(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_a) + $unsigned(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_b);
        end
    end
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_q = redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_o[3:0];

    // redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt(ADD,33189)
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_a = {1'b0, redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_q};
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_o <= $unsigned(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_a) + $unsigned(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_b);
        end
    end
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_q = redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_o[5:0];

    // redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_inputreg0(DELAY,33184)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl);
        end
    end

    // redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem(DUALMEM,33186)
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_ia = $unsigned(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_inputreg0_q);
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_aa = redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_q;
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_ab = redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_aa),
        .data_a(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_ab),
        .q_b(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_q = redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_iq[15:0];

    // redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_outputreg0(DELAY,33185)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_outputreg0_q <= $unsigned(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_mem_q);
        end
    end

    // redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_inputreg0(DELAY,33190)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_inputreg0_q <= $unsigned(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_outputreg0_q);
        end
    end

    // redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr(COUNTER,33187)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_i <= $unsigned(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_q = redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_i[4:0];

    // redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem(DUALMEM,33192)
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_ia = $unsigned(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_inputreg0_q);
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_aa = redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_wraddr_q;
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_ab = redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_aa),
        .data_a(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_ab),
        .q_b(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_q = redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_iq[15:0];

    // redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_outputreg0(DELAY,33191)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_outputreg0_q <= $unsigned(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_mem_q);
        end
    end

    // redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_inputreg0(DELAY,31440)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_inputreg0_q <= $unsigned(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_split_1_outputreg0_q);
        end
    end

    // redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_wraddr(COUNTER,31443)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_wraddr_i <= $unsigned(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_wraddr_q = redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_wraddr_i[2:0];

    // redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem(DUALMEM,31442)
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_ia = $unsigned(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_inputreg0_q);
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_aa = redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_wraddr_q;
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_ab = redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_aa),
        .data_a(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_ab),
        .q_b(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_q = redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_iq[15:0];

    // redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_outputreg0(DELAY,31441)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_outputreg0_q <= $unsigned(redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27998)@85 + 5
    // out q@91
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128(ADD,8581)@91
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod236_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_b = $unsigned({{5{i_shl_i_i_i_i_i_i_39_c_compstr1127_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_39_c_compstr1127_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_o[33:0];

    // rightShiftStage0_uid17387_dupName_157_i_unnamed_c_compstr0_shift_x(MUX,17386)@91
    assign rightShiftStage0_uid17387_dupName_157_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17387_dupName_157_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_q or rightShiftStage0Idx1_uid17385_dupName_157_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17387_dupName_157_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17387_dupName_157_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_q;
            1'b1 : rightShiftStage0_uid17387_dupName_157_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17385_dupName_157_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17387_dupName_157_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17392_dupName_157_i_unnamed_c_compstr0_shift_x(MUX,17391)@91
    assign rightShiftStage1_uid17392_dupName_157_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17392_dupName_157_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17387_dupName_157_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17390_dupName_157_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17392_dupName_157_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17392_dupName_157_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17387_dupName_157_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17392_dupName_157_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17390_dupName_157_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17392_dupName_157_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17397_dupName_157_i_unnamed_c_compstr0_shift_x(MUX,17396)@91
    assign rightShiftStage2_uid17397_dupName_157_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17397_dupName_157_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17392_dupName_157_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17395_dupName_157_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17397_dupName_157_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17397_dupName_157_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17392_dupName_157_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17397_dupName_157_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17395_dupName_157_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17397_dupName_157_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1129_vt_select_20(BITSELECT,9915)@91
    assign i_unnamed_c_compstr1129_vt_select_20_b = rightShiftStage2_uid17397_dupName_157_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1129_vt_join(BITJOIN,9914)@91
    assign i_unnamed_c_compstr1129_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1129_vt_select_20_b};

    // i_conv_i_i_i_i_i_39_c_compstr1130_sel_x(BITSELECT,3772)@91
    assign i_conv_i_i_i_i_i_39_c_compstr1130_sel_x_b = i_unnamed_c_compstr1129_vt_join_q[15:0];

    // redist1093_i_conv_i_i_i_i_i_39_c_compstr1130_sel_x_b_1(DELAY,29321)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1093_i_conv_i_i_i_i_i_39_c_compstr1130_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_39_c_compstr1130_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17406_dupName_158_i_unnamed_c_compstr0_shift_x(BITSELECT,17405)@91
    assign rightShiftStage1Idx1Rng8_uid17406_dupName_158_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17405_dupName_158_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17408_dupName_158_i_unnamed_c_compstr0_shift_x(BITJOIN,17407)@91
    assign rightShiftStage1Idx1_uid17408_dupName_158_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17406_dupName_158_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17401_dupName_158_i_unnamed_c_compstr0_shift_x(BITSELECT,17400)@91
    assign rightShiftStage0Idx1Rng4_uid17401_dupName_158_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_q[33:4];

    // rightShiftStage0Idx1_uid17403_dupName_158_i_unnamed_c_compstr0_shift_x(BITJOIN,17402)@91
    assign rightShiftStage0Idx1_uid17403_dupName_158_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17401_dupName_158_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17405_dupName_158_i_unnamed_c_compstr0_shift_x(MUX,17404)@91
    assign rightShiftStage0_uid17405_dupName_158_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17405_dupName_158_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_q or rightShiftStage0Idx1_uid17403_dupName_158_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17405_dupName_158_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17405_dupName_158_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compstr1128_q;
            1'b1 : rightShiftStage0_uid17405_dupName_158_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17403_dupName_158_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17405_dupName_158_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17410_dupName_158_i_unnamed_c_compstr0_shift_x(MUX,17409)@91
    assign rightShiftStage1_uid17410_dupName_158_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17410_dupName_158_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17405_dupName_158_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17408_dupName_158_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17410_dupName_158_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17410_dupName_158_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17405_dupName_158_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17410_dupName_158_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17408_dupName_158_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17410_dupName_158_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1131_vt_select_21(BITSELECT,9918)@91
    assign i_unnamed_c_compstr1131_vt_select_21_b = rightShiftStage1_uid17410_dupName_158_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1131_vt_join(BITJOIN,9917)@91
    assign i_unnamed_c_compstr1131_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1131_vt_select_21_b};

    // i_unnamed_c_compstr1132_sel_x(BITSELECT,6045)@91
    assign i_unnamed_c_compstr1132_sel_x_b = i_unnamed_c_compstr1131_vt_join_q[15:0];

    // i_unnamed_c_compstr1133_BitSelect_for_a(BITSELECT,27479)@91
    assign i_unnamed_c_compstr1133_BitSelect_for_a_b = i_unnamed_c_compstr1132_sel_x_b[0:0];

    // i_unnamed_c_compstr1133_join(BITJOIN,27480)@91
    assign i_unnamed_c_compstr1133_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1133_BitSelect_for_a_b};

    // i_unnamed_c_compstr1133_vt_select_0(BITSELECT,9923)@91
    assign i_unnamed_c_compstr1133_vt_select_0_b = i_unnamed_c_compstr1133_join_q[0:0];

    // redist245_i_unnamed_c_compstr1133_vt_select_0_b_1(DELAY,28473)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist245_i_unnamed_c_compstr1133_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1133_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1133_vt_join(BITJOIN,9922)@92
    assign i_unnamed_c_compstr1133_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist245_i_unnamed_c_compstr1133_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_39_c_compstr1134(ADD,7039)@92
    assign i_add_i_i_i_i_i_i_39_c_compstr1134_a = {1'b0, i_unnamed_c_compstr1133_vt_join_q};
    assign i_add_i_i_i_i_i_i_39_c_compstr1134_b = {1'b0, redist1093_i_conv_i_i_i_i_i_39_c_compstr1130_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_39_c_compstr1134_o = $unsigned(i_add_i_i_i_i_i_i_39_c_compstr1134_a) + $unsigned(i_add_i_i_i_i_i_i_39_c_compstr1134_b);
    assign i_add_i_i_i_i_i_i_39_c_compstr1134_q = i_add_i_i_i_i_i_i_39_c_compstr1134_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_39_c_compstr1134_sel_x(BITSELECT,2233)@92
    assign bgTrunc_i_add_i_i_i_i_i_i_39_c_compstr1134_sel_x_b = i_add_i_i_i_i_i_i_39_c_compstr1134_q[15:0];

    // i_conv_i_i_i_i_i_i279_40_c_compstr1154_sel_x(BITSELECT,3902)@92
    assign i_conv_i_i_i_i_i_i279_40_c_compstr1154_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_39_c_compstr1134_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_40_c_compstr1154_vt_select_15(BITSELECT,8125)@92
    assign i_conv_i_i_i_i_i_i279_40_c_compstr1154_vt_select_15_b = i_conv_i_i_i_i_i_i279_40_c_compstr1154_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_40_c_compstr1154_vt_join(BITJOIN,8124)@92
    assign i_conv_i_i_i_i_i_i279_40_c_compstr1154_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_40_c_compstr1154_vt_select_15_b};

    // leftShiftStage0_uid26258_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x(MUX,26257)@92
    assign leftShiftStage0_uid26258_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26258_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_40_c_compstr1154_vt_join_q or leftShiftStage0Idx1_uid26256_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26258_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26258_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_40_c_compstr1154_vt_join_q;
            1'b1 : leftShiftStage0_uid26258_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26256_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26258_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26263_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x(MUX,26262)@92
    assign leftShiftStage1_uid26263_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26263_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_s or leftShiftStage0_uid26258_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26261_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26263_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26263_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q = leftShiftStage0_uid26258_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26263_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26261_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26263_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26268_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x(MUX,26267)@92
    assign leftShiftStage2_uid26268_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26268_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_s or leftShiftStage1_uid26263_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26266_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26268_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26268_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q = leftShiftStage1_uid26263_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26268_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26266_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26268_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_40_c_compstr1155_vt_select_28(BITSELECT,9607)@92
    assign i_shl_i_i_i_i_i_i_40_c_compstr1155_vt_select_28_b = leftShiftStage2_uid26268_i_shl_i_i_i_i_i_i_40_c_compstr0_shift_x_q[28:13];

    // redist321_i_shl_i_i_i_i_i_i_40_c_compstr1155_vt_select_28_b_1(DELAY,28549)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist321_i_shl_i_i_i_i_i_i_40_c_compstr1155_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_40_c_compstr1155_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_40_c_compstr1155_vt_join(BITJOIN,9606)@93
    assign i_shl_i_i_i_i_i_i_40_c_compstr1155_vt_join_q = {redist321_i_shl_i_i_i_i_i_i_40_c_compstr1155_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_rdcnt(ADD,31463)
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_a = {1'b0, redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_wraddr_q};
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_b = {1'b0, redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_o <= $unsigned(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_a) + $unsigned(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_b);
        end
    end
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_q = redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_o[4:0];

    // redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt(ADD,33225)
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_a = {1'b0, redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_q};
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_o <= $unsigned(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_a) + $unsigned(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_b);
        end
    end
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_q = redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_o[5:0];

    // redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_inputreg0(DELAY,33220)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl);
        end
    end

    // redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem(DUALMEM,33222)
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_ia = $unsigned(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_inputreg0_q);
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_aa = redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_q;
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_ab = redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_aa),
        .data_a(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_ab),
        .q_b(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_q = redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_iq[15:0];

    // redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_outputreg0(DELAY,33221)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_outputreg0_q <= $unsigned(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_q);
        end
    end

    // redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_inputreg0(DELAY,33226)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_inputreg0_q <= $unsigned(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_outputreg0_q);
        end
    end

    // redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr(COUNTER,33223)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_i <= $unsigned(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_q = redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_i[4:0];

    // redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem(DUALMEM,33228)
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_ia = $unsigned(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_inputreg0_q);
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_aa = redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_q;
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_ab = redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_aa),
        .data_a(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_ab),
        .q_b(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_q = redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_iq[15:0];

    // redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_outputreg0(DELAY,33227)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_outputreg0_q <= $unsigned(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_q);
        end
    end

    // redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_inputreg0(DELAY,31458)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_inputreg0_q <= $unsigned(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_split_1_outputreg0_q);
        end
    end

    // redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_wraddr(COUNTER,31461)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_wraddr_i <= $unsigned(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_wraddr_q = redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_wraddr_i[3:0];

    // redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem(DUALMEM,31460)
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_ia = $unsigned(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_inputreg0_q);
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_aa = redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_wraddr_q;
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_ab = redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_aa),
        .data_a(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_ab),
        .q_b(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_q = redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_iq[15:0];

    // redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_outputreg0(DELAY,31459)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_outputreg0_q <= $unsigned(redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_mem_q);
        end
    end

    // redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_rdcnt(ADD,30015)
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_a = {1'b0, redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_wraddr_q};
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_b = {1'b0, redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_o <= $unsigned(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_a) + $unsigned(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_b);
        end
    end
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_q = redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_o[4:0];

    // redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt(ADD,32853)
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_a = {1'b0, redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_q};
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_o <= $unsigned(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_a) + $unsigned(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_b);
        end
    end
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_q = redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_o[5:0];

    // redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_inputreg0(DELAY,32848)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl);
        end
    end

    // redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem(DUALMEM,32850)
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_ia = $unsigned(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_inputreg0_q);
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_aa = redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_q;
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_ab = redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_aa),
        .data_a(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_ab),
        .q_b(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_q = redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_iq[15:0];

    // redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_outputreg0(DELAY,32849)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_outputreg0_q <= $unsigned(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_q);
        end
    end

    // redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_inputreg0(DELAY,32854)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_inputreg0_q <= $unsigned(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_outputreg0_q);
        end
    end

    // redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr(COUNTER,32851)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_i <= $unsigned(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_q = redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_i[4:0];

    // redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem(DUALMEM,32856)
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_ia = $unsigned(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_inputreg0_q);
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_aa = redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_q;
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_ab = redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_aa),
        .data_a(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_ab),
        .q_b(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_q = redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_iq[15:0];

    // redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_outputreg0(DELAY,32855)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_outputreg0_q <= $unsigned(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_q);
        end
    end

    // redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_inputreg0(DELAY,30010)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_inputreg0_q <= $unsigned(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_split_1_outputreg0_q);
        end
    end

    // redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_wraddr(COUNTER,30013)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_wraddr_i <= $unsigned(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_wraddr_q = redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_wraddr_i[3:0];

    // redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem(DUALMEM,30012)
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_ia = $unsigned(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_inputreg0_q);
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_aa = redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_wraddr_q;
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_ab = redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_aa),
        .data_a(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_ab),
        .q_b(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_q = redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_iq[15:0];

    // redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_outputreg0(DELAY,30011)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_outputreg0_q <= $unsigned(redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_mem_q);
        end
    end

    // redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_rdcnt(ADD,30021)
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_a = {1'b0, redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_wraddr_q};
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_b = {1'b0, redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_o <= $unsigned(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_a) + $unsigned(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_b);
        end
    end
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_q = redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_o[4:0];

    // redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt(ADD,32865)
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_a = {1'b0, redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_q};
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_o <= $unsigned(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_a) + $unsigned(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_b);
        end
    end
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_q = redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_o[5:0];

    // redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_inputreg0(DELAY,32860)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl);
        end
    end

    // redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem(DUALMEM,32862)
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_ia = $unsigned(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_inputreg0_q);
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_aa = redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_q;
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_ab = redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_aa),
        .data_a(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_ab),
        .q_b(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_q = redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_iq[15:0];

    // redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_outputreg0(DELAY,32861)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_outputreg0_q <= $unsigned(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_mem_q);
        end
    end

    // redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_inputreg0(DELAY,32866)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_inputreg0_q <= $unsigned(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_outputreg0_q);
        end
    end

    // redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr(COUNTER,32863)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_i <= $unsigned(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_q = redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_i[4:0];

    // redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem(DUALMEM,32868)
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_ia = $unsigned(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_inputreg0_q);
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_aa = redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_wraddr_q;
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_ab = redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_aa),
        .data_a(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_ab),
        .q_b(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_q = redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_iq[15:0];

    // redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_outputreg0(DELAY,32867)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_outputreg0_q <= $unsigned(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_mem_q);
        end
    end

    // redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_inputreg0(DELAY,30016)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_inputreg0_q <= $unsigned(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_split_1_outputreg0_q);
        end
    end

    // redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_wraddr(COUNTER,30019)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_wraddr_i <= $unsigned(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_wraddr_q = redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_wraddr_i[3:0];

    // redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem(DUALMEM,30018)
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_ia = $unsigned(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_inputreg0_q);
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_aa = redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_wraddr_q;
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_ab = redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_aa),
        .data_a(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_ab),
        .q_b(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_q = redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_iq[15:0];

    // redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_outputreg0(DELAY,30017)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_outputreg0_q <= $unsigned(redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_mem_q);
        end
    end

    // redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_rdcnt(ADD,31457)
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_a = {1'b0, redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_wraddr_q};
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_b = {1'b0, redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_o <= $unsigned(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_a) + $unsigned(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_b);
        end
    end
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_q = redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_o[4:0];

    // redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt(ADD,33213)
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_a = {1'b0, redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_q};
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_b = {1'b0, redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_o <= $unsigned(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_a) + $unsigned(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_b);
        end
    end
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_q = redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_o[5:0];

    // redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_inputreg0(DELAY,33208)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl);
        end
    end

    // redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem(DUALMEM,33210)
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_ia = $unsigned(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_inputreg0_q);
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_aa = redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_q;
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_ab = redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_aa),
        .data_a(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_ab),
        .q_b(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_q = redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_iq[15:0];

    // redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_outputreg0(DELAY,33209)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_outputreg0_q <= $unsigned(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_mem_q);
        end
    end

    // redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_inputreg0(DELAY,33214)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_inputreg0_q <= $unsigned(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_outputreg0_q);
        end
    end

    // redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr(COUNTER,33211)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_i <= $unsigned(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_q = redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_i[4:0];

    // redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem(DUALMEM,33216)
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_ia = $unsigned(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_inputreg0_q);
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_aa = redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_wraddr_q;
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_ab = redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_aa),
        .data_a(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_ab),
        .q_b(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_q = redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_iq[15:0];

    // redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_outputreg0(DELAY,33215)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_outputreg0_q <= $unsigned(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_mem_q);
        end
    end

    // redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_inputreg0(DELAY,31452)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_inputreg0_q <= $unsigned(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_split_1_outputreg0_q);
        end
    end

    // redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_wraddr(COUNTER,31455)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_wraddr_i <= $unsigned(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_wraddr_q = redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_wraddr_i[3:0];

    // redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem(DUALMEM,31454)
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_ia = $unsigned(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_inputreg0_q);
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_aa = redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_wraddr_q;
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_ab = redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_aa),
        .data_a(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_ab),
        .q_b(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_q = redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_iq[15:0];

    // redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_outputreg0(DELAY,31453)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_outputreg0_q <= $unsigned(redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,27999)@87 + 5
    // out q@93
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156(ADD,8583)@93
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod241_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_b = $unsigned({{5{i_shl_i_i_i_i_i_i_40_c_compstr1155_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_40_c_compstr1155_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_o[33:0];

    // rightShiftStage0_uid17449_dupName_161_i_unnamed_c_compstr0_shift_x(MUX,17448)@93
    assign rightShiftStage0_uid17449_dupName_161_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17449_dupName_161_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_q or rightShiftStage0Idx1_uid17447_dupName_161_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17449_dupName_161_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17449_dupName_161_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_q;
            1'b1 : rightShiftStage0_uid17449_dupName_161_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17447_dupName_161_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17449_dupName_161_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17454_dupName_161_i_unnamed_c_compstr0_shift_x(MUX,17453)@93
    assign rightShiftStage1_uid17454_dupName_161_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17454_dupName_161_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17449_dupName_161_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17452_dupName_161_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17454_dupName_161_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17454_dupName_161_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17449_dupName_161_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17454_dupName_161_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17452_dupName_161_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17454_dupName_161_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17459_dupName_161_i_unnamed_c_compstr0_shift_x(MUX,17458)@93
    assign rightShiftStage2_uid17459_dupName_161_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17459_dupName_161_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17454_dupName_161_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17457_dupName_161_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17459_dupName_161_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17459_dupName_161_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17454_dupName_161_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17459_dupName_161_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17457_dupName_161_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17459_dupName_161_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1157_vt_select_20(BITSELECT,9937)@93
    assign i_unnamed_c_compstr1157_vt_select_20_b = rightShiftStage2_uid17459_dupName_161_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1157_vt_join(BITJOIN,9936)@93
    assign i_unnamed_c_compstr1157_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1157_vt_select_20_b};

    // i_conv_i_i_i_i_i_40_c_compstr1158_sel_x(BITSELECT,3774)@93
    assign i_conv_i_i_i_i_i_40_c_compstr1158_sel_x_b = i_unnamed_c_compstr1157_vt_join_q[15:0];

    // redist1091_i_conv_i_i_i_i_i_40_c_compstr1158_sel_x_b_1(DELAY,29319)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1091_i_conv_i_i_i_i_i_40_c_compstr1158_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_40_c_compstr1158_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17468_dupName_162_i_unnamed_c_compstr0_shift_x(BITSELECT,17467)@93
    assign rightShiftStage1Idx1Rng8_uid17468_dupName_162_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17467_dupName_162_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17470_dupName_162_i_unnamed_c_compstr0_shift_x(BITJOIN,17469)@93
    assign rightShiftStage1Idx1_uid17470_dupName_162_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17468_dupName_162_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17463_dupName_162_i_unnamed_c_compstr0_shift_x(BITSELECT,17462)@93
    assign rightShiftStage0Idx1Rng4_uid17463_dupName_162_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_q[33:4];

    // rightShiftStage0Idx1_uid17465_dupName_162_i_unnamed_c_compstr0_shift_x(BITJOIN,17464)@93
    assign rightShiftStage0Idx1_uid17465_dupName_162_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17463_dupName_162_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17467_dupName_162_i_unnamed_c_compstr0_shift_x(MUX,17466)@93
    assign rightShiftStage0_uid17467_dupName_162_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17467_dupName_162_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_q or rightShiftStage0Idx1_uid17465_dupName_162_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17467_dupName_162_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17467_dupName_162_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compstr1156_q;
            1'b1 : rightShiftStage0_uid17467_dupName_162_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17465_dupName_162_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17467_dupName_162_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17472_dupName_162_i_unnamed_c_compstr0_shift_x(MUX,17471)@93
    assign rightShiftStage1_uid17472_dupName_162_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17472_dupName_162_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17467_dupName_162_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17470_dupName_162_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17472_dupName_162_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17472_dupName_162_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17467_dupName_162_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17472_dupName_162_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17470_dupName_162_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17472_dupName_162_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1159_vt_select_21(BITSELECT,9940)@93
    assign i_unnamed_c_compstr1159_vt_select_21_b = rightShiftStage1_uid17472_dupName_162_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1159_vt_join(BITJOIN,9939)@93
    assign i_unnamed_c_compstr1159_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1159_vt_select_21_b};

    // i_unnamed_c_compstr1160_sel_x(BITSELECT,6047)@93
    assign i_unnamed_c_compstr1160_sel_x_b = i_unnamed_c_compstr1159_vt_join_q[15:0];

    // i_unnamed_c_compstr1161_BitSelect_for_a(BITSELECT,27483)@93
    assign i_unnamed_c_compstr1161_BitSelect_for_a_b = i_unnamed_c_compstr1160_sel_x_b[0:0];

    // i_unnamed_c_compstr1161_join(BITJOIN,27484)@93
    assign i_unnamed_c_compstr1161_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1161_BitSelect_for_a_b};

    // i_unnamed_c_compstr1161_vt_select_0(BITSELECT,9945)@93
    assign i_unnamed_c_compstr1161_vt_select_0_b = i_unnamed_c_compstr1161_join_q[0:0];

    // redist243_i_unnamed_c_compstr1161_vt_select_0_b_1(DELAY,28471)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist243_i_unnamed_c_compstr1161_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1161_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1161_vt_join(BITJOIN,9944)@94
    assign i_unnamed_c_compstr1161_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist243_i_unnamed_c_compstr1161_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_40_c_compstr1162(ADD,7041)@94
    assign i_add_i_i_i_i_i_i_40_c_compstr1162_a = {1'b0, i_unnamed_c_compstr1161_vt_join_q};
    assign i_add_i_i_i_i_i_i_40_c_compstr1162_b = {1'b0, redist1091_i_conv_i_i_i_i_i_40_c_compstr1158_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_40_c_compstr1162_o = $unsigned(i_add_i_i_i_i_i_i_40_c_compstr1162_a) + $unsigned(i_add_i_i_i_i_i_i_40_c_compstr1162_b);
    assign i_add_i_i_i_i_i_i_40_c_compstr1162_q = i_add_i_i_i_i_i_i_40_c_compstr1162_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_40_c_compstr1162_sel_x(BITSELECT,2235)@94
    assign bgTrunc_i_add_i_i_i_i_i_i_40_c_compstr1162_sel_x_b = i_add_i_i_i_i_i_i_40_c_compstr1162_q[15:0];

    // i_conv_i_i_i_i_i_i279_41_c_compstr1182_sel_x(BITSELECT,3903)@94
    assign i_conv_i_i_i_i_i_i279_41_c_compstr1182_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_40_c_compstr1162_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_41_c_compstr1182_vt_select_15(BITSELECT,8129)@94
    assign i_conv_i_i_i_i_i_i279_41_c_compstr1182_vt_select_15_b = i_conv_i_i_i_i_i_i279_41_c_compstr1182_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_41_c_compstr1182_vt_join(BITJOIN,8128)@94
    assign i_conv_i_i_i_i_i_i279_41_c_compstr1182_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_41_c_compstr1182_vt_select_15_b};

    // leftShiftStage0_uid26276_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x(MUX,26275)@94
    assign leftShiftStage0_uid26276_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26276_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_41_c_compstr1182_vt_join_q or leftShiftStage0Idx1_uid26274_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26276_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26276_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_41_c_compstr1182_vt_join_q;
            1'b1 : leftShiftStage0_uid26276_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26274_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26276_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26281_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x(MUX,26280)@94
    assign leftShiftStage1_uid26281_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26281_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_s or leftShiftStage0_uid26276_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26279_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26281_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26281_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q = leftShiftStage0_uid26276_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26281_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26279_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26281_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26286_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x(MUX,26285)@94
    assign leftShiftStage2_uid26286_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26286_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_s or leftShiftStage1_uid26281_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26284_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26286_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26286_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q = leftShiftStage1_uid26281_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26286_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26284_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26286_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_41_c_compstr1183_vt_select_28(BITSELECT,9610)@94
    assign i_shl_i_i_i_i_i_i_41_c_compstr1183_vt_select_28_b = leftShiftStage2_uid26286_i_shl_i_i_i_i_i_i_41_c_compstr0_shift_x_q[28:13];

    // redist320_i_shl_i_i_i_i_i_i_41_c_compstr1183_vt_select_28_b_1(DELAY,28548)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist320_i_shl_i_i_i_i_i_i_41_c_compstr1183_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_41_c_compstr1183_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_41_c_compstr1183_vt_join(BITJOIN,9609)@95
    assign i_shl_i_i_i_i_i_i_41_c_compstr1183_vt_join_q = {redist320_i_shl_i_i_i_i_i_i_41_c_compstr1183_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_rdcnt(ADD,31479)
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_a = {1'b0, redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_wraddr_q};
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_b = {1'b0, redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_o <= $unsigned(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_a) + $unsigned(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_b);
        end
    end
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_q = redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_o[4:0];

    // redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_offset(CONSTANT,33234)
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_offset_q = $unsigned(5'b00010);

    // redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt(ADD,33259)
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_a = {1'b0, redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_q};
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_b = {1'b0, redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_o <= $unsigned(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_a) + $unsigned(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_b);
        end
    end
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_q = redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_o[5:0];

    // redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_inputreg0(DELAY,31472)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl);
        end
    end

    // redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem(DUALMEM,33256)
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_ia = $unsigned(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_inputreg0_q);
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_aa = redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_q;
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_ab = redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_aa),
        .data_a(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_ab),
        .q_b(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_q = redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_iq[15:0];

    // redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr(COUNTER,33257)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_i <= $unsigned(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_q = redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_i[4:0];

    // redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem(DUALMEM,33260)
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_ia = $unsigned(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_q);
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_aa = redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_q;
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_ab = redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_aa),
        .data_a(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_ab),
        .q_b(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_q = redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_iq[15:0];

    // redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_wraddr(COUNTER,31477)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_wraddr_i <= $unsigned(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_wraddr_q = redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_wraddr_i[3:0];

    // redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem(DUALMEM,31476)
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_ia = $unsigned(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_q);
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_aa = redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_wraddr_q;
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_ab = redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_aa),
        .data_a(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_ab),
        .q_b(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_q = redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_iq[15:0];

    // redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_outputreg0(DELAY,31473)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_outputreg0_q <= $unsigned(redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_mem_q);
        end
    end

    // redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_rdcnt(ADD,30029)
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_a = {1'b0, redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_wraddr_q};
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_b = {1'b0, redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_o <= $unsigned(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_a) + $unsigned(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_b);
        end
    end
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_q = redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_o[4:0];

    // redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt(ADD,33235)
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_a = {1'b0, redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_q};
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_b = {1'b0, redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_o <= $unsigned(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_a) + $unsigned(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_b);
        end
    end
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_q = redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_o[5:0];

    // redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_inputreg0(DELAY,30022)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl);
        end
    end

    // redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem(DUALMEM,33232)
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_ia = $unsigned(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_inputreg0_q);
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_aa = redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_q;
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_ab = redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_aa),
        .data_a(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_ab),
        .q_b(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_q = redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_iq[15:0];

    // redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr(COUNTER,33233)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_i <= $unsigned(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_q = redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_i[4:0];

    // redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem(DUALMEM,33236)
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_ia = $unsigned(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_q);
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_aa = redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_q;
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_ab = redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_aa),
        .data_a(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_ab),
        .q_b(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_q = redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_iq[15:0];

    // redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_wraddr(COUNTER,30027)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_wraddr_i <= $unsigned(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_wraddr_q = redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_wraddr_i[3:0];

    // redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem(DUALMEM,30026)
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_ia = $unsigned(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_q);
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_aa = redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_wraddr_q;
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_ab = redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_aa),
        .data_a(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_ab),
        .q_b(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_q = redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_iq[15:0];

    // redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_outputreg0(DELAY,30023)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_outputreg0_q <= $unsigned(redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_mem_q);
        end
    end

    // redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_rdcnt(ADD,30037)
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_a = {1'b0, redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_wraddr_q};
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_b = {1'b0, redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_o <= $unsigned(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_a) + $unsigned(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_b);
        end
    end
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_q = redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_o[4:0];

    // redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt(ADD,33243)
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_a = {1'b0, redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_q};
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_b = {1'b0, redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_o <= $unsigned(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_a) + $unsigned(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_b);
        end
    end
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_q = redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_o[5:0];

    // redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_inputreg0(DELAY,30030)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl);
        end
    end

    // redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem(DUALMEM,33240)
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_ia = $unsigned(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_inputreg0_q);
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_aa = redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_q;
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_ab = redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_aa),
        .data_a(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_ab),
        .q_b(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_q = redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_iq[15:0];

    // redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr(COUNTER,33241)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_i <= $unsigned(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_q = redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_i[4:0];

    // redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem(DUALMEM,33244)
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_ia = $unsigned(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_mem_q);
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_aa = redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_wraddr_q;
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_ab = redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_aa),
        .data_a(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_ab),
        .q_b(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_q = redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_iq[15:0];

    // redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_wraddr(COUNTER,30035)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_wraddr_i <= $unsigned(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_wraddr_q = redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_wraddr_i[3:0];

    // redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem(DUALMEM,30034)
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_ia = $unsigned(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_split_1_mem_q);
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_aa = redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_wraddr_q;
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_ab = redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_aa),
        .data_a(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_ab),
        .q_b(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_q = redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_iq[15:0];

    // redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_outputreg0(DELAY,30031)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_outputreg0_q <= $unsigned(redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_mem_q);
        end
    end

    // redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_rdcnt(ADD,31471)
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_a = {1'b0, redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_wraddr_q};
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_b = {1'b0, redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_o <= $unsigned(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_a) + $unsigned(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_b);
        end
    end
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_q = redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_o[4:0];

    // redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt(ADD,33251)
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_a = {1'b0, redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_q};
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_b = {1'b0, redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_split_0_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_o <= $unsigned(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_a) + $unsigned(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_b);
        end
    end
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_q = redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_o[5:0];

    // redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_inputreg0(DELAY,31464)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl);
        end
    end

    // redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem(DUALMEM,33248)
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_ia = $unsigned(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_inputreg0_q);
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_aa = redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_q;
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_ab = redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_aa),
        .data_a(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_ab),
        .q_b(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_q = redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_iq[15:0];

    // redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr(COUNTER,33249)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_i <= $unsigned(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_q = redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_i[4:0];

    // redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem(DUALMEM,33252)
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_ia = $unsigned(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_mem_q);
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_aa = redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_wraddr_q;
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_ab = redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_aa),
        .data_a(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_ab),
        .q_b(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_q = redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_iq[15:0];

    // redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_wraddr(COUNTER,31469)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_wraddr_i <= $unsigned(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_wraddr_q = redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_wraddr_i[3:0];

    // redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem(DUALMEM,31468)
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_ia = $unsigned(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_split_1_mem_q);
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_aa = redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_wraddr_q;
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_ab = redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_aa),
        .data_a(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_ab),
        .q_b(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_q = redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_iq[15:0];

    // redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_outputreg0(DELAY,31465)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_outputreg0_q <= $unsigned(redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28000)@89 + 5
    // out q@95
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184(ADD,8584)@95
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod246_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_b = $unsigned({{5{i_shl_i_i_i_i_i_i_41_c_compstr1183_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_41_c_compstr1183_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_o[33:0];

    // rightShiftStage0_uid17511_dupName_165_i_unnamed_c_compstr0_shift_x(MUX,17510)@95
    assign rightShiftStage0_uid17511_dupName_165_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17511_dupName_165_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_q or rightShiftStage0Idx1_uid17509_dupName_165_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17511_dupName_165_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17511_dupName_165_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_q;
            1'b1 : rightShiftStage0_uid17511_dupName_165_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17509_dupName_165_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17511_dupName_165_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17516_dupName_165_i_unnamed_c_compstr0_shift_x(MUX,17515)@95
    assign rightShiftStage1_uid17516_dupName_165_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17516_dupName_165_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17511_dupName_165_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17514_dupName_165_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17516_dupName_165_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17516_dupName_165_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17511_dupName_165_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17516_dupName_165_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17514_dupName_165_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17516_dupName_165_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17521_dupName_165_i_unnamed_c_compstr0_shift_x(MUX,17520)@95
    assign rightShiftStage2_uid17521_dupName_165_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17521_dupName_165_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17516_dupName_165_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17519_dupName_165_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17521_dupName_165_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17521_dupName_165_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17516_dupName_165_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17521_dupName_165_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17519_dupName_165_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17521_dupName_165_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1185_vt_select_20(BITSELECT,9959)@95
    assign i_unnamed_c_compstr1185_vt_select_20_b = rightShiftStage2_uid17521_dupName_165_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1185_vt_join(BITJOIN,9958)@95
    assign i_unnamed_c_compstr1185_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1185_vt_select_20_b};

    // i_conv_i_i_i_i_i_41_c_compstr1186_sel_x(BITSELECT,3775)@95
    assign i_conv_i_i_i_i_i_41_c_compstr1186_sel_x_b = i_unnamed_c_compstr1185_vt_join_q[15:0];

    // redist1090_i_conv_i_i_i_i_i_41_c_compstr1186_sel_x_b_1(DELAY,29318)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1090_i_conv_i_i_i_i_i_41_c_compstr1186_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_41_c_compstr1186_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17530_dupName_166_i_unnamed_c_compstr0_shift_x(BITSELECT,17529)@95
    assign rightShiftStage1Idx1Rng8_uid17530_dupName_166_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17529_dupName_166_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17532_dupName_166_i_unnamed_c_compstr0_shift_x(BITJOIN,17531)@95
    assign rightShiftStage1Idx1_uid17532_dupName_166_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17530_dupName_166_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17525_dupName_166_i_unnamed_c_compstr0_shift_x(BITSELECT,17524)@95
    assign rightShiftStage0Idx1Rng4_uid17525_dupName_166_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_q[33:4];

    // rightShiftStage0Idx1_uid17527_dupName_166_i_unnamed_c_compstr0_shift_x(BITJOIN,17526)@95
    assign rightShiftStage0Idx1_uid17527_dupName_166_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17525_dupName_166_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17529_dupName_166_i_unnamed_c_compstr0_shift_x(MUX,17528)@95
    assign rightShiftStage0_uid17529_dupName_166_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17529_dupName_166_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_q or rightShiftStage0Idx1_uid17527_dupName_166_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17529_dupName_166_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17529_dupName_166_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compstr1184_q;
            1'b1 : rightShiftStage0_uid17529_dupName_166_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17527_dupName_166_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17529_dupName_166_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17534_dupName_166_i_unnamed_c_compstr0_shift_x(MUX,17533)@95
    assign rightShiftStage1_uid17534_dupName_166_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17534_dupName_166_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17529_dupName_166_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17532_dupName_166_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17534_dupName_166_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17534_dupName_166_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17529_dupName_166_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17534_dupName_166_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17532_dupName_166_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17534_dupName_166_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1187_vt_select_21(BITSELECT,9962)@95
    assign i_unnamed_c_compstr1187_vt_select_21_b = rightShiftStage1_uid17534_dupName_166_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1187_vt_join(BITJOIN,9961)@95
    assign i_unnamed_c_compstr1187_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1187_vt_select_21_b};

    // i_unnamed_c_compstr1188_sel_x(BITSELECT,6049)@95
    assign i_unnamed_c_compstr1188_sel_x_b = i_unnamed_c_compstr1187_vt_join_q[15:0];

    // i_unnamed_c_compstr1189_BitSelect_for_a(BITSELECT,27487)@95
    assign i_unnamed_c_compstr1189_BitSelect_for_a_b = i_unnamed_c_compstr1188_sel_x_b[0:0];

    // i_unnamed_c_compstr1189_join(BITJOIN,27488)@95
    assign i_unnamed_c_compstr1189_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1189_BitSelect_for_a_b};

    // i_unnamed_c_compstr1189_vt_select_0(BITSELECT,9967)@95
    assign i_unnamed_c_compstr1189_vt_select_0_b = i_unnamed_c_compstr1189_join_q[0:0];

    // redist241_i_unnamed_c_compstr1189_vt_select_0_b_1(DELAY,28469)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist241_i_unnamed_c_compstr1189_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1189_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1189_vt_join(BITJOIN,9966)@96
    assign i_unnamed_c_compstr1189_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist241_i_unnamed_c_compstr1189_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_41_c_compstr1190(ADD,7042)@96
    assign i_add_i_i_i_i_i_i_41_c_compstr1190_a = {1'b0, i_unnamed_c_compstr1189_vt_join_q};
    assign i_add_i_i_i_i_i_i_41_c_compstr1190_b = {1'b0, redist1090_i_conv_i_i_i_i_i_41_c_compstr1186_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_41_c_compstr1190_o = $unsigned(i_add_i_i_i_i_i_i_41_c_compstr1190_a) + $unsigned(i_add_i_i_i_i_i_i_41_c_compstr1190_b);
    assign i_add_i_i_i_i_i_i_41_c_compstr1190_q = i_add_i_i_i_i_i_i_41_c_compstr1190_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_41_c_compstr1190_sel_x(BITSELECT,2236)@96
    assign bgTrunc_i_add_i_i_i_i_i_i_41_c_compstr1190_sel_x_b = i_add_i_i_i_i_i_i_41_c_compstr1190_q[15:0];

    // i_conv_i_i_i_i_i_i279_42_c_compstr1210_sel_x(BITSELECT,3904)@96
    assign i_conv_i_i_i_i_i_i279_42_c_compstr1210_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_41_c_compstr1190_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_42_c_compstr1210_vt_select_15(BITSELECT,8133)@96
    assign i_conv_i_i_i_i_i_i279_42_c_compstr1210_vt_select_15_b = i_conv_i_i_i_i_i_i279_42_c_compstr1210_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_42_c_compstr1210_vt_join(BITJOIN,8132)@96
    assign i_conv_i_i_i_i_i_i279_42_c_compstr1210_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_42_c_compstr1210_vt_select_15_b};

    // leftShiftStage0_uid26294_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x(MUX,26293)@96
    assign leftShiftStage0_uid26294_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26294_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_42_c_compstr1210_vt_join_q or leftShiftStage0Idx1_uid26292_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26294_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26294_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_42_c_compstr1210_vt_join_q;
            1'b1 : leftShiftStage0_uid26294_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26292_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26294_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26299_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x(MUX,26298)@96
    assign leftShiftStage1_uid26299_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26299_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_s or leftShiftStage0_uid26294_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26297_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26299_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26299_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q = leftShiftStage0_uid26294_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26299_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26297_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26299_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26304_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x(MUX,26303)@96
    assign leftShiftStage2_uid26304_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26304_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_s or leftShiftStage1_uid26299_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26302_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26304_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26304_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q = leftShiftStage1_uid26299_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26304_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26302_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26304_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_42_c_compstr1211_vt_select_28(BITSELECT,9613)@96
    assign i_shl_i_i_i_i_i_i_42_c_compstr1211_vt_select_28_b = leftShiftStage2_uid26304_i_shl_i_i_i_i_i_i_42_c_compstr0_shift_x_q[28:13];

    // redist319_i_shl_i_i_i_i_i_i_42_c_compstr1211_vt_select_28_b_1(DELAY,28547)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist319_i_shl_i_i_i_i_i_i_42_c_compstr1211_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_42_c_compstr1211_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_42_c_compstr1211_vt_join(BITJOIN,9612)@97
    assign i_shl_i_i_i_i_i_i_42_c_compstr1211_vt_join_q = {redist319_i_shl_i_i_i_i_i_i_42_c_compstr1211_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_offset(CONSTANT,30042)
    assign redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_offset_q = $unsigned(7'b0110010);

    // redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_rdcnt(ADD,31491)
    assign redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_a = {1'b0, redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_wraddr_q};
    assign redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_b = {1'b0, redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_o <= $unsigned(redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_a) + $unsigned(redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_b);
        end
    end
    assign redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_q = redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_o[7:0];

    // redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_inputreg0(DELAY,31486)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl);
        end
    end

    // redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_wraddr(COUNTER,31489)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_wraddr_i <= $unsigned(redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_wraddr_q = redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_wraddr_i[6:0];

    // redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem(DUALMEM,31488)
    assign redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_ia = $unsigned(redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_inputreg0_q);
    assign redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_aa = redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_wraddr_q;
    assign redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_ab = redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_aa),
        .data_a(redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_ab),
        .q_b(redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_q = redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_iq[15:0];

    // redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_outputreg0(DELAY,31487)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_outputreg0_q <= $unsigned(redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_mem_q);
        end
    end

    // redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_rdcnt(ADD,30043)
    assign redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_a = {1'b0, redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_wraddr_q};
    assign redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_b = {1'b0, redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_o <= $unsigned(redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_a) + $unsigned(redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_b);
        end
    end
    assign redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_q = redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_o[7:0];

    // redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_inputreg0(DELAY,30038)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl);
        end
    end

    // redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_wraddr(COUNTER,30041)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_wraddr_i <= $unsigned(redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_wraddr_q = redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_wraddr_i[6:0];

    // redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem(DUALMEM,30040)
    assign redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_ia = $unsigned(redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_inputreg0_q);
    assign redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_aa = redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_wraddr_q;
    assign redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_ab = redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_aa),
        .data_a(redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_ab),
        .q_b(redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_q = redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_iq[15:0];

    // redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_outputreg0(DELAY,30039)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_outputreg0_q <= $unsigned(redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_mem_q);
        end
    end

    // redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_rdcnt(ADD,30049)
    assign redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_a = {1'b0, redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_wraddr_q};
    assign redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_b = {1'b0, redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_o <= $unsigned(redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_a) + $unsigned(redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_b);
        end
    end
    assign redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_q = redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_o[7:0];

    // redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_inputreg0(DELAY,30044)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl);
        end
    end

    // redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_wraddr(COUNTER,30047)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_wraddr_i <= $unsigned(redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_wraddr_q = redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_wraddr_i[6:0];

    // redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem(DUALMEM,30046)
    assign redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_ia = $unsigned(redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_inputreg0_q);
    assign redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_aa = redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_wraddr_q;
    assign redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_ab = redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_aa),
        .data_a(redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_ab),
        .q_b(redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_q = redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_iq[15:0];

    // redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_outputreg0(DELAY,30045)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_outputreg0_q <= $unsigned(redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_mem_q);
        end
    end

    // redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_rdcnt(ADD,31485)
    assign redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_a = {1'b0, redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_wraddr_q};
    assign redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_b = {1'b0, redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_o <= $unsigned(redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_a) + $unsigned(redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_b);
        end
    end
    assign redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_q = redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_o[7:0];

    // redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_inputreg0(DELAY,31480)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl);
        end
    end

    // redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_wraddr(COUNTER,31483)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_wraddr_i <= $unsigned(redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_wraddr_q = redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_wraddr_i[6:0];

    // redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem(DUALMEM,31482)
    assign redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_ia = $unsigned(redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_inputreg0_q);
    assign redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_aa = redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_wraddr_q;
    assign redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_ab = redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_aa),
        .data_a(redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_ab),
        .q_b(redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_q = redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_iq[15:0];

    // redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_outputreg0(DELAY,31481)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_outputreg0_q <= $unsigned(redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28001)@91 + 5
    // out q@97
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212(ADD,8585)@97
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod251_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_b = $unsigned({{5{i_shl_i_i_i_i_i_i_42_c_compstr1211_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_42_c_compstr1211_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_o[33:0];

    // rightShiftStage0_uid17573_dupName_169_i_unnamed_c_compstr0_shift_x(MUX,17572)@97
    assign rightShiftStage0_uid17573_dupName_169_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17573_dupName_169_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_q or rightShiftStage0Idx1_uid17571_dupName_169_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17573_dupName_169_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17573_dupName_169_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_q;
            1'b1 : rightShiftStage0_uid17573_dupName_169_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17571_dupName_169_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17573_dupName_169_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17578_dupName_169_i_unnamed_c_compstr0_shift_x(MUX,17577)@97
    assign rightShiftStage1_uid17578_dupName_169_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17578_dupName_169_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17573_dupName_169_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17576_dupName_169_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17578_dupName_169_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17578_dupName_169_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17573_dupName_169_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17578_dupName_169_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17576_dupName_169_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17578_dupName_169_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17583_dupName_169_i_unnamed_c_compstr0_shift_x(MUX,17582)@97
    assign rightShiftStage2_uid17583_dupName_169_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17583_dupName_169_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17578_dupName_169_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17581_dupName_169_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17583_dupName_169_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17583_dupName_169_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17578_dupName_169_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17583_dupName_169_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17581_dupName_169_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17583_dupName_169_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1213_vt_select_20(BITSELECT,9981)@97
    assign i_unnamed_c_compstr1213_vt_select_20_b = rightShiftStage2_uid17583_dupName_169_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1213_vt_join(BITJOIN,9980)@97
    assign i_unnamed_c_compstr1213_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1213_vt_select_20_b};

    // i_conv_i_i_i_i_i_42_c_compstr1214_sel_x(BITSELECT,3776)@97
    assign i_conv_i_i_i_i_i_42_c_compstr1214_sel_x_b = i_unnamed_c_compstr1213_vt_join_q[15:0];

    // redist1089_i_conv_i_i_i_i_i_42_c_compstr1214_sel_x_b_1(DELAY,29317)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1089_i_conv_i_i_i_i_i_42_c_compstr1214_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_42_c_compstr1214_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17592_dupName_170_i_unnamed_c_compstr0_shift_x(BITSELECT,17591)@97
    assign rightShiftStage1Idx1Rng8_uid17592_dupName_170_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17591_dupName_170_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17594_dupName_170_i_unnamed_c_compstr0_shift_x(BITJOIN,17593)@97
    assign rightShiftStage1Idx1_uid17594_dupName_170_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17592_dupName_170_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17587_dupName_170_i_unnamed_c_compstr0_shift_x(BITSELECT,17586)@97
    assign rightShiftStage0Idx1Rng4_uid17587_dupName_170_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_q[33:4];

    // rightShiftStage0Idx1_uid17589_dupName_170_i_unnamed_c_compstr0_shift_x(BITJOIN,17588)@97
    assign rightShiftStage0Idx1_uid17589_dupName_170_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17587_dupName_170_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17591_dupName_170_i_unnamed_c_compstr0_shift_x(MUX,17590)@97
    assign rightShiftStage0_uid17591_dupName_170_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17591_dupName_170_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_q or rightShiftStage0Idx1_uid17589_dupName_170_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17591_dupName_170_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17591_dupName_170_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compstr1212_q;
            1'b1 : rightShiftStage0_uid17591_dupName_170_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17589_dupName_170_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17591_dupName_170_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17596_dupName_170_i_unnamed_c_compstr0_shift_x(MUX,17595)@97
    assign rightShiftStage1_uid17596_dupName_170_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17596_dupName_170_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17591_dupName_170_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17594_dupName_170_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17596_dupName_170_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17596_dupName_170_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17591_dupName_170_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17596_dupName_170_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17594_dupName_170_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17596_dupName_170_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1215_vt_select_21(BITSELECT,9984)@97
    assign i_unnamed_c_compstr1215_vt_select_21_b = rightShiftStage1_uid17596_dupName_170_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1215_vt_join(BITJOIN,9983)@97
    assign i_unnamed_c_compstr1215_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1215_vt_select_21_b};

    // i_unnamed_c_compstr1216_sel_x(BITSELECT,6051)@97
    assign i_unnamed_c_compstr1216_sel_x_b = i_unnamed_c_compstr1215_vt_join_q[15:0];

    // i_unnamed_c_compstr1217_BitSelect_for_a(BITSELECT,27491)@97
    assign i_unnamed_c_compstr1217_BitSelect_for_a_b = i_unnamed_c_compstr1216_sel_x_b[0:0];

    // i_unnamed_c_compstr1217_join(BITJOIN,27492)@97
    assign i_unnamed_c_compstr1217_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1217_BitSelect_for_a_b};

    // i_unnamed_c_compstr1217_vt_select_0(BITSELECT,9989)@97
    assign i_unnamed_c_compstr1217_vt_select_0_b = i_unnamed_c_compstr1217_join_q[0:0];

    // redist239_i_unnamed_c_compstr1217_vt_select_0_b_1(DELAY,28467)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist239_i_unnamed_c_compstr1217_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1217_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1217_vt_join(BITJOIN,9988)@98
    assign i_unnamed_c_compstr1217_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist239_i_unnamed_c_compstr1217_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_42_c_compstr1218(ADD,7043)@98
    assign i_add_i_i_i_i_i_i_42_c_compstr1218_a = {1'b0, i_unnamed_c_compstr1217_vt_join_q};
    assign i_add_i_i_i_i_i_i_42_c_compstr1218_b = {1'b0, redist1089_i_conv_i_i_i_i_i_42_c_compstr1214_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_42_c_compstr1218_o = $unsigned(i_add_i_i_i_i_i_i_42_c_compstr1218_a) + $unsigned(i_add_i_i_i_i_i_i_42_c_compstr1218_b);
    assign i_add_i_i_i_i_i_i_42_c_compstr1218_q = i_add_i_i_i_i_i_i_42_c_compstr1218_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_42_c_compstr1218_sel_x(BITSELECT,2237)@98
    assign bgTrunc_i_add_i_i_i_i_i_i_42_c_compstr1218_sel_x_b = i_add_i_i_i_i_i_i_42_c_compstr1218_q[15:0];

    // i_conv_i_i_i_i_i_i279_43_c_compstr1238_sel_x(BITSELECT,3905)@98
    assign i_conv_i_i_i_i_i_i279_43_c_compstr1238_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_42_c_compstr1218_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_43_c_compstr1238_vt_select_15(BITSELECT,8137)@98
    assign i_conv_i_i_i_i_i_i279_43_c_compstr1238_vt_select_15_b = i_conv_i_i_i_i_i_i279_43_c_compstr1238_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_43_c_compstr1238_vt_join(BITJOIN,8136)@98
    assign i_conv_i_i_i_i_i_i279_43_c_compstr1238_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_43_c_compstr1238_vt_select_15_b};

    // leftShiftStage0_uid26312_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x(MUX,26311)@98
    assign leftShiftStage0_uid26312_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26312_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_43_c_compstr1238_vt_join_q or leftShiftStage0Idx1_uid26310_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26312_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26312_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_43_c_compstr1238_vt_join_q;
            1'b1 : leftShiftStage0_uid26312_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26310_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26312_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26317_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x(MUX,26316)@98
    assign leftShiftStage1_uid26317_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26317_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_s or leftShiftStage0_uid26312_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26315_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26317_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26317_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q = leftShiftStage0_uid26312_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26317_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26315_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26317_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26322_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x(MUX,26321)@98
    assign leftShiftStage2_uid26322_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26322_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_s or leftShiftStage1_uid26317_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26320_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26322_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26322_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q = leftShiftStage1_uid26317_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26322_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26320_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26322_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_43_c_compstr1239_vt_select_28(BITSELECT,9616)@98
    assign i_shl_i_i_i_i_i_i_43_c_compstr1239_vt_select_28_b = leftShiftStage2_uid26322_i_shl_i_i_i_i_i_i_43_c_compstr0_shift_x_q[28:13];

    // redist318_i_shl_i_i_i_i_i_i_43_c_compstr1239_vt_select_28_b_1(DELAY,28546)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist318_i_shl_i_i_i_i_i_i_43_c_compstr1239_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_43_c_compstr1239_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_43_c_compstr1239_vt_join(BITJOIN,9615)@99
    assign i_shl_i_i_i_i_i_i_43_c_compstr1239_vt_join_q = {redist318_i_shl_i_i_i_i_i_i_43_c_compstr1239_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_offset(CONSTANT,30054)
    assign redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_offset_q = $unsigned(7'b0110000);

    // redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_rdcnt(ADD,31503)
    assign redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_a = {1'b0, redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_wraddr_q};
    assign redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_b = {1'b0, redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_o <= $unsigned(redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_a) + $unsigned(redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_b);
        end
    end
    assign redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_q = redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_o[7:0];

    // redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_inputreg0(DELAY,31498)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl);
        end
    end

    // redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_wraddr(COUNTER,31501)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_wraddr_i <= $unsigned(redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_wraddr_q = redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_wraddr_i[6:0];

    // redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem(DUALMEM,31500)
    assign redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_ia = $unsigned(redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_inputreg0_q);
    assign redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_aa = redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_wraddr_q;
    assign redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_ab = redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_aa),
        .data_a(redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_ab),
        .q_b(redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_q = redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_iq[15:0];

    // redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_outputreg0(DELAY,31499)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_outputreg0_q <= $unsigned(redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_mem_q);
        end
    end

    // redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_rdcnt(ADD,30055)
    assign redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_a = {1'b0, redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_wraddr_q};
    assign redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_b = {1'b0, redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_o <= $unsigned(redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_a) + $unsigned(redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_b);
        end
    end
    assign redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_q = redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_o[7:0];

    // redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_inputreg0(DELAY,30050)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl);
        end
    end

    // redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_wraddr(COUNTER,30053)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_wraddr_i <= $unsigned(redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_wraddr_q = redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_wraddr_i[6:0];

    // redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem(DUALMEM,30052)
    assign redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_ia = $unsigned(redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_inputreg0_q);
    assign redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_aa = redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_wraddr_q;
    assign redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_ab = redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_aa),
        .data_a(redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_ab),
        .q_b(redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_q = redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_iq[15:0];

    // redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_outputreg0(DELAY,30051)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_outputreg0_q <= $unsigned(redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_mem_q);
        end
    end

    // redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_rdcnt(ADD,30061)
    assign redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_a = {1'b0, redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_wraddr_q};
    assign redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_b = {1'b0, redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_o <= $unsigned(redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_a) + $unsigned(redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_b);
        end
    end
    assign redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_q = redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_o[7:0];

    // redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_inputreg0(DELAY,30056)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl);
        end
    end

    // redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_wraddr(COUNTER,30059)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_wraddr_i <= $unsigned(redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_wraddr_q = redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_wraddr_i[6:0];

    // redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem(DUALMEM,30058)
    assign redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_ia = $unsigned(redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_inputreg0_q);
    assign redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_aa = redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_wraddr_q;
    assign redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_ab = redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_aa),
        .data_a(redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_ab),
        .q_b(redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_q = redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_iq[15:0];

    // redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_outputreg0(DELAY,30057)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_outputreg0_q <= $unsigned(redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_mem_q);
        end
    end

    // redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_rdcnt(ADD,31497)
    assign redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_a = {1'b0, redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_wraddr_q};
    assign redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_b = {1'b0, redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_o <= $unsigned(redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_a) + $unsigned(redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_b);
        end
    end
    assign redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_q = redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_o[7:0];

    // redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_inputreg0(DELAY,31492)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl);
        end
    end

    // redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_wraddr(COUNTER,31495)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_wraddr_i <= $unsigned(redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_wraddr_q = redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_wraddr_i[6:0];

    // redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem(DUALMEM,31494)
    assign redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_ia = $unsigned(redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_inputreg0_q);
    assign redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_aa = redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_wraddr_q;
    assign redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_ab = redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_aa),
        .data_a(redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_ab),
        .q_b(redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_q = redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_iq[15:0];

    // redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_outputreg0(DELAY,31493)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_outputreg0_q <= $unsigned(redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28002)@93 + 5
    // out q@99
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240(ADD,8586)@99
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod256_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_b = $unsigned({{5{i_shl_i_i_i_i_i_i_43_c_compstr1239_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_43_c_compstr1239_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_o[33:0];

    // rightShiftStage0_uid17635_dupName_173_i_unnamed_c_compstr0_shift_x(MUX,17634)@99
    assign rightShiftStage0_uid17635_dupName_173_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17635_dupName_173_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_q or rightShiftStage0Idx1_uid17633_dupName_173_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17635_dupName_173_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17635_dupName_173_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_q;
            1'b1 : rightShiftStage0_uid17635_dupName_173_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17633_dupName_173_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17635_dupName_173_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17640_dupName_173_i_unnamed_c_compstr0_shift_x(MUX,17639)@99
    assign rightShiftStage1_uid17640_dupName_173_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17640_dupName_173_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17635_dupName_173_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17638_dupName_173_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17640_dupName_173_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17640_dupName_173_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17635_dupName_173_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17640_dupName_173_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17638_dupName_173_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17640_dupName_173_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17645_dupName_173_i_unnamed_c_compstr0_shift_x(MUX,17644)@99
    assign rightShiftStage2_uid17645_dupName_173_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17645_dupName_173_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17640_dupName_173_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17643_dupName_173_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17645_dupName_173_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17645_dupName_173_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17640_dupName_173_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17645_dupName_173_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17643_dupName_173_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17645_dupName_173_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1241_vt_select_20(BITSELECT,10009)@99
    assign i_unnamed_c_compstr1241_vt_select_20_b = rightShiftStage2_uid17645_dupName_173_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1241_vt_join(BITJOIN,10008)@99
    assign i_unnamed_c_compstr1241_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1241_vt_select_20_b};

    // i_conv_i_i_i_i_i_43_c_compstr1242_sel_x(BITSELECT,3777)@99
    assign i_conv_i_i_i_i_i_43_c_compstr1242_sel_x_b = i_unnamed_c_compstr1241_vt_join_q[15:0];

    // redist1088_i_conv_i_i_i_i_i_43_c_compstr1242_sel_x_b_1(DELAY,29316)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1088_i_conv_i_i_i_i_i_43_c_compstr1242_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_43_c_compstr1242_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17654_dupName_174_i_unnamed_c_compstr0_shift_x(BITSELECT,17653)@99
    assign rightShiftStage1Idx1Rng8_uid17654_dupName_174_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17653_dupName_174_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17656_dupName_174_i_unnamed_c_compstr0_shift_x(BITJOIN,17655)@99
    assign rightShiftStage1Idx1_uid17656_dupName_174_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17654_dupName_174_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17649_dupName_174_i_unnamed_c_compstr0_shift_x(BITSELECT,17648)@99
    assign rightShiftStage0Idx1Rng4_uid17649_dupName_174_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_q[33:4];

    // rightShiftStage0Idx1_uid17651_dupName_174_i_unnamed_c_compstr0_shift_x(BITJOIN,17650)@99
    assign rightShiftStage0Idx1_uid17651_dupName_174_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17649_dupName_174_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17653_dupName_174_i_unnamed_c_compstr0_shift_x(MUX,17652)@99
    assign rightShiftStage0_uid17653_dupName_174_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17653_dupName_174_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_q or rightShiftStage0Idx1_uid17651_dupName_174_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17653_dupName_174_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17653_dupName_174_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compstr1240_q;
            1'b1 : rightShiftStage0_uid17653_dupName_174_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17651_dupName_174_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17653_dupName_174_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17658_dupName_174_i_unnamed_c_compstr0_shift_x(MUX,17657)@99
    assign rightShiftStage1_uid17658_dupName_174_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17658_dupName_174_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17653_dupName_174_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17656_dupName_174_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17658_dupName_174_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17658_dupName_174_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17653_dupName_174_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17658_dupName_174_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17656_dupName_174_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17658_dupName_174_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1243_vt_select_21(BITSELECT,10012)@99
    assign i_unnamed_c_compstr1243_vt_select_21_b = rightShiftStage1_uid17658_dupName_174_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1243_vt_join(BITJOIN,10011)@99
    assign i_unnamed_c_compstr1243_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1243_vt_select_21_b};

    // i_unnamed_c_compstr1244_sel_x(BITSELECT,6054)@99
    assign i_unnamed_c_compstr1244_sel_x_b = i_unnamed_c_compstr1243_vt_join_q[15:0];

    // i_unnamed_c_compstr1245_BitSelect_for_a(BITSELECT,27495)@99
    assign i_unnamed_c_compstr1245_BitSelect_for_a_b = i_unnamed_c_compstr1244_sel_x_b[0:0];

    // i_unnamed_c_compstr1245_join(BITJOIN,27496)@99
    assign i_unnamed_c_compstr1245_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1245_BitSelect_for_a_b};

    // i_unnamed_c_compstr1245_vt_select_0(BITSELECT,10017)@99
    assign i_unnamed_c_compstr1245_vt_select_0_b = i_unnamed_c_compstr1245_join_q[0:0];

    // redist237_i_unnamed_c_compstr1245_vt_select_0_b_1(DELAY,28465)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist237_i_unnamed_c_compstr1245_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1245_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1245_vt_join(BITJOIN,10016)@100
    assign i_unnamed_c_compstr1245_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist237_i_unnamed_c_compstr1245_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_43_c_compstr1246(ADD,7044)@100
    assign i_add_i_i_i_i_i_i_43_c_compstr1246_a = {1'b0, i_unnamed_c_compstr1245_vt_join_q};
    assign i_add_i_i_i_i_i_i_43_c_compstr1246_b = {1'b0, redist1088_i_conv_i_i_i_i_i_43_c_compstr1242_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_43_c_compstr1246_o = $unsigned(i_add_i_i_i_i_i_i_43_c_compstr1246_a) + $unsigned(i_add_i_i_i_i_i_i_43_c_compstr1246_b);
    assign i_add_i_i_i_i_i_i_43_c_compstr1246_q = i_add_i_i_i_i_i_i_43_c_compstr1246_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_43_c_compstr1246_sel_x(BITSELECT,2238)@100
    assign bgTrunc_i_add_i_i_i_i_i_i_43_c_compstr1246_sel_x_b = i_add_i_i_i_i_i_i_43_c_compstr1246_q[15:0];

    // i_conv_i_i_i_i_i_i279_44_c_compstr1266_sel_x(BITSELECT,3906)@100
    assign i_conv_i_i_i_i_i_i279_44_c_compstr1266_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_43_c_compstr1246_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_44_c_compstr1266_vt_select_15(BITSELECT,8141)@100
    assign i_conv_i_i_i_i_i_i279_44_c_compstr1266_vt_select_15_b = i_conv_i_i_i_i_i_i279_44_c_compstr1266_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_44_c_compstr1266_vt_join(BITJOIN,8140)@100
    assign i_conv_i_i_i_i_i_i279_44_c_compstr1266_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_44_c_compstr1266_vt_select_15_b};

    // leftShiftStage0_uid26330_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x(MUX,26329)@100
    assign leftShiftStage0_uid26330_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26330_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_44_c_compstr1266_vt_join_q or leftShiftStage0Idx1_uid26328_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26330_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26330_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_44_c_compstr1266_vt_join_q;
            1'b1 : leftShiftStage0_uid26330_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26328_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26330_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26335_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x(MUX,26334)@100
    assign leftShiftStage1_uid26335_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26335_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_s or leftShiftStage0_uid26330_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26333_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26335_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26335_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q = leftShiftStage0_uid26330_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26335_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26333_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26335_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26340_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x(MUX,26339)@100
    assign leftShiftStage2_uid26340_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26340_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_s or leftShiftStage1_uid26335_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26338_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26340_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26340_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q = leftShiftStage1_uid26335_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26340_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26338_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26340_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_44_c_compstr1267_vt_select_28(BITSELECT,9619)@100
    assign i_shl_i_i_i_i_i_i_44_c_compstr1267_vt_select_28_b = leftShiftStage2_uid26340_i_shl_i_i_i_i_i_i_44_c_compstr0_shift_x_q[28:13];

    // redist317_i_shl_i_i_i_i_i_i_44_c_compstr1267_vt_select_28_b_1(DELAY,28545)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist317_i_shl_i_i_i_i_i_i_44_c_compstr1267_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_44_c_compstr1267_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_44_c_compstr1267_vt_join(BITJOIN,9618)@101
    assign i_shl_i_i_i_i_i_i_44_c_compstr1267_vt_join_q = {redist317_i_shl_i_i_i_i_i_i_44_c_compstr1267_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_offset(CONSTANT,30066)
    assign redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_offset_q = $unsigned(7'b0101110);

    // redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_rdcnt(ADD,31515)
    assign redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_a = {1'b0, redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_wraddr_q};
    assign redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_b = {1'b0, redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_o <= $unsigned(redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_a) + $unsigned(redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_b);
        end
    end
    assign redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_q = redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_o[7:0];

    // redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_inputreg0(DELAY,31510)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl);
        end
    end

    // redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_wraddr(COUNTER,31513)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_wraddr_i <= $unsigned(redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_wraddr_q = redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_wraddr_i[6:0];

    // redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem(DUALMEM,31512)
    assign redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_ia = $unsigned(redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_inputreg0_q);
    assign redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_aa = redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_wraddr_q;
    assign redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_ab = redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_aa),
        .data_a(redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_ab),
        .q_b(redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_q = redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_iq[15:0];

    // redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_outputreg0(DELAY,31511)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_outputreg0_q <= $unsigned(redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_mem_q);
        end
    end

    // redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_rdcnt(ADD,30067)
    assign redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_a = {1'b0, redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_wraddr_q};
    assign redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_b = {1'b0, redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_o <= $unsigned(redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_a) + $unsigned(redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_b);
        end
    end
    assign redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_q = redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_o[7:0];

    // redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_inputreg0(DELAY,30062)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl);
        end
    end

    // redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_wraddr(COUNTER,30065)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_wraddr_i <= $unsigned(redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_wraddr_q = redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_wraddr_i[6:0];

    // redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem(DUALMEM,30064)
    assign redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_ia = $unsigned(redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_inputreg0_q);
    assign redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_aa = redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_wraddr_q;
    assign redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_ab = redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_aa),
        .data_a(redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_ab),
        .q_b(redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_q = redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_iq[15:0];

    // redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_outputreg0(DELAY,30063)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_outputreg0_q <= $unsigned(redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_mem_q);
        end
    end

    // redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_rdcnt(ADD,30073)
    assign redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_a = {1'b0, redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_wraddr_q};
    assign redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_b = {1'b0, redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_o <= $unsigned(redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_a) + $unsigned(redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_b);
        end
    end
    assign redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_q = redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_o[7:0];

    // redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_inputreg0(DELAY,30068)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl);
        end
    end

    // redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_wraddr(COUNTER,30071)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_wraddr_i <= $unsigned(redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_wraddr_q = redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_wraddr_i[6:0];

    // redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem(DUALMEM,30070)
    assign redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_ia = $unsigned(redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_inputreg0_q);
    assign redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_aa = redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_wraddr_q;
    assign redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_ab = redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_aa),
        .data_a(redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_ab),
        .q_b(redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_q = redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_iq[15:0];

    // redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_outputreg0(DELAY,30069)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_outputreg0_q <= $unsigned(redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_mem_q);
        end
    end

    // redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_rdcnt(ADD,31509)
    assign redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_a = {1'b0, redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_wraddr_q};
    assign redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_b = {1'b0, redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_o <= $unsigned(redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_a) + $unsigned(redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_b);
        end
    end
    assign redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_q = redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_o[7:0];

    // redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_inputreg0(DELAY,31504)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl);
        end
    end

    // redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_wraddr(COUNTER,31507)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_wraddr_i <= $unsigned(redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_wraddr_q = redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_wraddr_i[6:0];

    // redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem(DUALMEM,31506)
    assign redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_ia = $unsigned(redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_inputreg0_q);
    assign redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_aa = redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_wraddr_q;
    assign redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_ab = redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_aa),
        .data_a(redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_ab),
        .q_b(redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_q = redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_iq[15:0];

    // redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_outputreg0(DELAY,31505)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_outputreg0_q <= $unsigned(redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28003)@95 + 5
    // out q@101
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268(ADD,8587)@101
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod261_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_b = $unsigned({{5{i_shl_i_i_i_i_i_i_44_c_compstr1267_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_44_c_compstr1267_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_o[33:0];

    // rightShiftStage0_uid17697_dupName_177_i_unnamed_c_compstr0_shift_x(MUX,17696)@101
    assign rightShiftStage0_uid17697_dupName_177_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17697_dupName_177_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_q or rightShiftStage0Idx1_uid17695_dupName_177_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17697_dupName_177_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17697_dupName_177_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_q;
            1'b1 : rightShiftStage0_uid17697_dupName_177_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17695_dupName_177_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17697_dupName_177_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17702_dupName_177_i_unnamed_c_compstr0_shift_x(MUX,17701)@101
    assign rightShiftStage1_uid17702_dupName_177_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17702_dupName_177_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17697_dupName_177_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17700_dupName_177_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17702_dupName_177_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17702_dupName_177_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17697_dupName_177_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17702_dupName_177_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17700_dupName_177_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17702_dupName_177_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17707_dupName_177_i_unnamed_c_compstr0_shift_x(MUX,17706)@101
    assign rightShiftStage2_uid17707_dupName_177_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17707_dupName_177_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17702_dupName_177_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17705_dupName_177_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17707_dupName_177_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17707_dupName_177_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17702_dupName_177_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17707_dupName_177_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17705_dupName_177_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17707_dupName_177_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1269_vt_select_20(BITSELECT,10036)@101
    assign i_unnamed_c_compstr1269_vt_select_20_b = rightShiftStage2_uid17707_dupName_177_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1269_vt_join(BITJOIN,10035)@101
    assign i_unnamed_c_compstr1269_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1269_vt_select_20_b};

    // i_conv_i_i_i_i_i_44_c_compstr1270_sel_x(BITSELECT,3778)@101
    assign i_conv_i_i_i_i_i_44_c_compstr1270_sel_x_b = i_unnamed_c_compstr1269_vt_join_q[15:0];

    // redist1087_i_conv_i_i_i_i_i_44_c_compstr1270_sel_x_b_1(DELAY,29315)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1087_i_conv_i_i_i_i_i_44_c_compstr1270_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_44_c_compstr1270_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17716_dupName_178_i_unnamed_c_compstr0_shift_x(BITSELECT,17715)@101
    assign rightShiftStage1Idx1Rng8_uid17716_dupName_178_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17715_dupName_178_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17718_dupName_178_i_unnamed_c_compstr0_shift_x(BITJOIN,17717)@101
    assign rightShiftStage1Idx1_uid17718_dupName_178_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17716_dupName_178_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17711_dupName_178_i_unnamed_c_compstr0_shift_x(BITSELECT,17710)@101
    assign rightShiftStage0Idx1Rng4_uid17711_dupName_178_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_q[33:4];

    // rightShiftStage0Idx1_uid17713_dupName_178_i_unnamed_c_compstr0_shift_x(BITJOIN,17712)@101
    assign rightShiftStage0Idx1_uid17713_dupName_178_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17711_dupName_178_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17715_dupName_178_i_unnamed_c_compstr0_shift_x(MUX,17714)@101
    assign rightShiftStage0_uid17715_dupName_178_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17715_dupName_178_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_q or rightShiftStage0Idx1_uid17713_dupName_178_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17715_dupName_178_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17715_dupName_178_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compstr1268_q;
            1'b1 : rightShiftStage0_uid17715_dupName_178_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17713_dupName_178_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17715_dupName_178_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17720_dupName_178_i_unnamed_c_compstr0_shift_x(MUX,17719)@101
    assign rightShiftStage1_uid17720_dupName_178_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17720_dupName_178_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17715_dupName_178_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17718_dupName_178_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17720_dupName_178_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17720_dupName_178_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17715_dupName_178_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17720_dupName_178_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17718_dupName_178_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17720_dupName_178_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1271_vt_select_21(BITSELECT,10039)@101
    assign i_unnamed_c_compstr1271_vt_select_21_b = rightShiftStage1_uid17720_dupName_178_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1271_vt_join(BITJOIN,10038)@101
    assign i_unnamed_c_compstr1271_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1271_vt_select_21_b};

    // i_unnamed_c_compstr1272_sel_x(BITSELECT,6056)@101
    assign i_unnamed_c_compstr1272_sel_x_b = i_unnamed_c_compstr1271_vt_join_q[15:0];

    // i_unnamed_c_compstr1273_BitSelect_for_a(BITSELECT,27501)@101
    assign i_unnamed_c_compstr1273_BitSelect_for_a_b = i_unnamed_c_compstr1272_sel_x_b[0:0];

    // i_unnamed_c_compstr1273_join(BITJOIN,27502)@101
    assign i_unnamed_c_compstr1273_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1273_BitSelect_for_a_b};

    // i_unnamed_c_compstr1273_vt_select_0(BITSELECT,10044)@101
    assign i_unnamed_c_compstr1273_vt_select_0_b = i_unnamed_c_compstr1273_join_q[0:0];

    // redist234_i_unnamed_c_compstr1273_vt_select_0_b_1(DELAY,28462)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist234_i_unnamed_c_compstr1273_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1273_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1273_vt_join(BITJOIN,10043)@102
    assign i_unnamed_c_compstr1273_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist234_i_unnamed_c_compstr1273_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_44_c_compstr1274(ADD,7045)@102
    assign i_add_i_i_i_i_i_i_44_c_compstr1274_a = {1'b0, i_unnamed_c_compstr1273_vt_join_q};
    assign i_add_i_i_i_i_i_i_44_c_compstr1274_b = {1'b0, redist1087_i_conv_i_i_i_i_i_44_c_compstr1270_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_44_c_compstr1274_o = $unsigned(i_add_i_i_i_i_i_i_44_c_compstr1274_a) + $unsigned(i_add_i_i_i_i_i_i_44_c_compstr1274_b);
    assign i_add_i_i_i_i_i_i_44_c_compstr1274_q = i_add_i_i_i_i_i_i_44_c_compstr1274_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_44_c_compstr1274_sel_x(BITSELECT,2239)@102
    assign bgTrunc_i_add_i_i_i_i_i_i_44_c_compstr1274_sel_x_b = i_add_i_i_i_i_i_i_44_c_compstr1274_q[15:0];

    // i_conv_i_i_i_i_i_i279_45_c_compstr1294_sel_x(BITSELECT,3907)@102
    assign i_conv_i_i_i_i_i_i279_45_c_compstr1294_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_44_c_compstr1274_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_45_c_compstr1294_vt_select_15(BITSELECT,8145)@102
    assign i_conv_i_i_i_i_i_i279_45_c_compstr1294_vt_select_15_b = i_conv_i_i_i_i_i_i279_45_c_compstr1294_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_45_c_compstr1294_vt_join(BITJOIN,8144)@102
    assign i_conv_i_i_i_i_i_i279_45_c_compstr1294_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_45_c_compstr1294_vt_select_15_b};

    // leftShiftStage0_uid26348_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x(MUX,26347)@102
    assign leftShiftStage0_uid26348_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26348_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_45_c_compstr1294_vt_join_q or leftShiftStage0Idx1_uid26346_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26348_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26348_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_45_c_compstr1294_vt_join_q;
            1'b1 : leftShiftStage0_uid26348_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26346_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26348_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26353_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x(MUX,26352)@102
    assign leftShiftStage1_uid26353_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26353_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_s or leftShiftStage0_uid26348_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26351_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26353_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26353_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q = leftShiftStage0_uid26348_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26353_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26351_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26353_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26358_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x(MUX,26357)@102
    assign leftShiftStage2_uid26358_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26358_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_s or leftShiftStage1_uid26353_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26356_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26358_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26358_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q = leftShiftStage1_uid26353_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26358_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26356_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26358_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_45_c_compstr1295_vt_select_28(BITSELECT,9622)@102
    assign i_shl_i_i_i_i_i_i_45_c_compstr1295_vt_select_28_b = leftShiftStage2_uid26358_i_shl_i_i_i_i_i_i_45_c_compstr0_shift_x_q[28:13];

    // redist316_i_shl_i_i_i_i_i_i_45_c_compstr1295_vt_select_28_b_1(DELAY,28544)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist316_i_shl_i_i_i_i_i_i_45_c_compstr1295_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_45_c_compstr1295_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_45_c_compstr1295_vt_join(BITJOIN,9621)@103
    assign i_shl_i_i_i_i_i_i_45_c_compstr1295_vt_join_q = {redist316_i_shl_i_i_i_i_i_i_45_c_compstr1295_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_offset(CONSTANT,30078)
    assign redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_offset_q = $unsigned(7'b0101100);

    // redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_rdcnt(ADD,31527)
    assign redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_a = {1'b0, redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_wraddr_q};
    assign redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_b = {1'b0, redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_o <= $unsigned(redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_a) + $unsigned(redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_b);
        end
    end
    assign redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_q = redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_o[7:0];

    // redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_inputreg0(DELAY,31522)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl);
        end
    end

    // redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_wraddr(COUNTER,31525)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_wraddr_i <= $unsigned(redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_wraddr_q = redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_wraddr_i[6:0];

    // redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem(DUALMEM,31524)
    assign redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_ia = $unsigned(redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_inputreg0_q);
    assign redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_aa = redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_wraddr_q;
    assign redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_ab = redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_aa),
        .data_a(redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_ab),
        .q_b(redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_q = redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_iq[15:0];

    // redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_outputreg0(DELAY,31523)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_outputreg0_q <= $unsigned(redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_mem_q);
        end
    end

    // redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_rdcnt(ADD,30079)
    assign redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_a = {1'b0, redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_wraddr_q};
    assign redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_b = {1'b0, redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_o <= $unsigned(redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_a) + $unsigned(redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_b);
        end
    end
    assign redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_q = redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_o[7:0];

    // redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_inputreg0(DELAY,30074)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl);
        end
    end

    // redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_wraddr(COUNTER,30077)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_wraddr_i <= $unsigned(redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_wraddr_q = redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_wraddr_i[6:0];

    // redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem(DUALMEM,30076)
    assign redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_ia = $unsigned(redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_inputreg0_q);
    assign redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_aa = redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_wraddr_q;
    assign redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_ab = redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_aa),
        .data_a(redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_ab),
        .q_b(redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_q = redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_iq[15:0];

    // redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_outputreg0(DELAY,30075)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_outputreg0_q <= $unsigned(redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_mem_q);
        end
    end

    // redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_rdcnt(ADD,30085)
    assign redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_a = {1'b0, redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_wraddr_q};
    assign redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_b = {1'b0, redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_o <= $unsigned(redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_a) + $unsigned(redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_b);
        end
    end
    assign redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_q = redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_o[7:0];

    // redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_inputreg0(DELAY,30080)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl);
        end
    end

    // redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_wraddr(COUNTER,30083)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_wraddr_i <= $unsigned(redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_wraddr_q = redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_wraddr_i[6:0];

    // redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem(DUALMEM,30082)
    assign redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_ia = $unsigned(redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_inputreg0_q);
    assign redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_aa = redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_wraddr_q;
    assign redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_ab = redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_aa),
        .data_a(redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_ab),
        .q_b(redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_q = redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_iq[15:0];

    // redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_outputreg0(DELAY,30081)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_outputreg0_q <= $unsigned(redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_mem_q);
        end
    end

    // redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_rdcnt(ADD,31521)
    assign redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_a = {1'b0, redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_wraddr_q};
    assign redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_b = {1'b0, redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_o <= $unsigned(redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_a) + $unsigned(redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_b);
        end
    end
    assign redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_q = redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_o[7:0];

    // redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_inputreg0(DELAY,31516)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl);
        end
    end

    // redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_wraddr(COUNTER,31519)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_wraddr_i <= $unsigned(redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_wraddr_q = redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_wraddr_i[6:0];

    // redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem(DUALMEM,31518)
    assign redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_ia = $unsigned(redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_inputreg0_q);
    assign redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_aa = redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_wraddr_q;
    assign redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_ab = redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_aa),
        .data_a(redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_ab),
        .q_b(redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_q = redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_iq[15:0];

    // redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_outputreg0(DELAY,31517)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_outputreg0_q <= $unsigned(redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28004)@97 + 5
    // out q@103
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296(ADD,8588)@103
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod266_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_b = $unsigned({{5{i_shl_i_i_i_i_i_i_45_c_compstr1295_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_45_c_compstr1295_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_o[33:0];

    // rightShiftStage0_uid17759_dupName_181_i_unnamed_c_compstr0_shift_x(MUX,17758)@103
    assign rightShiftStage0_uid17759_dupName_181_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17759_dupName_181_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_q or rightShiftStage0Idx1_uid17757_dupName_181_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17759_dupName_181_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17759_dupName_181_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_q;
            1'b1 : rightShiftStage0_uid17759_dupName_181_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17757_dupName_181_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17759_dupName_181_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17764_dupName_181_i_unnamed_c_compstr0_shift_x(MUX,17763)@103
    assign rightShiftStage1_uid17764_dupName_181_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17764_dupName_181_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17759_dupName_181_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17762_dupName_181_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17764_dupName_181_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17764_dupName_181_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17759_dupName_181_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17764_dupName_181_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17762_dupName_181_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17764_dupName_181_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17769_dupName_181_i_unnamed_c_compstr0_shift_x(MUX,17768)@103
    assign rightShiftStage2_uid17769_dupName_181_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17769_dupName_181_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17764_dupName_181_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17767_dupName_181_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17769_dupName_181_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17769_dupName_181_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17764_dupName_181_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17769_dupName_181_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17767_dupName_181_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17769_dupName_181_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1297_vt_select_20(BITSELECT,10058)@103
    assign i_unnamed_c_compstr1297_vt_select_20_b = rightShiftStage2_uid17769_dupName_181_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1297_vt_join(BITJOIN,10057)@103
    assign i_unnamed_c_compstr1297_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1297_vt_select_20_b};

    // i_conv_i_i_i_i_i_45_c_compstr1298_sel_x(BITSELECT,3779)@103
    assign i_conv_i_i_i_i_i_45_c_compstr1298_sel_x_b = i_unnamed_c_compstr1297_vt_join_q[15:0];

    // redist1086_i_conv_i_i_i_i_i_45_c_compstr1298_sel_x_b_1(DELAY,29314)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1086_i_conv_i_i_i_i_i_45_c_compstr1298_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_45_c_compstr1298_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17778_dupName_182_i_unnamed_c_compstr0_shift_x(BITSELECT,17777)@103
    assign rightShiftStage1Idx1Rng8_uid17778_dupName_182_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17777_dupName_182_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17780_dupName_182_i_unnamed_c_compstr0_shift_x(BITJOIN,17779)@103
    assign rightShiftStage1Idx1_uid17780_dupName_182_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17778_dupName_182_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17773_dupName_182_i_unnamed_c_compstr0_shift_x(BITSELECT,17772)@103
    assign rightShiftStage0Idx1Rng4_uid17773_dupName_182_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_q[33:4];

    // rightShiftStage0Idx1_uid17775_dupName_182_i_unnamed_c_compstr0_shift_x(BITJOIN,17774)@103
    assign rightShiftStage0Idx1_uid17775_dupName_182_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17773_dupName_182_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17777_dupName_182_i_unnamed_c_compstr0_shift_x(MUX,17776)@103
    assign rightShiftStage0_uid17777_dupName_182_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17777_dupName_182_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_q or rightShiftStage0Idx1_uid17775_dupName_182_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17777_dupName_182_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17777_dupName_182_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compstr1296_q;
            1'b1 : rightShiftStage0_uid17777_dupName_182_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17775_dupName_182_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17777_dupName_182_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17782_dupName_182_i_unnamed_c_compstr0_shift_x(MUX,17781)@103
    assign rightShiftStage1_uid17782_dupName_182_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17782_dupName_182_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17777_dupName_182_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17780_dupName_182_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17782_dupName_182_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17782_dupName_182_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17777_dupName_182_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17782_dupName_182_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17780_dupName_182_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17782_dupName_182_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1299_vt_select_21(BITSELECT,10061)@103
    assign i_unnamed_c_compstr1299_vt_select_21_b = rightShiftStage1_uid17782_dupName_182_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1299_vt_join(BITJOIN,10060)@103
    assign i_unnamed_c_compstr1299_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1299_vt_select_21_b};

    // i_unnamed_c_compstr1300_sel_x(BITSELECT,6058)@103
    assign i_unnamed_c_compstr1300_sel_x_b = i_unnamed_c_compstr1299_vt_join_q[15:0];

    // i_unnamed_c_compstr1301_BitSelect_for_a(BITSELECT,27505)@103
    assign i_unnamed_c_compstr1301_BitSelect_for_a_b = i_unnamed_c_compstr1300_sel_x_b[0:0];

    // i_unnamed_c_compstr1301_join(BITJOIN,27506)@103
    assign i_unnamed_c_compstr1301_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1301_BitSelect_for_a_b};

    // i_unnamed_c_compstr1301_vt_select_0(BITSELECT,10066)@103
    assign i_unnamed_c_compstr1301_vt_select_0_b = i_unnamed_c_compstr1301_join_q[0:0];

    // redist232_i_unnamed_c_compstr1301_vt_select_0_b_1(DELAY,28460)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist232_i_unnamed_c_compstr1301_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1301_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1301_vt_join(BITJOIN,10065)@104
    assign i_unnamed_c_compstr1301_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist232_i_unnamed_c_compstr1301_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_45_c_compstr1302(ADD,7046)@104
    assign i_add_i_i_i_i_i_i_45_c_compstr1302_a = {1'b0, i_unnamed_c_compstr1301_vt_join_q};
    assign i_add_i_i_i_i_i_i_45_c_compstr1302_b = {1'b0, redist1086_i_conv_i_i_i_i_i_45_c_compstr1298_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_45_c_compstr1302_o = $unsigned(i_add_i_i_i_i_i_i_45_c_compstr1302_a) + $unsigned(i_add_i_i_i_i_i_i_45_c_compstr1302_b);
    assign i_add_i_i_i_i_i_i_45_c_compstr1302_q = i_add_i_i_i_i_i_i_45_c_compstr1302_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_45_c_compstr1302_sel_x(BITSELECT,2240)@104
    assign bgTrunc_i_add_i_i_i_i_i_i_45_c_compstr1302_sel_x_b = i_add_i_i_i_i_i_i_45_c_compstr1302_q[15:0];

    // i_conv_i_i_i_i_i_i279_46_c_compstr1322_sel_x(BITSELECT,3908)@104
    assign i_conv_i_i_i_i_i_i279_46_c_compstr1322_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_45_c_compstr1302_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_46_c_compstr1322_vt_select_15(BITSELECT,8149)@104
    assign i_conv_i_i_i_i_i_i279_46_c_compstr1322_vt_select_15_b = i_conv_i_i_i_i_i_i279_46_c_compstr1322_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_46_c_compstr1322_vt_join(BITJOIN,8148)@104
    assign i_conv_i_i_i_i_i_i279_46_c_compstr1322_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_46_c_compstr1322_vt_select_15_b};

    // leftShiftStage0_uid26366_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x(MUX,26365)@104
    assign leftShiftStage0_uid26366_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26366_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_46_c_compstr1322_vt_join_q or leftShiftStage0Idx1_uid26364_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26366_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26366_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_46_c_compstr1322_vt_join_q;
            1'b1 : leftShiftStage0_uid26366_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26364_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26366_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26371_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x(MUX,26370)@104
    assign leftShiftStage1_uid26371_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26371_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_s or leftShiftStage0_uid26366_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26369_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26371_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26371_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q = leftShiftStage0_uid26366_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26371_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26369_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26371_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26376_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x(MUX,26375)@104
    assign leftShiftStage2_uid26376_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26376_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_s or leftShiftStage1_uid26371_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26374_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26376_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26376_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q = leftShiftStage1_uid26371_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26376_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26374_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26376_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_46_c_compstr1323_vt_select_28(BITSELECT,9625)@104
    assign i_shl_i_i_i_i_i_i_46_c_compstr1323_vt_select_28_b = leftShiftStage2_uid26376_i_shl_i_i_i_i_i_i_46_c_compstr0_shift_x_q[28:13];

    // redist315_i_shl_i_i_i_i_i_i_46_c_compstr1323_vt_select_28_b_1(DELAY,28543)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist315_i_shl_i_i_i_i_i_i_46_c_compstr1323_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_46_c_compstr1323_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_46_c_compstr1323_vt_join(BITJOIN,9624)@105
    assign i_shl_i_i_i_i_i_i_46_c_compstr1323_vt_join_q = {redist315_i_shl_i_i_i_i_i_i_46_c_compstr1323_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_offset(CONSTANT,30090)
    assign redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_offset_q = $unsigned(7'b0101010);

    // redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_rdcnt(ADD,31539)
    assign redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_a = {1'b0, redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_wraddr_q};
    assign redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_b = {1'b0, redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_o <= $unsigned(redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_a) + $unsigned(redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_b);
        end
    end
    assign redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_q = redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_o[7:0];

    // redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_inputreg0(DELAY,31534)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl);
        end
    end

    // redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_wraddr(COUNTER,31537)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_wraddr_i <= $unsigned(redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_wraddr_q = redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_wraddr_i[6:0];

    // redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem(DUALMEM,31536)
    assign redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_ia = $unsigned(redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_inputreg0_q);
    assign redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_aa = redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_wraddr_q;
    assign redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_ab = redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_aa),
        .data_a(redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_ab),
        .q_b(redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_q = redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_iq[15:0];

    // redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_outputreg0(DELAY,31535)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_outputreg0_q <= $unsigned(redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_mem_q);
        end
    end

    // redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_rdcnt(ADD,30091)
    assign redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_a = {1'b0, redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_wraddr_q};
    assign redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_b = {1'b0, redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_o <= $unsigned(redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_a) + $unsigned(redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_b);
        end
    end
    assign redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_q = redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_o[7:0];

    // redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_inputreg0(DELAY,30086)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl);
        end
    end

    // redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_wraddr(COUNTER,30089)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_wraddr_i <= $unsigned(redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_wraddr_q = redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_wraddr_i[6:0];

    // redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem(DUALMEM,30088)
    assign redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_ia = $unsigned(redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_inputreg0_q);
    assign redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_aa = redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_wraddr_q;
    assign redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_ab = redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_aa),
        .data_a(redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_ab),
        .q_b(redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_q = redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_iq[15:0];

    // redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_outputreg0(DELAY,30087)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_outputreg0_q <= $unsigned(redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_mem_q);
        end
    end

    // redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_rdcnt(ADD,30097)
    assign redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_a = {1'b0, redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_wraddr_q};
    assign redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_b = {1'b0, redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_o <= $unsigned(redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_a) + $unsigned(redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_b);
        end
    end
    assign redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_q = redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_o[7:0];

    // redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_inputreg0(DELAY,30092)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl);
        end
    end

    // redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_wraddr(COUNTER,30095)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_wraddr_i <= $unsigned(redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_wraddr_q = redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_wraddr_i[6:0];

    // redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem(DUALMEM,30094)
    assign redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_ia = $unsigned(redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_inputreg0_q);
    assign redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_aa = redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_wraddr_q;
    assign redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_ab = redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_aa),
        .data_a(redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_ab),
        .q_b(redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_q = redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_iq[15:0];

    // redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_outputreg0(DELAY,30093)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_outputreg0_q <= $unsigned(redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_mem_q);
        end
    end

    // redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_rdcnt(ADD,31533)
    assign redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_a = {1'b0, redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_wraddr_q};
    assign redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_b = {1'b0, redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_o <= $unsigned(redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_a) + $unsigned(redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_b);
        end
    end
    assign redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_q = redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_o[7:0];

    // redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_inputreg0(DELAY,31528)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl);
        end
    end

    // redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_wraddr(COUNTER,31531)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_wraddr_i <= $unsigned(redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_wraddr_q = redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_wraddr_i[6:0];

    // redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem(DUALMEM,31530)
    assign redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_ia = $unsigned(redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_inputreg0_q);
    assign redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_aa = redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_wraddr_q;
    assign redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_ab = redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_aa),
        .data_a(redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_ab),
        .q_b(redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_q = redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_iq[15:0];

    // redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_outputreg0(DELAY,31529)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_outputreg0_q <= $unsigned(redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28005)@99 + 5
    // out q@105
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324(ADD,8589)@105
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod271_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_b = $unsigned({{5{i_shl_i_i_i_i_i_i_46_c_compstr1323_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_46_c_compstr1323_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_o[33:0];

    // rightShiftStage0_uid17821_dupName_185_i_unnamed_c_compstr0_shift_x(MUX,17820)@105
    assign rightShiftStage0_uid17821_dupName_185_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17821_dupName_185_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_q or rightShiftStage0Idx1_uid17819_dupName_185_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17821_dupName_185_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17821_dupName_185_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_q;
            1'b1 : rightShiftStage0_uid17821_dupName_185_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17819_dupName_185_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17821_dupName_185_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17826_dupName_185_i_unnamed_c_compstr0_shift_x(MUX,17825)@105
    assign rightShiftStage1_uid17826_dupName_185_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17826_dupName_185_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17821_dupName_185_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17824_dupName_185_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17826_dupName_185_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17826_dupName_185_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17821_dupName_185_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17826_dupName_185_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17824_dupName_185_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17826_dupName_185_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17831_dupName_185_i_unnamed_c_compstr0_shift_x(MUX,17830)@105
    assign rightShiftStage2_uid17831_dupName_185_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17831_dupName_185_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17826_dupName_185_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17829_dupName_185_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17831_dupName_185_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17831_dupName_185_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17826_dupName_185_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17831_dupName_185_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17829_dupName_185_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17831_dupName_185_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1325_vt_select_20(BITSELECT,10080)@105
    assign i_unnamed_c_compstr1325_vt_select_20_b = rightShiftStage2_uid17831_dupName_185_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1325_vt_join(BITJOIN,10079)@105
    assign i_unnamed_c_compstr1325_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1325_vt_select_20_b};

    // i_conv_i_i_i_i_i_46_c_compstr1326_sel_x(BITSELECT,3780)@105
    assign i_conv_i_i_i_i_i_46_c_compstr1326_sel_x_b = i_unnamed_c_compstr1325_vt_join_q[15:0];

    // redist1085_i_conv_i_i_i_i_i_46_c_compstr1326_sel_x_b_1(DELAY,29313)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1085_i_conv_i_i_i_i_i_46_c_compstr1326_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_46_c_compstr1326_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17840_dupName_186_i_unnamed_c_compstr0_shift_x(BITSELECT,17839)@105
    assign rightShiftStage1Idx1Rng8_uid17840_dupName_186_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17839_dupName_186_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17842_dupName_186_i_unnamed_c_compstr0_shift_x(BITJOIN,17841)@105
    assign rightShiftStage1Idx1_uid17842_dupName_186_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17840_dupName_186_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17835_dupName_186_i_unnamed_c_compstr0_shift_x(BITSELECT,17834)@105
    assign rightShiftStage0Idx1Rng4_uid17835_dupName_186_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_q[33:4];

    // rightShiftStage0Idx1_uid17837_dupName_186_i_unnamed_c_compstr0_shift_x(BITJOIN,17836)@105
    assign rightShiftStage0Idx1_uid17837_dupName_186_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17835_dupName_186_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17839_dupName_186_i_unnamed_c_compstr0_shift_x(MUX,17838)@105
    assign rightShiftStage0_uid17839_dupName_186_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17839_dupName_186_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_q or rightShiftStage0Idx1_uid17837_dupName_186_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17839_dupName_186_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17839_dupName_186_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compstr1324_q;
            1'b1 : rightShiftStage0_uid17839_dupName_186_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17837_dupName_186_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17839_dupName_186_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17844_dupName_186_i_unnamed_c_compstr0_shift_x(MUX,17843)@105
    assign rightShiftStage1_uid17844_dupName_186_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17844_dupName_186_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17839_dupName_186_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17842_dupName_186_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17844_dupName_186_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17844_dupName_186_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17839_dupName_186_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17844_dupName_186_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17842_dupName_186_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17844_dupName_186_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1327_vt_select_21(BITSELECT,10083)@105
    assign i_unnamed_c_compstr1327_vt_select_21_b = rightShiftStage1_uid17844_dupName_186_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1327_vt_join(BITJOIN,10082)@105
    assign i_unnamed_c_compstr1327_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1327_vt_select_21_b};

    // i_unnamed_c_compstr1328_sel_x(BITSELECT,6060)@105
    assign i_unnamed_c_compstr1328_sel_x_b = i_unnamed_c_compstr1327_vt_join_q[15:0];

    // i_unnamed_c_compstr1329_BitSelect_for_a(BITSELECT,27509)@105
    assign i_unnamed_c_compstr1329_BitSelect_for_a_b = i_unnamed_c_compstr1328_sel_x_b[0:0];

    // i_unnamed_c_compstr1329_join(BITJOIN,27510)@105
    assign i_unnamed_c_compstr1329_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1329_BitSelect_for_a_b};

    // i_unnamed_c_compstr1329_vt_select_0(BITSELECT,10088)@105
    assign i_unnamed_c_compstr1329_vt_select_0_b = i_unnamed_c_compstr1329_join_q[0:0];

    // redist230_i_unnamed_c_compstr1329_vt_select_0_b_1(DELAY,28458)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist230_i_unnamed_c_compstr1329_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1329_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1329_vt_join(BITJOIN,10087)@106
    assign i_unnamed_c_compstr1329_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist230_i_unnamed_c_compstr1329_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_46_c_compstr1330(ADD,7047)@106
    assign i_add_i_i_i_i_i_i_46_c_compstr1330_a = {1'b0, i_unnamed_c_compstr1329_vt_join_q};
    assign i_add_i_i_i_i_i_i_46_c_compstr1330_b = {1'b0, redist1085_i_conv_i_i_i_i_i_46_c_compstr1326_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_46_c_compstr1330_o = $unsigned(i_add_i_i_i_i_i_i_46_c_compstr1330_a) + $unsigned(i_add_i_i_i_i_i_i_46_c_compstr1330_b);
    assign i_add_i_i_i_i_i_i_46_c_compstr1330_q = i_add_i_i_i_i_i_i_46_c_compstr1330_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_46_c_compstr1330_sel_x(BITSELECT,2241)@106
    assign bgTrunc_i_add_i_i_i_i_i_i_46_c_compstr1330_sel_x_b = i_add_i_i_i_i_i_i_46_c_compstr1330_q[15:0];

    // i_conv_i_i_i_i_i_i279_47_c_compstr1350_sel_x(BITSELECT,3909)@106
    assign i_conv_i_i_i_i_i_i279_47_c_compstr1350_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_46_c_compstr1330_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_47_c_compstr1350_vt_select_15(BITSELECT,8153)@106
    assign i_conv_i_i_i_i_i_i279_47_c_compstr1350_vt_select_15_b = i_conv_i_i_i_i_i_i279_47_c_compstr1350_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_47_c_compstr1350_vt_join(BITJOIN,8152)@106
    assign i_conv_i_i_i_i_i_i279_47_c_compstr1350_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_47_c_compstr1350_vt_select_15_b};

    // leftShiftStage0_uid26384_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x(MUX,26383)@106
    assign leftShiftStage0_uid26384_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26384_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_47_c_compstr1350_vt_join_q or leftShiftStage0Idx1_uid26382_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26384_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26384_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_47_c_compstr1350_vt_join_q;
            1'b1 : leftShiftStage0_uid26384_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26382_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26384_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26389_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x(MUX,26388)@106
    assign leftShiftStage1_uid26389_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26389_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_s or leftShiftStage0_uid26384_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26387_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26389_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26389_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q = leftShiftStage0_uid26384_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26389_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26387_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26389_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26394_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x(MUX,26393)@106
    assign leftShiftStage2_uid26394_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26394_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_s or leftShiftStage1_uid26389_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26392_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26394_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26394_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q = leftShiftStage1_uid26389_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26394_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26392_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26394_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_47_c_compstr1351_vt_select_28(BITSELECT,9628)@106
    assign i_shl_i_i_i_i_i_i_47_c_compstr1351_vt_select_28_b = leftShiftStage2_uid26394_i_shl_i_i_i_i_i_i_47_c_compstr0_shift_x_q[28:13];

    // redist314_i_shl_i_i_i_i_i_i_47_c_compstr1351_vt_select_28_b_1(DELAY,28542)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist314_i_shl_i_i_i_i_i_i_47_c_compstr1351_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_47_c_compstr1351_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_47_c_compstr1351_vt_join(BITJOIN,9627)@107
    assign i_shl_i_i_i_i_i_i_47_c_compstr1351_vt_join_q = {redist314_i_shl_i_i_i_i_i_i_47_c_compstr1351_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_offset(CONSTANT,30102)
    assign redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_offset_q = $unsigned(7'b0101000);

    // redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_rdcnt(ADD,31551)
    assign redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_a = {1'b0, redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_wraddr_q};
    assign redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_b = {1'b0, redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_o <= $unsigned(redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_a) + $unsigned(redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_b);
        end
    end
    assign redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_q = redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_o[7:0];

    // redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_inputreg0(DELAY,31546)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl);
        end
    end

    // redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_wraddr(COUNTER,31549)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_wraddr_i <= $unsigned(redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_wraddr_q = redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_wraddr_i[6:0];

    // redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem(DUALMEM,31548)
    assign redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_ia = $unsigned(redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_inputreg0_q);
    assign redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_aa = redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_wraddr_q;
    assign redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_ab = redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_aa),
        .data_a(redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_ab),
        .q_b(redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_q = redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_iq[15:0];

    // redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_outputreg0(DELAY,31547)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_outputreg0_q <= $unsigned(redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_mem_q);
        end
    end

    // redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_rdcnt(ADD,30103)
    assign redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_a = {1'b0, redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_wraddr_q};
    assign redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_b = {1'b0, redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_o <= $unsigned(redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_a) + $unsigned(redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_b);
        end
    end
    assign redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_q = redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_o[7:0];

    // redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_inputreg0(DELAY,30098)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl);
        end
    end

    // redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_wraddr(COUNTER,30101)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_wraddr_i <= $unsigned(redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_wraddr_q = redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_wraddr_i[6:0];

    // redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem(DUALMEM,30100)
    assign redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_ia = $unsigned(redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_inputreg0_q);
    assign redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_aa = redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_wraddr_q;
    assign redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_ab = redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_aa),
        .data_a(redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_ab),
        .q_b(redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_q = redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_iq[15:0];

    // redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_outputreg0(DELAY,30099)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_outputreg0_q <= $unsigned(redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_mem_q);
        end
    end

    // redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_rdcnt(ADD,30109)
    assign redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_a = {1'b0, redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_wraddr_q};
    assign redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_b = {1'b0, redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_o <= $unsigned(redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_a) + $unsigned(redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_b);
        end
    end
    assign redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_q = redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_o[7:0];

    // redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_inputreg0(DELAY,30104)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl);
        end
    end

    // redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_wraddr(COUNTER,30107)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_wraddr_i <= $unsigned(redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_wraddr_q = redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_wraddr_i[6:0];

    // redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem(DUALMEM,30106)
    assign redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_ia = $unsigned(redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_inputreg0_q);
    assign redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_aa = redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_wraddr_q;
    assign redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_ab = redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_aa),
        .data_a(redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_ab),
        .q_b(redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_q = redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_iq[15:0];

    // redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_outputreg0(DELAY,30105)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_outputreg0_q <= $unsigned(redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_mem_q);
        end
    end

    // redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_rdcnt(ADD,31545)
    assign redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_a = {1'b0, redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_wraddr_q};
    assign redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_b = {1'b0, redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_o <= $unsigned(redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_a) + $unsigned(redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_b);
        end
    end
    assign redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_q = redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_o[7:0];

    // redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_inputreg0(DELAY,31540)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl);
        end
    end

    // redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_wraddr(COUNTER,31543)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_wraddr_i <= $unsigned(redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_wraddr_q = redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_wraddr_i[6:0];

    // redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem(DUALMEM,31542)
    assign redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_ia = $unsigned(redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_inputreg0_q);
    assign redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_aa = redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_wraddr_q;
    assign redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_ab = redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_aa),
        .data_a(redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_ab),
        .q_b(redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_q = redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_iq[15:0];

    // redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_outputreg0(DELAY,31541)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_outputreg0_q <= $unsigned(redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28006)@101 + 5
    // out q@107
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352(ADD,8590)@107
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod276_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_b = $unsigned({{5{i_shl_i_i_i_i_i_i_47_c_compstr1351_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_47_c_compstr1351_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_o[33:0];

    // rightShiftStage0_uid17883_dupName_189_i_unnamed_c_compstr0_shift_x(MUX,17882)@107
    assign rightShiftStage0_uid17883_dupName_189_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17883_dupName_189_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_q or rightShiftStage0Idx1_uid17881_dupName_189_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17883_dupName_189_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17883_dupName_189_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_q;
            1'b1 : rightShiftStage0_uid17883_dupName_189_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17881_dupName_189_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17883_dupName_189_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17888_dupName_189_i_unnamed_c_compstr0_shift_x(MUX,17887)@107
    assign rightShiftStage1_uid17888_dupName_189_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17888_dupName_189_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17883_dupName_189_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17886_dupName_189_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17888_dupName_189_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17888_dupName_189_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17883_dupName_189_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17888_dupName_189_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17886_dupName_189_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17888_dupName_189_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17893_dupName_189_i_unnamed_c_compstr0_shift_x(MUX,17892)@107
    assign rightShiftStage2_uid17893_dupName_189_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17893_dupName_189_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17888_dupName_189_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17891_dupName_189_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17893_dupName_189_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17893_dupName_189_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17888_dupName_189_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17893_dupName_189_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17891_dupName_189_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17893_dupName_189_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1353_vt_select_20(BITSELECT,10105)@107
    assign i_unnamed_c_compstr1353_vt_select_20_b = rightShiftStage2_uid17893_dupName_189_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1353_vt_join(BITJOIN,10104)@107
    assign i_unnamed_c_compstr1353_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1353_vt_select_20_b};

    // i_conv_i_i_i_i_i_47_c_compstr1354_sel_x(BITSELECT,3781)@107
    assign i_conv_i_i_i_i_i_47_c_compstr1354_sel_x_b = i_unnamed_c_compstr1353_vt_join_q[15:0];

    // redist1084_i_conv_i_i_i_i_i_47_c_compstr1354_sel_x_b_1(DELAY,29312)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1084_i_conv_i_i_i_i_i_47_c_compstr1354_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_47_c_compstr1354_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17902_dupName_190_i_unnamed_c_compstr0_shift_x(BITSELECT,17901)@107
    assign rightShiftStage1Idx1Rng8_uid17902_dupName_190_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17901_dupName_190_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17904_dupName_190_i_unnamed_c_compstr0_shift_x(BITJOIN,17903)@107
    assign rightShiftStage1Idx1_uid17904_dupName_190_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17902_dupName_190_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17897_dupName_190_i_unnamed_c_compstr0_shift_x(BITSELECT,17896)@107
    assign rightShiftStage0Idx1Rng4_uid17897_dupName_190_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_q[33:4];

    // rightShiftStage0Idx1_uid17899_dupName_190_i_unnamed_c_compstr0_shift_x(BITJOIN,17898)@107
    assign rightShiftStage0Idx1_uid17899_dupName_190_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17897_dupName_190_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17901_dupName_190_i_unnamed_c_compstr0_shift_x(MUX,17900)@107
    assign rightShiftStage0_uid17901_dupName_190_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17901_dupName_190_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_q or rightShiftStage0Idx1_uid17899_dupName_190_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17901_dupName_190_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17901_dupName_190_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compstr1352_q;
            1'b1 : rightShiftStage0_uid17901_dupName_190_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17899_dupName_190_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17901_dupName_190_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17906_dupName_190_i_unnamed_c_compstr0_shift_x(MUX,17905)@107
    assign rightShiftStage1_uid17906_dupName_190_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17906_dupName_190_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17901_dupName_190_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17904_dupName_190_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17906_dupName_190_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17906_dupName_190_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17901_dupName_190_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17906_dupName_190_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17904_dupName_190_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17906_dupName_190_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1355_vt_select_21(BITSELECT,10108)@107
    assign i_unnamed_c_compstr1355_vt_select_21_b = rightShiftStage1_uid17906_dupName_190_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1355_vt_join(BITJOIN,10107)@107
    assign i_unnamed_c_compstr1355_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1355_vt_select_21_b};

    // i_unnamed_c_compstr1356_sel_x(BITSELECT,6062)@107
    assign i_unnamed_c_compstr1356_sel_x_b = i_unnamed_c_compstr1355_vt_join_q[15:0];

    // i_unnamed_c_compstr1357_BitSelect_for_a(BITSELECT,27513)@107
    assign i_unnamed_c_compstr1357_BitSelect_for_a_b = i_unnamed_c_compstr1356_sel_x_b[0:0];

    // i_unnamed_c_compstr1357_join(BITJOIN,27514)@107
    assign i_unnamed_c_compstr1357_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1357_BitSelect_for_a_b};

    // i_unnamed_c_compstr1357_vt_select_0(BITSELECT,10113)@107
    assign i_unnamed_c_compstr1357_vt_select_0_b = i_unnamed_c_compstr1357_join_q[0:0];

    // redist228_i_unnamed_c_compstr1357_vt_select_0_b_1(DELAY,28456)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist228_i_unnamed_c_compstr1357_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1357_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1357_vt_join(BITJOIN,10112)@108
    assign i_unnamed_c_compstr1357_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist228_i_unnamed_c_compstr1357_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_47_c_compstr1358(ADD,7048)@108
    assign i_add_i_i_i_i_i_i_47_c_compstr1358_a = {1'b0, i_unnamed_c_compstr1357_vt_join_q};
    assign i_add_i_i_i_i_i_i_47_c_compstr1358_b = {1'b0, redist1084_i_conv_i_i_i_i_i_47_c_compstr1354_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_47_c_compstr1358_o = $unsigned(i_add_i_i_i_i_i_i_47_c_compstr1358_a) + $unsigned(i_add_i_i_i_i_i_i_47_c_compstr1358_b);
    assign i_add_i_i_i_i_i_i_47_c_compstr1358_q = i_add_i_i_i_i_i_i_47_c_compstr1358_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_47_c_compstr1358_sel_x(BITSELECT,2242)@108
    assign bgTrunc_i_add_i_i_i_i_i_i_47_c_compstr1358_sel_x_b = i_add_i_i_i_i_i_i_47_c_compstr1358_q[15:0];

    // i_conv_i_i_i_i_i_i279_48_c_compstr1378_sel_x(BITSELECT,3910)@108
    assign i_conv_i_i_i_i_i_i279_48_c_compstr1378_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_47_c_compstr1358_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_48_c_compstr1378_vt_select_15(BITSELECT,8157)@108
    assign i_conv_i_i_i_i_i_i279_48_c_compstr1378_vt_select_15_b = i_conv_i_i_i_i_i_i279_48_c_compstr1378_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_48_c_compstr1378_vt_join(BITJOIN,8156)@108
    assign i_conv_i_i_i_i_i_i279_48_c_compstr1378_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_48_c_compstr1378_vt_select_15_b};

    // leftShiftStage0_uid26402_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x(MUX,26401)@108
    assign leftShiftStage0_uid26402_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26402_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_48_c_compstr1378_vt_join_q or leftShiftStage0Idx1_uid26400_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26402_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26402_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_48_c_compstr1378_vt_join_q;
            1'b1 : leftShiftStage0_uid26402_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26400_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26402_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26407_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x(MUX,26406)@108
    assign leftShiftStage1_uid26407_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26407_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_s or leftShiftStage0_uid26402_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26405_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26407_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26407_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q = leftShiftStage0_uid26402_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26407_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26405_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26407_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26412_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x(MUX,26411)@108
    assign leftShiftStage2_uid26412_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26412_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_s or leftShiftStage1_uid26407_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26410_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26412_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26412_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q = leftShiftStage1_uid26407_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26412_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26410_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26412_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_48_c_compstr1379_vt_select_28(BITSELECT,9631)@108
    assign i_shl_i_i_i_i_i_i_48_c_compstr1379_vt_select_28_b = leftShiftStage2_uid26412_i_shl_i_i_i_i_i_i_48_c_compstr0_shift_x_q[28:13];

    // redist313_i_shl_i_i_i_i_i_i_48_c_compstr1379_vt_select_28_b_1(DELAY,28541)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist313_i_shl_i_i_i_i_i_i_48_c_compstr1379_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_48_c_compstr1379_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_48_c_compstr1379_vt_join(BITJOIN,9630)@109
    assign i_shl_i_i_i_i_i_i_48_c_compstr1379_vt_join_q = {redist313_i_shl_i_i_i_i_i_i_48_c_compstr1379_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_offset(CONSTANT,30114)
    assign redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_offset_q = $unsigned(7'b0100110);

    // redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_rdcnt(ADD,31563)
    assign redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_a = {1'b0, redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_wraddr_q};
    assign redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_b = {1'b0, redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_o <= $unsigned(redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_a) + $unsigned(redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_b);
        end
    end
    assign redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_q = redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_o[7:0];

    // redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_inputreg0(DELAY,31558)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl);
        end
    end

    // redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_wraddr(COUNTER,31561)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_wraddr_i <= $unsigned(redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_wraddr_q = redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_wraddr_i[6:0];

    // redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem(DUALMEM,31560)
    assign redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_ia = $unsigned(redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_inputreg0_q);
    assign redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_aa = redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_wraddr_q;
    assign redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_ab = redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_aa),
        .data_a(redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_ab),
        .q_b(redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_q = redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_iq[15:0];

    // redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_outputreg0(DELAY,31559)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_outputreg0_q <= $unsigned(redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_mem_q);
        end
    end

    // redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_rdcnt(ADD,30115)
    assign redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_a = {1'b0, redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_wraddr_q};
    assign redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_b = {1'b0, redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_o <= $unsigned(redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_a) + $unsigned(redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_b);
        end
    end
    assign redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_q = redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_o[7:0];

    // redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_inputreg0(DELAY,30110)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl);
        end
    end

    // redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_wraddr(COUNTER,30113)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_wraddr_i <= $unsigned(redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_wraddr_q = redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_wraddr_i[6:0];

    // redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem(DUALMEM,30112)
    assign redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_ia = $unsigned(redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_inputreg0_q);
    assign redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_aa = redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_wraddr_q;
    assign redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_ab = redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_aa),
        .data_a(redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_ab),
        .q_b(redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_q = redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_iq[15:0];

    // redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_outputreg0(DELAY,30111)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_outputreg0_q <= $unsigned(redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_mem_q);
        end
    end

    // redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_rdcnt(ADD,30121)
    assign redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_a = {1'b0, redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_wraddr_q};
    assign redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_b = {1'b0, redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_o <= $unsigned(redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_a) + $unsigned(redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_b);
        end
    end
    assign redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_q = redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_o[7:0];

    // redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_inputreg0(DELAY,30116)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl);
        end
    end

    // redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_wraddr(COUNTER,30119)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_wraddr_i <= $unsigned(redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_wraddr_q = redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_wraddr_i[6:0];

    // redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem(DUALMEM,30118)
    assign redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_ia = $unsigned(redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_inputreg0_q);
    assign redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_aa = redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_wraddr_q;
    assign redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_ab = redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_aa),
        .data_a(redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_ab),
        .q_b(redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_q = redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_iq[15:0];

    // redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_outputreg0(DELAY,30117)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_outputreg0_q <= $unsigned(redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_mem_q);
        end
    end

    // redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_rdcnt(ADD,31557)
    assign redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_a = {1'b0, redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_wraddr_q};
    assign redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_b = {1'b0, redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_o <= $unsigned(redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_a) + $unsigned(redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_b);
        end
    end
    assign redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_q = redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_o[7:0];

    // redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_inputreg0(DELAY,31552)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl);
        end
    end

    // redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_wraddr(COUNTER,31555)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_wraddr_i <= $unsigned(redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_wraddr_q = redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_wraddr_i[6:0];

    // redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem(DUALMEM,31554)
    assign redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_ia = $unsigned(redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_inputreg0_q);
    assign redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_aa = redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_wraddr_q;
    assign redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_ab = redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_aa),
        .data_a(redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_ab),
        .q_b(redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_q = redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_iq[15:0];

    // redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_outputreg0(DELAY,31553)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_outputreg0_q <= $unsigned(redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28007)@103 + 5
    // out q@109
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380(ADD,8591)@109
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod281_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_b = $unsigned({{5{i_shl_i_i_i_i_i_i_48_c_compstr1379_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_48_c_compstr1379_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_o[33:0];

    // rightShiftStage0_uid17945_dupName_193_i_unnamed_c_compstr0_shift_x(MUX,17944)@109
    assign rightShiftStage0_uid17945_dupName_193_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17945_dupName_193_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_q or rightShiftStage0Idx1_uid17943_dupName_193_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17945_dupName_193_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17945_dupName_193_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_q;
            1'b1 : rightShiftStage0_uid17945_dupName_193_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17943_dupName_193_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17945_dupName_193_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17950_dupName_193_i_unnamed_c_compstr0_shift_x(MUX,17949)@109
    assign rightShiftStage1_uid17950_dupName_193_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17950_dupName_193_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17945_dupName_193_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17948_dupName_193_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17950_dupName_193_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17950_dupName_193_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17945_dupName_193_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17950_dupName_193_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17948_dupName_193_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17950_dupName_193_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17955_dupName_193_i_unnamed_c_compstr0_shift_x(MUX,17954)@109
    assign rightShiftStage2_uid17955_dupName_193_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17955_dupName_193_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17950_dupName_193_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17953_dupName_193_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17955_dupName_193_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17955_dupName_193_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17950_dupName_193_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17955_dupName_193_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17953_dupName_193_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17955_dupName_193_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1381_vt_select_20(BITSELECT,10135)@109
    assign i_unnamed_c_compstr1381_vt_select_20_b = rightShiftStage2_uid17955_dupName_193_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1381_vt_join(BITJOIN,10134)@109
    assign i_unnamed_c_compstr1381_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1381_vt_select_20_b};

    // i_conv_i_i_i_i_i_48_c_compstr1382_sel_x(BITSELECT,3782)@109
    assign i_conv_i_i_i_i_i_48_c_compstr1382_sel_x_b = i_unnamed_c_compstr1381_vt_join_q[15:0];

    // redist1083_i_conv_i_i_i_i_i_48_c_compstr1382_sel_x_b_1(DELAY,29311)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1083_i_conv_i_i_i_i_i_48_c_compstr1382_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_48_c_compstr1382_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17964_dupName_194_i_unnamed_c_compstr0_shift_x(BITSELECT,17963)@109
    assign rightShiftStage1Idx1Rng8_uid17964_dupName_194_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17963_dupName_194_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17966_dupName_194_i_unnamed_c_compstr0_shift_x(BITJOIN,17965)@109
    assign rightShiftStage1Idx1_uid17966_dupName_194_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17964_dupName_194_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17959_dupName_194_i_unnamed_c_compstr0_shift_x(BITSELECT,17958)@109
    assign rightShiftStage0Idx1Rng4_uid17959_dupName_194_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_q[33:4];

    // rightShiftStage0Idx1_uid17961_dupName_194_i_unnamed_c_compstr0_shift_x(BITJOIN,17960)@109
    assign rightShiftStage0Idx1_uid17961_dupName_194_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17959_dupName_194_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17963_dupName_194_i_unnamed_c_compstr0_shift_x(MUX,17962)@109
    assign rightShiftStage0_uid17963_dupName_194_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17963_dupName_194_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_q or rightShiftStage0Idx1_uid17961_dupName_194_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17963_dupName_194_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17963_dupName_194_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compstr1380_q;
            1'b1 : rightShiftStage0_uid17963_dupName_194_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17961_dupName_194_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17963_dupName_194_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17968_dupName_194_i_unnamed_c_compstr0_shift_x(MUX,17967)@109
    assign rightShiftStage1_uid17968_dupName_194_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17968_dupName_194_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17963_dupName_194_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17966_dupName_194_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17968_dupName_194_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17968_dupName_194_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17963_dupName_194_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17968_dupName_194_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17966_dupName_194_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17968_dupName_194_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1383_vt_select_21(BITSELECT,10138)@109
    assign i_unnamed_c_compstr1383_vt_select_21_b = rightShiftStage1_uid17968_dupName_194_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1383_vt_join(BITJOIN,10137)@109
    assign i_unnamed_c_compstr1383_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1383_vt_select_21_b};

    // i_unnamed_c_compstr1384_sel_x(BITSELECT,6065)@109
    assign i_unnamed_c_compstr1384_sel_x_b = i_unnamed_c_compstr1383_vt_join_q[15:0];

    // i_unnamed_c_compstr1385_BitSelect_for_a(BITSELECT,27519)@109
    assign i_unnamed_c_compstr1385_BitSelect_for_a_b = i_unnamed_c_compstr1384_sel_x_b[0:0];

    // i_unnamed_c_compstr1385_join(BITJOIN,27520)@109
    assign i_unnamed_c_compstr1385_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1385_BitSelect_for_a_b};

    // i_unnamed_c_compstr1385_vt_select_0(BITSELECT,10143)@109
    assign i_unnamed_c_compstr1385_vt_select_0_b = i_unnamed_c_compstr1385_join_q[0:0];

    // redist225_i_unnamed_c_compstr1385_vt_select_0_b_1(DELAY,28453)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist225_i_unnamed_c_compstr1385_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1385_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1385_vt_join(BITJOIN,10142)@110
    assign i_unnamed_c_compstr1385_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist225_i_unnamed_c_compstr1385_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_48_c_compstr1386(ADD,7049)@110
    assign i_add_i_i_i_i_i_i_48_c_compstr1386_a = {1'b0, i_unnamed_c_compstr1385_vt_join_q};
    assign i_add_i_i_i_i_i_i_48_c_compstr1386_b = {1'b0, redist1083_i_conv_i_i_i_i_i_48_c_compstr1382_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_48_c_compstr1386_o = $unsigned(i_add_i_i_i_i_i_i_48_c_compstr1386_a) + $unsigned(i_add_i_i_i_i_i_i_48_c_compstr1386_b);
    assign i_add_i_i_i_i_i_i_48_c_compstr1386_q = i_add_i_i_i_i_i_i_48_c_compstr1386_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_48_c_compstr1386_sel_x(BITSELECT,2243)@110
    assign bgTrunc_i_add_i_i_i_i_i_i_48_c_compstr1386_sel_x_b = i_add_i_i_i_i_i_i_48_c_compstr1386_q[15:0];

    // i_conv_i_i_i_i_i_i279_49_c_compstr1406_sel_x(BITSELECT,3911)@110
    assign i_conv_i_i_i_i_i_i279_49_c_compstr1406_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_48_c_compstr1386_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_49_c_compstr1406_vt_select_15(BITSELECT,8161)@110
    assign i_conv_i_i_i_i_i_i279_49_c_compstr1406_vt_select_15_b = i_conv_i_i_i_i_i_i279_49_c_compstr1406_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_49_c_compstr1406_vt_join(BITJOIN,8160)@110
    assign i_conv_i_i_i_i_i_i279_49_c_compstr1406_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_49_c_compstr1406_vt_select_15_b};

    // leftShiftStage0_uid26420_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x(MUX,26419)@110
    assign leftShiftStage0_uid26420_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26420_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_49_c_compstr1406_vt_join_q or leftShiftStage0Idx1_uid26418_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26420_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26420_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_49_c_compstr1406_vt_join_q;
            1'b1 : leftShiftStage0_uid26420_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26418_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26420_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26425_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x(MUX,26424)@110
    assign leftShiftStage1_uid26425_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26425_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_s or leftShiftStage0_uid26420_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26423_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26425_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26425_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q = leftShiftStage0_uid26420_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26425_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26423_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26425_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26430_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x(MUX,26429)@110
    assign leftShiftStage2_uid26430_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26430_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_s or leftShiftStage1_uid26425_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26428_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26430_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26430_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q = leftShiftStage1_uid26425_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26430_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26428_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26430_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_49_c_compstr1407_vt_select_28(BITSELECT,9634)@110
    assign i_shl_i_i_i_i_i_i_49_c_compstr1407_vt_select_28_b = leftShiftStage2_uid26430_i_shl_i_i_i_i_i_i_49_c_compstr0_shift_x_q[28:13];

    // redist312_i_shl_i_i_i_i_i_i_49_c_compstr1407_vt_select_28_b_1(DELAY,28540)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist312_i_shl_i_i_i_i_i_i_49_c_compstr1407_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_49_c_compstr1407_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_49_c_compstr1407_vt_join(BITJOIN,9633)@111
    assign i_shl_i_i_i_i_i_i_49_c_compstr1407_vt_join_q = {redist312_i_shl_i_i_i_i_i_i_49_c_compstr1407_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_offset(CONSTANT,30126)
    assign redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_offset_q = $unsigned(7'b0100100);

    // redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_rdcnt(ADD,31575)
    assign redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_a = {1'b0, redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_wraddr_q};
    assign redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_b = {1'b0, redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_o <= $unsigned(redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_a) + $unsigned(redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_b);
        end
    end
    assign redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_q = redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_o[7:0];

    // redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_inputreg0(DELAY,31570)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl);
        end
    end

    // redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_wraddr(COUNTER,31573)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_wraddr_i <= $unsigned(redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_wraddr_q = redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_wraddr_i[6:0];

    // redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem(DUALMEM,31572)
    assign redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_ia = $unsigned(redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_inputreg0_q);
    assign redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_aa = redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_wraddr_q;
    assign redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_ab = redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_aa),
        .data_a(redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_ab),
        .q_b(redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_q = redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_iq[15:0];

    // redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_outputreg0(DELAY,31571)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_outputreg0_q <= $unsigned(redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_mem_q);
        end
    end

    // redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_rdcnt(ADD,30127)
    assign redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_a = {1'b0, redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_wraddr_q};
    assign redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_b = {1'b0, redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_o <= $unsigned(redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_a) + $unsigned(redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_b);
        end
    end
    assign redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_q = redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_o[7:0];

    // redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_inputreg0(DELAY,30122)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl);
        end
    end

    // redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_wraddr(COUNTER,30125)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_wraddr_i <= $unsigned(redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_wraddr_q = redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_wraddr_i[6:0];

    // redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem(DUALMEM,30124)
    assign redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_ia = $unsigned(redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_inputreg0_q);
    assign redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_aa = redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_wraddr_q;
    assign redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_ab = redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_aa),
        .data_a(redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_ab),
        .q_b(redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_q = redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_iq[15:0];

    // redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_outputreg0(DELAY,30123)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_outputreg0_q <= $unsigned(redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_mem_q);
        end
    end

    // redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_rdcnt(ADD,30133)
    assign redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_a = {1'b0, redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_wraddr_q};
    assign redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_b = {1'b0, redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_o <= $unsigned(redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_a) + $unsigned(redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_b);
        end
    end
    assign redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_q = redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_o[7:0];

    // redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_inputreg0(DELAY,30128)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl);
        end
    end

    // redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_wraddr(COUNTER,30131)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_wraddr_i <= $unsigned(redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_wraddr_q = redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_wraddr_i[6:0];

    // redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem(DUALMEM,30130)
    assign redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_ia = $unsigned(redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_inputreg0_q);
    assign redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_aa = redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_wraddr_q;
    assign redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_ab = redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_aa),
        .data_a(redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_ab),
        .q_b(redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_q = redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_iq[15:0];

    // redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_outputreg0(DELAY,30129)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_outputreg0_q <= $unsigned(redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_mem_q);
        end
    end

    // redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_rdcnt(ADD,31569)
    assign redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_a = {1'b0, redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_wraddr_q};
    assign redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_b = {1'b0, redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_o <= $unsigned(redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_a) + $unsigned(redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_b);
        end
    end
    assign redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_q = redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_o[7:0];

    // redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_inputreg0(DELAY,31564)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl);
        end
    end

    // redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_wraddr(COUNTER,31567)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_wraddr_i <= $unsigned(redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_wraddr_q = redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_wraddr_i[6:0];

    // redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem(DUALMEM,31566)
    assign redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_ia = $unsigned(redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_inputreg0_q);
    assign redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_aa = redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_wraddr_q;
    assign redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_ab = redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_aa),
        .data_a(redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_ab),
        .q_b(redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_q = redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_iq[15:0];

    // redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_outputreg0(DELAY,31565)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_outputreg0_q <= $unsigned(redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28008)@105 + 5
    // out q@111
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408(ADD,8592)@111
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod286_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_b = $unsigned({{5{i_shl_i_i_i_i_i_i_49_c_compstr1407_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_49_c_compstr1407_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_o[33:0];

    // rightShiftStage0_uid18007_dupName_197_i_unnamed_c_compstr0_shift_x(MUX,18006)@111
    assign rightShiftStage0_uid18007_dupName_197_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18007_dupName_197_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_q or rightShiftStage0Idx1_uid18005_dupName_197_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18007_dupName_197_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18007_dupName_197_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_q;
            1'b1 : rightShiftStage0_uid18007_dupName_197_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18005_dupName_197_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18007_dupName_197_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18012_dupName_197_i_unnamed_c_compstr0_shift_x(MUX,18011)@111
    assign rightShiftStage1_uid18012_dupName_197_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18012_dupName_197_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18007_dupName_197_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18010_dupName_197_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18012_dupName_197_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18012_dupName_197_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18007_dupName_197_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18012_dupName_197_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18010_dupName_197_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18012_dupName_197_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18017_dupName_197_i_unnamed_c_compstr0_shift_x(MUX,18016)@111
    assign rightShiftStage2_uid18017_dupName_197_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18017_dupName_197_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18012_dupName_197_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18015_dupName_197_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18017_dupName_197_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18017_dupName_197_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18012_dupName_197_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18017_dupName_197_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18015_dupName_197_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18017_dupName_197_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1409_vt_select_20(BITSELECT,10157)@111
    assign i_unnamed_c_compstr1409_vt_select_20_b = rightShiftStage2_uid18017_dupName_197_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1409_vt_join(BITJOIN,10156)@111
    assign i_unnamed_c_compstr1409_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1409_vt_select_20_b};

    // i_conv_i_i_i_i_i_49_c_compstr1410_sel_x(BITSELECT,3783)@111
    assign i_conv_i_i_i_i_i_49_c_compstr1410_sel_x_b = i_unnamed_c_compstr1409_vt_join_q[15:0];

    // redist1082_i_conv_i_i_i_i_i_49_c_compstr1410_sel_x_b_1(DELAY,29310)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1082_i_conv_i_i_i_i_i_49_c_compstr1410_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_49_c_compstr1410_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18026_dupName_198_i_unnamed_c_compstr0_shift_x(BITSELECT,18025)@111
    assign rightShiftStage1Idx1Rng8_uid18026_dupName_198_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18025_dupName_198_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18028_dupName_198_i_unnamed_c_compstr0_shift_x(BITJOIN,18027)@111
    assign rightShiftStage1Idx1_uid18028_dupName_198_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18026_dupName_198_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18021_dupName_198_i_unnamed_c_compstr0_shift_x(BITSELECT,18020)@111
    assign rightShiftStage0Idx1Rng4_uid18021_dupName_198_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_q[33:4];

    // rightShiftStage0Idx1_uid18023_dupName_198_i_unnamed_c_compstr0_shift_x(BITJOIN,18022)@111
    assign rightShiftStage0Idx1_uid18023_dupName_198_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18021_dupName_198_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18025_dupName_198_i_unnamed_c_compstr0_shift_x(MUX,18024)@111
    assign rightShiftStage0_uid18025_dupName_198_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18025_dupName_198_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_q or rightShiftStage0Idx1_uid18023_dupName_198_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18025_dupName_198_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18025_dupName_198_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compstr1408_q;
            1'b1 : rightShiftStage0_uid18025_dupName_198_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18023_dupName_198_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18025_dupName_198_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18030_dupName_198_i_unnamed_c_compstr0_shift_x(MUX,18029)@111
    assign rightShiftStage1_uid18030_dupName_198_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18030_dupName_198_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18025_dupName_198_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18028_dupName_198_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18030_dupName_198_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18030_dupName_198_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18025_dupName_198_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18030_dupName_198_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18028_dupName_198_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18030_dupName_198_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1411_vt_select_21(BITSELECT,10160)@111
    assign i_unnamed_c_compstr1411_vt_select_21_b = rightShiftStage1_uid18030_dupName_198_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1411_vt_join(BITJOIN,10159)@111
    assign i_unnamed_c_compstr1411_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1411_vt_select_21_b};

    // i_unnamed_c_compstr1412_sel_x(BITSELECT,6067)@111
    assign i_unnamed_c_compstr1412_sel_x_b = i_unnamed_c_compstr1411_vt_join_q[15:0];

    // i_unnamed_c_compstr1413_BitSelect_for_a(BITSELECT,27523)@111
    assign i_unnamed_c_compstr1413_BitSelect_for_a_b = i_unnamed_c_compstr1412_sel_x_b[0:0];

    // i_unnamed_c_compstr1413_join(BITJOIN,27524)@111
    assign i_unnamed_c_compstr1413_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1413_BitSelect_for_a_b};

    // i_unnamed_c_compstr1413_vt_select_0(BITSELECT,10165)@111
    assign i_unnamed_c_compstr1413_vt_select_0_b = i_unnamed_c_compstr1413_join_q[0:0];

    // redist223_i_unnamed_c_compstr1413_vt_select_0_b_1(DELAY,28451)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist223_i_unnamed_c_compstr1413_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1413_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1413_vt_join(BITJOIN,10164)@112
    assign i_unnamed_c_compstr1413_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist223_i_unnamed_c_compstr1413_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_49_c_compstr1414(ADD,7050)@112
    assign i_add_i_i_i_i_i_i_49_c_compstr1414_a = {1'b0, i_unnamed_c_compstr1413_vt_join_q};
    assign i_add_i_i_i_i_i_i_49_c_compstr1414_b = {1'b0, redist1082_i_conv_i_i_i_i_i_49_c_compstr1410_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_49_c_compstr1414_o = $unsigned(i_add_i_i_i_i_i_i_49_c_compstr1414_a) + $unsigned(i_add_i_i_i_i_i_i_49_c_compstr1414_b);
    assign i_add_i_i_i_i_i_i_49_c_compstr1414_q = i_add_i_i_i_i_i_i_49_c_compstr1414_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_49_c_compstr1414_sel_x(BITSELECT,2244)@112
    assign bgTrunc_i_add_i_i_i_i_i_i_49_c_compstr1414_sel_x_b = i_add_i_i_i_i_i_i_49_c_compstr1414_q[15:0];

    // i_conv_i_i_i_i_i_i279_50_c_compstr1434_sel_x(BITSELECT,3913)@112
    assign i_conv_i_i_i_i_i_i279_50_c_compstr1434_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_49_c_compstr1414_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_50_c_compstr1434_vt_select_15(BITSELECT,8169)@112
    assign i_conv_i_i_i_i_i_i279_50_c_compstr1434_vt_select_15_b = i_conv_i_i_i_i_i_i279_50_c_compstr1434_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_50_c_compstr1434_vt_join(BITJOIN,8168)@112
    assign i_conv_i_i_i_i_i_i279_50_c_compstr1434_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_50_c_compstr1434_vt_select_15_b};

    // leftShiftStage0_uid26456_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x(MUX,26455)@112
    assign leftShiftStage0_uid26456_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26456_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_50_c_compstr1434_vt_join_q or leftShiftStage0Idx1_uid26454_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26456_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26456_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_50_c_compstr1434_vt_join_q;
            1'b1 : leftShiftStage0_uid26456_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26454_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26456_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26461_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x(MUX,26460)@112
    assign leftShiftStage1_uid26461_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26461_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_s or leftShiftStage0_uid26456_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26459_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26461_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26461_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q = leftShiftStage0_uid26456_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26461_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26459_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26461_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26466_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x(MUX,26465)@112
    assign leftShiftStage2_uid26466_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26466_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_s or leftShiftStage1_uid26461_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26464_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26466_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26466_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q = leftShiftStage1_uid26461_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26466_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26464_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26466_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_50_c_compstr1435_vt_select_28(BITSELECT,9640)@112
    assign i_shl_i_i_i_i_i_i_50_c_compstr1435_vt_select_28_b = leftShiftStage2_uid26466_i_shl_i_i_i_i_i_i_50_c_compstr0_shift_x_q[28:13];

    // redist310_i_shl_i_i_i_i_i_i_50_c_compstr1435_vt_select_28_b_1(DELAY,28538)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist310_i_shl_i_i_i_i_i_i_50_c_compstr1435_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_50_c_compstr1435_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_50_c_compstr1435_vt_join(BITJOIN,9639)@113
    assign i_shl_i_i_i_i_i_i_50_c_compstr1435_vt_join_q = {redist310_i_shl_i_i_i_i_i_i_50_c_compstr1435_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_offset(CONSTANT,30138)
    assign redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_offset_q = $unsigned(7'b0100010);

    // redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_rdcnt(ADD,31587)
    assign redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_a = {1'b0, redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_wraddr_q};
    assign redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_b = {1'b0, redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_o <= $unsigned(redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_a) + $unsigned(redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_b);
        end
    end
    assign redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_q = redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_o[7:0];

    // redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_inputreg0(DELAY,31582)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl);
        end
    end

    // redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_wraddr(COUNTER,31585)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_wraddr_i <= $unsigned(redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_wraddr_q = redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_wraddr_i[6:0];

    // redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem(DUALMEM,31584)
    assign redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_ia = $unsigned(redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_inputreg0_q);
    assign redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_aa = redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_wraddr_q;
    assign redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_ab = redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_aa),
        .data_a(redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_ab),
        .q_b(redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_q = redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_iq[15:0];

    // redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_outputreg0(DELAY,31583)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_outputreg0_q <= $unsigned(redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_mem_q);
        end
    end

    // redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_rdcnt(ADD,30139)
    assign redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_a = {1'b0, redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_wraddr_q};
    assign redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_b = {1'b0, redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_o <= $unsigned(redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_a) + $unsigned(redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_b);
        end
    end
    assign redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_q = redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_o[7:0];

    // redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_inputreg0(DELAY,30134)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl);
        end
    end

    // redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_wraddr(COUNTER,30137)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_wraddr_i <= $unsigned(redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_wraddr_q = redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_wraddr_i[6:0];

    // redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem(DUALMEM,30136)
    assign redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_ia = $unsigned(redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_inputreg0_q);
    assign redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_aa = redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_wraddr_q;
    assign redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_ab = redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_aa),
        .data_a(redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_ab),
        .q_b(redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_q = redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_iq[15:0];

    // redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_outputreg0(DELAY,30135)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_outputreg0_q <= $unsigned(redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_mem_q);
        end
    end

    // redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_rdcnt(ADD,30145)
    assign redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_a = {1'b0, redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_wraddr_q};
    assign redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_b = {1'b0, redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_o <= $unsigned(redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_a) + $unsigned(redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_b);
        end
    end
    assign redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_q = redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_o[7:0];

    // redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_inputreg0(DELAY,30140)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl);
        end
    end

    // redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_wraddr(COUNTER,30143)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_wraddr_i <= $unsigned(redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_wraddr_q = redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_wraddr_i[6:0];

    // redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem(DUALMEM,30142)
    assign redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_ia = $unsigned(redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_inputreg0_q);
    assign redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_aa = redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_wraddr_q;
    assign redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_ab = redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_aa),
        .data_a(redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_ab),
        .q_b(redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_q = redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_iq[15:0];

    // redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_outputreg0(DELAY,30141)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_outputreg0_q <= $unsigned(redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_mem_q);
        end
    end

    // redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_rdcnt(ADD,31581)
    assign redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_a = {1'b0, redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_wraddr_q};
    assign redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_b = {1'b0, redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_o <= $unsigned(redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_a) + $unsigned(redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_b);
        end
    end
    assign redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_q = redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_o[7:0];

    // redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_inputreg0(DELAY,31576)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl);
        end
    end

    // redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_wraddr(COUNTER,31579)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_wraddr_i <= $unsigned(redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_wraddr_q = redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_wraddr_i[6:0];

    // redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem(DUALMEM,31578)
    assign redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_ia = $unsigned(redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_inputreg0_q);
    assign redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_aa = redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_wraddr_q;
    assign redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_ab = redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_aa),
        .data_a(redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_ab),
        .q_b(redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_q = redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_iq[15:0];

    // redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_outputreg0(DELAY,31577)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_outputreg0_q <= $unsigned(redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28009)@107 + 5
    // out q@113
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436(ADD,8594)@113
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod291_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_b = $unsigned({{5{i_shl_i_i_i_i_i_i_50_c_compstr1435_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_50_c_compstr1435_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_o[33:0];

    // rightShiftStage0_uid18069_dupName_201_i_unnamed_c_compstr0_shift_x(MUX,18068)@113
    assign rightShiftStage0_uid18069_dupName_201_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18069_dupName_201_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_q or rightShiftStage0Idx1_uid18067_dupName_201_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18069_dupName_201_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18069_dupName_201_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_q;
            1'b1 : rightShiftStage0_uid18069_dupName_201_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18067_dupName_201_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18069_dupName_201_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18074_dupName_201_i_unnamed_c_compstr0_shift_x(MUX,18073)@113
    assign rightShiftStage1_uid18074_dupName_201_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18074_dupName_201_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18069_dupName_201_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18072_dupName_201_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18074_dupName_201_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18074_dupName_201_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18069_dupName_201_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18074_dupName_201_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18072_dupName_201_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18074_dupName_201_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18079_dupName_201_i_unnamed_c_compstr0_shift_x(MUX,18078)@113
    assign rightShiftStage2_uid18079_dupName_201_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18079_dupName_201_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18074_dupName_201_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18077_dupName_201_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18079_dupName_201_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18079_dupName_201_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18074_dupName_201_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18079_dupName_201_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18077_dupName_201_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18079_dupName_201_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1437_vt_select_20(BITSELECT,10179)@113
    assign i_unnamed_c_compstr1437_vt_select_20_b = rightShiftStage2_uid18079_dupName_201_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1437_vt_join(BITJOIN,10178)@113
    assign i_unnamed_c_compstr1437_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1437_vt_select_20_b};

    // i_conv_i_i_i_i_i_50_c_compstr1438_sel_x(BITSELECT,3785)@113
    assign i_conv_i_i_i_i_i_50_c_compstr1438_sel_x_b = i_unnamed_c_compstr1437_vt_join_q[15:0];

    // redist1080_i_conv_i_i_i_i_i_50_c_compstr1438_sel_x_b_1(DELAY,29308)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1080_i_conv_i_i_i_i_i_50_c_compstr1438_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_50_c_compstr1438_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18088_dupName_202_i_unnamed_c_compstr0_shift_x(BITSELECT,18087)@113
    assign rightShiftStage1Idx1Rng8_uid18088_dupName_202_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18087_dupName_202_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18090_dupName_202_i_unnamed_c_compstr0_shift_x(BITJOIN,18089)@113
    assign rightShiftStage1Idx1_uid18090_dupName_202_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18088_dupName_202_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18083_dupName_202_i_unnamed_c_compstr0_shift_x(BITSELECT,18082)@113
    assign rightShiftStage0Idx1Rng4_uid18083_dupName_202_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_q[33:4];

    // rightShiftStage0Idx1_uid18085_dupName_202_i_unnamed_c_compstr0_shift_x(BITJOIN,18084)@113
    assign rightShiftStage0Idx1_uid18085_dupName_202_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18083_dupName_202_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18087_dupName_202_i_unnamed_c_compstr0_shift_x(MUX,18086)@113
    assign rightShiftStage0_uid18087_dupName_202_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18087_dupName_202_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_q or rightShiftStage0Idx1_uid18085_dupName_202_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18087_dupName_202_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18087_dupName_202_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compstr1436_q;
            1'b1 : rightShiftStage0_uid18087_dupName_202_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18085_dupName_202_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18087_dupName_202_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18092_dupName_202_i_unnamed_c_compstr0_shift_x(MUX,18091)@113
    assign rightShiftStage1_uid18092_dupName_202_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18092_dupName_202_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18087_dupName_202_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18090_dupName_202_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18092_dupName_202_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18092_dupName_202_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18087_dupName_202_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18092_dupName_202_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18090_dupName_202_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18092_dupName_202_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1439_vt_select_21(BITSELECT,10182)@113
    assign i_unnamed_c_compstr1439_vt_select_21_b = rightShiftStage1_uid18092_dupName_202_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1439_vt_join(BITJOIN,10181)@113
    assign i_unnamed_c_compstr1439_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1439_vt_select_21_b};

    // i_unnamed_c_compstr1440_sel_x(BITSELECT,6069)@113
    assign i_unnamed_c_compstr1440_sel_x_b = i_unnamed_c_compstr1439_vt_join_q[15:0];

    // i_unnamed_c_compstr1441_BitSelect_for_a(BITSELECT,27527)@113
    assign i_unnamed_c_compstr1441_BitSelect_for_a_b = i_unnamed_c_compstr1440_sel_x_b[0:0];

    // i_unnamed_c_compstr1441_join(BITJOIN,27528)@113
    assign i_unnamed_c_compstr1441_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1441_BitSelect_for_a_b};

    // i_unnamed_c_compstr1441_vt_select_0(BITSELECT,10187)@113
    assign i_unnamed_c_compstr1441_vt_select_0_b = i_unnamed_c_compstr1441_join_q[0:0];

    // redist221_i_unnamed_c_compstr1441_vt_select_0_b_1(DELAY,28449)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist221_i_unnamed_c_compstr1441_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1441_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1441_vt_join(BITJOIN,10186)@114
    assign i_unnamed_c_compstr1441_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist221_i_unnamed_c_compstr1441_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_50_c_compstr1442(ADD,7052)@114
    assign i_add_i_i_i_i_i_i_50_c_compstr1442_a = {1'b0, i_unnamed_c_compstr1441_vt_join_q};
    assign i_add_i_i_i_i_i_i_50_c_compstr1442_b = {1'b0, redist1080_i_conv_i_i_i_i_i_50_c_compstr1438_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_50_c_compstr1442_o = $unsigned(i_add_i_i_i_i_i_i_50_c_compstr1442_a) + $unsigned(i_add_i_i_i_i_i_i_50_c_compstr1442_b);
    assign i_add_i_i_i_i_i_i_50_c_compstr1442_q = i_add_i_i_i_i_i_i_50_c_compstr1442_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_50_c_compstr1442_sel_x(BITSELECT,2246)@114
    assign bgTrunc_i_add_i_i_i_i_i_i_50_c_compstr1442_sel_x_b = i_add_i_i_i_i_i_i_50_c_compstr1442_q[15:0];

    // i_conv_i_i_i_i_i_i279_51_c_compstr1462_sel_x(BITSELECT,3914)@114
    assign i_conv_i_i_i_i_i_i279_51_c_compstr1462_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_50_c_compstr1442_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_51_c_compstr1462_vt_select_15(BITSELECT,8173)@114
    assign i_conv_i_i_i_i_i_i279_51_c_compstr1462_vt_select_15_b = i_conv_i_i_i_i_i_i279_51_c_compstr1462_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_51_c_compstr1462_vt_join(BITJOIN,8172)@114
    assign i_conv_i_i_i_i_i_i279_51_c_compstr1462_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_51_c_compstr1462_vt_select_15_b};

    // leftShiftStage0_uid26474_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x(MUX,26473)@114
    assign leftShiftStage0_uid26474_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26474_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_51_c_compstr1462_vt_join_q or leftShiftStage0Idx1_uid26472_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26474_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26474_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_51_c_compstr1462_vt_join_q;
            1'b1 : leftShiftStage0_uid26474_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26472_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26474_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26479_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x(MUX,26478)@114
    assign leftShiftStage1_uid26479_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26479_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_s or leftShiftStage0_uid26474_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26477_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26479_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26479_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q = leftShiftStage0_uid26474_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26479_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26477_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26479_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26484_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x(MUX,26483)@114
    assign leftShiftStage2_uid26484_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26484_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_s or leftShiftStage1_uid26479_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26482_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26484_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26484_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q = leftShiftStage1_uid26479_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26484_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26482_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26484_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_51_c_compstr1463_vt_select_28(BITSELECT,9643)@114
    assign i_shl_i_i_i_i_i_i_51_c_compstr1463_vt_select_28_b = leftShiftStage2_uid26484_i_shl_i_i_i_i_i_i_51_c_compstr0_shift_x_q[28:13];

    // redist309_i_shl_i_i_i_i_i_i_51_c_compstr1463_vt_select_28_b_1(DELAY,28537)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist309_i_shl_i_i_i_i_i_i_51_c_compstr1463_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_51_c_compstr1463_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_51_c_compstr1463_vt_join(BITJOIN,9642)@115
    assign i_shl_i_i_i_i_i_i_51_c_compstr1463_vt_join_q = {redist309_i_shl_i_i_i_i_i_i_51_c_compstr1463_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_offset(CONSTANT,30150)
    assign redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_offset_q = $unsigned(7'b0100000);

    // redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_rdcnt(ADD,31599)
    assign redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_a = {1'b0, redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_wraddr_q};
    assign redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_b = {1'b0, redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_o <= $unsigned(redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_a) + $unsigned(redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_b);
        end
    end
    assign redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_q = redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_o[7:0];

    // redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_inputreg0(DELAY,31594)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl);
        end
    end

    // redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_wraddr(COUNTER,31597)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_wraddr_i <= $unsigned(redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_wraddr_q = redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_wraddr_i[6:0];

    // redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem(DUALMEM,31596)
    assign redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_ia = $unsigned(redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_inputreg0_q);
    assign redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_aa = redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_wraddr_q;
    assign redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_ab = redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_aa),
        .data_a(redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_ab),
        .q_b(redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_q = redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_iq[15:0];

    // redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_outputreg0(DELAY,31595)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_outputreg0_q <= $unsigned(redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_mem_q);
        end
    end

    // redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_rdcnt(ADD,30151)
    assign redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_a = {1'b0, redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_wraddr_q};
    assign redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_b = {1'b0, redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_o <= $unsigned(redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_a) + $unsigned(redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_b);
        end
    end
    assign redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_q = redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_o[7:0];

    // redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_inputreg0(DELAY,30146)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl);
        end
    end

    // redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_wraddr(COUNTER,30149)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_wraddr_i <= $unsigned(redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_wraddr_q = redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_wraddr_i[6:0];

    // redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem(DUALMEM,30148)
    assign redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_ia = $unsigned(redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_inputreg0_q);
    assign redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_aa = redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_wraddr_q;
    assign redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_ab = redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_aa),
        .data_a(redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_ab),
        .q_b(redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_q = redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_iq[15:0];

    // redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_outputreg0(DELAY,30147)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_outputreg0_q <= $unsigned(redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_mem_q);
        end
    end

    // redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_rdcnt(ADD,30157)
    assign redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_a = {1'b0, redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_wraddr_q};
    assign redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_b = {1'b0, redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_o <= $unsigned(redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_a) + $unsigned(redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_b);
        end
    end
    assign redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_q = redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_o[7:0];

    // redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_inputreg0(DELAY,30152)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl);
        end
    end

    // redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_wraddr(COUNTER,30155)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_wraddr_i <= $unsigned(redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_wraddr_q = redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_wraddr_i[6:0];

    // redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem(DUALMEM,30154)
    assign redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_ia = $unsigned(redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_inputreg0_q);
    assign redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_aa = redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_wraddr_q;
    assign redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_ab = redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_aa),
        .data_a(redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_ab),
        .q_b(redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_q = redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_iq[15:0];

    // redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_outputreg0(DELAY,30153)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_outputreg0_q <= $unsigned(redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_mem_q);
        end
    end

    // redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_rdcnt(ADD,31593)
    assign redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_a = {1'b0, redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_wraddr_q};
    assign redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_b = {1'b0, redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_o <= $unsigned(redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_a) + $unsigned(redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_b);
        end
    end
    assign redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_q = redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_o[7:0];

    // redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_inputreg0(DELAY,31588)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl);
        end
    end

    // redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_wraddr(COUNTER,31591)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_wraddr_i <= $unsigned(redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_wraddr_q = redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_wraddr_i[6:0];

    // redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem(DUALMEM,31590)
    assign redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_ia = $unsigned(redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_inputreg0_q);
    assign redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_aa = redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_wraddr_q;
    assign redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_ab = redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_aa),
        .data_a(redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_ab),
        .q_b(redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_q = redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_iq[15:0];

    // redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_outputreg0(DELAY,31589)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_outputreg0_q <= $unsigned(redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28010)@109 + 5
    // out q@115
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464(ADD,8595)@115
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod296_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_b = $unsigned({{5{i_shl_i_i_i_i_i_i_51_c_compstr1463_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_51_c_compstr1463_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_o[33:0];

    // rightShiftStage0_uid18131_dupName_205_i_unnamed_c_compstr0_shift_x(MUX,18130)@115
    assign rightShiftStage0_uid18131_dupName_205_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18131_dupName_205_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_q or rightShiftStage0Idx1_uid18129_dupName_205_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18131_dupName_205_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18131_dupName_205_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_q;
            1'b1 : rightShiftStage0_uid18131_dupName_205_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18129_dupName_205_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18131_dupName_205_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18136_dupName_205_i_unnamed_c_compstr0_shift_x(MUX,18135)@115
    assign rightShiftStage1_uid18136_dupName_205_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18136_dupName_205_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18131_dupName_205_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18134_dupName_205_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18136_dupName_205_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18136_dupName_205_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18131_dupName_205_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18136_dupName_205_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18134_dupName_205_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18136_dupName_205_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18141_dupName_205_i_unnamed_c_compstr0_shift_x(MUX,18140)@115
    assign rightShiftStage2_uid18141_dupName_205_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18141_dupName_205_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18136_dupName_205_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18139_dupName_205_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18141_dupName_205_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18141_dupName_205_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18136_dupName_205_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18141_dupName_205_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18139_dupName_205_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18141_dupName_205_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1465_vt_select_20(BITSELECT,10201)@115
    assign i_unnamed_c_compstr1465_vt_select_20_b = rightShiftStage2_uid18141_dupName_205_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1465_vt_join(BITJOIN,10200)@115
    assign i_unnamed_c_compstr1465_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1465_vt_select_20_b};

    // i_conv_i_i_i_i_i_51_c_compstr1466_sel_x(BITSELECT,3786)@115
    assign i_conv_i_i_i_i_i_51_c_compstr1466_sel_x_b = i_unnamed_c_compstr1465_vt_join_q[15:0];

    // redist1079_i_conv_i_i_i_i_i_51_c_compstr1466_sel_x_b_1(DELAY,29307)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1079_i_conv_i_i_i_i_i_51_c_compstr1466_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_51_c_compstr1466_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18150_dupName_206_i_unnamed_c_compstr0_shift_x(BITSELECT,18149)@115
    assign rightShiftStage1Idx1Rng8_uid18150_dupName_206_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18149_dupName_206_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18152_dupName_206_i_unnamed_c_compstr0_shift_x(BITJOIN,18151)@115
    assign rightShiftStage1Idx1_uid18152_dupName_206_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18150_dupName_206_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18145_dupName_206_i_unnamed_c_compstr0_shift_x(BITSELECT,18144)@115
    assign rightShiftStage0Idx1Rng4_uid18145_dupName_206_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_q[33:4];

    // rightShiftStage0Idx1_uid18147_dupName_206_i_unnamed_c_compstr0_shift_x(BITJOIN,18146)@115
    assign rightShiftStage0Idx1_uid18147_dupName_206_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18145_dupName_206_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18149_dupName_206_i_unnamed_c_compstr0_shift_x(MUX,18148)@115
    assign rightShiftStage0_uid18149_dupName_206_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18149_dupName_206_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_q or rightShiftStage0Idx1_uid18147_dupName_206_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18149_dupName_206_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18149_dupName_206_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compstr1464_q;
            1'b1 : rightShiftStage0_uid18149_dupName_206_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18147_dupName_206_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18149_dupName_206_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18154_dupName_206_i_unnamed_c_compstr0_shift_x(MUX,18153)@115
    assign rightShiftStage1_uid18154_dupName_206_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18154_dupName_206_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18149_dupName_206_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18152_dupName_206_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18154_dupName_206_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18154_dupName_206_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18149_dupName_206_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18154_dupName_206_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18152_dupName_206_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18154_dupName_206_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1467_vt_select_21(BITSELECT,10204)@115
    assign i_unnamed_c_compstr1467_vt_select_21_b = rightShiftStage1_uid18154_dupName_206_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1467_vt_join(BITJOIN,10203)@115
    assign i_unnamed_c_compstr1467_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1467_vt_select_21_b};

    // i_unnamed_c_compstr1468_sel_x(BITSELECT,6071)@115
    assign i_unnamed_c_compstr1468_sel_x_b = i_unnamed_c_compstr1467_vt_join_q[15:0];

    // i_unnamed_c_compstr1469_BitSelect_for_a(BITSELECT,27531)@115
    assign i_unnamed_c_compstr1469_BitSelect_for_a_b = i_unnamed_c_compstr1468_sel_x_b[0:0];

    // i_unnamed_c_compstr1469_join(BITJOIN,27532)@115
    assign i_unnamed_c_compstr1469_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1469_BitSelect_for_a_b};

    // i_unnamed_c_compstr1469_vt_select_0(BITSELECT,10209)@115
    assign i_unnamed_c_compstr1469_vt_select_0_b = i_unnamed_c_compstr1469_join_q[0:0];

    // redist219_i_unnamed_c_compstr1469_vt_select_0_b_1(DELAY,28447)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist219_i_unnamed_c_compstr1469_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1469_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1469_vt_join(BITJOIN,10208)@116
    assign i_unnamed_c_compstr1469_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist219_i_unnamed_c_compstr1469_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_51_c_compstr1470(ADD,7053)@116
    assign i_add_i_i_i_i_i_i_51_c_compstr1470_a = {1'b0, i_unnamed_c_compstr1469_vt_join_q};
    assign i_add_i_i_i_i_i_i_51_c_compstr1470_b = {1'b0, redist1079_i_conv_i_i_i_i_i_51_c_compstr1466_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_51_c_compstr1470_o = $unsigned(i_add_i_i_i_i_i_i_51_c_compstr1470_a) + $unsigned(i_add_i_i_i_i_i_i_51_c_compstr1470_b);
    assign i_add_i_i_i_i_i_i_51_c_compstr1470_q = i_add_i_i_i_i_i_i_51_c_compstr1470_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_51_c_compstr1470_sel_x(BITSELECT,2247)@116
    assign bgTrunc_i_add_i_i_i_i_i_i_51_c_compstr1470_sel_x_b = i_add_i_i_i_i_i_i_51_c_compstr1470_q[15:0];

    // i_conv_i_i_i_i_i_i279_52_c_compstr1490_sel_x(BITSELECT,3915)@116
    assign i_conv_i_i_i_i_i_i279_52_c_compstr1490_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_51_c_compstr1470_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_52_c_compstr1490_vt_select_15(BITSELECT,8177)@116
    assign i_conv_i_i_i_i_i_i279_52_c_compstr1490_vt_select_15_b = i_conv_i_i_i_i_i_i279_52_c_compstr1490_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_52_c_compstr1490_vt_join(BITJOIN,8176)@116
    assign i_conv_i_i_i_i_i_i279_52_c_compstr1490_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_52_c_compstr1490_vt_select_15_b};

    // leftShiftStage0_uid26492_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x(MUX,26491)@116
    assign leftShiftStage0_uid26492_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26492_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_52_c_compstr1490_vt_join_q or leftShiftStage0Idx1_uid26490_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26492_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26492_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_52_c_compstr1490_vt_join_q;
            1'b1 : leftShiftStage0_uid26492_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26490_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26492_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26497_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x(MUX,26496)@116
    assign leftShiftStage1_uid26497_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26497_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_s or leftShiftStage0_uid26492_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26495_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26497_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26497_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q = leftShiftStage0_uid26492_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26497_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26495_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26497_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26502_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x(MUX,26501)@116
    assign leftShiftStage2_uid26502_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26502_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_s or leftShiftStage1_uid26497_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26500_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26502_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26502_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q = leftShiftStage1_uid26497_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26502_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26500_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26502_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_52_c_compstr1491_vt_select_28(BITSELECT,9646)@116
    assign i_shl_i_i_i_i_i_i_52_c_compstr1491_vt_select_28_b = leftShiftStage2_uid26502_i_shl_i_i_i_i_i_i_52_c_compstr0_shift_x_q[28:13];

    // redist308_i_shl_i_i_i_i_i_i_52_c_compstr1491_vt_select_28_b_1(DELAY,28536)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist308_i_shl_i_i_i_i_i_i_52_c_compstr1491_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_52_c_compstr1491_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_52_c_compstr1491_vt_join(BITJOIN,9645)@117
    assign i_shl_i_i_i_i_i_i_52_c_compstr1491_vt_join_q = {redist308_i_shl_i_i_i_i_i_i_52_c_compstr1491_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_offset(CONSTANT,30162)
    assign redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_offset_q = $unsigned(7'b0011110);

    // redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_rdcnt(ADD,31611)
    assign redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_a = {1'b0, redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_wraddr_q};
    assign redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_b = {1'b0, redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_o <= $unsigned(redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_a) + $unsigned(redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_b);
        end
    end
    assign redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_q = redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_o[7:0];

    // redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_inputreg0(DELAY,31606)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl);
        end
    end

    // redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_wraddr(COUNTER,31609)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_wraddr_i <= $unsigned(redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_wraddr_q = redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_wraddr_i[6:0];

    // redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem(DUALMEM,31608)
    assign redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_ia = $unsigned(redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_inputreg0_q);
    assign redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_aa = redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_wraddr_q;
    assign redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_ab = redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_aa),
        .data_a(redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_ab),
        .q_b(redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_q = redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_iq[15:0];

    // redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_outputreg0(DELAY,31607)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_outputreg0_q <= $unsigned(redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_mem_q);
        end
    end

    // redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_rdcnt(ADD,30163)
    assign redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_a = {1'b0, redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_wraddr_q};
    assign redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_b = {1'b0, redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_o <= $unsigned(redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_a) + $unsigned(redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_b);
        end
    end
    assign redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_q = redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_o[7:0];

    // redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_inputreg0(DELAY,30158)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl);
        end
    end

    // redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_wraddr(COUNTER,30161)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_wraddr_i <= $unsigned(redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_wraddr_q = redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_wraddr_i[6:0];

    // redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem(DUALMEM,30160)
    assign redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_ia = $unsigned(redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_inputreg0_q);
    assign redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_aa = redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_wraddr_q;
    assign redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_ab = redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_aa),
        .data_a(redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_ab),
        .q_b(redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_q = redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_iq[15:0];

    // redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_outputreg0(DELAY,30159)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_outputreg0_q <= $unsigned(redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_mem_q);
        end
    end

    // redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_rdcnt(ADD,30169)
    assign redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_a = {1'b0, redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_wraddr_q};
    assign redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_b = {1'b0, redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_o <= $unsigned(redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_a) + $unsigned(redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_b);
        end
    end
    assign redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_q = redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_o[7:0];

    // redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_inputreg0(DELAY,30164)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl);
        end
    end

    // redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_wraddr(COUNTER,30167)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_wraddr_i <= $unsigned(redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_wraddr_q = redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_wraddr_i[6:0];

    // redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem(DUALMEM,30166)
    assign redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_ia = $unsigned(redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_inputreg0_q);
    assign redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_aa = redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_wraddr_q;
    assign redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_ab = redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_aa),
        .data_a(redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_ab),
        .q_b(redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_q = redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_iq[15:0];

    // redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_outputreg0(DELAY,30165)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_outputreg0_q <= $unsigned(redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_mem_q);
        end
    end

    // redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_rdcnt(ADD,31605)
    assign redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_a = {1'b0, redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_wraddr_q};
    assign redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_b = {1'b0, redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_o <= $unsigned(redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_a) + $unsigned(redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_b);
        end
    end
    assign redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_q = redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_o[7:0];

    // redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_inputreg0(DELAY,31600)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl);
        end
    end

    // redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_wraddr(COUNTER,31603)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_wraddr_i <= $unsigned(redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_wraddr_q = redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_wraddr_i[6:0];

    // redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem(DUALMEM,31602)
    assign redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_ia = $unsigned(redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_inputreg0_q);
    assign redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_aa = redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_wraddr_q;
    assign redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_ab = redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_aa),
        .data_a(redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_ab),
        .q_b(redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_q = redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_iq[15:0];

    // redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_outputreg0(DELAY,31601)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_outputreg0_q <= $unsigned(redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28011)@111 + 5
    // out q@117
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492(ADD,8596)@117
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod301_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_b = $unsigned({{5{i_shl_i_i_i_i_i_i_52_c_compstr1491_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_52_c_compstr1491_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_o[33:0];

    // rightShiftStage0_uid18193_dupName_209_i_unnamed_c_compstr0_shift_x(MUX,18192)@117
    assign rightShiftStage0_uid18193_dupName_209_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18193_dupName_209_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_q or rightShiftStage0Idx1_uid18191_dupName_209_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18193_dupName_209_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18193_dupName_209_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_q;
            1'b1 : rightShiftStage0_uid18193_dupName_209_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18191_dupName_209_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18193_dupName_209_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18198_dupName_209_i_unnamed_c_compstr0_shift_x(MUX,18197)@117
    assign rightShiftStage1_uid18198_dupName_209_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18198_dupName_209_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18193_dupName_209_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18196_dupName_209_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18198_dupName_209_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18198_dupName_209_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18193_dupName_209_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18198_dupName_209_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18196_dupName_209_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18198_dupName_209_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18203_dupName_209_i_unnamed_c_compstr0_shift_x(MUX,18202)@117
    assign rightShiftStage2_uid18203_dupName_209_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18203_dupName_209_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18198_dupName_209_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18201_dupName_209_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18203_dupName_209_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18203_dupName_209_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18198_dupName_209_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18203_dupName_209_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18201_dupName_209_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18203_dupName_209_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1493_vt_select_20(BITSELECT,10223)@117
    assign i_unnamed_c_compstr1493_vt_select_20_b = rightShiftStage2_uid18203_dupName_209_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1493_vt_join(BITJOIN,10222)@117
    assign i_unnamed_c_compstr1493_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1493_vt_select_20_b};

    // i_conv_i_i_i_i_i_52_c_compstr1494_sel_x(BITSELECT,3787)@117
    assign i_conv_i_i_i_i_i_52_c_compstr1494_sel_x_b = i_unnamed_c_compstr1493_vt_join_q[15:0];

    // redist1078_i_conv_i_i_i_i_i_52_c_compstr1494_sel_x_b_1(DELAY,29306)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1078_i_conv_i_i_i_i_i_52_c_compstr1494_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_52_c_compstr1494_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18212_dupName_210_i_unnamed_c_compstr0_shift_x(BITSELECT,18211)@117
    assign rightShiftStage1Idx1Rng8_uid18212_dupName_210_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18211_dupName_210_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18214_dupName_210_i_unnamed_c_compstr0_shift_x(BITJOIN,18213)@117
    assign rightShiftStage1Idx1_uid18214_dupName_210_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18212_dupName_210_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18207_dupName_210_i_unnamed_c_compstr0_shift_x(BITSELECT,18206)@117
    assign rightShiftStage0Idx1Rng4_uid18207_dupName_210_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_q[33:4];

    // rightShiftStage0Idx1_uid18209_dupName_210_i_unnamed_c_compstr0_shift_x(BITJOIN,18208)@117
    assign rightShiftStage0Idx1_uid18209_dupName_210_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18207_dupName_210_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18211_dupName_210_i_unnamed_c_compstr0_shift_x(MUX,18210)@117
    assign rightShiftStage0_uid18211_dupName_210_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18211_dupName_210_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_q or rightShiftStage0Idx1_uid18209_dupName_210_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18211_dupName_210_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18211_dupName_210_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compstr1492_q;
            1'b1 : rightShiftStage0_uid18211_dupName_210_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18209_dupName_210_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18211_dupName_210_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18216_dupName_210_i_unnamed_c_compstr0_shift_x(MUX,18215)@117
    assign rightShiftStage1_uid18216_dupName_210_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18216_dupName_210_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18211_dupName_210_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18214_dupName_210_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18216_dupName_210_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18216_dupName_210_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18211_dupName_210_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18216_dupName_210_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18214_dupName_210_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18216_dupName_210_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1495_vt_select_21(BITSELECT,10226)@117
    assign i_unnamed_c_compstr1495_vt_select_21_b = rightShiftStage1_uid18216_dupName_210_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1495_vt_join(BITJOIN,10225)@117
    assign i_unnamed_c_compstr1495_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1495_vt_select_21_b};

    // i_unnamed_c_compstr1496_sel_x(BITSELECT,6073)@117
    assign i_unnamed_c_compstr1496_sel_x_b = i_unnamed_c_compstr1495_vt_join_q[15:0];

    // i_unnamed_c_compstr1497_BitSelect_for_a(BITSELECT,27535)@117
    assign i_unnamed_c_compstr1497_BitSelect_for_a_b = i_unnamed_c_compstr1496_sel_x_b[0:0];

    // i_unnamed_c_compstr1497_join(BITJOIN,27536)@117
    assign i_unnamed_c_compstr1497_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1497_BitSelect_for_a_b};

    // i_unnamed_c_compstr1497_vt_select_0(BITSELECT,10231)@117
    assign i_unnamed_c_compstr1497_vt_select_0_b = i_unnamed_c_compstr1497_join_q[0:0];

    // redist217_i_unnamed_c_compstr1497_vt_select_0_b_1(DELAY,28445)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist217_i_unnamed_c_compstr1497_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1497_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1497_vt_join(BITJOIN,10230)@118
    assign i_unnamed_c_compstr1497_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist217_i_unnamed_c_compstr1497_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_52_c_compstr1498(ADD,7054)@118
    assign i_add_i_i_i_i_i_i_52_c_compstr1498_a = {1'b0, i_unnamed_c_compstr1497_vt_join_q};
    assign i_add_i_i_i_i_i_i_52_c_compstr1498_b = {1'b0, redist1078_i_conv_i_i_i_i_i_52_c_compstr1494_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_52_c_compstr1498_o = $unsigned(i_add_i_i_i_i_i_i_52_c_compstr1498_a) + $unsigned(i_add_i_i_i_i_i_i_52_c_compstr1498_b);
    assign i_add_i_i_i_i_i_i_52_c_compstr1498_q = i_add_i_i_i_i_i_i_52_c_compstr1498_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_52_c_compstr1498_sel_x(BITSELECT,2248)@118
    assign bgTrunc_i_add_i_i_i_i_i_i_52_c_compstr1498_sel_x_b = i_add_i_i_i_i_i_i_52_c_compstr1498_q[15:0];

    // i_conv_i_i_i_i_i_i279_53_c_compstr1518_sel_x(BITSELECT,3916)@118
    assign i_conv_i_i_i_i_i_i279_53_c_compstr1518_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_52_c_compstr1498_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_53_c_compstr1518_vt_select_15(BITSELECT,8181)@118
    assign i_conv_i_i_i_i_i_i279_53_c_compstr1518_vt_select_15_b = i_conv_i_i_i_i_i_i279_53_c_compstr1518_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_53_c_compstr1518_vt_join(BITJOIN,8180)@118
    assign i_conv_i_i_i_i_i_i279_53_c_compstr1518_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_53_c_compstr1518_vt_select_15_b};

    // leftShiftStage0_uid26510_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x(MUX,26509)@118
    assign leftShiftStage0_uid26510_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26510_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_53_c_compstr1518_vt_join_q or leftShiftStage0Idx1_uid26508_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26510_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26510_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_53_c_compstr1518_vt_join_q;
            1'b1 : leftShiftStage0_uid26510_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26508_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26510_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26515_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x(MUX,26514)@118
    assign leftShiftStage1_uid26515_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26515_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_s or leftShiftStage0_uid26510_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26513_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26515_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26515_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q = leftShiftStage0_uid26510_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26515_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26513_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26515_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26520_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x(MUX,26519)@118
    assign leftShiftStage2_uid26520_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26520_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_s or leftShiftStage1_uid26515_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26518_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26520_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26520_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q = leftShiftStage1_uid26515_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26520_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26518_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26520_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_53_c_compstr1519_vt_select_28(BITSELECT,9649)@118
    assign i_shl_i_i_i_i_i_i_53_c_compstr1519_vt_select_28_b = leftShiftStage2_uid26520_i_shl_i_i_i_i_i_i_53_c_compstr0_shift_x_q[28:13];

    // redist307_i_shl_i_i_i_i_i_i_53_c_compstr1519_vt_select_28_b_1(DELAY,28535)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist307_i_shl_i_i_i_i_i_i_53_c_compstr1519_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_53_c_compstr1519_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_53_c_compstr1519_vt_join(BITJOIN,9648)@119
    assign i_shl_i_i_i_i_i_i_53_c_compstr1519_vt_join_q = {redist307_i_shl_i_i_i_i_i_i_53_c_compstr1519_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_offset(CONSTANT,30174)
    assign redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_offset_q = $unsigned(7'b0011100);

    // redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_rdcnt(ADD,31623)
    assign redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_a = {1'b0, redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_wraddr_q};
    assign redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_b = {1'b0, redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_o <= $unsigned(redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_a) + $unsigned(redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_b);
        end
    end
    assign redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_q = redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_o[7:0];

    // redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_inputreg0(DELAY,31618)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl);
        end
    end

    // redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_wraddr(COUNTER,31621)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_wraddr_i <= $unsigned(redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_wraddr_q = redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_wraddr_i[6:0];

    // redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem(DUALMEM,31620)
    assign redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_ia = $unsigned(redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_inputreg0_q);
    assign redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_aa = redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_wraddr_q;
    assign redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_ab = redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_aa),
        .data_a(redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_ab),
        .q_b(redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_q = redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_iq[15:0];

    // redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_outputreg0(DELAY,31619)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_outputreg0_q <= $unsigned(redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_mem_q);
        end
    end

    // redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_rdcnt(ADD,30175)
    assign redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_a = {1'b0, redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_wraddr_q};
    assign redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_b = {1'b0, redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_o <= $unsigned(redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_a) + $unsigned(redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_b);
        end
    end
    assign redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_q = redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_o[7:0];

    // redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_inputreg0(DELAY,30170)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl);
        end
    end

    // redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_wraddr(COUNTER,30173)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_wraddr_i <= $unsigned(redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_wraddr_q = redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_wraddr_i[6:0];

    // redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem(DUALMEM,30172)
    assign redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_ia = $unsigned(redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_inputreg0_q);
    assign redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_aa = redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_wraddr_q;
    assign redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_ab = redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_aa),
        .data_a(redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_ab),
        .q_b(redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_q = redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_iq[15:0];

    // redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_outputreg0(DELAY,30171)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_outputreg0_q <= $unsigned(redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_mem_q);
        end
    end

    // redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_rdcnt(ADD,30181)
    assign redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_a = {1'b0, redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_wraddr_q};
    assign redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_b = {1'b0, redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_o <= $unsigned(redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_a) + $unsigned(redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_b);
        end
    end
    assign redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_q = redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_o[7:0];

    // redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_inputreg0(DELAY,30176)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl);
        end
    end

    // redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_wraddr(COUNTER,30179)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_wraddr_i <= $unsigned(redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_wraddr_q = redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_wraddr_i[6:0];

    // redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem(DUALMEM,30178)
    assign redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_ia = $unsigned(redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_inputreg0_q);
    assign redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_aa = redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_wraddr_q;
    assign redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_ab = redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_aa),
        .data_a(redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_ab),
        .q_b(redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_q = redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_iq[15:0];

    // redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_outputreg0(DELAY,30177)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_outputreg0_q <= $unsigned(redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_mem_q);
        end
    end

    // redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_rdcnt(ADD,31617)
    assign redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_a = {1'b0, redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_wraddr_q};
    assign redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_b = {1'b0, redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_o <= $unsigned(redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_a) + $unsigned(redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_b);
        end
    end
    assign redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_q = redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_o[7:0];

    // redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_inputreg0(DELAY,31612)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl);
        end
    end

    // redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_wraddr(COUNTER,31615)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_wraddr_i <= $unsigned(redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_wraddr_q = redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_wraddr_i[6:0];

    // redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem(DUALMEM,31614)
    assign redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_ia = $unsigned(redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_inputreg0_q);
    assign redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_aa = redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_wraddr_q;
    assign redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_ab = redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_aa),
        .data_a(redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_ab),
        .q_b(redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_q = redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_iq[15:0];

    // redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_outputreg0(DELAY,31613)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_outputreg0_q <= $unsigned(redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28012)@113 + 5
    // out q@119
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520(ADD,8597)@119
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod306_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_b = $unsigned({{5{i_shl_i_i_i_i_i_i_53_c_compstr1519_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_53_c_compstr1519_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_o[33:0];

    // rightShiftStage0_uid18255_dupName_213_i_unnamed_c_compstr0_shift_x(MUX,18254)@119
    assign rightShiftStage0_uid18255_dupName_213_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18255_dupName_213_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_q or rightShiftStage0Idx1_uid18253_dupName_213_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18255_dupName_213_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18255_dupName_213_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_q;
            1'b1 : rightShiftStage0_uid18255_dupName_213_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18253_dupName_213_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18255_dupName_213_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18260_dupName_213_i_unnamed_c_compstr0_shift_x(MUX,18259)@119
    assign rightShiftStage1_uid18260_dupName_213_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18260_dupName_213_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18255_dupName_213_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18258_dupName_213_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18260_dupName_213_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18260_dupName_213_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18255_dupName_213_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18260_dupName_213_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18258_dupName_213_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18260_dupName_213_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18265_dupName_213_i_unnamed_c_compstr0_shift_x(MUX,18264)@119
    assign rightShiftStage2_uid18265_dupName_213_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18265_dupName_213_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18260_dupName_213_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18263_dupName_213_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18265_dupName_213_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18265_dupName_213_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18260_dupName_213_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18265_dupName_213_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18263_dupName_213_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18265_dupName_213_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1521_vt_select_20(BITSELECT,10251)@119
    assign i_unnamed_c_compstr1521_vt_select_20_b = rightShiftStage2_uid18265_dupName_213_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1521_vt_join(BITJOIN,10250)@119
    assign i_unnamed_c_compstr1521_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1521_vt_select_20_b};

    // i_conv_i_i_i_i_i_53_c_compstr1522_sel_x(BITSELECT,3788)@119
    assign i_conv_i_i_i_i_i_53_c_compstr1522_sel_x_b = i_unnamed_c_compstr1521_vt_join_q[15:0];

    // redist1077_i_conv_i_i_i_i_i_53_c_compstr1522_sel_x_b_1(DELAY,29305)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1077_i_conv_i_i_i_i_i_53_c_compstr1522_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_53_c_compstr1522_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18274_dupName_214_i_unnamed_c_compstr0_shift_x(BITSELECT,18273)@119
    assign rightShiftStage1Idx1Rng8_uid18274_dupName_214_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18273_dupName_214_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18276_dupName_214_i_unnamed_c_compstr0_shift_x(BITJOIN,18275)@119
    assign rightShiftStage1Idx1_uid18276_dupName_214_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18274_dupName_214_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18269_dupName_214_i_unnamed_c_compstr0_shift_x(BITSELECT,18268)@119
    assign rightShiftStage0Idx1Rng4_uid18269_dupName_214_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_q[33:4];

    // rightShiftStage0Idx1_uid18271_dupName_214_i_unnamed_c_compstr0_shift_x(BITJOIN,18270)@119
    assign rightShiftStage0Idx1_uid18271_dupName_214_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18269_dupName_214_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18273_dupName_214_i_unnamed_c_compstr0_shift_x(MUX,18272)@119
    assign rightShiftStage0_uid18273_dupName_214_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18273_dupName_214_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_q or rightShiftStage0Idx1_uid18271_dupName_214_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18273_dupName_214_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18273_dupName_214_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compstr1520_q;
            1'b1 : rightShiftStage0_uid18273_dupName_214_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18271_dupName_214_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18273_dupName_214_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18278_dupName_214_i_unnamed_c_compstr0_shift_x(MUX,18277)@119
    assign rightShiftStage1_uid18278_dupName_214_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18278_dupName_214_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18273_dupName_214_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18276_dupName_214_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18278_dupName_214_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18278_dupName_214_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18273_dupName_214_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18278_dupName_214_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18276_dupName_214_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18278_dupName_214_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1523_vt_select_21(BITSELECT,10254)@119
    assign i_unnamed_c_compstr1523_vt_select_21_b = rightShiftStage1_uid18278_dupName_214_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1523_vt_join(BITJOIN,10253)@119
    assign i_unnamed_c_compstr1523_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1523_vt_select_21_b};

    // i_unnamed_c_compstr1524_sel_x(BITSELECT,6076)@119
    assign i_unnamed_c_compstr1524_sel_x_b = i_unnamed_c_compstr1523_vt_join_q[15:0];

    // i_unnamed_c_compstr1525_BitSelect_for_a(BITSELECT,27539)@119
    assign i_unnamed_c_compstr1525_BitSelect_for_a_b = i_unnamed_c_compstr1524_sel_x_b[0:0];

    // i_unnamed_c_compstr1525_join(BITJOIN,27540)@119
    assign i_unnamed_c_compstr1525_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1525_BitSelect_for_a_b};

    // i_unnamed_c_compstr1525_vt_select_0(BITSELECT,10259)@119
    assign i_unnamed_c_compstr1525_vt_select_0_b = i_unnamed_c_compstr1525_join_q[0:0];

    // redist215_i_unnamed_c_compstr1525_vt_select_0_b_1(DELAY,28443)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist215_i_unnamed_c_compstr1525_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1525_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1525_vt_join(BITJOIN,10258)@120
    assign i_unnamed_c_compstr1525_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist215_i_unnamed_c_compstr1525_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_53_c_compstr1526(ADD,7055)@120
    assign i_add_i_i_i_i_i_i_53_c_compstr1526_a = {1'b0, i_unnamed_c_compstr1525_vt_join_q};
    assign i_add_i_i_i_i_i_i_53_c_compstr1526_b = {1'b0, redist1077_i_conv_i_i_i_i_i_53_c_compstr1522_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_53_c_compstr1526_o = $unsigned(i_add_i_i_i_i_i_i_53_c_compstr1526_a) + $unsigned(i_add_i_i_i_i_i_i_53_c_compstr1526_b);
    assign i_add_i_i_i_i_i_i_53_c_compstr1526_q = i_add_i_i_i_i_i_i_53_c_compstr1526_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_53_c_compstr1526_sel_x(BITSELECT,2249)@120
    assign bgTrunc_i_add_i_i_i_i_i_i_53_c_compstr1526_sel_x_b = i_add_i_i_i_i_i_i_53_c_compstr1526_q[15:0];

    // i_conv_i_i_i_i_i_i279_54_c_compstr1546_sel_x(BITSELECT,3917)@120
    assign i_conv_i_i_i_i_i_i279_54_c_compstr1546_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_53_c_compstr1526_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_54_c_compstr1546_vt_select_15(BITSELECT,8185)@120
    assign i_conv_i_i_i_i_i_i279_54_c_compstr1546_vt_select_15_b = i_conv_i_i_i_i_i_i279_54_c_compstr1546_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_54_c_compstr1546_vt_join(BITJOIN,8184)@120
    assign i_conv_i_i_i_i_i_i279_54_c_compstr1546_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_54_c_compstr1546_vt_select_15_b};

    // leftShiftStage0_uid26528_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x(MUX,26527)@120
    assign leftShiftStage0_uid26528_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26528_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_54_c_compstr1546_vt_join_q or leftShiftStage0Idx1_uid26526_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26528_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26528_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_54_c_compstr1546_vt_join_q;
            1'b1 : leftShiftStage0_uid26528_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26526_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26528_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26533_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x(MUX,26532)@120
    assign leftShiftStage1_uid26533_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26533_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_s or leftShiftStage0_uid26528_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26531_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26533_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26533_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q = leftShiftStage0_uid26528_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26533_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26531_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26533_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26538_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x(MUX,26537)@120
    assign leftShiftStage2_uid26538_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26538_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_s or leftShiftStage1_uid26533_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26536_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26538_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26538_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q = leftShiftStage1_uid26533_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26538_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26536_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26538_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_54_c_compstr1547_vt_select_28(BITSELECT,9652)@120
    assign i_shl_i_i_i_i_i_i_54_c_compstr1547_vt_select_28_b = leftShiftStage2_uid26538_i_shl_i_i_i_i_i_i_54_c_compstr0_shift_x_q[28:13];

    // redist306_i_shl_i_i_i_i_i_i_54_c_compstr1547_vt_select_28_b_1(DELAY,28534)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist306_i_shl_i_i_i_i_i_i_54_c_compstr1547_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_54_c_compstr1547_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_54_c_compstr1547_vt_join(BITJOIN,9651)@121
    assign i_shl_i_i_i_i_i_i_54_c_compstr1547_vt_join_q = {redist306_i_shl_i_i_i_i_i_i_54_c_compstr1547_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_offset(CONSTANT,30186)
    assign redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_offset_q = $unsigned(7'b0011010);

    // redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_rdcnt(ADD,31635)
    assign redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_a = {1'b0, redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_wraddr_q};
    assign redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_b = {1'b0, redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_o <= $unsigned(redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_a) + $unsigned(redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_b);
        end
    end
    assign redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_q = redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_o[7:0];

    // redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_inputreg0(DELAY,31630)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl);
        end
    end

    // redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_wraddr(COUNTER,31633)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_wraddr_i <= $unsigned(redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_wraddr_q = redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_wraddr_i[6:0];

    // redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem(DUALMEM,31632)
    assign redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_ia = $unsigned(redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_inputreg0_q);
    assign redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_aa = redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_wraddr_q;
    assign redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_ab = redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_aa),
        .data_a(redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_ab),
        .q_b(redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_q = redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_iq[15:0];

    // redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_outputreg0(DELAY,31631)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_outputreg0_q <= $unsigned(redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_mem_q);
        end
    end

    // redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_rdcnt(ADD,30187)
    assign redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_a = {1'b0, redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_wraddr_q};
    assign redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_b = {1'b0, redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_o <= $unsigned(redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_a) + $unsigned(redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_b);
        end
    end
    assign redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_q = redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_o[7:0];

    // redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_inputreg0(DELAY,30182)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl);
        end
    end

    // redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_wraddr(COUNTER,30185)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_wraddr_i <= $unsigned(redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_wraddr_q = redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_wraddr_i[6:0];

    // redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem(DUALMEM,30184)
    assign redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_ia = $unsigned(redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_inputreg0_q);
    assign redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_aa = redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_wraddr_q;
    assign redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_ab = redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_aa),
        .data_a(redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_ab),
        .q_b(redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_q = redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_iq[15:0];

    // redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_outputreg0(DELAY,30183)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_outputreg0_q <= $unsigned(redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_mem_q);
        end
    end

    // redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_rdcnt(ADD,30193)
    assign redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_a = {1'b0, redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_wraddr_q};
    assign redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_b = {1'b0, redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_o <= $unsigned(redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_a) + $unsigned(redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_b);
        end
    end
    assign redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_q = redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_o[7:0];

    // redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_inputreg0(DELAY,30188)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl);
        end
    end

    // redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_wraddr(COUNTER,30191)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_wraddr_i <= $unsigned(redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_wraddr_q = redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_wraddr_i[6:0];

    // redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem(DUALMEM,30190)
    assign redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_ia = $unsigned(redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_inputreg0_q);
    assign redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_aa = redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_wraddr_q;
    assign redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_ab = redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_aa),
        .data_a(redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_ab),
        .q_b(redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_q = redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_iq[15:0];

    // redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_outputreg0(DELAY,30189)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_outputreg0_q <= $unsigned(redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_mem_q);
        end
    end

    // redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_rdcnt(ADD,31629)
    assign redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_a = {1'b0, redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_wraddr_q};
    assign redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_b = {1'b0, redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_o <= $unsigned(redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_a) + $unsigned(redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_b);
        end
    end
    assign redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_q = redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_o[7:0];

    // redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_inputreg0(DELAY,31624)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl);
        end
    end

    // redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_wraddr(COUNTER,31627)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_wraddr_i <= $unsigned(redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_wraddr_q = redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_wraddr_i[6:0];

    // redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem(DUALMEM,31626)
    assign redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_ia = $unsigned(redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_inputreg0_q);
    assign redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_aa = redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_wraddr_q;
    assign redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_ab = redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_aa),
        .data_a(redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_ab),
        .q_b(redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_q = redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_iq[15:0];

    // redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_outputreg0(DELAY,31625)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_outputreg0_q <= $unsigned(redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28013)@115 + 5
    // out q@121
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548(ADD,8598)@121
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod311_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_b = $unsigned({{5{i_shl_i_i_i_i_i_i_54_c_compstr1547_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_54_c_compstr1547_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_o[33:0];

    // rightShiftStage0_uid18317_dupName_217_i_unnamed_c_compstr0_shift_x(MUX,18316)@121
    assign rightShiftStage0_uid18317_dupName_217_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18317_dupName_217_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_q or rightShiftStage0Idx1_uid18315_dupName_217_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18317_dupName_217_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18317_dupName_217_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_q;
            1'b1 : rightShiftStage0_uid18317_dupName_217_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18315_dupName_217_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18317_dupName_217_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18322_dupName_217_i_unnamed_c_compstr0_shift_x(MUX,18321)@121
    assign rightShiftStage1_uid18322_dupName_217_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18322_dupName_217_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18317_dupName_217_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18320_dupName_217_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18322_dupName_217_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18322_dupName_217_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18317_dupName_217_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18322_dupName_217_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18320_dupName_217_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18322_dupName_217_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18327_dupName_217_i_unnamed_c_compstr0_shift_x(MUX,18326)@121
    assign rightShiftStage2_uid18327_dupName_217_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18327_dupName_217_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18322_dupName_217_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18325_dupName_217_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18327_dupName_217_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18327_dupName_217_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18322_dupName_217_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18327_dupName_217_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18325_dupName_217_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18327_dupName_217_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1549_vt_select_20(BITSELECT,10278)@121
    assign i_unnamed_c_compstr1549_vt_select_20_b = rightShiftStage2_uid18327_dupName_217_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1549_vt_join(BITJOIN,10277)@121
    assign i_unnamed_c_compstr1549_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1549_vt_select_20_b};

    // i_conv_i_i_i_i_i_54_c_compstr1550_sel_x(BITSELECT,3789)@121
    assign i_conv_i_i_i_i_i_54_c_compstr1550_sel_x_b = i_unnamed_c_compstr1549_vt_join_q[15:0];

    // redist1076_i_conv_i_i_i_i_i_54_c_compstr1550_sel_x_b_1(DELAY,29304)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1076_i_conv_i_i_i_i_i_54_c_compstr1550_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_54_c_compstr1550_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18336_dupName_218_i_unnamed_c_compstr0_shift_x(BITSELECT,18335)@121
    assign rightShiftStage1Idx1Rng8_uid18336_dupName_218_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18335_dupName_218_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18338_dupName_218_i_unnamed_c_compstr0_shift_x(BITJOIN,18337)@121
    assign rightShiftStage1Idx1_uid18338_dupName_218_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18336_dupName_218_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18331_dupName_218_i_unnamed_c_compstr0_shift_x(BITSELECT,18330)@121
    assign rightShiftStage0Idx1Rng4_uid18331_dupName_218_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_q[33:4];

    // rightShiftStage0Idx1_uid18333_dupName_218_i_unnamed_c_compstr0_shift_x(BITJOIN,18332)@121
    assign rightShiftStage0Idx1_uid18333_dupName_218_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18331_dupName_218_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18335_dupName_218_i_unnamed_c_compstr0_shift_x(MUX,18334)@121
    assign rightShiftStage0_uid18335_dupName_218_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18335_dupName_218_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_q or rightShiftStage0Idx1_uid18333_dupName_218_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18335_dupName_218_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18335_dupName_218_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compstr1548_q;
            1'b1 : rightShiftStage0_uid18335_dupName_218_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18333_dupName_218_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18335_dupName_218_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18340_dupName_218_i_unnamed_c_compstr0_shift_x(MUX,18339)@121
    assign rightShiftStage1_uid18340_dupName_218_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18340_dupName_218_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18335_dupName_218_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18338_dupName_218_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18340_dupName_218_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18340_dupName_218_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18335_dupName_218_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18340_dupName_218_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18338_dupName_218_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18340_dupName_218_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1551_vt_select_21(BITSELECT,10281)@121
    assign i_unnamed_c_compstr1551_vt_select_21_b = rightShiftStage1_uid18340_dupName_218_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1551_vt_join(BITJOIN,10280)@121
    assign i_unnamed_c_compstr1551_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1551_vt_select_21_b};

    // i_unnamed_c_compstr1552_sel_x(BITSELECT,6078)@121
    assign i_unnamed_c_compstr1552_sel_x_b = i_unnamed_c_compstr1551_vt_join_q[15:0];

    // i_unnamed_c_compstr1553_BitSelect_for_a(BITSELECT,27545)@121
    assign i_unnamed_c_compstr1553_BitSelect_for_a_b = i_unnamed_c_compstr1552_sel_x_b[0:0];

    // i_unnamed_c_compstr1553_join(BITJOIN,27546)@121
    assign i_unnamed_c_compstr1553_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1553_BitSelect_for_a_b};

    // i_unnamed_c_compstr1553_vt_select_0(BITSELECT,10286)@121
    assign i_unnamed_c_compstr1553_vt_select_0_b = i_unnamed_c_compstr1553_join_q[0:0];

    // redist212_i_unnamed_c_compstr1553_vt_select_0_b_1(DELAY,28440)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist212_i_unnamed_c_compstr1553_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1553_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1553_vt_join(BITJOIN,10285)@122
    assign i_unnamed_c_compstr1553_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist212_i_unnamed_c_compstr1553_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_54_c_compstr1554(ADD,7056)@122
    assign i_add_i_i_i_i_i_i_54_c_compstr1554_a = {1'b0, i_unnamed_c_compstr1553_vt_join_q};
    assign i_add_i_i_i_i_i_i_54_c_compstr1554_b = {1'b0, redist1076_i_conv_i_i_i_i_i_54_c_compstr1550_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_54_c_compstr1554_o = $unsigned(i_add_i_i_i_i_i_i_54_c_compstr1554_a) + $unsigned(i_add_i_i_i_i_i_i_54_c_compstr1554_b);
    assign i_add_i_i_i_i_i_i_54_c_compstr1554_q = i_add_i_i_i_i_i_i_54_c_compstr1554_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_54_c_compstr1554_sel_x(BITSELECT,2250)@122
    assign bgTrunc_i_add_i_i_i_i_i_i_54_c_compstr1554_sel_x_b = i_add_i_i_i_i_i_i_54_c_compstr1554_q[15:0];

    // i_conv_i_i_i_i_i_i279_55_c_compstr1574_sel_x(BITSELECT,3918)@122
    assign i_conv_i_i_i_i_i_i279_55_c_compstr1574_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_54_c_compstr1554_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_55_c_compstr1574_vt_select_15(BITSELECT,8189)@122
    assign i_conv_i_i_i_i_i_i279_55_c_compstr1574_vt_select_15_b = i_conv_i_i_i_i_i_i279_55_c_compstr1574_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_55_c_compstr1574_vt_join(BITJOIN,8188)@122
    assign i_conv_i_i_i_i_i_i279_55_c_compstr1574_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_55_c_compstr1574_vt_select_15_b};

    // leftShiftStage0_uid26546_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x(MUX,26545)@122
    assign leftShiftStage0_uid26546_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26546_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_55_c_compstr1574_vt_join_q or leftShiftStage0Idx1_uid26544_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26546_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26546_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_55_c_compstr1574_vt_join_q;
            1'b1 : leftShiftStage0_uid26546_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26544_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26546_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26551_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x(MUX,26550)@122
    assign leftShiftStage1_uid26551_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26551_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_s or leftShiftStage0_uid26546_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26549_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26551_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26551_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q = leftShiftStage0_uid26546_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26551_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26549_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26551_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26556_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x(MUX,26555)@122
    assign leftShiftStage2_uid26556_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26556_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_s or leftShiftStage1_uid26551_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26554_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26556_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26556_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q = leftShiftStage1_uid26551_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26556_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26554_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26556_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_55_c_compstr1575_vt_select_28(BITSELECT,9655)@122
    assign i_shl_i_i_i_i_i_i_55_c_compstr1575_vt_select_28_b = leftShiftStage2_uid26556_i_shl_i_i_i_i_i_i_55_c_compstr0_shift_x_q[28:13];

    // redist305_i_shl_i_i_i_i_i_i_55_c_compstr1575_vt_select_28_b_1(DELAY,28533)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist305_i_shl_i_i_i_i_i_i_55_c_compstr1575_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_55_c_compstr1575_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_55_c_compstr1575_vt_join(BITJOIN,9654)@123
    assign i_shl_i_i_i_i_i_i_55_c_compstr1575_vt_join_q = {redist305_i_shl_i_i_i_i_i_i_55_c_compstr1575_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_offset(CONSTANT,30198)
    assign redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_offset_q = $unsigned(7'b0011000);

    // redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_rdcnt(ADD,31647)
    assign redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_a = {1'b0, redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_wraddr_q};
    assign redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_b = {1'b0, redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_o <= $unsigned(redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_a) + $unsigned(redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_b);
        end
    end
    assign redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_q = redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_o[7:0];

    // redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_inputreg0(DELAY,31642)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl);
        end
    end

    // redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_wraddr(COUNTER,31645)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_wraddr_i <= $unsigned(redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_wraddr_q = redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_wraddr_i[6:0];

    // redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem(DUALMEM,31644)
    assign redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_ia = $unsigned(redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_inputreg0_q);
    assign redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_aa = redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_wraddr_q;
    assign redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_ab = redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_aa),
        .data_a(redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_ab),
        .q_b(redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_q = redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_iq[15:0];

    // redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_outputreg0(DELAY,31643)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_outputreg0_q <= $unsigned(redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_mem_q);
        end
    end

    // redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_rdcnt(ADD,30199)
    assign redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_a = {1'b0, redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_wraddr_q};
    assign redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_b = {1'b0, redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_o <= $unsigned(redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_a) + $unsigned(redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_b);
        end
    end
    assign redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_q = redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_o[7:0];

    // redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_inputreg0(DELAY,30194)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl);
        end
    end

    // redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_wraddr(COUNTER,30197)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_wraddr_i <= $unsigned(redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_wraddr_q = redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_wraddr_i[6:0];

    // redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem(DUALMEM,30196)
    assign redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_ia = $unsigned(redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_inputreg0_q);
    assign redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_aa = redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_wraddr_q;
    assign redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_ab = redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_aa),
        .data_a(redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_ab),
        .q_b(redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_q = redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_iq[15:0];

    // redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_outputreg0(DELAY,30195)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_outputreg0_q <= $unsigned(redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_mem_q);
        end
    end

    // redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_rdcnt(ADD,30205)
    assign redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_a = {1'b0, redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_wraddr_q};
    assign redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_b = {1'b0, redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_o <= $unsigned(redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_a) + $unsigned(redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_b);
        end
    end
    assign redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_q = redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_o[7:0];

    // redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_inputreg0(DELAY,30200)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl);
        end
    end

    // redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_wraddr(COUNTER,30203)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_wraddr_i <= $unsigned(redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_wraddr_q = redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_wraddr_i[6:0];

    // redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem(DUALMEM,30202)
    assign redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_ia = $unsigned(redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_inputreg0_q);
    assign redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_aa = redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_wraddr_q;
    assign redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_ab = redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_aa),
        .data_a(redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_ab),
        .q_b(redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_q = redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_iq[15:0];

    // redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_outputreg0(DELAY,30201)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_outputreg0_q <= $unsigned(redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_mem_q);
        end
    end

    // redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_rdcnt(ADD,31641)
    assign redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_a = {1'b0, redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_wraddr_q};
    assign redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_b = {1'b0, redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_o <= $unsigned(redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_a) + $unsigned(redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_b);
        end
    end
    assign redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_q = redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_o[7:0];

    // redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_inputreg0(DELAY,31636)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl);
        end
    end

    // redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_wraddr(COUNTER,31639)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_wraddr_i <= $unsigned(redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_wraddr_q = redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_wraddr_i[6:0];

    // redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem(DUALMEM,31638)
    assign redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_ia = $unsigned(redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_inputreg0_q);
    assign redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_aa = redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_wraddr_q;
    assign redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_ab = redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_aa),
        .data_a(redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_ab),
        .q_b(redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_q = redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_iq[15:0];

    // redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_outputreg0(DELAY,31637)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_outputreg0_q <= $unsigned(redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28014)@117 + 5
    // out q@123
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576(ADD,8599)@123
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod316_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_b = $unsigned({{5{i_shl_i_i_i_i_i_i_55_c_compstr1575_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_55_c_compstr1575_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_o[33:0];

    // rightShiftStage0_uid18379_dupName_221_i_unnamed_c_compstr0_shift_x(MUX,18378)@123
    assign rightShiftStage0_uid18379_dupName_221_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18379_dupName_221_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_q or rightShiftStage0Idx1_uid18377_dupName_221_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18379_dupName_221_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18379_dupName_221_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_q;
            1'b1 : rightShiftStage0_uid18379_dupName_221_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18377_dupName_221_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18379_dupName_221_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18384_dupName_221_i_unnamed_c_compstr0_shift_x(MUX,18383)@123
    assign rightShiftStage1_uid18384_dupName_221_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18384_dupName_221_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18379_dupName_221_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18382_dupName_221_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18384_dupName_221_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18384_dupName_221_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18379_dupName_221_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18384_dupName_221_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18382_dupName_221_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18384_dupName_221_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18389_dupName_221_i_unnamed_c_compstr0_shift_x(MUX,18388)@123
    assign rightShiftStage2_uid18389_dupName_221_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18389_dupName_221_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18384_dupName_221_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18387_dupName_221_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18389_dupName_221_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18389_dupName_221_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18384_dupName_221_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18389_dupName_221_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18387_dupName_221_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18389_dupName_221_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1577_vt_select_20(BITSELECT,10300)@123
    assign i_unnamed_c_compstr1577_vt_select_20_b = rightShiftStage2_uid18389_dupName_221_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1577_vt_join(BITJOIN,10299)@123
    assign i_unnamed_c_compstr1577_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1577_vt_select_20_b};

    // i_conv_i_i_i_i_i_55_c_compstr1578_sel_x(BITSELECT,3790)@123
    assign i_conv_i_i_i_i_i_55_c_compstr1578_sel_x_b = i_unnamed_c_compstr1577_vt_join_q[15:0];

    // redist1075_i_conv_i_i_i_i_i_55_c_compstr1578_sel_x_b_1(DELAY,29303)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1075_i_conv_i_i_i_i_i_55_c_compstr1578_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_55_c_compstr1578_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18398_dupName_222_i_unnamed_c_compstr0_shift_x(BITSELECT,18397)@123
    assign rightShiftStage1Idx1Rng8_uid18398_dupName_222_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18397_dupName_222_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18400_dupName_222_i_unnamed_c_compstr0_shift_x(BITJOIN,18399)@123
    assign rightShiftStage1Idx1_uid18400_dupName_222_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18398_dupName_222_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18393_dupName_222_i_unnamed_c_compstr0_shift_x(BITSELECT,18392)@123
    assign rightShiftStage0Idx1Rng4_uid18393_dupName_222_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_q[33:4];

    // rightShiftStage0Idx1_uid18395_dupName_222_i_unnamed_c_compstr0_shift_x(BITJOIN,18394)@123
    assign rightShiftStage0Idx1_uid18395_dupName_222_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18393_dupName_222_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18397_dupName_222_i_unnamed_c_compstr0_shift_x(MUX,18396)@123
    assign rightShiftStage0_uid18397_dupName_222_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18397_dupName_222_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_q or rightShiftStage0Idx1_uid18395_dupName_222_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18397_dupName_222_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18397_dupName_222_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compstr1576_q;
            1'b1 : rightShiftStage0_uid18397_dupName_222_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18395_dupName_222_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18397_dupName_222_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18402_dupName_222_i_unnamed_c_compstr0_shift_x(MUX,18401)@123
    assign rightShiftStage1_uid18402_dupName_222_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18402_dupName_222_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18397_dupName_222_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18400_dupName_222_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18402_dupName_222_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18402_dupName_222_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18397_dupName_222_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18402_dupName_222_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18400_dupName_222_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18402_dupName_222_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1579_vt_select_21(BITSELECT,10303)@123
    assign i_unnamed_c_compstr1579_vt_select_21_b = rightShiftStage1_uid18402_dupName_222_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1579_vt_join(BITJOIN,10302)@123
    assign i_unnamed_c_compstr1579_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1579_vt_select_21_b};

    // i_unnamed_c_compstr1580_sel_x(BITSELECT,6080)@123
    assign i_unnamed_c_compstr1580_sel_x_b = i_unnamed_c_compstr1579_vt_join_q[15:0];

    // i_unnamed_c_compstr1581_BitSelect_for_a(BITSELECT,27549)@123
    assign i_unnamed_c_compstr1581_BitSelect_for_a_b = i_unnamed_c_compstr1580_sel_x_b[0:0];

    // i_unnamed_c_compstr1581_join(BITJOIN,27550)@123
    assign i_unnamed_c_compstr1581_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1581_BitSelect_for_a_b};

    // i_unnamed_c_compstr1581_vt_select_0(BITSELECT,10308)@123
    assign i_unnamed_c_compstr1581_vt_select_0_b = i_unnamed_c_compstr1581_join_q[0:0];

    // redist210_i_unnamed_c_compstr1581_vt_select_0_b_1(DELAY,28438)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist210_i_unnamed_c_compstr1581_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1581_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1581_vt_join(BITJOIN,10307)@124
    assign i_unnamed_c_compstr1581_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist210_i_unnamed_c_compstr1581_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_55_c_compstr1582(ADD,7057)@124
    assign i_add_i_i_i_i_i_i_55_c_compstr1582_a = {1'b0, i_unnamed_c_compstr1581_vt_join_q};
    assign i_add_i_i_i_i_i_i_55_c_compstr1582_b = {1'b0, redist1075_i_conv_i_i_i_i_i_55_c_compstr1578_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_55_c_compstr1582_o = $unsigned(i_add_i_i_i_i_i_i_55_c_compstr1582_a) + $unsigned(i_add_i_i_i_i_i_i_55_c_compstr1582_b);
    assign i_add_i_i_i_i_i_i_55_c_compstr1582_q = i_add_i_i_i_i_i_i_55_c_compstr1582_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_55_c_compstr1582_sel_x(BITSELECT,2251)@124
    assign bgTrunc_i_add_i_i_i_i_i_i_55_c_compstr1582_sel_x_b = i_add_i_i_i_i_i_i_55_c_compstr1582_q[15:0];

    // i_conv_i_i_i_i_i_i279_56_c_compstr1602_sel_x(BITSELECT,3919)@124
    assign i_conv_i_i_i_i_i_i279_56_c_compstr1602_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_55_c_compstr1582_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_56_c_compstr1602_vt_select_15(BITSELECT,8193)@124
    assign i_conv_i_i_i_i_i_i279_56_c_compstr1602_vt_select_15_b = i_conv_i_i_i_i_i_i279_56_c_compstr1602_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_56_c_compstr1602_vt_join(BITJOIN,8192)@124
    assign i_conv_i_i_i_i_i_i279_56_c_compstr1602_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_56_c_compstr1602_vt_select_15_b};

    // leftShiftStage0_uid26564_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x(MUX,26563)@124
    assign leftShiftStage0_uid26564_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26564_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_56_c_compstr1602_vt_join_q or leftShiftStage0Idx1_uid26562_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26564_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26564_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_56_c_compstr1602_vt_join_q;
            1'b1 : leftShiftStage0_uid26564_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26562_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26564_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26569_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x(MUX,26568)@124
    assign leftShiftStage1_uid26569_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26569_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_s or leftShiftStage0_uid26564_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26567_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26569_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26569_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q = leftShiftStage0_uid26564_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26569_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26567_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26569_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26574_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x(MUX,26573)@124
    assign leftShiftStage2_uid26574_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26574_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_s or leftShiftStage1_uid26569_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26572_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26574_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26574_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q = leftShiftStage1_uid26569_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26574_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26572_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26574_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_56_c_compstr1603_vt_select_28(BITSELECT,9658)@124
    assign i_shl_i_i_i_i_i_i_56_c_compstr1603_vt_select_28_b = leftShiftStage2_uid26574_i_shl_i_i_i_i_i_i_56_c_compstr0_shift_x_q[28:13];

    // redist304_i_shl_i_i_i_i_i_i_56_c_compstr1603_vt_select_28_b_1(DELAY,28532)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist304_i_shl_i_i_i_i_i_i_56_c_compstr1603_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_56_c_compstr1603_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_56_c_compstr1603_vt_join(BITJOIN,9657)@125
    assign i_shl_i_i_i_i_i_i_56_c_compstr1603_vt_join_q = {redist304_i_shl_i_i_i_i_i_i_56_c_compstr1603_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_offset(CONSTANT,30210)
    assign redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_offset_q = $unsigned(7'b0010110);

    // redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_rdcnt(ADD,31659)
    assign redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_a = {1'b0, redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_wraddr_q};
    assign redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_b = {1'b0, redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_o <= $unsigned(redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_a) + $unsigned(redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_b);
        end
    end
    assign redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_q = redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_o[7:0];

    // redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_inputreg0(DELAY,31654)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl);
        end
    end

    // redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_wraddr(COUNTER,31657)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_wraddr_i <= $unsigned(redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_wraddr_q = redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_wraddr_i[6:0];

    // redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem(DUALMEM,31656)
    assign redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_ia = $unsigned(redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_inputreg0_q);
    assign redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_aa = redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_wraddr_q;
    assign redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_ab = redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_aa),
        .data_a(redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_ab),
        .q_b(redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_q = redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_iq[15:0];

    // redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_outputreg0(DELAY,31655)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_outputreg0_q <= $unsigned(redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_mem_q);
        end
    end

    // redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_rdcnt(ADD,30211)
    assign redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_a = {1'b0, redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_wraddr_q};
    assign redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_b = {1'b0, redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_o <= $unsigned(redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_a) + $unsigned(redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_b);
        end
    end
    assign redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_q = redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_o[7:0];

    // redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_inputreg0(DELAY,30206)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl);
        end
    end

    // redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_wraddr(COUNTER,30209)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_wraddr_i <= $unsigned(redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_wraddr_q = redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_wraddr_i[6:0];

    // redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem(DUALMEM,30208)
    assign redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_ia = $unsigned(redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_inputreg0_q);
    assign redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_aa = redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_wraddr_q;
    assign redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_ab = redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_aa),
        .data_a(redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_ab),
        .q_b(redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_q = redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_iq[15:0];

    // redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_outputreg0(DELAY,30207)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_outputreg0_q <= $unsigned(redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_mem_q);
        end
    end

    // redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_rdcnt(ADD,30217)
    assign redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_a = {1'b0, redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_wraddr_q};
    assign redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_b = {1'b0, redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_o <= $unsigned(redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_a) + $unsigned(redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_b);
        end
    end
    assign redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_q = redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_o[7:0];

    // redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_inputreg0(DELAY,30212)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl);
        end
    end

    // redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_wraddr(COUNTER,30215)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_wraddr_i <= $unsigned(redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_wraddr_q = redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_wraddr_i[6:0];

    // redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem(DUALMEM,30214)
    assign redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_ia = $unsigned(redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_inputreg0_q);
    assign redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_aa = redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_wraddr_q;
    assign redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_ab = redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_aa),
        .data_a(redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_ab),
        .q_b(redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_q = redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_iq[15:0];

    // redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_outputreg0(DELAY,30213)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_outputreg0_q <= $unsigned(redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_mem_q);
        end
    end

    // redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_rdcnt(ADD,31653)
    assign redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_a = {1'b0, redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_wraddr_q};
    assign redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_b = {1'b0, redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_o <= $unsigned(redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_a) + $unsigned(redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_b);
        end
    end
    assign redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_q = redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_o[7:0];

    // redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_inputreg0(DELAY,31648)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl);
        end
    end

    // redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_wraddr(COUNTER,31651)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_wraddr_i <= $unsigned(redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_wraddr_q = redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_wraddr_i[6:0];

    // redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem(DUALMEM,31650)
    assign redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_ia = $unsigned(redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_inputreg0_q);
    assign redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_aa = redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_wraddr_q;
    assign redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_ab = redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_aa),
        .data_a(redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_ab),
        .q_b(redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_q = redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_iq[15:0];

    // redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_outputreg0(DELAY,31649)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_outputreg0_q <= $unsigned(redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28015)@119 + 5
    // out q@125
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604(ADD,8600)@125
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod321_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_b = $unsigned({{5{i_shl_i_i_i_i_i_i_56_c_compstr1603_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_56_c_compstr1603_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_o[33:0];

    // rightShiftStage0_uid18441_dupName_225_i_unnamed_c_compstr0_shift_x(MUX,18440)@125
    assign rightShiftStage0_uid18441_dupName_225_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18441_dupName_225_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_q or rightShiftStage0Idx1_uid18439_dupName_225_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18441_dupName_225_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18441_dupName_225_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_q;
            1'b1 : rightShiftStage0_uid18441_dupName_225_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18439_dupName_225_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18441_dupName_225_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18446_dupName_225_i_unnamed_c_compstr0_shift_x(MUX,18445)@125
    assign rightShiftStage1_uid18446_dupName_225_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18446_dupName_225_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18441_dupName_225_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18444_dupName_225_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18446_dupName_225_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18446_dupName_225_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18441_dupName_225_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18446_dupName_225_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18444_dupName_225_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18446_dupName_225_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18451_dupName_225_i_unnamed_c_compstr0_shift_x(MUX,18450)@125
    assign rightShiftStage2_uid18451_dupName_225_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18451_dupName_225_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18446_dupName_225_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18449_dupName_225_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18451_dupName_225_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18451_dupName_225_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18446_dupName_225_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18451_dupName_225_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18449_dupName_225_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18451_dupName_225_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1605_vt_select_20(BITSELECT,10322)@125
    assign i_unnamed_c_compstr1605_vt_select_20_b = rightShiftStage2_uid18451_dupName_225_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1605_vt_join(BITJOIN,10321)@125
    assign i_unnamed_c_compstr1605_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1605_vt_select_20_b};

    // i_conv_i_i_i_i_i_56_c_compstr1606_sel_x(BITSELECT,3791)@125
    assign i_conv_i_i_i_i_i_56_c_compstr1606_sel_x_b = i_unnamed_c_compstr1605_vt_join_q[15:0];

    // redist1074_i_conv_i_i_i_i_i_56_c_compstr1606_sel_x_b_1(DELAY,29302)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1074_i_conv_i_i_i_i_i_56_c_compstr1606_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_56_c_compstr1606_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18460_dupName_226_i_unnamed_c_compstr0_shift_x(BITSELECT,18459)@125
    assign rightShiftStage1Idx1Rng8_uid18460_dupName_226_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18459_dupName_226_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18462_dupName_226_i_unnamed_c_compstr0_shift_x(BITJOIN,18461)@125
    assign rightShiftStage1Idx1_uid18462_dupName_226_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18460_dupName_226_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18455_dupName_226_i_unnamed_c_compstr0_shift_x(BITSELECT,18454)@125
    assign rightShiftStage0Idx1Rng4_uid18455_dupName_226_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_q[33:4];

    // rightShiftStage0Idx1_uid18457_dupName_226_i_unnamed_c_compstr0_shift_x(BITJOIN,18456)@125
    assign rightShiftStage0Idx1_uid18457_dupName_226_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18455_dupName_226_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18459_dupName_226_i_unnamed_c_compstr0_shift_x(MUX,18458)@125
    assign rightShiftStage0_uid18459_dupName_226_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18459_dupName_226_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_q or rightShiftStage0Idx1_uid18457_dupName_226_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18459_dupName_226_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18459_dupName_226_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compstr1604_q;
            1'b1 : rightShiftStage0_uid18459_dupName_226_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18457_dupName_226_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18459_dupName_226_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18464_dupName_226_i_unnamed_c_compstr0_shift_x(MUX,18463)@125
    assign rightShiftStage1_uid18464_dupName_226_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18464_dupName_226_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18459_dupName_226_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18462_dupName_226_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18464_dupName_226_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18464_dupName_226_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18459_dupName_226_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18464_dupName_226_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18462_dupName_226_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18464_dupName_226_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1607_vt_select_21(BITSELECT,10325)@125
    assign i_unnamed_c_compstr1607_vt_select_21_b = rightShiftStage1_uid18464_dupName_226_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1607_vt_join(BITJOIN,10324)@125
    assign i_unnamed_c_compstr1607_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1607_vt_select_21_b};

    // i_unnamed_c_compstr1608_sel_x(BITSELECT,6082)@125
    assign i_unnamed_c_compstr1608_sel_x_b = i_unnamed_c_compstr1607_vt_join_q[15:0];

    // i_unnamed_c_compstr1609_BitSelect_for_a(BITSELECT,27553)@125
    assign i_unnamed_c_compstr1609_BitSelect_for_a_b = i_unnamed_c_compstr1608_sel_x_b[0:0];

    // i_unnamed_c_compstr1609_join(BITJOIN,27554)@125
    assign i_unnamed_c_compstr1609_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1609_BitSelect_for_a_b};

    // i_unnamed_c_compstr1609_vt_select_0(BITSELECT,10330)@125
    assign i_unnamed_c_compstr1609_vt_select_0_b = i_unnamed_c_compstr1609_join_q[0:0];

    // redist208_i_unnamed_c_compstr1609_vt_select_0_b_1(DELAY,28436)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist208_i_unnamed_c_compstr1609_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1609_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1609_vt_join(BITJOIN,10329)@126
    assign i_unnamed_c_compstr1609_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist208_i_unnamed_c_compstr1609_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_56_c_compstr1610(ADD,7058)@126
    assign i_add_i_i_i_i_i_i_56_c_compstr1610_a = {1'b0, i_unnamed_c_compstr1609_vt_join_q};
    assign i_add_i_i_i_i_i_i_56_c_compstr1610_b = {1'b0, redist1074_i_conv_i_i_i_i_i_56_c_compstr1606_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_56_c_compstr1610_o = $unsigned(i_add_i_i_i_i_i_i_56_c_compstr1610_a) + $unsigned(i_add_i_i_i_i_i_i_56_c_compstr1610_b);
    assign i_add_i_i_i_i_i_i_56_c_compstr1610_q = i_add_i_i_i_i_i_i_56_c_compstr1610_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_56_c_compstr1610_sel_x(BITSELECT,2252)@126
    assign bgTrunc_i_add_i_i_i_i_i_i_56_c_compstr1610_sel_x_b = i_add_i_i_i_i_i_i_56_c_compstr1610_q[15:0];

    // i_conv_i_i_i_i_i_i279_57_c_compstr1630_sel_x(BITSELECT,3920)@126
    assign i_conv_i_i_i_i_i_i279_57_c_compstr1630_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_56_c_compstr1610_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_57_c_compstr1630_vt_select_15(BITSELECT,8197)@126
    assign i_conv_i_i_i_i_i_i279_57_c_compstr1630_vt_select_15_b = i_conv_i_i_i_i_i_i279_57_c_compstr1630_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_57_c_compstr1630_vt_join(BITJOIN,8196)@126
    assign i_conv_i_i_i_i_i_i279_57_c_compstr1630_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_57_c_compstr1630_vt_select_15_b};

    // leftShiftStage0_uid26582_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x(MUX,26581)@126
    assign leftShiftStage0_uid26582_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26582_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_57_c_compstr1630_vt_join_q or leftShiftStage0Idx1_uid26580_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26582_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26582_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_57_c_compstr1630_vt_join_q;
            1'b1 : leftShiftStage0_uid26582_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26580_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26582_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26587_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x(MUX,26586)@126
    assign leftShiftStage1_uid26587_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26587_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_s or leftShiftStage0_uid26582_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26585_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26587_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26587_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q = leftShiftStage0_uid26582_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26587_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26585_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26587_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26592_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x(MUX,26591)@126
    assign leftShiftStage2_uid26592_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26592_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_s or leftShiftStage1_uid26587_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26590_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26592_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26592_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q = leftShiftStage1_uid26587_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26592_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26590_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26592_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_57_c_compstr1631_vt_select_28(BITSELECT,9661)@126
    assign i_shl_i_i_i_i_i_i_57_c_compstr1631_vt_select_28_b = leftShiftStage2_uid26592_i_shl_i_i_i_i_i_i_57_c_compstr0_shift_x_q[28:13];

    // redist303_i_shl_i_i_i_i_i_i_57_c_compstr1631_vt_select_28_b_1(DELAY,28531)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist303_i_shl_i_i_i_i_i_i_57_c_compstr1631_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_57_c_compstr1631_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_57_c_compstr1631_vt_join(BITJOIN,9660)@127
    assign i_shl_i_i_i_i_i_i_57_c_compstr1631_vt_join_q = {redist303_i_shl_i_i_i_i_i_i_57_c_compstr1631_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_offset(CONSTANT,30222)
    assign redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_offset_q = $unsigned(7'b0010100);

    // redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_rdcnt(ADD,31671)
    assign redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_a = {1'b0, redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_wraddr_q};
    assign redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_b = {1'b0, redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_o <= $unsigned(redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_a) + $unsigned(redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_b);
        end
    end
    assign redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_q = redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_o[7:0];

    // redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_inputreg0(DELAY,31666)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl);
        end
    end

    // redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_wraddr(COUNTER,31669)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_wraddr_i <= $unsigned(redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_wraddr_q = redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_wraddr_i[6:0];

    // redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem(DUALMEM,31668)
    assign redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_ia = $unsigned(redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_inputreg0_q);
    assign redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_aa = redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_wraddr_q;
    assign redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_ab = redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_aa),
        .data_a(redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_ab),
        .q_b(redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_q = redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_iq[15:0];

    // redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_outputreg0(DELAY,31667)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_outputreg0_q <= $unsigned(redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_mem_q);
        end
    end

    // redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_rdcnt(ADD,30223)
    assign redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_a = {1'b0, redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_wraddr_q};
    assign redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_b = {1'b0, redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_o <= $unsigned(redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_a) + $unsigned(redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_b);
        end
    end
    assign redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_q = redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_o[7:0];

    // redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_inputreg0(DELAY,30218)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl);
        end
    end

    // redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_wraddr(COUNTER,30221)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_wraddr_i <= $unsigned(redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_wraddr_q = redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_wraddr_i[6:0];

    // redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem(DUALMEM,30220)
    assign redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_ia = $unsigned(redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_inputreg0_q);
    assign redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_aa = redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_wraddr_q;
    assign redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_ab = redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_aa),
        .data_a(redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_ab),
        .q_b(redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_q = redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_iq[15:0];

    // redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_outputreg0(DELAY,30219)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_outputreg0_q <= $unsigned(redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_mem_q);
        end
    end

    // redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_rdcnt(ADD,30229)
    assign redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_a = {1'b0, redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_wraddr_q};
    assign redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_b = {1'b0, redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_o <= $unsigned(redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_a) + $unsigned(redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_b);
        end
    end
    assign redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_q = redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_o[7:0];

    // redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_inputreg0(DELAY,30224)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl);
        end
    end

    // redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_wraddr(COUNTER,30227)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_wraddr_i <= $unsigned(redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_wraddr_q = redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_wraddr_i[6:0];

    // redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem(DUALMEM,30226)
    assign redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_ia = $unsigned(redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_inputreg0_q);
    assign redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_aa = redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_wraddr_q;
    assign redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_ab = redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_aa),
        .data_a(redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_ab),
        .q_b(redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_q = redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_iq[15:0];

    // redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_outputreg0(DELAY,30225)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_outputreg0_q <= $unsigned(redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_mem_q);
        end
    end

    // redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_rdcnt(ADD,31665)
    assign redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_a = {1'b0, redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_wraddr_q};
    assign redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_b = {1'b0, redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_o <= $unsigned(redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_a) + $unsigned(redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_b);
        end
    end
    assign redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_q = redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_o[7:0];

    // redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_inputreg0(DELAY,31660)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl);
        end
    end

    // redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_wraddr(COUNTER,31663)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_wraddr_i <= $unsigned(redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_wraddr_q = redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_wraddr_i[6:0];

    // redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem(DUALMEM,31662)
    assign redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_ia = $unsigned(redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_inputreg0_q);
    assign redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_aa = redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_wraddr_q;
    assign redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_ab = redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_aa),
        .data_a(redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_ab),
        .q_b(redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_q = redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_iq[15:0];

    // redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_outputreg0(DELAY,31661)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_outputreg0_q <= $unsigned(redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28016)@121 + 5
    // out q@127
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632(ADD,8601)@127
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod326_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_b = $unsigned({{5{i_shl_i_i_i_i_i_i_57_c_compstr1631_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_57_c_compstr1631_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_o[33:0];

    // rightShiftStage0_uid18503_dupName_229_i_unnamed_c_compstr0_shift_x(MUX,18502)@127
    assign rightShiftStage0_uid18503_dupName_229_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18503_dupName_229_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_q or rightShiftStage0Idx1_uid18501_dupName_229_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18503_dupName_229_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18503_dupName_229_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_q;
            1'b1 : rightShiftStage0_uid18503_dupName_229_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18501_dupName_229_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18503_dupName_229_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18508_dupName_229_i_unnamed_c_compstr0_shift_x(MUX,18507)@127
    assign rightShiftStage1_uid18508_dupName_229_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18508_dupName_229_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18503_dupName_229_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18506_dupName_229_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18508_dupName_229_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18508_dupName_229_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18503_dupName_229_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18508_dupName_229_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18506_dupName_229_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18508_dupName_229_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18513_dupName_229_i_unnamed_c_compstr0_shift_x(MUX,18512)@127
    assign rightShiftStage2_uid18513_dupName_229_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18513_dupName_229_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18508_dupName_229_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18511_dupName_229_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18513_dupName_229_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18513_dupName_229_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18508_dupName_229_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18513_dupName_229_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18511_dupName_229_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18513_dupName_229_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1633_vt_select_20(BITSELECT,10347)@127
    assign i_unnamed_c_compstr1633_vt_select_20_b = rightShiftStage2_uid18513_dupName_229_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1633_vt_join(BITJOIN,10346)@127
    assign i_unnamed_c_compstr1633_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1633_vt_select_20_b};

    // i_conv_i_i_i_i_i_57_c_compstr1634_sel_x(BITSELECT,3792)@127
    assign i_conv_i_i_i_i_i_57_c_compstr1634_sel_x_b = i_unnamed_c_compstr1633_vt_join_q[15:0];

    // redist1073_i_conv_i_i_i_i_i_57_c_compstr1634_sel_x_b_1(DELAY,29301)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1073_i_conv_i_i_i_i_i_57_c_compstr1634_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_57_c_compstr1634_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18522_dupName_230_i_unnamed_c_compstr0_shift_x(BITSELECT,18521)@127
    assign rightShiftStage1Idx1Rng8_uid18522_dupName_230_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18521_dupName_230_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18524_dupName_230_i_unnamed_c_compstr0_shift_x(BITJOIN,18523)@127
    assign rightShiftStage1Idx1_uid18524_dupName_230_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18522_dupName_230_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18517_dupName_230_i_unnamed_c_compstr0_shift_x(BITSELECT,18516)@127
    assign rightShiftStage0Idx1Rng4_uid18517_dupName_230_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_q[33:4];

    // rightShiftStage0Idx1_uid18519_dupName_230_i_unnamed_c_compstr0_shift_x(BITJOIN,18518)@127
    assign rightShiftStage0Idx1_uid18519_dupName_230_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18517_dupName_230_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18521_dupName_230_i_unnamed_c_compstr0_shift_x(MUX,18520)@127
    assign rightShiftStage0_uid18521_dupName_230_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18521_dupName_230_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_q or rightShiftStage0Idx1_uid18519_dupName_230_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18521_dupName_230_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18521_dupName_230_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compstr1632_q;
            1'b1 : rightShiftStage0_uid18521_dupName_230_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18519_dupName_230_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18521_dupName_230_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18526_dupName_230_i_unnamed_c_compstr0_shift_x(MUX,18525)@127
    assign rightShiftStage1_uid18526_dupName_230_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18526_dupName_230_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18521_dupName_230_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18524_dupName_230_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18526_dupName_230_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18526_dupName_230_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18521_dupName_230_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18526_dupName_230_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18524_dupName_230_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18526_dupName_230_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1635_vt_select_21(BITSELECT,10350)@127
    assign i_unnamed_c_compstr1635_vt_select_21_b = rightShiftStage1_uid18526_dupName_230_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1635_vt_join(BITJOIN,10349)@127
    assign i_unnamed_c_compstr1635_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1635_vt_select_21_b};

    // i_unnamed_c_compstr1636_sel_x(BITSELECT,6084)@127
    assign i_unnamed_c_compstr1636_sel_x_b = i_unnamed_c_compstr1635_vt_join_q[15:0];

    // i_unnamed_c_compstr1637_BitSelect_for_a(BITSELECT,27557)@127
    assign i_unnamed_c_compstr1637_BitSelect_for_a_b = i_unnamed_c_compstr1636_sel_x_b[0:0];

    // i_unnamed_c_compstr1637_join(BITJOIN,27558)@127
    assign i_unnamed_c_compstr1637_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1637_BitSelect_for_a_b};

    // i_unnamed_c_compstr1637_vt_select_0(BITSELECT,10355)@127
    assign i_unnamed_c_compstr1637_vt_select_0_b = i_unnamed_c_compstr1637_join_q[0:0];

    // redist206_i_unnamed_c_compstr1637_vt_select_0_b_1(DELAY,28434)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist206_i_unnamed_c_compstr1637_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1637_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1637_vt_join(BITJOIN,10354)@128
    assign i_unnamed_c_compstr1637_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist206_i_unnamed_c_compstr1637_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_57_c_compstr1638(ADD,7059)@128
    assign i_add_i_i_i_i_i_i_57_c_compstr1638_a = {1'b0, i_unnamed_c_compstr1637_vt_join_q};
    assign i_add_i_i_i_i_i_i_57_c_compstr1638_b = {1'b0, redist1073_i_conv_i_i_i_i_i_57_c_compstr1634_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_57_c_compstr1638_o = $unsigned(i_add_i_i_i_i_i_i_57_c_compstr1638_a) + $unsigned(i_add_i_i_i_i_i_i_57_c_compstr1638_b);
    assign i_add_i_i_i_i_i_i_57_c_compstr1638_q = i_add_i_i_i_i_i_i_57_c_compstr1638_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_57_c_compstr1638_sel_x(BITSELECT,2253)@128
    assign bgTrunc_i_add_i_i_i_i_i_i_57_c_compstr1638_sel_x_b = i_add_i_i_i_i_i_i_57_c_compstr1638_q[15:0];

    // i_conv_i_i_i_i_i_i279_58_c_compstr1658_sel_x(BITSELECT,3921)@128
    assign i_conv_i_i_i_i_i_i279_58_c_compstr1658_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_57_c_compstr1638_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_58_c_compstr1658_vt_select_15(BITSELECT,8201)@128
    assign i_conv_i_i_i_i_i_i279_58_c_compstr1658_vt_select_15_b = i_conv_i_i_i_i_i_i279_58_c_compstr1658_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_58_c_compstr1658_vt_join(BITJOIN,8200)@128
    assign i_conv_i_i_i_i_i_i279_58_c_compstr1658_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_58_c_compstr1658_vt_select_15_b};

    // leftShiftStage0_uid26600_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x(MUX,26599)@128
    assign leftShiftStage0_uid26600_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26600_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_58_c_compstr1658_vt_join_q or leftShiftStage0Idx1_uid26598_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26600_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26600_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_58_c_compstr1658_vt_join_q;
            1'b1 : leftShiftStage0_uid26600_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26598_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26600_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26605_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x(MUX,26604)@128
    assign leftShiftStage1_uid26605_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26605_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_s or leftShiftStage0_uid26600_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26603_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26605_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26605_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q = leftShiftStage0_uid26600_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26605_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26603_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26605_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26610_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x(MUX,26609)@128
    assign leftShiftStage2_uid26610_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26610_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_s or leftShiftStage1_uid26605_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26608_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26610_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26610_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q = leftShiftStage1_uid26605_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26610_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26608_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26610_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_58_c_compstr1659_vt_select_28(BITSELECT,9664)@128
    assign i_shl_i_i_i_i_i_i_58_c_compstr1659_vt_select_28_b = leftShiftStage2_uid26610_i_shl_i_i_i_i_i_i_58_c_compstr0_shift_x_q[28:13];

    // redist302_i_shl_i_i_i_i_i_i_58_c_compstr1659_vt_select_28_b_1(DELAY,28530)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist302_i_shl_i_i_i_i_i_i_58_c_compstr1659_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_58_c_compstr1659_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_58_c_compstr1659_vt_join(BITJOIN,9663)@129
    assign i_shl_i_i_i_i_i_i_58_c_compstr1659_vt_join_q = {redist302_i_shl_i_i_i_i_i_i_58_c_compstr1659_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_offset(CONSTANT,30234)
    assign redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_offset_q = $unsigned(7'b0010010);

    // redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_rdcnt(ADD,31683)
    assign redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_a = {1'b0, redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_wraddr_q};
    assign redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_b = {1'b0, redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_o <= $unsigned(redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_a) + $unsigned(redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_b);
        end
    end
    assign redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_q = redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_o[7:0];

    // redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_inputreg0(DELAY,31678)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl);
        end
    end

    // redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_wraddr(COUNTER,31681)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_wraddr_i <= $unsigned(redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_wraddr_q = redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_wraddr_i[6:0];

    // redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem(DUALMEM,31680)
    assign redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_ia = $unsigned(redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_inputreg0_q);
    assign redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_aa = redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_wraddr_q;
    assign redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_ab = redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_aa),
        .data_a(redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_ab),
        .q_b(redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_q = redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_iq[15:0];

    // redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_outputreg0(DELAY,31679)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_outputreg0_q <= $unsigned(redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_mem_q);
        end
    end

    // redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_rdcnt(ADD,30235)
    assign redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_a = {1'b0, redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_wraddr_q};
    assign redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_b = {1'b0, redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_o <= $unsigned(redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_a) + $unsigned(redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_b);
        end
    end
    assign redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_q = redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_o[7:0];

    // redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_inputreg0(DELAY,30230)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl);
        end
    end

    // redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_wraddr(COUNTER,30233)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_wraddr_i <= $unsigned(redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_wraddr_q = redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_wraddr_i[6:0];

    // redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem(DUALMEM,30232)
    assign redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_ia = $unsigned(redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_inputreg0_q);
    assign redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_aa = redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_wraddr_q;
    assign redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_ab = redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_aa),
        .data_a(redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_ab),
        .q_b(redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_q = redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_iq[15:0];

    // redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_outputreg0(DELAY,30231)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_outputreg0_q <= $unsigned(redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_mem_q);
        end
    end

    // redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_rdcnt(ADD,30241)
    assign redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_a = {1'b0, redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_wraddr_q};
    assign redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_b = {1'b0, redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_o <= $unsigned(redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_a) + $unsigned(redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_b);
        end
    end
    assign redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_q = redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_o[7:0];

    // redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_inputreg0(DELAY,30236)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl);
        end
    end

    // redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_wraddr(COUNTER,30239)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_wraddr_i <= $unsigned(redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_wraddr_q = redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_wraddr_i[6:0];

    // redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem(DUALMEM,30238)
    assign redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_ia = $unsigned(redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_inputreg0_q);
    assign redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_aa = redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_wraddr_q;
    assign redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_ab = redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_aa),
        .data_a(redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_ab),
        .q_b(redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_q = redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_iq[15:0];

    // redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_outputreg0(DELAY,30237)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_outputreg0_q <= $unsigned(redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_mem_q);
        end
    end

    // redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_rdcnt(ADD,31677)
    assign redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_a = {1'b0, redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_wraddr_q};
    assign redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_b = {1'b0, redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_o <= $unsigned(redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_a) + $unsigned(redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_b);
        end
    end
    assign redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_q = redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_o[7:0];

    // redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_inputreg0(DELAY,31672)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl);
        end
    end

    // redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_wraddr(COUNTER,31675)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_wraddr_i <= $unsigned(redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_wraddr_q = redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_wraddr_i[6:0];

    // redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem(DUALMEM,31674)
    assign redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_ia = $unsigned(redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_inputreg0_q);
    assign redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_aa = redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_wraddr_q;
    assign redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_ab = redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_aa),
        .data_a(redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_ab),
        .q_b(redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_q = redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_iq[15:0];

    // redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_outputreg0(DELAY,31673)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_outputreg0_q <= $unsigned(redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28017)@123 + 5
    // out q@129
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660(ADD,8602)@129
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod331_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_b = $unsigned({{5{i_shl_i_i_i_i_i_i_58_c_compstr1659_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_58_c_compstr1659_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_o[33:0];

    // rightShiftStage0_uid18565_dupName_233_i_unnamed_c_compstr0_shift_x(MUX,18564)@129
    assign rightShiftStage0_uid18565_dupName_233_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18565_dupName_233_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_q or rightShiftStage0Idx1_uid18563_dupName_233_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18565_dupName_233_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18565_dupName_233_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_q;
            1'b1 : rightShiftStage0_uid18565_dupName_233_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18563_dupName_233_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18565_dupName_233_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18570_dupName_233_i_unnamed_c_compstr0_shift_x(MUX,18569)@129
    assign rightShiftStage1_uid18570_dupName_233_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18570_dupName_233_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18565_dupName_233_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18568_dupName_233_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18570_dupName_233_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18570_dupName_233_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18565_dupName_233_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18570_dupName_233_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18568_dupName_233_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18570_dupName_233_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18575_dupName_233_i_unnamed_c_compstr0_shift_x(MUX,18574)@129
    assign rightShiftStage2_uid18575_dupName_233_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18575_dupName_233_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18570_dupName_233_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18573_dupName_233_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18575_dupName_233_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18575_dupName_233_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18570_dupName_233_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18575_dupName_233_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18573_dupName_233_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18575_dupName_233_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1661_vt_select_20(BITSELECT,10377)@129
    assign i_unnamed_c_compstr1661_vt_select_20_b = rightShiftStage2_uid18575_dupName_233_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1661_vt_join(BITJOIN,10376)@129
    assign i_unnamed_c_compstr1661_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1661_vt_select_20_b};

    // i_conv_i_i_i_i_i_58_c_compstr1662_sel_x(BITSELECT,3793)@129
    assign i_conv_i_i_i_i_i_58_c_compstr1662_sel_x_b = i_unnamed_c_compstr1661_vt_join_q[15:0];

    // redist1072_i_conv_i_i_i_i_i_58_c_compstr1662_sel_x_b_1(DELAY,29300)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1072_i_conv_i_i_i_i_i_58_c_compstr1662_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_58_c_compstr1662_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18584_dupName_234_i_unnamed_c_compstr0_shift_x(BITSELECT,18583)@129
    assign rightShiftStage1Idx1Rng8_uid18584_dupName_234_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18583_dupName_234_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18586_dupName_234_i_unnamed_c_compstr0_shift_x(BITJOIN,18585)@129
    assign rightShiftStage1Idx1_uid18586_dupName_234_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18584_dupName_234_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18579_dupName_234_i_unnamed_c_compstr0_shift_x(BITSELECT,18578)@129
    assign rightShiftStage0Idx1Rng4_uid18579_dupName_234_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_q[33:4];

    // rightShiftStage0Idx1_uid18581_dupName_234_i_unnamed_c_compstr0_shift_x(BITJOIN,18580)@129
    assign rightShiftStage0Idx1_uid18581_dupName_234_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18579_dupName_234_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18583_dupName_234_i_unnamed_c_compstr0_shift_x(MUX,18582)@129
    assign rightShiftStage0_uid18583_dupName_234_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18583_dupName_234_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_q or rightShiftStage0Idx1_uid18581_dupName_234_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18583_dupName_234_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18583_dupName_234_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compstr1660_q;
            1'b1 : rightShiftStage0_uid18583_dupName_234_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18581_dupName_234_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18583_dupName_234_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18588_dupName_234_i_unnamed_c_compstr0_shift_x(MUX,18587)@129
    assign rightShiftStage1_uid18588_dupName_234_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18588_dupName_234_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18583_dupName_234_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18586_dupName_234_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18588_dupName_234_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18588_dupName_234_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18583_dupName_234_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18588_dupName_234_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18586_dupName_234_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18588_dupName_234_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1663_vt_select_21(BITSELECT,10380)@129
    assign i_unnamed_c_compstr1663_vt_select_21_b = rightShiftStage1_uid18588_dupName_234_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1663_vt_join(BITJOIN,10379)@129
    assign i_unnamed_c_compstr1663_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1663_vt_select_21_b};

    // i_unnamed_c_compstr1664_sel_x(BITSELECT,6087)@129
    assign i_unnamed_c_compstr1664_sel_x_b = i_unnamed_c_compstr1663_vt_join_q[15:0];

    // i_unnamed_c_compstr1665_BitSelect_for_a(BITSELECT,27563)@129
    assign i_unnamed_c_compstr1665_BitSelect_for_a_b = i_unnamed_c_compstr1664_sel_x_b[0:0];

    // i_unnamed_c_compstr1665_join(BITJOIN,27564)@129
    assign i_unnamed_c_compstr1665_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1665_BitSelect_for_a_b};

    // i_unnamed_c_compstr1665_vt_select_0(BITSELECT,10385)@129
    assign i_unnamed_c_compstr1665_vt_select_0_b = i_unnamed_c_compstr1665_join_q[0:0];

    // redist203_i_unnamed_c_compstr1665_vt_select_0_b_1(DELAY,28431)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist203_i_unnamed_c_compstr1665_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1665_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1665_vt_join(BITJOIN,10384)@130
    assign i_unnamed_c_compstr1665_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist203_i_unnamed_c_compstr1665_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_58_c_compstr1666(ADD,7060)@130
    assign i_add_i_i_i_i_i_i_58_c_compstr1666_a = {1'b0, i_unnamed_c_compstr1665_vt_join_q};
    assign i_add_i_i_i_i_i_i_58_c_compstr1666_b = {1'b0, redist1072_i_conv_i_i_i_i_i_58_c_compstr1662_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_58_c_compstr1666_o = $unsigned(i_add_i_i_i_i_i_i_58_c_compstr1666_a) + $unsigned(i_add_i_i_i_i_i_i_58_c_compstr1666_b);
    assign i_add_i_i_i_i_i_i_58_c_compstr1666_q = i_add_i_i_i_i_i_i_58_c_compstr1666_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_58_c_compstr1666_sel_x(BITSELECT,2254)@130
    assign bgTrunc_i_add_i_i_i_i_i_i_58_c_compstr1666_sel_x_b = i_add_i_i_i_i_i_i_58_c_compstr1666_q[15:0];

    // i_conv_i_i_i_i_i_i279_59_c_compstr1686_sel_x(BITSELECT,3922)@130
    assign i_conv_i_i_i_i_i_i279_59_c_compstr1686_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_58_c_compstr1666_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_59_c_compstr1686_vt_select_15(BITSELECT,8205)@130
    assign i_conv_i_i_i_i_i_i279_59_c_compstr1686_vt_select_15_b = i_conv_i_i_i_i_i_i279_59_c_compstr1686_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_59_c_compstr1686_vt_join(BITJOIN,8204)@130
    assign i_conv_i_i_i_i_i_i279_59_c_compstr1686_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_59_c_compstr1686_vt_select_15_b};

    // leftShiftStage0_uid26618_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x(MUX,26617)@130
    assign leftShiftStage0_uid26618_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26618_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_59_c_compstr1686_vt_join_q or leftShiftStage0Idx1_uid26616_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26618_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26618_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_59_c_compstr1686_vt_join_q;
            1'b1 : leftShiftStage0_uid26618_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26616_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26618_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26623_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x(MUX,26622)@130
    assign leftShiftStage1_uid26623_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26623_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_s or leftShiftStage0_uid26618_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26621_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26623_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26623_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q = leftShiftStage0_uid26618_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26623_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26621_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26623_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26628_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x(MUX,26627)@130
    assign leftShiftStage2_uid26628_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26628_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_s or leftShiftStage1_uid26623_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26626_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26628_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26628_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q = leftShiftStage1_uid26623_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26628_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26626_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26628_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_59_c_compstr1687_vt_select_28(BITSELECT,9667)@130
    assign i_shl_i_i_i_i_i_i_59_c_compstr1687_vt_select_28_b = leftShiftStage2_uid26628_i_shl_i_i_i_i_i_i_59_c_compstr0_shift_x_q[28:13];

    // redist301_i_shl_i_i_i_i_i_i_59_c_compstr1687_vt_select_28_b_1(DELAY,28529)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist301_i_shl_i_i_i_i_i_i_59_c_compstr1687_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_59_c_compstr1687_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_59_c_compstr1687_vt_join(BITJOIN,9666)@131
    assign i_shl_i_i_i_i_i_i_59_c_compstr1687_vt_join_q = {redist301_i_shl_i_i_i_i_i_i_59_c_compstr1687_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_offset(CONSTANT,30246)
    assign redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_offset_q = $unsigned(7'b0010000);

    // redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_rdcnt(ADD,31695)
    assign redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_a = {1'b0, redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_wraddr_q};
    assign redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_b = {1'b0, redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_o <= $unsigned(redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_a) + $unsigned(redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_b);
        end
    end
    assign redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_q = redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_o[7:0];

    // redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_inputreg0(DELAY,31690)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl);
        end
    end

    // redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_wraddr(COUNTER,31693)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_wraddr_i <= $unsigned(redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_wraddr_q = redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_wraddr_i[6:0];

    // redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem(DUALMEM,31692)
    assign redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_ia = $unsigned(redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_inputreg0_q);
    assign redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_aa = redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_wraddr_q;
    assign redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_ab = redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_aa),
        .data_a(redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_ab),
        .q_b(redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_q = redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_iq[15:0];

    // redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_outputreg0(DELAY,31691)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_outputreg0_q <= $unsigned(redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_mem_q);
        end
    end

    // redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_rdcnt(ADD,30247)
    assign redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_a = {1'b0, redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_wraddr_q};
    assign redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_b = {1'b0, redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_o <= $unsigned(redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_a) + $unsigned(redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_b);
        end
    end
    assign redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_q = redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_o[7:0];

    // redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_inputreg0(DELAY,30242)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl);
        end
    end

    // redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_wraddr(COUNTER,30245)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_wraddr_i <= $unsigned(redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_wraddr_q = redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_wraddr_i[6:0];

    // redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem(DUALMEM,30244)
    assign redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_ia = $unsigned(redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_inputreg0_q);
    assign redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_aa = redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_wraddr_q;
    assign redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_ab = redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_aa),
        .data_a(redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_ab),
        .q_b(redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_q = redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_iq[15:0];

    // redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_outputreg0(DELAY,30243)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_outputreg0_q <= $unsigned(redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_mem_q);
        end
    end

    // redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_rdcnt(ADD,30253)
    assign redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_a = {1'b0, redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_wraddr_q};
    assign redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_b = {1'b0, redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_o <= $unsigned(redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_a) + $unsigned(redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_b);
        end
    end
    assign redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_q = redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_o[7:0];

    // redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_inputreg0(DELAY,30248)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl);
        end
    end

    // redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_wraddr(COUNTER,30251)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_wraddr_i <= $unsigned(redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_wraddr_q = redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_wraddr_i[6:0];

    // redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem(DUALMEM,30250)
    assign redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_ia = $unsigned(redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_inputreg0_q);
    assign redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_aa = redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_wraddr_q;
    assign redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_ab = redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_aa),
        .data_a(redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_ab),
        .q_b(redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_q = redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_iq[15:0];

    // redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_outputreg0(DELAY,30249)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_outputreg0_q <= $unsigned(redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_mem_q);
        end
    end

    // redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_rdcnt(ADD,31689)
    assign redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_a = {1'b0, redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_wraddr_q};
    assign redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_b = {1'b0, redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_o <= $unsigned(redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_a) + $unsigned(redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_b);
        end
    end
    assign redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_q = redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_o[7:0];

    // redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_inputreg0(DELAY,31684)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl);
        end
    end

    // redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_wraddr(COUNTER,31687)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_wraddr_i <= $unsigned(redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_wraddr_q = redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_wraddr_i[6:0];

    // redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem(DUALMEM,31686)
    assign redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_ia = $unsigned(redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_inputreg0_q);
    assign redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_aa = redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_wraddr_q;
    assign redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_ab = redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_aa),
        .data_a(redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_ab),
        .q_b(redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_q = redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_iq[15:0];

    // redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_outputreg0(DELAY,31685)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_outputreg0_q <= $unsigned(redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28018)@125 + 5
    // out q@131
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688(ADD,8603)@131
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod336_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_b = $unsigned({{5{i_shl_i_i_i_i_i_i_59_c_compstr1687_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_59_c_compstr1687_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_o[33:0];

    // rightShiftStage0_uid18627_dupName_237_i_unnamed_c_compstr0_shift_x(MUX,18626)@131
    assign rightShiftStage0_uid18627_dupName_237_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18627_dupName_237_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_q or rightShiftStage0Idx1_uid18625_dupName_237_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18627_dupName_237_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18627_dupName_237_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_q;
            1'b1 : rightShiftStage0_uid18627_dupName_237_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18625_dupName_237_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18627_dupName_237_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18632_dupName_237_i_unnamed_c_compstr0_shift_x(MUX,18631)@131
    assign rightShiftStage1_uid18632_dupName_237_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18632_dupName_237_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18627_dupName_237_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18630_dupName_237_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18632_dupName_237_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18632_dupName_237_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18627_dupName_237_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18632_dupName_237_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18630_dupName_237_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18632_dupName_237_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18637_dupName_237_i_unnamed_c_compstr0_shift_x(MUX,18636)@131
    assign rightShiftStage2_uid18637_dupName_237_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18637_dupName_237_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18632_dupName_237_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18635_dupName_237_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18637_dupName_237_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18637_dupName_237_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18632_dupName_237_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18637_dupName_237_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18635_dupName_237_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18637_dupName_237_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1689_vt_select_20(BITSELECT,10399)@131
    assign i_unnamed_c_compstr1689_vt_select_20_b = rightShiftStage2_uid18637_dupName_237_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1689_vt_join(BITJOIN,10398)@131
    assign i_unnamed_c_compstr1689_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1689_vt_select_20_b};

    // i_conv_i_i_i_i_i_59_c_compstr1690_sel_x(BITSELECT,3794)@131
    assign i_conv_i_i_i_i_i_59_c_compstr1690_sel_x_b = i_unnamed_c_compstr1689_vt_join_q[15:0];

    // redist1071_i_conv_i_i_i_i_i_59_c_compstr1690_sel_x_b_1(DELAY,29299)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1071_i_conv_i_i_i_i_i_59_c_compstr1690_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_59_c_compstr1690_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18646_dupName_238_i_unnamed_c_compstr0_shift_x(BITSELECT,18645)@131
    assign rightShiftStage1Idx1Rng8_uid18646_dupName_238_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18645_dupName_238_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18648_dupName_238_i_unnamed_c_compstr0_shift_x(BITJOIN,18647)@131
    assign rightShiftStage1Idx1_uid18648_dupName_238_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18646_dupName_238_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18641_dupName_238_i_unnamed_c_compstr0_shift_x(BITSELECT,18640)@131
    assign rightShiftStage0Idx1Rng4_uid18641_dupName_238_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_q[33:4];

    // rightShiftStage0Idx1_uid18643_dupName_238_i_unnamed_c_compstr0_shift_x(BITJOIN,18642)@131
    assign rightShiftStage0Idx1_uid18643_dupName_238_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18641_dupName_238_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18645_dupName_238_i_unnamed_c_compstr0_shift_x(MUX,18644)@131
    assign rightShiftStage0_uid18645_dupName_238_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18645_dupName_238_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_q or rightShiftStage0Idx1_uid18643_dupName_238_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18645_dupName_238_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18645_dupName_238_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compstr1688_q;
            1'b1 : rightShiftStage0_uid18645_dupName_238_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18643_dupName_238_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18645_dupName_238_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18650_dupName_238_i_unnamed_c_compstr0_shift_x(MUX,18649)@131
    assign rightShiftStage1_uid18650_dupName_238_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18650_dupName_238_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18645_dupName_238_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18648_dupName_238_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18650_dupName_238_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18650_dupName_238_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18645_dupName_238_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18650_dupName_238_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18648_dupName_238_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18650_dupName_238_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1691_vt_select_21(BITSELECT,10402)@131
    assign i_unnamed_c_compstr1691_vt_select_21_b = rightShiftStage1_uid18650_dupName_238_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1691_vt_join(BITJOIN,10401)@131
    assign i_unnamed_c_compstr1691_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1691_vt_select_21_b};

    // i_unnamed_c_compstr1692_sel_x(BITSELECT,6089)@131
    assign i_unnamed_c_compstr1692_sel_x_b = i_unnamed_c_compstr1691_vt_join_q[15:0];

    // i_unnamed_c_compstr1693_BitSelect_for_a(BITSELECT,27567)@131
    assign i_unnamed_c_compstr1693_BitSelect_for_a_b = i_unnamed_c_compstr1692_sel_x_b[0:0];

    // i_unnamed_c_compstr1693_join(BITJOIN,27568)@131
    assign i_unnamed_c_compstr1693_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1693_BitSelect_for_a_b};

    // i_unnamed_c_compstr1693_vt_select_0(BITSELECT,10407)@131
    assign i_unnamed_c_compstr1693_vt_select_0_b = i_unnamed_c_compstr1693_join_q[0:0];

    // redist201_i_unnamed_c_compstr1693_vt_select_0_b_1(DELAY,28429)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist201_i_unnamed_c_compstr1693_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1693_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1693_vt_join(BITJOIN,10406)@132
    assign i_unnamed_c_compstr1693_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist201_i_unnamed_c_compstr1693_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_59_c_compstr1694(ADD,7061)@132
    assign i_add_i_i_i_i_i_i_59_c_compstr1694_a = {1'b0, i_unnamed_c_compstr1693_vt_join_q};
    assign i_add_i_i_i_i_i_i_59_c_compstr1694_b = {1'b0, redist1071_i_conv_i_i_i_i_i_59_c_compstr1690_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_59_c_compstr1694_o = $unsigned(i_add_i_i_i_i_i_i_59_c_compstr1694_a) + $unsigned(i_add_i_i_i_i_i_i_59_c_compstr1694_b);
    assign i_add_i_i_i_i_i_i_59_c_compstr1694_q = i_add_i_i_i_i_i_i_59_c_compstr1694_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_59_c_compstr1694_sel_x(BITSELECT,2255)@132
    assign bgTrunc_i_add_i_i_i_i_i_i_59_c_compstr1694_sel_x_b = i_add_i_i_i_i_i_i_59_c_compstr1694_q[15:0];

    // i_conv_i_i_i_i_i_i279_60_c_compstr1714_sel_x(BITSELECT,3924)@132
    assign i_conv_i_i_i_i_i_i279_60_c_compstr1714_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_59_c_compstr1694_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_60_c_compstr1714_vt_select_15(BITSELECT,8213)@132
    assign i_conv_i_i_i_i_i_i279_60_c_compstr1714_vt_select_15_b = i_conv_i_i_i_i_i_i279_60_c_compstr1714_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_60_c_compstr1714_vt_join(BITJOIN,8212)@132
    assign i_conv_i_i_i_i_i_i279_60_c_compstr1714_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_60_c_compstr1714_vt_select_15_b};

    // leftShiftStage0_uid26654_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x(MUX,26653)@132
    assign leftShiftStage0_uid26654_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26654_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_60_c_compstr1714_vt_join_q or leftShiftStage0Idx1_uid26652_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26654_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26654_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_60_c_compstr1714_vt_join_q;
            1'b1 : leftShiftStage0_uid26654_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26652_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26654_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26659_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x(MUX,26658)@132
    assign leftShiftStage1_uid26659_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26659_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_s or leftShiftStage0_uid26654_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26657_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26659_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26659_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q = leftShiftStage0_uid26654_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26659_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26657_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26659_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26664_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x(MUX,26663)@132
    assign leftShiftStage2_uid26664_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26664_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_s or leftShiftStage1_uid26659_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26662_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26664_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26664_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q = leftShiftStage1_uid26659_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26664_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26662_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26664_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_60_c_compstr1715_vt_select_28(BITSELECT,9673)@132
    assign i_shl_i_i_i_i_i_i_60_c_compstr1715_vt_select_28_b = leftShiftStage2_uid26664_i_shl_i_i_i_i_i_i_60_c_compstr0_shift_x_q[28:13];

    // redist299_i_shl_i_i_i_i_i_i_60_c_compstr1715_vt_select_28_b_1(DELAY,28527)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist299_i_shl_i_i_i_i_i_i_60_c_compstr1715_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_60_c_compstr1715_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_60_c_compstr1715_vt_join(BITJOIN,9672)@133
    assign i_shl_i_i_i_i_i_i_60_c_compstr1715_vt_join_q = {redist299_i_shl_i_i_i_i_i_i_60_c_compstr1715_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_offset(CONSTANT,30258)
    assign redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_offset_q = $unsigned(7'b0001110);

    // redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_rdcnt(ADD,31707)
    assign redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_a = {1'b0, redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_wraddr_q};
    assign redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_b = {1'b0, redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_o <= $unsigned(redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_a) + $unsigned(redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_b);
        end
    end
    assign redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_q = redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_o[7:0];

    // redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_inputreg0(DELAY,31702)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl);
        end
    end

    // redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_wraddr(COUNTER,31705)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_wraddr_i <= $unsigned(redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_wraddr_q = redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_wraddr_i[6:0];

    // redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem(DUALMEM,31704)
    assign redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_ia = $unsigned(redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_inputreg0_q);
    assign redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_aa = redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_wraddr_q;
    assign redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_ab = redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_aa),
        .data_a(redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_ab),
        .q_b(redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_q = redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_iq[15:0];

    // redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_outputreg0(DELAY,31703)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_outputreg0_q <= $unsigned(redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_mem_q);
        end
    end

    // redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_rdcnt(ADD,30259)
    assign redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_a = {1'b0, redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_wraddr_q};
    assign redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_b = {1'b0, redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_o <= $unsigned(redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_a) + $unsigned(redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_b);
        end
    end
    assign redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_q = redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_o[7:0];

    // redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_inputreg0(DELAY,30254)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl);
        end
    end

    // redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_wraddr(COUNTER,30257)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_wraddr_i <= $unsigned(redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_wraddr_q = redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_wraddr_i[6:0];

    // redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem(DUALMEM,30256)
    assign redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_ia = $unsigned(redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_inputreg0_q);
    assign redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_aa = redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_wraddr_q;
    assign redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_ab = redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_aa),
        .data_a(redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_ab),
        .q_b(redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_q = redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_iq[15:0];

    // redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_outputreg0(DELAY,30255)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_outputreg0_q <= $unsigned(redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_mem_q);
        end
    end

    // redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_rdcnt(ADD,30265)
    assign redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_a = {1'b0, redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_wraddr_q};
    assign redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_b = {1'b0, redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_o <= $unsigned(redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_a) + $unsigned(redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_b);
        end
    end
    assign redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_q = redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_o[7:0];

    // redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_inputreg0(DELAY,30260)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl);
        end
    end

    // redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_wraddr(COUNTER,30263)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_wraddr_i <= $unsigned(redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_wraddr_q = redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_wraddr_i[6:0];

    // redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem(DUALMEM,30262)
    assign redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_ia = $unsigned(redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_inputreg0_q);
    assign redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_aa = redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_wraddr_q;
    assign redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_ab = redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_aa),
        .data_a(redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_ab),
        .q_b(redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_q = redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_iq[15:0];

    // redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_outputreg0(DELAY,30261)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_outputreg0_q <= $unsigned(redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_mem_q);
        end
    end

    // redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_rdcnt(ADD,31701)
    assign redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_a = {1'b0, redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_wraddr_q};
    assign redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_b = {1'b0, redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_o <= $unsigned(redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_a) + $unsigned(redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_b);
        end
    end
    assign redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_q = redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_o[7:0];

    // redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_inputreg0(DELAY,31696)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl);
        end
    end

    // redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_wraddr(COUNTER,31699)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_wraddr_i <= $unsigned(redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_wraddr_q = redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_wraddr_i[6:0];

    // redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem(DUALMEM,31698)
    assign redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_ia = $unsigned(redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_inputreg0_q);
    assign redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_aa = redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_wraddr_q;
    assign redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_ab = redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_aa),
        .data_a(redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_ab),
        .q_b(redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_q = redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_iq[15:0];

    // redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_outputreg0(DELAY,31697)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_outputreg0_q <= $unsigned(redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28019)@127 + 5
    // out q@133
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716(ADD,8605)@133
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod341_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_b = $unsigned({{5{i_shl_i_i_i_i_i_i_60_c_compstr1715_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_60_c_compstr1715_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_o[33:0];

    // rightShiftStage0_uid18689_dupName_241_i_unnamed_c_compstr0_shift_x(MUX,18688)@133
    assign rightShiftStage0_uid18689_dupName_241_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18689_dupName_241_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_q or rightShiftStage0Idx1_uid18687_dupName_241_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18689_dupName_241_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18689_dupName_241_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_q;
            1'b1 : rightShiftStage0_uid18689_dupName_241_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18687_dupName_241_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18689_dupName_241_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18694_dupName_241_i_unnamed_c_compstr0_shift_x(MUX,18693)@133
    assign rightShiftStage1_uid18694_dupName_241_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18694_dupName_241_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18689_dupName_241_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18692_dupName_241_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18694_dupName_241_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18694_dupName_241_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18689_dupName_241_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18694_dupName_241_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18692_dupName_241_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18694_dupName_241_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18699_dupName_241_i_unnamed_c_compstr0_shift_x(MUX,18698)@133
    assign rightShiftStage2_uid18699_dupName_241_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18699_dupName_241_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18694_dupName_241_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18697_dupName_241_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18699_dupName_241_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18699_dupName_241_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18694_dupName_241_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18699_dupName_241_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18697_dupName_241_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18699_dupName_241_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1717_vt_select_20(BITSELECT,10421)@133
    assign i_unnamed_c_compstr1717_vt_select_20_b = rightShiftStage2_uid18699_dupName_241_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1717_vt_join(BITJOIN,10420)@133
    assign i_unnamed_c_compstr1717_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1717_vt_select_20_b};

    // i_conv_i_i_i_i_i_60_c_compstr1718_sel_x(BITSELECT,3796)@133
    assign i_conv_i_i_i_i_i_60_c_compstr1718_sel_x_b = i_unnamed_c_compstr1717_vt_join_q[15:0];

    // redist1069_i_conv_i_i_i_i_i_60_c_compstr1718_sel_x_b_1(DELAY,29297)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1069_i_conv_i_i_i_i_i_60_c_compstr1718_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_60_c_compstr1718_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18708_dupName_242_i_unnamed_c_compstr0_shift_x(BITSELECT,18707)@133
    assign rightShiftStage1Idx1Rng8_uid18708_dupName_242_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18707_dupName_242_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18710_dupName_242_i_unnamed_c_compstr0_shift_x(BITJOIN,18709)@133
    assign rightShiftStage1Idx1_uid18710_dupName_242_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18708_dupName_242_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18703_dupName_242_i_unnamed_c_compstr0_shift_x(BITSELECT,18702)@133
    assign rightShiftStage0Idx1Rng4_uid18703_dupName_242_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_q[33:4];

    // rightShiftStage0Idx1_uid18705_dupName_242_i_unnamed_c_compstr0_shift_x(BITJOIN,18704)@133
    assign rightShiftStage0Idx1_uid18705_dupName_242_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18703_dupName_242_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18707_dupName_242_i_unnamed_c_compstr0_shift_x(MUX,18706)@133
    assign rightShiftStage0_uid18707_dupName_242_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18707_dupName_242_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_q or rightShiftStage0Idx1_uid18705_dupName_242_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18707_dupName_242_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18707_dupName_242_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compstr1716_q;
            1'b1 : rightShiftStage0_uid18707_dupName_242_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18705_dupName_242_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18707_dupName_242_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18712_dupName_242_i_unnamed_c_compstr0_shift_x(MUX,18711)@133
    assign rightShiftStage1_uid18712_dupName_242_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18712_dupName_242_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18707_dupName_242_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18710_dupName_242_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18712_dupName_242_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18712_dupName_242_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18707_dupName_242_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18712_dupName_242_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18710_dupName_242_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18712_dupName_242_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1719_vt_select_21(BITSELECT,10424)@133
    assign i_unnamed_c_compstr1719_vt_select_21_b = rightShiftStage1_uid18712_dupName_242_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1719_vt_join(BITJOIN,10423)@133
    assign i_unnamed_c_compstr1719_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1719_vt_select_21_b};

    // i_unnamed_c_compstr1720_sel_x(BITSELECT,6091)@133
    assign i_unnamed_c_compstr1720_sel_x_b = i_unnamed_c_compstr1719_vt_join_q[15:0];

    // i_unnamed_c_compstr1721_BitSelect_for_a(BITSELECT,27571)@133
    assign i_unnamed_c_compstr1721_BitSelect_for_a_b = i_unnamed_c_compstr1720_sel_x_b[0:0];

    // i_unnamed_c_compstr1721_join(BITJOIN,27572)@133
    assign i_unnamed_c_compstr1721_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1721_BitSelect_for_a_b};

    // i_unnamed_c_compstr1721_vt_select_0(BITSELECT,10429)@133
    assign i_unnamed_c_compstr1721_vt_select_0_b = i_unnamed_c_compstr1721_join_q[0:0];

    // redist199_i_unnamed_c_compstr1721_vt_select_0_b_1(DELAY,28427)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist199_i_unnamed_c_compstr1721_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1721_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1721_vt_join(BITJOIN,10428)@134
    assign i_unnamed_c_compstr1721_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist199_i_unnamed_c_compstr1721_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_60_c_compstr1722(ADD,7063)@134
    assign i_add_i_i_i_i_i_i_60_c_compstr1722_a = {1'b0, i_unnamed_c_compstr1721_vt_join_q};
    assign i_add_i_i_i_i_i_i_60_c_compstr1722_b = {1'b0, redist1069_i_conv_i_i_i_i_i_60_c_compstr1718_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_60_c_compstr1722_o = $unsigned(i_add_i_i_i_i_i_i_60_c_compstr1722_a) + $unsigned(i_add_i_i_i_i_i_i_60_c_compstr1722_b);
    assign i_add_i_i_i_i_i_i_60_c_compstr1722_q = i_add_i_i_i_i_i_i_60_c_compstr1722_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_60_c_compstr1722_sel_x(BITSELECT,2257)@134
    assign bgTrunc_i_add_i_i_i_i_i_i_60_c_compstr1722_sel_x_b = i_add_i_i_i_i_i_i_60_c_compstr1722_q[15:0];

    // i_conv_i_i_i_i_i_i279_61_c_compstr1742_sel_x(BITSELECT,3925)@134
    assign i_conv_i_i_i_i_i_i279_61_c_compstr1742_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_60_c_compstr1722_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_61_c_compstr1742_vt_select_15(BITSELECT,8217)@134
    assign i_conv_i_i_i_i_i_i279_61_c_compstr1742_vt_select_15_b = i_conv_i_i_i_i_i_i279_61_c_compstr1742_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_61_c_compstr1742_vt_join(BITJOIN,8216)@134
    assign i_conv_i_i_i_i_i_i279_61_c_compstr1742_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_61_c_compstr1742_vt_select_15_b};

    // leftShiftStage0_uid26672_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x(MUX,26671)@134
    assign leftShiftStage0_uid26672_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26672_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_61_c_compstr1742_vt_join_q or leftShiftStage0Idx1_uid26670_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26672_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26672_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_61_c_compstr1742_vt_join_q;
            1'b1 : leftShiftStage0_uid26672_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26670_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26672_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26677_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x(MUX,26676)@134
    assign leftShiftStage1_uid26677_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26677_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_s or leftShiftStage0_uid26672_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26675_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26677_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26677_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q = leftShiftStage0_uid26672_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26677_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26675_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26677_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26682_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x(MUX,26681)@134
    assign leftShiftStage2_uid26682_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26682_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_s or leftShiftStage1_uid26677_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26680_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26682_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26682_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q = leftShiftStage1_uid26677_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26682_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26680_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26682_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_61_c_compstr1743_vt_select_28(BITSELECT,9676)@134
    assign i_shl_i_i_i_i_i_i_61_c_compstr1743_vt_select_28_b = leftShiftStage2_uid26682_i_shl_i_i_i_i_i_i_61_c_compstr0_shift_x_q[28:13];

    // redist298_i_shl_i_i_i_i_i_i_61_c_compstr1743_vt_select_28_b_1(DELAY,28526)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist298_i_shl_i_i_i_i_i_i_61_c_compstr1743_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_61_c_compstr1743_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_61_c_compstr1743_vt_join(BITJOIN,9675)@135
    assign i_shl_i_i_i_i_i_i_61_c_compstr1743_vt_join_q = {redist298_i_shl_i_i_i_i_i_i_61_c_compstr1743_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_offset(CONSTANT,30270)
    assign redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_offset_q = $unsigned(7'b0001100);

    // redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_rdcnt(ADD,31719)
    assign redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_a = {1'b0, redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_wraddr_q};
    assign redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_b = {1'b0, redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_o <= $unsigned(redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_a) + $unsigned(redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_b);
        end
    end
    assign redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_q = redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_o[7:0];

    // redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_inputreg0(DELAY,31714)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl);
        end
    end

    // redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_wraddr(COUNTER,31717)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_wraddr_i <= $unsigned(redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_wraddr_q = redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_wraddr_i[6:0];

    // redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem(DUALMEM,31716)
    assign redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_ia = $unsigned(redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_inputreg0_q);
    assign redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_aa = redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_wraddr_q;
    assign redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_ab = redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_aa),
        .data_a(redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_ab),
        .q_b(redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_q = redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_iq[15:0];

    // redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_outputreg0(DELAY,31715)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_outputreg0_q <= $unsigned(redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_mem_q);
        end
    end

    // redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_rdcnt(ADD,30271)
    assign redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_a = {1'b0, redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_wraddr_q};
    assign redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_b = {1'b0, redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_o <= $unsigned(redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_a) + $unsigned(redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_b);
        end
    end
    assign redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_q = redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_o[7:0];

    // redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_inputreg0(DELAY,30266)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl);
        end
    end

    // redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_wraddr(COUNTER,30269)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_wraddr_i <= $unsigned(redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_wraddr_q = redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_wraddr_i[6:0];

    // redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem(DUALMEM,30268)
    assign redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_ia = $unsigned(redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_inputreg0_q);
    assign redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_aa = redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_wraddr_q;
    assign redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_ab = redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_aa),
        .data_a(redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_ab),
        .q_b(redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_q = redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_iq[15:0];

    // redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_outputreg0(DELAY,30267)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_outputreg0_q <= $unsigned(redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_mem_q);
        end
    end

    // redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_rdcnt(ADD,30277)
    assign redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_a = {1'b0, redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_wraddr_q};
    assign redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_b = {1'b0, redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_o <= $unsigned(redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_a) + $unsigned(redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_b);
        end
    end
    assign redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_q = redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_o[7:0];

    // redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_inputreg0(DELAY,30272)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl);
        end
    end

    // redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_wraddr(COUNTER,30275)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_wraddr_i <= $unsigned(redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_wraddr_q = redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_wraddr_i[6:0];

    // redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem(DUALMEM,30274)
    assign redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_ia = $unsigned(redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_inputreg0_q);
    assign redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_aa = redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_wraddr_q;
    assign redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_ab = redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_aa),
        .data_a(redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_ab),
        .q_b(redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_q = redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_iq[15:0];

    // redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_outputreg0(DELAY,30273)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_outputreg0_q <= $unsigned(redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_mem_q);
        end
    end

    // redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_rdcnt(ADD,31713)
    assign redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_a = {1'b0, redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_wraddr_q};
    assign redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_b = {1'b0, redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_o <= $unsigned(redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_a) + $unsigned(redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_b);
        end
    end
    assign redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_q = redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_o[7:0];

    // redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_inputreg0(DELAY,31708)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl);
        end
    end

    // redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_wraddr(COUNTER,31711)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_wraddr_i <= $unsigned(redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_wraddr_q = redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_wraddr_i[6:0];

    // redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem(DUALMEM,31710)
    assign redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_ia = $unsigned(redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_inputreg0_q);
    assign redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_aa = redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_wraddr_q;
    assign redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_ab = redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_aa),
        .data_a(redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_ab),
        .q_b(redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_q = redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_iq[15:0];

    // redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_outputreg0(DELAY,31709)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_outputreg0_q <= $unsigned(redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28020)@129 + 5
    // out q@135
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744(ADD,8606)@135
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod346_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_b = $unsigned({{5{i_shl_i_i_i_i_i_i_61_c_compstr1743_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_61_c_compstr1743_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_o[33:0];

    // rightShiftStage0_uid18751_dupName_245_i_unnamed_c_compstr0_shift_x(MUX,18750)@135
    assign rightShiftStage0_uid18751_dupName_245_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18751_dupName_245_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_q or rightShiftStage0Idx1_uid18749_dupName_245_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18751_dupName_245_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18751_dupName_245_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_q;
            1'b1 : rightShiftStage0_uid18751_dupName_245_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18749_dupName_245_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18751_dupName_245_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18756_dupName_245_i_unnamed_c_compstr0_shift_x(MUX,18755)@135
    assign rightShiftStage1_uid18756_dupName_245_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18756_dupName_245_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18751_dupName_245_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18754_dupName_245_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18756_dupName_245_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18756_dupName_245_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18751_dupName_245_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18756_dupName_245_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18754_dupName_245_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18756_dupName_245_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18761_dupName_245_i_unnamed_c_compstr0_shift_x(MUX,18760)@135
    assign rightShiftStage2_uid18761_dupName_245_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18761_dupName_245_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18756_dupName_245_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18759_dupName_245_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18761_dupName_245_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18761_dupName_245_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18756_dupName_245_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18761_dupName_245_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18759_dupName_245_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18761_dupName_245_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1745_vt_select_20(BITSELECT,10443)@135
    assign i_unnamed_c_compstr1745_vt_select_20_b = rightShiftStage2_uid18761_dupName_245_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1745_vt_join(BITJOIN,10442)@135
    assign i_unnamed_c_compstr1745_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1745_vt_select_20_b};

    // i_conv_i_i_i_i_i_61_c_compstr1746_sel_x(BITSELECT,3797)@135
    assign i_conv_i_i_i_i_i_61_c_compstr1746_sel_x_b = i_unnamed_c_compstr1745_vt_join_q[15:0];

    // redist1068_i_conv_i_i_i_i_i_61_c_compstr1746_sel_x_b_1(DELAY,29296)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1068_i_conv_i_i_i_i_i_61_c_compstr1746_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_61_c_compstr1746_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18770_dupName_246_i_unnamed_c_compstr0_shift_x(BITSELECT,18769)@135
    assign rightShiftStage1Idx1Rng8_uid18770_dupName_246_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18769_dupName_246_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18772_dupName_246_i_unnamed_c_compstr0_shift_x(BITJOIN,18771)@135
    assign rightShiftStage1Idx1_uid18772_dupName_246_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18770_dupName_246_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18765_dupName_246_i_unnamed_c_compstr0_shift_x(BITSELECT,18764)@135
    assign rightShiftStage0Idx1Rng4_uid18765_dupName_246_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_q[33:4];

    // rightShiftStage0Idx1_uid18767_dupName_246_i_unnamed_c_compstr0_shift_x(BITJOIN,18766)@135
    assign rightShiftStage0Idx1_uid18767_dupName_246_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18765_dupName_246_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18769_dupName_246_i_unnamed_c_compstr0_shift_x(MUX,18768)@135
    assign rightShiftStage0_uid18769_dupName_246_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18769_dupName_246_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_q or rightShiftStage0Idx1_uid18767_dupName_246_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18769_dupName_246_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18769_dupName_246_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compstr1744_q;
            1'b1 : rightShiftStage0_uid18769_dupName_246_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18767_dupName_246_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18769_dupName_246_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18774_dupName_246_i_unnamed_c_compstr0_shift_x(MUX,18773)@135
    assign rightShiftStage1_uid18774_dupName_246_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18774_dupName_246_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18769_dupName_246_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18772_dupName_246_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18774_dupName_246_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18774_dupName_246_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18769_dupName_246_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18774_dupName_246_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18772_dupName_246_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18774_dupName_246_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1747_vt_select_21(BITSELECT,10446)@135
    assign i_unnamed_c_compstr1747_vt_select_21_b = rightShiftStage1_uid18774_dupName_246_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1747_vt_join(BITJOIN,10445)@135
    assign i_unnamed_c_compstr1747_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1747_vt_select_21_b};

    // i_unnamed_c_compstr1748_sel_x(BITSELECT,6093)@135
    assign i_unnamed_c_compstr1748_sel_x_b = i_unnamed_c_compstr1747_vt_join_q[15:0];

    // i_unnamed_c_compstr1749_BitSelect_for_a(BITSELECT,27575)@135
    assign i_unnamed_c_compstr1749_BitSelect_for_a_b = i_unnamed_c_compstr1748_sel_x_b[0:0];

    // i_unnamed_c_compstr1749_join(BITJOIN,27576)@135
    assign i_unnamed_c_compstr1749_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1749_BitSelect_for_a_b};

    // i_unnamed_c_compstr1749_vt_select_0(BITSELECT,10451)@135
    assign i_unnamed_c_compstr1749_vt_select_0_b = i_unnamed_c_compstr1749_join_q[0:0];

    // redist197_i_unnamed_c_compstr1749_vt_select_0_b_1(DELAY,28425)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist197_i_unnamed_c_compstr1749_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1749_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1749_vt_join(BITJOIN,10450)@136
    assign i_unnamed_c_compstr1749_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist197_i_unnamed_c_compstr1749_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_61_c_compstr1750(ADD,7064)@136
    assign i_add_i_i_i_i_i_i_61_c_compstr1750_a = {1'b0, i_unnamed_c_compstr1749_vt_join_q};
    assign i_add_i_i_i_i_i_i_61_c_compstr1750_b = {1'b0, redist1068_i_conv_i_i_i_i_i_61_c_compstr1746_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_61_c_compstr1750_o = $unsigned(i_add_i_i_i_i_i_i_61_c_compstr1750_a) + $unsigned(i_add_i_i_i_i_i_i_61_c_compstr1750_b);
    assign i_add_i_i_i_i_i_i_61_c_compstr1750_q = i_add_i_i_i_i_i_i_61_c_compstr1750_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_61_c_compstr1750_sel_x(BITSELECT,2258)@136
    assign bgTrunc_i_add_i_i_i_i_i_i_61_c_compstr1750_sel_x_b = i_add_i_i_i_i_i_i_61_c_compstr1750_q[15:0];

    // i_conv_i_i_i_i_i_i279_62_c_compstr1770_sel_x(BITSELECT,3926)@136
    assign i_conv_i_i_i_i_i_i279_62_c_compstr1770_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_61_c_compstr1750_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_62_c_compstr1770_vt_select_15(BITSELECT,8221)@136
    assign i_conv_i_i_i_i_i_i279_62_c_compstr1770_vt_select_15_b = i_conv_i_i_i_i_i_i279_62_c_compstr1770_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_62_c_compstr1770_vt_join(BITJOIN,8220)@136
    assign i_conv_i_i_i_i_i_i279_62_c_compstr1770_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_62_c_compstr1770_vt_select_15_b};

    // leftShiftStage0_uid26690_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x(MUX,26689)@136
    assign leftShiftStage0_uid26690_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26690_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_62_c_compstr1770_vt_join_q or leftShiftStage0Idx1_uid26688_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26690_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26690_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_62_c_compstr1770_vt_join_q;
            1'b1 : leftShiftStage0_uid26690_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26688_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26690_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26695_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x(MUX,26694)@136
    assign leftShiftStage1_uid26695_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26695_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_s or leftShiftStage0_uid26690_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26693_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26695_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26695_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q = leftShiftStage0_uid26690_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26695_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26693_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26695_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26700_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x(MUX,26699)@136
    assign leftShiftStage2_uid26700_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26700_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_s or leftShiftStage1_uid26695_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26698_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26700_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26700_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q = leftShiftStage1_uid26695_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26700_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26698_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26700_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_62_c_compstr1771_vt_select_28(BITSELECT,9679)@136
    assign i_shl_i_i_i_i_i_i_62_c_compstr1771_vt_select_28_b = leftShiftStage2_uid26700_i_shl_i_i_i_i_i_i_62_c_compstr0_shift_x_q[28:13];

    // redist297_i_shl_i_i_i_i_i_i_62_c_compstr1771_vt_select_28_b_1(DELAY,28525)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist297_i_shl_i_i_i_i_i_i_62_c_compstr1771_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_62_c_compstr1771_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_62_c_compstr1771_vt_join(BITJOIN,9678)@137
    assign i_shl_i_i_i_i_i_i_62_c_compstr1771_vt_join_q = {redist297_i_shl_i_i_i_i_i_i_62_c_compstr1771_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_offset(CONSTANT,30282)
    assign redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_offset_q = $unsigned(7'b0001010);

    // redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_rdcnt(ADD,31731)
    assign redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_a = {1'b0, redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_wraddr_q};
    assign redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_b = {1'b0, redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_o <= $unsigned(redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_a) + $unsigned(redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_b);
        end
    end
    assign redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_q = redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_o[7:0];

    // redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_inputreg0(DELAY,31726)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl);
        end
    end

    // redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_wraddr(COUNTER,31729)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_wraddr_i <= $unsigned(redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_wraddr_q = redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_wraddr_i[6:0];

    // redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem(DUALMEM,31728)
    assign redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_ia = $unsigned(redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_inputreg0_q);
    assign redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_aa = redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_wraddr_q;
    assign redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_ab = redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_aa),
        .data_a(redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_ab),
        .q_b(redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_q = redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_iq[15:0];

    // redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_outputreg0(DELAY,31727)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_outputreg0_q <= $unsigned(redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_mem_q);
        end
    end

    // redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_rdcnt(ADD,30283)
    assign redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_a = {1'b0, redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_wraddr_q};
    assign redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_b = {1'b0, redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_o <= $unsigned(redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_a) + $unsigned(redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_b);
        end
    end
    assign redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_q = redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_o[7:0];

    // redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_inputreg0(DELAY,30278)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl);
        end
    end

    // redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_wraddr(COUNTER,30281)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_wraddr_i <= $unsigned(redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_wraddr_q = redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_wraddr_i[6:0];

    // redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem(DUALMEM,30280)
    assign redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_ia = $unsigned(redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_inputreg0_q);
    assign redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_aa = redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_wraddr_q;
    assign redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_ab = redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_aa),
        .data_a(redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_ab),
        .q_b(redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_q = redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_iq[15:0];

    // redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_outputreg0(DELAY,30279)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_outputreg0_q <= $unsigned(redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_mem_q);
        end
    end

    // redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_rdcnt(ADD,30289)
    assign redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_a = {1'b0, redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_wraddr_q};
    assign redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_b = {1'b0, redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_o <= $unsigned(redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_a) + $unsigned(redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_b);
        end
    end
    assign redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_q = redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_o[7:0];

    // redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_inputreg0(DELAY,30284)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl);
        end
    end

    // redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_wraddr(COUNTER,30287)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_wraddr_i <= $unsigned(redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_wraddr_q = redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_wraddr_i[6:0];

    // redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem(DUALMEM,30286)
    assign redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_ia = $unsigned(redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_inputreg0_q);
    assign redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_aa = redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_wraddr_q;
    assign redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_ab = redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_aa),
        .data_a(redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_ab),
        .q_b(redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_q = redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_iq[15:0];

    // redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_outputreg0(DELAY,30285)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_outputreg0_q <= $unsigned(redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_mem_q);
        end
    end

    // redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_rdcnt(ADD,31725)
    assign redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_a = {1'b0, redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_wraddr_q};
    assign redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_b = {1'b0, redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_o <= $unsigned(redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_a) + $unsigned(redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_b);
        end
    end
    assign redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_q = redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_o[7:0];

    // redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_inputreg0(DELAY,31720)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl);
        end
    end

    // redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_wraddr(COUNTER,31723)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_wraddr_i <= $unsigned(redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_wraddr_q = redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_wraddr_i[6:0];

    // redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem(DUALMEM,31722)
    assign redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_ia = $unsigned(redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_inputreg0_q);
    assign redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_aa = redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_wraddr_q;
    assign redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_ab = redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_aa),
        .data_a(redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_ab),
        .q_b(redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_q = redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_iq[15:0];

    // redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_outputreg0(DELAY,31721)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_outputreg0_q <= $unsigned(redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28021)@131 + 5
    // out q@137
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772(ADD,8607)@137
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod351_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_b = $unsigned({{5{i_shl_i_i_i_i_i_i_62_c_compstr1771_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_62_c_compstr1771_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_o[33:0];

    // rightShiftStage0_uid18813_dupName_249_i_unnamed_c_compstr0_shift_x(MUX,18812)@137
    assign rightShiftStage0_uid18813_dupName_249_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18813_dupName_249_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_q or rightShiftStage0Idx1_uid18811_dupName_249_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18813_dupName_249_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18813_dupName_249_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_q;
            1'b1 : rightShiftStage0_uid18813_dupName_249_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18811_dupName_249_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18813_dupName_249_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18818_dupName_249_i_unnamed_c_compstr0_shift_x(MUX,18817)@137
    assign rightShiftStage1_uid18818_dupName_249_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18818_dupName_249_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18813_dupName_249_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18816_dupName_249_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18818_dupName_249_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18818_dupName_249_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18813_dupName_249_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18818_dupName_249_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18816_dupName_249_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18818_dupName_249_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18823_dupName_249_i_unnamed_c_compstr0_shift_x(MUX,18822)@137
    assign rightShiftStage2_uid18823_dupName_249_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18823_dupName_249_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18818_dupName_249_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18821_dupName_249_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18823_dupName_249_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18823_dupName_249_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18818_dupName_249_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18823_dupName_249_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18821_dupName_249_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18823_dupName_249_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1773_vt_select_20(BITSELECT,10465)@137
    assign i_unnamed_c_compstr1773_vt_select_20_b = rightShiftStage2_uid18823_dupName_249_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1773_vt_join(BITJOIN,10464)@137
    assign i_unnamed_c_compstr1773_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1773_vt_select_20_b};

    // i_conv_i_i_i_i_i_62_c_compstr1774_sel_x(BITSELECT,3798)@137
    assign i_conv_i_i_i_i_i_62_c_compstr1774_sel_x_b = i_unnamed_c_compstr1773_vt_join_q[15:0];

    // redist1067_i_conv_i_i_i_i_i_62_c_compstr1774_sel_x_b_1(DELAY,29295)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1067_i_conv_i_i_i_i_i_62_c_compstr1774_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_62_c_compstr1774_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18832_dupName_250_i_unnamed_c_compstr0_shift_x(BITSELECT,18831)@137
    assign rightShiftStage1Idx1Rng8_uid18832_dupName_250_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18831_dupName_250_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18834_dupName_250_i_unnamed_c_compstr0_shift_x(BITJOIN,18833)@137
    assign rightShiftStage1Idx1_uid18834_dupName_250_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18832_dupName_250_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18827_dupName_250_i_unnamed_c_compstr0_shift_x(BITSELECT,18826)@137
    assign rightShiftStage0Idx1Rng4_uid18827_dupName_250_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_q[33:4];

    // rightShiftStage0Idx1_uid18829_dupName_250_i_unnamed_c_compstr0_shift_x(BITJOIN,18828)@137
    assign rightShiftStage0Idx1_uid18829_dupName_250_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18827_dupName_250_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18831_dupName_250_i_unnamed_c_compstr0_shift_x(MUX,18830)@137
    assign rightShiftStage0_uid18831_dupName_250_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18831_dupName_250_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_q or rightShiftStage0Idx1_uid18829_dupName_250_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18831_dupName_250_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18831_dupName_250_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compstr1772_q;
            1'b1 : rightShiftStage0_uid18831_dupName_250_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18829_dupName_250_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18831_dupName_250_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18836_dupName_250_i_unnamed_c_compstr0_shift_x(MUX,18835)@137
    assign rightShiftStage1_uid18836_dupName_250_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18836_dupName_250_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18831_dupName_250_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18834_dupName_250_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18836_dupName_250_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18836_dupName_250_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18831_dupName_250_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18836_dupName_250_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18834_dupName_250_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18836_dupName_250_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1775_vt_select_21(BITSELECT,10468)@137
    assign i_unnamed_c_compstr1775_vt_select_21_b = rightShiftStage1_uid18836_dupName_250_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1775_vt_join(BITJOIN,10467)@137
    assign i_unnamed_c_compstr1775_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1775_vt_select_21_b};

    // i_unnamed_c_compstr1776_sel_x(BITSELECT,6095)@137
    assign i_unnamed_c_compstr1776_sel_x_b = i_unnamed_c_compstr1775_vt_join_q[15:0];

    // i_unnamed_c_compstr1777_BitSelect_for_a(BITSELECT,27579)@137
    assign i_unnamed_c_compstr1777_BitSelect_for_a_b = i_unnamed_c_compstr1776_sel_x_b[0:0];

    // i_unnamed_c_compstr1777_join(BITJOIN,27580)@137
    assign i_unnamed_c_compstr1777_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1777_BitSelect_for_a_b};

    // i_unnamed_c_compstr1777_vt_select_0(BITSELECT,10473)@137
    assign i_unnamed_c_compstr1777_vt_select_0_b = i_unnamed_c_compstr1777_join_q[0:0];

    // redist195_i_unnamed_c_compstr1777_vt_select_0_b_1(DELAY,28423)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist195_i_unnamed_c_compstr1777_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1777_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1777_vt_join(BITJOIN,10472)@138
    assign i_unnamed_c_compstr1777_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist195_i_unnamed_c_compstr1777_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_62_c_compstr1778(ADD,7065)@138
    assign i_add_i_i_i_i_i_i_62_c_compstr1778_a = {1'b0, i_unnamed_c_compstr1777_vt_join_q};
    assign i_add_i_i_i_i_i_i_62_c_compstr1778_b = {1'b0, redist1067_i_conv_i_i_i_i_i_62_c_compstr1774_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_62_c_compstr1778_o = $unsigned(i_add_i_i_i_i_i_i_62_c_compstr1778_a) + $unsigned(i_add_i_i_i_i_i_i_62_c_compstr1778_b);
    assign i_add_i_i_i_i_i_i_62_c_compstr1778_q = i_add_i_i_i_i_i_i_62_c_compstr1778_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_62_c_compstr1778_sel_x(BITSELECT,2259)@138
    assign bgTrunc_i_add_i_i_i_i_i_i_62_c_compstr1778_sel_x_b = i_add_i_i_i_i_i_i_62_c_compstr1778_q[15:0];

    // i_conv_i_i_i_i_i_i279_63_c_compstr1798_sel_x(BITSELECT,3927)@138
    assign i_conv_i_i_i_i_i_i279_63_c_compstr1798_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_62_c_compstr1778_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_63_c_compstr1798_vt_select_15(BITSELECT,8225)@138
    assign i_conv_i_i_i_i_i_i279_63_c_compstr1798_vt_select_15_b = i_conv_i_i_i_i_i_i279_63_c_compstr1798_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_63_c_compstr1798_vt_join(BITJOIN,8224)@138
    assign i_conv_i_i_i_i_i_i279_63_c_compstr1798_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_63_c_compstr1798_vt_select_15_b};

    // leftShiftStage0_uid26708_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x(MUX,26707)@138
    assign leftShiftStage0_uid26708_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26708_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_63_c_compstr1798_vt_join_q or leftShiftStage0Idx1_uid26706_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26708_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26708_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_63_c_compstr1798_vt_join_q;
            1'b1 : leftShiftStage0_uid26708_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26706_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26708_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26713_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x(MUX,26712)@138
    assign leftShiftStage1_uid26713_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26713_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_s or leftShiftStage0_uid26708_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26711_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26713_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26713_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q = leftShiftStage0_uid26708_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26713_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26711_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26713_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26718_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x(MUX,26717)@138
    assign leftShiftStage2_uid26718_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26718_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_s or leftShiftStage1_uid26713_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26716_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26718_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26718_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q = leftShiftStage1_uid26713_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26718_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26716_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26718_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_63_c_compstr1799_vt_select_28(BITSELECT,9682)@138
    assign i_shl_i_i_i_i_i_i_63_c_compstr1799_vt_select_28_b = leftShiftStage2_uid26718_i_shl_i_i_i_i_i_i_63_c_compstr0_shift_x_q[28:13];

    // redist296_i_shl_i_i_i_i_i_i_63_c_compstr1799_vt_select_28_b_1(DELAY,28524)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist296_i_shl_i_i_i_i_i_i_63_c_compstr1799_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_63_c_compstr1799_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_63_c_compstr1799_vt_join(BITJOIN,9681)@139
    assign i_shl_i_i_i_i_i_i_63_c_compstr1799_vt_join_q = {redist296_i_shl_i_i_i_i_i_i_63_c_compstr1799_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_offset(CONSTANT,30294)
    assign redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_offset_q = $unsigned(7'b0001000);

    // redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_rdcnt(ADD,31743)
    assign redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_a = {1'b0, redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_wraddr_q};
    assign redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_b = {1'b0, redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_o <= $unsigned(redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_a) + $unsigned(redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_b);
        end
    end
    assign redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_q = redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_o[7:0];

    // redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_inputreg0(DELAY,31738)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl);
        end
    end

    // redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_wraddr(COUNTER,31741)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_wraddr_i <= $unsigned(redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_wraddr_q = redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_wraddr_i[6:0];

    // redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem(DUALMEM,31740)
    assign redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_ia = $unsigned(redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_inputreg0_q);
    assign redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_aa = redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_wraddr_q;
    assign redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_ab = redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_aa),
        .data_a(redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_ab),
        .q_b(redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_q = redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_iq[15:0];

    // redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_outputreg0(DELAY,31739)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_outputreg0_q <= $unsigned(redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_mem_q);
        end
    end

    // redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_rdcnt(ADD,30295)
    assign redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_a = {1'b0, redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_wraddr_q};
    assign redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_b = {1'b0, redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_o <= $unsigned(redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_a) + $unsigned(redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_b);
        end
    end
    assign redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_q = redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_o[7:0];

    // redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_inputreg0(DELAY,30290)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl);
        end
    end

    // redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_wraddr(COUNTER,30293)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_wraddr_i <= $unsigned(redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_wraddr_q = redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_wraddr_i[6:0];

    // redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem(DUALMEM,30292)
    assign redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_ia = $unsigned(redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_inputreg0_q);
    assign redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_aa = redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_wraddr_q;
    assign redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_ab = redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_aa),
        .data_a(redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_ab),
        .q_b(redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_q = redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_iq[15:0];

    // redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_outputreg0(DELAY,30291)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_outputreg0_q <= $unsigned(redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_mem_q);
        end
    end

    // redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_rdcnt(ADD,30301)
    assign redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_a = {1'b0, redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_wraddr_q};
    assign redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_b = {1'b0, redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_o <= $unsigned(redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_a) + $unsigned(redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_b);
        end
    end
    assign redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_q = redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_o[7:0];

    // redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_inputreg0(DELAY,30296)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl);
        end
    end

    // redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_wraddr(COUNTER,30299)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_wraddr_i <= $unsigned(redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_wraddr_q = redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_wraddr_i[6:0];

    // redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem(DUALMEM,30298)
    assign redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_ia = $unsigned(redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_inputreg0_q);
    assign redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_aa = redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_wraddr_q;
    assign redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_ab = redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_aa),
        .data_a(redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_ab),
        .q_b(redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_q = redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_iq[15:0];

    // redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_outputreg0(DELAY,30297)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_outputreg0_q <= $unsigned(redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_mem_q);
        end
    end

    // redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_rdcnt(ADD,31737)
    assign redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_a = {1'b0, redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_wraddr_q};
    assign redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_b = {1'b0, redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_o <= $unsigned(redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_a) + $unsigned(redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_b);
        end
    end
    assign redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_q = redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_o[7:0];

    // redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_inputreg0(DELAY,31732)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl);
        end
    end

    // redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_wraddr(COUNTER,31735)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_wraddr_i <= $unsigned(redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_wraddr_q = redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_wraddr_i[6:0];

    // redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem(DUALMEM,31734)
    assign redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_ia = $unsigned(redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_inputreg0_q);
    assign redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_aa = redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_wraddr_q;
    assign redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_ab = redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_aa),
        .data_a(redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_ab),
        .q_b(redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_q = redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_iq[15:0];

    // redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_outputreg0(DELAY,31733)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_outputreg0_q <= $unsigned(redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28022)@133 + 5
    // out q@139
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800(ADD,8608)@139
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod356_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_b = $unsigned({{5{i_shl_i_i_i_i_i_i_63_c_compstr1799_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_63_c_compstr1799_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_o[33:0];

    // rightShiftStage0_uid18875_dupName_253_i_unnamed_c_compstr0_shift_x(MUX,18874)@139
    assign rightShiftStage0_uid18875_dupName_253_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18875_dupName_253_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_q or rightShiftStage0Idx1_uid18873_dupName_253_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18875_dupName_253_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18875_dupName_253_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_q;
            1'b1 : rightShiftStage0_uid18875_dupName_253_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18873_dupName_253_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18875_dupName_253_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18880_dupName_253_i_unnamed_c_compstr0_shift_x(MUX,18879)@139
    assign rightShiftStage1_uid18880_dupName_253_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18880_dupName_253_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18875_dupName_253_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18878_dupName_253_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18880_dupName_253_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18880_dupName_253_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18875_dupName_253_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18880_dupName_253_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18878_dupName_253_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18880_dupName_253_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18885_dupName_253_i_unnamed_c_compstr0_shift_x(MUX,18884)@139
    assign rightShiftStage2_uid18885_dupName_253_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18885_dupName_253_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18880_dupName_253_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18883_dupName_253_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18885_dupName_253_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18885_dupName_253_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18880_dupName_253_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18885_dupName_253_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18883_dupName_253_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18885_dupName_253_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1801_vt_select_20(BITSELECT,10493)@139
    assign i_unnamed_c_compstr1801_vt_select_20_b = rightShiftStage2_uid18885_dupName_253_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1801_vt_join(BITJOIN,10492)@139
    assign i_unnamed_c_compstr1801_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1801_vt_select_20_b};

    // i_conv_i_i_i_i_i_63_c_compstr1802_sel_x(BITSELECT,3799)@139
    assign i_conv_i_i_i_i_i_63_c_compstr1802_sel_x_b = i_unnamed_c_compstr1801_vt_join_q[15:0];

    // redist1066_i_conv_i_i_i_i_i_63_c_compstr1802_sel_x_b_1(DELAY,29294)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1066_i_conv_i_i_i_i_i_63_c_compstr1802_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_63_c_compstr1802_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18894_dupName_254_i_unnamed_c_compstr0_shift_x(BITSELECT,18893)@139
    assign rightShiftStage1Idx1Rng8_uid18894_dupName_254_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18893_dupName_254_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18896_dupName_254_i_unnamed_c_compstr0_shift_x(BITJOIN,18895)@139
    assign rightShiftStage1Idx1_uid18896_dupName_254_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18894_dupName_254_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18889_dupName_254_i_unnamed_c_compstr0_shift_x(BITSELECT,18888)@139
    assign rightShiftStage0Idx1Rng4_uid18889_dupName_254_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_q[33:4];

    // rightShiftStage0Idx1_uid18891_dupName_254_i_unnamed_c_compstr0_shift_x(BITJOIN,18890)@139
    assign rightShiftStage0Idx1_uid18891_dupName_254_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18889_dupName_254_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18893_dupName_254_i_unnamed_c_compstr0_shift_x(MUX,18892)@139
    assign rightShiftStage0_uid18893_dupName_254_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18893_dupName_254_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_q or rightShiftStage0Idx1_uid18891_dupName_254_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18893_dupName_254_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18893_dupName_254_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compstr1800_q;
            1'b1 : rightShiftStage0_uid18893_dupName_254_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18891_dupName_254_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18893_dupName_254_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18898_dupName_254_i_unnamed_c_compstr0_shift_x(MUX,18897)@139
    assign rightShiftStage1_uid18898_dupName_254_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18898_dupName_254_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18893_dupName_254_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18896_dupName_254_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18898_dupName_254_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18898_dupName_254_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18893_dupName_254_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18898_dupName_254_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18896_dupName_254_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18898_dupName_254_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1803_vt_select_21(BITSELECT,10496)@139
    assign i_unnamed_c_compstr1803_vt_select_21_b = rightShiftStage1_uid18898_dupName_254_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1803_vt_join(BITJOIN,10495)@139
    assign i_unnamed_c_compstr1803_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1803_vt_select_21_b};

    // i_unnamed_c_compstr1804_sel_x(BITSELECT,6098)@139
    assign i_unnamed_c_compstr1804_sel_x_b = i_unnamed_c_compstr1803_vt_join_q[15:0];

    // i_unnamed_c_compstr1805_BitSelect_for_a(BITSELECT,27583)@139
    assign i_unnamed_c_compstr1805_BitSelect_for_a_b = i_unnamed_c_compstr1804_sel_x_b[0:0];

    // i_unnamed_c_compstr1805_join(BITJOIN,27584)@139
    assign i_unnamed_c_compstr1805_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1805_BitSelect_for_a_b};

    // i_unnamed_c_compstr1805_vt_select_0(BITSELECT,10501)@139
    assign i_unnamed_c_compstr1805_vt_select_0_b = i_unnamed_c_compstr1805_join_q[0:0];

    // redist193_i_unnamed_c_compstr1805_vt_select_0_b_1(DELAY,28421)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist193_i_unnamed_c_compstr1805_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1805_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1805_vt_join(BITJOIN,10500)@140
    assign i_unnamed_c_compstr1805_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist193_i_unnamed_c_compstr1805_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_63_c_compstr1806(ADD,7066)@140
    assign i_add_i_i_i_i_i_i_63_c_compstr1806_a = {1'b0, i_unnamed_c_compstr1805_vt_join_q};
    assign i_add_i_i_i_i_i_i_63_c_compstr1806_b = {1'b0, redist1066_i_conv_i_i_i_i_i_63_c_compstr1802_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_63_c_compstr1806_o = $unsigned(i_add_i_i_i_i_i_i_63_c_compstr1806_a) + $unsigned(i_add_i_i_i_i_i_i_63_c_compstr1806_b);
    assign i_add_i_i_i_i_i_i_63_c_compstr1806_q = i_add_i_i_i_i_i_i_63_c_compstr1806_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_63_c_compstr1806_sel_x(BITSELECT,2260)@140
    assign bgTrunc_i_add_i_i_i_i_i_i_63_c_compstr1806_sel_x_b = i_add_i_i_i_i_i_i_63_c_compstr1806_q[15:0];

    // i_conv_i_i_i_i_i_i279_64_c_compstr1826_sel_x(BITSELECT,3928)@140
    assign i_conv_i_i_i_i_i_i279_64_c_compstr1826_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_63_c_compstr1806_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_64_c_compstr1826_vt_select_15(BITSELECT,8229)@140
    assign i_conv_i_i_i_i_i_i279_64_c_compstr1826_vt_select_15_b = i_conv_i_i_i_i_i_i279_64_c_compstr1826_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_64_c_compstr1826_vt_join(BITJOIN,8228)@140
    assign i_conv_i_i_i_i_i_i279_64_c_compstr1826_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_64_c_compstr1826_vt_select_15_b};

    // leftShiftStage0_uid26726_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x(MUX,26725)@140
    assign leftShiftStage0_uid26726_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26726_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_64_c_compstr1826_vt_join_q or leftShiftStage0Idx1_uid26724_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26726_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26726_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_64_c_compstr1826_vt_join_q;
            1'b1 : leftShiftStage0_uid26726_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26724_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26726_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26731_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x(MUX,26730)@140
    assign leftShiftStage1_uid26731_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26731_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_s or leftShiftStage0_uid26726_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26729_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26731_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26731_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q = leftShiftStage0_uid26726_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26731_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26729_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26731_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26736_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x(MUX,26735)@140
    assign leftShiftStage2_uid26736_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26736_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_s or leftShiftStage1_uid26731_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26734_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26736_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26736_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q = leftShiftStage1_uid26731_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26736_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26734_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26736_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_64_c_compstr1827_vt_select_28(BITSELECT,9685)@140
    assign i_shl_i_i_i_i_i_i_64_c_compstr1827_vt_select_28_b = leftShiftStage2_uid26736_i_shl_i_i_i_i_i_i_64_c_compstr0_shift_x_q[28:13];

    // redist295_i_shl_i_i_i_i_i_i_64_c_compstr1827_vt_select_28_b_1(DELAY,28523)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist295_i_shl_i_i_i_i_i_i_64_c_compstr1827_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_64_c_compstr1827_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_64_c_compstr1827_vt_join(BITJOIN,9684)@141
    assign i_shl_i_i_i_i_i_i_64_c_compstr1827_vt_join_q = {redist295_i_shl_i_i_i_i_i_i_64_c_compstr1827_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_offset(CONSTANT,30306)
    assign redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_offset_q = $unsigned(7'b0000110);

    // redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_rdcnt(ADD,31755)
    assign redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_a = {1'b0, redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_wraddr_q};
    assign redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_b = {1'b0, redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_o <= $unsigned(redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_a) + $unsigned(redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_b);
        end
    end
    assign redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_q = redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_o[7:0];

    // redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_inputreg0(DELAY,31750)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl);
        end
    end

    // redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_wraddr(COUNTER,31753)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_wraddr_i <= $unsigned(redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_wraddr_q = redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_wraddr_i[6:0];

    // redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem(DUALMEM,31752)
    assign redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_ia = $unsigned(redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_inputreg0_q);
    assign redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_aa = redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_wraddr_q;
    assign redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_ab = redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_aa),
        .data_a(redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_ab),
        .q_b(redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_q = redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_iq[15:0];

    // redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_outputreg0(DELAY,31751)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_outputreg0_q <= $unsigned(redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_mem_q);
        end
    end

    // redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_rdcnt(ADD,30307)
    assign redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_a = {1'b0, redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_wraddr_q};
    assign redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_b = {1'b0, redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_o <= $unsigned(redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_a) + $unsigned(redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_b);
        end
    end
    assign redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_q = redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_o[7:0];

    // redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_inputreg0(DELAY,30302)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl);
        end
    end

    // redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_wraddr(COUNTER,30305)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_wraddr_i <= $unsigned(redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_wraddr_q = redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_wraddr_i[6:0];

    // redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem(DUALMEM,30304)
    assign redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_ia = $unsigned(redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_inputreg0_q);
    assign redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_aa = redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_wraddr_q;
    assign redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_ab = redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_aa),
        .data_a(redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_ab),
        .q_b(redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_q = redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_iq[15:0];

    // redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_outputreg0(DELAY,30303)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_outputreg0_q <= $unsigned(redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_mem_q);
        end
    end

    // redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_rdcnt(ADD,30313)
    assign redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_a = {1'b0, redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_wraddr_q};
    assign redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_b = {1'b0, redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_o <= $unsigned(redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_a) + $unsigned(redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_b);
        end
    end
    assign redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_q = redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_o[7:0];

    // redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_inputreg0(DELAY,30308)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl);
        end
    end

    // redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_wraddr(COUNTER,30311)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_wraddr_i <= $unsigned(redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_wraddr_q = redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_wraddr_i[6:0];

    // redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem(DUALMEM,30310)
    assign redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_ia = $unsigned(redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_inputreg0_q);
    assign redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_aa = redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_wraddr_q;
    assign redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_ab = redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_aa),
        .data_a(redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_ab),
        .q_b(redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_q = redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_iq[15:0];

    // redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_outputreg0(DELAY,30309)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_outputreg0_q <= $unsigned(redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_mem_q);
        end
    end

    // redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_rdcnt(ADD,31749)
    assign redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_a = {1'b0, redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_wraddr_q};
    assign redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_b = {1'b0, redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_o <= $unsigned(redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_a) + $unsigned(redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_b);
        end
    end
    assign redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_q = redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_o[7:0];

    // redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_inputreg0(DELAY,31744)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl);
        end
    end

    // redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_wraddr(COUNTER,31747)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_wraddr_i <= $unsigned(redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_wraddr_q = redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_wraddr_i[6:0];

    // redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem(DUALMEM,31746)
    assign redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_ia = $unsigned(redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_inputreg0_q);
    assign redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_aa = redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_wraddr_q;
    assign redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_ab = redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_aa),
        .data_a(redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_ab),
        .q_b(redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_q = redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_iq[15:0];

    // redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_outputreg0(DELAY,31745)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_outputreg0_q <= $unsigned(redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28023)@135 + 5
    // out q@141
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828(ADD,8609)@141
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod361_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_b = $unsigned({{5{i_shl_i_i_i_i_i_i_64_c_compstr1827_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_64_c_compstr1827_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_o[33:0];

    // rightShiftStage0_uid18937_dupName_257_i_unnamed_c_compstr0_shift_x(MUX,18936)@141
    assign rightShiftStage0_uid18937_dupName_257_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18937_dupName_257_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_q or rightShiftStage0Idx1_uid18935_dupName_257_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18937_dupName_257_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18937_dupName_257_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_q;
            1'b1 : rightShiftStage0_uid18937_dupName_257_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18935_dupName_257_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18937_dupName_257_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18942_dupName_257_i_unnamed_c_compstr0_shift_x(MUX,18941)@141
    assign rightShiftStage1_uid18942_dupName_257_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18942_dupName_257_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18937_dupName_257_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18940_dupName_257_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18942_dupName_257_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18942_dupName_257_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18937_dupName_257_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18942_dupName_257_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18940_dupName_257_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18942_dupName_257_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18947_dupName_257_i_unnamed_c_compstr0_shift_x(MUX,18946)@141
    assign rightShiftStage2_uid18947_dupName_257_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18947_dupName_257_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18942_dupName_257_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18945_dupName_257_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18947_dupName_257_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18947_dupName_257_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18942_dupName_257_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18947_dupName_257_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18945_dupName_257_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18947_dupName_257_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1829_vt_select_20(BITSELECT,10520)@141
    assign i_unnamed_c_compstr1829_vt_select_20_b = rightShiftStage2_uid18947_dupName_257_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1829_vt_join(BITJOIN,10519)@141
    assign i_unnamed_c_compstr1829_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1829_vt_select_20_b};

    // i_conv_i_i_i_i_i_64_c_compstr1830_sel_x(BITSELECT,3800)@141
    assign i_conv_i_i_i_i_i_64_c_compstr1830_sel_x_b = i_unnamed_c_compstr1829_vt_join_q[15:0];

    // redist1065_i_conv_i_i_i_i_i_64_c_compstr1830_sel_x_b_1(DELAY,29293)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1065_i_conv_i_i_i_i_i_64_c_compstr1830_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_64_c_compstr1830_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18956_dupName_258_i_unnamed_c_compstr0_shift_x(BITSELECT,18955)@141
    assign rightShiftStage1Idx1Rng8_uid18956_dupName_258_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18955_dupName_258_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18958_dupName_258_i_unnamed_c_compstr0_shift_x(BITJOIN,18957)@141
    assign rightShiftStage1Idx1_uid18958_dupName_258_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18956_dupName_258_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18951_dupName_258_i_unnamed_c_compstr0_shift_x(BITSELECT,18950)@141
    assign rightShiftStage0Idx1Rng4_uid18951_dupName_258_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_q[33:4];

    // rightShiftStage0Idx1_uid18953_dupName_258_i_unnamed_c_compstr0_shift_x(BITJOIN,18952)@141
    assign rightShiftStage0Idx1_uid18953_dupName_258_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18951_dupName_258_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18955_dupName_258_i_unnamed_c_compstr0_shift_x(MUX,18954)@141
    assign rightShiftStage0_uid18955_dupName_258_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18955_dupName_258_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_q or rightShiftStage0Idx1_uid18953_dupName_258_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18955_dupName_258_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18955_dupName_258_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compstr1828_q;
            1'b1 : rightShiftStage0_uid18955_dupName_258_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18953_dupName_258_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18955_dupName_258_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18960_dupName_258_i_unnamed_c_compstr0_shift_x(MUX,18959)@141
    assign rightShiftStage1_uid18960_dupName_258_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18960_dupName_258_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18955_dupName_258_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18958_dupName_258_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18960_dupName_258_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18960_dupName_258_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18955_dupName_258_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18960_dupName_258_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18958_dupName_258_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18960_dupName_258_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1831_vt_select_21(BITSELECT,10523)@141
    assign i_unnamed_c_compstr1831_vt_select_21_b = rightShiftStage1_uid18960_dupName_258_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1831_vt_join(BITJOIN,10522)@141
    assign i_unnamed_c_compstr1831_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1831_vt_select_21_b};

    // i_unnamed_c_compstr1832_sel_x(BITSELECT,6100)@141
    assign i_unnamed_c_compstr1832_sel_x_b = i_unnamed_c_compstr1831_vt_join_q[15:0];

    // i_unnamed_c_compstr1833_BitSelect_for_a(BITSELECT,27589)@141
    assign i_unnamed_c_compstr1833_BitSelect_for_a_b = i_unnamed_c_compstr1832_sel_x_b[0:0];

    // i_unnamed_c_compstr1833_join(BITJOIN,27590)@141
    assign i_unnamed_c_compstr1833_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1833_BitSelect_for_a_b};

    // i_unnamed_c_compstr1833_vt_select_0(BITSELECT,10528)@141
    assign i_unnamed_c_compstr1833_vt_select_0_b = i_unnamed_c_compstr1833_join_q[0:0];

    // redist190_i_unnamed_c_compstr1833_vt_select_0_b_1(DELAY,28418)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist190_i_unnamed_c_compstr1833_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1833_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1833_vt_join(BITJOIN,10527)@142
    assign i_unnamed_c_compstr1833_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist190_i_unnamed_c_compstr1833_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_64_c_compstr1834(ADD,7067)@142
    assign i_add_i_i_i_i_i_i_64_c_compstr1834_a = {1'b0, i_unnamed_c_compstr1833_vt_join_q};
    assign i_add_i_i_i_i_i_i_64_c_compstr1834_b = {1'b0, redist1065_i_conv_i_i_i_i_i_64_c_compstr1830_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_64_c_compstr1834_o = $unsigned(i_add_i_i_i_i_i_i_64_c_compstr1834_a) + $unsigned(i_add_i_i_i_i_i_i_64_c_compstr1834_b);
    assign i_add_i_i_i_i_i_i_64_c_compstr1834_q = i_add_i_i_i_i_i_i_64_c_compstr1834_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_64_c_compstr1834_sel_x(BITSELECT,2261)@142
    assign bgTrunc_i_add_i_i_i_i_i_i_64_c_compstr1834_sel_x_b = i_add_i_i_i_i_i_i_64_c_compstr1834_q[15:0];

    // i_conv_i_i_i_i_i_i279_65_c_compstr1854_sel_x(BITSELECT,3929)@142
    assign i_conv_i_i_i_i_i_i279_65_c_compstr1854_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_64_c_compstr1834_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_65_c_compstr1854_vt_select_15(BITSELECT,8233)@142
    assign i_conv_i_i_i_i_i_i279_65_c_compstr1854_vt_select_15_b = i_conv_i_i_i_i_i_i279_65_c_compstr1854_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_65_c_compstr1854_vt_join(BITJOIN,8232)@142
    assign i_conv_i_i_i_i_i_i279_65_c_compstr1854_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_65_c_compstr1854_vt_select_15_b};

    // leftShiftStage0_uid26744_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x(MUX,26743)@142
    assign leftShiftStage0_uid26744_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26744_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_65_c_compstr1854_vt_join_q or leftShiftStage0Idx1_uid26742_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26744_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26744_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_65_c_compstr1854_vt_join_q;
            1'b1 : leftShiftStage0_uid26744_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26742_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26744_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26749_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x(MUX,26748)@142
    assign leftShiftStage1_uid26749_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26749_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_s or leftShiftStage0_uid26744_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26747_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26749_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26749_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q = leftShiftStage0_uid26744_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26749_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26747_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26749_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26754_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x(MUX,26753)@142
    assign leftShiftStage2_uid26754_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26754_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_s or leftShiftStage1_uid26749_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26752_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26754_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26754_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q = leftShiftStage1_uid26749_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26754_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26752_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26754_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_65_c_compstr1855_vt_select_28(BITSELECT,9688)@142
    assign i_shl_i_i_i_i_i_i_65_c_compstr1855_vt_select_28_b = leftShiftStage2_uid26754_i_shl_i_i_i_i_i_i_65_c_compstr0_shift_x_q[28:13];

    // redist294_i_shl_i_i_i_i_i_i_65_c_compstr1855_vt_select_28_b_1(DELAY,28522)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist294_i_shl_i_i_i_i_i_i_65_c_compstr1855_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_65_c_compstr1855_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_65_c_compstr1855_vt_join(BITJOIN,9687)@143
    assign i_shl_i_i_i_i_i_i_65_c_compstr1855_vt_join_q = {redist294_i_shl_i_i_i_i_i_i_65_c_compstr1855_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_offset(CONSTANT,30318)
    assign redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_offset_q = $unsigned(7'b0000100);

    // redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_rdcnt(ADD,31767)
    assign redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_a = {1'b0, redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_wraddr_q};
    assign redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_b = {1'b0, redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_o <= $unsigned(redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_a) + $unsigned(redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_b);
        end
    end
    assign redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_q = redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_o[7:0];

    // redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_inputreg0(DELAY,31762)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl);
        end
    end

    // redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_wraddr(COUNTER,31765)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_wraddr_i <= $unsigned(redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_wraddr_q = redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_wraddr_i[6:0];

    // redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem(DUALMEM,31764)
    assign redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_ia = $unsigned(redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_inputreg0_q);
    assign redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_aa = redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_wraddr_q;
    assign redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_ab = redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_aa),
        .data_a(redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_ab),
        .q_b(redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_q = redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_iq[15:0];

    // redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_outputreg0(DELAY,31763)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_outputreg0_q <= $unsigned(redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_mem_q);
        end
    end

    // redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_rdcnt(ADD,30319)
    assign redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_a = {1'b0, redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_wraddr_q};
    assign redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_b = {1'b0, redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_o <= $unsigned(redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_a) + $unsigned(redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_b);
        end
    end
    assign redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_q = redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_o[7:0];

    // redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_inputreg0(DELAY,30314)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl);
        end
    end

    // redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_wraddr(COUNTER,30317)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_wraddr_i <= $unsigned(redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_wraddr_q = redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_wraddr_i[6:0];

    // redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem(DUALMEM,30316)
    assign redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_ia = $unsigned(redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_inputreg0_q);
    assign redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_aa = redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_wraddr_q;
    assign redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_ab = redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_aa),
        .data_a(redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_ab),
        .q_b(redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_q = redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_iq[15:0];

    // redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_outputreg0(DELAY,30315)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_outputreg0_q <= $unsigned(redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_mem_q);
        end
    end

    // redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_rdcnt(ADD,30325)
    assign redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_a = {1'b0, redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_wraddr_q};
    assign redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_b = {1'b0, redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_o <= $unsigned(redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_a) + $unsigned(redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_b);
        end
    end
    assign redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_q = redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_o[7:0];

    // redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_inputreg0(DELAY,30320)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl);
        end
    end

    // redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_wraddr(COUNTER,30323)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_wraddr_i <= $unsigned(redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_wraddr_q = redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_wraddr_i[6:0];

    // redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem(DUALMEM,30322)
    assign redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_ia = $unsigned(redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_inputreg0_q);
    assign redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_aa = redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_wraddr_q;
    assign redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_ab = redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_aa),
        .data_a(redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_ab),
        .q_b(redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_q = redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_iq[15:0];

    // redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_outputreg0(DELAY,30321)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_outputreg0_q <= $unsigned(redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_mem_q);
        end
    end

    // redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_rdcnt(ADD,31761)
    assign redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_a = {1'b0, redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_wraddr_q};
    assign redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_b = {1'b0, redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_o <= $unsigned(redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_a) + $unsigned(redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_b);
        end
    end
    assign redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_q = redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_o[7:0];

    // redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_inputreg0(DELAY,31756)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl);
        end
    end

    // redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_wraddr(COUNTER,31759)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_wraddr_i <= $unsigned(redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_wraddr_q = redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_wraddr_i[6:0];

    // redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem(DUALMEM,31758)
    assign redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_ia = $unsigned(redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_inputreg0_q);
    assign redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_aa = redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_wraddr_q;
    assign redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_ab = redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_aa),
        .data_a(redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_ab),
        .q_b(redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_q = redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_iq[15:0];

    // redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_outputreg0(DELAY,31757)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_outputreg0_q <= $unsigned(redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28024)@137 + 5
    // out q@143
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856(ADD,8610)@143
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod366_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_b = $unsigned({{5{i_shl_i_i_i_i_i_i_65_c_compstr1855_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_65_c_compstr1855_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_o[33:0];

    // rightShiftStage0_uid18999_dupName_261_i_unnamed_c_compstr0_shift_x(MUX,18998)@143
    assign rightShiftStage0_uid18999_dupName_261_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18999_dupName_261_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_q or rightShiftStage0Idx1_uid18997_dupName_261_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18999_dupName_261_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18999_dupName_261_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_q;
            1'b1 : rightShiftStage0_uid18999_dupName_261_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18997_dupName_261_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18999_dupName_261_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19004_dupName_261_i_unnamed_c_compstr0_shift_x(MUX,19003)@143
    assign rightShiftStage1_uid19004_dupName_261_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19004_dupName_261_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18999_dupName_261_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19002_dupName_261_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19004_dupName_261_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19004_dupName_261_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18999_dupName_261_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19004_dupName_261_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19002_dupName_261_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19004_dupName_261_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19009_dupName_261_i_unnamed_c_compstr0_shift_x(MUX,19008)@143
    assign rightShiftStage2_uid19009_dupName_261_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19009_dupName_261_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19004_dupName_261_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19007_dupName_261_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19009_dupName_261_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19009_dupName_261_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19004_dupName_261_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19009_dupName_261_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19007_dupName_261_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19009_dupName_261_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1857_vt_select_20(BITSELECT,10542)@143
    assign i_unnamed_c_compstr1857_vt_select_20_b = rightShiftStage2_uid19009_dupName_261_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1857_vt_join(BITJOIN,10541)@143
    assign i_unnamed_c_compstr1857_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1857_vt_select_20_b};

    // i_conv_i_i_i_i_i_65_c_compstr1858_sel_x(BITSELECT,3801)@143
    assign i_conv_i_i_i_i_i_65_c_compstr1858_sel_x_b = i_unnamed_c_compstr1857_vt_join_q[15:0];

    // redist1064_i_conv_i_i_i_i_i_65_c_compstr1858_sel_x_b_1(DELAY,29292)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1064_i_conv_i_i_i_i_i_65_c_compstr1858_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_65_c_compstr1858_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19018_dupName_262_i_unnamed_c_compstr0_shift_x(BITSELECT,19017)@143
    assign rightShiftStage1Idx1Rng8_uid19018_dupName_262_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19017_dupName_262_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19020_dupName_262_i_unnamed_c_compstr0_shift_x(BITJOIN,19019)@143
    assign rightShiftStage1Idx1_uid19020_dupName_262_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19018_dupName_262_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19013_dupName_262_i_unnamed_c_compstr0_shift_x(BITSELECT,19012)@143
    assign rightShiftStage0Idx1Rng4_uid19013_dupName_262_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_q[33:4];

    // rightShiftStage0Idx1_uid19015_dupName_262_i_unnamed_c_compstr0_shift_x(BITJOIN,19014)@143
    assign rightShiftStage0Idx1_uid19015_dupName_262_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19013_dupName_262_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19017_dupName_262_i_unnamed_c_compstr0_shift_x(MUX,19016)@143
    assign rightShiftStage0_uid19017_dupName_262_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19017_dupName_262_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_q or rightShiftStage0Idx1_uid19015_dupName_262_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19017_dupName_262_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19017_dupName_262_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compstr1856_q;
            1'b1 : rightShiftStage0_uid19017_dupName_262_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19015_dupName_262_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19017_dupName_262_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19022_dupName_262_i_unnamed_c_compstr0_shift_x(MUX,19021)@143
    assign rightShiftStage1_uid19022_dupName_262_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19022_dupName_262_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19017_dupName_262_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19020_dupName_262_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19022_dupName_262_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19022_dupName_262_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19017_dupName_262_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19022_dupName_262_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19020_dupName_262_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19022_dupName_262_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1859_vt_select_21(BITSELECT,10545)@143
    assign i_unnamed_c_compstr1859_vt_select_21_b = rightShiftStage1_uid19022_dupName_262_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1859_vt_join(BITJOIN,10544)@143
    assign i_unnamed_c_compstr1859_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1859_vt_select_21_b};

    // i_unnamed_c_compstr1860_sel_x(BITSELECT,6102)@143
    assign i_unnamed_c_compstr1860_sel_x_b = i_unnamed_c_compstr1859_vt_join_q[15:0];

    // i_unnamed_c_compstr1861_BitSelect_for_a(BITSELECT,27593)@143
    assign i_unnamed_c_compstr1861_BitSelect_for_a_b = i_unnamed_c_compstr1860_sel_x_b[0:0];

    // i_unnamed_c_compstr1861_join(BITJOIN,27594)@143
    assign i_unnamed_c_compstr1861_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1861_BitSelect_for_a_b};

    // i_unnamed_c_compstr1861_vt_select_0(BITSELECT,10550)@143
    assign i_unnamed_c_compstr1861_vt_select_0_b = i_unnamed_c_compstr1861_join_q[0:0];

    // redist188_i_unnamed_c_compstr1861_vt_select_0_b_1(DELAY,28416)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist188_i_unnamed_c_compstr1861_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1861_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1861_vt_join(BITJOIN,10549)@144
    assign i_unnamed_c_compstr1861_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist188_i_unnamed_c_compstr1861_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_65_c_compstr1862(ADD,7068)@144
    assign i_add_i_i_i_i_i_i_65_c_compstr1862_a = {1'b0, i_unnamed_c_compstr1861_vt_join_q};
    assign i_add_i_i_i_i_i_i_65_c_compstr1862_b = {1'b0, redist1064_i_conv_i_i_i_i_i_65_c_compstr1858_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_65_c_compstr1862_o = $unsigned(i_add_i_i_i_i_i_i_65_c_compstr1862_a) + $unsigned(i_add_i_i_i_i_i_i_65_c_compstr1862_b);
    assign i_add_i_i_i_i_i_i_65_c_compstr1862_q = i_add_i_i_i_i_i_i_65_c_compstr1862_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_65_c_compstr1862_sel_x(BITSELECT,2262)@144
    assign bgTrunc_i_add_i_i_i_i_i_i_65_c_compstr1862_sel_x_b = i_add_i_i_i_i_i_i_65_c_compstr1862_q[15:0];

    // i_conv_i_i_i_i_i_i279_66_c_compstr1882_sel_x(BITSELECT,3930)@144
    assign i_conv_i_i_i_i_i_i279_66_c_compstr1882_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_65_c_compstr1862_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_66_c_compstr1882_vt_select_15(BITSELECT,8237)@144
    assign i_conv_i_i_i_i_i_i279_66_c_compstr1882_vt_select_15_b = i_conv_i_i_i_i_i_i279_66_c_compstr1882_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_66_c_compstr1882_vt_join(BITJOIN,8236)@144
    assign i_conv_i_i_i_i_i_i279_66_c_compstr1882_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_66_c_compstr1882_vt_select_15_b};

    // leftShiftStage0_uid26762_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x(MUX,26761)@144
    assign leftShiftStage0_uid26762_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26762_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_66_c_compstr1882_vt_join_q or leftShiftStage0Idx1_uid26760_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26762_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26762_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_66_c_compstr1882_vt_join_q;
            1'b1 : leftShiftStage0_uid26762_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26760_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26762_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26767_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x(MUX,26766)@144
    assign leftShiftStage1_uid26767_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26767_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_s or leftShiftStage0_uid26762_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26765_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26767_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26767_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q = leftShiftStage0_uid26762_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26767_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26765_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26767_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26772_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x(MUX,26771)@144
    assign leftShiftStage2_uid26772_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26772_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_s or leftShiftStage1_uid26767_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26770_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26772_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26772_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q = leftShiftStage1_uid26767_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26772_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26770_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26772_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_66_c_compstr1883_vt_select_28(BITSELECT,9691)@144
    assign i_shl_i_i_i_i_i_i_66_c_compstr1883_vt_select_28_b = leftShiftStage2_uid26772_i_shl_i_i_i_i_i_i_66_c_compstr0_shift_x_q[28:13];

    // redist293_i_shl_i_i_i_i_i_i_66_c_compstr1883_vt_select_28_b_1(DELAY,28521)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist293_i_shl_i_i_i_i_i_i_66_c_compstr1883_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_66_c_compstr1883_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_66_c_compstr1883_vt_join(BITJOIN,9690)@145
    assign i_shl_i_i_i_i_i_i_66_c_compstr1883_vt_join_q = {redist293_i_shl_i_i_i_i_i_i_66_c_compstr1883_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_offset(CONSTANT,30330)
    assign redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_offset_q = $unsigned(7'b0000010);

    // redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_rdcnt(ADD,31779)
    assign redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_a = {1'b0, redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_wraddr_q};
    assign redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_b = {1'b0, redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_o <= $unsigned(redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_a) + $unsigned(redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_b);
        end
    end
    assign redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_q = redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_o[7:0];

    // redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_inputreg0(DELAY,31774)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl);
        end
    end

    // redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_wraddr(COUNTER,31777)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_wraddr_i <= $unsigned(redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_wraddr_q = redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_wraddr_i[6:0];

    // redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem(DUALMEM,31776)
    assign redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_ia = $unsigned(redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_inputreg0_q);
    assign redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_aa = redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_wraddr_q;
    assign redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_ab = redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_aa),
        .data_a(redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_ab),
        .q_b(redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_q = redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_iq[15:0];

    // redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_outputreg0(DELAY,31775)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_outputreg0_q <= $unsigned(redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_mem_q);
        end
    end

    // redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_rdcnt(ADD,30331)
    assign redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_a = {1'b0, redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_wraddr_q};
    assign redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_b = {1'b0, redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_o <= $unsigned(redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_a) + $unsigned(redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_b);
        end
    end
    assign redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_q = redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_o[7:0];

    // redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_inputreg0(DELAY,30326)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl);
        end
    end

    // redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_wraddr(COUNTER,30329)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_wraddr_i <= $unsigned(redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_wraddr_q = redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_wraddr_i[6:0];

    // redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem(DUALMEM,30328)
    assign redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_ia = $unsigned(redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_inputreg0_q);
    assign redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_aa = redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_wraddr_q;
    assign redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_ab = redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_aa),
        .data_a(redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_ab),
        .q_b(redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_q = redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_iq[15:0];

    // redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_outputreg0(DELAY,30327)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_outputreg0_q <= $unsigned(redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_mem_q);
        end
    end

    // redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_rdcnt(ADD,30337)
    assign redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_a = {1'b0, redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_wraddr_q};
    assign redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_b = {1'b0, redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_o <= $unsigned(redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_a) + $unsigned(redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_b);
        end
    end
    assign redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_q = redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_o[7:0];

    // redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_inputreg0(DELAY,30332)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl);
        end
    end

    // redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_wraddr(COUNTER,30335)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_wraddr_i <= $unsigned(redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_wraddr_q = redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_wraddr_i[6:0];

    // redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem(DUALMEM,30334)
    assign redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_ia = $unsigned(redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_inputreg0_q);
    assign redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_aa = redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_wraddr_q;
    assign redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_ab = redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_aa),
        .data_a(redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_ab),
        .q_b(redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_q = redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_iq[15:0];

    // redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_outputreg0(DELAY,30333)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_outputreg0_q <= $unsigned(redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_mem_q);
        end
    end

    // redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_rdcnt(ADD,31773)
    assign redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_a = {1'b0, redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_wraddr_q};
    assign redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_b = {1'b0, redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_o <= $unsigned(redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_a) + $unsigned(redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_b);
        end
    end
    assign redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_q = redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_o[7:0];

    // redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_inputreg0(DELAY,31768)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl);
        end
    end

    // redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_wraddr(COUNTER,31771)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_wraddr_i <= $unsigned(redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_wraddr_q = redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_wraddr_i[6:0];

    // redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem(DUALMEM,31770)
    assign redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_ia = $unsigned(redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_inputreg0_q);
    assign redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_aa = redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_wraddr_q;
    assign redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_ab = redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_aa),
        .data_a(redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_ab),
        .q_b(redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_q = redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_iq[15:0];

    // redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_outputreg0(DELAY,31769)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_outputreg0_q <= $unsigned(redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28025)@139 + 5
    // out q@145
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884(ADD,8611)@145
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod371_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_b = $unsigned({{5{i_shl_i_i_i_i_i_i_66_c_compstr1883_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_66_c_compstr1883_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_o[33:0];

    // rightShiftStage0_uid19061_dupName_265_i_unnamed_c_compstr0_shift_x(MUX,19060)@145
    assign rightShiftStage0_uid19061_dupName_265_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19061_dupName_265_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_q or rightShiftStage0Idx1_uid19059_dupName_265_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19061_dupName_265_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19061_dupName_265_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_q;
            1'b1 : rightShiftStage0_uid19061_dupName_265_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19059_dupName_265_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19061_dupName_265_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19066_dupName_265_i_unnamed_c_compstr0_shift_x(MUX,19065)@145
    assign rightShiftStage1_uid19066_dupName_265_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19066_dupName_265_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19061_dupName_265_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19064_dupName_265_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19066_dupName_265_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19066_dupName_265_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19061_dupName_265_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19066_dupName_265_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19064_dupName_265_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19066_dupName_265_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19071_dupName_265_i_unnamed_c_compstr0_shift_x(MUX,19070)@145
    assign rightShiftStage2_uid19071_dupName_265_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19071_dupName_265_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19066_dupName_265_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19069_dupName_265_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19071_dupName_265_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19071_dupName_265_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19066_dupName_265_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19071_dupName_265_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19069_dupName_265_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19071_dupName_265_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1885_vt_select_20(BITSELECT,10564)@145
    assign i_unnamed_c_compstr1885_vt_select_20_b = rightShiftStage2_uid19071_dupName_265_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1885_vt_join(BITJOIN,10563)@145
    assign i_unnamed_c_compstr1885_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1885_vt_select_20_b};

    // i_conv_i_i_i_i_i_66_c_compstr1886_sel_x(BITSELECT,3802)@145
    assign i_conv_i_i_i_i_i_66_c_compstr1886_sel_x_b = i_unnamed_c_compstr1885_vt_join_q[15:0];

    // redist1063_i_conv_i_i_i_i_i_66_c_compstr1886_sel_x_b_1(DELAY,29291)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1063_i_conv_i_i_i_i_i_66_c_compstr1886_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_66_c_compstr1886_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19080_dupName_266_i_unnamed_c_compstr0_shift_x(BITSELECT,19079)@145
    assign rightShiftStage1Idx1Rng8_uid19080_dupName_266_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19079_dupName_266_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19082_dupName_266_i_unnamed_c_compstr0_shift_x(BITJOIN,19081)@145
    assign rightShiftStage1Idx1_uid19082_dupName_266_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19080_dupName_266_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19075_dupName_266_i_unnamed_c_compstr0_shift_x(BITSELECT,19074)@145
    assign rightShiftStage0Idx1Rng4_uid19075_dupName_266_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_q[33:4];

    // rightShiftStage0Idx1_uid19077_dupName_266_i_unnamed_c_compstr0_shift_x(BITJOIN,19076)@145
    assign rightShiftStage0Idx1_uid19077_dupName_266_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19075_dupName_266_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19079_dupName_266_i_unnamed_c_compstr0_shift_x(MUX,19078)@145
    assign rightShiftStage0_uid19079_dupName_266_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19079_dupName_266_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_q or rightShiftStage0Idx1_uid19077_dupName_266_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19079_dupName_266_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19079_dupName_266_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compstr1884_q;
            1'b1 : rightShiftStage0_uid19079_dupName_266_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19077_dupName_266_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19079_dupName_266_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19084_dupName_266_i_unnamed_c_compstr0_shift_x(MUX,19083)@145
    assign rightShiftStage1_uid19084_dupName_266_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19084_dupName_266_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19079_dupName_266_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19082_dupName_266_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19084_dupName_266_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19084_dupName_266_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19079_dupName_266_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19084_dupName_266_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19082_dupName_266_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19084_dupName_266_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1887_vt_select_21(BITSELECT,10567)@145
    assign i_unnamed_c_compstr1887_vt_select_21_b = rightShiftStage1_uid19084_dupName_266_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1887_vt_join(BITJOIN,10566)@145
    assign i_unnamed_c_compstr1887_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1887_vt_select_21_b};

    // i_unnamed_c_compstr1888_sel_x(BITSELECT,6104)@145
    assign i_unnamed_c_compstr1888_sel_x_b = i_unnamed_c_compstr1887_vt_join_q[15:0];

    // i_unnamed_c_compstr1889_BitSelect_for_a(BITSELECT,27597)@145
    assign i_unnamed_c_compstr1889_BitSelect_for_a_b = i_unnamed_c_compstr1888_sel_x_b[0:0];

    // i_unnamed_c_compstr1889_join(BITJOIN,27598)@145
    assign i_unnamed_c_compstr1889_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1889_BitSelect_for_a_b};

    // i_unnamed_c_compstr1889_vt_select_0(BITSELECT,10572)@145
    assign i_unnamed_c_compstr1889_vt_select_0_b = i_unnamed_c_compstr1889_join_q[0:0];

    // redist186_i_unnamed_c_compstr1889_vt_select_0_b_1(DELAY,28414)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist186_i_unnamed_c_compstr1889_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1889_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1889_vt_join(BITJOIN,10571)@146
    assign i_unnamed_c_compstr1889_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist186_i_unnamed_c_compstr1889_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_66_c_compstr1890(ADD,7069)@146
    assign i_add_i_i_i_i_i_i_66_c_compstr1890_a = {1'b0, i_unnamed_c_compstr1889_vt_join_q};
    assign i_add_i_i_i_i_i_i_66_c_compstr1890_b = {1'b0, redist1063_i_conv_i_i_i_i_i_66_c_compstr1886_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_66_c_compstr1890_o = $unsigned(i_add_i_i_i_i_i_i_66_c_compstr1890_a) + $unsigned(i_add_i_i_i_i_i_i_66_c_compstr1890_b);
    assign i_add_i_i_i_i_i_i_66_c_compstr1890_q = i_add_i_i_i_i_i_i_66_c_compstr1890_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_66_c_compstr1890_sel_x(BITSELECT,2263)@146
    assign bgTrunc_i_add_i_i_i_i_i_i_66_c_compstr1890_sel_x_b = i_add_i_i_i_i_i_i_66_c_compstr1890_q[15:0];

    // i_conv_i_i_i_i_i_i279_67_c_compstr1910_sel_x(BITSELECT,3931)@146
    assign i_conv_i_i_i_i_i_i279_67_c_compstr1910_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_66_c_compstr1890_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_67_c_compstr1910_vt_select_15(BITSELECT,8241)@146
    assign i_conv_i_i_i_i_i_i279_67_c_compstr1910_vt_select_15_b = i_conv_i_i_i_i_i_i279_67_c_compstr1910_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_67_c_compstr1910_vt_join(BITJOIN,8240)@146
    assign i_conv_i_i_i_i_i_i279_67_c_compstr1910_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_67_c_compstr1910_vt_select_15_b};

    // leftShiftStage0_uid26780_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x(MUX,26779)@146
    assign leftShiftStage0_uid26780_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26780_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_67_c_compstr1910_vt_join_q or leftShiftStage0Idx1_uid26778_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26780_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26780_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_67_c_compstr1910_vt_join_q;
            1'b1 : leftShiftStage0_uid26780_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26778_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26780_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26785_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x(MUX,26784)@146
    assign leftShiftStage1_uid26785_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26785_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_s or leftShiftStage0_uid26780_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26783_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26785_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26785_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q = leftShiftStage0_uid26780_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26785_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26783_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26785_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26790_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x(MUX,26789)@146
    assign leftShiftStage2_uid26790_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26790_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_s or leftShiftStage1_uid26785_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26788_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26790_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26790_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q = leftShiftStage1_uid26785_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26790_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26788_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26790_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_67_c_compstr1911_vt_select_28(BITSELECT,9694)@146
    assign i_shl_i_i_i_i_i_i_67_c_compstr1911_vt_select_28_b = leftShiftStage2_uid26790_i_shl_i_i_i_i_i_i_67_c_compstr0_shift_x_q[28:13];

    // redist292_i_shl_i_i_i_i_i_i_67_c_compstr1911_vt_select_28_b_1(DELAY,28520)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist292_i_shl_i_i_i_i_i_i_67_c_compstr1911_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_67_c_compstr1911_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_67_c_compstr1911_vt_join(BITJOIN,9693)@147
    assign i_shl_i_i_i_i_i_i_67_c_compstr1911_vt_join_q = {redist292_i_shl_i_i_i_i_i_i_67_c_compstr1911_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_offset(CONSTANT,30342)
    assign redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_offset_q = $unsigned(8'b10000000);

    // redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_rdcnt(ADD,31791)
    assign redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_a = {1'b0, redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_wraddr_q};
    assign redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_b = {1'b0, redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_o <= $unsigned(redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_a) + $unsigned(redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_b);
        end
    end
    assign redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_q = redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_o[8:0];

    // redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_inputreg0(DELAY,31786)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl);
        end
    end

    // redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_wraddr(COUNTER,31789)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_wraddr_i <= $unsigned(redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_wraddr_q = redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_wraddr_i[7:0];

    // redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem(DUALMEM,31788)
    assign redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_ia = $unsigned(redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_inputreg0_q);
    assign redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_aa = redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_wraddr_q;
    assign redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_ab = redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_aa),
        .data_a(redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_ab),
        .q_b(redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_q = redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_iq[15:0];

    // redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_outputreg0(DELAY,31787)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_outputreg0_q <= $unsigned(redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_mem_q);
        end
    end

    // redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_rdcnt(ADD,30343)
    assign redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_a = {1'b0, redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_wraddr_q};
    assign redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_b = {1'b0, redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_o <= $unsigned(redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_a) + $unsigned(redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_b);
        end
    end
    assign redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_q = redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_o[8:0];

    // redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_inputreg0(DELAY,30338)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl);
        end
    end

    // redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_wraddr(COUNTER,30341)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_wraddr_i <= $unsigned(redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_wraddr_q = redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_wraddr_i[7:0];

    // redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem(DUALMEM,30340)
    assign redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_ia = $unsigned(redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_inputreg0_q);
    assign redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_aa = redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_wraddr_q;
    assign redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_ab = redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_aa),
        .data_a(redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_ab),
        .q_b(redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_q = redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_iq[15:0];

    // redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_outputreg0(DELAY,30339)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_outputreg0_q <= $unsigned(redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_mem_q);
        end
    end

    // redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_rdcnt(ADD,30349)
    assign redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_a = {1'b0, redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_wraddr_q};
    assign redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_b = {1'b0, redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_o <= $unsigned(redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_a) + $unsigned(redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_b);
        end
    end
    assign redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_q = redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_o[8:0];

    // redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_inputreg0(DELAY,30344)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl);
        end
    end

    // redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_wraddr(COUNTER,30347)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_wraddr_i <= $unsigned(redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_wraddr_q = redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_wraddr_i[7:0];

    // redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem(DUALMEM,30346)
    assign redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_ia = $unsigned(redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_inputreg0_q);
    assign redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_aa = redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_wraddr_q;
    assign redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_ab = redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_aa),
        .data_a(redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_ab),
        .q_b(redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_q = redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_iq[15:0];

    // redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_outputreg0(DELAY,30345)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_outputreg0_q <= $unsigned(redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_mem_q);
        end
    end

    // redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_rdcnt(ADD,31785)
    assign redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_a = {1'b0, redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_wraddr_q};
    assign redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_b = {1'b0, redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_o <= $unsigned(redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_a) + $unsigned(redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_b);
        end
    end
    assign redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_q = redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_o[8:0];

    // redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_inputreg0(DELAY,31780)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl);
        end
    end

    // redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_wraddr(COUNTER,31783)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_wraddr_i <= $unsigned(redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_wraddr_q = redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_wraddr_i[7:0];

    // redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem(DUALMEM,31782)
    assign redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_ia = $unsigned(redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_inputreg0_q);
    assign redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_aa = redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_wraddr_q;
    assign redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_ab = redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_aa),
        .data_a(redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_ab),
        .q_b(redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_q = redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_iq[15:0];

    // redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_outputreg0(DELAY,31781)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_outputreg0_q <= $unsigned(redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28026)@141 + 5
    // out q@147
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912(ADD,8612)@147
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod376_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_b = $unsigned({{5{i_shl_i_i_i_i_i_i_67_c_compstr1911_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_67_c_compstr1911_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_o[33:0];

    // rightShiftStage0_uid19123_dupName_269_i_unnamed_c_compstr0_shift_x(MUX,19122)@147
    assign rightShiftStage0_uid19123_dupName_269_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19123_dupName_269_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_q or rightShiftStage0Idx1_uid19121_dupName_269_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19123_dupName_269_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19123_dupName_269_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_q;
            1'b1 : rightShiftStage0_uid19123_dupName_269_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19121_dupName_269_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19123_dupName_269_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19128_dupName_269_i_unnamed_c_compstr0_shift_x(MUX,19127)@147
    assign rightShiftStage1_uid19128_dupName_269_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19128_dupName_269_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19123_dupName_269_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19126_dupName_269_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19128_dupName_269_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19128_dupName_269_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19123_dupName_269_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19128_dupName_269_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19126_dupName_269_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19128_dupName_269_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19133_dupName_269_i_unnamed_c_compstr0_shift_x(MUX,19132)@147
    assign rightShiftStage2_uid19133_dupName_269_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19133_dupName_269_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19128_dupName_269_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19131_dupName_269_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19133_dupName_269_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19133_dupName_269_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19128_dupName_269_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19133_dupName_269_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19131_dupName_269_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19133_dupName_269_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1913_vt_select_20(BITSELECT,10589)@147
    assign i_unnamed_c_compstr1913_vt_select_20_b = rightShiftStage2_uid19133_dupName_269_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1913_vt_join(BITJOIN,10588)@147
    assign i_unnamed_c_compstr1913_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1913_vt_select_20_b};

    // i_conv_i_i_i_i_i_67_c_compstr1914_sel_x(BITSELECT,3803)@147
    assign i_conv_i_i_i_i_i_67_c_compstr1914_sel_x_b = i_unnamed_c_compstr1913_vt_join_q[15:0];

    // redist1062_i_conv_i_i_i_i_i_67_c_compstr1914_sel_x_b_1(DELAY,29290)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1062_i_conv_i_i_i_i_i_67_c_compstr1914_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_67_c_compstr1914_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19142_dupName_270_i_unnamed_c_compstr0_shift_x(BITSELECT,19141)@147
    assign rightShiftStage1Idx1Rng8_uid19142_dupName_270_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19141_dupName_270_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19144_dupName_270_i_unnamed_c_compstr0_shift_x(BITJOIN,19143)@147
    assign rightShiftStage1Idx1_uid19144_dupName_270_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19142_dupName_270_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19137_dupName_270_i_unnamed_c_compstr0_shift_x(BITSELECT,19136)@147
    assign rightShiftStage0Idx1Rng4_uid19137_dupName_270_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_q[33:4];

    // rightShiftStage0Idx1_uid19139_dupName_270_i_unnamed_c_compstr0_shift_x(BITJOIN,19138)@147
    assign rightShiftStage0Idx1_uid19139_dupName_270_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19137_dupName_270_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19141_dupName_270_i_unnamed_c_compstr0_shift_x(MUX,19140)@147
    assign rightShiftStage0_uid19141_dupName_270_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19141_dupName_270_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_q or rightShiftStage0Idx1_uid19139_dupName_270_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19141_dupName_270_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19141_dupName_270_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compstr1912_q;
            1'b1 : rightShiftStage0_uid19141_dupName_270_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19139_dupName_270_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19141_dupName_270_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19146_dupName_270_i_unnamed_c_compstr0_shift_x(MUX,19145)@147
    assign rightShiftStage1_uid19146_dupName_270_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19146_dupName_270_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19141_dupName_270_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19144_dupName_270_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19146_dupName_270_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19146_dupName_270_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19141_dupName_270_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19146_dupName_270_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19144_dupName_270_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19146_dupName_270_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1915_vt_select_21(BITSELECT,10592)@147
    assign i_unnamed_c_compstr1915_vt_select_21_b = rightShiftStage1_uid19146_dupName_270_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1915_vt_join(BITJOIN,10591)@147
    assign i_unnamed_c_compstr1915_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1915_vt_select_21_b};

    // i_unnamed_c_compstr1916_sel_x(BITSELECT,6106)@147
    assign i_unnamed_c_compstr1916_sel_x_b = i_unnamed_c_compstr1915_vt_join_q[15:0];

    // i_unnamed_c_compstr1917_BitSelect_for_a(BITSELECT,27601)@147
    assign i_unnamed_c_compstr1917_BitSelect_for_a_b = i_unnamed_c_compstr1916_sel_x_b[0:0];

    // i_unnamed_c_compstr1917_join(BITJOIN,27602)@147
    assign i_unnamed_c_compstr1917_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1917_BitSelect_for_a_b};

    // i_unnamed_c_compstr1917_vt_select_0(BITSELECT,10597)@147
    assign i_unnamed_c_compstr1917_vt_select_0_b = i_unnamed_c_compstr1917_join_q[0:0];

    // redist184_i_unnamed_c_compstr1917_vt_select_0_b_1(DELAY,28412)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist184_i_unnamed_c_compstr1917_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1917_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1917_vt_join(BITJOIN,10596)@148
    assign i_unnamed_c_compstr1917_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist184_i_unnamed_c_compstr1917_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_67_c_compstr1918(ADD,7070)@148
    assign i_add_i_i_i_i_i_i_67_c_compstr1918_a = {1'b0, i_unnamed_c_compstr1917_vt_join_q};
    assign i_add_i_i_i_i_i_i_67_c_compstr1918_b = {1'b0, redist1062_i_conv_i_i_i_i_i_67_c_compstr1914_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_67_c_compstr1918_o = $unsigned(i_add_i_i_i_i_i_i_67_c_compstr1918_a) + $unsigned(i_add_i_i_i_i_i_i_67_c_compstr1918_b);
    assign i_add_i_i_i_i_i_i_67_c_compstr1918_q = i_add_i_i_i_i_i_i_67_c_compstr1918_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_67_c_compstr1918_sel_x(BITSELECT,2264)@148
    assign bgTrunc_i_add_i_i_i_i_i_i_67_c_compstr1918_sel_x_b = i_add_i_i_i_i_i_i_67_c_compstr1918_q[15:0];

    // i_conv_i_i_i_i_i_i279_68_c_compstr1938_sel_x(BITSELECT,3932)@148
    assign i_conv_i_i_i_i_i_i279_68_c_compstr1938_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_67_c_compstr1918_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_68_c_compstr1938_vt_select_15(BITSELECT,8245)@148
    assign i_conv_i_i_i_i_i_i279_68_c_compstr1938_vt_select_15_b = i_conv_i_i_i_i_i_i279_68_c_compstr1938_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_68_c_compstr1938_vt_join(BITJOIN,8244)@148
    assign i_conv_i_i_i_i_i_i279_68_c_compstr1938_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_68_c_compstr1938_vt_select_15_b};

    // leftShiftStage0_uid26798_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x(MUX,26797)@148
    assign leftShiftStage0_uid26798_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26798_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_68_c_compstr1938_vt_join_q or leftShiftStage0Idx1_uid26796_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26798_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26798_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_68_c_compstr1938_vt_join_q;
            1'b1 : leftShiftStage0_uid26798_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26796_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26798_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26803_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x(MUX,26802)@148
    assign leftShiftStage1_uid26803_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26803_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_s or leftShiftStage0_uid26798_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26801_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26803_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26803_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q = leftShiftStage0_uid26798_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26803_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26801_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26803_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26808_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x(MUX,26807)@148
    assign leftShiftStage2_uid26808_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26808_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_s or leftShiftStage1_uid26803_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26806_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26808_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26808_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q = leftShiftStage1_uid26803_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26808_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26806_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26808_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_68_c_compstr1939_vt_select_28(BITSELECT,9697)@148
    assign i_shl_i_i_i_i_i_i_68_c_compstr1939_vt_select_28_b = leftShiftStage2_uid26808_i_shl_i_i_i_i_i_i_68_c_compstr0_shift_x_q[28:13];

    // redist291_i_shl_i_i_i_i_i_i_68_c_compstr1939_vt_select_28_b_1(DELAY,28519)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist291_i_shl_i_i_i_i_i_i_68_c_compstr1939_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_68_c_compstr1939_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_68_c_compstr1939_vt_join(BITJOIN,9696)@149
    assign i_shl_i_i_i_i_i_i_68_c_compstr1939_vt_join_q = {redist291_i_shl_i_i_i_i_i_i_68_c_compstr1939_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_offset(CONSTANT,30354)
    assign redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_offset_q = $unsigned(8'b01111110);

    // redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_rdcnt(ADD,31803)
    assign redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_a = {1'b0, redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_wraddr_q};
    assign redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_b = {1'b0, redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_o <= $unsigned(redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_a) + $unsigned(redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_b);
        end
    end
    assign redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_q = redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_o[8:0];

    // redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_inputreg0(DELAY,31798)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl);
        end
    end

    // redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_wraddr(COUNTER,31801)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_wraddr_i <= $unsigned(redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_wraddr_q = redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_wraddr_i[7:0];

    // redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem(DUALMEM,31800)
    assign redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_ia = $unsigned(redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_inputreg0_q);
    assign redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_aa = redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_wraddr_q;
    assign redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_ab = redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_aa),
        .data_a(redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_ab),
        .q_b(redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_q = redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_iq[15:0];

    // redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_outputreg0(DELAY,31799)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_outputreg0_q <= $unsigned(redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_mem_q);
        end
    end

    // redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_rdcnt(ADD,30355)
    assign redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_a = {1'b0, redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_wraddr_q};
    assign redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_b = {1'b0, redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_o <= $unsigned(redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_a) + $unsigned(redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_b);
        end
    end
    assign redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_q = redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_o[8:0];

    // redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_inputreg0(DELAY,30350)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl);
        end
    end

    // redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_wraddr(COUNTER,30353)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_wraddr_i <= $unsigned(redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_wraddr_q = redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_wraddr_i[7:0];

    // redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem(DUALMEM,30352)
    assign redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_ia = $unsigned(redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_inputreg0_q);
    assign redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_aa = redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_wraddr_q;
    assign redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_ab = redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_aa),
        .data_a(redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_ab),
        .q_b(redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_q = redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_iq[15:0];

    // redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_outputreg0(DELAY,30351)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_outputreg0_q <= $unsigned(redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_mem_q);
        end
    end

    // redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_rdcnt(ADD,30361)
    assign redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_a = {1'b0, redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_wraddr_q};
    assign redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_b = {1'b0, redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_o <= $unsigned(redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_a) + $unsigned(redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_b);
        end
    end
    assign redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_q = redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_o[8:0];

    // redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_inputreg0(DELAY,30356)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl);
        end
    end

    // redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_wraddr(COUNTER,30359)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_wraddr_i <= $unsigned(redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_wraddr_q = redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_wraddr_i[7:0];

    // redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem(DUALMEM,30358)
    assign redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_ia = $unsigned(redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_inputreg0_q);
    assign redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_aa = redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_wraddr_q;
    assign redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_ab = redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_aa),
        .data_a(redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_ab),
        .q_b(redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_q = redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_iq[15:0];

    // redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_outputreg0(DELAY,30357)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_outputreg0_q <= $unsigned(redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_mem_q);
        end
    end

    // redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_rdcnt(ADD,31797)
    assign redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_a = {1'b0, redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_wraddr_q};
    assign redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_b = {1'b0, redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_o <= $unsigned(redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_a) + $unsigned(redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_b);
        end
    end
    assign redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_q = redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_o[8:0];

    // redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_inputreg0(DELAY,31792)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl);
        end
    end

    // redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_wraddr(COUNTER,31795)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_wraddr_i <= $unsigned(redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_wraddr_q = redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_wraddr_i[7:0];

    // redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem(DUALMEM,31794)
    assign redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_ia = $unsigned(redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_inputreg0_q);
    assign redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_aa = redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_wraddr_q;
    assign redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_ab = redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_aa),
        .data_a(redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_ab),
        .q_b(redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_q = redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_iq[15:0];

    // redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_outputreg0(DELAY,31793)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_outputreg0_q <= $unsigned(redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28027)@143 + 5
    // out q@149
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940(ADD,8613)@149
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod381_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_b = $unsigned({{5{i_shl_i_i_i_i_i_i_68_c_compstr1939_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_68_c_compstr1939_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_o[33:0];

    // rightShiftStage0_uid19185_dupName_273_i_unnamed_c_compstr0_shift_x(MUX,19184)@149
    assign rightShiftStage0_uid19185_dupName_273_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19185_dupName_273_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_q or rightShiftStage0Idx1_uid19183_dupName_273_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19185_dupName_273_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19185_dupName_273_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_q;
            1'b1 : rightShiftStage0_uid19185_dupName_273_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19183_dupName_273_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19185_dupName_273_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19190_dupName_273_i_unnamed_c_compstr0_shift_x(MUX,19189)@149
    assign rightShiftStage1_uid19190_dupName_273_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19190_dupName_273_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19185_dupName_273_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19188_dupName_273_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19190_dupName_273_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19190_dupName_273_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19185_dupName_273_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19190_dupName_273_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19188_dupName_273_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19190_dupName_273_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19195_dupName_273_i_unnamed_c_compstr0_shift_x(MUX,19194)@149
    assign rightShiftStage2_uid19195_dupName_273_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19195_dupName_273_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19190_dupName_273_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19193_dupName_273_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19195_dupName_273_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19195_dupName_273_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19190_dupName_273_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19195_dupName_273_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19193_dupName_273_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19195_dupName_273_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1941_vt_select_20(BITSELECT,10619)@149
    assign i_unnamed_c_compstr1941_vt_select_20_b = rightShiftStage2_uid19195_dupName_273_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1941_vt_join(BITJOIN,10618)@149
    assign i_unnamed_c_compstr1941_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1941_vt_select_20_b};

    // i_conv_i_i_i_i_i_68_c_compstr1942_sel_x(BITSELECT,3804)@149
    assign i_conv_i_i_i_i_i_68_c_compstr1942_sel_x_b = i_unnamed_c_compstr1941_vt_join_q[15:0];

    // redist1061_i_conv_i_i_i_i_i_68_c_compstr1942_sel_x_b_1(DELAY,29289)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1061_i_conv_i_i_i_i_i_68_c_compstr1942_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_68_c_compstr1942_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19204_dupName_274_i_unnamed_c_compstr0_shift_x(BITSELECT,19203)@149
    assign rightShiftStage1Idx1Rng8_uid19204_dupName_274_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19203_dupName_274_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19206_dupName_274_i_unnamed_c_compstr0_shift_x(BITJOIN,19205)@149
    assign rightShiftStage1Idx1_uid19206_dupName_274_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19204_dupName_274_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19199_dupName_274_i_unnamed_c_compstr0_shift_x(BITSELECT,19198)@149
    assign rightShiftStage0Idx1Rng4_uid19199_dupName_274_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_q[33:4];

    // rightShiftStage0Idx1_uid19201_dupName_274_i_unnamed_c_compstr0_shift_x(BITJOIN,19200)@149
    assign rightShiftStage0Idx1_uid19201_dupName_274_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19199_dupName_274_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19203_dupName_274_i_unnamed_c_compstr0_shift_x(MUX,19202)@149
    assign rightShiftStage0_uid19203_dupName_274_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19203_dupName_274_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_q or rightShiftStage0Idx1_uid19201_dupName_274_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19203_dupName_274_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19203_dupName_274_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compstr1940_q;
            1'b1 : rightShiftStage0_uid19203_dupName_274_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19201_dupName_274_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19203_dupName_274_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19208_dupName_274_i_unnamed_c_compstr0_shift_x(MUX,19207)@149
    assign rightShiftStage1_uid19208_dupName_274_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19208_dupName_274_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19203_dupName_274_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19206_dupName_274_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19208_dupName_274_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19208_dupName_274_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19203_dupName_274_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19208_dupName_274_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19206_dupName_274_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19208_dupName_274_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1943_vt_select_21(BITSELECT,10622)@149
    assign i_unnamed_c_compstr1943_vt_select_21_b = rightShiftStage1_uid19208_dupName_274_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1943_vt_join(BITJOIN,10621)@149
    assign i_unnamed_c_compstr1943_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1943_vt_select_21_b};

    // i_unnamed_c_compstr1944_sel_x(BITSELECT,6109)@149
    assign i_unnamed_c_compstr1944_sel_x_b = i_unnamed_c_compstr1943_vt_join_q[15:0];

    // i_unnamed_c_compstr1945_BitSelect_for_a(BITSELECT,27607)@149
    assign i_unnamed_c_compstr1945_BitSelect_for_a_b = i_unnamed_c_compstr1944_sel_x_b[0:0];

    // i_unnamed_c_compstr1945_join(BITJOIN,27608)@149
    assign i_unnamed_c_compstr1945_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1945_BitSelect_for_a_b};

    // i_unnamed_c_compstr1945_vt_select_0(BITSELECT,10627)@149
    assign i_unnamed_c_compstr1945_vt_select_0_b = i_unnamed_c_compstr1945_join_q[0:0];

    // redist181_i_unnamed_c_compstr1945_vt_select_0_b_1(DELAY,28409)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist181_i_unnamed_c_compstr1945_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1945_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1945_vt_join(BITJOIN,10626)@150
    assign i_unnamed_c_compstr1945_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist181_i_unnamed_c_compstr1945_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_68_c_compstr1946(ADD,7071)@150
    assign i_add_i_i_i_i_i_i_68_c_compstr1946_a = {1'b0, i_unnamed_c_compstr1945_vt_join_q};
    assign i_add_i_i_i_i_i_i_68_c_compstr1946_b = {1'b0, redist1061_i_conv_i_i_i_i_i_68_c_compstr1942_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_68_c_compstr1946_o = $unsigned(i_add_i_i_i_i_i_i_68_c_compstr1946_a) + $unsigned(i_add_i_i_i_i_i_i_68_c_compstr1946_b);
    assign i_add_i_i_i_i_i_i_68_c_compstr1946_q = i_add_i_i_i_i_i_i_68_c_compstr1946_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_68_c_compstr1946_sel_x(BITSELECT,2265)@150
    assign bgTrunc_i_add_i_i_i_i_i_i_68_c_compstr1946_sel_x_b = i_add_i_i_i_i_i_i_68_c_compstr1946_q[15:0];

    // i_conv_i_i_i_i_i_i279_69_c_compstr1966_sel_x(BITSELECT,3933)@150
    assign i_conv_i_i_i_i_i_i279_69_c_compstr1966_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_68_c_compstr1946_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_69_c_compstr1966_vt_select_15(BITSELECT,8249)@150
    assign i_conv_i_i_i_i_i_i279_69_c_compstr1966_vt_select_15_b = i_conv_i_i_i_i_i_i279_69_c_compstr1966_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_69_c_compstr1966_vt_join(BITJOIN,8248)@150
    assign i_conv_i_i_i_i_i_i279_69_c_compstr1966_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_69_c_compstr1966_vt_select_15_b};

    // leftShiftStage0_uid26816_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x(MUX,26815)@150
    assign leftShiftStage0_uid26816_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26816_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_69_c_compstr1966_vt_join_q or leftShiftStage0Idx1_uid26814_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26816_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26816_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_69_c_compstr1966_vt_join_q;
            1'b1 : leftShiftStage0_uid26816_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26814_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26816_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26821_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x(MUX,26820)@150
    assign leftShiftStage1_uid26821_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26821_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_s or leftShiftStage0_uid26816_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26819_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26821_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26821_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q = leftShiftStage0_uid26816_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26821_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26819_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26821_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26826_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x(MUX,26825)@150
    assign leftShiftStage2_uid26826_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26826_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_s or leftShiftStage1_uid26821_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26824_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26826_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26826_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q = leftShiftStage1_uid26821_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26826_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26824_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26826_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_69_c_compstr1967_vt_select_28(BITSELECT,9700)@150
    assign i_shl_i_i_i_i_i_i_69_c_compstr1967_vt_select_28_b = leftShiftStage2_uid26826_i_shl_i_i_i_i_i_i_69_c_compstr0_shift_x_q[28:13];

    // redist290_i_shl_i_i_i_i_i_i_69_c_compstr1967_vt_select_28_b_1(DELAY,28518)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist290_i_shl_i_i_i_i_i_i_69_c_compstr1967_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_69_c_compstr1967_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_69_c_compstr1967_vt_join(BITJOIN,9699)@151
    assign i_shl_i_i_i_i_i_i_69_c_compstr1967_vt_join_q = {redist290_i_shl_i_i_i_i_i_i_69_c_compstr1967_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_offset(CONSTANT,30366)
    assign redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_offset_q = $unsigned(8'b01111100);

    // redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_rdcnt(ADD,31815)
    assign redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_a = {1'b0, redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_wraddr_q};
    assign redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_b = {1'b0, redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_o <= $unsigned(redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_a) + $unsigned(redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_b);
        end
    end
    assign redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_q = redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_o[8:0];

    // redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_inputreg0(DELAY,31810)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl);
        end
    end

    // redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_wraddr(COUNTER,31813)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_wraddr_i <= $unsigned(redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_wraddr_q = redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_wraddr_i[7:0];

    // redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem(DUALMEM,31812)
    assign redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_ia = $unsigned(redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_inputreg0_q);
    assign redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_aa = redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_wraddr_q;
    assign redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_ab = redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_aa),
        .data_a(redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_ab),
        .q_b(redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_q = redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_iq[15:0];

    // redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_outputreg0(DELAY,31811)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_outputreg0_q <= $unsigned(redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_mem_q);
        end
    end

    // redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_rdcnt(ADD,30367)
    assign redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_a = {1'b0, redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_wraddr_q};
    assign redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_b = {1'b0, redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_o <= $unsigned(redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_a) + $unsigned(redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_b);
        end
    end
    assign redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_q = redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_o[8:0];

    // redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_inputreg0(DELAY,30362)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl);
        end
    end

    // redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_wraddr(COUNTER,30365)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_wraddr_i <= $unsigned(redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_wraddr_q = redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_wraddr_i[7:0];

    // redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem(DUALMEM,30364)
    assign redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_ia = $unsigned(redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_inputreg0_q);
    assign redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_aa = redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_wraddr_q;
    assign redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_ab = redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_aa),
        .data_a(redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_ab),
        .q_b(redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_q = redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_iq[15:0];

    // redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_outputreg0(DELAY,30363)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_outputreg0_q <= $unsigned(redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_mem_q);
        end
    end

    // redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_rdcnt(ADD,30373)
    assign redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_a = {1'b0, redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_wraddr_q};
    assign redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_b = {1'b0, redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_o <= $unsigned(redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_a) + $unsigned(redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_b);
        end
    end
    assign redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_q = redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_o[8:0];

    // redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_inputreg0(DELAY,30368)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl);
        end
    end

    // redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_wraddr(COUNTER,30371)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_wraddr_i <= $unsigned(redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_wraddr_q = redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_wraddr_i[7:0];

    // redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem(DUALMEM,30370)
    assign redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_ia = $unsigned(redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_inputreg0_q);
    assign redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_aa = redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_wraddr_q;
    assign redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_ab = redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_aa),
        .data_a(redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_ab),
        .q_b(redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_q = redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_iq[15:0];

    // redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_outputreg0(DELAY,30369)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_outputreg0_q <= $unsigned(redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_mem_q);
        end
    end

    // redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_rdcnt(ADD,31809)
    assign redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_a = {1'b0, redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_wraddr_q};
    assign redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_b = {1'b0, redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_o <= $unsigned(redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_a) + $unsigned(redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_b);
        end
    end
    assign redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_q = redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_o[8:0];

    // redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_inputreg0(DELAY,31804)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl);
        end
    end

    // redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_wraddr(COUNTER,31807)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_wraddr_i <= $unsigned(redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_wraddr_q = redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_wraddr_i[7:0];

    // redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem(DUALMEM,31806)
    assign redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_ia = $unsigned(redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_inputreg0_q);
    assign redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_aa = redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_wraddr_q;
    assign redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_ab = redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_aa),
        .data_a(redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_ab),
        .q_b(redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_q = redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_iq[15:0];

    // redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_outputreg0(DELAY,31805)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_outputreg0_q <= $unsigned(redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28028)@145 + 5
    // out q@151
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968(ADD,8614)@151
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod386_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_b = $unsigned({{5{i_shl_i_i_i_i_i_i_69_c_compstr1967_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_69_c_compstr1967_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_o[33:0];

    // rightShiftStage0_uid19247_dupName_277_i_unnamed_c_compstr0_shift_x(MUX,19246)@151
    assign rightShiftStage0_uid19247_dupName_277_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19247_dupName_277_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_q or rightShiftStage0Idx1_uid19245_dupName_277_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19247_dupName_277_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19247_dupName_277_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_q;
            1'b1 : rightShiftStage0_uid19247_dupName_277_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19245_dupName_277_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19247_dupName_277_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19252_dupName_277_i_unnamed_c_compstr0_shift_x(MUX,19251)@151
    assign rightShiftStage1_uid19252_dupName_277_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19252_dupName_277_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19247_dupName_277_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19250_dupName_277_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19252_dupName_277_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19252_dupName_277_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19247_dupName_277_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19252_dupName_277_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19250_dupName_277_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19252_dupName_277_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19257_dupName_277_i_unnamed_c_compstr0_shift_x(MUX,19256)@151
    assign rightShiftStage2_uid19257_dupName_277_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19257_dupName_277_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19252_dupName_277_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19255_dupName_277_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19257_dupName_277_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19257_dupName_277_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19252_dupName_277_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19257_dupName_277_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19255_dupName_277_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19257_dupName_277_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1969_vt_select_20(BITSELECT,10641)@151
    assign i_unnamed_c_compstr1969_vt_select_20_b = rightShiftStage2_uid19257_dupName_277_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1969_vt_join(BITJOIN,10640)@151
    assign i_unnamed_c_compstr1969_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1969_vt_select_20_b};

    // i_conv_i_i_i_i_i_69_c_compstr1970_sel_x(BITSELECT,3805)@151
    assign i_conv_i_i_i_i_i_69_c_compstr1970_sel_x_b = i_unnamed_c_compstr1969_vt_join_q[15:0];

    // redist1060_i_conv_i_i_i_i_i_69_c_compstr1970_sel_x_b_1(DELAY,29288)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1060_i_conv_i_i_i_i_i_69_c_compstr1970_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_69_c_compstr1970_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19266_dupName_278_i_unnamed_c_compstr0_shift_x(BITSELECT,19265)@151
    assign rightShiftStage1Idx1Rng8_uid19266_dupName_278_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19265_dupName_278_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19268_dupName_278_i_unnamed_c_compstr0_shift_x(BITJOIN,19267)@151
    assign rightShiftStage1Idx1_uid19268_dupName_278_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19266_dupName_278_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19261_dupName_278_i_unnamed_c_compstr0_shift_x(BITSELECT,19260)@151
    assign rightShiftStage0Idx1Rng4_uid19261_dupName_278_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_q[33:4];

    // rightShiftStage0Idx1_uid19263_dupName_278_i_unnamed_c_compstr0_shift_x(BITJOIN,19262)@151
    assign rightShiftStage0Idx1_uid19263_dupName_278_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19261_dupName_278_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19265_dupName_278_i_unnamed_c_compstr0_shift_x(MUX,19264)@151
    assign rightShiftStage0_uid19265_dupName_278_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19265_dupName_278_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_q or rightShiftStage0Idx1_uid19263_dupName_278_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19265_dupName_278_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19265_dupName_278_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compstr1968_q;
            1'b1 : rightShiftStage0_uid19265_dupName_278_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19263_dupName_278_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19265_dupName_278_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19270_dupName_278_i_unnamed_c_compstr0_shift_x(MUX,19269)@151
    assign rightShiftStage1_uid19270_dupName_278_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19270_dupName_278_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19265_dupName_278_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19268_dupName_278_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19270_dupName_278_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19270_dupName_278_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19265_dupName_278_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19270_dupName_278_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19268_dupName_278_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19270_dupName_278_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1971_vt_select_21(BITSELECT,10644)@151
    assign i_unnamed_c_compstr1971_vt_select_21_b = rightShiftStage1_uid19270_dupName_278_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1971_vt_join(BITJOIN,10643)@151
    assign i_unnamed_c_compstr1971_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1971_vt_select_21_b};

    // i_unnamed_c_compstr1972_sel_x(BITSELECT,6111)@151
    assign i_unnamed_c_compstr1972_sel_x_b = i_unnamed_c_compstr1971_vt_join_q[15:0];

    // i_unnamed_c_compstr1973_BitSelect_for_a(BITSELECT,27611)@151
    assign i_unnamed_c_compstr1973_BitSelect_for_a_b = i_unnamed_c_compstr1972_sel_x_b[0:0];

    // i_unnamed_c_compstr1973_join(BITJOIN,27612)@151
    assign i_unnamed_c_compstr1973_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1973_BitSelect_for_a_b};

    // i_unnamed_c_compstr1973_vt_select_0(BITSELECT,10649)@151
    assign i_unnamed_c_compstr1973_vt_select_0_b = i_unnamed_c_compstr1973_join_q[0:0];

    // redist179_i_unnamed_c_compstr1973_vt_select_0_b_1(DELAY,28407)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist179_i_unnamed_c_compstr1973_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1973_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1973_vt_join(BITJOIN,10648)@152
    assign i_unnamed_c_compstr1973_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist179_i_unnamed_c_compstr1973_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_69_c_compstr1974(ADD,7072)@152
    assign i_add_i_i_i_i_i_i_69_c_compstr1974_a = {1'b0, i_unnamed_c_compstr1973_vt_join_q};
    assign i_add_i_i_i_i_i_i_69_c_compstr1974_b = {1'b0, redist1060_i_conv_i_i_i_i_i_69_c_compstr1970_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_69_c_compstr1974_o = $unsigned(i_add_i_i_i_i_i_i_69_c_compstr1974_a) + $unsigned(i_add_i_i_i_i_i_i_69_c_compstr1974_b);
    assign i_add_i_i_i_i_i_i_69_c_compstr1974_q = i_add_i_i_i_i_i_i_69_c_compstr1974_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_69_c_compstr1974_sel_x(BITSELECT,2266)@152
    assign bgTrunc_i_add_i_i_i_i_i_i_69_c_compstr1974_sel_x_b = i_add_i_i_i_i_i_i_69_c_compstr1974_q[15:0];

    // i_conv_i_i_i_i_i_i279_70_c_compstr1994_sel_x(BITSELECT,3935)@152
    assign i_conv_i_i_i_i_i_i279_70_c_compstr1994_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_69_c_compstr1974_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_70_c_compstr1994_vt_select_15(BITSELECT,8257)@152
    assign i_conv_i_i_i_i_i_i279_70_c_compstr1994_vt_select_15_b = i_conv_i_i_i_i_i_i279_70_c_compstr1994_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_70_c_compstr1994_vt_join(BITJOIN,8256)@152
    assign i_conv_i_i_i_i_i_i279_70_c_compstr1994_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_70_c_compstr1994_vt_select_15_b};

    // leftShiftStage0_uid26852_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x(MUX,26851)@152
    assign leftShiftStage0_uid26852_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26852_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_70_c_compstr1994_vt_join_q or leftShiftStage0Idx1_uid26850_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26852_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26852_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_70_c_compstr1994_vt_join_q;
            1'b1 : leftShiftStage0_uid26852_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26850_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26852_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26857_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x(MUX,26856)@152
    assign leftShiftStage1_uid26857_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26857_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_s or leftShiftStage0_uid26852_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26855_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26857_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26857_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q = leftShiftStage0_uid26852_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26857_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26855_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26857_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26862_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x(MUX,26861)@152
    assign leftShiftStage2_uid26862_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26862_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_s or leftShiftStage1_uid26857_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26860_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26862_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26862_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q = leftShiftStage1_uid26857_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26862_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26860_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26862_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_70_c_compstr1995_vt_select_28(BITSELECT,9706)@152
    assign i_shl_i_i_i_i_i_i_70_c_compstr1995_vt_select_28_b = leftShiftStage2_uid26862_i_shl_i_i_i_i_i_i_70_c_compstr0_shift_x_q[28:13];

    // redist288_i_shl_i_i_i_i_i_i_70_c_compstr1995_vt_select_28_b_1(DELAY,28516)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist288_i_shl_i_i_i_i_i_i_70_c_compstr1995_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_70_c_compstr1995_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_70_c_compstr1995_vt_join(BITJOIN,9705)@153
    assign i_shl_i_i_i_i_i_i_70_c_compstr1995_vt_join_q = {redist288_i_shl_i_i_i_i_i_i_70_c_compstr1995_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_offset(CONSTANT,30378)
    assign redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_offset_q = $unsigned(8'b01111010);

    // redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_rdcnt(ADD,31827)
    assign redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_a = {1'b0, redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_wraddr_q};
    assign redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_b = {1'b0, redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_o <= $unsigned(redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_a) + $unsigned(redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_b);
        end
    end
    assign redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_q = redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_o[8:0];

    // redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_inputreg0(DELAY,31822)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl);
        end
    end

    // redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_wraddr(COUNTER,31825)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_wraddr_i <= $unsigned(redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_wraddr_q = redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_wraddr_i[7:0];

    // redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem(DUALMEM,31824)
    assign redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_ia = $unsigned(redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_inputreg0_q);
    assign redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_aa = redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_wraddr_q;
    assign redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_ab = redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_aa),
        .data_a(redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_ab),
        .q_b(redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_q = redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_iq[15:0];

    // redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_outputreg0(DELAY,31823)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_outputreg0_q <= $unsigned(redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_mem_q);
        end
    end

    // redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_rdcnt(ADD,30379)
    assign redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_a = {1'b0, redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_wraddr_q};
    assign redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_b = {1'b0, redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_o <= $unsigned(redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_a) + $unsigned(redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_b);
        end
    end
    assign redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_q = redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_o[8:0];

    // redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_inputreg0(DELAY,30374)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl);
        end
    end

    // redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_wraddr(COUNTER,30377)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_wraddr_i <= $unsigned(redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_wraddr_q = redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_wraddr_i[7:0];

    // redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem(DUALMEM,30376)
    assign redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_ia = $unsigned(redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_inputreg0_q);
    assign redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_aa = redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_wraddr_q;
    assign redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_ab = redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_aa),
        .data_a(redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_ab),
        .q_b(redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_q = redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_iq[15:0];

    // redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_outputreg0(DELAY,30375)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_outputreg0_q <= $unsigned(redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_mem_q);
        end
    end

    // redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_rdcnt(ADD,30385)
    assign redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_a = {1'b0, redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_wraddr_q};
    assign redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_b = {1'b0, redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_o <= $unsigned(redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_a) + $unsigned(redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_b);
        end
    end
    assign redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_q = redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_o[8:0];

    // redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_inputreg0(DELAY,30380)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl);
        end
    end

    // redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_wraddr(COUNTER,30383)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_wraddr_i <= $unsigned(redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_wraddr_q = redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_wraddr_i[7:0];

    // redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem(DUALMEM,30382)
    assign redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_ia = $unsigned(redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_inputreg0_q);
    assign redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_aa = redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_wraddr_q;
    assign redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_ab = redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_aa),
        .data_a(redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_ab),
        .q_b(redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_q = redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_iq[15:0];

    // redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_outputreg0(DELAY,30381)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_outputreg0_q <= $unsigned(redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_mem_q);
        end
    end

    // redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_rdcnt(ADD,31821)
    assign redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_a = {1'b0, redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_wraddr_q};
    assign redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_b = {1'b0, redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_o <= $unsigned(redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_a) + $unsigned(redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_b);
        end
    end
    assign redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_q = redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_o[8:0];

    // redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_inputreg0(DELAY,31816)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl);
        end
    end

    // redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_wraddr(COUNTER,31819)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_wraddr_i <= $unsigned(redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_wraddr_q = redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_wraddr_i[7:0];

    // redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem(DUALMEM,31818)
    assign redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_ia = $unsigned(redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_inputreg0_q);
    assign redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_aa = redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_wraddr_q;
    assign redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_ab = redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_aa),
        .data_a(redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_ab),
        .q_b(redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_q = redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_iq[15:0];

    // redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_outputreg0(DELAY,31817)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_outputreg0_q <= $unsigned(redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28029)@147 + 5
    // out q@153
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996(ADD,8616)@153
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod391_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_b = $unsigned({{5{i_shl_i_i_i_i_i_i_70_c_compstr1995_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_70_c_compstr1995_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_o[33:0];

    // rightShiftStage0_uid19309_dupName_281_i_unnamed_c_compstr0_shift_x(MUX,19308)@153
    assign rightShiftStage0_uid19309_dupName_281_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19309_dupName_281_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_q or rightShiftStage0Idx1_uid19307_dupName_281_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19309_dupName_281_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19309_dupName_281_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_q;
            1'b1 : rightShiftStage0_uid19309_dupName_281_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19307_dupName_281_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19309_dupName_281_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19314_dupName_281_i_unnamed_c_compstr0_shift_x(MUX,19313)@153
    assign rightShiftStage1_uid19314_dupName_281_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19314_dupName_281_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19309_dupName_281_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19312_dupName_281_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19314_dupName_281_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19314_dupName_281_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19309_dupName_281_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19314_dupName_281_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19312_dupName_281_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19314_dupName_281_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19319_dupName_281_i_unnamed_c_compstr0_shift_x(MUX,19318)@153
    assign rightShiftStage2_uid19319_dupName_281_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19319_dupName_281_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19314_dupName_281_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19317_dupName_281_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19319_dupName_281_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19319_dupName_281_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19314_dupName_281_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19319_dupName_281_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19317_dupName_281_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19319_dupName_281_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1997_vt_select_20(BITSELECT,10663)@153
    assign i_unnamed_c_compstr1997_vt_select_20_b = rightShiftStage2_uid19319_dupName_281_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1997_vt_join(BITJOIN,10662)@153
    assign i_unnamed_c_compstr1997_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1997_vt_select_20_b};

    // i_conv_i_i_i_i_i_70_c_compstr1998_sel_x(BITSELECT,3807)@153
    assign i_conv_i_i_i_i_i_70_c_compstr1998_sel_x_b = i_unnamed_c_compstr1997_vt_join_q[15:0];

    // redist1058_i_conv_i_i_i_i_i_70_c_compstr1998_sel_x_b_1(DELAY,29286)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1058_i_conv_i_i_i_i_i_70_c_compstr1998_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_70_c_compstr1998_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19328_dupName_282_i_unnamed_c_compstr0_shift_x(BITSELECT,19327)@153
    assign rightShiftStage1Idx1Rng8_uid19328_dupName_282_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19327_dupName_282_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19330_dupName_282_i_unnamed_c_compstr0_shift_x(BITJOIN,19329)@153
    assign rightShiftStage1Idx1_uid19330_dupName_282_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19328_dupName_282_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19323_dupName_282_i_unnamed_c_compstr0_shift_x(BITSELECT,19322)@153
    assign rightShiftStage0Idx1Rng4_uid19323_dupName_282_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_q[33:4];

    // rightShiftStage0Idx1_uid19325_dupName_282_i_unnamed_c_compstr0_shift_x(BITJOIN,19324)@153
    assign rightShiftStage0Idx1_uid19325_dupName_282_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19323_dupName_282_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19327_dupName_282_i_unnamed_c_compstr0_shift_x(MUX,19326)@153
    assign rightShiftStage0_uid19327_dupName_282_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19327_dupName_282_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_q or rightShiftStage0Idx1_uid19325_dupName_282_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19327_dupName_282_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19327_dupName_282_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compstr1996_q;
            1'b1 : rightShiftStage0_uid19327_dupName_282_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19325_dupName_282_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19327_dupName_282_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19332_dupName_282_i_unnamed_c_compstr0_shift_x(MUX,19331)@153
    assign rightShiftStage1_uid19332_dupName_282_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19332_dupName_282_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19327_dupName_282_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19330_dupName_282_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19332_dupName_282_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19332_dupName_282_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19327_dupName_282_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19332_dupName_282_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19330_dupName_282_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19332_dupName_282_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1999_vt_select_21(BITSELECT,10666)@153
    assign i_unnamed_c_compstr1999_vt_select_21_b = rightShiftStage1_uid19332_dupName_282_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1999_vt_join(BITJOIN,10665)@153
    assign i_unnamed_c_compstr1999_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1999_vt_select_21_b};

    // i_unnamed_c_compstr2000_sel_x(BITSELECT,6113)@153
    assign i_unnamed_c_compstr2000_sel_x_b = i_unnamed_c_compstr1999_vt_join_q[15:0];

    // i_unnamed_c_compstr2001_BitSelect_for_a(BITSELECT,27615)@153
    assign i_unnamed_c_compstr2001_BitSelect_for_a_b = i_unnamed_c_compstr2000_sel_x_b[0:0];

    // i_unnamed_c_compstr2001_join(BITJOIN,27616)@153
    assign i_unnamed_c_compstr2001_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2001_BitSelect_for_a_b};

    // i_unnamed_c_compstr2001_vt_select_0(BITSELECT,10671)@153
    assign i_unnamed_c_compstr2001_vt_select_0_b = i_unnamed_c_compstr2001_join_q[0:0];

    // redist177_i_unnamed_c_compstr2001_vt_select_0_b_1(DELAY,28405)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist177_i_unnamed_c_compstr2001_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2001_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2001_vt_join(BITJOIN,10670)@154
    assign i_unnamed_c_compstr2001_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist177_i_unnamed_c_compstr2001_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_70_c_compstr2002(ADD,7074)@154
    assign i_add_i_i_i_i_i_i_70_c_compstr2002_a = {1'b0, i_unnamed_c_compstr2001_vt_join_q};
    assign i_add_i_i_i_i_i_i_70_c_compstr2002_b = {1'b0, redist1058_i_conv_i_i_i_i_i_70_c_compstr1998_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_70_c_compstr2002_o = $unsigned(i_add_i_i_i_i_i_i_70_c_compstr2002_a) + $unsigned(i_add_i_i_i_i_i_i_70_c_compstr2002_b);
    assign i_add_i_i_i_i_i_i_70_c_compstr2002_q = i_add_i_i_i_i_i_i_70_c_compstr2002_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_70_c_compstr2002_sel_x(BITSELECT,2268)@154
    assign bgTrunc_i_add_i_i_i_i_i_i_70_c_compstr2002_sel_x_b = i_add_i_i_i_i_i_i_70_c_compstr2002_q[15:0];

    // i_conv_i_i_i_i_i_i279_71_c_compstr2022_sel_x(BITSELECT,3936)@154
    assign i_conv_i_i_i_i_i_i279_71_c_compstr2022_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_70_c_compstr2002_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_71_c_compstr2022_vt_select_15(BITSELECT,8261)@154
    assign i_conv_i_i_i_i_i_i279_71_c_compstr2022_vt_select_15_b = i_conv_i_i_i_i_i_i279_71_c_compstr2022_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_71_c_compstr2022_vt_join(BITJOIN,8260)@154
    assign i_conv_i_i_i_i_i_i279_71_c_compstr2022_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_71_c_compstr2022_vt_select_15_b};

    // leftShiftStage0_uid26870_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x(MUX,26869)@154
    assign leftShiftStage0_uid26870_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26870_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_71_c_compstr2022_vt_join_q or leftShiftStage0Idx1_uid26868_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26870_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26870_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_71_c_compstr2022_vt_join_q;
            1'b1 : leftShiftStage0_uid26870_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26868_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26870_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26875_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x(MUX,26874)@154
    assign leftShiftStage1_uid26875_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26875_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_s or leftShiftStage0_uid26870_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26873_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26875_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26875_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q = leftShiftStage0_uid26870_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26875_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26873_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26875_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26880_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x(MUX,26879)@154
    assign leftShiftStage2_uid26880_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26880_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_s or leftShiftStage1_uid26875_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26878_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26880_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26880_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q = leftShiftStage1_uid26875_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26880_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26878_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26880_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_71_c_compstr2023_vt_select_28(BITSELECT,9709)@154
    assign i_shl_i_i_i_i_i_i_71_c_compstr2023_vt_select_28_b = leftShiftStage2_uid26880_i_shl_i_i_i_i_i_i_71_c_compstr0_shift_x_q[28:13];

    // redist287_i_shl_i_i_i_i_i_i_71_c_compstr2023_vt_select_28_b_1(DELAY,28515)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist287_i_shl_i_i_i_i_i_i_71_c_compstr2023_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_71_c_compstr2023_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_71_c_compstr2023_vt_join(BITJOIN,9708)@155
    assign i_shl_i_i_i_i_i_i_71_c_compstr2023_vt_join_q = {redist287_i_shl_i_i_i_i_i_i_71_c_compstr2023_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_offset(CONSTANT,30390)
    assign redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_offset_q = $unsigned(8'b01111000);

    // redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_rdcnt(ADD,31839)
    assign redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_a = {1'b0, redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_wraddr_q};
    assign redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_b = {1'b0, redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_o <= $unsigned(redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_a) + $unsigned(redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_b);
        end
    end
    assign redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_q = redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_o[8:0];

    // redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_inputreg0(DELAY,31834)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl);
        end
    end

    // redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_wraddr(COUNTER,31837)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_wraddr_i <= $unsigned(redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_wraddr_q = redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_wraddr_i[7:0];

    // redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem(DUALMEM,31836)
    assign redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_ia = $unsigned(redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_inputreg0_q);
    assign redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_aa = redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_wraddr_q;
    assign redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_ab = redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_aa),
        .data_a(redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_ab),
        .q_b(redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_q = redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_iq[15:0];

    // redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_outputreg0(DELAY,31835)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_outputreg0_q <= $unsigned(redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_mem_q);
        end
    end

    // redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_rdcnt(ADD,30391)
    assign redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_a = {1'b0, redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_wraddr_q};
    assign redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_b = {1'b0, redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_o <= $unsigned(redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_a) + $unsigned(redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_b);
        end
    end
    assign redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_q = redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_o[8:0];

    // redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_inputreg0(DELAY,30386)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl);
        end
    end

    // redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_wraddr(COUNTER,30389)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_wraddr_i <= $unsigned(redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_wraddr_q = redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_wraddr_i[7:0];

    // redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem(DUALMEM,30388)
    assign redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_ia = $unsigned(redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_inputreg0_q);
    assign redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_aa = redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_wraddr_q;
    assign redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_ab = redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_aa),
        .data_a(redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_ab),
        .q_b(redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_q = redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_iq[15:0];

    // redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_outputreg0(DELAY,30387)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_outputreg0_q <= $unsigned(redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_mem_q);
        end
    end

    // redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_rdcnt(ADD,30397)
    assign redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_a = {1'b0, redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_wraddr_q};
    assign redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_b = {1'b0, redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_o <= $unsigned(redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_a) + $unsigned(redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_b);
        end
    end
    assign redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_q = redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_o[8:0];

    // redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_inputreg0(DELAY,30392)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl);
        end
    end

    // redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_wraddr(COUNTER,30395)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_wraddr_i <= $unsigned(redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_wraddr_q = redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_wraddr_i[7:0];

    // redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem(DUALMEM,30394)
    assign redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_ia = $unsigned(redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_inputreg0_q);
    assign redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_aa = redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_wraddr_q;
    assign redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_ab = redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_aa),
        .data_a(redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_ab),
        .q_b(redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_q = redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_iq[15:0];

    // redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_outputreg0(DELAY,30393)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_outputreg0_q <= $unsigned(redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_mem_q);
        end
    end

    // redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_rdcnt(ADD,31833)
    assign redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_a = {1'b0, redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_wraddr_q};
    assign redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_b = {1'b0, redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_o <= $unsigned(redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_a) + $unsigned(redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_b);
        end
    end
    assign redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_q = redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_o[8:0];

    // redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_inputreg0(DELAY,31828)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl);
        end
    end

    // redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_wraddr(COUNTER,31831)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_wraddr_i <= $unsigned(redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_wraddr_q = redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_wraddr_i[7:0];

    // redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem(DUALMEM,31830)
    assign redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_ia = $unsigned(redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_inputreg0_q);
    assign redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_aa = redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_wraddr_q;
    assign redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_ab = redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_aa),
        .data_a(redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_ab),
        .q_b(redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_q = redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_iq[15:0];

    // redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_outputreg0(DELAY,31829)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_outputreg0_q <= $unsigned(redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28030)@149 + 5
    // out q@155
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024(ADD,8617)@155
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod396_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_b = $unsigned({{5{i_shl_i_i_i_i_i_i_71_c_compstr2023_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_71_c_compstr2023_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_o[33:0];

    // rightShiftStage0_uid19371_dupName_285_i_unnamed_c_compstr0_shift_x(MUX,19370)@155
    assign rightShiftStage0_uid19371_dupName_285_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19371_dupName_285_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_q or rightShiftStage0Idx1_uid19369_dupName_285_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19371_dupName_285_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19371_dupName_285_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_q;
            1'b1 : rightShiftStage0_uid19371_dupName_285_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19369_dupName_285_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19371_dupName_285_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19376_dupName_285_i_unnamed_c_compstr0_shift_x(MUX,19375)@155
    assign rightShiftStage1_uid19376_dupName_285_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19376_dupName_285_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19371_dupName_285_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19374_dupName_285_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19376_dupName_285_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19376_dupName_285_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19371_dupName_285_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19376_dupName_285_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19374_dupName_285_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19376_dupName_285_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19381_dupName_285_i_unnamed_c_compstr0_shift_x(MUX,19380)@155
    assign rightShiftStage2_uid19381_dupName_285_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19381_dupName_285_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19376_dupName_285_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19379_dupName_285_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19381_dupName_285_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19381_dupName_285_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19376_dupName_285_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19381_dupName_285_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19379_dupName_285_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19381_dupName_285_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2025_vt_select_20(BITSELECT,10685)@155
    assign i_unnamed_c_compstr2025_vt_select_20_b = rightShiftStage2_uid19381_dupName_285_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2025_vt_join(BITJOIN,10684)@155
    assign i_unnamed_c_compstr2025_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2025_vt_select_20_b};

    // i_conv_i_i_i_i_i_71_c_compstr2026_sel_x(BITSELECT,3808)@155
    assign i_conv_i_i_i_i_i_71_c_compstr2026_sel_x_b = i_unnamed_c_compstr2025_vt_join_q[15:0];

    // redist1057_i_conv_i_i_i_i_i_71_c_compstr2026_sel_x_b_1(DELAY,29285)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1057_i_conv_i_i_i_i_i_71_c_compstr2026_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_71_c_compstr2026_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19390_dupName_286_i_unnamed_c_compstr0_shift_x(BITSELECT,19389)@155
    assign rightShiftStage1Idx1Rng8_uid19390_dupName_286_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19389_dupName_286_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19392_dupName_286_i_unnamed_c_compstr0_shift_x(BITJOIN,19391)@155
    assign rightShiftStage1Idx1_uid19392_dupName_286_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19390_dupName_286_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19385_dupName_286_i_unnamed_c_compstr0_shift_x(BITSELECT,19384)@155
    assign rightShiftStage0Idx1Rng4_uid19385_dupName_286_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_q[33:4];

    // rightShiftStage0Idx1_uid19387_dupName_286_i_unnamed_c_compstr0_shift_x(BITJOIN,19386)@155
    assign rightShiftStage0Idx1_uid19387_dupName_286_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19385_dupName_286_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19389_dupName_286_i_unnamed_c_compstr0_shift_x(MUX,19388)@155
    assign rightShiftStage0_uid19389_dupName_286_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19389_dupName_286_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_q or rightShiftStage0Idx1_uid19387_dupName_286_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19389_dupName_286_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19389_dupName_286_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compstr2024_q;
            1'b1 : rightShiftStage0_uid19389_dupName_286_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19387_dupName_286_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19389_dupName_286_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19394_dupName_286_i_unnamed_c_compstr0_shift_x(MUX,19393)@155
    assign rightShiftStage1_uid19394_dupName_286_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19394_dupName_286_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19389_dupName_286_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19392_dupName_286_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19394_dupName_286_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19394_dupName_286_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19389_dupName_286_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19394_dupName_286_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19392_dupName_286_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19394_dupName_286_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2027_vt_select_21(BITSELECT,10688)@155
    assign i_unnamed_c_compstr2027_vt_select_21_b = rightShiftStage1_uid19394_dupName_286_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2027_vt_join(BITJOIN,10687)@155
    assign i_unnamed_c_compstr2027_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2027_vt_select_21_b};

    // i_unnamed_c_compstr2028_sel_x(BITSELECT,6115)@155
    assign i_unnamed_c_compstr2028_sel_x_b = i_unnamed_c_compstr2027_vt_join_q[15:0];

    // i_unnamed_c_compstr2029_BitSelect_for_a(BITSELECT,27619)@155
    assign i_unnamed_c_compstr2029_BitSelect_for_a_b = i_unnamed_c_compstr2028_sel_x_b[0:0];

    // i_unnamed_c_compstr2029_join(BITJOIN,27620)@155
    assign i_unnamed_c_compstr2029_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2029_BitSelect_for_a_b};

    // i_unnamed_c_compstr2029_vt_select_0(BITSELECT,10693)@155
    assign i_unnamed_c_compstr2029_vt_select_0_b = i_unnamed_c_compstr2029_join_q[0:0];

    // redist175_i_unnamed_c_compstr2029_vt_select_0_b_1(DELAY,28403)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist175_i_unnamed_c_compstr2029_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2029_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2029_vt_join(BITJOIN,10692)@156
    assign i_unnamed_c_compstr2029_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist175_i_unnamed_c_compstr2029_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_71_c_compstr2030(ADD,7075)@156
    assign i_add_i_i_i_i_i_i_71_c_compstr2030_a = {1'b0, i_unnamed_c_compstr2029_vt_join_q};
    assign i_add_i_i_i_i_i_i_71_c_compstr2030_b = {1'b0, redist1057_i_conv_i_i_i_i_i_71_c_compstr2026_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_71_c_compstr2030_o = $unsigned(i_add_i_i_i_i_i_i_71_c_compstr2030_a) + $unsigned(i_add_i_i_i_i_i_i_71_c_compstr2030_b);
    assign i_add_i_i_i_i_i_i_71_c_compstr2030_q = i_add_i_i_i_i_i_i_71_c_compstr2030_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_71_c_compstr2030_sel_x(BITSELECT,2269)@156
    assign bgTrunc_i_add_i_i_i_i_i_i_71_c_compstr2030_sel_x_b = i_add_i_i_i_i_i_i_71_c_compstr2030_q[15:0];

    // i_conv_i_i_i_i_i_i279_72_c_compstr2050_sel_x(BITSELECT,3937)@156
    assign i_conv_i_i_i_i_i_i279_72_c_compstr2050_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_71_c_compstr2030_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_72_c_compstr2050_vt_select_15(BITSELECT,8265)@156
    assign i_conv_i_i_i_i_i_i279_72_c_compstr2050_vt_select_15_b = i_conv_i_i_i_i_i_i279_72_c_compstr2050_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_72_c_compstr2050_vt_join(BITJOIN,8264)@156
    assign i_conv_i_i_i_i_i_i279_72_c_compstr2050_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_72_c_compstr2050_vt_select_15_b};

    // leftShiftStage0_uid26888_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x(MUX,26887)@156
    assign leftShiftStage0_uid26888_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26888_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_72_c_compstr2050_vt_join_q or leftShiftStage0Idx1_uid26886_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26888_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26888_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_72_c_compstr2050_vt_join_q;
            1'b1 : leftShiftStage0_uid26888_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26886_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26888_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26893_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x(MUX,26892)@156
    assign leftShiftStage1_uid26893_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26893_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_s or leftShiftStage0_uid26888_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26891_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26893_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26893_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q = leftShiftStage0_uid26888_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26893_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26891_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26893_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26898_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x(MUX,26897)@156
    assign leftShiftStage2_uid26898_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26898_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_s or leftShiftStage1_uid26893_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26896_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26898_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26898_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q = leftShiftStage1_uid26893_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26898_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26896_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26898_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_72_c_compstr2051_vt_select_28(BITSELECT,9712)@156
    assign i_shl_i_i_i_i_i_i_72_c_compstr2051_vt_select_28_b = leftShiftStage2_uid26898_i_shl_i_i_i_i_i_i_72_c_compstr0_shift_x_q[28:13];

    // redist286_i_shl_i_i_i_i_i_i_72_c_compstr2051_vt_select_28_b_1(DELAY,28514)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist286_i_shl_i_i_i_i_i_i_72_c_compstr2051_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_72_c_compstr2051_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_72_c_compstr2051_vt_join(BITJOIN,9711)@157
    assign i_shl_i_i_i_i_i_i_72_c_compstr2051_vt_join_q = {redist286_i_shl_i_i_i_i_i_i_72_c_compstr2051_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_offset(CONSTANT,30402)
    assign redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_offset_q = $unsigned(8'b01110110);

    // redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_rdcnt(ADD,31851)
    assign redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_a = {1'b0, redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_wraddr_q};
    assign redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_b = {1'b0, redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_o <= $unsigned(redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_a) + $unsigned(redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_b);
        end
    end
    assign redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_q = redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_o[8:0];

    // redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_inputreg0(DELAY,31846)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl);
        end
    end

    // redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_wraddr(COUNTER,31849)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_wraddr_i <= $unsigned(redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_wraddr_q = redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_wraddr_i[7:0];

    // redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem(DUALMEM,31848)
    assign redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_ia = $unsigned(redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_inputreg0_q);
    assign redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_aa = redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_wraddr_q;
    assign redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_ab = redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_aa),
        .data_a(redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_ab),
        .q_b(redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_q = redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_iq[15:0];

    // redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_outputreg0(DELAY,31847)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_outputreg0_q <= $unsigned(redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_mem_q);
        end
    end

    // redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_rdcnt(ADD,30403)
    assign redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_a = {1'b0, redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_wraddr_q};
    assign redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_b = {1'b0, redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_o <= $unsigned(redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_a) + $unsigned(redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_b);
        end
    end
    assign redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_q = redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_o[8:0];

    // redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_inputreg0(DELAY,30398)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl);
        end
    end

    // redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_wraddr(COUNTER,30401)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_wraddr_i <= $unsigned(redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_wraddr_q = redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_wraddr_i[7:0];

    // redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem(DUALMEM,30400)
    assign redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_ia = $unsigned(redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_inputreg0_q);
    assign redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_aa = redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_wraddr_q;
    assign redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_ab = redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_aa),
        .data_a(redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_ab),
        .q_b(redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_q = redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_iq[15:0];

    // redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_outputreg0(DELAY,30399)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_outputreg0_q <= $unsigned(redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_mem_q);
        end
    end

    // redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_rdcnt(ADD,30409)
    assign redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_a = {1'b0, redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_wraddr_q};
    assign redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_b = {1'b0, redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_o <= $unsigned(redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_a) + $unsigned(redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_b);
        end
    end
    assign redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_q = redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_o[8:0];

    // redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_inputreg0(DELAY,30404)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl);
        end
    end

    // redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_wraddr(COUNTER,30407)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_wraddr_i <= $unsigned(redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_wraddr_q = redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_wraddr_i[7:0];

    // redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem(DUALMEM,30406)
    assign redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_ia = $unsigned(redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_inputreg0_q);
    assign redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_aa = redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_wraddr_q;
    assign redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_ab = redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_aa),
        .data_a(redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_ab),
        .q_b(redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_q = redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_iq[15:0];

    // redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_outputreg0(DELAY,30405)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_outputreg0_q <= $unsigned(redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_mem_q);
        end
    end

    // redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_rdcnt(ADD,31845)
    assign redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_a = {1'b0, redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_wraddr_q};
    assign redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_b = {1'b0, redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_o <= $unsigned(redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_a) + $unsigned(redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_b);
        end
    end
    assign redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_q = redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_o[8:0];

    // redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_inputreg0(DELAY,31840)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl);
        end
    end

    // redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_wraddr(COUNTER,31843)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_wraddr_i <= $unsigned(redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_wraddr_q = redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_wraddr_i[7:0];

    // redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem(DUALMEM,31842)
    assign redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_ia = $unsigned(redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_inputreg0_q);
    assign redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_aa = redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_wraddr_q;
    assign redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_ab = redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_aa),
        .data_a(redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_ab),
        .q_b(redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_q = redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_iq[15:0];

    // redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_outputreg0(DELAY,31841)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_outputreg0_q <= $unsigned(redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28031)@151 + 5
    // out q@157
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052(ADD,8618)@157
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod401_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_b = $unsigned({{5{i_shl_i_i_i_i_i_i_72_c_compstr2051_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_72_c_compstr2051_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_o[33:0];

    // rightShiftStage0_uid19433_dupName_289_i_unnamed_c_compstr0_shift_x(MUX,19432)@157
    assign rightShiftStage0_uid19433_dupName_289_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19433_dupName_289_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_q or rightShiftStage0Idx1_uid19431_dupName_289_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19433_dupName_289_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19433_dupName_289_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_q;
            1'b1 : rightShiftStage0_uid19433_dupName_289_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19431_dupName_289_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19433_dupName_289_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19438_dupName_289_i_unnamed_c_compstr0_shift_x(MUX,19437)@157
    assign rightShiftStage1_uid19438_dupName_289_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19438_dupName_289_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19433_dupName_289_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19436_dupName_289_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19438_dupName_289_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19438_dupName_289_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19433_dupName_289_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19438_dupName_289_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19436_dupName_289_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19438_dupName_289_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19443_dupName_289_i_unnamed_c_compstr0_shift_x(MUX,19442)@157
    assign rightShiftStage2_uid19443_dupName_289_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19443_dupName_289_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19438_dupName_289_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19441_dupName_289_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19443_dupName_289_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19443_dupName_289_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19438_dupName_289_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19443_dupName_289_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19441_dupName_289_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19443_dupName_289_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2053_vt_select_20(BITSELECT,10707)@157
    assign i_unnamed_c_compstr2053_vt_select_20_b = rightShiftStage2_uid19443_dupName_289_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2053_vt_join(BITJOIN,10706)@157
    assign i_unnamed_c_compstr2053_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2053_vt_select_20_b};

    // i_conv_i_i_i_i_i_72_c_compstr2054_sel_x(BITSELECT,3809)@157
    assign i_conv_i_i_i_i_i_72_c_compstr2054_sel_x_b = i_unnamed_c_compstr2053_vt_join_q[15:0];

    // redist1056_i_conv_i_i_i_i_i_72_c_compstr2054_sel_x_b_1(DELAY,29284)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1056_i_conv_i_i_i_i_i_72_c_compstr2054_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_72_c_compstr2054_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19452_dupName_290_i_unnamed_c_compstr0_shift_x(BITSELECT,19451)@157
    assign rightShiftStage1Idx1Rng8_uid19452_dupName_290_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19451_dupName_290_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19454_dupName_290_i_unnamed_c_compstr0_shift_x(BITJOIN,19453)@157
    assign rightShiftStage1Idx1_uid19454_dupName_290_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19452_dupName_290_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19447_dupName_290_i_unnamed_c_compstr0_shift_x(BITSELECT,19446)@157
    assign rightShiftStage0Idx1Rng4_uid19447_dupName_290_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_q[33:4];

    // rightShiftStage0Idx1_uid19449_dupName_290_i_unnamed_c_compstr0_shift_x(BITJOIN,19448)@157
    assign rightShiftStage0Idx1_uid19449_dupName_290_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19447_dupName_290_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19451_dupName_290_i_unnamed_c_compstr0_shift_x(MUX,19450)@157
    assign rightShiftStage0_uid19451_dupName_290_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19451_dupName_290_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_q or rightShiftStage0Idx1_uid19449_dupName_290_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19451_dupName_290_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19451_dupName_290_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compstr2052_q;
            1'b1 : rightShiftStage0_uid19451_dupName_290_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19449_dupName_290_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19451_dupName_290_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19456_dupName_290_i_unnamed_c_compstr0_shift_x(MUX,19455)@157
    assign rightShiftStage1_uid19456_dupName_290_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19456_dupName_290_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19451_dupName_290_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19454_dupName_290_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19456_dupName_290_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19456_dupName_290_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19451_dupName_290_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19456_dupName_290_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19454_dupName_290_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19456_dupName_290_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2055_vt_select_21(BITSELECT,10710)@157
    assign i_unnamed_c_compstr2055_vt_select_21_b = rightShiftStage1_uid19456_dupName_290_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2055_vt_join(BITJOIN,10709)@157
    assign i_unnamed_c_compstr2055_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2055_vt_select_21_b};

    // i_unnamed_c_compstr2056_sel_x(BITSELECT,6117)@157
    assign i_unnamed_c_compstr2056_sel_x_b = i_unnamed_c_compstr2055_vt_join_q[15:0];

    // i_unnamed_c_compstr2057_BitSelect_for_a(BITSELECT,27623)@157
    assign i_unnamed_c_compstr2057_BitSelect_for_a_b = i_unnamed_c_compstr2056_sel_x_b[0:0];

    // i_unnamed_c_compstr2057_join(BITJOIN,27624)@157
    assign i_unnamed_c_compstr2057_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2057_BitSelect_for_a_b};

    // i_unnamed_c_compstr2057_vt_select_0(BITSELECT,10715)@157
    assign i_unnamed_c_compstr2057_vt_select_0_b = i_unnamed_c_compstr2057_join_q[0:0];

    // redist173_i_unnamed_c_compstr2057_vt_select_0_b_1(DELAY,28401)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist173_i_unnamed_c_compstr2057_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2057_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2057_vt_join(BITJOIN,10714)@158
    assign i_unnamed_c_compstr2057_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist173_i_unnamed_c_compstr2057_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_72_c_compstr2058(ADD,7076)@158
    assign i_add_i_i_i_i_i_i_72_c_compstr2058_a = {1'b0, i_unnamed_c_compstr2057_vt_join_q};
    assign i_add_i_i_i_i_i_i_72_c_compstr2058_b = {1'b0, redist1056_i_conv_i_i_i_i_i_72_c_compstr2054_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_72_c_compstr2058_o = $unsigned(i_add_i_i_i_i_i_i_72_c_compstr2058_a) + $unsigned(i_add_i_i_i_i_i_i_72_c_compstr2058_b);
    assign i_add_i_i_i_i_i_i_72_c_compstr2058_q = i_add_i_i_i_i_i_i_72_c_compstr2058_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_72_c_compstr2058_sel_x(BITSELECT,2270)@158
    assign bgTrunc_i_add_i_i_i_i_i_i_72_c_compstr2058_sel_x_b = i_add_i_i_i_i_i_i_72_c_compstr2058_q[15:0];

    // i_conv_i_i_i_i_i_i279_73_c_compstr2078_sel_x(BITSELECT,3938)@158
    assign i_conv_i_i_i_i_i_i279_73_c_compstr2078_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_72_c_compstr2058_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_73_c_compstr2078_vt_select_15(BITSELECT,8269)@158
    assign i_conv_i_i_i_i_i_i279_73_c_compstr2078_vt_select_15_b = i_conv_i_i_i_i_i_i279_73_c_compstr2078_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_73_c_compstr2078_vt_join(BITJOIN,8268)@158
    assign i_conv_i_i_i_i_i_i279_73_c_compstr2078_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_73_c_compstr2078_vt_select_15_b};

    // leftShiftStage0_uid26906_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x(MUX,26905)@158
    assign leftShiftStage0_uid26906_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26906_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_73_c_compstr2078_vt_join_q or leftShiftStage0Idx1_uid26904_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26906_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26906_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_73_c_compstr2078_vt_join_q;
            1'b1 : leftShiftStage0_uid26906_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26904_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26906_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26911_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x(MUX,26910)@158
    assign leftShiftStage1_uid26911_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26911_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_s or leftShiftStage0_uid26906_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26909_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26911_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26911_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q = leftShiftStage0_uid26906_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26911_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26909_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26911_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26916_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x(MUX,26915)@158
    assign leftShiftStage2_uid26916_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26916_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_s or leftShiftStage1_uid26911_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26914_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26916_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26916_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q = leftShiftStage1_uid26911_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26916_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26914_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26916_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_73_c_compstr2079_vt_select_28(BITSELECT,9715)@158
    assign i_shl_i_i_i_i_i_i_73_c_compstr2079_vt_select_28_b = leftShiftStage2_uid26916_i_shl_i_i_i_i_i_i_73_c_compstr0_shift_x_q[28:13];

    // redist285_i_shl_i_i_i_i_i_i_73_c_compstr2079_vt_select_28_b_1(DELAY,28513)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist285_i_shl_i_i_i_i_i_i_73_c_compstr2079_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_73_c_compstr2079_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_73_c_compstr2079_vt_join(BITJOIN,9714)@159
    assign i_shl_i_i_i_i_i_i_73_c_compstr2079_vt_join_q = {redist285_i_shl_i_i_i_i_i_i_73_c_compstr2079_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_offset(CONSTANT,30414)
    assign redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_offset_q = $unsigned(8'b01110100);

    // redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_rdcnt(ADD,31863)
    assign redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_a = {1'b0, redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_wraddr_q};
    assign redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_b = {1'b0, redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_o <= $unsigned(redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_a) + $unsigned(redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_b);
        end
    end
    assign redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_q = redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_o[8:0];

    // redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_inputreg0(DELAY,31858)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl);
        end
    end

    // redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_wraddr(COUNTER,31861)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_wraddr_i <= $unsigned(redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_wraddr_q = redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_wraddr_i[7:0];

    // redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem(DUALMEM,31860)
    assign redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_ia = $unsigned(redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_inputreg0_q);
    assign redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_aa = redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_wraddr_q;
    assign redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_ab = redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_aa),
        .data_a(redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_ab),
        .q_b(redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_q = redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_iq[15:0];

    // redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_outputreg0(DELAY,31859)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_outputreg0_q <= $unsigned(redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_mem_q);
        end
    end

    // redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_rdcnt(ADD,30415)
    assign redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_a = {1'b0, redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_wraddr_q};
    assign redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_b = {1'b0, redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_o <= $unsigned(redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_a) + $unsigned(redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_b);
        end
    end
    assign redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_q = redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_o[8:0];

    // redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_inputreg0(DELAY,30410)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl);
        end
    end

    // redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_wraddr(COUNTER,30413)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_wraddr_i <= $unsigned(redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_wraddr_q = redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_wraddr_i[7:0];

    // redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem(DUALMEM,30412)
    assign redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_ia = $unsigned(redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_inputreg0_q);
    assign redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_aa = redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_wraddr_q;
    assign redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_ab = redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_aa),
        .data_a(redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_ab),
        .q_b(redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_q = redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_iq[15:0];

    // redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_outputreg0(DELAY,30411)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_outputreg0_q <= $unsigned(redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_mem_q);
        end
    end

    // redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_rdcnt(ADD,30421)
    assign redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_a = {1'b0, redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_wraddr_q};
    assign redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_b = {1'b0, redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_o <= $unsigned(redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_a) + $unsigned(redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_b);
        end
    end
    assign redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_q = redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_o[8:0];

    // redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_inputreg0(DELAY,30416)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl);
        end
    end

    // redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_wraddr(COUNTER,30419)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_wraddr_i <= $unsigned(redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_wraddr_q = redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_wraddr_i[7:0];

    // redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem(DUALMEM,30418)
    assign redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_ia = $unsigned(redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_inputreg0_q);
    assign redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_aa = redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_wraddr_q;
    assign redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_ab = redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_aa),
        .data_a(redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_ab),
        .q_b(redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_q = redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_iq[15:0];

    // redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_outputreg0(DELAY,30417)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_outputreg0_q <= $unsigned(redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_mem_q);
        end
    end

    // redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_rdcnt(ADD,31857)
    assign redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_a = {1'b0, redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_wraddr_q};
    assign redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_b = {1'b0, redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_o <= $unsigned(redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_a) + $unsigned(redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_b);
        end
    end
    assign redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_q = redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_o[8:0];

    // redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_inputreg0(DELAY,31852)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl);
        end
    end

    // redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_wraddr(COUNTER,31855)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_wraddr_i <= $unsigned(redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_wraddr_q = redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_wraddr_i[7:0];

    // redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem(DUALMEM,31854)
    assign redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_ia = $unsigned(redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_inputreg0_q);
    assign redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_aa = redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_wraddr_q;
    assign redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_ab = redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_aa),
        .data_a(redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_ab),
        .q_b(redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_q = redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_iq[15:0];

    // redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_outputreg0(DELAY,31853)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_outputreg0_q <= $unsigned(redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28032)@153 + 5
    // out q@159
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080(ADD,8619)@159
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod406_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_b = $unsigned({{5{i_shl_i_i_i_i_i_i_73_c_compstr2079_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_73_c_compstr2079_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_o[33:0];

    // rightShiftStage0_uid19495_dupName_293_i_unnamed_c_compstr0_shift_x(MUX,19494)@159
    assign rightShiftStage0_uid19495_dupName_293_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19495_dupName_293_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_q or rightShiftStage0Idx1_uid19493_dupName_293_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19495_dupName_293_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19495_dupName_293_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_q;
            1'b1 : rightShiftStage0_uid19495_dupName_293_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19493_dupName_293_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19495_dupName_293_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19500_dupName_293_i_unnamed_c_compstr0_shift_x(MUX,19499)@159
    assign rightShiftStage1_uid19500_dupName_293_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19500_dupName_293_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19495_dupName_293_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19498_dupName_293_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19500_dupName_293_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19500_dupName_293_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19495_dupName_293_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19500_dupName_293_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19498_dupName_293_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19500_dupName_293_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19505_dupName_293_i_unnamed_c_compstr0_shift_x(MUX,19504)@159
    assign rightShiftStage2_uid19505_dupName_293_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19505_dupName_293_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19500_dupName_293_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19503_dupName_293_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19505_dupName_293_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19505_dupName_293_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19500_dupName_293_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19505_dupName_293_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19503_dupName_293_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19505_dupName_293_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2081_vt_select_20(BITSELECT,10735)@159
    assign i_unnamed_c_compstr2081_vt_select_20_b = rightShiftStage2_uid19505_dupName_293_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2081_vt_join(BITJOIN,10734)@159
    assign i_unnamed_c_compstr2081_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2081_vt_select_20_b};

    // i_conv_i_i_i_i_i_73_c_compstr2082_sel_x(BITSELECT,3810)@159
    assign i_conv_i_i_i_i_i_73_c_compstr2082_sel_x_b = i_unnamed_c_compstr2081_vt_join_q[15:0];

    // redist1055_i_conv_i_i_i_i_i_73_c_compstr2082_sel_x_b_1(DELAY,29283)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1055_i_conv_i_i_i_i_i_73_c_compstr2082_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_73_c_compstr2082_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19514_dupName_294_i_unnamed_c_compstr0_shift_x(BITSELECT,19513)@159
    assign rightShiftStage1Idx1Rng8_uid19514_dupName_294_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19513_dupName_294_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19516_dupName_294_i_unnamed_c_compstr0_shift_x(BITJOIN,19515)@159
    assign rightShiftStage1Idx1_uid19516_dupName_294_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19514_dupName_294_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19509_dupName_294_i_unnamed_c_compstr0_shift_x(BITSELECT,19508)@159
    assign rightShiftStage0Idx1Rng4_uid19509_dupName_294_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_q[33:4];

    // rightShiftStage0Idx1_uid19511_dupName_294_i_unnamed_c_compstr0_shift_x(BITJOIN,19510)@159
    assign rightShiftStage0Idx1_uid19511_dupName_294_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19509_dupName_294_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19513_dupName_294_i_unnamed_c_compstr0_shift_x(MUX,19512)@159
    assign rightShiftStage0_uid19513_dupName_294_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19513_dupName_294_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_q or rightShiftStage0Idx1_uid19511_dupName_294_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19513_dupName_294_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19513_dupName_294_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compstr2080_q;
            1'b1 : rightShiftStage0_uid19513_dupName_294_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19511_dupName_294_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19513_dupName_294_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19518_dupName_294_i_unnamed_c_compstr0_shift_x(MUX,19517)@159
    assign rightShiftStage1_uid19518_dupName_294_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19518_dupName_294_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19513_dupName_294_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19516_dupName_294_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19518_dupName_294_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19518_dupName_294_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19513_dupName_294_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19518_dupName_294_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19516_dupName_294_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19518_dupName_294_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2083_vt_select_21(BITSELECT,10738)@159
    assign i_unnamed_c_compstr2083_vt_select_21_b = rightShiftStage1_uid19518_dupName_294_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2083_vt_join(BITJOIN,10737)@159
    assign i_unnamed_c_compstr2083_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2083_vt_select_21_b};

    // i_unnamed_c_compstr2084_sel_x(BITSELECT,6120)@159
    assign i_unnamed_c_compstr2084_sel_x_b = i_unnamed_c_compstr2083_vt_join_q[15:0];

    // i_unnamed_c_compstr2085_BitSelect_for_a(BITSELECT,27627)@159
    assign i_unnamed_c_compstr2085_BitSelect_for_a_b = i_unnamed_c_compstr2084_sel_x_b[0:0];

    // i_unnamed_c_compstr2085_join(BITJOIN,27628)@159
    assign i_unnamed_c_compstr2085_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2085_BitSelect_for_a_b};

    // i_unnamed_c_compstr2085_vt_select_0(BITSELECT,10743)@159
    assign i_unnamed_c_compstr2085_vt_select_0_b = i_unnamed_c_compstr2085_join_q[0:0];

    // redist171_i_unnamed_c_compstr2085_vt_select_0_b_1(DELAY,28399)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist171_i_unnamed_c_compstr2085_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2085_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2085_vt_join(BITJOIN,10742)@160
    assign i_unnamed_c_compstr2085_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist171_i_unnamed_c_compstr2085_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_73_c_compstr2086(ADD,7077)@160
    assign i_add_i_i_i_i_i_i_73_c_compstr2086_a = {1'b0, i_unnamed_c_compstr2085_vt_join_q};
    assign i_add_i_i_i_i_i_i_73_c_compstr2086_b = {1'b0, redist1055_i_conv_i_i_i_i_i_73_c_compstr2082_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_73_c_compstr2086_o = $unsigned(i_add_i_i_i_i_i_i_73_c_compstr2086_a) + $unsigned(i_add_i_i_i_i_i_i_73_c_compstr2086_b);
    assign i_add_i_i_i_i_i_i_73_c_compstr2086_q = i_add_i_i_i_i_i_i_73_c_compstr2086_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_73_c_compstr2086_sel_x(BITSELECT,2271)@160
    assign bgTrunc_i_add_i_i_i_i_i_i_73_c_compstr2086_sel_x_b = i_add_i_i_i_i_i_i_73_c_compstr2086_q[15:0];

    // i_conv_i_i_i_i_i_i279_74_c_compstr2106_sel_x(BITSELECT,3939)@160
    assign i_conv_i_i_i_i_i_i279_74_c_compstr2106_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_73_c_compstr2086_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_74_c_compstr2106_vt_select_15(BITSELECT,8273)@160
    assign i_conv_i_i_i_i_i_i279_74_c_compstr2106_vt_select_15_b = i_conv_i_i_i_i_i_i279_74_c_compstr2106_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_74_c_compstr2106_vt_join(BITJOIN,8272)@160
    assign i_conv_i_i_i_i_i_i279_74_c_compstr2106_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_74_c_compstr2106_vt_select_15_b};

    // leftShiftStage0_uid26924_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x(MUX,26923)@160
    assign leftShiftStage0_uid26924_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26924_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_74_c_compstr2106_vt_join_q or leftShiftStage0Idx1_uid26922_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26924_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26924_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_74_c_compstr2106_vt_join_q;
            1'b1 : leftShiftStage0_uid26924_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26922_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26924_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26929_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x(MUX,26928)@160
    assign leftShiftStage1_uid26929_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26929_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_s or leftShiftStage0_uid26924_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26927_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26929_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26929_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q = leftShiftStage0_uid26924_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26929_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26927_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26929_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26934_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x(MUX,26933)@160
    assign leftShiftStage2_uid26934_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26934_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_s or leftShiftStage1_uid26929_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26932_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26934_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26934_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q = leftShiftStage1_uid26929_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26934_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26932_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26934_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_74_c_compstr2107_vt_select_28(BITSELECT,9718)@160
    assign i_shl_i_i_i_i_i_i_74_c_compstr2107_vt_select_28_b = leftShiftStage2_uid26934_i_shl_i_i_i_i_i_i_74_c_compstr0_shift_x_q[28:13];

    // redist284_i_shl_i_i_i_i_i_i_74_c_compstr2107_vt_select_28_b_1(DELAY,28512)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist284_i_shl_i_i_i_i_i_i_74_c_compstr2107_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_74_c_compstr2107_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_74_c_compstr2107_vt_join(BITJOIN,9717)@161
    assign i_shl_i_i_i_i_i_i_74_c_compstr2107_vt_join_q = {redist284_i_shl_i_i_i_i_i_i_74_c_compstr2107_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_offset(CONSTANT,30426)
    assign redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_offset_q = $unsigned(8'b01110010);

    // redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_rdcnt(ADD,31875)
    assign redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_a = {1'b0, redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_wraddr_q};
    assign redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_b = {1'b0, redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_o <= $unsigned(redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_a) + $unsigned(redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_b);
        end
    end
    assign redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_q = redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_o[8:0];

    // redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_inputreg0(DELAY,31870)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl);
        end
    end

    // redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_wraddr(COUNTER,31873)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_wraddr_i <= $unsigned(redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_wraddr_q = redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_wraddr_i[7:0];

    // redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem(DUALMEM,31872)
    assign redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_ia = $unsigned(redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_inputreg0_q);
    assign redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_aa = redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_wraddr_q;
    assign redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_ab = redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_aa),
        .data_a(redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_ab),
        .q_b(redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_q = redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_iq[15:0];

    // redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_outputreg0(DELAY,31871)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_outputreg0_q <= $unsigned(redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_mem_q);
        end
    end

    // redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_rdcnt(ADD,30427)
    assign redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_a = {1'b0, redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_wraddr_q};
    assign redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_b = {1'b0, redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_o <= $unsigned(redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_a) + $unsigned(redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_b);
        end
    end
    assign redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_q = redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_o[8:0];

    // redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_inputreg0(DELAY,30422)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl);
        end
    end

    // redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_wraddr(COUNTER,30425)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_wraddr_i <= $unsigned(redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_wraddr_q = redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_wraddr_i[7:0];

    // redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem(DUALMEM,30424)
    assign redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_ia = $unsigned(redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_inputreg0_q);
    assign redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_aa = redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_wraddr_q;
    assign redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_ab = redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_aa),
        .data_a(redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_ab),
        .q_b(redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_q = redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_iq[15:0];

    // redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_outputreg0(DELAY,30423)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_outputreg0_q <= $unsigned(redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_mem_q);
        end
    end

    // redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_rdcnt(ADD,30433)
    assign redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_a = {1'b0, redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_wraddr_q};
    assign redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_b = {1'b0, redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_o <= $unsigned(redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_a) + $unsigned(redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_b);
        end
    end
    assign redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_q = redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_o[8:0];

    // redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_inputreg0(DELAY,30428)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl);
        end
    end

    // redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_wraddr(COUNTER,30431)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_wraddr_i <= $unsigned(redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_wraddr_q = redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_wraddr_i[7:0];

    // redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem(DUALMEM,30430)
    assign redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_ia = $unsigned(redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_inputreg0_q);
    assign redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_aa = redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_wraddr_q;
    assign redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_ab = redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_aa),
        .data_a(redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_ab),
        .q_b(redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_q = redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_iq[15:0];

    // redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_outputreg0(DELAY,30429)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_outputreg0_q <= $unsigned(redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_mem_q);
        end
    end

    // redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_rdcnt(ADD,31869)
    assign redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_a = {1'b0, redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_wraddr_q};
    assign redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_b = {1'b0, redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_o <= $unsigned(redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_a) + $unsigned(redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_b);
        end
    end
    assign redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_q = redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_o[8:0];

    // redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_inputreg0(DELAY,31864)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl);
        end
    end

    // redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_wraddr(COUNTER,31867)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_wraddr_i <= $unsigned(redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_wraddr_q = redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_wraddr_i[7:0];

    // redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem(DUALMEM,31866)
    assign redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_ia = $unsigned(redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_inputreg0_q);
    assign redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_aa = redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_wraddr_q;
    assign redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_ab = redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_aa),
        .data_a(redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_ab),
        .q_b(redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_q = redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_iq[15:0];

    // redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_outputreg0(DELAY,31865)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_outputreg0_q <= $unsigned(redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28033)@155 + 5
    // out q@161
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108(ADD,8620)@161
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod411_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_b = $unsigned({{5{i_shl_i_i_i_i_i_i_74_c_compstr2107_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_74_c_compstr2107_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_o[33:0];

    // rightShiftStage0_uid19557_dupName_297_i_unnamed_c_compstr0_shift_x(MUX,19556)@161
    assign rightShiftStage0_uid19557_dupName_297_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19557_dupName_297_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_q or rightShiftStage0Idx1_uid19555_dupName_297_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19557_dupName_297_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19557_dupName_297_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_q;
            1'b1 : rightShiftStage0_uid19557_dupName_297_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19555_dupName_297_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19557_dupName_297_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19562_dupName_297_i_unnamed_c_compstr0_shift_x(MUX,19561)@161
    assign rightShiftStage1_uid19562_dupName_297_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19562_dupName_297_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19557_dupName_297_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19560_dupName_297_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19562_dupName_297_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19562_dupName_297_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19557_dupName_297_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19562_dupName_297_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19560_dupName_297_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19562_dupName_297_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19567_dupName_297_i_unnamed_c_compstr0_shift_x(MUX,19566)@161
    assign rightShiftStage2_uid19567_dupName_297_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19567_dupName_297_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19562_dupName_297_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19565_dupName_297_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19567_dupName_297_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19567_dupName_297_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19562_dupName_297_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19567_dupName_297_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19565_dupName_297_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19567_dupName_297_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2109_vt_select_20(BITSELECT,10762)@161
    assign i_unnamed_c_compstr2109_vt_select_20_b = rightShiftStage2_uid19567_dupName_297_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2109_vt_join(BITJOIN,10761)@161
    assign i_unnamed_c_compstr2109_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2109_vt_select_20_b};

    // i_conv_i_i_i_i_i_74_c_compstr2110_sel_x(BITSELECT,3811)@161
    assign i_conv_i_i_i_i_i_74_c_compstr2110_sel_x_b = i_unnamed_c_compstr2109_vt_join_q[15:0];

    // redist1054_i_conv_i_i_i_i_i_74_c_compstr2110_sel_x_b_1(DELAY,29282)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1054_i_conv_i_i_i_i_i_74_c_compstr2110_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_74_c_compstr2110_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19576_dupName_298_i_unnamed_c_compstr0_shift_x(BITSELECT,19575)@161
    assign rightShiftStage1Idx1Rng8_uid19576_dupName_298_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19575_dupName_298_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19578_dupName_298_i_unnamed_c_compstr0_shift_x(BITJOIN,19577)@161
    assign rightShiftStage1Idx1_uid19578_dupName_298_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19576_dupName_298_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19571_dupName_298_i_unnamed_c_compstr0_shift_x(BITSELECT,19570)@161
    assign rightShiftStage0Idx1Rng4_uid19571_dupName_298_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_q[33:4];

    // rightShiftStage0Idx1_uid19573_dupName_298_i_unnamed_c_compstr0_shift_x(BITJOIN,19572)@161
    assign rightShiftStage0Idx1_uid19573_dupName_298_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19571_dupName_298_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19575_dupName_298_i_unnamed_c_compstr0_shift_x(MUX,19574)@161
    assign rightShiftStage0_uid19575_dupName_298_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19575_dupName_298_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_q or rightShiftStage0Idx1_uid19573_dupName_298_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19575_dupName_298_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19575_dupName_298_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compstr2108_q;
            1'b1 : rightShiftStage0_uid19575_dupName_298_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19573_dupName_298_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19575_dupName_298_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19580_dupName_298_i_unnamed_c_compstr0_shift_x(MUX,19579)@161
    assign rightShiftStage1_uid19580_dupName_298_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19580_dupName_298_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19575_dupName_298_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19578_dupName_298_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19580_dupName_298_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19580_dupName_298_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19575_dupName_298_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19580_dupName_298_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19578_dupName_298_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19580_dupName_298_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2111_vt_select_21(BITSELECT,10765)@161
    assign i_unnamed_c_compstr2111_vt_select_21_b = rightShiftStage1_uid19580_dupName_298_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2111_vt_join(BITJOIN,10764)@161
    assign i_unnamed_c_compstr2111_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2111_vt_select_21_b};

    // i_unnamed_c_compstr2112_sel_x(BITSELECT,6122)@161
    assign i_unnamed_c_compstr2112_sel_x_b = i_unnamed_c_compstr2111_vt_join_q[15:0];

    // i_unnamed_c_compstr2113_BitSelect_for_a(BITSELECT,27633)@161
    assign i_unnamed_c_compstr2113_BitSelect_for_a_b = i_unnamed_c_compstr2112_sel_x_b[0:0];

    // i_unnamed_c_compstr2113_join(BITJOIN,27634)@161
    assign i_unnamed_c_compstr2113_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2113_BitSelect_for_a_b};

    // i_unnamed_c_compstr2113_vt_select_0(BITSELECT,10770)@161
    assign i_unnamed_c_compstr2113_vt_select_0_b = i_unnamed_c_compstr2113_join_q[0:0];

    // redist168_i_unnamed_c_compstr2113_vt_select_0_b_1(DELAY,28396)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist168_i_unnamed_c_compstr2113_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2113_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2113_vt_join(BITJOIN,10769)@162
    assign i_unnamed_c_compstr2113_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist168_i_unnamed_c_compstr2113_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_74_c_compstr2114(ADD,7078)@162
    assign i_add_i_i_i_i_i_i_74_c_compstr2114_a = {1'b0, i_unnamed_c_compstr2113_vt_join_q};
    assign i_add_i_i_i_i_i_i_74_c_compstr2114_b = {1'b0, redist1054_i_conv_i_i_i_i_i_74_c_compstr2110_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_74_c_compstr2114_o = $unsigned(i_add_i_i_i_i_i_i_74_c_compstr2114_a) + $unsigned(i_add_i_i_i_i_i_i_74_c_compstr2114_b);
    assign i_add_i_i_i_i_i_i_74_c_compstr2114_q = i_add_i_i_i_i_i_i_74_c_compstr2114_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_74_c_compstr2114_sel_x(BITSELECT,2272)@162
    assign bgTrunc_i_add_i_i_i_i_i_i_74_c_compstr2114_sel_x_b = i_add_i_i_i_i_i_i_74_c_compstr2114_q[15:0];

    // i_conv_i_i_i_i_i_i279_75_c_compstr2134_sel_x(BITSELECT,3940)@162
    assign i_conv_i_i_i_i_i_i279_75_c_compstr2134_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_74_c_compstr2114_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_75_c_compstr2134_vt_select_15(BITSELECT,8277)@162
    assign i_conv_i_i_i_i_i_i279_75_c_compstr2134_vt_select_15_b = i_conv_i_i_i_i_i_i279_75_c_compstr2134_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_75_c_compstr2134_vt_join(BITJOIN,8276)@162
    assign i_conv_i_i_i_i_i_i279_75_c_compstr2134_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_75_c_compstr2134_vt_select_15_b};

    // leftShiftStage0_uid26942_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x(MUX,26941)@162
    assign leftShiftStage0_uid26942_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26942_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_75_c_compstr2134_vt_join_q or leftShiftStage0Idx1_uid26940_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26942_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26942_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_75_c_compstr2134_vt_join_q;
            1'b1 : leftShiftStage0_uid26942_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26940_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26942_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26947_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x(MUX,26946)@162
    assign leftShiftStage1_uid26947_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26947_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_s or leftShiftStage0_uid26942_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26945_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26947_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26947_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q = leftShiftStage0_uid26942_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26947_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26945_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26947_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26952_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x(MUX,26951)@162
    assign leftShiftStage2_uid26952_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26952_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_s or leftShiftStage1_uid26947_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26950_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26952_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26952_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q = leftShiftStage1_uid26947_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26952_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26950_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26952_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_75_c_compstr2135_vt_select_28(BITSELECT,9721)@162
    assign i_shl_i_i_i_i_i_i_75_c_compstr2135_vt_select_28_b = leftShiftStage2_uid26952_i_shl_i_i_i_i_i_i_75_c_compstr0_shift_x_q[28:13];

    // redist283_i_shl_i_i_i_i_i_i_75_c_compstr2135_vt_select_28_b_1(DELAY,28511)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist283_i_shl_i_i_i_i_i_i_75_c_compstr2135_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_75_c_compstr2135_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_75_c_compstr2135_vt_join(BITJOIN,9720)@163
    assign i_shl_i_i_i_i_i_i_75_c_compstr2135_vt_join_q = {redist283_i_shl_i_i_i_i_i_i_75_c_compstr2135_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_offset(CONSTANT,30438)
    assign redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_offset_q = $unsigned(8'b01110000);

    // redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_rdcnt(ADD,31887)
    assign redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_a = {1'b0, redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_wraddr_q};
    assign redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_b = {1'b0, redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_o <= $unsigned(redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_a) + $unsigned(redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_b);
        end
    end
    assign redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_q = redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_o[8:0];

    // redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_inputreg0(DELAY,31882)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl);
        end
    end

    // redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_wraddr(COUNTER,31885)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_wraddr_i <= $unsigned(redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_wraddr_q = redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_wraddr_i[7:0];

    // redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem(DUALMEM,31884)
    assign redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_ia = $unsigned(redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_inputreg0_q);
    assign redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_aa = redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_wraddr_q;
    assign redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_ab = redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_aa),
        .data_a(redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_ab),
        .q_b(redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_q = redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_iq[15:0];

    // redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_outputreg0(DELAY,31883)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_outputreg0_q <= $unsigned(redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_mem_q);
        end
    end

    // redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_rdcnt(ADD,30439)
    assign redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_a = {1'b0, redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_wraddr_q};
    assign redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_b = {1'b0, redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_o <= $unsigned(redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_a) + $unsigned(redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_b);
        end
    end
    assign redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_q = redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_o[8:0];

    // redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_inputreg0(DELAY,30434)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl);
        end
    end

    // redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_wraddr(COUNTER,30437)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_wraddr_i <= $unsigned(redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_wraddr_q = redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_wraddr_i[7:0];

    // redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem(DUALMEM,30436)
    assign redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_ia = $unsigned(redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_inputreg0_q);
    assign redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_aa = redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_wraddr_q;
    assign redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_ab = redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_aa),
        .data_a(redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_ab),
        .q_b(redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_q = redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_iq[15:0];

    // redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_outputreg0(DELAY,30435)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_outputreg0_q <= $unsigned(redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_mem_q);
        end
    end

    // redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_rdcnt(ADD,30445)
    assign redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_a = {1'b0, redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_wraddr_q};
    assign redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_b = {1'b0, redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_o <= $unsigned(redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_a) + $unsigned(redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_b);
        end
    end
    assign redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_q = redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_o[8:0];

    // redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_inputreg0(DELAY,30440)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl);
        end
    end

    // redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_wraddr(COUNTER,30443)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_wraddr_i <= $unsigned(redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_wraddr_q = redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_wraddr_i[7:0];

    // redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem(DUALMEM,30442)
    assign redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_ia = $unsigned(redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_inputreg0_q);
    assign redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_aa = redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_wraddr_q;
    assign redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_ab = redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_aa),
        .data_a(redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_ab),
        .q_b(redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_q = redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_iq[15:0];

    // redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_outputreg0(DELAY,30441)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_outputreg0_q <= $unsigned(redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_mem_q);
        end
    end

    // redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_rdcnt(ADD,31881)
    assign redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_a = {1'b0, redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_wraddr_q};
    assign redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_b = {1'b0, redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_o <= $unsigned(redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_a) + $unsigned(redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_b);
        end
    end
    assign redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_q = redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_o[8:0];

    // redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_inputreg0(DELAY,31876)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl);
        end
    end

    // redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_wraddr(COUNTER,31879)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_wraddr_i <= $unsigned(redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_wraddr_q = redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_wraddr_i[7:0];

    // redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem(DUALMEM,31878)
    assign redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_ia = $unsigned(redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_inputreg0_q);
    assign redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_aa = redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_wraddr_q;
    assign redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_ab = redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_aa),
        .data_a(redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_ab),
        .q_b(redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_q = redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_iq[15:0];

    // redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_outputreg0(DELAY,31877)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_outputreg0_q <= $unsigned(redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28034)@157 + 5
    // out q@163
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136(ADD,8621)@163
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod416_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_b = $unsigned({{5{i_shl_i_i_i_i_i_i_75_c_compstr2135_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_75_c_compstr2135_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_o[33:0];

    // rightShiftStage0_uid19619_dupName_301_i_unnamed_c_compstr0_shift_x(MUX,19618)@163
    assign rightShiftStage0_uid19619_dupName_301_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19619_dupName_301_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_q or rightShiftStage0Idx1_uid19617_dupName_301_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19619_dupName_301_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19619_dupName_301_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_q;
            1'b1 : rightShiftStage0_uid19619_dupName_301_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19617_dupName_301_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19619_dupName_301_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19624_dupName_301_i_unnamed_c_compstr0_shift_x(MUX,19623)@163
    assign rightShiftStage1_uid19624_dupName_301_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19624_dupName_301_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19619_dupName_301_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19622_dupName_301_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19624_dupName_301_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19624_dupName_301_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19619_dupName_301_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19624_dupName_301_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19622_dupName_301_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19624_dupName_301_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19629_dupName_301_i_unnamed_c_compstr0_shift_x(MUX,19628)@163
    assign rightShiftStage2_uid19629_dupName_301_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19629_dupName_301_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19624_dupName_301_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19627_dupName_301_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19629_dupName_301_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19629_dupName_301_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19624_dupName_301_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19629_dupName_301_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19627_dupName_301_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19629_dupName_301_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2137_vt_select_20(BITSELECT,10784)@163
    assign i_unnamed_c_compstr2137_vt_select_20_b = rightShiftStage2_uid19629_dupName_301_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2137_vt_join(BITJOIN,10783)@163
    assign i_unnamed_c_compstr2137_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2137_vt_select_20_b};

    // i_conv_i_i_i_i_i_75_c_compstr2138_sel_x(BITSELECT,3812)@163
    assign i_conv_i_i_i_i_i_75_c_compstr2138_sel_x_b = i_unnamed_c_compstr2137_vt_join_q[15:0];

    // redist1053_i_conv_i_i_i_i_i_75_c_compstr2138_sel_x_b_1(DELAY,29281)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1053_i_conv_i_i_i_i_i_75_c_compstr2138_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_75_c_compstr2138_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19638_dupName_302_i_unnamed_c_compstr0_shift_x(BITSELECT,19637)@163
    assign rightShiftStage1Idx1Rng8_uid19638_dupName_302_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19637_dupName_302_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19640_dupName_302_i_unnamed_c_compstr0_shift_x(BITJOIN,19639)@163
    assign rightShiftStage1Idx1_uid19640_dupName_302_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19638_dupName_302_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19633_dupName_302_i_unnamed_c_compstr0_shift_x(BITSELECT,19632)@163
    assign rightShiftStage0Idx1Rng4_uid19633_dupName_302_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_q[33:4];

    // rightShiftStage0Idx1_uid19635_dupName_302_i_unnamed_c_compstr0_shift_x(BITJOIN,19634)@163
    assign rightShiftStage0Idx1_uid19635_dupName_302_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19633_dupName_302_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19637_dupName_302_i_unnamed_c_compstr0_shift_x(MUX,19636)@163
    assign rightShiftStage0_uid19637_dupName_302_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19637_dupName_302_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_q or rightShiftStage0Idx1_uid19635_dupName_302_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19637_dupName_302_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19637_dupName_302_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compstr2136_q;
            1'b1 : rightShiftStage0_uid19637_dupName_302_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19635_dupName_302_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19637_dupName_302_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19642_dupName_302_i_unnamed_c_compstr0_shift_x(MUX,19641)@163
    assign rightShiftStage1_uid19642_dupName_302_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19642_dupName_302_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19637_dupName_302_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19640_dupName_302_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19642_dupName_302_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19642_dupName_302_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19637_dupName_302_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19642_dupName_302_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19640_dupName_302_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19642_dupName_302_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2139_vt_select_21(BITSELECT,10787)@163
    assign i_unnamed_c_compstr2139_vt_select_21_b = rightShiftStage1_uid19642_dupName_302_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2139_vt_join(BITJOIN,10786)@163
    assign i_unnamed_c_compstr2139_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2139_vt_select_21_b};

    // i_unnamed_c_compstr2140_sel_x(BITSELECT,6124)@163
    assign i_unnamed_c_compstr2140_sel_x_b = i_unnamed_c_compstr2139_vt_join_q[15:0];

    // i_unnamed_c_compstr2141_BitSelect_for_a(BITSELECT,27637)@163
    assign i_unnamed_c_compstr2141_BitSelect_for_a_b = i_unnamed_c_compstr2140_sel_x_b[0:0];

    // i_unnamed_c_compstr2141_join(BITJOIN,27638)@163
    assign i_unnamed_c_compstr2141_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2141_BitSelect_for_a_b};

    // i_unnamed_c_compstr2141_vt_select_0(BITSELECT,10792)@163
    assign i_unnamed_c_compstr2141_vt_select_0_b = i_unnamed_c_compstr2141_join_q[0:0];

    // redist166_i_unnamed_c_compstr2141_vt_select_0_b_1(DELAY,28394)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist166_i_unnamed_c_compstr2141_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2141_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2141_vt_join(BITJOIN,10791)@164
    assign i_unnamed_c_compstr2141_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist166_i_unnamed_c_compstr2141_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_75_c_compstr2142(ADD,7079)@164
    assign i_add_i_i_i_i_i_i_75_c_compstr2142_a = {1'b0, i_unnamed_c_compstr2141_vt_join_q};
    assign i_add_i_i_i_i_i_i_75_c_compstr2142_b = {1'b0, redist1053_i_conv_i_i_i_i_i_75_c_compstr2138_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_75_c_compstr2142_o = $unsigned(i_add_i_i_i_i_i_i_75_c_compstr2142_a) + $unsigned(i_add_i_i_i_i_i_i_75_c_compstr2142_b);
    assign i_add_i_i_i_i_i_i_75_c_compstr2142_q = i_add_i_i_i_i_i_i_75_c_compstr2142_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_75_c_compstr2142_sel_x(BITSELECT,2273)@164
    assign bgTrunc_i_add_i_i_i_i_i_i_75_c_compstr2142_sel_x_b = i_add_i_i_i_i_i_i_75_c_compstr2142_q[15:0];

    // i_conv_i_i_i_i_i_i279_76_c_compstr2162_sel_x(BITSELECT,3941)@164
    assign i_conv_i_i_i_i_i_i279_76_c_compstr2162_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_75_c_compstr2142_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_76_c_compstr2162_vt_select_15(BITSELECT,8281)@164
    assign i_conv_i_i_i_i_i_i279_76_c_compstr2162_vt_select_15_b = i_conv_i_i_i_i_i_i279_76_c_compstr2162_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_76_c_compstr2162_vt_join(BITJOIN,8280)@164
    assign i_conv_i_i_i_i_i_i279_76_c_compstr2162_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_76_c_compstr2162_vt_select_15_b};

    // leftShiftStage0_uid26960_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x(MUX,26959)@164
    assign leftShiftStage0_uid26960_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26960_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_76_c_compstr2162_vt_join_q or leftShiftStage0Idx1_uid26958_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26960_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26960_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_76_c_compstr2162_vt_join_q;
            1'b1 : leftShiftStage0_uid26960_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26958_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26960_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26965_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x(MUX,26964)@164
    assign leftShiftStage1_uid26965_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26965_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_s or leftShiftStage0_uid26960_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26963_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26965_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26965_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q = leftShiftStage0_uid26960_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26965_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26963_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26965_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26970_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x(MUX,26969)@164
    assign leftShiftStage2_uid26970_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26970_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_s or leftShiftStage1_uid26965_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26968_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26970_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26970_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q = leftShiftStage1_uid26965_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26970_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26968_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26970_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_76_c_compstr2163_vt_select_28(BITSELECT,9724)@164
    assign i_shl_i_i_i_i_i_i_76_c_compstr2163_vt_select_28_b = leftShiftStage2_uid26970_i_shl_i_i_i_i_i_i_76_c_compstr0_shift_x_q[28:13];

    // redist282_i_shl_i_i_i_i_i_i_76_c_compstr2163_vt_select_28_b_1(DELAY,28510)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist282_i_shl_i_i_i_i_i_i_76_c_compstr2163_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_76_c_compstr2163_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_76_c_compstr2163_vt_join(BITJOIN,9723)@165
    assign i_shl_i_i_i_i_i_i_76_c_compstr2163_vt_join_q = {redist282_i_shl_i_i_i_i_i_i_76_c_compstr2163_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_offset(CONSTANT,30450)
    assign redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_offset_q = $unsigned(8'b01101110);

    // redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_rdcnt(ADD,31899)
    assign redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_a = {1'b0, redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_wraddr_q};
    assign redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_b = {1'b0, redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_o <= $unsigned(redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_a) + $unsigned(redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_b);
        end
    end
    assign redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_q = redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_o[8:0];

    // redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_inputreg0(DELAY,31894)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl);
        end
    end

    // redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_wraddr(COUNTER,31897)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_wraddr_i <= $unsigned(redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_wraddr_q = redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_wraddr_i[7:0];

    // redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem(DUALMEM,31896)
    assign redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_ia = $unsigned(redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_inputreg0_q);
    assign redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_aa = redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_wraddr_q;
    assign redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_ab = redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_aa),
        .data_a(redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_ab),
        .q_b(redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_q = redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_iq[15:0];

    // redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_outputreg0(DELAY,31895)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_outputreg0_q <= $unsigned(redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_mem_q);
        end
    end

    // redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_rdcnt(ADD,30451)
    assign redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_a = {1'b0, redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_wraddr_q};
    assign redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_b = {1'b0, redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_o <= $unsigned(redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_a) + $unsigned(redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_b);
        end
    end
    assign redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_q = redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_o[8:0];

    // redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_inputreg0(DELAY,30446)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl);
        end
    end

    // redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_wraddr(COUNTER,30449)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_wraddr_i <= $unsigned(redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_wraddr_q = redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_wraddr_i[7:0];

    // redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem(DUALMEM,30448)
    assign redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_ia = $unsigned(redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_inputreg0_q);
    assign redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_aa = redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_wraddr_q;
    assign redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_ab = redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_aa),
        .data_a(redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_ab),
        .q_b(redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_q = redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_iq[15:0];

    // redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_outputreg0(DELAY,30447)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_outputreg0_q <= $unsigned(redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_mem_q);
        end
    end

    // redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_rdcnt(ADD,30457)
    assign redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_a = {1'b0, redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_wraddr_q};
    assign redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_b = {1'b0, redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_o <= $unsigned(redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_a) + $unsigned(redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_b);
        end
    end
    assign redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_q = redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_o[8:0];

    // redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_inputreg0(DELAY,30452)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl);
        end
    end

    // redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_wraddr(COUNTER,30455)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_wraddr_i <= $unsigned(redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_wraddr_q = redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_wraddr_i[7:0];

    // redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem(DUALMEM,30454)
    assign redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_ia = $unsigned(redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_inputreg0_q);
    assign redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_aa = redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_wraddr_q;
    assign redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_ab = redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_aa),
        .data_a(redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_ab),
        .q_b(redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_q = redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_iq[15:0];

    // redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_outputreg0(DELAY,30453)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_outputreg0_q <= $unsigned(redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_mem_q);
        end
    end

    // redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_rdcnt(ADD,31893)
    assign redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_a = {1'b0, redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_wraddr_q};
    assign redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_b = {1'b0, redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_o <= $unsigned(redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_a) + $unsigned(redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_b);
        end
    end
    assign redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_q = redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_o[8:0];

    // redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_inputreg0(DELAY,31888)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl);
        end
    end

    // redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_wraddr(COUNTER,31891)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_wraddr_i <= $unsigned(redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_wraddr_q = redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_wraddr_i[7:0];

    // redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem(DUALMEM,31890)
    assign redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_ia = $unsigned(redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_inputreg0_q);
    assign redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_aa = redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_wraddr_q;
    assign redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_ab = redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_aa),
        .data_a(redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_ab),
        .q_b(redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_q = redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_iq[15:0];

    // redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_outputreg0(DELAY,31889)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_outputreg0_q <= $unsigned(redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28035)@159 + 5
    // out q@165
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164(ADD,8622)@165
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod421_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_b = $unsigned({{5{i_shl_i_i_i_i_i_i_76_c_compstr2163_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_76_c_compstr2163_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_o[33:0];

    // rightShiftStage0_uid19681_dupName_305_i_unnamed_c_compstr0_shift_x(MUX,19680)@165
    assign rightShiftStage0_uid19681_dupName_305_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19681_dupName_305_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_q or rightShiftStage0Idx1_uid19679_dupName_305_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19681_dupName_305_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19681_dupName_305_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_q;
            1'b1 : rightShiftStage0_uid19681_dupName_305_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19679_dupName_305_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19681_dupName_305_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19686_dupName_305_i_unnamed_c_compstr0_shift_x(MUX,19685)@165
    assign rightShiftStage1_uid19686_dupName_305_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19686_dupName_305_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19681_dupName_305_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19684_dupName_305_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19686_dupName_305_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19686_dupName_305_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19681_dupName_305_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19686_dupName_305_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19684_dupName_305_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19686_dupName_305_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19691_dupName_305_i_unnamed_c_compstr0_shift_x(MUX,19690)@165
    assign rightShiftStage2_uid19691_dupName_305_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19691_dupName_305_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19686_dupName_305_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19689_dupName_305_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19691_dupName_305_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19691_dupName_305_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19686_dupName_305_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19691_dupName_305_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19689_dupName_305_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19691_dupName_305_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2165_vt_select_20(BITSELECT,10806)@165
    assign i_unnamed_c_compstr2165_vt_select_20_b = rightShiftStage2_uid19691_dupName_305_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2165_vt_join(BITJOIN,10805)@165
    assign i_unnamed_c_compstr2165_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2165_vt_select_20_b};

    // i_conv_i_i_i_i_i_76_c_compstr2166_sel_x(BITSELECT,3813)@165
    assign i_conv_i_i_i_i_i_76_c_compstr2166_sel_x_b = i_unnamed_c_compstr2165_vt_join_q[15:0];

    // redist1052_i_conv_i_i_i_i_i_76_c_compstr2166_sel_x_b_1(DELAY,29280)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1052_i_conv_i_i_i_i_i_76_c_compstr2166_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_76_c_compstr2166_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19700_dupName_306_i_unnamed_c_compstr0_shift_x(BITSELECT,19699)@165
    assign rightShiftStage1Idx1Rng8_uid19700_dupName_306_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19699_dupName_306_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19702_dupName_306_i_unnamed_c_compstr0_shift_x(BITJOIN,19701)@165
    assign rightShiftStage1Idx1_uid19702_dupName_306_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19700_dupName_306_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19695_dupName_306_i_unnamed_c_compstr0_shift_x(BITSELECT,19694)@165
    assign rightShiftStage0Idx1Rng4_uid19695_dupName_306_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_q[33:4];

    // rightShiftStage0Idx1_uid19697_dupName_306_i_unnamed_c_compstr0_shift_x(BITJOIN,19696)@165
    assign rightShiftStage0Idx1_uid19697_dupName_306_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19695_dupName_306_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19699_dupName_306_i_unnamed_c_compstr0_shift_x(MUX,19698)@165
    assign rightShiftStage0_uid19699_dupName_306_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19699_dupName_306_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_q or rightShiftStage0Idx1_uid19697_dupName_306_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19699_dupName_306_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19699_dupName_306_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compstr2164_q;
            1'b1 : rightShiftStage0_uid19699_dupName_306_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19697_dupName_306_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19699_dupName_306_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19704_dupName_306_i_unnamed_c_compstr0_shift_x(MUX,19703)@165
    assign rightShiftStage1_uid19704_dupName_306_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19704_dupName_306_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19699_dupName_306_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19702_dupName_306_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19704_dupName_306_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19704_dupName_306_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19699_dupName_306_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19704_dupName_306_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19702_dupName_306_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19704_dupName_306_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2167_vt_select_21(BITSELECT,10809)@165
    assign i_unnamed_c_compstr2167_vt_select_21_b = rightShiftStage1_uid19704_dupName_306_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2167_vt_join(BITJOIN,10808)@165
    assign i_unnamed_c_compstr2167_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2167_vt_select_21_b};

    // i_unnamed_c_compstr2168_sel_x(BITSELECT,6126)@165
    assign i_unnamed_c_compstr2168_sel_x_b = i_unnamed_c_compstr2167_vt_join_q[15:0];

    // i_unnamed_c_compstr2169_BitSelect_for_a(BITSELECT,27641)@165
    assign i_unnamed_c_compstr2169_BitSelect_for_a_b = i_unnamed_c_compstr2168_sel_x_b[0:0];

    // i_unnamed_c_compstr2169_join(BITJOIN,27642)@165
    assign i_unnamed_c_compstr2169_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2169_BitSelect_for_a_b};

    // i_unnamed_c_compstr2169_vt_select_0(BITSELECT,10814)@165
    assign i_unnamed_c_compstr2169_vt_select_0_b = i_unnamed_c_compstr2169_join_q[0:0];

    // redist164_i_unnamed_c_compstr2169_vt_select_0_b_1(DELAY,28392)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist164_i_unnamed_c_compstr2169_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2169_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2169_vt_join(BITJOIN,10813)@166
    assign i_unnamed_c_compstr2169_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist164_i_unnamed_c_compstr2169_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_76_c_compstr2170(ADD,7080)@166
    assign i_add_i_i_i_i_i_i_76_c_compstr2170_a = {1'b0, i_unnamed_c_compstr2169_vt_join_q};
    assign i_add_i_i_i_i_i_i_76_c_compstr2170_b = {1'b0, redist1052_i_conv_i_i_i_i_i_76_c_compstr2166_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_76_c_compstr2170_o = $unsigned(i_add_i_i_i_i_i_i_76_c_compstr2170_a) + $unsigned(i_add_i_i_i_i_i_i_76_c_compstr2170_b);
    assign i_add_i_i_i_i_i_i_76_c_compstr2170_q = i_add_i_i_i_i_i_i_76_c_compstr2170_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_76_c_compstr2170_sel_x(BITSELECT,2274)@166
    assign bgTrunc_i_add_i_i_i_i_i_i_76_c_compstr2170_sel_x_b = i_add_i_i_i_i_i_i_76_c_compstr2170_q[15:0];

    // i_conv_i_i_i_i_i_i279_77_c_compstr2190_sel_x(BITSELECT,3942)@166
    assign i_conv_i_i_i_i_i_i279_77_c_compstr2190_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_76_c_compstr2170_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_77_c_compstr2190_vt_select_15(BITSELECT,8285)@166
    assign i_conv_i_i_i_i_i_i279_77_c_compstr2190_vt_select_15_b = i_conv_i_i_i_i_i_i279_77_c_compstr2190_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_77_c_compstr2190_vt_join(BITJOIN,8284)@166
    assign i_conv_i_i_i_i_i_i279_77_c_compstr2190_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_77_c_compstr2190_vt_select_15_b};

    // leftShiftStage0_uid26978_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x(MUX,26977)@166
    assign leftShiftStage0_uid26978_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26978_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_77_c_compstr2190_vt_join_q or leftShiftStage0Idx1_uid26976_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26978_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26978_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_77_c_compstr2190_vt_join_q;
            1'b1 : leftShiftStage0_uid26978_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26976_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26978_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26983_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x(MUX,26982)@166
    assign leftShiftStage1_uid26983_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26983_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_s or leftShiftStage0_uid26978_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26981_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26983_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid26983_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q = leftShiftStage0_uid26978_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid26983_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26981_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid26983_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26988_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x(MUX,26987)@166
    assign leftShiftStage2_uid26988_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26988_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_s or leftShiftStage1_uid26983_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid26986_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26988_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid26988_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q = leftShiftStage1_uid26983_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid26988_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid26986_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid26988_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_77_c_compstr2191_vt_select_28(BITSELECT,9727)@166
    assign i_shl_i_i_i_i_i_i_77_c_compstr2191_vt_select_28_b = leftShiftStage2_uid26988_i_shl_i_i_i_i_i_i_77_c_compstr0_shift_x_q[28:13];

    // redist281_i_shl_i_i_i_i_i_i_77_c_compstr2191_vt_select_28_b_1(DELAY,28509)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist281_i_shl_i_i_i_i_i_i_77_c_compstr2191_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_77_c_compstr2191_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_77_c_compstr2191_vt_join(BITJOIN,9726)@167
    assign i_shl_i_i_i_i_i_i_77_c_compstr2191_vt_join_q = {redist281_i_shl_i_i_i_i_i_i_77_c_compstr2191_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_offset(CONSTANT,30462)
    assign redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_offset_q = $unsigned(8'b01101100);

    // redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_rdcnt(ADD,31911)
    assign redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_a = {1'b0, redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_wraddr_q};
    assign redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_b = {1'b0, redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_o <= $unsigned(redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_a) + $unsigned(redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_b);
        end
    end
    assign redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_q = redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_o[8:0];

    // redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_inputreg0(DELAY,31906)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl);
        end
    end

    // redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_wraddr(COUNTER,31909)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_wraddr_i <= $unsigned(redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_wraddr_q = redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_wraddr_i[7:0];

    // redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem(DUALMEM,31908)
    assign redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_ia = $unsigned(redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_inputreg0_q);
    assign redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_aa = redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_wraddr_q;
    assign redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_ab = redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_aa),
        .data_a(redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_ab),
        .q_b(redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_q = redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_iq[15:0];

    // redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_outputreg0(DELAY,31907)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_outputreg0_q <= $unsigned(redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_mem_q);
        end
    end

    // redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_rdcnt(ADD,30463)
    assign redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_a = {1'b0, redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_wraddr_q};
    assign redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_b = {1'b0, redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_o <= $unsigned(redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_a) + $unsigned(redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_b);
        end
    end
    assign redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_q = redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_o[8:0];

    // redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_inputreg0(DELAY,30458)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl);
        end
    end

    // redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_wraddr(COUNTER,30461)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_wraddr_i <= $unsigned(redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_wraddr_q = redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_wraddr_i[7:0];

    // redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem(DUALMEM,30460)
    assign redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_ia = $unsigned(redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_inputreg0_q);
    assign redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_aa = redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_wraddr_q;
    assign redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_ab = redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_aa),
        .data_a(redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_ab),
        .q_b(redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_q = redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_iq[15:0];

    // redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_outputreg0(DELAY,30459)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_outputreg0_q <= $unsigned(redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_mem_q);
        end
    end

    // redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_rdcnt(ADD,30469)
    assign redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_a = {1'b0, redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_wraddr_q};
    assign redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_b = {1'b0, redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_o <= $unsigned(redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_a) + $unsigned(redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_b);
        end
    end
    assign redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_q = redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_o[8:0];

    // redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_inputreg0(DELAY,30464)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl);
        end
    end

    // redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_wraddr(COUNTER,30467)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_wraddr_i <= $unsigned(redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_wraddr_q = redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_wraddr_i[7:0];

    // redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem(DUALMEM,30466)
    assign redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_ia = $unsigned(redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_inputreg0_q);
    assign redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_aa = redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_wraddr_q;
    assign redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_ab = redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_aa),
        .data_a(redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_ab),
        .q_b(redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_q = redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_iq[15:0];

    // redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_outputreg0(DELAY,30465)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_outputreg0_q <= $unsigned(redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_mem_q);
        end
    end

    // redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_rdcnt(ADD,31905)
    assign redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_a = {1'b0, redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_wraddr_q};
    assign redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_b = {1'b0, redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_o <= $unsigned(redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_a) + $unsigned(redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_b);
        end
    end
    assign redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_q = redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_o[8:0];

    // redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_inputreg0(DELAY,31900)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl);
        end
    end

    // redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_wraddr(COUNTER,31903)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_wraddr_i <= $unsigned(redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_wraddr_q = redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_wraddr_i[7:0];

    // redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem(DUALMEM,31902)
    assign redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_ia = $unsigned(redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_inputreg0_q);
    assign redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_aa = redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_wraddr_q;
    assign redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_ab = redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_aa),
        .data_a(redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_ab),
        .q_b(redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_q = redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_iq[15:0];

    // redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_outputreg0(DELAY,31901)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_outputreg0_q <= $unsigned(redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28036)@161 + 5
    // out q@167
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192(ADD,8623)@167
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod426_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_b = $unsigned({{5{i_shl_i_i_i_i_i_i_77_c_compstr2191_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_77_c_compstr2191_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_o[33:0];

    // rightShiftStage0_uid19743_dupName_309_i_unnamed_c_compstr0_shift_x(MUX,19742)@167
    assign rightShiftStage0_uid19743_dupName_309_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19743_dupName_309_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_q or rightShiftStage0Idx1_uid19741_dupName_309_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19743_dupName_309_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19743_dupName_309_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_q;
            1'b1 : rightShiftStage0_uid19743_dupName_309_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19741_dupName_309_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19743_dupName_309_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19748_dupName_309_i_unnamed_c_compstr0_shift_x(MUX,19747)@167
    assign rightShiftStage1_uid19748_dupName_309_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19748_dupName_309_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19743_dupName_309_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19746_dupName_309_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19748_dupName_309_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19748_dupName_309_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19743_dupName_309_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19748_dupName_309_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19746_dupName_309_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19748_dupName_309_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19753_dupName_309_i_unnamed_c_compstr0_shift_x(MUX,19752)@167
    assign rightShiftStage2_uid19753_dupName_309_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19753_dupName_309_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19748_dupName_309_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19751_dupName_309_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19753_dupName_309_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19753_dupName_309_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19748_dupName_309_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19753_dupName_309_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19751_dupName_309_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19753_dupName_309_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2193_vt_select_20(BITSELECT,10831)@167
    assign i_unnamed_c_compstr2193_vt_select_20_b = rightShiftStage2_uid19753_dupName_309_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2193_vt_join(BITJOIN,10830)@167
    assign i_unnamed_c_compstr2193_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2193_vt_select_20_b};

    // i_conv_i_i_i_i_i_77_c_compstr2194_sel_x(BITSELECT,3814)@167
    assign i_conv_i_i_i_i_i_77_c_compstr2194_sel_x_b = i_unnamed_c_compstr2193_vt_join_q[15:0];

    // redist1051_i_conv_i_i_i_i_i_77_c_compstr2194_sel_x_b_1(DELAY,29279)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1051_i_conv_i_i_i_i_i_77_c_compstr2194_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_77_c_compstr2194_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19762_dupName_310_i_unnamed_c_compstr0_shift_x(BITSELECT,19761)@167
    assign rightShiftStage1Idx1Rng8_uid19762_dupName_310_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19761_dupName_310_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19764_dupName_310_i_unnamed_c_compstr0_shift_x(BITJOIN,19763)@167
    assign rightShiftStage1Idx1_uid19764_dupName_310_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19762_dupName_310_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19757_dupName_310_i_unnamed_c_compstr0_shift_x(BITSELECT,19756)@167
    assign rightShiftStage0Idx1Rng4_uid19757_dupName_310_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_q[33:4];

    // rightShiftStage0Idx1_uid19759_dupName_310_i_unnamed_c_compstr0_shift_x(BITJOIN,19758)@167
    assign rightShiftStage0Idx1_uid19759_dupName_310_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19757_dupName_310_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19761_dupName_310_i_unnamed_c_compstr0_shift_x(MUX,19760)@167
    assign rightShiftStage0_uid19761_dupName_310_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19761_dupName_310_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_q or rightShiftStage0Idx1_uid19759_dupName_310_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19761_dupName_310_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19761_dupName_310_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compstr2192_q;
            1'b1 : rightShiftStage0_uid19761_dupName_310_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19759_dupName_310_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19761_dupName_310_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19766_dupName_310_i_unnamed_c_compstr0_shift_x(MUX,19765)@167
    assign rightShiftStage1_uid19766_dupName_310_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19766_dupName_310_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19761_dupName_310_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19764_dupName_310_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19766_dupName_310_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19766_dupName_310_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19761_dupName_310_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19766_dupName_310_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19764_dupName_310_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19766_dupName_310_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2195_vt_select_21(BITSELECT,10834)@167
    assign i_unnamed_c_compstr2195_vt_select_21_b = rightShiftStage1_uid19766_dupName_310_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2195_vt_join(BITJOIN,10833)@167
    assign i_unnamed_c_compstr2195_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2195_vt_select_21_b};

    // i_unnamed_c_compstr2196_sel_x(BITSELECT,6128)@167
    assign i_unnamed_c_compstr2196_sel_x_b = i_unnamed_c_compstr2195_vt_join_q[15:0];

    // i_unnamed_c_compstr2197_BitSelect_for_a(BITSELECT,27645)@167
    assign i_unnamed_c_compstr2197_BitSelect_for_a_b = i_unnamed_c_compstr2196_sel_x_b[0:0];

    // i_unnamed_c_compstr2197_join(BITJOIN,27646)@167
    assign i_unnamed_c_compstr2197_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2197_BitSelect_for_a_b};

    // i_unnamed_c_compstr2197_vt_select_0(BITSELECT,10839)@167
    assign i_unnamed_c_compstr2197_vt_select_0_b = i_unnamed_c_compstr2197_join_q[0:0];

    // redist162_i_unnamed_c_compstr2197_vt_select_0_b_1(DELAY,28390)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist162_i_unnamed_c_compstr2197_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2197_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2197_vt_join(BITJOIN,10838)@168
    assign i_unnamed_c_compstr2197_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist162_i_unnamed_c_compstr2197_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_77_c_compstr2198(ADD,7081)@168
    assign i_add_i_i_i_i_i_i_77_c_compstr2198_a = {1'b0, i_unnamed_c_compstr2197_vt_join_q};
    assign i_add_i_i_i_i_i_i_77_c_compstr2198_b = {1'b0, redist1051_i_conv_i_i_i_i_i_77_c_compstr2194_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_77_c_compstr2198_o = $unsigned(i_add_i_i_i_i_i_i_77_c_compstr2198_a) + $unsigned(i_add_i_i_i_i_i_i_77_c_compstr2198_b);
    assign i_add_i_i_i_i_i_i_77_c_compstr2198_q = i_add_i_i_i_i_i_i_77_c_compstr2198_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_77_c_compstr2198_sel_x(BITSELECT,2275)@168
    assign bgTrunc_i_add_i_i_i_i_i_i_77_c_compstr2198_sel_x_b = i_add_i_i_i_i_i_i_77_c_compstr2198_q[15:0];

    // i_conv_i_i_i_i_i_i279_78_c_compstr2218_sel_x(BITSELECT,3943)@168
    assign i_conv_i_i_i_i_i_i279_78_c_compstr2218_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_77_c_compstr2198_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_78_c_compstr2218_vt_select_15(BITSELECT,8289)@168
    assign i_conv_i_i_i_i_i_i279_78_c_compstr2218_vt_select_15_b = i_conv_i_i_i_i_i_i279_78_c_compstr2218_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_78_c_compstr2218_vt_join(BITJOIN,8288)@168
    assign i_conv_i_i_i_i_i_i279_78_c_compstr2218_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_78_c_compstr2218_vt_select_15_b};

    // leftShiftStage0_uid26996_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x(MUX,26995)@168
    assign leftShiftStage0_uid26996_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26996_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_78_c_compstr2218_vt_join_q or leftShiftStage0Idx1_uid26994_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26996_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid26996_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_78_c_compstr2218_vt_join_q;
            1'b1 : leftShiftStage0_uid26996_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid26994_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid26996_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27001_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x(MUX,27000)@168
    assign leftShiftStage1_uid27001_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27001_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_s or leftShiftStage0_uid26996_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid26999_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27001_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27001_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q = leftShiftStage0_uid26996_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27001_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid26999_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27001_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27006_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x(MUX,27005)@168
    assign leftShiftStage2_uid27006_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27006_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_s or leftShiftStage1_uid27001_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27004_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27006_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27006_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q = leftShiftStage1_uid27001_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27006_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27004_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27006_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_78_c_compstr2219_vt_select_28(BITSELECT,9730)@168
    assign i_shl_i_i_i_i_i_i_78_c_compstr2219_vt_select_28_b = leftShiftStage2_uid27006_i_shl_i_i_i_i_i_i_78_c_compstr0_shift_x_q[28:13];

    // redist280_i_shl_i_i_i_i_i_i_78_c_compstr2219_vt_select_28_b_1(DELAY,28508)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist280_i_shl_i_i_i_i_i_i_78_c_compstr2219_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_78_c_compstr2219_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_78_c_compstr2219_vt_join(BITJOIN,9729)@169
    assign i_shl_i_i_i_i_i_i_78_c_compstr2219_vt_join_q = {redist280_i_shl_i_i_i_i_i_i_78_c_compstr2219_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_offset(CONSTANT,30474)
    assign redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_offset_q = $unsigned(8'b01101010);

    // redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_rdcnt(ADD,31923)
    assign redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_a = {1'b0, redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_wraddr_q};
    assign redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_b = {1'b0, redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_o <= $unsigned(redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_a) + $unsigned(redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_b);
        end
    end
    assign redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_q = redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_o[8:0];

    // redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_inputreg0(DELAY,31918)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl);
        end
    end

    // redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_wraddr(COUNTER,31921)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_wraddr_i <= $unsigned(redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_wraddr_q = redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_wraddr_i[7:0];

    // redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem(DUALMEM,31920)
    assign redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_ia = $unsigned(redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_inputreg0_q);
    assign redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_aa = redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_wraddr_q;
    assign redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_ab = redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_aa),
        .data_a(redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_ab),
        .q_b(redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_q = redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_iq[15:0];

    // redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_outputreg0(DELAY,31919)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_outputreg0_q <= $unsigned(redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_mem_q);
        end
    end

    // redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_rdcnt(ADD,30475)
    assign redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_a = {1'b0, redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_wraddr_q};
    assign redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_b = {1'b0, redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_o <= $unsigned(redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_a) + $unsigned(redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_b);
        end
    end
    assign redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_q = redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_o[8:0];

    // redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_inputreg0(DELAY,30470)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl);
        end
    end

    // redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_wraddr(COUNTER,30473)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_wraddr_i <= $unsigned(redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_wraddr_q = redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_wraddr_i[7:0];

    // redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem(DUALMEM,30472)
    assign redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_ia = $unsigned(redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_inputreg0_q);
    assign redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_aa = redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_wraddr_q;
    assign redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_ab = redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_aa),
        .data_a(redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_ab),
        .q_b(redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_q = redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_iq[15:0];

    // redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_outputreg0(DELAY,30471)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_outputreg0_q <= $unsigned(redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_mem_q);
        end
    end

    // redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_rdcnt(ADD,30481)
    assign redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_a = {1'b0, redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_wraddr_q};
    assign redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_b = {1'b0, redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_o <= $unsigned(redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_a) + $unsigned(redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_b);
        end
    end
    assign redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_q = redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_o[8:0];

    // redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_inputreg0(DELAY,30476)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl);
        end
    end

    // redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_wraddr(COUNTER,30479)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_wraddr_i <= $unsigned(redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_wraddr_q = redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_wraddr_i[7:0];

    // redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem(DUALMEM,30478)
    assign redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_ia = $unsigned(redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_inputreg0_q);
    assign redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_aa = redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_wraddr_q;
    assign redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_ab = redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_aa),
        .data_a(redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_ab),
        .q_b(redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_q = redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_iq[15:0];

    // redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_outputreg0(DELAY,30477)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_outputreg0_q <= $unsigned(redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_mem_q);
        end
    end

    // redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_rdcnt(ADD,31917)
    assign redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_a = {1'b0, redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_wraddr_q};
    assign redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_b = {1'b0, redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_o <= $unsigned(redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_a) + $unsigned(redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_b);
        end
    end
    assign redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_q = redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_o[8:0];

    // redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_inputreg0(DELAY,31912)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl);
        end
    end

    // redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_wraddr(COUNTER,31915)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_wraddr_i <= $unsigned(redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_wraddr_q = redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_wraddr_i[7:0];

    // redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem(DUALMEM,31914)
    assign redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_ia = $unsigned(redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_inputreg0_q);
    assign redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_aa = redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_wraddr_q;
    assign redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_ab = redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_aa),
        .data_a(redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_ab),
        .q_b(redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_q = redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_iq[15:0];

    // redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_outputreg0(DELAY,31913)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_outputreg0_q <= $unsigned(redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28037)@163 + 5
    // out q@169
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220(ADD,8624)@169
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod431_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_b = $unsigned({{5{i_shl_i_i_i_i_i_i_78_c_compstr2219_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_78_c_compstr2219_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_o[33:0];

    // rightShiftStage0_uid19805_dupName_313_i_unnamed_c_compstr0_shift_x(MUX,19804)@169
    assign rightShiftStage0_uid19805_dupName_313_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19805_dupName_313_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_q or rightShiftStage0Idx1_uid19803_dupName_313_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19805_dupName_313_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19805_dupName_313_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_q;
            1'b1 : rightShiftStage0_uid19805_dupName_313_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19803_dupName_313_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19805_dupName_313_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19810_dupName_313_i_unnamed_c_compstr0_shift_x(MUX,19809)@169
    assign rightShiftStage1_uid19810_dupName_313_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19810_dupName_313_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19805_dupName_313_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19808_dupName_313_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19810_dupName_313_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19810_dupName_313_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19805_dupName_313_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19810_dupName_313_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19808_dupName_313_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19810_dupName_313_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19815_dupName_313_i_unnamed_c_compstr0_shift_x(MUX,19814)@169
    assign rightShiftStage2_uid19815_dupName_313_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19815_dupName_313_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19810_dupName_313_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19813_dupName_313_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19815_dupName_313_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19815_dupName_313_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19810_dupName_313_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19815_dupName_313_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19813_dupName_313_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19815_dupName_313_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2221_vt_select_20(BITSELECT,10861)@169
    assign i_unnamed_c_compstr2221_vt_select_20_b = rightShiftStage2_uid19815_dupName_313_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2221_vt_join(BITJOIN,10860)@169
    assign i_unnamed_c_compstr2221_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2221_vt_select_20_b};

    // i_conv_i_i_i_i_i_78_c_compstr2222_sel_x(BITSELECT,3815)@169
    assign i_conv_i_i_i_i_i_78_c_compstr2222_sel_x_b = i_unnamed_c_compstr2221_vt_join_q[15:0];

    // redist1050_i_conv_i_i_i_i_i_78_c_compstr2222_sel_x_b_1(DELAY,29278)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1050_i_conv_i_i_i_i_i_78_c_compstr2222_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_78_c_compstr2222_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19824_dupName_314_i_unnamed_c_compstr0_shift_x(BITSELECT,19823)@169
    assign rightShiftStage1Idx1Rng8_uid19824_dupName_314_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19823_dupName_314_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19826_dupName_314_i_unnamed_c_compstr0_shift_x(BITJOIN,19825)@169
    assign rightShiftStage1Idx1_uid19826_dupName_314_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19824_dupName_314_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19819_dupName_314_i_unnamed_c_compstr0_shift_x(BITSELECT,19818)@169
    assign rightShiftStage0Idx1Rng4_uid19819_dupName_314_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_q[33:4];

    // rightShiftStage0Idx1_uid19821_dupName_314_i_unnamed_c_compstr0_shift_x(BITJOIN,19820)@169
    assign rightShiftStage0Idx1_uid19821_dupName_314_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19819_dupName_314_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19823_dupName_314_i_unnamed_c_compstr0_shift_x(MUX,19822)@169
    assign rightShiftStage0_uid19823_dupName_314_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19823_dupName_314_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_q or rightShiftStage0Idx1_uid19821_dupName_314_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19823_dupName_314_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19823_dupName_314_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compstr2220_q;
            1'b1 : rightShiftStage0_uid19823_dupName_314_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19821_dupName_314_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19823_dupName_314_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19828_dupName_314_i_unnamed_c_compstr0_shift_x(MUX,19827)@169
    assign rightShiftStage1_uid19828_dupName_314_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19828_dupName_314_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19823_dupName_314_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19826_dupName_314_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19828_dupName_314_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19828_dupName_314_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19823_dupName_314_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19828_dupName_314_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19826_dupName_314_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19828_dupName_314_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2223_vt_select_21(BITSELECT,10864)@169
    assign i_unnamed_c_compstr2223_vt_select_21_b = rightShiftStage1_uid19828_dupName_314_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2223_vt_join(BITJOIN,10863)@169
    assign i_unnamed_c_compstr2223_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2223_vt_select_21_b};

    // i_unnamed_c_compstr2224_sel_x(BITSELECT,6131)@169
    assign i_unnamed_c_compstr2224_sel_x_b = i_unnamed_c_compstr2223_vt_join_q[15:0];

    // i_unnamed_c_compstr2225_BitSelect_for_a(BITSELECT,27651)@169
    assign i_unnamed_c_compstr2225_BitSelect_for_a_b = i_unnamed_c_compstr2224_sel_x_b[0:0];

    // i_unnamed_c_compstr2225_join(BITJOIN,27652)@169
    assign i_unnamed_c_compstr2225_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2225_BitSelect_for_a_b};

    // i_unnamed_c_compstr2225_vt_select_0(BITSELECT,10869)@169
    assign i_unnamed_c_compstr2225_vt_select_0_b = i_unnamed_c_compstr2225_join_q[0:0];

    // redist159_i_unnamed_c_compstr2225_vt_select_0_b_1(DELAY,28387)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist159_i_unnamed_c_compstr2225_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2225_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2225_vt_join(BITJOIN,10868)@170
    assign i_unnamed_c_compstr2225_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist159_i_unnamed_c_compstr2225_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_78_c_compstr2226(ADD,7082)@170
    assign i_add_i_i_i_i_i_i_78_c_compstr2226_a = {1'b0, i_unnamed_c_compstr2225_vt_join_q};
    assign i_add_i_i_i_i_i_i_78_c_compstr2226_b = {1'b0, redist1050_i_conv_i_i_i_i_i_78_c_compstr2222_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_78_c_compstr2226_o = $unsigned(i_add_i_i_i_i_i_i_78_c_compstr2226_a) + $unsigned(i_add_i_i_i_i_i_i_78_c_compstr2226_b);
    assign i_add_i_i_i_i_i_i_78_c_compstr2226_q = i_add_i_i_i_i_i_i_78_c_compstr2226_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_78_c_compstr2226_sel_x(BITSELECT,2276)@170
    assign bgTrunc_i_add_i_i_i_i_i_i_78_c_compstr2226_sel_x_b = i_add_i_i_i_i_i_i_78_c_compstr2226_q[15:0];

    // i_conv_i_i_i_i_i_i279_79_c_compstr2246_sel_x(BITSELECT,3944)@170
    assign i_conv_i_i_i_i_i_i279_79_c_compstr2246_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_78_c_compstr2226_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_79_c_compstr2246_vt_select_15(BITSELECT,8293)@170
    assign i_conv_i_i_i_i_i_i279_79_c_compstr2246_vt_select_15_b = i_conv_i_i_i_i_i_i279_79_c_compstr2246_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_79_c_compstr2246_vt_join(BITJOIN,8292)@170
    assign i_conv_i_i_i_i_i_i279_79_c_compstr2246_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_79_c_compstr2246_vt_select_15_b};

    // leftShiftStage0_uid27014_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x(MUX,27013)@170
    assign leftShiftStage0_uid27014_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27014_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_79_c_compstr2246_vt_join_q or leftShiftStage0Idx1_uid27012_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27014_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27014_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_79_c_compstr2246_vt_join_q;
            1'b1 : leftShiftStage0_uid27014_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27012_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27014_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27019_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x(MUX,27018)@170
    assign leftShiftStage1_uid27019_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27019_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_s or leftShiftStage0_uid27014_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27017_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27019_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27019_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q = leftShiftStage0_uid27014_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27019_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27017_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27019_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27024_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x(MUX,27023)@170
    assign leftShiftStage2_uid27024_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27024_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_s or leftShiftStage1_uid27019_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27022_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27024_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27024_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q = leftShiftStage1_uid27019_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27024_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27022_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27024_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_79_c_compstr2247_vt_select_28(BITSELECT,9733)@170
    assign i_shl_i_i_i_i_i_i_79_c_compstr2247_vt_select_28_b = leftShiftStage2_uid27024_i_shl_i_i_i_i_i_i_79_c_compstr0_shift_x_q[28:13];

    // redist279_i_shl_i_i_i_i_i_i_79_c_compstr2247_vt_select_28_b_1(DELAY,28507)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist279_i_shl_i_i_i_i_i_i_79_c_compstr2247_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_79_c_compstr2247_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_79_c_compstr2247_vt_join(BITJOIN,9732)@171
    assign i_shl_i_i_i_i_i_i_79_c_compstr2247_vt_join_q = {redist279_i_shl_i_i_i_i_i_i_79_c_compstr2247_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_offset(CONSTANT,30486)
    assign redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_offset_q = $unsigned(8'b01101000);

    // redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_rdcnt(ADD,31935)
    assign redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_a = {1'b0, redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_wraddr_q};
    assign redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_b = {1'b0, redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_o <= $unsigned(redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_a) + $unsigned(redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_b);
        end
    end
    assign redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_q = redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_o[8:0];

    // redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_inputreg0(DELAY,31930)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl);
        end
    end

    // redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_wraddr(COUNTER,31933)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_wraddr_i <= $unsigned(redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_wraddr_q = redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_wraddr_i[7:0];

    // redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem(DUALMEM,31932)
    assign redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_ia = $unsigned(redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_inputreg0_q);
    assign redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_aa = redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_wraddr_q;
    assign redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_ab = redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_aa),
        .data_a(redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_ab),
        .q_b(redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_q = redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_iq[15:0];

    // redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_outputreg0(DELAY,31931)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_outputreg0_q <= $unsigned(redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_mem_q);
        end
    end

    // redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_rdcnt(ADD,30487)
    assign redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_a = {1'b0, redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_wraddr_q};
    assign redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_b = {1'b0, redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_o <= $unsigned(redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_a) + $unsigned(redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_b);
        end
    end
    assign redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_q = redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_o[8:0];

    // redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_inputreg0(DELAY,30482)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl);
        end
    end

    // redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_wraddr(COUNTER,30485)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_wraddr_i <= $unsigned(redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_wraddr_q = redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_wraddr_i[7:0];

    // redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem(DUALMEM,30484)
    assign redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_ia = $unsigned(redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_inputreg0_q);
    assign redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_aa = redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_wraddr_q;
    assign redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_ab = redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_aa),
        .data_a(redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_ab),
        .q_b(redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_q = redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_iq[15:0];

    // redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_outputreg0(DELAY,30483)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_outputreg0_q <= $unsigned(redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_mem_q);
        end
    end

    // redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_rdcnt(ADD,30493)
    assign redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_a = {1'b0, redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_wraddr_q};
    assign redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_b = {1'b0, redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_o <= $unsigned(redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_a) + $unsigned(redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_b);
        end
    end
    assign redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_q = redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_o[8:0];

    // redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_inputreg0(DELAY,30488)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl);
        end
    end

    // redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_wraddr(COUNTER,30491)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_wraddr_i <= $unsigned(redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_wraddr_q = redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_wraddr_i[7:0];

    // redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem(DUALMEM,30490)
    assign redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_ia = $unsigned(redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_inputreg0_q);
    assign redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_aa = redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_wraddr_q;
    assign redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_ab = redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_aa),
        .data_a(redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_ab),
        .q_b(redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_q = redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_iq[15:0];

    // redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_outputreg0(DELAY,30489)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_outputreg0_q <= $unsigned(redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_mem_q);
        end
    end

    // redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_rdcnt(ADD,31929)
    assign redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_a = {1'b0, redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_wraddr_q};
    assign redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_b = {1'b0, redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_o <= $unsigned(redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_a) + $unsigned(redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_b);
        end
    end
    assign redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_q = redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_o[8:0];

    // redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_inputreg0(DELAY,31924)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl);
        end
    end

    // redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_wraddr(COUNTER,31927)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_wraddr_i <= $unsigned(redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_wraddr_q = redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_wraddr_i[7:0];

    // redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem(DUALMEM,31926)
    assign redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_ia = $unsigned(redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_inputreg0_q);
    assign redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_aa = redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_wraddr_q;
    assign redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_ab = redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_aa),
        .data_a(redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_ab),
        .q_b(redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_q = redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_iq[15:0];

    // redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_outputreg0(DELAY,31925)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_outputreg0_q <= $unsigned(redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28038)@165 + 5
    // out q@171
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248(ADD,8625)@171
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod436_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_b = $unsigned({{5{i_shl_i_i_i_i_i_i_79_c_compstr2247_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_79_c_compstr2247_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_o[33:0];

    // rightShiftStage0_uid19867_dupName_317_i_unnamed_c_compstr0_shift_x(MUX,19866)@171
    assign rightShiftStage0_uid19867_dupName_317_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19867_dupName_317_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_q or rightShiftStage0Idx1_uid19865_dupName_317_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19867_dupName_317_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19867_dupName_317_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_q;
            1'b1 : rightShiftStage0_uid19867_dupName_317_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19865_dupName_317_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19867_dupName_317_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19872_dupName_317_i_unnamed_c_compstr0_shift_x(MUX,19871)@171
    assign rightShiftStage1_uid19872_dupName_317_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19872_dupName_317_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19867_dupName_317_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19870_dupName_317_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19872_dupName_317_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19872_dupName_317_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19867_dupName_317_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19872_dupName_317_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19870_dupName_317_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19872_dupName_317_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19877_dupName_317_i_unnamed_c_compstr0_shift_x(MUX,19876)@171
    assign rightShiftStage2_uid19877_dupName_317_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19877_dupName_317_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19872_dupName_317_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19875_dupName_317_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19877_dupName_317_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19877_dupName_317_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19872_dupName_317_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19877_dupName_317_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19875_dupName_317_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19877_dupName_317_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2249_vt_select_20(BITSELECT,10883)@171
    assign i_unnamed_c_compstr2249_vt_select_20_b = rightShiftStage2_uid19877_dupName_317_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2249_vt_join(BITJOIN,10882)@171
    assign i_unnamed_c_compstr2249_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2249_vt_select_20_b};

    // i_conv_i_i_i_i_i_79_c_compstr2250_sel_x(BITSELECT,3816)@171
    assign i_conv_i_i_i_i_i_79_c_compstr2250_sel_x_b = i_unnamed_c_compstr2249_vt_join_q[15:0];

    // redist1049_i_conv_i_i_i_i_i_79_c_compstr2250_sel_x_b_1(DELAY,29277)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1049_i_conv_i_i_i_i_i_79_c_compstr2250_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_79_c_compstr2250_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19886_dupName_318_i_unnamed_c_compstr0_shift_x(BITSELECT,19885)@171
    assign rightShiftStage1Idx1Rng8_uid19886_dupName_318_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19885_dupName_318_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19888_dupName_318_i_unnamed_c_compstr0_shift_x(BITJOIN,19887)@171
    assign rightShiftStage1Idx1_uid19888_dupName_318_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19886_dupName_318_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19881_dupName_318_i_unnamed_c_compstr0_shift_x(BITSELECT,19880)@171
    assign rightShiftStage0Idx1Rng4_uid19881_dupName_318_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_q[33:4];

    // rightShiftStage0Idx1_uid19883_dupName_318_i_unnamed_c_compstr0_shift_x(BITJOIN,19882)@171
    assign rightShiftStage0Idx1_uid19883_dupName_318_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19881_dupName_318_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19885_dupName_318_i_unnamed_c_compstr0_shift_x(MUX,19884)@171
    assign rightShiftStage0_uid19885_dupName_318_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19885_dupName_318_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_q or rightShiftStage0Idx1_uid19883_dupName_318_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19885_dupName_318_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19885_dupName_318_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compstr2248_q;
            1'b1 : rightShiftStage0_uid19885_dupName_318_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19883_dupName_318_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19885_dupName_318_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19890_dupName_318_i_unnamed_c_compstr0_shift_x(MUX,19889)@171
    assign rightShiftStage1_uid19890_dupName_318_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19890_dupName_318_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19885_dupName_318_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19888_dupName_318_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19890_dupName_318_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19890_dupName_318_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19885_dupName_318_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19890_dupName_318_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19888_dupName_318_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19890_dupName_318_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2251_vt_select_21(BITSELECT,10886)@171
    assign i_unnamed_c_compstr2251_vt_select_21_b = rightShiftStage1_uid19890_dupName_318_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2251_vt_join(BITJOIN,10885)@171
    assign i_unnamed_c_compstr2251_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2251_vt_select_21_b};

    // i_unnamed_c_compstr2252_sel_x(BITSELECT,6133)@171
    assign i_unnamed_c_compstr2252_sel_x_b = i_unnamed_c_compstr2251_vt_join_q[15:0];

    // i_unnamed_c_compstr2253_BitSelect_for_a(BITSELECT,27655)@171
    assign i_unnamed_c_compstr2253_BitSelect_for_a_b = i_unnamed_c_compstr2252_sel_x_b[0:0];

    // i_unnamed_c_compstr2253_join(BITJOIN,27656)@171
    assign i_unnamed_c_compstr2253_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2253_BitSelect_for_a_b};

    // i_unnamed_c_compstr2253_vt_select_0(BITSELECT,10891)@171
    assign i_unnamed_c_compstr2253_vt_select_0_b = i_unnamed_c_compstr2253_join_q[0:0];

    // redist157_i_unnamed_c_compstr2253_vt_select_0_b_1(DELAY,28385)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist157_i_unnamed_c_compstr2253_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2253_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2253_vt_join(BITJOIN,10890)@172
    assign i_unnamed_c_compstr2253_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist157_i_unnamed_c_compstr2253_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_79_c_compstr2254(ADD,7083)@172
    assign i_add_i_i_i_i_i_i_79_c_compstr2254_a = {1'b0, i_unnamed_c_compstr2253_vt_join_q};
    assign i_add_i_i_i_i_i_i_79_c_compstr2254_b = {1'b0, redist1049_i_conv_i_i_i_i_i_79_c_compstr2250_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_79_c_compstr2254_o = $unsigned(i_add_i_i_i_i_i_i_79_c_compstr2254_a) + $unsigned(i_add_i_i_i_i_i_i_79_c_compstr2254_b);
    assign i_add_i_i_i_i_i_i_79_c_compstr2254_q = i_add_i_i_i_i_i_i_79_c_compstr2254_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_79_c_compstr2254_sel_x(BITSELECT,2277)@172
    assign bgTrunc_i_add_i_i_i_i_i_i_79_c_compstr2254_sel_x_b = i_add_i_i_i_i_i_i_79_c_compstr2254_q[15:0];

    // i_conv_i_i_i_i_i_i279_80_c_compstr2274_sel_x(BITSELECT,3946)@172
    assign i_conv_i_i_i_i_i_i279_80_c_compstr2274_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_79_c_compstr2254_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_80_c_compstr2274_vt_select_15(BITSELECT,8301)@172
    assign i_conv_i_i_i_i_i_i279_80_c_compstr2274_vt_select_15_b = i_conv_i_i_i_i_i_i279_80_c_compstr2274_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_80_c_compstr2274_vt_join(BITJOIN,8300)@172
    assign i_conv_i_i_i_i_i_i279_80_c_compstr2274_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_80_c_compstr2274_vt_select_15_b};

    // leftShiftStage0_uid27050_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x(MUX,27049)@172
    assign leftShiftStage0_uid27050_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27050_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_80_c_compstr2274_vt_join_q or leftShiftStage0Idx1_uid27048_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27050_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27050_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_80_c_compstr2274_vt_join_q;
            1'b1 : leftShiftStage0_uid27050_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27048_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27050_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27055_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x(MUX,27054)@172
    assign leftShiftStage1_uid27055_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27055_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_s or leftShiftStage0_uid27050_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27053_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27055_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27055_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q = leftShiftStage0_uid27050_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27055_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27053_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27055_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27060_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x(MUX,27059)@172
    assign leftShiftStage2_uid27060_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27060_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_s or leftShiftStage1_uid27055_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27058_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27060_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27060_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q = leftShiftStage1_uid27055_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27060_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27058_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27060_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_80_c_compstr2275_vt_select_28(BITSELECT,9739)@172
    assign i_shl_i_i_i_i_i_i_80_c_compstr2275_vt_select_28_b = leftShiftStage2_uid27060_i_shl_i_i_i_i_i_i_80_c_compstr0_shift_x_q[28:13];

    // redist277_i_shl_i_i_i_i_i_i_80_c_compstr2275_vt_select_28_b_1(DELAY,28505)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist277_i_shl_i_i_i_i_i_i_80_c_compstr2275_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_80_c_compstr2275_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_80_c_compstr2275_vt_join(BITJOIN,9738)@173
    assign i_shl_i_i_i_i_i_i_80_c_compstr2275_vt_join_q = {redist277_i_shl_i_i_i_i_i_i_80_c_compstr2275_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_offset(CONSTANT,30498)
    assign redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_offset_q = $unsigned(8'b01100110);

    // redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_rdcnt(ADD,31947)
    assign redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_a = {1'b0, redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_wraddr_q};
    assign redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_b = {1'b0, redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_o <= $unsigned(redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_a) + $unsigned(redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_b);
        end
    end
    assign redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_q = redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_o[8:0];

    // redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_inputreg0(DELAY,31942)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl);
        end
    end

    // redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_wraddr(COUNTER,31945)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_wraddr_i <= $unsigned(redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_wraddr_q = redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_wraddr_i[7:0];

    // redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem(DUALMEM,31944)
    assign redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_ia = $unsigned(redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_inputreg0_q);
    assign redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_aa = redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_wraddr_q;
    assign redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_ab = redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_aa),
        .data_a(redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_ab),
        .q_b(redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_q = redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_iq[15:0];

    // redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_outputreg0(DELAY,31943)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_outputreg0_q <= $unsigned(redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_mem_q);
        end
    end

    // redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_rdcnt(ADD,30499)
    assign redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_a = {1'b0, redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_wraddr_q};
    assign redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_b = {1'b0, redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_o <= $unsigned(redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_a) + $unsigned(redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_b);
        end
    end
    assign redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_q = redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_o[8:0];

    // redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_inputreg0(DELAY,30494)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl);
        end
    end

    // redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_wraddr(COUNTER,30497)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_wraddr_i <= $unsigned(redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_wraddr_q = redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_wraddr_i[7:0];

    // redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem(DUALMEM,30496)
    assign redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_ia = $unsigned(redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_inputreg0_q);
    assign redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_aa = redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_wraddr_q;
    assign redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_ab = redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_aa),
        .data_a(redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_ab),
        .q_b(redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_q = redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_iq[15:0];

    // redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_outputreg0(DELAY,30495)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_outputreg0_q <= $unsigned(redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_mem_q);
        end
    end

    // redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_rdcnt(ADD,30505)
    assign redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_a = {1'b0, redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_wraddr_q};
    assign redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_b = {1'b0, redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_o <= $unsigned(redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_a) + $unsigned(redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_b);
        end
    end
    assign redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_q = redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_o[8:0];

    // redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_inputreg0(DELAY,30500)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl);
        end
    end

    // redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_wraddr(COUNTER,30503)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_wraddr_i <= $unsigned(redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_wraddr_q = redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_wraddr_i[7:0];

    // redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem(DUALMEM,30502)
    assign redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_ia = $unsigned(redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_inputreg0_q);
    assign redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_aa = redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_wraddr_q;
    assign redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_ab = redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_aa),
        .data_a(redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_ab),
        .q_b(redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_q = redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_iq[15:0];

    // redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_outputreg0(DELAY,30501)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_outputreg0_q <= $unsigned(redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_mem_q);
        end
    end

    // redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_rdcnt(ADD,31941)
    assign redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_a = {1'b0, redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_wraddr_q};
    assign redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_b = {1'b0, redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_o <= $unsigned(redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_a) + $unsigned(redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_b);
        end
    end
    assign redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_q = redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_o[8:0];

    // redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_inputreg0(DELAY,31936)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl);
        end
    end

    // redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_wraddr(COUNTER,31939)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_wraddr_i <= $unsigned(redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_wraddr_q = redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_wraddr_i[7:0];

    // redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem(DUALMEM,31938)
    assign redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_ia = $unsigned(redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_inputreg0_q);
    assign redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_aa = redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_wraddr_q;
    assign redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_ab = redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_aa),
        .data_a(redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_ab),
        .q_b(redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_q = redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_iq[15:0];

    // redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_outputreg0(DELAY,31937)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_outputreg0_q <= $unsigned(redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28039)@167 + 5
    // out q@173
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276(ADD,8627)@173
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod441_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_b = $unsigned({{5{i_shl_i_i_i_i_i_i_80_c_compstr2275_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_80_c_compstr2275_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_o[33:0];

    // rightShiftStage0_uid19929_dupName_321_i_unnamed_c_compstr0_shift_x(MUX,19928)@173
    assign rightShiftStage0_uid19929_dupName_321_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19929_dupName_321_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_q or rightShiftStage0Idx1_uid19927_dupName_321_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19929_dupName_321_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19929_dupName_321_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_q;
            1'b1 : rightShiftStage0_uid19929_dupName_321_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19927_dupName_321_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19929_dupName_321_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19934_dupName_321_i_unnamed_c_compstr0_shift_x(MUX,19933)@173
    assign rightShiftStage1_uid19934_dupName_321_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19934_dupName_321_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19929_dupName_321_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19932_dupName_321_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19934_dupName_321_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19934_dupName_321_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19929_dupName_321_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19934_dupName_321_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19932_dupName_321_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19934_dupName_321_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19939_dupName_321_i_unnamed_c_compstr0_shift_x(MUX,19938)@173
    assign rightShiftStage2_uid19939_dupName_321_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19939_dupName_321_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19934_dupName_321_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19937_dupName_321_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19939_dupName_321_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19939_dupName_321_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19934_dupName_321_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19939_dupName_321_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19937_dupName_321_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19939_dupName_321_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2277_vt_select_20(BITSELECT,10905)@173
    assign i_unnamed_c_compstr2277_vt_select_20_b = rightShiftStage2_uid19939_dupName_321_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2277_vt_join(BITJOIN,10904)@173
    assign i_unnamed_c_compstr2277_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2277_vt_select_20_b};

    // i_conv_i_i_i_i_i_80_c_compstr2278_sel_x(BITSELECT,3818)@173
    assign i_conv_i_i_i_i_i_80_c_compstr2278_sel_x_b = i_unnamed_c_compstr2277_vt_join_q[15:0];

    // redist1047_i_conv_i_i_i_i_i_80_c_compstr2278_sel_x_b_1(DELAY,29275)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1047_i_conv_i_i_i_i_i_80_c_compstr2278_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_80_c_compstr2278_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19948_dupName_322_i_unnamed_c_compstr0_shift_x(BITSELECT,19947)@173
    assign rightShiftStage1Idx1Rng8_uid19948_dupName_322_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19947_dupName_322_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19950_dupName_322_i_unnamed_c_compstr0_shift_x(BITJOIN,19949)@173
    assign rightShiftStage1Idx1_uid19950_dupName_322_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19948_dupName_322_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19943_dupName_322_i_unnamed_c_compstr0_shift_x(BITSELECT,19942)@173
    assign rightShiftStage0Idx1Rng4_uid19943_dupName_322_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_q[33:4];

    // rightShiftStage0Idx1_uid19945_dupName_322_i_unnamed_c_compstr0_shift_x(BITJOIN,19944)@173
    assign rightShiftStage0Idx1_uid19945_dupName_322_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19943_dupName_322_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19947_dupName_322_i_unnamed_c_compstr0_shift_x(MUX,19946)@173
    assign rightShiftStage0_uid19947_dupName_322_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19947_dupName_322_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_q or rightShiftStage0Idx1_uid19945_dupName_322_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19947_dupName_322_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19947_dupName_322_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compstr2276_q;
            1'b1 : rightShiftStage0_uid19947_dupName_322_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19945_dupName_322_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19947_dupName_322_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19952_dupName_322_i_unnamed_c_compstr0_shift_x(MUX,19951)@173
    assign rightShiftStage1_uid19952_dupName_322_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19952_dupName_322_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19947_dupName_322_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19950_dupName_322_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19952_dupName_322_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19952_dupName_322_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19947_dupName_322_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19952_dupName_322_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19950_dupName_322_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19952_dupName_322_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2279_vt_select_21(BITSELECT,10908)@173
    assign i_unnamed_c_compstr2279_vt_select_21_b = rightShiftStage1_uid19952_dupName_322_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2279_vt_join(BITJOIN,10907)@173
    assign i_unnamed_c_compstr2279_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2279_vt_select_21_b};

    // i_unnamed_c_compstr2280_sel_x(BITSELECT,6135)@173
    assign i_unnamed_c_compstr2280_sel_x_b = i_unnamed_c_compstr2279_vt_join_q[15:0];

    // i_unnamed_c_compstr2281_BitSelect_for_a(BITSELECT,27659)@173
    assign i_unnamed_c_compstr2281_BitSelect_for_a_b = i_unnamed_c_compstr2280_sel_x_b[0:0];

    // i_unnamed_c_compstr2281_join(BITJOIN,27660)@173
    assign i_unnamed_c_compstr2281_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2281_BitSelect_for_a_b};

    // i_unnamed_c_compstr2281_vt_select_0(BITSELECT,10913)@173
    assign i_unnamed_c_compstr2281_vt_select_0_b = i_unnamed_c_compstr2281_join_q[0:0];

    // redist155_i_unnamed_c_compstr2281_vt_select_0_b_1(DELAY,28383)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist155_i_unnamed_c_compstr2281_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2281_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2281_vt_join(BITJOIN,10912)@174
    assign i_unnamed_c_compstr2281_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist155_i_unnamed_c_compstr2281_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_80_c_compstr2282(ADD,7085)@174
    assign i_add_i_i_i_i_i_i_80_c_compstr2282_a = {1'b0, i_unnamed_c_compstr2281_vt_join_q};
    assign i_add_i_i_i_i_i_i_80_c_compstr2282_b = {1'b0, redist1047_i_conv_i_i_i_i_i_80_c_compstr2278_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_80_c_compstr2282_o = $unsigned(i_add_i_i_i_i_i_i_80_c_compstr2282_a) + $unsigned(i_add_i_i_i_i_i_i_80_c_compstr2282_b);
    assign i_add_i_i_i_i_i_i_80_c_compstr2282_q = i_add_i_i_i_i_i_i_80_c_compstr2282_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_80_c_compstr2282_sel_x(BITSELECT,2279)@174
    assign bgTrunc_i_add_i_i_i_i_i_i_80_c_compstr2282_sel_x_b = i_add_i_i_i_i_i_i_80_c_compstr2282_q[15:0];

    // i_conv_i_i_i_i_i_i279_81_c_compstr2302_sel_x(BITSELECT,3947)@174
    assign i_conv_i_i_i_i_i_i279_81_c_compstr2302_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_80_c_compstr2282_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_81_c_compstr2302_vt_select_15(BITSELECT,8305)@174
    assign i_conv_i_i_i_i_i_i279_81_c_compstr2302_vt_select_15_b = i_conv_i_i_i_i_i_i279_81_c_compstr2302_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_81_c_compstr2302_vt_join(BITJOIN,8304)@174
    assign i_conv_i_i_i_i_i_i279_81_c_compstr2302_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_81_c_compstr2302_vt_select_15_b};

    // leftShiftStage0_uid27068_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x(MUX,27067)@174
    assign leftShiftStage0_uid27068_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27068_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_81_c_compstr2302_vt_join_q or leftShiftStage0Idx1_uid27066_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27068_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27068_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_81_c_compstr2302_vt_join_q;
            1'b1 : leftShiftStage0_uid27068_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27066_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27068_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27073_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x(MUX,27072)@174
    assign leftShiftStage1_uid27073_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27073_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_s or leftShiftStage0_uid27068_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27071_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27073_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27073_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q = leftShiftStage0_uid27068_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27073_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27071_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27073_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27078_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x(MUX,27077)@174
    assign leftShiftStage2_uid27078_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27078_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_s or leftShiftStage1_uid27073_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27076_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27078_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27078_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q = leftShiftStage1_uid27073_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27078_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27076_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27078_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_81_c_compstr2303_vt_select_28(BITSELECT,9742)@174
    assign i_shl_i_i_i_i_i_i_81_c_compstr2303_vt_select_28_b = leftShiftStage2_uid27078_i_shl_i_i_i_i_i_i_81_c_compstr0_shift_x_q[28:13];

    // redist276_i_shl_i_i_i_i_i_i_81_c_compstr2303_vt_select_28_b_1(DELAY,28504)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist276_i_shl_i_i_i_i_i_i_81_c_compstr2303_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_81_c_compstr2303_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_81_c_compstr2303_vt_join(BITJOIN,9741)@175
    assign i_shl_i_i_i_i_i_i_81_c_compstr2303_vt_join_q = {redist276_i_shl_i_i_i_i_i_i_81_c_compstr2303_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_offset(CONSTANT,30510)
    assign redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_offset_q = $unsigned(8'b01100100);

    // redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_rdcnt(ADD,31959)
    assign redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_a = {1'b0, redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_wraddr_q};
    assign redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_b = {1'b0, redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_o <= $unsigned(redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_a) + $unsigned(redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_b);
        end
    end
    assign redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_q = redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_o[8:0];

    // redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_inputreg0(DELAY,31954)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl);
        end
    end

    // redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_wraddr(COUNTER,31957)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_wraddr_i <= $unsigned(redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_wraddr_q = redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_wraddr_i[7:0];

    // redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem(DUALMEM,31956)
    assign redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_ia = $unsigned(redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_inputreg0_q);
    assign redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_aa = redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_wraddr_q;
    assign redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_ab = redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_aa),
        .data_a(redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_ab),
        .q_b(redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_q = redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_iq[15:0];

    // redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_outputreg0(DELAY,31955)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_outputreg0_q <= $unsigned(redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_mem_q);
        end
    end

    // redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_rdcnt(ADD,30511)
    assign redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_a = {1'b0, redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_wraddr_q};
    assign redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_b = {1'b0, redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_o <= $unsigned(redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_a) + $unsigned(redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_b);
        end
    end
    assign redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_q = redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_o[8:0];

    // redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_inputreg0(DELAY,30506)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl);
        end
    end

    // redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_wraddr(COUNTER,30509)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_wraddr_i <= $unsigned(redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_wraddr_q = redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_wraddr_i[7:0];

    // redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem(DUALMEM,30508)
    assign redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_ia = $unsigned(redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_inputreg0_q);
    assign redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_aa = redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_wraddr_q;
    assign redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_ab = redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_aa),
        .data_a(redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_ab),
        .q_b(redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_q = redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_iq[15:0];

    // redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_outputreg0(DELAY,30507)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_outputreg0_q <= $unsigned(redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_mem_q);
        end
    end

    // redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_rdcnt(ADD,30517)
    assign redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_a = {1'b0, redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_wraddr_q};
    assign redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_b = {1'b0, redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_o <= $unsigned(redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_a) + $unsigned(redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_b);
        end
    end
    assign redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_q = redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_o[8:0];

    // redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_inputreg0(DELAY,30512)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl);
        end
    end

    // redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_wraddr(COUNTER,30515)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_wraddr_i <= $unsigned(redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_wraddr_q = redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_wraddr_i[7:0];

    // redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem(DUALMEM,30514)
    assign redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_ia = $unsigned(redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_inputreg0_q);
    assign redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_aa = redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_wraddr_q;
    assign redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_ab = redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_aa),
        .data_a(redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_ab),
        .q_b(redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_q = redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_iq[15:0];

    // redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_outputreg0(DELAY,30513)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_outputreg0_q <= $unsigned(redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_mem_q);
        end
    end

    // redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_rdcnt(ADD,31953)
    assign redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_a = {1'b0, redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_wraddr_q};
    assign redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_b = {1'b0, redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_o <= $unsigned(redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_a) + $unsigned(redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_b);
        end
    end
    assign redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_q = redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_o[8:0];

    // redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_inputreg0(DELAY,31948)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl);
        end
    end

    // redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_wraddr(COUNTER,31951)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_wraddr_i <= $unsigned(redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_wraddr_q = redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_wraddr_i[7:0];

    // redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem(DUALMEM,31950)
    assign redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_ia = $unsigned(redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_inputreg0_q);
    assign redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_aa = redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_wraddr_q;
    assign redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_ab = redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_aa),
        .data_a(redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_ab),
        .q_b(redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_q = redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_iq[15:0];

    // redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_outputreg0(DELAY,31949)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_outputreg0_q <= $unsigned(redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28040)@169 + 5
    // out q@175
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304(ADD,8628)@175
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod446_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_b = $unsigned({{5{i_shl_i_i_i_i_i_i_81_c_compstr2303_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_81_c_compstr2303_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_o[33:0];

    // rightShiftStage0_uid19991_dupName_325_i_unnamed_c_compstr0_shift_x(MUX,19990)@175
    assign rightShiftStage0_uid19991_dupName_325_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19991_dupName_325_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_q or rightShiftStage0Idx1_uid19989_dupName_325_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19991_dupName_325_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19991_dupName_325_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_q;
            1'b1 : rightShiftStage0_uid19991_dupName_325_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19989_dupName_325_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19991_dupName_325_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19996_dupName_325_i_unnamed_c_compstr0_shift_x(MUX,19995)@175
    assign rightShiftStage1_uid19996_dupName_325_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19996_dupName_325_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19991_dupName_325_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19994_dupName_325_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19996_dupName_325_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19996_dupName_325_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19991_dupName_325_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19996_dupName_325_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19994_dupName_325_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19996_dupName_325_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20001_dupName_325_i_unnamed_c_compstr0_shift_x(MUX,20000)@175
    assign rightShiftStage2_uid20001_dupName_325_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20001_dupName_325_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19996_dupName_325_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19999_dupName_325_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20001_dupName_325_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20001_dupName_325_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19996_dupName_325_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20001_dupName_325_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19999_dupName_325_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20001_dupName_325_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2305_vt_select_20(BITSELECT,10927)@175
    assign i_unnamed_c_compstr2305_vt_select_20_b = rightShiftStage2_uid20001_dupName_325_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2305_vt_join(BITJOIN,10926)@175
    assign i_unnamed_c_compstr2305_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2305_vt_select_20_b};

    // i_conv_i_i_i_i_i_81_c_compstr2306_sel_x(BITSELECT,3819)@175
    assign i_conv_i_i_i_i_i_81_c_compstr2306_sel_x_b = i_unnamed_c_compstr2305_vt_join_q[15:0];

    // redist1046_i_conv_i_i_i_i_i_81_c_compstr2306_sel_x_b_1(DELAY,29274)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1046_i_conv_i_i_i_i_i_81_c_compstr2306_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_81_c_compstr2306_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20010_dupName_326_i_unnamed_c_compstr0_shift_x(BITSELECT,20009)@175
    assign rightShiftStage1Idx1Rng8_uid20010_dupName_326_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20009_dupName_326_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20012_dupName_326_i_unnamed_c_compstr0_shift_x(BITJOIN,20011)@175
    assign rightShiftStage1Idx1_uid20012_dupName_326_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20010_dupName_326_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20005_dupName_326_i_unnamed_c_compstr0_shift_x(BITSELECT,20004)@175
    assign rightShiftStage0Idx1Rng4_uid20005_dupName_326_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_q[33:4];

    // rightShiftStage0Idx1_uid20007_dupName_326_i_unnamed_c_compstr0_shift_x(BITJOIN,20006)@175
    assign rightShiftStage0Idx1_uid20007_dupName_326_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20005_dupName_326_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20009_dupName_326_i_unnamed_c_compstr0_shift_x(MUX,20008)@175
    assign rightShiftStage0_uid20009_dupName_326_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20009_dupName_326_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_q or rightShiftStage0Idx1_uid20007_dupName_326_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20009_dupName_326_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20009_dupName_326_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compstr2304_q;
            1'b1 : rightShiftStage0_uid20009_dupName_326_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20007_dupName_326_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20009_dupName_326_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20014_dupName_326_i_unnamed_c_compstr0_shift_x(MUX,20013)@175
    assign rightShiftStage1_uid20014_dupName_326_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20014_dupName_326_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20009_dupName_326_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20012_dupName_326_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20014_dupName_326_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20014_dupName_326_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20009_dupName_326_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20014_dupName_326_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20012_dupName_326_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20014_dupName_326_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2307_vt_select_21(BITSELECT,10930)@175
    assign i_unnamed_c_compstr2307_vt_select_21_b = rightShiftStage1_uid20014_dupName_326_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2307_vt_join(BITJOIN,10929)@175
    assign i_unnamed_c_compstr2307_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2307_vt_select_21_b};

    // i_unnamed_c_compstr2308_sel_x(BITSELECT,6137)@175
    assign i_unnamed_c_compstr2308_sel_x_b = i_unnamed_c_compstr2307_vt_join_q[15:0];

    // i_unnamed_c_compstr2309_BitSelect_for_a(BITSELECT,27663)@175
    assign i_unnamed_c_compstr2309_BitSelect_for_a_b = i_unnamed_c_compstr2308_sel_x_b[0:0];

    // i_unnamed_c_compstr2309_join(BITJOIN,27664)@175
    assign i_unnamed_c_compstr2309_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2309_BitSelect_for_a_b};

    // i_unnamed_c_compstr2309_vt_select_0(BITSELECT,10935)@175
    assign i_unnamed_c_compstr2309_vt_select_0_b = i_unnamed_c_compstr2309_join_q[0:0];

    // redist153_i_unnamed_c_compstr2309_vt_select_0_b_1(DELAY,28381)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist153_i_unnamed_c_compstr2309_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2309_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2309_vt_join(BITJOIN,10934)@176
    assign i_unnamed_c_compstr2309_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist153_i_unnamed_c_compstr2309_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_81_c_compstr2310(ADD,7086)@176
    assign i_add_i_i_i_i_i_i_81_c_compstr2310_a = {1'b0, i_unnamed_c_compstr2309_vt_join_q};
    assign i_add_i_i_i_i_i_i_81_c_compstr2310_b = {1'b0, redist1046_i_conv_i_i_i_i_i_81_c_compstr2306_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_81_c_compstr2310_o = $unsigned(i_add_i_i_i_i_i_i_81_c_compstr2310_a) + $unsigned(i_add_i_i_i_i_i_i_81_c_compstr2310_b);
    assign i_add_i_i_i_i_i_i_81_c_compstr2310_q = i_add_i_i_i_i_i_i_81_c_compstr2310_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_81_c_compstr2310_sel_x(BITSELECT,2280)@176
    assign bgTrunc_i_add_i_i_i_i_i_i_81_c_compstr2310_sel_x_b = i_add_i_i_i_i_i_i_81_c_compstr2310_q[15:0];

    // i_conv_i_i_i_i_i_i279_82_c_compstr2330_sel_x(BITSELECT,3948)@176
    assign i_conv_i_i_i_i_i_i279_82_c_compstr2330_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_81_c_compstr2310_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_82_c_compstr2330_vt_select_15(BITSELECT,8309)@176
    assign i_conv_i_i_i_i_i_i279_82_c_compstr2330_vt_select_15_b = i_conv_i_i_i_i_i_i279_82_c_compstr2330_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_82_c_compstr2330_vt_join(BITJOIN,8308)@176
    assign i_conv_i_i_i_i_i_i279_82_c_compstr2330_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_82_c_compstr2330_vt_select_15_b};

    // leftShiftStage0_uid27086_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x(MUX,27085)@176
    assign leftShiftStage0_uid27086_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27086_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_82_c_compstr2330_vt_join_q or leftShiftStage0Idx1_uid27084_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27086_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27086_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_82_c_compstr2330_vt_join_q;
            1'b1 : leftShiftStage0_uid27086_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27084_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27086_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27091_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x(MUX,27090)@176
    assign leftShiftStage1_uid27091_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27091_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_s or leftShiftStage0_uid27086_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27089_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27091_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27091_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q = leftShiftStage0_uid27086_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27091_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27089_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27091_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27096_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x(MUX,27095)@176
    assign leftShiftStage2_uid27096_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27096_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_s or leftShiftStage1_uid27091_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27094_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27096_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27096_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q = leftShiftStage1_uid27091_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27096_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27094_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27096_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_82_c_compstr2331_vt_select_28(BITSELECT,9745)@176
    assign i_shl_i_i_i_i_i_i_82_c_compstr2331_vt_select_28_b = leftShiftStage2_uid27096_i_shl_i_i_i_i_i_i_82_c_compstr0_shift_x_q[28:13];

    // redist275_i_shl_i_i_i_i_i_i_82_c_compstr2331_vt_select_28_b_1(DELAY,28503)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist275_i_shl_i_i_i_i_i_i_82_c_compstr2331_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_82_c_compstr2331_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_82_c_compstr2331_vt_join(BITJOIN,9744)@177
    assign i_shl_i_i_i_i_i_i_82_c_compstr2331_vt_join_q = {redist275_i_shl_i_i_i_i_i_i_82_c_compstr2331_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_offset(CONSTANT,30522)
    assign redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_offset_q = $unsigned(8'b01100010);

    // redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_rdcnt(ADD,31971)
    assign redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_a = {1'b0, redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_wraddr_q};
    assign redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_b = {1'b0, redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_o <= $unsigned(redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_a) + $unsigned(redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_b);
        end
    end
    assign redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_q = redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_o[8:0];

    // redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_inputreg0(DELAY,31966)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl);
        end
    end

    // redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_wraddr(COUNTER,31969)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_wraddr_i <= $unsigned(redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_wraddr_q = redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_wraddr_i[7:0];

    // redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem(DUALMEM,31968)
    assign redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_ia = $unsigned(redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_inputreg0_q);
    assign redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_aa = redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_wraddr_q;
    assign redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_ab = redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_aa),
        .data_a(redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_ab),
        .q_b(redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_q = redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_iq[15:0];

    // redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_outputreg0(DELAY,31967)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_outputreg0_q <= $unsigned(redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_mem_q);
        end
    end

    // redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_rdcnt(ADD,30523)
    assign redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_a = {1'b0, redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_wraddr_q};
    assign redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_b = {1'b0, redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_o <= $unsigned(redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_a) + $unsigned(redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_b);
        end
    end
    assign redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_q = redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_o[8:0];

    // redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_inputreg0(DELAY,30518)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl);
        end
    end

    // redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_wraddr(COUNTER,30521)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_wraddr_i <= $unsigned(redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_wraddr_q = redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_wraddr_i[7:0];

    // redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem(DUALMEM,30520)
    assign redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_ia = $unsigned(redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_inputreg0_q);
    assign redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_aa = redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_wraddr_q;
    assign redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_ab = redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_aa),
        .data_a(redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_ab),
        .q_b(redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_q = redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_iq[15:0];

    // redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_outputreg0(DELAY,30519)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_outputreg0_q <= $unsigned(redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_mem_q);
        end
    end

    // redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_rdcnt(ADD,30529)
    assign redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_a = {1'b0, redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_wraddr_q};
    assign redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_b = {1'b0, redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_o <= $unsigned(redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_a) + $unsigned(redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_b);
        end
    end
    assign redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_q = redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_o[8:0];

    // redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_inputreg0(DELAY,30524)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl);
        end
    end

    // redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_wraddr(COUNTER,30527)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_wraddr_i <= $unsigned(redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_wraddr_q = redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_wraddr_i[7:0];

    // redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem(DUALMEM,30526)
    assign redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_ia = $unsigned(redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_inputreg0_q);
    assign redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_aa = redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_wraddr_q;
    assign redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_ab = redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_aa),
        .data_a(redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_ab),
        .q_b(redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_q = redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_iq[15:0];

    // redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_outputreg0(DELAY,30525)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_outputreg0_q <= $unsigned(redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_mem_q);
        end
    end

    // redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_rdcnt(ADD,31965)
    assign redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_a = {1'b0, redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_wraddr_q};
    assign redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_b = {1'b0, redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_o <= $unsigned(redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_a) + $unsigned(redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_b);
        end
    end
    assign redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_q = redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_o[8:0];

    // redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_inputreg0(DELAY,31960)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl);
        end
    end

    // redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_wraddr(COUNTER,31963)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_wraddr_i <= $unsigned(redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_wraddr_q = redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_wraddr_i[7:0];

    // redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem(DUALMEM,31962)
    assign redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_ia = $unsigned(redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_inputreg0_q);
    assign redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_aa = redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_wraddr_q;
    assign redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_ab = redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_aa),
        .data_a(redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_ab),
        .q_b(redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_q = redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_iq[15:0];

    // redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_outputreg0(DELAY,31961)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_outputreg0_q <= $unsigned(redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28041)@171 + 5
    // out q@177
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332(ADD,8629)@177
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod451_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_b = $unsigned({{5{i_shl_i_i_i_i_i_i_82_c_compstr2331_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_82_c_compstr2331_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_o[33:0];

    // rightShiftStage0_uid20053_dupName_329_i_unnamed_c_compstr0_shift_x(MUX,20052)@177
    assign rightShiftStage0_uid20053_dupName_329_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20053_dupName_329_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_q or rightShiftStage0Idx1_uid20051_dupName_329_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20053_dupName_329_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20053_dupName_329_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_q;
            1'b1 : rightShiftStage0_uid20053_dupName_329_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20051_dupName_329_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20053_dupName_329_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20058_dupName_329_i_unnamed_c_compstr0_shift_x(MUX,20057)@177
    assign rightShiftStage1_uid20058_dupName_329_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20058_dupName_329_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20053_dupName_329_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20056_dupName_329_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20058_dupName_329_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20058_dupName_329_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20053_dupName_329_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20058_dupName_329_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20056_dupName_329_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20058_dupName_329_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20063_dupName_329_i_unnamed_c_compstr0_shift_x(MUX,20062)@177
    assign rightShiftStage2_uid20063_dupName_329_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20063_dupName_329_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20058_dupName_329_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20061_dupName_329_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20063_dupName_329_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20063_dupName_329_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20058_dupName_329_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20063_dupName_329_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20061_dupName_329_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20063_dupName_329_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2333_vt_select_20(BITSELECT,10949)@177
    assign i_unnamed_c_compstr2333_vt_select_20_b = rightShiftStage2_uid20063_dupName_329_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2333_vt_join(BITJOIN,10948)@177
    assign i_unnamed_c_compstr2333_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2333_vt_select_20_b};

    // i_conv_i_i_i_i_i_82_c_compstr2334_sel_x(BITSELECT,3820)@177
    assign i_conv_i_i_i_i_i_82_c_compstr2334_sel_x_b = i_unnamed_c_compstr2333_vt_join_q[15:0];

    // redist1045_i_conv_i_i_i_i_i_82_c_compstr2334_sel_x_b_1(DELAY,29273)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1045_i_conv_i_i_i_i_i_82_c_compstr2334_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_82_c_compstr2334_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20072_dupName_330_i_unnamed_c_compstr0_shift_x(BITSELECT,20071)@177
    assign rightShiftStage1Idx1Rng8_uid20072_dupName_330_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20071_dupName_330_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20074_dupName_330_i_unnamed_c_compstr0_shift_x(BITJOIN,20073)@177
    assign rightShiftStage1Idx1_uid20074_dupName_330_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20072_dupName_330_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20067_dupName_330_i_unnamed_c_compstr0_shift_x(BITSELECT,20066)@177
    assign rightShiftStage0Idx1Rng4_uid20067_dupName_330_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_q[33:4];

    // rightShiftStage0Idx1_uid20069_dupName_330_i_unnamed_c_compstr0_shift_x(BITJOIN,20068)@177
    assign rightShiftStage0Idx1_uid20069_dupName_330_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20067_dupName_330_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20071_dupName_330_i_unnamed_c_compstr0_shift_x(MUX,20070)@177
    assign rightShiftStage0_uid20071_dupName_330_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20071_dupName_330_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_q or rightShiftStage0Idx1_uid20069_dupName_330_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20071_dupName_330_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20071_dupName_330_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compstr2332_q;
            1'b1 : rightShiftStage0_uid20071_dupName_330_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20069_dupName_330_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20071_dupName_330_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20076_dupName_330_i_unnamed_c_compstr0_shift_x(MUX,20075)@177
    assign rightShiftStage1_uid20076_dupName_330_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20076_dupName_330_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20071_dupName_330_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20074_dupName_330_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20076_dupName_330_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20076_dupName_330_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20071_dupName_330_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20076_dupName_330_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20074_dupName_330_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20076_dupName_330_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2335_vt_select_21(BITSELECT,10952)@177
    assign i_unnamed_c_compstr2335_vt_select_21_b = rightShiftStage1_uid20076_dupName_330_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2335_vt_join(BITJOIN,10951)@177
    assign i_unnamed_c_compstr2335_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2335_vt_select_21_b};

    // i_unnamed_c_compstr2336_sel_x(BITSELECT,6139)@177
    assign i_unnamed_c_compstr2336_sel_x_b = i_unnamed_c_compstr2335_vt_join_q[15:0];

    // i_unnamed_c_compstr2337_BitSelect_for_a(BITSELECT,27667)@177
    assign i_unnamed_c_compstr2337_BitSelect_for_a_b = i_unnamed_c_compstr2336_sel_x_b[0:0];

    // i_unnamed_c_compstr2337_join(BITJOIN,27668)@177
    assign i_unnamed_c_compstr2337_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2337_BitSelect_for_a_b};

    // i_unnamed_c_compstr2337_vt_select_0(BITSELECT,10957)@177
    assign i_unnamed_c_compstr2337_vt_select_0_b = i_unnamed_c_compstr2337_join_q[0:0];

    // redist151_i_unnamed_c_compstr2337_vt_select_0_b_1(DELAY,28379)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist151_i_unnamed_c_compstr2337_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2337_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2337_vt_join(BITJOIN,10956)@178
    assign i_unnamed_c_compstr2337_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist151_i_unnamed_c_compstr2337_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_82_c_compstr2338(ADD,7087)@178
    assign i_add_i_i_i_i_i_i_82_c_compstr2338_a = {1'b0, i_unnamed_c_compstr2337_vt_join_q};
    assign i_add_i_i_i_i_i_i_82_c_compstr2338_b = {1'b0, redist1045_i_conv_i_i_i_i_i_82_c_compstr2334_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_82_c_compstr2338_o = $unsigned(i_add_i_i_i_i_i_i_82_c_compstr2338_a) + $unsigned(i_add_i_i_i_i_i_i_82_c_compstr2338_b);
    assign i_add_i_i_i_i_i_i_82_c_compstr2338_q = i_add_i_i_i_i_i_i_82_c_compstr2338_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_82_c_compstr2338_sel_x(BITSELECT,2281)@178
    assign bgTrunc_i_add_i_i_i_i_i_i_82_c_compstr2338_sel_x_b = i_add_i_i_i_i_i_i_82_c_compstr2338_q[15:0];

    // i_conv_i_i_i_i_i_i279_83_c_compstr2358_sel_x(BITSELECT,3949)@178
    assign i_conv_i_i_i_i_i_i279_83_c_compstr2358_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_82_c_compstr2338_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_83_c_compstr2358_vt_select_15(BITSELECT,8313)@178
    assign i_conv_i_i_i_i_i_i279_83_c_compstr2358_vt_select_15_b = i_conv_i_i_i_i_i_i279_83_c_compstr2358_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_83_c_compstr2358_vt_join(BITJOIN,8312)@178
    assign i_conv_i_i_i_i_i_i279_83_c_compstr2358_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_83_c_compstr2358_vt_select_15_b};

    // leftShiftStage0_uid27104_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x(MUX,27103)@178
    assign leftShiftStage0_uid27104_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27104_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_83_c_compstr2358_vt_join_q or leftShiftStage0Idx1_uid27102_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27104_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27104_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_83_c_compstr2358_vt_join_q;
            1'b1 : leftShiftStage0_uid27104_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27102_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27104_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27109_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x(MUX,27108)@178
    assign leftShiftStage1_uid27109_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27109_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_s or leftShiftStage0_uid27104_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27107_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27109_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27109_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q = leftShiftStage0_uid27104_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27109_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27107_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27109_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27114_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x(MUX,27113)@178
    assign leftShiftStage2_uid27114_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27114_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_s or leftShiftStage1_uid27109_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27112_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27114_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27114_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q = leftShiftStage1_uid27109_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27114_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27112_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27114_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_83_c_compstr2359_vt_select_28(BITSELECT,9748)@178
    assign i_shl_i_i_i_i_i_i_83_c_compstr2359_vt_select_28_b = leftShiftStage2_uid27114_i_shl_i_i_i_i_i_i_83_c_compstr0_shift_x_q[28:13];

    // redist274_i_shl_i_i_i_i_i_i_83_c_compstr2359_vt_select_28_b_1(DELAY,28502)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist274_i_shl_i_i_i_i_i_i_83_c_compstr2359_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_83_c_compstr2359_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_83_c_compstr2359_vt_join(BITJOIN,9747)@179
    assign i_shl_i_i_i_i_i_i_83_c_compstr2359_vt_join_q = {redist274_i_shl_i_i_i_i_i_i_83_c_compstr2359_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_offset(CONSTANT,30534)
    assign redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_offset_q = $unsigned(8'b01100000);

    // redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_rdcnt(ADD,31983)
    assign redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_a = {1'b0, redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_wraddr_q};
    assign redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_b = {1'b0, redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_o <= $unsigned(redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_a) + $unsigned(redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_b);
        end
    end
    assign redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_q = redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_o[8:0];

    // redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_inputreg0(DELAY,31978)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl);
        end
    end

    // redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_wraddr(COUNTER,31981)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_wraddr_i <= $unsigned(redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_wraddr_q = redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_wraddr_i[7:0];

    // redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem(DUALMEM,31980)
    assign redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_ia = $unsigned(redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_inputreg0_q);
    assign redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_aa = redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_wraddr_q;
    assign redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_ab = redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_aa),
        .data_a(redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_ab),
        .q_b(redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_q = redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_iq[15:0];

    // redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_outputreg0(DELAY,31979)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_outputreg0_q <= $unsigned(redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_mem_q);
        end
    end

    // redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_rdcnt(ADD,30535)
    assign redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_a = {1'b0, redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_wraddr_q};
    assign redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_b = {1'b0, redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_o <= $unsigned(redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_a) + $unsigned(redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_b);
        end
    end
    assign redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_q = redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_o[8:0];

    // redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_inputreg0(DELAY,30530)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl);
        end
    end

    // redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_wraddr(COUNTER,30533)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_wraddr_i <= $unsigned(redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_wraddr_q = redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_wraddr_i[7:0];

    // redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem(DUALMEM,30532)
    assign redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_ia = $unsigned(redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_inputreg0_q);
    assign redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_aa = redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_wraddr_q;
    assign redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_ab = redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_aa),
        .data_a(redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_ab),
        .q_b(redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_q = redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_iq[15:0];

    // redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_outputreg0(DELAY,30531)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_outputreg0_q <= $unsigned(redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_mem_q);
        end
    end

    // redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_rdcnt(ADD,30541)
    assign redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_a = {1'b0, redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_wraddr_q};
    assign redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_b = {1'b0, redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_o <= $unsigned(redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_a) + $unsigned(redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_b);
        end
    end
    assign redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_q = redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_o[8:0];

    // redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_inputreg0(DELAY,30536)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl);
        end
    end

    // redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_wraddr(COUNTER,30539)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_wraddr_i <= $unsigned(redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_wraddr_q = redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_wraddr_i[7:0];

    // redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem(DUALMEM,30538)
    assign redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_ia = $unsigned(redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_inputreg0_q);
    assign redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_aa = redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_wraddr_q;
    assign redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_ab = redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_aa),
        .data_a(redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_ab),
        .q_b(redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_q = redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_iq[15:0];

    // redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_outputreg0(DELAY,30537)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_outputreg0_q <= $unsigned(redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_mem_q);
        end
    end

    // redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_rdcnt(ADD,31977)
    assign redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_a = {1'b0, redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_wraddr_q};
    assign redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_b = {1'b0, redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_o <= $unsigned(redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_a) + $unsigned(redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_b);
        end
    end
    assign redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_q = redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_o[8:0];

    // redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_inputreg0(DELAY,31972)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl);
        end
    end

    // redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_wraddr(COUNTER,31975)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_wraddr_i <= $unsigned(redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_wraddr_q = redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_wraddr_i[7:0];

    // redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem(DUALMEM,31974)
    assign redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_ia = $unsigned(redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_inputreg0_q);
    assign redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_aa = redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_wraddr_q;
    assign redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_ab = redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_aa),
        .data_a(redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_ab),
        .q_b(redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_q = redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_iq[15:0];

    // redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_outputreg0(DELAY,31973)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_outputreg0_q <= $unsigned(redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28042)@173 + 5
    // out q@179
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360(ADD,8630)@179
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod456_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_b = $unsigned({{5{i_shl_i_i_i_i_i_i_83_c_compstr2359_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_83_c_compstr2359_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_o[33:0];

    // rightShiftStage0_uid20115_dupName_333_i_unnamed_c_compstr0_shift_x(MUX,20114)@179
    assign rightShiftStage0_uid20115_dupName_333_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20115_dupName_333_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_q or rightShiftStage0Idx1_uid20113_dupName_333_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20115_dupName_333_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20115_dupName_333_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_q;
            1'b1 : rightShiftStage0_uid20115_dupName_333_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20113_dupName_333_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20115_dupName_333_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20120_dupName_333_i_unnamed_c_compstr0_shift_x(MUX,20119)@179
    assign rightShiftStage1_uid20120_dupName_333_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20120_dupName_333_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20115_dupName_333_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20118_dupName_333_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20120_dupName_333_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20120_dupName_333_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20115_dupName_333_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20120_dupName_333_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20118_dupName_333_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20120_dupName_333_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20125_dupName_333_i_unnamed_c_compstr0_shift_x(MUX,20124)@179
    assign rightShiftStage2_uid20125_dupName_333_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20125_dupName_333_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20120_dupName_333_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20123_dupName_333_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20125_dupName_333_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20125_dupName_333_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20120_dupName_333_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20125_dupName_333_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20123_dupName_333_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20125_dupName_333_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2361_vt_select_20(BITSELECT,10977)@179
    assign i_unnamed_c_compstr2361_vt_select_20_b = rightShiftStage2_uid20125_dupName_333_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2361_vt_join(BITJOIN,10976)@179
    assign i_unnamed_c_compstr2361_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2361_vt_select_20_b};

    // i_conv_i_i_i_i_i_83_c_compstr2362_sel_x(BITSELECT,3821)@179
    assign i_conv_i_i_i_i_i_83_c_compstr2362_sel_x_b = i_unnamed_c_compstr2361_vt_join_q[15:0];

    // redist1044_i_conv_i_i_i_i_i_83_c_compstr2362_sel_x_b_1(DELAY,29272)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1044_i_conv_i_i_i_i_i_83_c_compstr2362_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_83_c_compstr2362_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20134_dupName_334_i_unnamed_c_compstr0_shift_x(BITSELECT,20133)@179
    assign rightShiftStage1Idx1Rng8_uid20134_dupName_334_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20133_dupName_334_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20136_dupName_334_i_unnamed_c_compstr0_shift_x(BITJOIN,20135)@179
    assign rightShiftStage1Idx1_uid20136_dupName_334_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20134_dupName_334_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20129_dupName_334_i_unnamed_c_compstr0_shift_x(BITSELECT,20128)@179
    assign rightShiftStage0Idx1Rng4_uid20129_dupName_334_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_q[33:4];

    // rightShiftStage0Idx1_uid20131_dupName_334_i_unnamed_c_compstr0_shift_x(BITJOIN,20130)@179
    assign rightShiftStage0Idx1_uid20131_dupName_334_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20129_dupName_334_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20133_dupName_334_i_unnamed_c_compstr0_shift_x(MUX,20132)@179
    assign rightShiftStage0_uid20133_dupName_334_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20133_dupName_334_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_q or rightShiftStage0Idx1_uid20131_dupName_334_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20133_dupName_334_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20133_dupName_334_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compstr2360_q;
            1'b1 : rightShiftStage0_uid20133_dupName_334_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20131_dupName_334_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20133_dupName_334_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20138_dupName_334_i_unnamed_c_compstr0_shift_x(MUX,20137)@179
    assign rightShiftStage1_uid20138_dupName_334_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20138_dupName_334_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20133_dupName_334_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20136_dupName_334_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20138_dupName_334_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20138_dupName_334_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20133_dupName_334_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20138_dupName_334_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20136_dupName_334_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20138_dupName_334_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2363_vt_select_21(BITSELECT,10980)@179
    assign i_unnamed_c_compstr2363_vt_select_21_b = rightShiftStage1_uid20138_dupName_334_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2363_vt_join(BITJOIN,10979)@179
    assign i_unnamed_c_compstr2363_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2363_vt_select_21_b};

    // i_unnamed_c_compstr2364_sel_x(BITSELECT,6142)@179
    assign i_unnamed_c_compstr2364_sel_x_b = i_unnamed_c_compstr2363_vt_join_q[15:0];

    // i_unnamed_c_compstr2365_BitSelect_for_a(BITSELECT,27671)@179
    assign i_unnamed_c_compstr2365_BitSelect_for_a_b = i_unnamed_c_compstr2364_sel_x_b[0:0];

    // i_unnamed_c_compstr2365_join(BITJOIN,27672)@179
    assign i_unnamed_c_compstr2365_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2365_BitSelect_for_a_b};

    // i_unnamed_c_compstr2365_vt_select_0(BITSELECT,10985)@179
    assign i_unnamed_c_compstr2365_vt_select_0_b = i_unnamed_c_compstr2365_join_q[0:0];

    // redist149_i_unnamed_c_compstr2365_vt_select_0_b_1(DELAY,28377)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist149_i_unnamed_c_compstr2365_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2365_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2365_vt_join(BITJOIN,10984)@180
    assign i_unnamed_c_compstr2365_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist149_i_unnamed_c_compstr2365_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_83_c_compstr2366(ADD,7088)@180
    assign i_add_i_i_i_i_i_i_83_c_compstr2366_a = {1'b0, i_unnamed_c_compstr2365_vt_join_q};
    assign i_add_i_i_i_i_i_i_83_c_compstr2366_b = {1'b0, redist1044_i_conv_i_i_i_i_i_83_c_compstr2362_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_83_c_compstr2366_o = $unsigned(i_add_i_i_i_i_i_i_83_c_compstr2366_a) + $unsigned(i_add_i_i_i_i_i_i_83_c_compstr2366_b);
    assign i_add_i_i_i_i_i_i_83_c_compstr2366_q = i_add_i_i_i_i_i_i_83_c_compstr2366_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_83_c_compstr2366_sel_x(BITSELECT,2282)@180
    assign bgTrunc_i_add_i_i_i_i_i_i_83_c_compstr2366_sel_x_b = i_add_i_i_i_i_i_i_83_c_compstr2366_q[15:0];

    // i_conv_i_i_i_i_i_i279_84_c_compstr2386_sel_x(BITSELECT,3950)@180
    assign i_conv_i_i_i_i_i_i279_84_c_compstr2386_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_83_c_compstr2366_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_84_c_compstr2386_vt_select_15(BITSELECT,8317)@180
    assign i_conv_i_i_i_i_i_i279_84_c_compstr2386_vt_select_15_b = i_conv_i_i_i_i_i_i279_84_c_compstr2386_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_84_c_compstr2386_vt_join(BITJOIN,8316)@180
    assign i_conv_i_i_i_i_i_i279_84_c_compstr2386_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_84_c_compstr2386_vt_select_15_b};

    // leftShiftStage0_uid27122_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x(MUX,27121)@180
    assign leftShiftStage0_uid27122_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27122_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_84_c_compstr2386_vt_join_q or leftShiftStage0Idx1_uid27120_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27122_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27122_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_84_c_compstr2386_vt_join_q;
            1'b1 : leftShiftStage0_uid27122_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27120_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27122_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27127_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x(MUX,27126)@180
    assign leftShiftStage1_uid27127_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27127_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_s or leftShiftStage0_uid27122_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27125_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27127_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27127_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q = leftShiftStage0_uid27122_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27127_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27125_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27127_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27132_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x(MUX,27131)@180
    assign leftShiftStage2_uid27132_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27132_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_s or leftShiftStage1_uid27127_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27130_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27132_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27132_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q = leftShiftStage1_uid27127_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27132_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27130_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27132_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_84_c_compstr2387_vt_select_28(BITSELECT,9751)@180
    assign i_shl_i_i_i_i_i_i_84_c_compstr2387_vt_select_28_b = leftShiftStage2_uid27132_i_shl_i_i_i_i_i_i_84_c_compstr0_shift_x_q[28:13];

    // redist273_i_shl_i_i_i_i_i_i_84_c_compstr2387_vt_select_28_b_1(DELAY,28501)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist273_i_shl_i_i_i_i_i_i_84_c_compstr2387_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_84_c_compstr2387_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_84_c_compstr2387_vt_join(BITJOIN,9750)@181
    assign i_shl_i_i_i_i_i_i_84_c_compstr2387_vt_join_q = {redist273_i_shl_i_i_i_i_i_i_84_c_compstr2387_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_offset(CONSTANT,30546)
    assign redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_offset_q = $unsigned(8'b01011110);

    // redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_rdcnt(ADD,31995)
    assign redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_a = {1'b0, redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_wraddr_q};
    assign redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_b = {1'b0, redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_o <= $unsigned(redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_a) + $unsigned(redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_b);
        end
    end
    assign redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_q = redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_o[8:0];

    // redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_inputreg0(DELAY,31990)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl);
        end
    end

    // redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_wraddr(COUNTER,31993)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_wraddr_i <= $unsigned(redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_wraddr_q = redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_wraddr_i[7:0];

    // redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem(DUALMEM,31992)
    assign redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_ia = $unsigned(redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_inputreg0_q);
    assign redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_aa = redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_wraddr_q;
    assign redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_ab = redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_aa),
        .data_a(redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_ab),
        .q_b(redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_q = redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_iq[15:0];

    // redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_outputreg0(DELAY,31991)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_outputreg0_q <= $unsigned(redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_mem_q);
        end
    end

    // redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_rdcnt(ADD,30547)
    assign redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_a = {1'b0, redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_wraddr_q};
    assign redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_b = {1'b0, redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_o <= $unsigned(redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_a) + $unsigned(redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_b);
        end
    end
    assign redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_q = redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_o[8:0];

    // redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_inputreg0(DELAY,30542)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl);
        end
    end

    // redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_wraddr(COUNTER,30545)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_wraddr_i <= $unsigned(redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_wraddr_q = redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_wraddr_i[7:0];

    // redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem(DUALMEM,30544)
    assign redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_ia = $unsigned(redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_inputreg0_q);
    assign redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_aa = redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_wraddr_q;
    assign redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_ab = redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_aa),
        .data_a(redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_ab),
        .q_b(redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_q = redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_iq[15:0];

    // redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_outputreg0(DELAY,30543)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_outputreg0_q <= $unsigned(redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_mem_q);
        end
    end

    // redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_rdcnt(ADD,30553)
    assign redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_a = {1'b0, redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_wraddr_q};
    assign redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_b = {1'b0, redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_o <= $unsigned(redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_a) + $unsigned(redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_b);
        end
    end
    assign redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_q = redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_o[8:0];

    // redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_inputreg0(DELAY,30548)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl);
        end
    end

    // redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_wraddr(COUNTER,30551)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_wraddr_i <= $unsigned(redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_wraddr_q = redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_wraddr_i[7:0];

    // redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem(DUALMEM,30550)
    assign redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_ia = $unsigned(redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_inputreg0_q);
    assign redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_aa = redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_wraddr_q;
    assign redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_ab = redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_aa),
        .data_a(redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_ab),
        .q_b(redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_q = redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_iq[15:0];

    // redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_outputreg0(DELAY,30549)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_outputreg0_q <= $unsigned(redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_mem_q);
        end
    end

    // redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_rdcnt(ADD,31989)
    assign redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_a = {1'b0, redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_wraddr_q};
    assign redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_b = {1'b0, redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_o <= $unsigned(redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_a) + $unsigned(redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_b);
        end
    end
    assign redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_q = redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_o[8:0];

    // redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_inputreg0(DELAY,31984)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl);
        end
    end

    // redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_wraddr(COUNTER,31987)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_wraddr_i <= $unsigned(redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_wraddr_q = redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_wraddr_i[7:0];

    // redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem(DUALMEM,31986)
    assign redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_ia = $unsigned(redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_inputreg0_q);
    assign redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_aa = redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_wraddr_q;
    assign redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_ab = redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_aa),
        .data_a(redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_ab),
        .q_b(redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_q = redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_iq[15:0];

    // redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_outputreg0(DELAY,31985)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_outputreg0_q <= $unsigned(redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28043)@175 + 5
    // out q@181
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388(ADD,8631)@181
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod461_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_b = $unsigned({{5{i_shl_i_i_i_i_i_i_84_c_compstr2387_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_84_c_compstr2387_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_o[33:0];

    // rightShiftStage0_uid20177_dupName_337_i_unnamed_c_compstr0_shift_x(MUX,20176)@181
    assign rightShiftStage0_uid20177_dupName_337_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20177_dupName_337_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_q or rightShiftStage0Idx1_uid20175_dupName_337_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20177_dupName_337_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20177_dupName_337_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_q;
            1'b1 : rightShiftStage0_uid20177_dupName_337_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20175_dupName_337_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20177_dupName_337_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20182_dupName_337_i_unnamed_c_compstr0_shift_x(MUX,20181)@181
    assign rightShiftStage1_uid20182_dupName_337_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20182_dupName_337_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20177_dupName_337_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20180_dupName_337_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20182_dupName_337_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20182_dupName_337_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20177_dupName_337_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20182_dupName_337_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20180_dupName_337_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20182_dupName_337_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20187_dupName_337_i_unnamed_c_compstr0_shift_x(MUX,20186)@181
    assign rightShiftStage2_uid20187_dupName_337_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20187_dupName_337_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20182_dupName_337_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20185_dupName_337_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20187_dupName_337_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20187_dupName_337_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20182_dupName_337_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20187_dupName_337_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20185_dupName_337_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20187_dupName_337_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2389_vt_select_20(BITSELECT,11004)@181
    assign i_unnamed_c_compstr2389_vt_select_20_b = rightShiftStage2_uid20187_dupName_337_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2389_vt_join(BITJOIN,11003)@181
    assign i_unnamed_c_compstr2389_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2389_vt_select_20_b};

    // i_conv_i_i_i_i_i_84_c_compstr2390_sel_x(BITSELECT,3822)@181
    assign i_conv_i_i_i_i_i_84_c_compstr2390_sel_x_b = i_unnamed_c_compstr2389_vt_join_q[15:0];

    // redist1043_i_conv_i_i_i_i_i_84_c_compstr2390_sel_x_b_1(DELAY,29271)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1043_i_conv_i_i_i_i_i_84_c_compstr2390_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_84_c_compstr2390_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20196_dupName_338_i_unnamed_c_compstr0_shift_x(BITSELECT,20195)@181
    assign rightShiftStage1Idx1Rng8_uid20196_dupName_338_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20195_dupName_338_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20198_dupName_338_i_unnamed_c_compstr0_shift_x(BITJOIN,20197)@181
    assign rightShiftStage1Idx1_uid20198_dupName_338_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20196_dupName_338_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20191_dupName_338_i_unnamed_c_compstr0_shift_x(BITSELECT,20190)@181
    assign rightShiftStage0Idx1Rng4_uid20191_dupName_338_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_q[33:4];

    // rightShiftStage0Idx1_uid20193_dupName_338_i_unnamed_c_compstr0_shift_x(BITJOIN,20192)@181
    assign rightShiftStage0Idx1_uid20193_dupName_338_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20191_dupName_338_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20195_dupName_338_i_unnamed_c_compstr0_shift_x(MUX,20194)@181
    assign rightShiftStage0_uid20195_dupName_338_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20195_dupName_338_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_q or rightShiftStage0Idx1_uid20193_dupName_338_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20195_dupName_338_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20195_dupName_338_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compstr2388_q;
            1'b1 : rightShiftStage0_uid20195_dupName_338_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20193_dupName_338_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20195_dupName_338_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20200_dupName_338_i_unnamed_c_compstr0_shift_x(MUX,20199)@181
    assign rightShiftStage1_uid20200_dupName_338_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20200_dupName_338_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20195_dupName_338_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20198_dupName_338_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20200_dupName_338_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20200_dupName_338_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20195_dupName_338_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20200_dupName_338_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20198_dupName_338_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20200_dupName_338_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2391_vt_select_21(BITSELECT,11007)@181
    assign i_unnamed_c_compstr2391_vt_select_21_b = rightShiftStage1_uid20200_dupName_338_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2391_vt_join(BITJOIN,11006)@181
    assign i_unnamed_c_compstr2391_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2391_vt_select_21_b};

    // i_unnamed_c_compstr2392_sel_x(BITSELECT,6144)@181
    assign i_unnamed_c_compstr2392_sel_x_b = i_unnamed_c_compstr2391_vt_join_q[15:0];

    // i_unnamed_c_compstr2393_BitSelect_for_a(BITSELECT,27677)@181
    assign i_unnamed_c_compstr2393_BitSelect_for_a_b = i_unnamed_c_compstr2392_sel_x_b[0:0];

    // i_unnamed_c_compstr2393_join(BITJOIN,27678)@181
    assign i_unnamed_c_compstr2393_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2393_BitSelect_for_a_b};

    // i_unnamed_c_compstr2393_vt_select_0(BITSELECT,11012)@181
    assign i_unnamed_c_compstr2393_vt_select_0_b = i_unnamed_c_compstr2393_join_q[0:0];

    // redist146_i_unnamed_c_compstr2393_vt_select_0_b_1(DELAY,28374)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist146_i_unnamed_c_compstr2393_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2393_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2393_vt_join(BITJOIN,11011)@182
    assign i_unnamed_c_compstr2393_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist146_i_unnamed_c_compstr2393_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_84_c_compstr2394(ADD,7089)@182
    assign i_add_i_i_i_i_i_i_84_c_compstr2394_a = {1'b0, i_unnamed_c_compstr2393_vt_join_q};
    assign i_add_i_i_i_i_i_i_84_c_compstr2394_b = {1'b0, redist1043_i_conv_i_i_i_i_i_84_c_compstr2390_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_84_c_compstr2394_o = $unsigned(i_add_i_i_i_i_i_i_84_c_compstr2394_a) + $unsigned(i_add_i_i_i_i_i_i_84_c_compstr2394_b);
    assign i_add_i_i_i_i_i_i_84_c_compstr2394_q = i_add_i_i_i_i_i_i_84_c_compstr2394_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_84_c_compstr2394_sel_x(BITSELECT,2283)@182
    assign bgTrunc_i_add_i_i_i_i_i_i_84_c_compstr2394_sel_x_b = i_add_i_i_i_i_i_i_84_c_compstr2394_q[15:0];

    // i_conv_i_i_i_i_i_i279_85_c_compstr2414_sel_x(BITSELECT,3951)@182
    assign i_conv_i_i_i_i_i_i279_85_c_compstr2414_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_84_c_compstr2394_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_85_c_compstr2414_vt_select_15(BITSELECT,8321)@182
    assign i_conv_i_i_i_i_i_i279_85_c_compstr2414_vt_select_15_b = i_conv_i_i_i_i_i_i279_85_c_compstr2414_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_85_c_compstr2414_vt_join(BITJOIN,8320)@182
    assign i_conv_i_i_i_i_i_i279_85_c_compstr2414_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_85_c_compstr2414_vt_select_15_b};

    // leftShiftStage0_uid27140_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x(MUX,27139)@182
    assign leftShiftStage0_uid27140_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27140_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_85_c_compstr2414_vt_join_q or leftShiftStage0Idx1_uid27138_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27140_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27140_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_85_c_compstr2414_vt_join_q;
            1'b1 : leftShiftStage0_uid27140_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27138_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27140_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27145_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x(MUX,27144)@182
    assign leftShiftStage1_uid27145_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27145_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_s or leftShiftStage0_uid27140_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27143_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27145_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27145_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q = leftShiftStage0_uid27140_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27145_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27143_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27145_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27150_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x(MUX,27149)@182
    assign leftShiftStage2_uid27150_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27150_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_s or leftShiftStage1_uid27145_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27148_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27150_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27150_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q = leftShiftStage1_uid27145_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27150_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27148_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27150_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_85_c_compstr2415_vt_select_28(BITSELECT,9754)@182
    assign i_shl_i_i_i_i_i_i_85_c_compstr2415_vt_select_28_b = leftShiftStage2_uid27150_i_shl_i_i_i_i_i_i_85_c_compstr0_shift_x_q[28:13];

    // redist272_i_shl_i_i_i_i_i_i_85_c_compstr2415_vt_select_28_b_1(DELAY,28500)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist272_i_shl_i_i_i_i_i_i_85_c_compstr2415_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_85_c_compstr2415_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_85_c_compstr2415_vt_join(BITJOIN,9753)@183
    assign i_shl_i_i_i_i_i_i_85_c_compstr2415_vt_join_q = {redist272_i_shl_i_i_i_i_i_i_85_c_compstr2415_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_offset(CONSTANT,30558)
    assign redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_offset_q = $unsigned(8'b01011100);

    // redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_rdcnt(ADD,32007)
    assign redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_a = {1'b0, redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_wraddr_q};
    assign redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_b = {1'b0, redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_o <= $unsigned(redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_a) + $unsigned(redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_b);
        end
    end
    assign redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_q = redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_o[8:0];

    // redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_inputreg0(DELAY,32002)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl);
        end
    end

    // redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_wraddr(COUNTER,32005)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_wraddr_i <= $unsigned(redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_wraddr_q = redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_wraddr_i[7:0];

    // redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem(DUALMEM,32004)
    assign redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_ia = $unsigned(redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_inputreg0_q);
    assign redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_aa = redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_wraddr_q;
    assign redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_ab = redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_aa),
        .data_a(redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_ab),
        .q_b(redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_q = redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_iq[15:0];

    // redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_outputreg0(DELAY,32003)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_outputreg0_q <= $unsigned(redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_mem_q);
        end
    end

    // redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_rdcnt(ADD,30559)
    assign redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_a = {1'b0, redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_wraddr_q};
    assign redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_b = {1'b0, redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_o <= $unsigned(redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_a) + $unsigned(redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_b);
        end
    end
    assign redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_q = redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_o[8:0];

    // redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_inputreg0(DELAY,30554)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl);
        end
    end

    // redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_wraddr(COUNTER,30557)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_wraddr_i <= $unsigned(redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_wraddr_q = redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_wraddr_i[7:0];

    // redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem(DUALMEM,30556)
    assign redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_ia = $unsigned(redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_inputreg0_q);
    assign redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_aa = redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_wraddr_q;
    assign redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_ab = redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_aa),
        .data_a(redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_ab),
        .q_b(redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_q = redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_iq[15:0];

    // redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_outputreg0(DELAY,30555)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_outputreg0_q <= $unsigned(redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_mem_q);
        end
    end

    // redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_rdcnt(ADD,30565)
    assign redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_a = {1'b0, redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_wraddr_q};
    assign redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_b = {1'b0, redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_o <= $unsigned(redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_a) + $unsigned(redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_b);
        end
    end
    assign redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_q = redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_o[8:0];

    // redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_inputreg0(DELAY,30560)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl);
        end
    end

    // redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_wraddr(COUNTER,30563)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_wraddr_i <= $unsigned(redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_wraddr_q = redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_wraddr_i[7:0];

    // redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem(DUALMEM,30562)
    assign redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_ia = $unsigned(redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_inputreg0_q);
    assign redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_aa = redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_wraddr_q;
    assign redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_ab = redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_aa),
        .data_a(redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_ab),
        .q_b(redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_q = redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_iq[15:0];

    // redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_outputreg0(DELAY,30561)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_outputreg0_q <= $unsigned(redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_mem_q);
        end
    end

    // redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_rdcnt(ADD,32001)
    assign redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_a = {1'b0, redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_wraddr_q};
    assign redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_b = {1'b0, redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_o <= $unsigned(redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_a) + $unsigned(redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_b);
        end
    end
    assign redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_q = redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_o[8:0];

    // redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_inputreg0(DELAY,31996)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl);
        end
    end

    // redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_wraddr(COUNTER,31999)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_wraddr_i <= $unsigned(redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_wraddr_q = redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_wraddr_i[7:0];

    // redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem(DUALMEM,31998)
    assign redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_ia = $unsigned(redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_inputreg0_q);
    assign redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_aa = redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_wraddr_q;
    assign redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_ab = redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_aa),
        .data_a(redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_ab),
        .q_b(redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_q = redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_iq[15:0];

    // redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_outputreg0(DELAY,31997)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_outputreg0_q <= $unsigned(redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28044)@177 + 5
    // out q@183
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416(ADD,8632)@183
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod466_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_b = $unsigned({{5{i_shl_i_i_i_i_i_i_85_c_compstr2415_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_85_c_compstr2415_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_o[33:0];

    // rightShiftStage0_uid20239_dupName_341_i_unnamed_c_compstr0_shift_x(MUX,20238)@183
    assign rightShiftStage0_uid20239_dupName_341_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20239_dupName_341_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_q or rightShiftStage0Idx1_uid20237_dupName_341_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20239_dupName_341_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20239_dupName_341_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_q;
            1'b1 : rightShiftStage0_uid20239_dupName_341_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20237_dupName_341_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20239_dupName_341_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20244_dupName_341_i_unnamed_c_compstr0_shift_x(MUX,20243)@183
    assign rightShiftStage1_uid20244_dupName_341_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20244_dupName_341_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20239_dupName_341_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20242_dupName_341_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20244_dupName_341_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20244_dupName_341_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20239_dupName_341_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20244_dupName_341_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20242_dupName_341_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20244_dupName_341_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20249_dupName_341_i_unnamed_c_compstr0_shift_x(MUX,20248)@183
    assign rightShiftStage2_uid20249_dupName_341_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20249_dupName_341_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20244_dupName_341_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20247_dupName_341_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20249_dupName_341_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20249_dupName_341_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20244_dupName_341_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20249_dupName_341_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20247_dupName_341_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20249_dupName_341_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2417_vt_select_20(BITSELECT,11029)@183
    assign i_unnamed_c_compstr2417_vt_select_20_b = rightShiftStage2_uid20249_dupName_341_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2417_vt_join(BITJOIN,11028)@183
    assign i_unnamed_c_compstr2417_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2417_vt_select_20_b};

    // i_conv_i_i_i_i_i_85_c_compstr2418_sel_x(BITSELECT,3823)@183
    assign i_conv_i_i_i_i_i_85_c_compstr2418_sel_x_b = i_unnamed_c_compstr2417_vt_join_q[15:0];

    // redist1042_i_conv_i_i_i_i_i_85_c_compstr2418_sel_x_b_1(DELAY,29270)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1042_i_conv_i_i_i_i_i_85_c_compstr2418_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_85_c_compstr2418_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20258_dupName_342_i_unnamed_c_compstr0_shift_x(BITSELECT,20257)@183
    assign rightShiftStage1Idx1Rng8_uid20258_dupName_342_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20257_dupName_342_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20260_dupName_342_i_unnamed_c_compstr0_shift_x(BITJOIN,20259)@183
    assign rightShiftStage1Idx1_uid20260_dupName_342_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20258_dupName_342_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20253_dupName_342_i_unnamed_c_compstr0_shift_x(BITSELECT,20252)@183
    assign rightShiftStage0Idx1Rng4_uid20253_dupName_342_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_q[33:4];

    // rightShiftStage0Idx1_uid20255_dupName_342_i_unnamed_c_compstr0_shift_x(BITJOIN,20254)@183
    assign rightShiftStage0Idx1_uid20255_dupName_342_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20253_dupName_342_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20257_dupName_342_i_unnamed_c_compstr0_shift_x(MUX,20256)@183
    assign rightShiftStage0_uid20257_dupName_342_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20257_dupName_342_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_q or rightShiftStage0Idx1_uid20255_dupName_342_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20257_dupName_342_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20257_dupName_342_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compstr2416_q;
            1'b1 : rightShiftStage0_uid20257_dupName_342_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20255_dupName_342_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20257_dupName_342_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20262_dupName_342_i_unnamed_c_compstr0_shift_x(MUX,20261)@183
    assign rightShiftStage1_uid20262_dupName_342_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20262_dupName_342_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20257_dupName_342_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20260_dupName_342_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20262_dupName_342_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20262_dupName_342_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20257_dupName_342_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20262_dupName_342_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20260_dupName_342_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20262_dupName_342_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2419_vt_select_21(BITSELECT,11032)@183
    assign i_unnamed_c_compstr2419_vt_select_21_b = rightShiftStage1_uid20262_dupName_342_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2419_vt_join(BITJOIN,11031)@183
    assign i_unnamed_c_compstr2419_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2419_vt_select_21_b};

    // i_unnamed_c_compstr2420_sel_x(BITSELECT,6146)@183
    assign i_unnamed_c_compstr2420_sel_x_b = i_unnamed_c_compstr2419_vt_join_q[15:0];

    // i_unnamed_c_compstr2421_BitSelect_for_a(BITSELECT,27681)@183
    assign i_unnamed_c_compstr2421_BitSelect_for_a_b = i_unnamed_c_compstr2420_sel_x_b[0:0];

    // i_unnamed_c_compstr2421_join(BITJOIN,27682)@183
    assign i_unnamed_c_compstr2421_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2421_BitSelect_for_a_b};

    // i_unnamed_c_compstr2421_vt_select_0(BITSELECT,11037)@183
    assign i_unnamed_c_compstr2421_vt_select_0_b = i_unnamed_c_compstr2421_join_q[0:0];

    // redist144_i_unnamed_c_compstr2421_vt_select_0_b_1(DELAY,28372)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist144_i_unnamed_c_compstr2421_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2421_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2421_vt_join(BITJOIN,11036)@184
    assign i_unnamed_c_compstr2421_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist144_i_unnamed_c_compstr2421_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_85_c_compstr2422(ADD,7090)@184
    assign i_add_i_i_i_i_i_i_85_c_compstr2422_a = {1'b0, i_unnamed_c_compstr2421_vt_join_q};
    assign i_add_i_i_i_i_i_i_85_c_compstr2422_b = {1'b0, redist1042_i_conv_i_i_i_i_i_85_c_compstr2418_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_85_c_compstr2422_o = $unsigned(i_add_i_i_i_i_i_i_85_c_compstr2422_a) + $unsigned(i_add_i_i_i_i_i_i_85_c_compstr2422_b);
    assign i_add_i_i_i_i_i_i_85_c_compstr2422_q = i_add_i_i_i_i_i_i_85_c_compstr2422_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_85_c_compstr2422_sel_x(BITSELECT,2284)@184
    assign bgTrunc_i_add_i_i_i_i_i_i_85_c_compstr2422_sel_x_b = i_add_i_i_i_i_i_i_85_c_compstr2422_q[15:0];

    // i_conv_i_i_i_i_i_i279_86_c_compstr2442_sel_x(BITSELECT,3952)@184
    assign i_conv_i_i_i_i_i_i279_86_c_compstr2442_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_85_c_compstr2422_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_86_c_compstr2442_vt_select_15(BITSELECT,8325)@184
    assign i_conv_i_i_i_i_i_i279_86_c_compstr2442_vt_select_15_b = i_conv_i_i_i_i_i_i279_86_c_compstr2442_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_86_c_compstr2442_vt_join(BITJOIN,8324)@184
    assign i_conv_i_i_i_i_i_i279_86_c_compstr2442_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_86_c_compstr2442_vt_select_15_b};

    // leftShiftStage0_uid27158_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x(MUX,27157)@184
    assign leftShiftStage0_uid27158_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27158_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_86_c_compstr2442_vt_join_q or leftShiftStage0Idx1_uid27156_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27158_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27158_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_86_c_compstr2442_vt_join_q;
            1'b1 : leftShiftStage0_uid27158_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27156_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27158_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27163_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x(MUX,27162)@184
    assign leftShiftStage1_uid27163_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27163_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_s or leftShiftStage0_uid27158_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27161_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27163_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27163_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q = leftShiftStage0_uid27158_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27163_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27161_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27163_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27168_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x(MUX,27167)@184
    assign leftShiftStage2_uid27168_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27168_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_s or leftShiftStage1_uid27163_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27166_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27168_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27168_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q = leftShiftStage1_uid27163_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27168_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27166_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27168_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_86_c_compstr2443_vt_select_28(BITSELECT,9757)@184
    assign i_shl_i_i_i_i_i_i_86_c_compstr2443_vt_select_28_b = leftShiftStage2_uid27168_i_shl_i_i_i_i_i_i_86_c_compstr0_shift_x_q[28:13];

    // redist271_i_shl_i_i_i_i_i_i_86_c_compstr2443_vt_select_28_b_1(DELAY,28499)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist271_i_shl_i_i_i_i_i_i_86_c_compstr2443_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_86_c_compstr2443_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_86_c_compstr2443_vt_join(BITJOIN,9756)@185
    assign i_shl_i_i_i_i_i_i_86_c_compstr2443_vt_join_q = {redist271_i_shl_i_i_i_i_i_i_86_c_compstr2443_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_offset(CONSTANT,30570)
    assign redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_offset_q = $unsigned(8'b01011010);

    // redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_rdcnt(ADD,32019)
    assign redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_a = {1'b0, redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_wraddr_q};
    assign redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_b = {1'b0, redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_o <= $unsigned(redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_a) + $unsigned(redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_b);
        end
    end
    assign redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_q = redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_o[8:0];

    // redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_inputreg0(DELAY,32014)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl);
        end
    end

    // redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_wraddr(COUNTER,32017)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_wraddr_i <= $unsigned(redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_wraddr_q = redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_wraddr_i[7:0];

    // redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem(DUALMEM,32016)
    assign redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_ia = $unsigned(redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_inputreg0_q);
    assign redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_aa = redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_wraddr_q;
    assign redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_ab = redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_aa),
        .data_a(redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_ab),
        .q_b(redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_q = redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_iq[15:0];

    // redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_outputreg0(DELAY,32015)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_outputreg0_q <= $unsigned(redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_mem_q);
        end
    end

    // redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_rdcnt(ADD,30571)
    assign redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_a = {1'b0, redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_wraddr_q};
    assign redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_b = {1'b0, redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_o <= $unsigned(redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_a) + $unsigned(redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_b);
        end
    end
    assign redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_q = redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_o[8:0];

    // redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_inputreg0(DELAY,30566)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl);
        end
    end

    // redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_wraddr(COUNTER,30569)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_wraddr_i <= $unsigned(redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_wraddr_q = redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_wraddr_i[7:0];

    // redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem(DUALMEM,30568)
    assign redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_ia = $unsigned(redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_inputreg0_q);
    assign redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_aa = redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_wraddr_q;
    assign redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_ab = redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_aa),
        .data_a(redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_ab),
        .q_b(redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_q = redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_iq[15:0];

    // redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_outputreg0(DELAY,30567)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_outputreg0_q <= $unsigned(redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_mem_q);
        end
    end

    // redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_rdcnt(ADD,30577)
    assign redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_a = {1'b0, redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_wraddr_q};
    assign redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_b = {1'b0, redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_o <= $unsigned(redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_a) + $unsigned(redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_b);
        end
    end
    assign redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_q = redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_o[8:0];

    // redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_inputreg0(DELAY,30572)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl);
        end
    end

    // redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_wraddr(COUNTER,30575)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_wraddr_i <= $unsigned(redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_wraddr_q = redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_wraddr_i[7:0];

    // redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem(DUALMEM,30574)
    assign redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_ia = $unsigned(redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_inputreg0_q);
    assign redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_aa = redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_wraddr_q;
    assign redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_ab = redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_aa),
        .data_a(redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_ab),
        .q_b(redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_q = redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_iq[15:0];

    // redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_outputreg0(DELAY,30573)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_outputreg0_q <= $unsigned(redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_mem_q);
        end
    end

    // redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_rdcnt(ADD,32013)
    assign redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_a = {1'b0, redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_wraddr_q};
    assign redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_b = {1'b0, redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_o <= $unsigned(redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_a) + $unsigned(redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_b);
        end
    end
    assign redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_q = redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_o[8:0];

    // redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_inputreg0(DELAY,32008)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl);
        end
    end

    // redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_wraddr(COUNTER,32011)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_wraddr_i <= $unsigned(redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_wraddr_q = redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_wraddr_i[7:0];

    // redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem(DUALMEM,32010)
    assign redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_ia = $unsigned(redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_inputreg0_q);
    assign redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_aa = redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_wraddr_q;
    assign redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_ab = redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_aa),
        .data_a(redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_ab),
        .q_b(redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_q = redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_iq[15:0];

    // redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_outputreg0(DELAY,32009)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_outputreg0_q <= $unsigned(redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28046)@179 + 5
    // out q@185
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444(ADD,8633)@185
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod471_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_b = $unsigned({{5{i_shl_i_i_i_i_i_i_86_c_compstr2443_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_86_c_compstr2443_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_o[33:0];

    // rightShiftStage0_uid20301_dupName_345_i_unnamed_c_compstr0_shift_x(MUX,20300)@185
    assign rightShiftStage0_uid20301_dupName_345_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20301_dupName_345_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_q or rightShiftStage0Idx1_uid20299_dupName_345_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20301_dupName_345_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20301_dupName_345_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_q;
            1'b1 : rightShiftStage0_uid20301_dupName_345_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20299_dupName_345_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20301_dupName_345_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20306_dupName_345_i_unnamed_c_compstr0_shift_x(MUX,20305)@185
    assign rightShiftStage1_uid20306_dupName_345_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20306_dupName_345_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20301_dupName_345_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20304_dupName_345_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20306_dupName_345_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20306_dupName_345_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20301_dupName_345_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20306_dupName_345_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20304_dupName_345_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20306_dupName_345_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20311_dupName_345_i_unnamed_c_compstr0_shift_x(MUX,20310)@185
    assign rightShiftStage2_uid20311_dupName_345_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20311_dupName_345_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20306_dupName_345_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20309_dupName_345_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20311_dupName_345_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20311_dupName_345_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20306_dupName_345_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20311_dupName_345_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20309_dupName_345_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20311_dupName_345_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2445_vt_select_20(BITSELECT,11051)@185
    assign i_unnamed_c_compstr2445_vt_select_20_b = rightShiftStage2_uid20311_dupName_345_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2445_vt_join(BITJOIN,11050)@185
    assign i_unnamed_c_compstr2445_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2445_vt_select_20_b};

    // i_conv_i_i_i_i_i_86_c_compstr2446_sel_x(BITSELECT,3824)@185
    assign i_conv_i_i_i_i_i_86_c_compstr2446_sel_x_b = i_unnamed_c_compstr2445_vt_join_q[15:0];

    // redist1041_i_conv_i_i_i_i_i_86_c_compstr2446_sel_x_b_1(DELAY,29269)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1041_i_conv_i_i_i_i_i_86_c_compstr2446_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_86_c_compstr2446_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20320_dupName_346_i_unnamed_c_compstr0_shift_x(BITSELECT,20319)@185
    assign rightShiftStage1Idx1Rng8_uid20320_dupName_346_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20319_dupName_346_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20322_dupName_346_i_unnamed_c_compstr0_shift_x(BITJOIN,20321)@185
    assign rightShiftStage1Idx1_uid20322_dupName_346_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20320_dupName_346_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20315_dupName_346_i_unnamed_c_compstr0_shift_x(BITSELECT,20314)@185
    assign rightShiftStage0Idx1Rng4_uid20315_dupName_346_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_q[33:4];

    // rightShiftStage0Idx1_uid20317_dupName_346_i_unnamed_c_compstr0_shift_x(BITJOIN,20316)@185
    assign rightShiftStage0Idx1_uid20317_dupName_346_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20315_dupName_346_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20319_dupName_346_i_unnamed_c_compstr0_shift_x(MUX,20318)@185
    assign rightShiftStage0_uid20319_dupName_346_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20319_dupName_346_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_q or rightShiftStage0Idx1_uid20317_dupName_346_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20319_dupName_346_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20319_dupName_346_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compstr2444_q;
            1'b1 : rightShiftStage0_uid20319_dupName_346_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20317_dupName_346_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20319_dupName_346_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20324_dupName_346_i_unnamed_c_compstr0_shift_x(MUX,20323)@185
    assign rightShiftStage1_uid20324_dupName_346_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20324_dupName_346_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20319_dupName_346_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20322_dupName_346_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20324_dupName_346_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20324_dupName_346_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20319_dupName_346_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20324_dupName_346_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20322_dupName_346_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20324_dupName_346_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2447_vt_select_21(BITSELECT,11054)@185
    assign i_unnamed_c_compstr2447_vt_select_21_b = rightShiftStage1_uid20324_dupName_346_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2447_vt_join(BITJOIN,11053)@185
    assign i_unnamed_c_compstr2447_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2447_vt_select_21_b};

    // i_unnamed_c_compstr2448_sel_x(BITSELECT,6148)@185
    assign i_unnamed_c_compstr2448_sel_x_b = i_unnamed_c_compstr2447_vt_join_q[15:0];

    // i_unnamed_c_compstr2449_BitSelect_for_a(BITSELECT,27685)@185
    assign i_unnamed_c_compstr2449_BitSelect_for_a_b = i_unnamed_c_compstr2448_sel_x_b[0:0];

    // i_unnamed_c_compstr2449_join(BITJOIN,27686)@185
    assign i_unnamed_c_compstr2449_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2449_BitSelect_for_a_b};

    // i_unnamed_c_compstr2449_vt_select_0(BITSELECT,11059)@185
    assign i_unnamed_c_compstr2449_vt_select_0_b = i_unnamed_c_compstr2449_join_q[0:0];

    // redist142_i_unnamed_c_compstr2449_vt_select_0_b_1(DELAY,28370)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist142_i_unnamed_c_compstr2449_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2449_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2449_vt_join(BITJOIN,11058)@186
    assign i_unnamed_c_compstr2449_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist142_i_unnamed_c_compstr2449_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_86_c_compstr2450(ADD,7091)@186
    assign i_add_i_i_i_i_i_i_86_c_compstr2450_a = {1'b0, i_unnamed_c_compstr2449_vt_join_q};
    assign i_add_i_i_i_i_i_i_86_c_compstr2450_b = {1'b0, redist1041_i_conv_i_i_i_i_i_86_c_compstr2446_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_86_c_compstr2450_o = $unsigned(i_add_i_i_i_i_i_i_86_c_compstr2450_a) + $unsigned(i_add_i_i_i_i_i_i_86_c_compstr2450_b);
    assign i_add_i_i_i_i_i_i_86_c_compstr2450_q = i_add_i_i_i_i_i_i_86_c_compstr2450_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_86_c_compstr2450_sel_x(BITSELECT,2285)@186
    assign bgTrunc_i_add_i_i_i_i_i_i_86_c_compstr2450_sel_x_b = i_add_i_i_i_i_i_i_86_c_compstr2450_q[15:0];

    // i_conv_i_i_i_i_i_i279_87_c_compstr2470_sel_x(BITSELECT,3953)@186
    assign i_conv_i_i_i_i_i_i279_87_c_compstr2470_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_86_c_compstr2450_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_87_c_compstr2470_vt_select_15(BITSELECT,8329)@186
    assign i_conv_i_i_i_i_i_i279_87_c_compstr2470_vt_select_15_b = i_conv_i_i_i_i_i_i279_87_c_compstr2470_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_87_c_compstr2470_vt_join(BITJOIN,8328)@186
    assign i_conv_i_i_i_i_i_i279_87_c_compstr2470_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_87_c_compstr2470_vt_select_15_b};

    // leftShiftStage0_uid27176_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x(MUX,27175)@186
    assign leftShiftStage0_uid27176_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27176_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_87_c_compstr2470_vt_join_q or leftShiftStage0Idx1_uid27174_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27176_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27176_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_87_c_compstr2470_vt_join_q;
            1'b1 : leftShiftStage0_uid27176_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27174_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27176_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27181_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x(MUX,27180)@186
    assign leftShiftStage1_uid27181_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27181_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_s or leftShiftStage0_uid27176_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27179_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27181_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27181_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q = leftShiftStage0_uid27176_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27181_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27179_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27181_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27186_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x(MUX,27185)@186
    assign leftShiftStage2_uid27186_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27186_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_s or leftShiftStage1_uid27181_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27184_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27186_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27186_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q = leftShiftStage1_uid27181_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27186_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27184_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27186_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_87_c_compstr2471_vt_select_28(BITSELECT,9760)@186
    assign i_shl_i_i_i_i_i_i_87_c_compstr2471_vt_select_28_b = leftShiftStage2_uid27186_i_shl_i_i_i_i_i_i_87_c_compstr0_shift_x_q[28:13];

    // redist270_i_shl_i_i_i_i_i_i_87_c_compstr2471_vt_select_28_b_1(DELAY,28498)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist270_i_shl_i_i_i_i_i_i_87_c_compstr2471_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_87_c_compstr2471_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_87_c_compstr2471_vt_join(BITJOIN,9759)@187
    assign i_shl_i_i_i_i_i_i_87_c_compstr2471_vt_join_q = {redist270_i_shl_i_i_i_i_i_i_87_c_compstr2471_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_offset(CONSTANT,30582)
    assign redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_offset_q = $unsigned(8'b01011000);

    // redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_rdcnt(ADD,32031)
    assign redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_a = {1'b0, redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_wraddr_q};
    assign redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_b = {1'b0, redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_o <= $unsigned(redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_a) + $unsigned(redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_b);
        end
    end
    assign redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_q = redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_o[8:0];

    // redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_inputreg0(DELAY,32026)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl);
        end
    end

    // redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_wraddr(COUNTER,32029)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_wraddr_i <= $unsigned(redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_wraddr_q = redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_wraddr_i[7:0];

    // redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem(DUALMEM,32028)
    assign redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_ia = $unsigned(redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_inputreg0_q);
    assign redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_aa = redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_wraddr_q;
    assign redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_ab = redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_aa),
        .data_a(redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_ab),
        .q_b(redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_q = redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_iq[15:0];

    // redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_outputreg0(DELAY,32027)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_outputreg0_q <= $unsigned(redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_mem_q);
        end
    end

    // redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_rdcnt(ADD,30583)
    assign redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_a = {1'b0, redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_wraddr_q};
    assign redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_b = {1'b0, redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_o <= $unsigned(redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_a) + $unsigned(redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_b);
        end
    end
    assign redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_q = redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_o[8:0];

    // redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_inputreg0(DELAY,30578)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl);
        end
    end

    // redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_wraddr(COUNTER,30581)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_wraddr_i <= $unsigned(redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_wraddr_q = redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_wraddr_i[7:0];

    // redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem(DUALMEM,30580)
    assign redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_ia = $unsigned(redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_inputreg0_q);
    assign redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_aa = redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_wraddr_q;
    assign redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_ab = redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_aa),
        .data_a(redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_ab),
        .q_b(redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_q = redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_iq[15:0];

    // redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_outputreg0(DELAY,30579)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_outputreg0_q <= $unsigned(redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_mem_q);
        end
    end

    // redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_rdcnt(ADD,30589)
    assign redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_a = {1'b0, redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_wraddr_q};
    assign redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_b = {1'b0, redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_o <= $unsigned(redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_a) + $unsigned(redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_b);
        end
    end
    assign redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_q = redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_o[8:0];

    // redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_inputreg0(DELAY,30584)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl);
        end
    end

    // redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_wraddr(COUNTER,30587)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_wraddr_i <= $unsigned(redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_wraddr_q = redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_wraddr_i[7:0];

    // redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem(DUALMEM,30586)
    assign redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_ia = $unsigned(redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_inputreg0_q);
    assign redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_aa = redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_wraddr_q;
    assign redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_ab = redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_aa),
        .data_a(redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_ab),
        .q_b(redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_q = redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_iq[15:0];

    // redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_outputreg0(DELAY,30585)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_outputreg0_q <= $unsigned(redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_mem_q);
        end
    end

    // redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_rdcnt(ADD,32025)
    assign redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_a = {1'b0, redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_wraddr_q};
    assign redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_b = {1'b0, redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_o <= $unsigned(redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_a) + $unsigned(redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_b);
        end
    end
    assign redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_q = redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_o[8:0];

    // redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_inputreg0(DELAY,32020)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl);
        end
    end

    // redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_wraddr(COUNTER,32023)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_wraddr_i <= $unsigned(redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_wraddr_q = redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_wraddr_i[7:0];

    // redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem(DUALMEM,32022)
    assign redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_ia = $unsigned(redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_inputreg0_q);
    assign redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_aa = redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_wraddr_q;
    assign redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_ab = redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_aa),
        .data_a(redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_ab),
        .q_b(redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_q = redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_iq[15:0];

    // redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_outputreg0(DELAY,32021)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_outputreg0_q <= $unsigned(redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28047)@181 + 5
    // out q@187
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472(ADD,8634)@187
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod476_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_b = $unsigned({{5{i_shl_i_i_i_i_i_i_87_c_compstr2471_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_87_c_compstr2471_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_o[33:0];

    // rightShiftStage0_uid20363_dupName_349_i_unnamed_c_compstr0_shift_x(MUX,20362)@187
    assign rightShiftStage0_uid20363_dupName_349_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20363_dupName_349_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_q or rightShiftStage0Idx1_uid20361_dupName_349_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20363_dupName_349_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20363_dupName_349_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_q;
            1'b1 : rightShiftStage0_uid20363_dupName_349_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20361_dupName_349_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20363_dupName_349_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20368_dupName_349_i_unnamed_c_compstr0_shift_x(MUX,20367)@187
    assign rightShiftStage1_uid20368_dupName_349_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20368_dupName_349_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20363_dupName_349_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20366_dupName_349_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20368_dupName_349_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20368_dupName_349_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20363_dupName_349_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20368_dupName_349_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20366_dupName_349_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20368_dupName_349_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20373_dupName_349_i_unnamed_c_compstr0_shift_x(MUX,20372)@187
    assign rightShiftStage2_uid20373_dupName_349_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20373_dupName_349_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20368_dupName_349_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20371_dupName_349_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20373_dupName_349_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20373_dupName_349_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20368_dupName_349_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20373_dupName_349_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20371_dupName_349_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20373_dupName_349_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2473_vt_select_20(BITSELECT,11076)@187
    assign i_unnamed_c_compstr2473_vt_select_20_b = rightShiftStage2_uid20373_dupName_349_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2473_vt_join(BITJOIN,11075)@187
    assign i_unnamed_c_compstr2473_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2473_vt_select_20_b};

    // i_conv_i_i_i_i_i_87_c_compstr2474_sel_x(BITSELECT,3825)@187
    assign i_conv_i_i_i_i_i_87_c_compstr2474_sel_x_b = i_unnamed_c_compstr2473_vt_join_q[15:0];

    // redist1040_i_conv_i_i_i_i_i_87_c_compstr2474_sel_x_b_1(DELAY,29268)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1040_i_conv_i_i_i_i_i_87_c_compstr2474_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_87_c_compstr2474_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20382_dupName_350_i_unnamed_c_compstr0_shift_x(BITSELECT,20381)@187
    assign rightShiftStage1Idx1Rng8_uid20382_dupName_350_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20381_dupName_350_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20384_dupName_350_i_unnamed_c_compstr0_shift_x(BITJOIN,20383)@187
    assign rightShiftStage1Idx1_uid20384_dupName_350_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20382_dupName_350_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20377_dupName_350_i_unnamed_c_compstr0_shift_x(BITSELECT,20376)@187
    assign rightShiftStage0Idx1Rng4_uid20377_dupName_350_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_q[33:4];

    // rightShiftStage0Idx1_uid20379_dupName_350_i_unnamed_c_compstr0_shift_x(BITJOIN,20378)@187
    assign rightShiftStage0Idx1_uid20379_dupName_350_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20377_dupName_350_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20381_dupName_350_i_unnamed_c_compstr0_shift_x(MUX,20380)@187
    assign rightShiftStage0_uid20381_dupName_350_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20381_dupName_350_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_q or rightShiftStage0Idx1_uid20379_dupName_350_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20381_dupName_350_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20381_dupName_350_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compstr2472_q;
            1'b1 : rightShiftStage0_uid20381_dupName_350_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20379_dupName_350_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20381_dupName_350_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20386_dupName_350_i_unnamed_c_compstr0_shift_x(MUX,20385)@187
    assign rightShiftStage1_uid20386_dupName_350_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20386_dupName_350_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20381_dupName_350_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20384_dupName_350_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20386_dupName_350_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20386_dupName_350_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20381_dupName_350_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20386_dupName_350_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20384_dupName_350_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20386_dupName_350_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2475_vt_select_21(BITSELECT,11079)@187
    assign i_unnamed_c_compstr2475_vt_select_21_b = rightShiftStage1_uid20386_dupName_350_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2475_vt_join(BITJOIN,11078)@187
    assign i_unnamed_c_compstr2475_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2475_vt_select_21_b};

    // i_unnamed_c_compstr2476_sel_x(BITSELECT,6150)@187
    assign i_unnamed_c_compstr2476_sel_x_b = i_unnamed_c_compstr2475_vt_join_q[15:0];

    // i_unnamed_c_compstr2477_BitSelect_for_a(BITSELECT,27689)@187
    assign i_unnamed_c_compstr2477_BitSelect_for_a_b = i_unnamed_c_compstr2476_sel_x_b[0:0];

    // i_unnamed_c_compstr2477_join(BITJOIN,27690)@187
    assign i_unnamed_c_compstr2477_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2477_BitSelect_for_a_b};

    // i_unnamed_c_compstr2477_vt_select_0(BITSELECT,11084)@187
    assign i_unnamed_c_compstr2477_vt_select_0_b = i_unnamed_c_compstr2477_join_q[0:0];

    // redist140_i_unnamed_c_compstr2477_vt_select_0_b_1(DELAY,28368)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist140_i_unnamed_c_compstr2477_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2477_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2477_vt_join(BITJOIN,11083)@188
    assign i_unnamed_c_compstr2477_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist140_i_unnamed_c_compstr2477_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_87_c_compstr2478(ADD,7092)@188
    assign i_add_i_i_i_i_i_i_87_c_compstr2478_a = {1'b0, i_unnamed_c_compstr2477_vt_join_q};
    assign i_add_i_i_i_i_i_i_87_c_compstr2478_b = {1'b0, redist1040_i_conv_i_i_i_i_i_87_c_compstr2474_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_87_c_compstr2478_o = $unsigned(i_add_i_i_i_i_i_i_87_c_compstr2478_a) + $unsigned(i_add_i_i_i_i_i_i_87_c_compstr2478_b);
    assign i_add_i_i_i_i_i_i_87_c_compstr2478_q = i_add_i_i_i_i_i_i_87_c_compstr2478_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_87_c_compstr2478_sel_x(BITSELECT,2286)@188
    assign bgTrunc_i_add_i_i_i_i_i_i_87_c_compstr2478_sel_x_b = i_add_i_i_i_i_i_i_87_c_compstr2478_q[15:0];

    // i_conv_i_i_i_i_i_i279_88_c_compstr2498_sel_x(BITSELECT,3954)@188
    assign i_conv_i_i_i_i_i_i279_88_c_compstr2498_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_87_c_compstr2478_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_88_c_compstr2498_vt_select_15(BITSELECT,8333)@188
    assign i_conv_i_i_i_i_i_i279_88_c_compstr2498_vt_select_15_b = i_conv_i_i_i_i_i_i279_88_c_compstr2498_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_88_c_compstr2498_vt_join(BITJOIN,8332)@188
    assign i_conv_i_i_i_i_i_i279_88_c_compstr2498_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_88_c_compstr2498_vt_select_15_b};

    // leftShiftStage0_uid27194_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x(MUX,27193)@188
    assign leftShiftStage0_uid27194_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27194_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_88_c_compstr2498_vt_join_q or leftShiftStage0Idx1_uid27192_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27194_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27194_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_88_c_compstr2498_vt_join_q;
            1'b1 : leftShiftStage0_uid27194_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27192_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27194_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27199_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x(MUX,27198)@188
    assign leftShiftStage1_uid27199_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27199_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_s or leftShiftStage0_uid27194_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27197_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27199_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27199_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q = leftShiftStage0_uid27194_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27199_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27197_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27199_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27204_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x(MUX,27203)@188
    assign leftShiftStage2_uid27204_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27204_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_s or leftShiftStage1_uid27199_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27202_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27204_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27204_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q = leftShiftStage1_uid27199_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27204_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27202_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27204_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_88_c_compstr2499_vt_select_28(BITSELECT,9763)@188
    assign i_shl_i_i_i_i_i_i_88_c_compstr2499_vt_select_28_b = leftShiftStage2_uid27204_i_shl_i_i_i_i_i_i_88_c_compstr0_shift_x_q[28:13];

    // redist269_i_shl_i_i_i_i_i_i_88_c_compstr2499_vt_select_28_b_1(DELAY,28497)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist269_i_shl_i_i_i_i_i_i_88_c_compstr2499_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_88_c_compstr2499_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_88_c_compstr2499_vt_join(BITJOIN,9762)@189
    assign i_shl_i_i_i_i_i_i_88_c_compstr2499_vt_join_q = {redist269_i_shl_i_i_i_i_i_i_88_c_compstr2499_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_offset(CONSTANT,30594)
    assign redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_offset_q = $unsigned(8'b01010110);

    // redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_rdcnt(ADD,32043)
    assign redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_a = {1'b0, redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_wraddr_q};
    assign redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_b = {1'b0, redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_o <= $unsigned(redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_a) + $unsigned(redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_b);
        end
    end
    assign redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_q = redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_o[8:0];

    // redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_inputreg0(DELAY,32038)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl);
        end
    end

    // redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_wraddr(COUNTER,32041)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_wraddr_i <= $unsigned(redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_wraddr_q = redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_wraddr_i[7:0];

    // redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem(DUALMEM,32040)
    assign redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_ia = $unsigned(redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_inputreg0_q);
    assign redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_aa = redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_wraddr_q;
    assign redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_ab = redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_aa),
        .data_a(redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_ab),
        .q_b(redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_q = redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_iq[15:0];

    // redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_outputreg0(DELAY,32039)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_outputreg0_q <= $unsigned(redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_mem_q);
        end
    end

    // redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_rdcnt(ADD,30595)
    assign redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_a = {1'b0, redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_wraddr_q};
    assign redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_b = {1'b0, redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_o <= $unsigned(redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_a) + $unsigned(redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_b);
        end
    end
    assign redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_q = redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_o[8:0];

    // redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_inputreg0(DELAY,30590)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl);
        end
    end

    // redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_wraddr(COUNTER,30593)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_wraddr_i <= $unsigned(redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_wraddr_q = redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_wraddr_i[7:0];

    // redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem(DUALMEM,30592)
    assign redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_ia = $unsigned(redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_inputreg0_q);
    assign redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_aa = redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_wraddr_q;
    assign redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_ab = redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_aa),
        .data_a(redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_ab),
        .q_b(redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_q = redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_iq[15:0];

    // redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_outputreg0(DELAY,30591)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_outputreg0_q <= $unsigned(redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_mem_q);
        end
    end

    // redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_rdcnt(ADD,30601)
    assign redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_a = {1'b0, redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_wraddr_q};
    assign redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_b = {1'b0, redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_o <= $unsigned(redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_a) + $unsigned(redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_b);
        end
    end
    assign redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_q = redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_o[8:0];

    // redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_inputreg0(DELAY,30596)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl);
        end
    end

    // redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_wraddr(COUNTER,30599)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_wraddr_i <= $unsigned(redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_wraddr_q = redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_wraddr_i[7:0];

    // redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem(DUALMEM,30598)
    assign redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_ia = $unsigned(redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_inputreg0_q);
    assign redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_aa = redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_wraddr_q;
    assign redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_ab = redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_aa),
        .data_a(redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_ab),
        .q_b(redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_q = redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_iq[15:0];

    // redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_outputreg0(DELAY,30597)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_outputreg0_q <= $unsigned(redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_mem_q);
        end
    end

    // redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_rdcnt(ADD,32037)
    assign redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_a = {1'b0, redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_wraddr_q};
    assign redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_b = {1'b0, redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_o <= $unsigned(redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_a) + $unsigned(redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_b);
        end
    end
    assign redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_q = redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_o[8:0];

    // redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_inputreg0(DELAY,32032)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl);
        end
    end

    // redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_wraddr(COUNTER,32035)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_wraddr_i <= $unsigned(redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_wraddr_q = redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_wraddr_i[7:0];

    // redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem(DUALMEM,32034)
    assign redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_ia = $unsigned(redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_inputreg0_q);
    assign redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_aa = redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_wraddr_q;
    assign redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_ab = redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_aa),
        .data_a(redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_ab),
        .q_b(redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_q = redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_iq[15:0];

    // redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_outputreg0(DELAY,32033)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_outputreg0_q <= $unsigned(redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28048)@183 + 5
    // out q@189
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500(ADD,8635)@189
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod481_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_b = $unsigned({{5{i_shl_i_i_i_i_i_i_88_c_compstr2499_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_88_c_compstr2499_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_o[33:0];

    // rightShiftStage0_uid20425_dupName_353_i_unnamed_c_compstr0_shift_x(MUX,20424)@189
    assign rightShiftStage0_uid20425_dupName_353_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20425_dupName_353_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_q or rightShiftStage0Idx1_uid20423_dupName_353_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20425_dupName_353_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20425_dupName_353_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_q;
            1'b1 : rightShiftStage0_uid20425_dupName_353_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20423_dupName_353_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20425_dupName_353_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20430_dupName_353_i_unnamed_c_compstr0_shift_x(MUX,20429)@189
    assign rightShiftStage1_uid20430_dupName_353_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20430_dupName_353_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20425_dupName_353_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20428_dupName_353_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20430_dupName_353_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20430_dupName_353_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20425_dupName_353_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20430_dupName_353_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20428_dupName_353_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20430_dupName_353_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20435_dupName_353_i_unnamed_c_compstr0_shift_x(MUX,20434)@189
    assign rightShiftStage2_uid20435_dupName_353_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20435_dupName_353_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20430_dupName_353_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20433_dupName_353_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20435_dupName_353_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20435_dupName_353_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20430_dupName_353_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20435_dupName_353_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20433_dupName_353_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20435_dupName_353_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2501_vt_select_20(BITSELECT,11106)@189
    assign i_unnamed_c_compstr2501_vt_select_20_b = rightShiftStage2_uid20435_dupName_353_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2501_vt_join(BITJOIN,11105)@189
    assign i_unnamed_c_compstr2501_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2501_vt_select_20_b};

    // i_conv_i_i_i_i_i_88_c_compstr2502_sel_x(BITSELECT,3826)@189
    assign i_conv_i_i_i_i_i_88_c_compstr2502_sel_x_b = i_unnamed_c_compstr2501_vt_join_q[15:0];

    // redist1039_i_conv_i_i_i_i_i_88_c_compstr2502_sel_x_b_1(DELAY,29267)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1039_i_conv_i_i_i_i_i_88_c_compstr2502_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_88_c_compstr2502_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20444_dupName_354_i_unnamed_c_compstr0_shift_x(BITSELECT,20443)@189
    assign rightShiftStage1Idx1Rng8_uid20444_dupName_354_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20443_dupName_354_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20446_dupName_354_i_unnamed_c_compstr0_shift_x(BITJOIN,20445)@189
    assign rightShiftStage1Idx1_uid20446_dupName_354_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20444_dupName_354_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20439_dupName_354_i_unnamed_c_compstr0_shift_x(BITSELECT,20438)@189
    assign rightShiftStage0Idx1Rng4_uid20439_dupName_354_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_q[33:4];

    // rightShiftStage0Idx1_uid20441_dupName_354_i_unnamed_c_compstr0_shift_x(BITJOIN,20440)@189
    assign rightShiftStage0Idx1_uid20441_dupName_354_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20439_dupName_354_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20443_dupName_354_i_unnamed_c_compstr0_shift_x(MUX,20442)@189
    assign rightShiftStage0_uid20443_dupName_354_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20443_dupName_354_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_q or rightShiftStage0Idx1_uid20441_dupName_354_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20443_dupName_354_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20443_dupName_354_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compstr2500_q;
            1'b1 : rightShiftStage0_uid20443_dupName_354_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20441_dupName_354_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20443_dupName_354_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20448_dupName_354_i_unnamed_c_compstr0_shift_x(MUX,20447)@189
    assign rightShiftStage1_uid20448_dupName_354_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20448_dupName_354_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20443_dupName_354_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20446_dupName_354_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20448_dupName_354_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20448_dupName_354_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20443_dupName_354_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20448_dupName_354_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20446_dupName_354_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20448_dupName_354_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2503_vt_select_21(BITSELECT,11109)@189
    assign i_unnamed_c_compstr2503_vt_select_21_b = rightShiftStage1_uid20448_dupName_354_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2503_vt_join(BITJOIN,11108)@189
    assign i_unnamed_c_compstr2503_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2503_vt_select_21_b};

    // i_unnamed_c_compstr2504_sel_x(BITSELECT,6153)@189
    assign i_unnamed_c_compstr2504_sel_x_b = i_unnamed_c_compstr2503_vt_join_q[15:0];

    // i_unnamed_c_compstr2505_BitSelect_for_a(BITSELECT,27695)@189
    assign i_unnamed_c_compstr2505_BitSelect_for_a_b = i_unnamed_c_compstr2504_sel_x_b[0:0];

    // i_unnamed_c_compstr2505_join(BITJOIN,27696)@189
    assign i_unnamed_c_compstr2505_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2505_BitSelect_for_a_b};

    // i_unnamed_c_compstr2505_vt_select_0(BITSELECT,11114)@189
    assign i_unnamed_c_compstr2505_vt_select_0_b = i_unnamed_c_compstr2505_join_q[0:0];

    // redist137_i_unnamed_c_compstr2505_vt_select_0_b_1(DELAY,28365)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist137_i_unnamed_c_compstr2505_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2505_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2505_vt_join(BITJOIN,11113)@190
    assign i_unnamed_c_compstr2505_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist137_i_unnamed_c_compstr2505_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_88_c_compstr2506(ADD,7093)@190
    assign i_add_i_i_i_i_i_i_88_c_compstr2506_a = {1'b0, i_unnamed_c_compstr2505_vt_join_q};
    assign i_add_i_i_i_i_i_i_88_c_compstr2506_b = {1'b0, redist1039_i_conv_i_i_i_i_i_88_c_compstr2502_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_88_c_compstr2506_o = $unsigned(i_add_i_i_i_i_i_i_88_c_compstr2506_a) + $unsigned(i_add_i_i_i_i_i_i_88_c_compstr2506_b);
    assign i_add_i_i_i_i_i_i_88_c_compstr2506_q = i_add_i_i_i_i_i_i_88_c_compstr2506_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_88_c_compstr2506_sel_x(BITSELECT,2287)@190
    assign bgTrunc_i_add_i_i_i_i_i_i_88_c_compstr2506_sel_x_b = i_add_i_i_i_i_i_i_88_c_compstr2506_q[15:0];

    // i_conv_i_i_i_i_i_i279_89_c_compstr2526_sel_x(BITSELECT,3955)@190
    assign i_conv_i_i_i_i_i_i279_89_c_compstr2526_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_88_c_compstr2506_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_89_c_compstr2526_vt_select_15(BITSELECT,8337)@190
    assign i_conv_i_i_i_i_i_i279_89_c_compstr2526_vt_select_15_b = i_conv_i_i_i_i_i_i279_89_c_compstr2526_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_89_c_compstr2526_vt_join(BITJOIN,8336)@190
    assign i_conv_i_i_i_i_i_i279_89_c_compstr2526_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_89_c_compstr2526_vt_select_15_b};

    // leftShiftStage0_uid27212_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x(MUX,27211)@190
    assign leftShiftStage0_uid27212_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27212_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_89_c_compstr2526_vt_join_q or leftShiftStage0Idx1_uid27210_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27212_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27212_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_89_c_compstr2526_vt_join_q;
            1'b1 : leftShiftStage0_uid27212_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27210_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27212_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27217_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x(MUX,27216)@190
    assign leftShiftStage1_uid27217_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27217_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_s or leftShiftStage0_uid27212_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27215_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27217_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27217_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q = leftShiftStage0_uid27212_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27217_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27215_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27217_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27222_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x(MUX,27221)@190
    assign leftShiftStage2_uid27222_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27222_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_s or leftShiftStage1_uid27217_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27220_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27222_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27222_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q = leftShiftStage1_uid27217_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27222_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27220_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27222_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_89_c_compstr2527_vt_select_28(BITSELECT,9766)@190
    assign i_shl_i_i_i_i_i_i_89_c_compstr2527_vt_select_28_b = leftShiftStage2_uid27222_i_shl_i_i_i_i_i_i_89_c_compstr0_shift_x_q[28:13];

    // redist268_i_shl_i_i_i_i_i_i_89_c_compstr2527_vt_select_28_b_1(DELAY,28496)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist268_i_shl_i_i_i_i_i_i_89_c_compstr2527_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_89_c_compstr2527_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_89_c_compstr2527_vt_join(BITJOIN,9765)@191
    assign i_shl_i_i_i_i_i_i_89_c_compstr2527_vt_join_q = {redist268_i_shl_i_i_i_i_i_i_89_c_compstr2527_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_offset(CONSTANT,30606)
    assign redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_offset_q = $unsigned(8'b01010100);

    // redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_rdcnt(ADD,32055)
    assign redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_a = {1'b0, redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_wraddr_q};
    assign redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_b = {1'b0, redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_o <= $unsigned(redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_a) + $unsigned(redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_b);
        end
    end
    assign redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_q = redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_o[8:0];

    // redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_inputreg0(DELAY,32050)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl);
        end
    end

    // redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_wraddr(COUNTER,32053)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_wraddr_i <= $unsigned(redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_wraddr_q = redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_wraddr_i[7:0];

    // redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem(DUALMEM,32052)
    assign redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_ia = $unsigned(redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_inputreg0_q);
    assign redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_aa = redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_wraddr_q;
    assign redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_ab = redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_aa),
        .data_a(redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_ab),
        .q_b(redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_q = redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_iq[15:0];

    // redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_outputreg0(DELAY,32051)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_outputreg0_q <= $unsigned(redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_mem_q);
        end
    end

    // redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_rdcnt(ADD,30607)
    assign redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_a = {1'b0, redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_wraddr_q};
    assign redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_b = {1'b0, redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_o <= $unsigned(redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_a) + $unsigned(redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_b);
        end
    end
    assign redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_q = redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_o[8:0];

    // redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_inputreg0(DELAY,30602)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl);
        end
    end

    // redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_wraddr(COUNTER,30605)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_wraddr_i <= $unsigned(redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_wraddr_q = redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_wraddr_i[7:0];

    // redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem(DUALMEM,30604)
    assign redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_ia = $unsigned(redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_inputreg0_q);
    assign redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_aa = redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_wraddr_q;
    assign redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_ab = redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_aa),
        .data_a(redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_ab),
        .q_b(redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_q = redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_iq[15:0];

    // redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_outputreg0(DELAY,30603)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_outputreg0_q <= $unsigned(redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_mem_q);
        end
    end

    // redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_rdcnt(ADD,30613)
    assign redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_a = {1'b0, redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_wraddr_q};
    assign redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_b = {1'b0, redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_o <= $unsigned(redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_a) + $unsigned(redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_b);
        end
    end
    assign redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_q = redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_o[8:0];

    // redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_inputreg0(DELAY,30608)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl);
        end
    end

    // redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_wraddr(COUNTER,30611)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_wraddr_i <= $unsigned(redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_wraddr_q = redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_wraddr_i[7:0];

    // redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem(DUALMEM,30610)
    assign redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_ia = $unsigned(redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_inputreg0_q);
    assign redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_aa = redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_wraddr_q;
    assign redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_ab = redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_aa),
        .data_a(redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_ab),
        .q_b(redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_q = redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_iq[15:0];

    // redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_outputreg0(DELAY,30609)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_outputreg0_q <= $unsigned(redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_mem_q);
        end
    end

    // redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_rdcnt(ADD,32049)
    assign redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_a = {1'b0, redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_wraddr_q};
    assign redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_b = {1'b0, redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_o <= $unsigned(redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_a) + $unsigned(redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_b);
        end
    end
    assign redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_q = redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_o[8:0];

    // redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_inputreg0(DELAY,32044)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl);
        end
    end

    // redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_wraddr(COUNTER,32047)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_wraddr_i <= $unsigned(redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_wraddr_q = redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_wraddr_i[7:0];

    // redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem(DUALMEM,32046)
    assign redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_ia = $unsigned(redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_inputreg0_q);
    assign redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_aa = redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_wraddr_q;
    assign redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_ab = redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_aa),
        .data_a(redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_ab),
        .q_b(redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_q = redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_iq[15:0];

    // redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_outputreg0(DELAY,32045)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_outputreg0_q <= $unsigned(redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28049)@185 + 5
    // out q@191
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528(ADD,8636)@191
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod486_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_b = $unsigned({{5{i_shl_i_i_i_i_i_i_89_c_compstr2527_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_89_c_compstr2527_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_o[33:0];

    // rightShiftStage0_uid20487_dupName_357_i_unnamed_c_compstr0_shift_x(MUX,20486)@191
    assign rightShiftStage0_uid20487_dupName_357_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20487_dupName_357_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_q or rightShiftStage0Idx1_uid20485_dupName_357_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20487_dupName_357_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20487_dupName_357_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_q;
            1'b1 : rightShiftStage0_uid20487_dupName_357_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20485_dupName_357_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20487_dupName_357_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20492_dupName_357_i_unnamed_c_compstr0_shift_x(MUX,20491)@191
    assign rightShiftStage1_uid20492_dupName_357_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20492_dupName_357_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20487_dupName_357_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20490_dupName_357_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20492_dupName_357_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20492_dupName_357_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20487_dupName_357_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20492_dupName_357_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20490_dupName_357_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20492_dupName_357_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20497_dupName_357_i_unnamed_c_compstr0_shift_x(MUX,20496)@191
    assign rightShiftStage2_uid20497_dupName_357_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20497_dupName_357_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20492_dupName_357_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20495_dupName_357_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20497_dupName_357_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20497_dupName_357_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20492_dupName_357_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20497_dupName_357_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20495_dupName_357_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20497_dupName_357_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2529_vt_select_20(BITSELECT,11128)@191
    assign i_unnamed_c_compstr2529_vt_select_20_b = rightShiftStage2_uid20497_dupName_357_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2529_vt_join(BITJOIN,11127)@191
    assign i_unnamed_c_compstr2529_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2529_vt_select_20_b};

    // i_conv_i_i_i_i_i_89_c_compstr2530_sel_x(BITSELECT,3827)@191
    assign i_conv_i_i_i_i_i_89_c_compstr2530_sel_x_b = i_unnamed_c_compstr2529_vt_join_q[15:0];

    // redist1038_i_conv_i_i_i_i_i_89_c_compstr2530_sel_x_b_1(DELAY,29266)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1038_i_conv_i_i_i_i_i_89_c_compstr2530_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_89_c_compstr2530_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20506_dupName_358_i_unnamed_c_compstr0_shift_x(BITSELECT,20505)@191
    assign rightShiftStage1Idx1Rng8_uid20506_dupName_358_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20505_dupName_358_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20508_dupName_358_i_unnamed_c_compstr0_shift_x(BITJOIN,20507)@191
    assign rightShiftStage1Idx1_uid20508_dupName_358_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20506_dupName_358_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20501_dupName_358_i_unnamed_c_compstr0_shift_x(BITSELECT,20500)@191
    assign rightShiftStage0Idx1Rng4_uid20501_dupName_358_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_q[33:4];

    // rightShiftStage0Idx1_uid20503_dupName_358_i_unnamed_c_compstr0_shift_x(BITJOIN,20502)@191
    assign rightShiftStage0Idx1_uid20503_dupName_358_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20501_dupName_358_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20505_dupName_358_i_unnamed_c_compstr0_shift_x(MUX,20504)@191
    assign rightShiftStage0_uid20505_dupName_358_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20505_dupName_358_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_q or rightShiftStage0Idx1_uid20503_dupName_358_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20505_dupName_358_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20505_dupName_358_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compstr2528_q;
            1'b1 : rightShiftStage0_uid20505_dupName_358_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20503_dupName_358_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20505_dupName_358_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20510_dupName_358_i_unnamed_c_compstr0_shift_x(MUX,20509)@191
    assign rightShiftStage1_uid20510_dupName_358_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20510_dupName_358_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20505_dupName_358_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20508_dupName_358_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20510_dupName_358_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20510_dupName_358_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20505_dupName_358_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20510_dupName_358_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20508_dupName_358_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20510_dupName_358_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2531_vt_select_21(BITSELECT,11131)@191
    assign i_unnamed_c_compstr2531_vt_select_21_b = rightShiftStage1_uid20510_dupName_358_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2531_vt_join(BITJOIN,11130)@191
    assign i_unnamed_c_compstr2531_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2531_vt_select_21_b};

    // i_unnamed_c_compstr2532_sel_x(BITSELECT,6155)@191
    assign i_unnamed_c_compstr2532_sel_x_b = i_unnamed_c_compstr2531_vt_join_q[15:0];

    // i_unnamed_c_compstr2533_BitSelect_for_a(BITSELECT,27699)@191
    assign i_unnamed_c_compstr2533_BitSelect_for_a_b = i_unnamed_c_compstr2532_sel_x_b[0:0];

    // i_unnamed_c_compstr2533_join(BITJOIN,27700)@191
    assign i_unnamed_c_compstr2533_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2533_BitSelect_for_a_b};

    // i_unnamed_c_compstr2533_vt_select_0(BITSELECT,11136)@191
    assign i_unnamed_c_compstr2533_vt_select_0_b = i_unnamed_c_compstr2533_join_q[0:0];

    // redist135_i_unnamed_c_compstr2533_vt_select_0_b_1(DELAY,28363)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist135_i_unnamed_c_compstr2533_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2533_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2533_vt_join(BITJOIN,11135)@192
    assign i_unnamed_c_compstr2533_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist135_i_unnamed_c_compstr2533_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_89_c_compstr2534(ADD,7094)@192
    assign i_add_i_i_i_i_i_i_89_c_compstr2534_a = {1'b0, i_unnamed_c_compstr2533_vt_join_q};
    assign i_add_i_i_i_i_i_i_89_c_compstr2534_b = {1'b0, redist1038_i_conv_i_i_i_i_i_89_c_compstr2530_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_89_c_compstr2534_o = $unsigned(i_add_i_i_i_i_i_i_89_c_compstr2534_a) + $unsigned(i_add_i_i_i_i_i_i_89_c_compstr2534_b);
    assign i_add_i_i_i_i_i_i_89_c_compstr2534_q = i_add_i_i_i_i_i_i_89_c_compstr2534_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_89_c_compstr2534_sel_x(BITSELECT,2288)@192
    assign bgTrunc_i_add_i_i_i_i_i_i_89_c_compstr2534_sel_x_b = i_add_i_i_i_i_i_i_89_c_compstr2534_q[15:0];

    // i_conv_i_i_i_i_i_i279_90_c_compstr2554_sel_x(BITSELECT,3957)@192
    assign i_conv_i_i_i_i_i_i279_90_c_compstr2554_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_89_c_compstr2534_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_90_c_compstr2554_vt_select_15(BITSELECT,8345)@192
    assign i_conv_i_i_i_i_i_i279_90_c_compstr2554_vt_select_15_b = i_conv_i_i_i_i_i_i279_90_c_compstr2554_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_90_c_compstr2554_vt_join(BITJOIN,8344)@192
    assign i_conv_i_i_i_i_i_i279_90_c_compstr2554_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_90_c_compstr2554_vt_select_15_b};

    // leftShiftStage0_uid27248_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x(MUX,27247)@192
    assign leftShiftStage0_uid27248_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27248_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_90_c_compstr2554_vt_join_q or leftShiftStage0Idx1_uid27246_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27248_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27248_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_90_c_compstr2554_vt_join_q;
            1'b1 : leftShiftStage0_uid27248_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27246_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27248_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27253_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x(MUX,27252)@192
    assign leftShiftStage1_uid27253_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27253_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_s or leftShiftStage0_uid27248_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27251_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27253_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27253_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q = leftShiftStage0_uid27248_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27253_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27251_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27253_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27258_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x(MUX,27257)@192
    assign leftShiftStage2_uid27258_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27258_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_s or leftShiftStage1_uid27253_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27256_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27258_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27258_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q = leftShiftStage1_uid27253_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27258_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27256_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27258_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_90_c_compstr2555_vt_select_28(BITSELECT,9772)@192
    assign i_shl_i_i_i_i_i_i_90_c_compstr2555_vt_select_28_b = leftShiftStage2_uid27258_i_shl_i_i_i_i_i_i_90_c_compstr0_shift_x_q[28:13];

    // redist266_i_shl_i_i_i_i_i_i_90_c_compstr2555_vt_select_28_b_1(DELAY,28494)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist266_i_shl_i_i_i_i_i_i_90_c_compstr2555_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_90_c_compstr2555_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_90_c_compstr2555_vt_join(BITJOIN,9771)@193
    assign i_shl_i_i_i_i_i_i_90_c_compstr2555_vt_join_q = {redist266_i_shl_i_i_i_i_i_i_90_c_compstr2555_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_offset(CONSTANT,30618)
    assign redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_offset_q = $unsigned(8'b01010010);

    // redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_rdcnt(ADD,32067)
    assign redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_a = {1'b0, redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_wraddr_q};
    assign redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_b = {1'b0, redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_o <= $unsigned(redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_a) + $unsigned(redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_b);
        end
    end
    assign redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_q = redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_o[8:0];

    // redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_inputreg0(DELAY,32062)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl);
        end
    end

    // redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_wraddr(COUNTER,32065)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_wraddr_i <= $unsigned(redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_wraddr_q = redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_wraddr_i[7:0];

    // redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem(DUALMEM,32064)
    assign redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_ia = $unsigned(redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_inputreg0_q);
    assign redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_aa = redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_wraddr_q;
    assign redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_ab = redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_aa),
        .data_a(redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_ab),
        .q_b(redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_q = redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_iq[15:0];

    // redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_outputreg0(DELAY,32063)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_outputreg0_q <= $unsigned(redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_mem_q);
        end
    end

    // redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_rdcnt(ADD,30619)
    assign redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_a = {1'b0, redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_wraddr_q};
    assign redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_b = {1'b0, redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_o <= $unsigned(redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_a) + $unsigned(redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_b);
        end
    end
    assign redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_q = redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_o[8:0];

    // redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_inputreg0(DELAY,30614)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl);
        end
    end

    // redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_wraddr(COUNTER,30617)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_wraddr_i <= $unsigned(redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_wraddr_q = redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_wraddr_i[7:0];

    // redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem(DUALMEM,30616)
    assign redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_ia = $unsigned(redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_inputreg0_q);
    assign redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_aa = redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_wraddr_q;
    assign redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_ab = redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_aa),
        .data_a(redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_ab),
        .q_b(redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_q = redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_iq[15:0];

    // redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_outputreg0(DELAY,30615)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_outputreg0_q <= $unsigned(redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_mem_q);
        end
    end

    // redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_rdcnt(ADD,30625)
    assign redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_a = {1'b0, redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_wraddr_q};
    assign redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_b = {1'b0, redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_o <= $unsigned(redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_a) + $unsigned(redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_b);
        end
    end
    assign redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_q = redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_o[8:0];

    // redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_inputreg0(DELAY,30620)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl);
        end
    end

    // redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_wraddr(COUNTER,30623)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_wraddr_i <= $unsigned(redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_wraddr_q = redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_wraddr_i[7:0];

    // redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem(DUALMEM,30622)
    assign redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_ia = $unsigned(redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_inputreg0_q);
    assign redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_aa = redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_wraddr_q;
    assign redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_ab = redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_aa),
        .data_a(redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_ab),
        .q_b(redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_q = redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_iq[15:0];

    // redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_outputreg0(DELAY,30621)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_outputreg0_q <= $unsigned(redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_mem_q);
        end
    end

    // redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_rdcnt(ADD,32061)
    assign redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_a = {1'b0, redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_wraddr_q};
    assign redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_b = {1'b0, redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_o <= $unsigned(redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_a) + $unsigned(redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_b);
        end
    end
    assign redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_q = redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_o[8:0];

    // redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_inputreg0(DELAY,32056)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl);
        end
    end

    // redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_wraddr(COUNTER,32059)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_wraddr_i <= $unsigned(redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_wraddr_q = redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_wraddr_i[7:0];

    // redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem(DUALMEM,32058)
    assign redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_ia = $unsigned(redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_inputreg0_q);
    assign redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_aa = redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_wraddr_q;
    assign redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_ab = redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_aa),
        .data_a(redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_ab),
        .q_b(redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_q = redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_iq[15:0];

    // redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_outputreg0(DELAY,32057)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_outputreg0_q <= $unsigned(redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28050)@187 + 5
    // out q@193
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556(ADD,8638)@193
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod491_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_b = $unsigned({{5{i_shl_i_i_i_i_i_i_90_c_compstr2555_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_90_c_compstr2555_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_o[33:0];

    // rightShiftStage0_uid20549_dupName_361_i_unnamed_c_compstr0_shift_x(MUX,20548)@193
    assign rightShiftStage0_uid20549_dupName_361_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20549_dupName_361_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_q or rightShiftStage0Idx1_uid20547_dupName_361_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20549_dupName_361_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20549_dupName_361_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_q;
            1'b1 : rightShiftStage0_uid20549_dupName_361_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20547_dupName_361_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20549_dupName_361_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20554_dupName_361_i_unnamed_c_compstr0_shift_x(MUX,20553)@193
    assign rightShiftStage1_uid20554_dupName_361_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20554_dupName_361_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20549_dupName_361_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20552_dupName_361_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20554_dupName_361_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20554_dupName_361_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20549_dupName_361_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20554_dupName_361_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20552_dupName_361_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20554_dupName_361_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20559_dupName_361_i_unnamed_c_compstr0_shift_x(MUX,20558)@193
    assign rightShiftStage2_uid20559_dupName_361_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20559_dupName_361_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20554_dupName_361_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20557_dupName_361_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20559_dupName_361_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20559_dupName_361_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20554_dupName_361_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20559_dupName_361_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20557_dupName_361_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20559_dupName_361_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2557_vt_select_20(BITSELECT,11150)@193
    assign i_unnamed_c_compstr2557_vt_select_20_b = rightShiftStage2_uid20559_dupName_361_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2557_vt_join(BITJOIN,11149)@193
    assign i_unnamed_c_compstr2557_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2557_vt_select_20_b};

    // i_conv_i_i_i_i_i_90_c_compstr2558_sel_x(BITSELECT,3829)@193
    assign i_conv_i_i_i_i_i_90_c_compstr2558_sel_x_b = i_unnamed_c_compstr2557_vt_join_q[15:0];

    // redist1036_i_conv_i_i_i_i_i_90_c_compstr2558_sel_x_b_1(DELAY,29264)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1036_i_conv_i_i_i_i_i_90_c_compstr2558_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_90_c_compstr2558_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20568_dupName_362_i_unnamed_c_compstr0_shift_x(BITSELECT,20567)@193
    assign rightShiftStage1Idx1Rng8_uid20568_dupName_362_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20567_dupName_362_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20570_dupName_362_i_unnamed_c_compstr0_shift_x(BITJOIN,20569)@193
    assign rightShiftStage1Idx1_uid20570_dupName_362_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20568_dupName_362_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20563_dupName_362_i_unnamed_c_compstr0_shift_x(BITSELECT,20562)@193
    assign rightShiftStage0Idx1Rng4_uid20563_dupName_362_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_q[33:4];

    // rightShiftStage0Idx1_uid20565_dupName_362_i_unnamed_c_compstr0_shift_x(BITJOIN,20564)@193
    assign rightShiftStage0Idx1_uid20565_dupName_362_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20563_dupName_362_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20567_dupName_362_i_unnamed_c_compstr0_shift_x(MUX,20566)@193
    assign rightShiftStage0_uid20567_dupName_362_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20567_dupName_362_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_q or rightShiftStage0Idx1_uid20565_dupName_362_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20567_dupName_362_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20567_dupName_362_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compstr2556_q;
            1'b1 : rightShiftStage0_uid20567_dupName_362_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20565_dupName_362_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20567_dupName_362_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20572_dupName_362_i_unnamed_c_compstr0_shift_x(MUX,20571)@193
    assign rightShiftStage1_uid20572_dupName_362_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20572_dupName_362_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20567_dupName_362_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20570_dupName_362_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20572_dupName_362_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20572_dupName_362_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20567_dupName_362_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20572_dupName_362_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20570_dupName_362_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20572_dupName_362_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2559_vt_select_21(BITSELECT,11153)@193
    assign i_unnamed_c_compstr2559_vt_select_21_b = rightShiftStage1_uid20572_dupName_362_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2559_vt_join(BITJOIN,11152)@193
    assign i_unnamed_c_compstr2559_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2559_vt_select_21_b};

    // i_unnamed_c_compstr2560_sel_x(BITSELECT,6157)@193
    assign i_unnamed_c_compstr2560_sel_x_b = i_unnamed_c_compstr2559_vt_join_q[15:0];

    // i_unnamed_c_compstr2561_BitSelect_for_a(BITSELECT,27703)@193
    assign i_unnamed_c_compstr2561_BitSelect_for_a_b = i_unnamed_c_compstr2560_sel_x_b[0:0];

    // i_unnamed_c_compstr2561_join(BITJOIN,27704)@193
    assign i_unnamed_c_compstr2561_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2561_BitSelect_for_a_b};

    // i_unnamed_c_compstr2561_vt_select_0(BITSELECT,11158)@193
    assign i_unnamed_c_compstr2561_vt_select_0_b = i_unnamed_c_compstr2561_join_q[0:0];

    // redist133_i_unnamed_c_compstr2561_vt_select_0_b_1(DELAY,28361)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist133_i_unnamed_c_compstr2561_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2561_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2561_vt_join(BITJOIN,11157)@194
    assign i_unnamed_c_compstr2561_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist133_i_unnamed_c_compstr2561_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_90_c_compstr2562(ADD,7096)@194
    assign i_add_i_i_i_i_i_i_90_c_compstr2562_a = {1'b0, i_unnamed_c_compstr2561_vt_join_q};
    assign i_add_i_i_i_i_i_i_90_c_compstr2562_b = {1'b0, redist1036_i_conv_i_i_i_i_i_90_c_compstr2558_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_90_c_compstr2562_o = $unsigned(i_add_i_i_i_i_i_i_90_c_compstr2562_a) + $unsigned(i_add_i_i_i_i_i_i_90_c_compstr2562_b);
    assign i_add_i_i_i_i_i_i_90_c_compstr2562_q = i_add_i_i_i_i_i_i_90_c_compstr2562_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_90_c_compstr2562_sel_x(BITSELECT,2290)@194
    assign bgTrunc_i_add_i_i_i_i_i_i_90_c_compstr2562_sel_x_b = i_add_i_i_i_i_i_i_90_c_compstr2562_q[15:0];

    // i_conv_i_i_i_i_i_i279_91_c_compstr2582_sel_x(BITSELECT,3958)@194
    assign i_conv_i_i_i_i_i_i279_91_c_compstr2582_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_90_c_compstr2562_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_91_c_compstr2582_vt_select_15(BITSELECT,8349)@194
    assign i_conv_i_i_i_i_i_i279_91_c_compstr2582_vt_select_15_b = i_conv_i_i_i_i_i_i279_91_c_compstr2582_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_91_c_compstr2582_vt_join(BITJOIN,8348)@194
    assign i_conv_i_i_i_i_i_i279_91_c_compstr2582_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_91_c_compstr2582_vt_select_15_b};

    // leftShiftStage0_uid27266_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x(MUX,27265)@194
    assign leftShiftStage0_uid27266_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27266_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_91_c_compstr2582_vt_join_q or leftShiftStage0Idx1_uid27264_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27266_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27266_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_91_c_compstr2582_vt_join_q;
            1'b1 : leftShiftStage0_uid27266_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27264_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27266_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27271_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x(MUX,27270)@194
    assign leftShiftStage1_uid27271_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27271_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_s or leftShiftStage0_uid27266_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27269_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27271_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27271_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q = leftShiftStage0_uid27266_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27271_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27269_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27271_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27276_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x(MUX,27275)@194
    assign leftShiftStage2_uid27276_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27276_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_s or leftShiftStage1_uid27271_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27274_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27276_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27276_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q = leftShiftStage1_uid27271_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27276_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27274_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27276_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_91_c_compstr2583_vt_select_28(BITSELECT,9775)@194
    assign i_shl_i_i_i_i_i_i_91_c_compstr2583_vt_select_28_b = leftShiftStage2_uid27276_i_shl_i_i_i_i_i_i_91_c_compstr0_shift_x_q[28:13];

    // redist265_i_shl_i_i_i_i_i_i_91_c_compstr2583_vt_select_28_b_1(DELAY,28493)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist265_i_shl_i_i_i_i_i_i_91_c_compstr2583_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_91_c_compstr2583_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_91_c_compstr2583_vt_join(BITJOIN,9774)@195
    assign i_shl_i_i_i_i_i_i_91_c_compstr2583_vt_join_q = {redist265_i_shl_i_i_i_i_i_i_91_c_compstr2583_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_offset(CONSTANT,30630)
    assign redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_offset_q = $unsigned(8'b01010000);

    // redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_rdcnt(ADD,32079)
    assign redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_a = {1'b0, redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_wraddr_q};
    assign redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_b = {1'b0, redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_o <= $unsigned(redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_a) + $unsigned(redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_b);
        end
    end
    assign redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_q = redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_o[8:0];

    // redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_inputreg0(DELAY,32074)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl);
        end
    end

    // redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_wraddr(COUNTER,32077)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_wraddr_i <= $unsigned(redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_wraddr_q = redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_wraddr_i[7:0];

    // redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem(DUALMEM,32076)
    assign redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_ia = $unsigned(redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_inputreg0_q);
    assign redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_aa = redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_wraddr_q;
    assign redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_ab = redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_aa),
        .data_a(redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_ab),
        .q_b(redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_q = redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_iq[15:0];

    // redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_outputreg0(DELAY,32075)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_outputreg0_q <= $unsigned(redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_mem_q);
        end
    end

    // redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_rdcnt(ADD,30631)
    assign redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_a = {1'b0, redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_wraddr_q};
    assign redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_b = {1'b0, redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_o <= $unsigned(redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_a) + $unsigned(redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_b);
        end
    end
    assign redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_q = redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_o[8:0];

    // redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_inputreg0(DELAY,30626)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl);
        end
    end

    // redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_wraddr(COUNTER,30629)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_wraddr_i <= $unsigned(redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_wraddr_q = redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_wraddr_i[7:0];

    // redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem(DUALMEM,30628)
    assign redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_ia = $unsigned(redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_inputreg0_q);
    assign redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_aa = redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_wraddr_q;
    assign redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_ab = redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_aa),
        .data_a(redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_ab),
        .q_b(redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_q = redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_iq[15:0];

    // redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_outputreg0(DELAY,30627)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_outputreg0_q <= $unsigned(redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_mem_q);
        end
    end

    // redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_rdcnt(ADD,30637)
    assign redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_a = {1'b0, redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_wraddr_q};
    assign redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_b = {1'b0, redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_o <= $unsigned(redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_a) + $unsigned(redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_b);
        end
    end
    assign redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_q = redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_o[8:0];

    // redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_inputreg0(DELAY,30632)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl);
        end
    end

    // redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_wraddr(COUNTER,30635)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_wraddr_i <= $unsigned(redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_wraddr_q = redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_wraddr_i[7:0];

    // redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem(DUALMEM,30634)
    assign redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_ia = $unsigned(redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_inputreg0_q);
    assign redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_aa = redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_wraddr_q;
    assign redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_ab = redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_aa),
        .data_a(redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_ab),
        .q_b(redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_q = redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_iq[15:0];

    // redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_outputreg0(DELAY,30633)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_outputreg0_q <= $unsigned(redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_mem_q);
        end
    end

    // redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_rdcnt(ADD,32073)
    assign redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_a = {1'b0, redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_wraddr_q};
    assign redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_b = {1'b0, redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_o <= $unsigned(redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_a) + $unsigned(redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_b);
        end
    end
    assign redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_q = redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_o[8:0];

    // redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_inputreg0(DELAY,32068)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl);
        end
    end

    // redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_wraddr(COUNTER,32071)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_wraddr_i <= $unsigned(redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_wraddr_q = redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_wraddr_i[7:0];

    // redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem(DUALMEM,32070)
    assign redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_ia = $unsigned(redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_inputreg0_q);
    assign redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_aa = redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_wraddr_q;
    assign redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_ab = redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_aa),
        .data_a(redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_ab),
        .q_b(redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_q = redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_iq[15:0];

    // redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_outputreg0(DELAY,32069)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_outputreg0_q <= $unsigned(redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28051)@189 + 5
    // out q@195
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584(ADD,8639)@195
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod496_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_b = $unsigned({{5{i_shl_i_i_i_i_i_i_91_c_compstr2583_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_91_c_compstr2583_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_o[33:0];

    // rightShiftStage0_uid20611_dupName_365_i_unnamed_c_compstr0_shift_x(MUX,20610)@195
    assign rightShiftStage0_uid20611_dupName_365_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20611_dupName_365_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_q or rightShiftStage0Idx1_uid20609_dupName_365_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20611_dupName_365_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20611_dupName_365_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_q;
            1'b1 : rightShiftStage0_uid20611_dupName_365_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20609_dupName_365_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20611_dupName_365_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20616_dupName_365_i_unnamed_c_compstr0_shift_x(MUX,20615)@195
    assign rightShiftStage1_uid20616_dupName_365_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20616_dupName_365_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20611_dupName_365_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20614_dupName_365_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20616_dupName_365_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20616_dupName_365_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20611_dupName_365_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20616_dupName_365_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20614_dupName_365_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20616_dupName_365_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20621_dupName_365_i_unnamed_c_compstr0_shift_x(MUX,20620)@195
    assign rightShiftStage2_uid20621_dupName_365_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20621_dupName_365_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20616_dupName_365_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20619_dupName_365_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20621_dupName_365_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20621_dupName_365_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20616_dupName_365_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20621_dupName_365_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20619_dupName_365_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20621_dupName_365_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2585_vt_select_20(BITSELECT,11172)@195
    assign i_unnamed_c_compstr2585_vt_select_20_b = rightShiftStage2_uid20621_dupName_365_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2585_vt_join(BITJOIN,11171)@195
    assign i_unnamed_c_compstr2585_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2585_vt_select_20_b};

    // i_conv_i_i_i_i_i_91_c_compstr2586_sel_x(BITSELECT,3830)@195
    assign i_conv_i_i_i_i_i_91_c_compstr2586_sel_x_b = i_unnamed_c_compstr2585_vt_join_q[15:0];

    // redist1035_i_conv_i_i_i_i_i_91_c_compstr2586_sel_x_b_1(DELAY,29263)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1035_i_conv_i_i_i_i_i_91_c_compstr2586_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_91_c_compstr2586_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20630_dupName_366_i_unnamed_c_compstr0_shift_x(BITSELECT,20629)@195
    assign rightShiftStage1Idx1Rng8_uid20630_dupName_366_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20629_dupName_366_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20632_dupName_366_i_unnamed_c_compstr0_shift_x(BITJOIN,20631)@195
    assign rightShiftStage1Idx1_uid20632_dupName_366_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20630_dupName_366_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20625_dupName_366_i_unnamed_c_compstr0_shift_x(BITSELECT,20624)@195
    assign rightShiftStage0Idx1Rng4_uid20625_dupName_366_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_q[33:4];

    // rightShiftStage0Idx1_uid20627_dupName_366_i_unnamed_c_compstr0_shift_x(BITJOIN,20626)@195
    assign rightShiftStage0Idx1_uid20627_dupName_366_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20625_dupName_366_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20629_dupName_366_i_unnamed_c_compstr0_shift_x(MUX,20628)@195
    assign rightShiftStage0_uid20629_dupName_366_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20629_dupName_366_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_q or rightShiftStage0Idx1_uid20627_dupName_366_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20629_dupName_366_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20629_dupName_366_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compstr2584_q;
            1'b1 : rightShiftStage0_uid20629_dupName_366_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20627_dupName_366_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20629_dupName_366_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20634_dupName_366_i_unnamed_c_compstr0_shift_x(MUX,20633)@195
    assign rightShiftStage1_uid20634_dupName_366_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20634_dupName_366_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20629_dupName_366_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20632_dupName_366_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20634_dupName_366_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20634_dupName_366_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20629_dupName_366_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20634_dupName_366_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20632_dupName_366_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20634_dupName_366_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2587_vt_select_21(BITSELECT,11175)@195
    assign i_unnamed_c_compstr2587_vt_select_21_b = rightShiftStage1_uid20634_dupName_366_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2587_vt_join(BITJOIN,11174)@195
    assign i_unnamed_c_compstr2587_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2587_vt_select_21_b};

    // i_unnamed_c_compstr2588_sel_x(BITSELECT,6159)@195
    assign i_unnamed_c_compstr2588_sel_x_b = i_unnamed_c_compstr2587_vt_join_q[15:0];

    // i_unnamed_c_compstr2589_BitSelect_for_a(BITSELECT,27707)@195
    assign i_unnamed_c_compstr2589_BitSelect_for_a_b = i_unnamed_c_compstr2588_sel_x_b[0:0];

    // i_unnamed_c_compstr2589_join(BITJOIN,27708)@195
    assign i_unnamed_c_compstr2589_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2589_BitSelect_for_a_b};

    // i_unnamed_c_compstr2589_vt_select_0(BITSELECT,11180)@195
    assign i_unnamed_c_compstr2589_vt_select_0_b = i_unnamed_c_compstr2589_join_q[0:0];

    // redist131_i_unnamed_c_compstr2589_vt_select_0_b_1(DELAY,28359)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist131_i_unnamed_c_compstr2589_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2589_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2589_vt_join(BITJOIN,11179)@196
    assign i_unnamed_c_compstr2589_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist131_i_unnamed_c_compstr2589_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_91_c_compstr2590(ADD,7097)@196
    assign i_add_i_i_i_i_i_i_91_c_compstr2590_a = {1'b0, i_unnamed_c_compstr2589_vt_join_q};
    assign i_add_i_i_i_i_i_i_91_c_compstr2590_b = {1'b0, redist1035_i_conv_i_i_i_i_i_91_c_compstr2586_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_91_c_compstr2590_o = $unsigned(i_add_i_i_i_i_i_i_91_c_compstr2590_a) + $unsigned(i_add_i_i_i_i_i_i_91_c_compstr2590_b);
    assign i_add_i_i_i_i_i_i_91_c_compstr2590_q = i_add_i_i_i_i_i_i_91_c_compstr2590_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_91_c_compstr2590_sel_x(BITSELECT,2291)@196
    assign bgTrunc_i_add_i_i_i_i_i_i_91_c_compstr2590_sel_x_b = i_add_i_i_i_i_i_i_91_c_compstr2590_q[15:0];

    // i_conv_i_i_i_i_i_i279_92_c_compstr2610_sel_x(BITSELECT,3959)@196
    assign i_conv_i_i_i_i_i_i279_92_c_compstr2610_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_91_c_compstr2590_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_92_c_compstr2610_vt_select_15(BITSELECT,8353)@196
    assign i_conv_i_i_i_i_i_i279_92_c_compstr2610_vt_select_15_b = i_conv_i_i_i_i_i_i279_92_c_compstr2610_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_92_c_compstr2610_vt_join(BITJOIN,8352)@196
    assign i_conv_i_i_i_i_i_i279_92_c_compstr2610_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_92_c_compstr2610_vt_select_15_b};

    // leftShiftStage0_uid27284_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x(MUX,27283)@196
    assign leftShiftStage0_uid27284_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27284_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_92_c_compstr2610_vt_join_q or leftShiftStage0Idx1_uid27282_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27284_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27284_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_92_c_compstr2610_vt_join_q;
            1'b1 : leftShiftStage0_uid27284_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27282_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27284_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27289_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x(MUX,27288)@196
    assign leftShiftStage1_uid27289_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27289_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_s or leftShiftStage0_uid27284_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27287_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27289_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27289_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q = leftShiftStage0_uid27284_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27289_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27287_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27289_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27294_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x(MUX,27293)@196
    assign leftShiftStage2_uid27294_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27294_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_s or leftShiftStage1_uid27289_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27292_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27294_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27294_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q = leftShiftStage1_uid27289_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27294_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27292_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27294_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_92_c_compstr2611_vt_select_28(BITSELECT,9778)@196
    assign i_shl_i_i_i_i_i_i_92_c_compstr2611_vt_select_28_b = leftShiftStage2_uid27294_i_shl_i_i_i_i_i_i_92_c_compstr0_shift_x_q[28:13];

    // redist264_i_shl_i_i_i_i_i_i_92_c_compstr2611_vt_select_28_b_1(DELAY,28492)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist264_i_shl_i_i_i_i_i_i_92_c_compstr2611_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_92_c_compstr2611_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_92_c_compstr2611_vt_join(BITJOIN,9777)@197
    assign i_shl_i_i_i_i_i_i_92_c_compstr2611_vt_join_q = {redist264_i_shl_i_i_i_i_i_i_92_c_compstr2611_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_offset(CONSTANT,30642)
    assign redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_offset_q = $unsigned(8'b01001110);

    // redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_rdcnt(ADD,32091)
    assign redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_a = {1'b0, redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_wraddr_q};
    assign redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_b = {1'b0, redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_o <= $unsigned(redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_a) + $unsigned(redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_b);
        end
    end
    assign redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_q = redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_o[8:0];

    // redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_inputreg0(DELAY,32086)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl);
        end
    end

    // redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_wraddr(COUNTER,32089)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_wraddr_i <= $unsigned(redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_wraddr_q = redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_wraddr_i[7:0];

    // redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem(DUALMEM,32088)
    assign redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_ia = $unsigned(redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_inputreg0_q);
    assign redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_aa = redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_wraddr_q;
    assign redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_ab = redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_aa),
        .data_a(redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_ab),
        .q_b(redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_q = redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_iq[15:0];

    // redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_outputreg0(DELAY,32087)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_outputreg0_q <= $unsigned(redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_mem_q);
        end
    end

    // redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_rdcnt(ADD,30643)
    assign redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_a = {1'b0, redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_wraddr_q};
    assign redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_b = {1'b0, redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_o <= $unsigned(redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_a) + $unsigned(redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_b);
        end
    end
    assign redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_q = redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_o[8:0];

    // redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_inputreg0(DELAY,30638)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl);
        end
    end

    // redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_wraddr(COUNTER,30641)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_wraddr_i <= $unsigned(redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_wraddr_q = redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_wraddr_i[7:0];

    // redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem(DUALMEM,30640)
    assign redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_ia = $unsigned(redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_inputreg0_q);
    assign redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_aa = redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_wraddr_q;
    assign redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_ab = redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_aa),
        .data_a(redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_ab),
        .q_b(redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_q = redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_iq[15:0];

    // redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_outputreg0(DELAY,30639)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_outputreg0_q <= $unsigned(redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_mem_q);
        end
    end

    // redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_rdcnt(ADD,30649)
    assign redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_a = {1'b0, redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_wraddr_q};
    assign redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_b = {1'b0, redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_o <= $unsigned(redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_a) + $unsigned(redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_b);
        end
    end
    assign redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_q = redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_o[8:0];

    // redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_inputreg0(DELAY,30644)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl);
        end
    end

    // redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_wraddr(COUNTER,30647)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_wraddr_i <= $unsigned(redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_wraddr_q = redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_wraddr_i[7:0];

    // redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem(DUALMEM,30646)
    assign redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_ia = $unsigned(redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_inputreg0_q);
    assign redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_aa = redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_wraddr_q;
    assign redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_ab = redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_aa),
        .data_a(redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_ab),
        .q_b(redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_q = redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_iq[15:0];

    // redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_outputreg0(DELAY,30645)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_outputreg0_q <= $unsigned(redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_mem_q);
        end
    end

    // redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_rdcnt(ADD,32085)
    assign redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_a = {1'b0, redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_wraddr_q};
    assign redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_b = {1'b0, redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_o <= $unsigned(redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_a) + $unsigned(redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_b);
        end
    end
    assign redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_q = redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_o[8:0];

    // redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_inputreg0(DELAY,32080)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl);
        end
    end

    // redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_wraddr(COUNTER,32083)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_wraddr_i <= $unsigned(redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_wraddr_q = redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_wraddr_i[7:0];

    // redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem(DUALMEM,32082)
    assign redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_ia = $unsigned(redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_inputreg0_q);
    assign redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_aa = redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_wraddr_q;
    assign redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_ab = redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_aa),
        .data_a(redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_ab),
        .q_b(redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_q = redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_iq[15:0];

    // redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_outputreg0(DELAY,32081)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_outputreg0_q <= $unsigned(redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28052)@191 + 5
    // out q@197
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612(ADD,8640)@197
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod501_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_b = $unsigned({{5{i_shl_i_i_i_i_i_i_92_c_compstr2611_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_92_c_compstr2611_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_o[33:0];

    // rightShiftStage0_uid20673_dupName_369_i_unnamed_c_compstr0_shift_x(MUX,20672)@197
    assign rightShiftStage0_uid20673_dupName_369_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20673_dupName_369_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_q or rightShiftStage0Idx1_uid20671_dupName_369_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20673_dupName_369_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20673_dupName_369_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_q;
            1'b1 : rightShiftStage0_uid20673_dupName_369_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20671_dupName_369_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20673_dupName_369_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20678_dupName_369_i_unnamed_c_compstr0_shift_x(MUX,20677)@197
    assign rightShiftStage1_uid20678_dupName_369_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20678_dupName_369_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20673_dupName_369_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20676_dupName_369_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20678_dupName_369_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20678_dupName_369_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20673_dupName_369_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20678_dupName_369_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20676_dupName_369_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20678_dupName_369_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20683_dupName_369_i_unnamed_c_compstr0_shift_x(MUX,20682)@197
    assign rightShiftStage2_uid20683_dupName_369_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20683_dupName_369_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20678_dupName_369_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20681_dupName_369_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20683_dupName_369_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20683_dupName_369_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20678_dupName_369_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20683_dupName_369_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20681_dupName_369_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20683_dupName_369_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2613_vt_select_20(BITSELECT,11197)@197
    assign i_unnamed_c_compstr2613_vt_select_20_b = rightShiftStage2_uid20683_dupName_369_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2613_vt_join(BITJOIN,11196)@197
    assign i_unnamed_c_compstr2613_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2613_vt_select_20_b};

    // i_conv_i_i_i_i_i_92_c_compstr2614_sel_x(BITSELECT,3831)@197
    assign i_conv_i_i_i_i_i_92_c_compstr2614_sel_x_b = i_unnamed_c_compstr2613_vt_join_q[15:0];

    // redist1034_i_conv_i_i_i_i_i_92_c_compstr2614_sel_x_b_1(DELAY,29262)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1034_i_conv_i_i_i_i_i_92_c_compstr2614_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_92_c_compstr2614_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20692_dupName_370_i_unnamed_c_compstr0_shift_x(BITSELECT,20691)@197
    assign rightShiftStage1Idx1Rng8_uid20692_dupName_370_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20691_dupName_370_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20694_dupName_370_i_unnamed_c_compstr0_shift_x(BITJOIN,20693)@197
    assign rightShiftStage1Idx1_uid20694_dupName_370_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20692_dupName_370_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20687_dupName_370_i_unnamed_c_compstr0_shift_x(BITSELECT,20686)@197
    assign rightShiftStage0Idx1Rng4_uid20687_dupName_370_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_q[33:4];

    // rightShiftStage0Idx1_uid20689_dupName_370_i_unnamed_c_compstr0_shift_x(BITJOIN,20688)@197
    assign rightShiftStage0Idx1_uid20689_dupName_370_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20687_dupName_370_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20691_dupName_370_i_unnamed_c_compstr0_shift_x(MUX,20690)@197
    assign rightShiftStage0_uid20691_dupName_370_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20691_dupName_370_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_q or rightShiftStage0Idx1_uid20689_dupName_370_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20691_dupName_370_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20691_dupName_370_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compstr2612_q;
            1'b1 : rightShiftStage0_uid20691_dupName_370_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20689_dupName_370_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20691_dupName_370_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20696_dupName_370_i_unnamed_c_compstr0_shift_x(MUX,20695)@197
    assign rightShiftStage1_uid20696_dupName_370_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20696_dupName_370_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20691_dupName_370_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20694_dupName_370_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20696_dupName_370_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20696_dupName_370_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20691_dupName_370_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20696_dupName_370_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20694_dupName_370_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20696_dupName_370_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2615_vt_select_21(BITSELECT,11200)@197
    assign i_unnamed_c_compstr2615_vt_select_21_b = rightShiftStage1_uid20696_dupName_370_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2615_vt_join(BITJOIN,11199)@197
    assign i_unnamed_c_compstr2615_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2615_vt_select_21_b};

    // i_unnamed_c_compstr2616_sel_x(BITSELECT,6162)@197
    assign i_unnamed_c_compstr2616_sel_x_b = i_unnamed_c_compstr2615_vt_join_q[15:0];

    // i_unnamed_c_compstr2617_BitSelect_for_a(BITSELECT,27711)@197
    assign i_unnamed_c_compstr2617_BitSelect_for_a_b = i_unnamed_c_compstr2616_sel_x_b[0:0];

    // i_unnamed_c_compstr2617_join(BITJOIN,27712)@197
    assign i_unnamed_c_compstr2617_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2617_BitSelect_for_a_b};

    // i_unnamed_c_compstr2617_vt_select_0(BITSELECT,11205)@197
    assign i_unnamed_c_compstr2617_vt_select_0_b = i_unnamed_c_compstr2617_join_q[0:0];

    // redist129_i_unnamed_c_compstr2617_vt_select_0_b_1(DELAY,28357)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist129_i_unnamed_c_compstr2617_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2617_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2617_vt_join(BITJOIN,11204)@198
    assign i_unnamed_c_compstr2617_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist129_i_unnamed_c_compstr2617_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_92_c_compstr2618(ADD,7098)@198
    assign i_add_i_i_i_i_i_i_92_c_compstr2618_a = {1'b0, i_unnamed_c_compstr2617_vt_join_q};
    assign i_add_i_i_i_i_i_i_92_c_compstr2618_b = {1'b0, redist1034_i_conv_i_i_i_i_i_92_c_compstr2614_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_92_c_compstr2618_o = $unsigned(i_add_i_i_i_i_i_i_92_c_compstr2618_a) + $unsigned(i_add_i_i_i_i_i_i_92_c_compstr2618_b);
    assign i_add_i_i_i_i_i_i_92_c_compstr2618_q = i_add_i_i_i_i_i_i_92_c_compstr2618_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_92_c_compstr2618_sel_x(BITSELECT,2292)@198
    assign bgTrunc_i_add_i_i_i_i_i_i_92_c_compstr2618_sel_x_b = i_add_i_i_i_i_i_i_92_c_compstr2618_q[15:0];

    // i_conv_i_i_i_i_i_i279_93_c_compstr2638_sel_x(BITSELECT,3960)@198
    assign i_conv_i_i_i_i_i_i279_93_c_compstr2638_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_92_c_compstr2618_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_93_c_compstr2638_vt_select_15(BITSELECT,8357)@198
    assign i_conv_i_i_i_i_i_i279_93_c_compstr2638_vt_select_15_b = i_conv_i_i_i_i_i_i279_93_c_compstr2638_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_93_c_compstr2638_vt_join(BITJOIN,8356)@198
    assign i_conv_i_i_i_i_i_i279_93_c_compstr2638_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_93_c_compstr2638_vt_select_15_b};

    // leftShiftStage0_uid27302_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x(MUX,27301)@198
    assign leftShiftStage0_uid27302_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27302_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_93_c_compstr2638_vt_join_q or leftShiftStage0Idx1_uid27300_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27302_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27302_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_93_c_compstr2638_vt_join_q;
            1'b1 : leftShiftStage0_uid27302_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27300_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27302_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27307_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x(MUX,27306)@198
    assign leftShiftStage1_uid27307_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27307_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_s or leftShiftStage0_uid27302_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27305_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27307_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27307_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q = leftShiftStage0_uid27302_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27307_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27305_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27307_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27312_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x(MUX,27311)@198
    assign leftShiftStage2_uid27312_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27312_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_s or leftShiftStage1_uid27307_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27310_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27312_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27312_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q = leftShiftStage1_uid27307_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27312_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27310_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27312_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_93_c_compstr2639_vt_select_28(BITSELECT,9781)@198
    assign i_shl_i_i_i_i_i_i_93_c_compstr2639_vt_select_28_b = leftShiftStage2_uid27312_i_shl_i_i_i_i_i_i_93_c_compstr0_shift_x_q[28:13];

    // redist263_i_shl_i_i_i_i_i_i_93_c_compstr2639_vt_select_28_b_1(DELAY,28491)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist263_i_shl_i_i_i_i_i_i_93_c_compstr2639_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_93_c_compstr2639_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_93_c_compstr2639_vt_join(BITJOIN,9780)@199
    assign i_shl_i_i_i_i_i_i_93_c_compstr2639_vt_join_q = {redist263_i_shl_i_i_i_i_i_i_93_c_compstr2639_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_offset(CONSTANT,30654)
    assign redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_offset_q = $unsigned(8'b01001100);

    // redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_rdcnt(ADD,32103)
    assign redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_a = {1'b0, redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_wraddr_q};
    assign redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_b = {1'b0, redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_o <= $unsigned(redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_a) + $unsigned(redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_b);
        end
    end
    assign redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_q = redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_o[8:0];

    // redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_inputreg0(DELAY,32098)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl);
        end
    end

    // redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_wraddr(COUNTER,32101)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_wraddr_i <= $unsigned(redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_wraddr_q = redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_wraddr_i[7:0];

    // redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem(DUALMEM,32100)
    assign redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_ia = $unsigned(redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_inputreg0_q);
    assign redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_aa = redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_wraddr_q;
    assign redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_ab = redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_aa),
        .data_a(redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_ab),
        .q_b(redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_q = redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_iq[15:0];

    // redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_outputreg0(DELAY,32099)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_outputreg0_q <= $unsigned(redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_mem_q);
        end
    end

    // redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_rdcnt(ADD,30655)
    assign redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_a = {1'b0, redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_wraddr_q};
    assign redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_b = {1'b0, redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_o <= $unsigned(redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_a) + $unsigned(redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_b);
        end
    end
    assign redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_q = redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_o[8:0];

    // redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_inputreg0(DELAY,30650)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl);
        end
    end

    // redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_wraddr(COUNTER,30653)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_wraddr_i <= $unsigned(redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_wraddr_q = redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_wraddr_i[7:0];

    // redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem(DUALMEM,30652)
    assign redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_ia = $unsigned(redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_inputreg0_q);
    assign redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_aa = redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_wraddr_q;
    assign redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_ab = redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_aa),
        .data_a(redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_ab),
        .q_b(redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_q = redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_iq[15:0];

    // redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_outputreg0(DELAY,30651)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_outputreg0_q <= $unsigned(redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_mem_q);
        end
    end

    // redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_rdcnt(ADD,30661)
    assign redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_a = {1'b0, redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_wraddr_q};
    assign redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_b = {1'b0, redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_o <= $unsigned(redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_a) + $unsigned(redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_b);
        end
    end
    assign redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_q = redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_o[8:0];

    // redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_inputreg0(DELAY,30656)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl);
        end
    end

    // redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_wraddr(COUNTER,30659)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_wraddr_i <= $unsigned(redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_wraddr_q = redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_wraddr_i[7:0];

    // redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem(DUALMEM,30658)
    assign redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_ia = $unsigned(redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_inputreg0_q);
    assign redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_aa = redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_wraddr_q;
    assign redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_ab = redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_aa),
        .data_a(redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_ab),
        .q_b(redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_q = redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_iq[15:0];

    // redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_outputreg0(DELAY,30657)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_outputreg0_q <= $unsigned(redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_mem_q);
        end
    end

    // redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_rdcnt(ADD,32097)
    assign redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_a = {1'b0, redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_wraddr_q};
    assign redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_b = {1'b0, redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_o <= $unsigned(redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_a) + $unsigned(redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_b);
        end
    end
    assign redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_q = redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_o[8:0];

    // redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_inputreg0(DELAY,32092)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl);
        end
    end

    // redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_wraddr(COUNTER,32095)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_wraddr_i <= $unsigned(redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_wraddr_q = redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_wraddr_i[7:0];

    // redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem(DUALMEM,32094)
    assign redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_ia = $unsigned(redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_inputreg0_q);
    assign redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_aa = redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_wraddr_q;
    assign redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_ab = redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_aa),
        .data_a(redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_ab),
        .q_b(redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_q = redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_iq[15:0];

    // redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_outputreg0(DELAY,32093)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_outputreg0_q <= $unsigned(redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28053)@193 + 5
    // out q@199
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640(ADD,8641)@199
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod506_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_b = $unsigned({{5{i_shl_i_i_i_i_i_i_93_c_compstr2639_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_93_c_compstr2639_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_o[33:0];

    // rightShiftStage0_uid20735_dupName_373_i_unnamed_c_compstr0_shift_x(MUX,20734)@199
    assign rightShiftStage0_uid20735_dupName_373_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20735_dupName_373_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_q or rightShiftStage0Idx1_uid20733_dupName_373_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20735_dupName_373_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20735_dupName_373_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_q;
            1'b1 : rightShiftStage0_uid20735_dupName_373_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20733_dupName_373_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20735_dupName_373_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20740_dupName_373_i_unnamed_c_compstr0_shift_x(MUX,20739)@199
    assign rightShiftStage1_uid20740_dupName_373_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20740_dupName_373_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20735_dupName_373_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20738_dupName_373_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20740_dupName_373_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20740_dupName_373_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20735_dupName_373_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20740_dupName_373_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20738_dupName_373_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20740_dupName_373_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20745_dupName_373_i_unnamed_c_compstr0_shift_x(MUX,20744)@199
    assign rightShiftStage2_uid20745_dupName_373_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20745_dupName_373_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20740_dupName_373_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20743_dupName_373_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20745_dupName_373_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20745_dupName_373_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20740_dupName_373_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20745_dupName_373_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20743_dupName_373_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20745_dupName_373_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2641_vt_select_20(BITSELECT,11225)@199
    assign i_unnamed_c_compstr2641_vt_select_20_b = rightShiftStage2_uid20745_dupName_373_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2641_vt_join(BITJOIN,11224)@199
    assign i_unnamed_c_compstr2641_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2641_vt_select_20_b};

    // i_conv_i_i_i_i_i_93_c_compstr2642_sel_x(BITSELECT,3832)@199
    assign i_conv_i_i_i_i_i_93_c_compstr2642_sel_x_b = i_unnamed_c_compstr2641_vt_join_q[15:0];

    // redist1033_i_conv_i_i_i_i_i_93_c_compstr2642_sel_x_b_1(DELAY,29261)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1033_i_conv_i_i_i_i_i_93_c_compstr2642_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_93_c_compstr2642_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20754_dupName_374_i_unnamed_c_compstr0_shift_x(BITSELECT,20753)@199
    assign rightShiftStage1Idx1Rng8_uid20754_dupName_374_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20753_dupName_374_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20756_dupName_374_i_unnamed_c_compstr0_shift_x(BITJOIN,20755)@199
    assign rightShiftStage1Idx1_uid20756_dupName_374_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20754_dupName_374_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20749_dupName_374_i_unnamed_c_compstr0_shift_x(BITSELECT,20748)@199
    assign rightShiftStage0Idx1Rng4_uid20749_dupName_374_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_q[33:4];

    // rightShiftStage0Idx1_uid20751_dupName_374_i_unnamed_c_compstr0_shift_x(BITJOIN,20750)@199
    assign rightShiftStage0Idx1_uid20751_dupName_374_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20749_dupName_374_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20753_dupName_374_i_unnamed_c_compstr0_shift_x(MUX,20752)@199
    assign rightShiftStage0_uid20753_dupName_374_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20753_dupName_374_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_q or rightShiftStage0Idx1_uid20751_dupName_374_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20753_dupName_374_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20753_dupName_374_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compstr2640_q;
            1'b1 : rightShiftStage0_uid20753_dupName_374_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20751_dupName_374_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20753_dupName_374_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20758_dupName_374_i_unnamed_c_compstr0_shift_x(MUX,20757)@199
    assign rightShiftStage1_uid20758_dupName_374_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20758_dupName_374_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20753_dupName_374_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20756_dupName_374_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20758_dupName_374_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20758_dupName_374_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20753_dupName_374_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20758_dupName_374_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20756_dupName_374_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20758_dupName_374_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2643_vt_select_21(BITSELECT,11228)@199
    assign i_unnamed_c_compstr2643_vt_select_21_b = rightShiftStage1_uid20758_dupName_374_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2643_vt_join(BITJOIN,11227)@199
    assign i_unnamed_c_compstr2643_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2643_vt_select_21_b};

    // i_unnamed_c_compstr2644_sel_x(BITSELECT,6165)@199
    assign i_unnamed_c_compstr2644_sel_x_b = i_unnamed_c_compstr2643_vt_join_q[15:0];

    // i_unnamed_c_compstr2645_BitSelect_for_a(BITSELECT,27715)@199
    assign i_unnamed_c_compstr2645_BitSelect_for_a_b = i_unnamed_c_compstr2644_sel_x_b[0:0];

    // i_unnamed_c_compstr2645_join(BITJOIN,27716)@199
    assign i_unnamed_c_compstr2645_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2645_BitSelect_for_a_b};

    // i_unnamed_c_compstr2645_vt_select_0(BITSELECT,11233)@199
    assign i_unnamed_c_compstr2645_vt_select_0_b = i_unnamed_c_compstr2645_join_q[0:0];

    // redist127_i_unnamed_c_compstr2645_vt_select_0_b_1(DELAY,28355)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist127_i_unnamed_c_compstr2645_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2645_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2645_vt_join(BITJOIN,11232)@200
    assign i_unnamed_c_compstr2645_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist127_i_unnamed_c_compstr2645_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_93_c_compstr2646(ADD,7099)@200
    assign i_add_i_i_i_i_i_i_93_c_compstr2646_a = {1'b0, i_unnamed_c_compstr2645_vt_join_q};
    assign i_add_i_i_i_i_i_i_93_c_compstr2646_b = {1'b0, redist1033_i_conv_i_i_i_i_i_93_c_compstr2642_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_93_c_compstr2646_o = $unsigned(i_add_i_i_i_i_i_i_93_c_compstr2646_a) + $unsigned(i_add_i_i_i_i_i_i_93_c_compstr2646_b);
    assign i_add_i_i_i_i_i_i_93_c_compstr2646_q = i_add_i_i_i_i_i_i_93_c_compstr2646_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_93_c_compstr2646_sel_x(BITSELECT,2293)@200
    assign bgTrunc_i_add_i_i_i_i_i_i_93_c_compstr2646_sel_x_b = i_add_i_i_i_i_i_i_93_c_compstr2646_q[15:0];

    // i_conv_i_i_i_i_i_i279_94_c_compstr2666_sel_x(BITSELECT,3961)@200
    assign i_conv_i_i_i_i_i_i279_94_c_compstr2666_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_93_c_compstr2646_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_94_c_compstr2666_vt_select_15(BITSELECT,8361)@200
    assign i_conv_i_i_i_i_i_i279_94_c_compstr2666_vt_select_15_b = i_conv_i_i_i_i_i_i279_94_c_compstr2666_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_94_c_compstr2666_vt_join(BITJOIN,8360)@200
    assign i_conv_i_i_i_i_i_i279_94_c_compstr2666_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_94_c_compstr2666_vt_select_15_b};

    // leftShiftStage0_uid27320_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x(MUX,27319)@200
    assign leftShiftStage0_uid27320_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27320_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_94_c_compstr2666_vt_join_q or leftShiftStage0Idx1_uid27318_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27320_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27320_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_94_c_compstr2666_vt_join_q;
            1'b1 : leftShiftStage0_uid27320_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27318_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27320_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27325_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x(MUX,27324)@200
    assign leftShiftStage1_uid27325_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27325_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_s or leftShiftStage0_uid27320_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27323_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27325_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27325_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q = leftShiftStage0_uid27320_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27325_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27323_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27325_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27330_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x(MUX,27329)@200
    assign leftShiftStage2_uid27330_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27330_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_s or leftShiftStage1_uid27325_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27328_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27330_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27330_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q = leftShiftStage1_uid27325_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27330_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27328_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27330_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_94_c_compstr2667_vt_select_28(BITSELECT,9784)@200
    assign i_shl_i_i_i_i_i_i_94_c_compstr2667_vt_select_28_b = leftShiftStage2_uid27330_i_shl_i_i_i_i_i_i_94_c_compstr0_shift_x_q[28:13];

    // redist262_i_shl_i_i_i_i_i_i_94_c_compstr2667_vt_select_28_b_1(DELAY,28490)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist262_i_shl_i_i_i_i_i_i_94_c_compstr2667_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_94_c_compstr2667_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_94_c_compstr2667_vt_join(BITJOIN,9783)@201
    assign i_shl_i_i_i_i_i_i_94_c_compstr2667_vt_join_q = {redist262_i_shl_i_i_i_i_i_i_94_c_compstr2667_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_offset(CONSTANT,30666)
    assign redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_offset_q = $unsigned(8'b01001010);

    // redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_rdcnt(ADD,32115)
    assign redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_a = {1'b0, redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_wraddr_q};
    assign redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_b = {1'b0, redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_o <= $unsigned(redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_a) + $unsigned(redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_b);
        end
    end
    assign redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_q = redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_o[8:0];

    // redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_inputreg0(DELAY,32110)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl);
        end
    end

    // redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_wraddr(COUNTER,32113)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_wraddr_i <= $unsigned(redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_wraddr_q = redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_wraddr_i[7:0];

    // redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem(DUALMEM,32112)
    assign redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_ia = $unsigned(redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_inputreg0_q);
    assign redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_aa = redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_wraddr_q;
    assign redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_ab = redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_aa),
        .data_a(redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_ab),
        .q_b(redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_q = redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_iq[15:0];

    // redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_outputreg0(DELAY,32111)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_outputreg0_q <= $unsigned(redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_mem_q);
        end
    end

    // redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_rdcnt(ADD,30667)
    assign redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_a = {1'b0, redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_wraddr_q};
    assign redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_b = {1'b0, redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_o <= $unsigned(redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_a) + $unsigned(redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_b);
        end
    end
    assign redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_q = redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_o[8:0];

    // redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_inputreg0(DELAY,30662)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl);
        end
    end

    // redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_wraddr(COUNTER,30665)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_wraddr_i <= $unsigned(redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_wraddr_q = redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_wraddr_i[7:0];

    // redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem(DUALMEM,30664)
    assign redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_ia = $unsigned(redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_inputreg0_q);
    assign redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_aa = redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_wraddr_q;
    assign redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_ab = redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_aa),
        .data_a(redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_ab),
        .q_b(redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_q = redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_iq[15:0];

    // redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_outputreg0(DELAY,30663)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_outputreg0_q <= $unsigned(redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_mem_q);
        end
    end

    // redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_rdcnt(ADD,30673)
    assign redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_a = {1'b0, redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_wraddr_q};
    assign redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_b = {1'b0, redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_o <= $unsigned(redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_a) + $unsigned(redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_b);
        end
    end
    assign redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_q = redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_o[8:0];

    // redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_inputreg0(DELAY,30668)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl);
        end
    end

    // redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_wraddr(COUNTER,30671)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_wraddr_i <= $unsigned(redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_wraddr_q = redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_wraddr_i[7:0];

    // redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem(DUALMEM,30670)
    assign redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_ia = $unsigned(redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_inputreg0_q);
    assign redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_aa = redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_wraddr_q;
    assign redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_ab = redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_aa),
        .data_a(redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_ab),
        .q_b(redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_q = redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_iq[15:0];

    // redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_outputreg0(DELAY,30669)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_outputreg0_q <= $unsigned(redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_mem_q);
        end
    end

    // redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_rdcnt(ADD,32109)
    assign redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_a = {1'b0, redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_wraddr_q};
    assign redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_b = {1'b0, redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_o <= $unsigned(redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_a) + $unsigned(redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_b);
        end
    end
    assign redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_q = redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_o[8:0];

    // redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_inputreg0(DELAY,32104)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl);
        end
    end

    // redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_wraddr(COUNTER,32107)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_wraddr_i <= $unsigned(redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_wraddr_q = redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_wraddr_i[7:0];

    // redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem(DUALMEM,32106)
    assign redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_ia = $unsigned(redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_inputreg0_q);
    assign redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_aa = redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_wraddr_q;
    assign redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_ab = redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_aa),
        .data_a(redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_ab),
        .q_b(redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_q = redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_iq[15:0];

    // redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_outputreg0(DELAY,32105)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_outputreg0_q <= $unsigned(redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28054)@195 + 5
    // out q@201
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668(ADD,8642)@201
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod511_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_b = $unsigned({{5{i_shl_i_i_i_i_i_i_94_c_compstr2667_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_94_c_compstr2667_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_o[33:0];

    // rightShiftStage0_uid20797_dupName_377_i_unnamed_c_compstr0_shift_x(MUX,20796)@201
    assign rightShiftStage0_uid20797_dupName_377_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20797_dupName_377_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_q or rightShiftStage0Idx1_uid20795_dupName_377_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20797_dupName_377_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20797_dupName_377_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_q;
            1'b1 : rightShiftStage0_uid20797_dupName_377_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20795_dupName_377_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20797_dupName_377_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20802_dupName_377_i_unnamed_c_compstr0_shift_x(MUX,20801)@201
    assign rightShiftStage1_uid20802_dupName_377_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20802_dupName_377_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20797_dupName_377_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20800_dupName_377_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20802_dupName_377_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20802_dupName_377_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20797_dupName_377_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20802_dupName_377_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20800_dupName_377_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20802_dupName_377_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20807_dupName_377_i_unnamed_c_compstr0_shift_x(MUX,20806)@201
    assign rightShiftStage2_uid20807_dupName_377_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20807_dupName_377_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20802_dupName_377_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20805_dupName_377_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20807_dupName_377_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20807_dupName_377_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20802_dupName_377_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20807_dupName_377_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20805_dupName_377_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20807_dupName_377_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2669_vt_select_20(BITSELECT,11252)@201
    assign i_unnamed_c_compstr2669_vt_select_20_b = rightShiftStage2_uid20807_dupName_377_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2669_vt_join(BITJOIN,11251)@201
    assign i_unnamed_c_compstr2669_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2669_vt_select_20_b};

    // i_conv_i_i_i_i_i_94_c_compstr2670_sel_x(BITSELECT,3833)@201
    assign i_conv_i_i_i_i_i_94_c_compstr2670_sel_x_b = i_unnamed_c_compstr2669_vt_join_q[15:0];

    // redist1032_i_conv_i_i_i_i_i_94_c_compstr2670_sel_x_b_1(DELAY,29260)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1032_i_conv_i_i_i_i_i_94_c_compstr2670_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_94_c_compstr2670_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20816_dupName_378_i_unnamed_c_compstr0_shift_x(BITSELECT,20815)@201
    assign rightShiftStage1Idx1Rng8_uid20816_dupName_378_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20815_dupName_378_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20818_dupName_378_i_unnamed_c_compstr0_shift_x(BITJOIN,20817)@201
    assign rightShiftStage1Idx1_uid20818_dupName_378_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20816_dupName_378_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20811_dupName_378_i_unnamed_c_compstr0_shift_x(BITSELECT,20810)@201
    assign rightShiftStage0Idx1Rng4_uid20811_dupName_378_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_q[33:4];

    // rightShiftStage0Idx1_uid20813_dupName_378_i_unnamed_c_compstr0_shift_x(BITJOIN,20812)@201
    assign rightShiftStage0Idx1_uid20813_dupName_378_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20811_dupName_378_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20815_dupName_378_i_unnamed_c_compstr0_shift_x(MUX,20814)@201
    assign rightShiftStage0_uid20815_dupName_378_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20815_dupName_378_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_q or rightShiftStage0Idx1_uid20813_dupName_378_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20815_dupName_378_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20815_dupName_378_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compstr2668_q;
            1'b1 : rightShiftStage0_uid20815_dupName_378_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20813_dupName_378_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20815_dupName_378_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20820_dupName_378_i_unnamed_c_compstr0_shift_x(MUX,20819)@201
    assign rightShiftStage1_uid20820_dupName_378_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20820_dupName_378_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20815_dupName_378_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20818_dupName_378_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20820_dupName_378_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20820_dupName_378_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20815_dupName_378_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20820_dupName_378_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20818_dupName_378_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20820_dupName_378_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2671_vt_select_21(BITSELECT,11255)@201
    assign i_unnamed_c_compstr2671_vt_select_21_b = rightShiftStage1_uid20820_dupName_378_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2671_vt_join(BITJOIN,11254)@201
    assign i_unnamed_c_compstr2671_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2671_vt_select_21_b};

    // i_unnamed_c_compstr2672_sel_x(BITSELECT,6167)@201
    assign i_unnamed_c_compstr2672_sel_x_b = i_unnamed_c_compstr2671_vt_join_q[15:0];

    // i_unnamed_c_compstr2673_BitSelect_for_a(BITSELECT,27721)@201
    assign i_unnamed_c_compstr2673_BitSelect_for_a_b = i_unnamed_c_compstr2672_sel_x_b[0:0];

    // i_unnamed_c_compstr2673_join(BITJOIN,27722)@201
    assign i_unnamed_c_compstr2673_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2673_BitSelect_for_a_b};

    // i_unnamed_c_compstr2673_vt_select_0(BITSELECT,11260)@201
    assign i_unnamed_c_compstr2673_vt_select_0_b = i_unnamed_c_compstr2673_join_q[0:0];

    // redist124_i_unnamed_c_compstr2673_vt_select_0_b_1(DELAY,28352)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist124_i_unnamed_c_compstr2673_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2673_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2673_vt_join(BITJOIN,11259)@202
    assign i_unnamed_c_compstr2673_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist124_i_unnamed_c_compstr2673_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_94_c_compstr2674(ADD,7100)@202
    assign i_add_i_i_i_i_i_i_94_c_compstr2674_a = {1'b0, i_unnamed_c_compstr2673_vt_join_q};
    assign i_add_i_i_i_i_i_i_94_c_compstr2674_b = {1'b0, redist1032_i_conv_i_i_i_i_i_94_c_compstr2670_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_94_c_compstr2674_o = $unsigned(i_add_i_i_i_i_i_i_94_c_compstr2674_a) + $unsigned(i_add_i_i_i_i_i_i_94_c_compstr2674_b);
    assign i_add_i_i_i_i_i_i_94_c_compstr2674_q = i_add_i_i_i_i_i_i_94_c_compstr2674_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_94_c_compstr2674_sel_x(BITSELECT,2294)@202
    assign bgTrunc_i_add_i_i_i_i_i_i_94_c_compstr2674_sel_x_b = i_add_i_i_i_i_i_i_94_c_compstr2674_q[15:0];

    // i_conv_i_i_i_i_i_i279_95_c_compstr2694_sel_x(BITSELECT,3962)@202
    assign i_conv_i_i_i_i_i_i279_95_c_compstr2694_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_94_c_compstr2674_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_95_c_compstr2694_vt_select_15(BITSELECT,8365)@202
    assign i_conv_i_i_i_i_i_i279_95_c_compstr2694_vt_select_15_b = i_conv_i_i_i_i_i_i279_95_c_compstr2694_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_95_c_compstr2694_vt_join(BITJOIN,8364)@202
    assign i_conv_i_i_i_i_i_i279_95_c_compstr2694_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_95_c_compstr2694_vt_select_15_b};

    // leftShiftStage0_uid27338_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x(MUX,27337)@202
    assign leftShiftStage0_uid27338_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27338_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_95_c_compstr2694_vt_join_q or leftShiftStage0Idx1_uid27336_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27338_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27338_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_95_c_compstr2694_vt_join_q;
            1'b1 : leftShiftStage0_uid27338_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27336_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27338_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27343_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x(MUX,27342)@202
    assign leftShiftStage1_uid27343_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27343_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_s or leftShiftStage0_uid27338_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27341_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27343_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27343_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q = leftShiftStage0_uid27338_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27343_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27341_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27343_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27348_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x(MUX,27347)@202
    assign leftShiftStage2_uid27348_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27348_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_s or leftShiftStage1_uid27343_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27346_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27348_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27348_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q = leftShiftStage1_uid27343_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27348_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27346_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27348_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_95_c_compstr2695_vt_select_28(BITSELECT,9787)@202
    assign i_shl_i_i_i_i_i_i_95_c_compstr2695_vt_select_28_b = leftShiftStage2_uid27348_i_shl_i_i_i_i_i_i_95_c_compstr0_shift_x_q[28:13];

    // redist261_i_shl_i_i_i_i_i_i_95_c_compstr2695_vt_select_28_b_1(DELAY,28489)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist261_i_shl_i_i_i_i_i_i_95_c_compstr2695_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_95_c_compstr2695_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_95_c_compstr2695_vt_join(BITJOIN,9786)@203
    assign i_shl_i_i_i_i_i_i_95_c_compstr2695_vt_join_q = {redist261_i_shl_i_i_i_i_i_i_95_c_compstr2695_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_offset(CONSTANT,30678)
    assign redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_offset_q = $unsigned(8'b01001000);

    // redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_rdcnt(ADD,32127)
    assign redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_a = {1'b0, redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_wraddr_q};
    assign redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_b = {1'b0, redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_o <= $unsigned(redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_a) + $unsigned(redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_b);
        end
    end
    assign redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_q = redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_o[8:0];

    // redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_inputreg0(DELAY,32122)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl);
        end
    end

    // redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_wraddr(COUNTER,32125)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_wraddr_i <= $unsigned(redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_wraddr_q = redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_wraddr_i[7:0];

    // redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem(DUALMEM,32124)
    assign redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_ia = $unsigned(redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_inputreg0_q);
    assign redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_aa = redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_wraddr_q;
    assign redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_ab = redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_aa),
        .data_a(redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_ab),
        .q_b(redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_q = redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_iq[15:0];

    // redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_outputreg0(DELAY,32123)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_outputreg0_q <= $unsigned(redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_mem_q);
        end
    end

    // redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_rdcnt(ADD,30679)
    assign redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_a = {1'b0, redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_wraddr_q};
    assign redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_b = {1'b0, redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_o <= $unsigned(redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_a) + $unsigned(redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_b);
        end
    end
    assign redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_q = redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_o[8:0];

    // redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_inputreg0(DELAY,30674)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl);
        end
    end

    // redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_wraddr(COUNTER,30677)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_wraddr_i <= $unsigned(redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_wraddr_q = redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_wraddr_i[7:0];

    // redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem(DUALMEM,30676)
    assign redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_ia = $unsigned(redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_inputreg0_q);
    assign redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_aa = redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_wraddr_q;
    assign redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_ab = redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_aa),
        .data_a(redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_ab),
        .q_b(redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_q = redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_iq[15:0];

    // redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_outputreg0(DELAY,30675)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_outputreg0_q <= $unsigned(redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_mem_q);
        end
    end

    // redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_rdcnt(ADD,30685)
    assign redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_a = {1'b0, redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_wraddr_q};
    assign redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_b = {1'b0, redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_o <= $unsigned(redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_a) + $unsigned(redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_b);
        end
    end
    assign redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_q = redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_o[8:0];

    // redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_inputreg0(DELAY,30680)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl);
        end
    end

    // redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_wraddr(COUNTER,30683)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_wraddr_i <= $unsigned(redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_wraddr_q = redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_wraddr_i[7:0];

    // redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem(DUALMEM,30682)
    assign redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_ia = $unsigned(redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_inputreg0_q);
    assign redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_aa = redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_wraddr_q;
    assign redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_ab = redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_aa),
        .data_a(redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_ab),
        .q_b(redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_q = redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_iq[15:0];

    // redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_outputreg0(DELAY,30681)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_outputreg0_q <= $unsigned(redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_mem_q);
        end
    end

    // redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_rdcnt(ADD,32121)
    assign redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_a = {1'b0, redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_wraddr_q};
    assign redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_b = {1'b0, redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_o <= $unsigned(redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_a) + $unsigned(redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_b);
        end
    end
    assign redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_q = redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_o[8:0];

    // redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_inputreg0(DELAY,32116)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl);
        end
    end

    // redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_wraddr(COUNTER,32119)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_wraddr_i <= $unsigned(redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_wraddr_q = redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_wraddr_i[7:0];

    // redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem(DUALMEM,32118)
    assign redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_ia = $unsigned(redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_inputreg0_q);
    assign redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_aa = redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_wraddr_q;
    assign redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_ab = redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_aa),
        .data_a(redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_ab),
        .q_b(redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_q = redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_iq[15:0];

    // redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_outputreg0(DELAY,32117)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_outputreg0_q <= $unsigned(redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28055)@197 + 5
    // out q@203
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696(ADD,8643)@203
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod516_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_b = $unsigned({{5{i_shl_i_i_i_i_i_i_95_c_compstr2695_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_95_c_compstr2695_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_o[33:0];

    // rightShiftStage0_uid20859_dupName_381_i_unnamed_c_compstr0_shift_x(MUX,20858)@203
    assign rightShiftStage0_uid20859_dupName_381_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20859_dupName_381_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_q or rightShiftStage0Idx1_uid20857_dupName_381_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20859_dupName_381_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20859_dupName_381_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_q;
            1'b1 : rightShiftStage0_uid20859_dupName_381_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20857_dupName_381_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20859_dupName_381_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20864_dupName_381_i_unnamed_c_compstr0_shift_x(MUX,20863)@203
    assign rightShiftStage1_uid20864_dupName_381_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20864_dupName_381_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20859_dupName_381_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20862_dupName_381_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20864_dupName_381_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20864_dupName_381_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20859_dupName_381_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20864_dupName_381_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20862_dupName_381_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20864_dupName_381_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20869_dupName_381_i_unnamed_c_compstr0_shift_x(MUX,20868)@203
    assign rightShiftStage2_uid20869_dupName_381_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20869_dupName_381_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20864_dupName_381_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20867_dupName_381_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20869_dupName_381_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20869_dupName_381_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20864_dupName_381_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20869_dupName_381_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20867_dupName_381_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20869_dupName_381_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2697_vt_select_20(BITSELECT,11274)@203
    assign i_unnamed_c_compstr2697_vt_select_20_b = rightShiftStage2_uid20869_dupName_381_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2697_vt_join(BITJOIN,11273)@203
    assign i_unnamed_c_compstr2697_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2697_vt_select_20_b};

    // i_conv_i_i_i_i_i_95_c_compstr2698_sel_x(BITSELECT,3834)@203
    assign i_conv_i_i_i_i_i_95_c_compstr2698_sel_x_b = i_unnamed_c_compstr2697_vt_join_q[15:0];

    // redist1031_i_conv_i_i_i_i_i_95_c_compstr2698_sel_x_b_1(DELAY,29259)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1031_i_conv_i_i_i_i_i_95_c_compstr2698_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_95_c_compstr2698_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20878_dupName_382_i_unnamed_c_compstr0_shift_x(BITSELECT,20877)@203
    assign rightShiftStage1Idx1Rng8_uid20878_dupName_382_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20877_dupName_382_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20880_dupName_382_i_unnamed_c_compstr0_shift_x(BITJOIN,20879)@203
    assign rightShiftStage1Idx1_uid20880_dupName_382_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20878_dupName_382_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20873_dupName_382_i_unnamed_c_compstr0_shift_x(BITSELECT,20872)@203
    assign rightShiftStage0Idx1Rng4_uid20873_dupName_382_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_q[33:4];

    // rightShiftStage0Idx1_uid20875_dupName_382_i_unnamed_c_compstr0_shift_x(BITJOIN,20874)@203
    assign rightShiftStage0Idx1_uid20875_dupName_382_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20873_dupName_382_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20877_dupName_382_i_unnamed_c_compstr0_shift_x(MUX,20876)@203
    assign rightShiftStage0_uid20877_dupName_382_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20877_dupName_382_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_q or rightShiftStage0Idx1_uid20875_dupName_382_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20877_dupName_382_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20877_dupName_382_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compstr2696_q;
            1'b1 : rightShiftStage0_uid20877_dupName_382_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20875_dupName_382_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20877_dupName_382_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20882_dupName_382_i_unnamed_c_compstr0_shift_x(MUX,20881)@203
    assign rightShiftStage1_uid20882_dupName_382_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20882_dupName_382_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20877_dupName_382_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20880_dupName_382_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20882_dupName_382_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20882_dupName_382_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20877_dupName_382_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20882_dupName_382_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20880_dupName_382_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20882_dupName_382_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2699_vt_select_21(BITSELECT,11277)@203
    assign i_unnamed_c_compstr2699_vt_select_21_b = rightShiftStage1_uid20882_dupName_382_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2699_vt_join(BITJOIN,11276)@203
    assign i_unnamed_c_compstr2699_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2699_vt_select_21_b};

    // i_unnamed_c_compstr2700_sel_x(BITSELECT,6169)@203
    assign i_unnamed_c_compstr2700_sel_x_b = i_unnamed_c_compstr2699_vt_join_q[15:0];

    // i_unnamed_c_compstr2701_BitSelect_for_a(BITSELECT,27727)@203
    assign i_unnamed_c_compstr2701_BitSelect_for_a_b = i_unnamed_c_compstr2700_sel_x_b[0:0];

    // i_unnamed_c_compstr2701_join(BITJOIN,27728)@203
    assign i_unnamed_c_compstr2701_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2701_BitSelect_for_a_b};

    // i_unnamed_c_compstr2701_vt_select_0(BITSELECT,11284)@203
    assign i_unnamed_c_compstr2701_vt_select_0_b = i_unnamed_c_compstr2701_join_q[0:0];

    // redist122_i_unnamed_c_compstr2701_vt_select_0_b_1(DELAY,28350)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist122_i_unnamed_c_compstr2701_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2701_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2701_vt_join(BITJOIN,11283)@204
    assign i_unnamed_c_compstr2701_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist122_i_unnamed_c_compstr2701_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_95_c_compstr2702(ADD,7101)@204
    assign i_add_i_i_i_i_i_i_95_c_compstr2702_a = {1'b0, i_unnamed_c_compstr2701_vt_join_q};
    assign i_add_i_i_i_i_i_i_95_c_compstr2702_b = {1'b0, redist1031_i_conv_i_i_i_i_i_95_c_compstr2698_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_95_c_compstr2702_o = $unsigned(i_add_i_i_i_i_i_i_95_c_compstr2702_a) + $unsigned(i_add_i_i_i_i_i_i_95_c_compstr2702_b);
    assign i_add_i_i_i_i_i_i_95_c_compstr2702_q = i_add_i_i_i_i_i_i_95_c_compstr2702_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_95_c_compstr2702_sel_x(BITSELECT,2295)@204
    assign bgTrunc_i_add_i_i_i_i_i_i_95_c_compstr2702_sel_x_b = i_add_i_i_i_i_i_i_95_c_compstr2702_q[15:0];

    // i_conv_i_i_i_i_i_i279_96_c_compstr2722_sel_x(BITSELECT,3963)@204
    assign i_conv_i_i_i_i_i_i279_96_c_compstr2722_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_95_c_compstr2702_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_96_c_compstr2722_vt_select_15(BITSELECT,8369)@204
    assign i_conv_i_i_i_i_i_i279_96_c_compstr2722_vt_select_15_b = i_conv_i_i_i_i_i_i279_96_c_compstr2722_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_96_c_compstr2722_vt_join(BITJOIN,8368)@204
    assign i_conv_i_i_i_i_i_i279_96_c_compstr2722_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_96_c_compstr2722_vt_select_15_b};

    // leftShiftStage0_uid27356_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x(MUX,27355)@204
    assign leftShiftStage0_uid27356_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27356_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_96_c_compstr2722_vt_join_q or leftShiftStage0Idx1_uid27354_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27356_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27356_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_96_c_compstr2722_vt_join_q;
            1'b1 : leftShiftStage0_uid27356_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27354_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27356_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27361_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x(MUX,27360)@204
    assign leftShiftStage1_uid27361_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27361_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_s or leftShiftStage0_uid27356_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27359_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27361_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27361_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q = leftShiftStage0_uid27356_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27361_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27359_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27361_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27366_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x(MUX,27365)@204
    assign leftShiftStage2_uid27366_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27366_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_s or leftShiftStage1_uid27361_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27364_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27366_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27366_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q = leftShiftStage1_uid27361_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27366_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27364_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27366_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_96_c_compstr2723_vt_select_28(BITSELECT,9790)@204
    assign i_shl_i_i_i_i_i_i_96_c_compstr2723_vt_select_28_b = leftShiftStage2_uid27366_i_shl_i_i_i_i_i_i_96_c_compstr0_shift_x_q[28:13];

    // redist260_i_shl_i_i_i_i_i_i_96_c_compstr2723_vt_select_28_b_1(DELAY,28488)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist260_i_shl_i_i_i_i_i_i_96_c_compstr2723_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_96_c_compstr2723_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_96_c_compstr2723_vt_join(BITJOIN,9789)@205
    assign i_shl_i_i_i_i_i_i_96_c_compstr2723_vt_join_q = {redist260_i_shl_i_i_i_i_i_i_96_c_compstr2723_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_offset(CONSTANT,30690)
    assign redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_offset_q = $unsigned(8'b01000110);

    // redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_rdcnt(ADD,32139)
    assign redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_a = {1'b0, redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_wraddr_q};
    assign redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_b = {1'b0, redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_o <= $unsigned(redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_a) + $unsigned(redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_b);
        end
    end
    assign redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_q = redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_o[8:0];

    // redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_inputreg0(DELAY,32134)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl);
        end
    end

    // redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_wraddr(COUNTER,32137)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_wraddr_i <= $unsigned(redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_wraddr_q = redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_wraddr_i[7:0];

    // redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem(DUALMEM,32136)
    assign redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_ia = $unsigned(redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_inputreg0_q);
    assign redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_aa = redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_wraddr_q;
    assign redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_ab = redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_aa),
        .data_a(redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_ab),
        .q_b(redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_q = redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_iq[15:0];

    // redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_outputreg0(DELAY,32135)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_outputreg0_q <= $unsigned(redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_mem_q);
        end
    end

    // redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_rdcnt(ADD,30691)
    assign redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_a = {1'b0, redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_wraddr_q};
    assign redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_b = {1'b0, redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_o <= $unsigned(redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_a) + $unsigned(redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_b);
        end
    end
    assign redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_q = redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_o[8:0];

    // redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_inputreg0(DELAY,30686)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl);
        end
    end

    // redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_wraddr(COUNTER,30689)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_wraddr_i <= $unsigned(redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_wraddr_q = redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_wraddr_i[7:0];

    // redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem(DUALMEM,30688)
    assign redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_ia = $unsigned(redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_inputreg0_q);
    assign redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_aa = redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_wraddr_q;
    assign redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_ab = redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_aa),
        .data_a(redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_ab),
        .q_b(redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_q = redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_iq[15:0];

    // redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_outputreg0(DELAY,30687)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_outputreg0_q <= $unsigned(redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_mem_q);
        end
    end

    // redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_rdcnt(ADD,30697)
    assign redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_a = {1'b0, redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_wraddr_q};
    assign redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_b = {1'b0, redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_o <= $unsigned(redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_a) + $unsigned(redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_b);
        end
    end
    assign redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_q = redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_o[8:0];

    // redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_inputreg0(DELAY,30692)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl);
        end
    end

    // redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_wraddr(COUNTER,30695)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_wraddr_i <= $unsigned(redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_wraddr_q = redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_wraddr_i[7:0];

    // redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem(DUALMEM,30694)
    assign redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_ia = $unsigned(redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_inputreg0_q);
    assign redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_aa = redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_wraddr_q;
    assign redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_ab = redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_aa),
        .data_a(redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_ab),
        .q_b(redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_q = redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_iq[15:0];

    // redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_outputreg0(DELAY,30693)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_outputreg0_q <= $unsigned(redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_mem_q);
        end
    end

    // redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_rdcnt(ADD,32133)
    assign redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_a = {1'b0, redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_wraddr_q};
    assign redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_b = {1'b0, redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_o <= $unsigned(redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_a) + $unsigned(redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_b);
        end
    end
    assign redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_q = redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_o[8:0];

    // redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_inputreg0(DELAY,32128)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl);
        end
    end

    // redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_wraddr(COUNTER,32131)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_wraddr_i <= $unsigned(redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_wraddr_q = redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_wraddr_i[7:0];

    // redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem(DUALMEM,32130)
    assign redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_ia = $unsigned(redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_inputreg0_q);
    assign redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_aa = redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_wraddr_q;
    assign redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_ab = redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_aa),
        .data_a(redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_ab),
        .q_b(redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_q = redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_iq[15:0];

    // redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_outputreg0(DELAY,32129)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_outputreg0_q <= $unsigned(redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28057)@199 + 5
    // out q@205
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724(ADD,8644)@205
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod521_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_b = $unsigned({{5{i_shl_i_i_i_i_i_i_96_c_compstr2723_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_96_c_compstr2723_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_o[33:0];

    // rightShiftStage0_uid20921_dupName_385_i_unnamed_c_compstr0_shift_x(MUX,20920)@205
    assign rightShiftStage0_uid20921_dupName_385_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20921_dupName_385_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_q or rightShiftStage0Idx1_uid20919_dupName_385_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20921_dupName_385_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20921_dupName_385_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_q;
            1'b1 : rightShiftStage0_uid20921_dupName_385_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20919_dupName_385_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20921_dupName_385_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20926_dupName_385_i_unnamed_c_compstr0_shift_x(MUX,20925)@205
    assign rightShiftStage1_uid20926_dupName_385_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20926_dupName_385_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20921_dupName_385_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20924_dupName_385_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20926_dupName_385_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20926_dupName_385_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20921_dupName_385_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20926_dupName_385_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20924_dupName_385_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20926_dupName_385_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20931_dupName_385_i_unnamed_c_compstr0_shift_x(MUX,20930)@205
    assign rightShiftStage2_uid20931_dupName_385_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20931_dupName_385_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20926_dupName_385_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20929_dupName_385_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20931_dupName_385_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20931_dupName_385_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20926_dupName_385_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20931_dupName_385_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20929_dupName_385_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20931_dupName_385_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2725_vt_select_20(BITSELECT,11298)@205
    assign i_unnamed_c_compstr2725_vt_select_20_b = rightShiftStage2_uid20931_dupName_385_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2725_vt_join(BITJOIN,11297)@205
    assign i_unnamed_c_compstr2725_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2725_vt_select_20_b};

    // i_conv_i_i_i_i_i_96_c_compstr2726_sel_x(BITSELECT,3835)@205
    assign i_conv_i_i_i_i_i_96_c_compstr2726_sel_x_b = i_unnamed_c_compstr2725_vt_join_q[15:0];

    // redist1030_i_conv_i_i_i_i_i_96_c_compstr2726_sel_x_b_1(DELAY,29258)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1030_i_conv_i_i_i_i_i_96_c_compstr2726_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_96_c_compstr2726_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20940_dupName_386_i_unnamed_c_compstr0_shift_x(BITSELECT,20939)@205
    assign rightShiftStage1Idx1Rng8_uid20940_dupName_386_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20939_dupName_386_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20942_dupName_386_i_unnamed_c_compstr0_shift_x(BITJOIN,20941)@205
    assign rightShiftStage1Idx1_uid20942_dupName_386_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20940_dupName_386_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20935_dupName_386_i_unnamed_c_compstr0_shift_x(BITSELECT,20934)@205
    assign rightShiftStage0Idx1Rng4_uid20935_dupName_386_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_q[33:4];

    // rightShiftStage0Idx1_uid20937_dupName_386_i_unnamed_c_compstr0_shift_x(BITJOIN,20936)@205
    assign rightShiftStage0Idx1_uid20937_dupName_386_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20935_dupName_386_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20939_dupName_386_i_unnamed_c_compstr0_shift_x(MUX,20938)@205
    assign rightShiftStage0_uid20939_dupName_386_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20939_dupName_386_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_q or rightShiftStage0Idx1_uid20937_dupName_386_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20939_dupName_386_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20939_dupName_386_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compstr2724_q;
            1'b1 : rightShiftStage0_uid20939_dupName_386_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20937_dupName_386_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20939_dupName_386_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20944_dupName_386_i_unnamed_c_compstr0_shift_x(MUX,20943)@205
    assign rightShiftStage1_uid20944_dupName_386_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20944_dupName_386_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20939_dupName_386_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20942_dupName_386_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20944_dupName_386_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20944_dupName_386_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20939_dupName_386_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20944_dupName_386_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20942_dupName_386_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20944_dupName_386_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2727_vt_select_21(BITSELECT,11301)@205
    assign i_unnamed_c_compstr2727_vt_select_21_b = rightShiftStage1_uid20944_dupName_386_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2727_vt_join(BITJOIN,11300)@205
    assign i_unnamed_c_compstr2727_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2727_vt_select_21_b};

    // i_unnamed_c_compstr2728_sel_x(BITSELECT,6171)@205
    assign i_unnamed_c_compstr2728_sel_x_b = i_unnamed_c_compstr2727_vt_join_q[15:0];

    // i_unnamed_c_compstr2729_BitSelect_for_a(BITSELECT,27731)@205
    assign i_unnamed_c_compstr2729_BitSelect_for_a_b = i_unnamed_c_compstr2728_sel_x_b[0:0];

    // i_unnamed_c_compstr2729_join(BITJOIN,27732)@205
    assign i_unnamed_c_compstr2729_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2729_BitSelect_for_a_b};

    // i_unnamed_c_compstr2729_vt_select_0(BITSELECT,11306)@205
    assign i_unnamed_c_compstr2729_vt_select_0_b = i_unnamed_c_compstr2729_join_q[0:0];

    // redist120_i_unnamed_c_compstr2729_vt_select_0_b_1(DELAY,28348)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist120_i_unnamed_c_compstr2729_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2729_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2729_vt_join(BITJOIN,11305)@206
    assign i_unnamed_c_compstr2729_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist120_i_unnamed_c_compstr2729_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_96_c_compstr2730(ADD,7102)@206
    assign i_add_i_i_i_i_i_i_96_c_compstr2730_a = {1'b0, i_unnamed_c_compstr2729_vt_join_q};
    assign i_add_i_i_i_i_i_i_96_c_compstr2730_b = {1'b0, redist1030_i_conv_i_i_i_i_i_96_c_compstr2726_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_96_c_compstr2730_o = $unsigned(i_add_i_i_i_i_i_i_96_c_compstr2730_a) + $unsigned(i_add_i_i_i_i_i_i_96_c_compstr2730_b);
    assign i_add_i_i_i_i_i_i_96_c_compstr2730_q = i_add_i_i_i_i_i_i_96_c_compstr2730_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_96_c_compstr2730_sel_x(BITSELECT,2296)@206
    assign bgTrunc_i_add_i_i_i_i_i_i_96_c_compstr2730_sel_x_b = i_add_i_i_i_i_i_i_96_c_compstr2730_q[15:0];

    // i_conv_i_i_i_i_i_i279_97_c_compstr2750_sel_x(BITSELECT,3964)@206
    assign i_conv_i_i_i_i_i_i279_97_c_compstr2750_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_96_c_compstr2730_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_97_c_compstr2750_vt_select_15(BITSELECT,8373)@206
    assign i_conv_i_i_i_i_i_i279_97_c_compstr2750_vt_select_15_b = i_conv_i_i_i_i_i_i279_97_c_compstr2750_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_97_c_compstr2750_vt_join(BITJOIN,8372)@206
    assign i_conv_i_i_i_i_i_i279_97_c_compstr2750_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_97_c_compstr2750_vt_select_15_b};

    // leftShiftStage0_uid27374_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x(MUX,27373)@206
    assign leftShiftStage0_uid27374_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27374_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_97_c_compstr2750_vt_join_q or leftShiftStage0Idx1_uid27372_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27374_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27374_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_97_c_compstr2750_vt_join_q;
            1'b1 : leftShiftStage0_uid27374_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27372_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27374_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27379_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x(MUX,27378)@206
    assign leftShiftStage1_uid27379_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27379_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_s or leftShiftStage0_uid27374_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27377_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27379_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27379_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q = leftShiftStage0_uid27374_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27379_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27377_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27379_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27384_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x(MUX,27383)@206
    assign leftShiftStage2_uid27384_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27384_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_s or leftShiftStage1_uid27379_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27382_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27384_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27384_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q = leftShiftStage1_uid27379_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27384_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27382_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27384_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_97_c_compstr2751_vt_select_28(BITSELECT,9793)@206
    assign i_shl_i_i_i_i_i_i_97_c_compstr2751_vt_select_28_b = leftShiftStage2_uid27384_i_shl_i_i_i_i_i_i_97_c_compstr0_shift_x_q[28:13];

    // redist259_i_shl_i_i_i_i_i_i_97_c_compstr2751_vt_select_28_b_1(DELAY,28487)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist259_i_shl_i_i_i_i_i_i_97_c_compstr2751_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_97_c_compstr2751_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_97_c_compstr2751_vt_join(BITJOIN,9792)@207
    assign i_shl_i_i_i_i_i_i_97_c_compstr2751_vt_join_q = {redist259_i_shl_i_i_i_i_i_i_97_c_compstr2751_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_offset(CONSTANT,30702)
    assign redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_offset_q = $unsigned(8'b01000100);

    // redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_rdcnt(ADD,32151)
    assign redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_a = {1'b0, redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_wraddr_q};
    assign redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_b = {1'b0, redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_o <= $unsigned(redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_a) + $unsigned(redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_b);
        end
    end
    assign redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_q = redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_o[8:0];

    // redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_inputreg0(DELAY,32146)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl);
        end
    end

    // redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_wraddr(COUNTER,32149)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_wraddr_i <= $unsigned(redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_wraddr_q = redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_wraddr_i[7:0];

    // redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem(DUALMEM,32148)
    assign redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_ia = $unsigned(redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_inputreg0_q);
    assign redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_aa = redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_wraddr_q;
    assign redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_ab = redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_aa),
        .data_a(redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_ab),
        .q_b(redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_q = redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_iq[15:0];

    // redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_outputreg0(DELAY,32147)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_outputreg0_q <= $unsigned(redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_mem_q);
        end
    end

    // redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_rdcnt(ADD,30703)
    assign redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_a = {1'b0, redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_wraddr_q};
    assign redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_b = {1'b0, redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_o <= $unsigned(redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_a) + $unsigned(redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_b);
        end
    end
    assign redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_q = redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_o[8:0];

    // redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_inputreg0(DELAY,30698)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl);
        end
    end

    // redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_wraddr(COUNTER,30701)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_wraddr_i <= $unsigned(redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_wraddr_q = redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_wraddr_i[7:0];

    // redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem(DUALMEM,30700)
    assign redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_ia = $unsigned(redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_inputreg0_q);
    assign redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_aa = redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_wraddr_q;
    assign redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_ab = redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_aa),
        .data_a(redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_ab),
        .q_b(redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_q = redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_iq[15:0];

    // redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_outputreg0(DELAY,30699)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_outputreg0_q <= $unsigned(redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_mem_q);
        end
    end

    // redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_rdcnt(ADD,30709)
    assign redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_a = {1'b0, redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_wraddr_q};
    assign redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_b = {1'b0, redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_o <= $unsigned(redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_a) + $unsigned(redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_b);
        end
    end
    assign redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_q = redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_o[8:0];

    // redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_inputreg0(DELAY,30704)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl);
        end
    end

    // redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_wraddr(COUNTER,30707)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_wraddr_i <= $unsigned(redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_wraddr_q = redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_wraddr_i[7:0];

    // redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem(DUALMEM,30706)
    assign redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_ia = $unsigned(redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_inputreg0_q);
    assign redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_aa = redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_wraddr_q;
    assign redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_ab = redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_aa),
        .data_a(redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_ab),
        .q_b(redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_q = redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_iq[15:0];

    // redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_outputreg0(DELAY,30705)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_outputreg0_q <= $unsigned(redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_mem_q);
        end
    end

    // redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_rdcnt(ADD,32145)
    assign redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_a = {1'b0, redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_wraddr_q};
    assign redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_b = {1'b0, redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_o <= $unsigned(redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_a) + $unsigned(redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_b);
        end
    end
    assign redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_q = redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_o[8:0];

    // redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_inputreg0(DELAY,32140)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl);
        end
    end

    // redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_wraddr(COUNTER,32143)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_wraddr_i <= $unsigned(redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_wraddr_q = redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_wraddr_i[7:0];

    // redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem(DUALMEM,32142)
    assign redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_ia = $unsigned(redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_inputreg0_q);
    assign redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_aa = redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_wraddr_q;
    assign redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_ab = redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_aa),
        .data_a(redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_ab),
        .q_b(redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_q = redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_iq[15:0];

    // redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_outputreg0(DELAY,32141)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_outputreg0_q <= $unsigned(redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28058)@201 + 5
    // out q@207
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752(ADD,8645)@207
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod526_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_b = $unsigned({{5{i_shl_i_i_i_i_i_i_97_c_compstr2751_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_97_c_compstr2751_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_o[33:0];

    // rightShiftStage0_uid20983_dupName_389_i_unnamed_c_compstr0_shift_x(MUX,20982)@207
    assign rightShiftStage0_uid20983_dupName_389_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20983_dupName_389_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_q or rightShiftStage0Idx1_uid20981_dupName_389_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20983_dupName_389_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20983_dupName_389_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_q;
            1'b1 : rightShiftStage0_uid20983_dupName_389_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20981_dupName_389_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20983_dupName_389_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20988_dupName_389_i_unnamed_c_compstr0_shift_x(MUX,20987)@207
    assign rightShiftStage1_uid20988_dupName_389_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20988_dupName_389_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20983_dupName_389_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20986_dupName_389_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20988_dupName_389_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20988_dupName_389_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20983_dupName_389_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20988_dupName_389_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20986_dupName_389_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20988_dupName_389_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20993_dupName_389_i_unnamed_c_compstr0_shift_x(MUX,20992)@207
    assign rightShiftStage2_uid20993_dupName_389_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20993_dupName_389_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20988_dupName_389_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20991_dupName_389_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20993_dupName_389_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20993_dupName_389_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20988_dupName_389_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20993_dupName_389_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20991_dupName_389_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20993_dupName_389_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2753_vt_select_20(BITSELECT,11323)@207
    assign i_unnamed_c_compstr2753_vt_select_20_b = rightShiftStage2_uid20993_dupName_389_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2753_vt_join(BITJOIN,11322)@207
    assign i_unnamed_c_compstr2753_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2753_vt_select_20_b};

    // i_conv_i_i_i_i_i_97_c_compstr2754_sel_x(BITSELECT,3836)@207
    assign i_conv_i_i_i_i_i_97_c_compstr2754_sel_x_b = i_unnamed_c_compstr2753_vt_join_q[15:0];

    // redist1029_i_conv_i_i_i_i_i_97_c_compstr2754_sel_x_b_1(DELAY,29257)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1029_i_conv_i_i_i_i_i_97_c_compstr2754_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_97_c_compstr2754_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21002_dupName_390_i_unnamed_c_compstr0_shift_x(BITSELECT,21001)@207
    assign rightShiftStage1Idx1Rng8_uid21002_dupName_390_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21001_dupName_390_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21004_dupName_390_i_unnamed_c_compstr0_shift_x(BITJOIN,21003)@207
    assign rightShiftStage1Idx1_uid21004_dupName_390_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21002_dupName_390_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20997_dupName_390_i_unnamed_c_compstr0_shift_x(BITSELECT,20996)@207
    assign rightShiftStage0Idx1Rng4_uid20997_dupName_390_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_q[33:4];

    // rightShiftStage0Idx1_uid20999_dupName_390_i_unnamed_c_compstr0_shift_x(BITJOIN,20998)@207
    assign rightShiftStage0Idx1_uid20999_dupName_390_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20997_dupName_390_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21001_dupName_390_i_unnamed_c_compstr0_shift_x(MUX,21000)@207
    assign rightShiftStage0_uid21001_dupName_390_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21001_dupName_390_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_q or rightShiftStage0Idx1_uid20999_dupName_390_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21001_dupName_390_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21001_dupName_390_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compstr2752_q;
            1'b1 : rightShiftStage0_uid21001_dupName_390_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20999_dupName_390_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21001_dupName_390_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21006_dupName_390_i_unnamed_c_compstr0_shift_x(MUX,21005)@207
    assign rightShiftStage1_uid21006_dupName_390_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21006_dupName_390_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21001_dupName_390_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21004_dupName_390_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21006_dupName_390_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21006_dupName_390_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21001_dupName_390_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21006_dupName_390_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21004_dupName_390_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21006_dupName_390_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2755_vt_select_21(BITSELECT,11326)@207
    assign i_unnamed_c_compstr2755_vt_select_21_b = rightShiftStage1_uid21006_dupName_390_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2755_vt_join(BITJOIN,11325)@207
    assign i_unnamed_c_compstr2755_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2755_vt_select_21_b};

    // i_unnamed_c_compstr2756_sel_x(BITSELECT,6173)@207
    assign i_unnamed_c_compstr2756_sel_x_b = i_unnamed_c_compstr2755_vt_join_q[15:0];

    // i_unnamed_c_compstr2757_BitSelect_for_a(BITSELECT,27735)@207
    assign i_unnamed_c_compstr2757_BitSelect_for_a_b = i_unnamed_c_compstr2756_sel_x_b[0:0];

    // i_unnamed_c_compstr2757_join(BITJOIN,27736)@207
    assign i_unnamed_c_compstr2757_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2757_BitSelect_for_a_b};

    // i_unnamed_c_compstr2757_vt_select_0(BITSELECT,11331)@207
    assign i_unnamed_c_compstr2757_vt_select_0_b = i_unnamed_c_compstr2757_join_q[0:0];

    // redist118_i_unnamed_c_compstr2757_vt_select_0_b_1(DELAY,28346)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist118_i_unnamed_c_compstr2757_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2757_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2757_vt_join(BITJOIN,11330)@208
    assign i_unnamed_c_compstr2757_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist118_i_unnamed_c_compstr2757_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_97_c_compstr2758(ADD,7103)@208
    assign i_add_i_i_i_i_i_i_97_c_compstr2758_a = {1'b0, i_unnamed_c_compstr2757_vt_join_q};
    assign i_add_i_i_i_i_i_i_97_c_compstr2758_b = {1'b0, redist1029_i_conv_i_i_i_i_i_97_c_compstr2754_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_97_c_compstr2758_o = $unsigned(i_add_i_i_i_i_i_i_97_c_compstr2758_a) + $unsigned(i_add_i_i_i_i_i_i_97_c_compstr2758_b);
    assign i_add_i_i_i_i_i_i_97_c_compstr2758_q = i_add_i_i_i_i_i_i_97_c_compstr2758_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_97_c_compstr2758_sel_x(BITSELECT,2297)@208
    assign bgTrunc_i_add_i_i_i_i_i_i_97_c_compstr2758_sel_x_b = i_add_i_i_i_i_i_i_97_c_compstr2758_q[15:0];

    // i_conv_i_i_i_i_i_i279_98_c_compstr2778_sel_x(BITSELECT,3965)@208
    assign i_conv_i_i_i_i_i_i279_98_c_compstr2778_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_97_c_compstr2758_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_98_c_compstr2778_vt_select_15(BITSELECT,8377)@208
    assign i_conv_i_i_i_i_i_i279_98_c_compstr2778_vt_select_15_b = i_conv_i_i_i_i_i_i279_98_c_compstr2778_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_98_c_compstr2778_vt_join(BITJOIN,8376)@208
    assign i_conv_i_i_i_i_i_i279_98_c_compstr2778_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_98_c_compstr2778_vt_select_15_b};

    // leftShiftStage0_uid27392_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x(MUX,27391)@208
    assign leftShiftStage0_uid27392_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27392_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_98_c_compstr2778_vt_join_q or leftShiftStage0Idx1_uid27390_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27392_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27392_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_98_c_compstr2778_vt_join_q;
            1'b1 : leftShiftStage0_uid27392_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27390_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27392_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27397_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x(MUX,27396)@208
    assign leftShiftStage1_uid27397_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27397_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_s or leftShiftStage0_uid27392_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27395_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27397_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27397_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q = leftShiftStage0_uid27392_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27397_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27395_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27397_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27402_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x(MUX,27401)@208
    assign leftShiftStage2_uid27402_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27402_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_s or leftShiftStage1_uid27397_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27400_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27402_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27402_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q = leftShiftStage1_uid27397_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27402_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27400_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27402_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_98_c_compstr2779_vt_select_28(BITSELECT,9796)@208
    assign i_shl_i_i_i_i_i_i_98_c_compstr2779_vt_select_28_b = leftShiftStage2_uid27402_i_shl_i_i_i_i_i_i_98_c_compstr0_shift_x_q[28:13];

    // redist258_i_shl_i_i_i_i_i_i_98_c_compstr2779_vt_select_28_b_1(DELAY,28486)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist258_i_shl_i_i_i_i_i_i_98_c_compstr2779_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_98_c_compstr2779_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_98_c_compstr2779_vt_join(BITJOIN,9795)@209
    assign i_shl_i_i_i_i_i_i_98_c_compstr2779_vt_join_q = {redist258_i_shl_i_i_i_i_i_i_98_c_compstr2779_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_offset(CONSTANT,30714)
    assign redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_offset_q = $unsigned(8'b01000010);

    // redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_rdcnt(ADD,32163)
    assign redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_a = {1'b0, redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_wraddr_q};
    assign redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_b = {1'b0, redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_o <= $unsigned(redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_a) + $unsigned(redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_b);
        end
    end
    assign redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_q = redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_o[8:0];

    // redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_inputreg0(DELAY,32158)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl);
        end
    end

    // redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_wraddr(COUNTER,32161)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_wraddr_i <= $unsigned(redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_wraddr_q = redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_wraddr_i[7:0];

    // redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem(DUALMEM,32160)
    assign redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_ia = $unsigned(redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_inputreg0_q);
    assign redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_aa = redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_wraddr_q;
    assign redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_ab = redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_aa),
        .data_a(redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_ab),
        .q_b(redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_q = redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_iq[15:0];

    // redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_outputreg0(DELAY,32159)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_outputreg0_q <= $unsigned(redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_mem_q);
        end
    end

    // redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_rdcnt(ADD,30715)
    assign redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_a = {1'b0, redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_wraddr_q};
    assign redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_b = {1'b0, redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_o <= $unsigned(redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_a) + $unsigned(redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_b);
        end
    end
    assign redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_q = redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_o[8:0];

    // redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_inputreg0(DELAY,30710)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl);
        end
    end

    // redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_wraddr(COUNTER,30713)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_wraddr_i <= $unsigned(redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_wraddr_q = redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_wraddr_i[7:0];

    // redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem(DUALMEM,30712)
    assign redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_ia = $unsigned(redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_inputreg0_q);
    assign redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_aa = redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_wraddr_q;
    assign redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_ab = redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_aa),
        .data_a(redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_ab),
        .q_b(redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_q = redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_iq[15:0];

    // redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_outputreg0(DELAY,30711)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_outputreg0_q <= $unsigned(redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_mem_q);
        end
    end

    // redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_rdcnt(ADD,30721)
    assign redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_a = {1'b0, redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_wraddr_q};
    assign redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_b = {1'b0, redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_o <= $unsigned(redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_a) + $unsigned(redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_b);
        end
    end
    assign redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_q = redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_o[8:0];

    // redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_inputreg0(DELAY,30716)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl);
        end
    end

    // redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_wraddr(COUNTER,30719)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_wraddr_i <= $unsigned(redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_wraddr_q = redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_wraddr_i[7:0];

    // redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem(DUALMEM,30718)
    assign redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_ia = $unsigned(redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_inputreg0_q);
    assign redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_aa = redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_wraddr_q;
    assign redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_ab = redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_aa),
        .data_a(redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_ab),
        .q_b(redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_q = redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_iq[15:0];

    // redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_outputreg0(DELAY,30717)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_outputreg0_q <= $unsigned(redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_mem_q);
        end
    end

    // redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_rdcnt(ADD,32157)
    assign redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_a = {1'b0, redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_wraddr_q};
    assign redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_b = {1'b0, redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_o <= $unsigned(redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_a) + $unsigned(redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_b);
        end
    end
    assign redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_q = redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_o[8:0];

    // redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_inputreg0(DELAY,32152)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl);
        end
    end

    // redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_wraddr(COUNTER,32155)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_wraddr_i <= $unsigned(redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_wraddr_q = redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_wraddr_i[7:0];

    // redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem(DUALMEM,32154)
    assign redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_ia = $unsigned(redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_inputreg0_q);
    assign redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_aa = redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_wraddr_q;
    assign redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_ab = redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_aa),
        .data_a(redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_ab),
        .q_b(redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_q = redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_iq[15:0];

    // redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_outputreg0(DELAY,32153)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_outputreg0_q <= $unsigned(redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28059)@203 + 5
    // out q@209
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780(ADD,8646)@209
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod531_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_b = $unsigned({{5{i_shl_i_i_i_i_i_i_98_c_compstr2779_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_98_c_compstr2779_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_o[33:0];

    // rightShiftStage0_uid21045_dupName_393_i_unnamed_c_compstr0_shift_x(MUX,21044)@209
    assign rightShiftStage0_uid21045_dupName_393_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21045_dupName_393_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_q or rightShiftStage0Idx1_uid21043_dupName_393_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21045_dupName_393_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21045_dupName_393_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_q;
            1'b1 : rightShiftStage0_uid21045_dupName_393_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21043_dupName_393_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21045_dupName_393_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21050_dupName_393_i_unnamed_c_compstr0_shift_x(MUX,21049)@209
    assign rightShiftStage1_uid21050_dupName_393_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21050_dupName_393_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21045_dupName_393_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21048_dupName_393_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21050_dupName_393_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21050_dupName_393_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21045_dupName_393_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21050_dupName_393_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21048_dupName_393_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21050_dupName_393_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21055_dupName_393_i_unnamed_c_compstr0_shift_x(MUX,21054)@209
    assign rightShiftStage2_uid21055_dupName_393_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21055_dupName_393_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21050_dupName_393_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21053_dupName_393_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21055_dupName_393_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21055_dupName_393_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21050_dupName_393_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21055_dupName_393_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21053_dupName_393_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21055_dupName_393_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2781_vt_select_20(BITSELECT,11353)@209
    assign i_unnamed_c_compstr2781_vt_select_20_b = rightShiftStage2_uid21055_dupName_393_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2781_vt_join(BITJOIN,11352)@209
    assign i_unnamed_c_compstr2781_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2781_vt_select_20_b};

    // i_conv_i_i_i_i_i_98_c_compstr2782_sel_x(BITSELECT,3837)@209
    assign i_conv_i_i_i_i_i_98_c_compstr2782_sel_x_b = i_unnamed_c_compstr2781_vt_join_q[15:0];

    // redist1028_i_conv_i_i_i_i_i_98_c_compstr2782_sel_x_b_1(DELAY,29256)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1028_i_conv_i_i_i_i_i_98_c_compstr2782_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_98_c_compstr2782_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21064_dupName_394_i_unnamed_c_compstr0_shift_x(BITSELECT,21063)@209
    assign rightShiftStage1Idx1Rng8_uid21064_dupName_394_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21063_dupName_394_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21066_dupName_394_i_unnamed_c_compstr0_shift_x(BITJOIN,21065)@209
    assign rightShiftStage1Idx1_uid21066_dupName_394_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21064_dupName_394_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21059_dupName_394_i_unnamed_c_compstr0_shift_x(BITSELECT,21058)@209
    assign rightShiftStage0Idx1Rng4_uid21059_dupName_394_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_q[33:4];

    // rightShiftStage0Idx1_uid21061_dupName_394_i_unnamed_c_compstr0_shift_x(BITJOIN,21060)@209
    assign rightShiftStage0Idx1_uid21061_dupName_394_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21059_dupName_394_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21063_dupName_394_i_unnamed_c_compstr0_shift_x(MUX,21062)@209
    assign rightShiftStage0_uid21063_dupName_394_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21063_dupName_394_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_q or rightShiftStage0Idx1_uid21061_dupName_394_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21063_dupName_394_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21063_dupName_394_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compstr2780_q;
            1'b1 : rightShiftStage0_uid21063_dupName_394_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21061_dupName_394_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21063_dupName_394_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21068_dupName_394_i_unnamed_c_compstr0_shift_x(MUX,21067)@209
    assign rightShiftStage1_uid21068_dupName_394_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21068_dupName_394_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21063_dupName_394_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21066_dupName_394_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21068_dupName_394_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21068_dupName_394_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21063_dupName_394_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21068_dupName_394_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21066_dupName_394_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21068_dupName_394_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2783_vt_select_21(BITSELECT,11356)@209
    assign i_unnamed_c_compstr2783_vt_select_21_b = rightShiftStage1_uid21068_dupName_394_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2783_vt_join(BITJOIN,11355)@209
    assign i_unnamed_c_compstr2783_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2783_vt_select_21_b};

    // i_unnamed_c_compstr2784_sel_x(BITSELECT,6176)@209
    assign i_unnamed_c_compstr2784_sel_x_b = i_unnamed_c_compstr2783_vt_join_q[15:0];

    // i_unnamed_c_compstr2785_BitSelect_for_a(BITSELECT,27741)@209
    assign i_unnamed_c_compstr2785_BitSelect_for_a_b = i_unnamed_c_compstr2784_sel_x_b[0:0];

    // i_unnamed_c_compstr2785_join(BITJOIN,27742)@209
    assign i_unnamed_c_compstr2785_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2785_BitSelect_for_a_b};

    // i_unnamed_c_compstr2785_vt_select_0(BITSELECT,11361)@209
    assign i_unnamed_c_compstr2785_vt_select_0_b = i_unnamed_c_compstr2785_join_q[0:0];

    // redist115_i_unnamed_c_compstr2785_vt_select_0_b_1(DELAY,28343)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist115_i_unnamed_c_compstr2785_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2785_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2785_vt_join(BITJOIN,11360)@210
    assign i_unnamed_c_compstr2785_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist115_i_unnamed_c_compstr2785_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_98_c_compstr2786(ADD,7104)@210
    assign i_add_i_i_i_i_i_i_98_c_compstr2786_a = {1'b0, i_unnamed_c_compstr2785_vt_join_q};
    assign i_add_i_i_i_i_i_i_98_c_compstr2786_b = {1'b0, redist1028_i_conv_i_i_i_i_i_98_c_compstr2782_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_98_c_compstr2786_o = $unsigned(i_add_i_i_i_i_i_i_98_c_compstr2786_a) + $unsigned(i_add_i_i_i_i_i_i_98_c_compstr2786_b);
    assign i_add_i_i_i_i_i_i_98_c_compstr2786_q = i_add_i_i_i_i_i_i_98_c_compstr2786_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_98_c_compstr2786_sel_x(BITSELECT,2298)@210
    assign bgTrunc_i_add_i_i_i_i_i_i_98_c_compstr2786_sel_x_b = i_add_i_i_i_i_i_i_98_c_compstr2786_q[15:0];

    // i_conv_i_i_i_i_i_i279_99_c_compstr2806_sel_x(BITSELECT,3966)@210
    assign i_conv_i_i_i_i_i_i279_99_c_compstr2806_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_98_c_compstr2786_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_99_c_compstr2806_vt_select_15(BITSELECT,8381)@210
    assign i_conv_i_i_i_i_i_i279_99_c_compstr2806_vt_select_15_b = i_conv_i_i_i_i_i_i279_99_c_compstr2806_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_99_c_compstr2806_vt_join(BITJOIN,8380)@210
    assign i_conv_i_i_i_i_i_i279_99_c_compstr2806_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_99_c_compstr2806_vt_select_15_b};

    // leftShiftStage0_uid27410_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x(MUX,27409)@210
    assign leftShiftStage0_uid27410_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27410_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_99_c_compstr2806_vt_join_q or leftShiftStage0Idx1_uid27408_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27410_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid27410_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_99_c_compstr2806_vt_join_q;
            1'b1 : leftShiftStage0_uid27410_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid27408_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid27410_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27415_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x(MUX,27414)@210
    assign leftShiftStage1_uid27415_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27415_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_s or leftShiftStage0_uid27410_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid27413_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27415_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid27415_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q = leftShiftStage0_uid27410_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid27415_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid27413_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid27415_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27420_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x(MUX,27419)@210
    assign leftShiftStage2_uid27420_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27420_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_s or leftShiftStage1_uid27415_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid27418_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27420_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid27420_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q = leftShiftStage1_uid27415_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid27420_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid27418_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid27420_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_99_c_compstr2807_vt_select_28(BITSELECT,9799)@210
    assign i_shl_i_i_i_i_i_i_99_c_compstr2807_vt_select_28_b = leftShiftStage2_uid27420_i_shl_i_i_i_i_i_i_99_c_compstr0_shift_x_q[28:13];

    // redist257_i_shl_i_i_i_i_i_i_99_c_compstr2807_vt_select_28_b_1(DELAY,28485)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist257_i_shl_i_i_i_i_i_i_99_c_compstr2807_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_99_c_compstr2807_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_99_c_compstr2807_vt_join(BITJOIN,9798)@211
    assign i_shl_i_i_i_i_i_i_99_c_compstr2807_vt_join_q = {redist257_i_shl_i_i_i_i_i_i_99_c_compstr2807_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_offset(CONSTANT,30726)
    assign redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_offset_q = $unsigned(8'b01000000);

    // redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_rdcnt(ADD,32175)
    assign redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_a = {1'b0, redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_wraddr_q};
    assign redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_b = {1'b0, redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_o <= $unsigned(redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_a) + $unsigned(redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_b);
        end
    end
    assign redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_q = redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_o[8:0];

    // redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_inputreg0(DELAY,32170)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl);
        end
    end

    // redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_wraddr(COUNTER,32173)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_wraddr_i <= $unsigned(redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_wraddr_q = redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_wraddr_i[7:0];

    // redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem(DUALMEM,32172)
    assign redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_ia = $unsigned(redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_inputreg0_q);
    assign redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_aa = redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_wraddr_q;
    assign redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_ab = redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_aa),
        .data_a(redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_ab),
        .q_b(redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_q = redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_iq[15:0];

    // redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_outputreg0(DELAY,32171)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_outputreg0_q <= $unsigned(redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_mem_q);
        end
    end

    // redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_rdcnt(ADD,30727)
    assign redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_a = {1'b0, redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_wraddr_q};
    assign redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_b = {1'b0, redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_o <= $unsigned(redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_a) + $unsigned(redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_b);
        end
    end
    assign redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_q = redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_o[8:0];

    // redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_inputreg0(DELAY,30722)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl);
        end
    end

    // redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_wraddr(COUNTER,30725)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_wraddr_i <= $unsigned(redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_wraddr_q = redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_wraddr_i[7:0];

    // redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem(DUALMEM,30724)
    assign redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_ia = $unsigned(redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_inputreg0_q);
    assign redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_aa = redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_wraddr_q;
    assign redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_ab = redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_aa),
        .data_a(redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_ab),
        .q_b(redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_q = redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_iq[15:0];

    // redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_outputreg0(DELAY,30723)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_outputreg0_q <= $unsigned(redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_mem_q);
        end
    end

    // redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_rdcnt(ADD,30733)
    assign redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_a = {1'b0, redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_wraddr_q};
    assign redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_b = {1'b0, redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_o <= $unsigned(redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_a) + $unsigned(redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_b);
        end
    end
    assign redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_q = redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_o[8:0];

    // redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_inputreg0(DELAY,30728)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl);
        end
    end

    // redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_wraddr(COUNTER,30731)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_wraddr_i <= $unsigned(redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_wraddr_q = redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_wraddr_i[7:0];

    // redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem(DUALMEM,30730)
    assign redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_ia = $unsigned(redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_inputreg0_q);
    assign redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_aa = redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_wraddr_q;
    assign redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_ab = redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_aa),
        .data_a(redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_ab),
        .q_b(redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_q = redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_iq[15:0];

    // redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_outputreg0(DELAY,30729)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_outputreg0_q <= $unsigned(redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_mem_q);
        end
    end

    // redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_rdcnt(ADD,32169)
    assign redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_a = {1'b0, redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_wraddr_q};
    assign redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_b = {1'b0, redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_o <= $unsigned(redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_a) + $unsigned(redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_b);
        end
    end
    assign redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_q = redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_o[8:0];

    // redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_inputreg0(DELAY,32164)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl);
        end
    end

    // redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_wraddr(COUNTER,32167)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_wraddr_i <= $unsigned(redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_wraddr_q = redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_wraddr_i[7:0];

    // redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem(DUALMEM,32166)
    assign redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_ia = $unsigned(redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_inputreg0_q);
    assign redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_aa = redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_wraddr_q;
    assign redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_ab = redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_aa),
        .data_a(redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_ab),
        .q_b(redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_q = redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_iq[15:0];

    // redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_outputreg0(DELAY,32165)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_outputreg0_q <= $unsigned(redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28060)@205 + 5
    // out q@211
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808(ADD,8647)@211
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod536_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_b = $unsigned({{5{i_shl_i_i_i_i_i_i_99_c_compstr2807_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_99_c_compstr2807_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_o[33:0];

    // rightShiftStage0_uid21107_dupName_397_i_unnamed_c_compstr0_shift_x(MUX,21106)@211
    assign rightShiftStage0_uid21107_dupName_397_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21107_dupName_397_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_q or rightShiftStage0Idx1_uid21105_dupName_397_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21107_dupName_397_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21107_dupName_397_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_q;
            1'b1 : rightShiftStage0_uid21107_dupName_397_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21105_dupName_397_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21107_dupName_397_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21112_dupName_397_i_unnamed_c_compstr0_shift_x(MUX,21111)@211
    assign rightShiftStage1_uid21112_dupName_397_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21112_dupName_397_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21107_dupName_397_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21110_dupName_397_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21112_dupName_397_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21112_dupName_397_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21107_dupName_397_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21112_dupName_397_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21110_dupName_397_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21112_dupName_397_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21117_dupName_397_i_unnamed_c_compstr0_shift_x(MUX,21116)@211
    assign rightShiftStage2_uid21117_dupName_397_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21117_dupName_397_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21112_dupName_397_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21115_dupName_397_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21117_dupName_397_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21117_dupName_397_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21112_dupName_397_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21117_dupName_397_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21115_dupName_397_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21117_dupName_397_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2809_vt_select_20(BITSELECT,11378)@211
    assign i_unnamed_c_compstr2809_vt_select_20_b = rightShiftStage2_uid21117_dupName_397_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2809_vt_join(BITJOIN,11377)@211
    assign i_unnamed_c_compstr2809_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2809_vt_select_20_b};

    // i_conv_i_i_i_i_i_99_c_compstr2810_sel_x(BITSELECT,3838)@211
    assign i_conv_i_i_i_i_i_99_c_compstr2810_sel_x_b = i_unnamed_c_compstr2809_vt_join_q[15:0];

    // redist1027_i_conv_i_i_i_i_i_99_c_compstr2810_sel_x_b_1(DELAY,29255)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1027_i_conv_i_i_i_i_i_99_c_compstr2810_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_99_c_compstr2810_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21126_dupName_398_i_unnamed_c_compstr0_shift_x(BITSELECT,21125)@211
    assign rightShiftStage1Idx1Rng8_uid21126_dupName_398_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21125_dupName_398_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21128_dupName_398_i_unnamed_c_compstr0_shift_x(BITJOIN,21127)@211
    assign rightShiftStage1Idx1_uid21128_dupName_398_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21126_dupName_398_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21121_dupName_398_i_unnamed_c_compstr0_shift_x(BITSELECT,21120)@211
    assign rightShiftStage0Idx1Rng4_uid21121_dupName_398_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_q[33:4];

    // rightShiftStage0Idx1_uid21123_dupName_398_i_unnamed_c_compstr0_shift_x(BITJOIN,21122)@211
    assign rightShiftStage0Idx1_uid21123_dupName_398_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21121_dupName_398_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21125_dupName_398_i_unnamed_c_compstr0_shift_x(MUX,21124)@211
    assign rightShiftStage0_uid21125_dupName_398_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21125_dupName_398_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_q or rightShiftStage0Idx1_uid21123_dupName_398_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21125_dupName_398_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21125_dupName_398_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compstr2808_q;
            1'b1 : rightShiftStage0_uid21125_dupName_398_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21123_dupName_398_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21125_dupName_398_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21130_dupName_398_i_unnamed_c_compstr0_shift_x(MUX,21129)@211
    assign rightShiftStage1_uid21130_dupName_398_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21130_dupName_398_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21125_dupName_398_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21128_dupName_398_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21130_dupName_398_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21130_dupName_398_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21125_dupName_398_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21130_dupName_398_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21128_dupName_398_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21130_dupName_398_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2811_vt_select_21(BITSELECT,11381)@211
    assign i_unnamed_c_compstr2811_vt_select_21_b = rightShiftStage1_uid21130_dupName_398_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2811_vt_join(BITJOIN,11380)@211
    assign i_unnamed_c_compstr2811_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2811_vt_select_21_b};

    // i_unnamed_c_compstr2812_sel_x(BITSELECT,6178)@211
    assign i_unnamed_c_compstr2812_sel_x_b = i_unnamed_c_compstr2811_vt_join_q[15:0];

    // i_unnamed_c_compstr2813_BitSelect_for_a(BITSELECT,27745)@211
    assign i_unnamed_c_compstr2813_BitSelect_for_a_b = i_unnamed_c_compstr2812_sel_x_b[0:0];

    // i_unnamed_c_compstr2813_join(BITJOIN,27746)@211
    assign i_unnamed_c_compstr2813_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2813_BitSelect_for_a_b};

    // i_unnamed_c_compstr2813_vt_select_0(BITSELECT,11386)@211
    assign i_unnamed_c_compstr2813_vt_select_0_b = i_unnamed_c_compstr2813_join_q[0:0];

    // redist113_i_unnamed_c_compstr2813_vt_select_0_b_1(DELAY,28341)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist113_i_unnamed_c_compstr2813_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2813_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2813_vt_join(BITJOIN,11385)@212
    assign i_unnamed_c_compstr2813_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist113_i_unnamed_c_compstr2813_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_99_c_compstr2814(ADD,7105)@212
    assign i_add_i_i_i_i_i_i_99_c_compstr2814_a = {1'b0, i_unnamed_c_compstr2813_vt_join_q};
    assign i_add_i_i_i_i_i_i_99_c_compstr2814_b = {1'b0, redist1027_i_conv_i_i_i_i_i_99_c_compstr2810_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_99_c_compstr2814_o = $unsigned(i_add_i_i_i_i_i_i_99_c_compstr2814_a) + $unsigned(i_add_i_i_i_i_i_i_99_c_compstr2814_b);
    assign i_add_i_i_i_i_i_i_99_c_compstr2814_q = i_add_i_i_i_i_i_i_99_c_compstr2814_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_99_c_compstr2814_sel_x(BITSELECT,2299)@212
    assign bgTrunc_i_add_i_i_i_i_i_i_99_c_compstr2814_sel_x_b = i_add_i_i_i_i_i_i_99_c_compstr2814_q[15:0];

    // i_conv_i_i_i_i_i_i279_100_c_compstr2834_sel_x(BITSELECT,3841)@212
    assign i_conv_i_i_i_i_i_i279_100_c_compstr2834_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_99_c_compstr2814_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_100_c_compstr2834_vt_select_15(BITSELECT,7881)@212
    assign i_conv_i_i_i_i_i_i279_100_c_compstr2834_vt_select_15_b = i_conv_i_i_i_i_i_i279_100_c_compstr2834_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_100_c_compstr2834_vt_join(BITJOIN,7880)@212
    assign i_conv_i_i_i_i_i_i279_100_c_compstr2834_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_100_c_compstr2834_vt_select_15_b};

    // leftShiftStage0_uid25160_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x(MUX,25159)@212
    assign leftShiftStage0_uid25160_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25160_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_100_c_compstr2834_vt_join_q or leftShiftStage0Idx1_uid25158_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25160_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25160_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_100_c_compstr2834_vt_join_q;
            1'b1 : leftShiftStage0_uid25160_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25158_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25160_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25165_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x(MUX,25164)@212
    assign leftShiftStage1_uid25165_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25165_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_s or leftShiftStage0_uid25160_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25163_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25165_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25165_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q = leftShiftStage0_uid25160_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25165_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25163_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25165_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25170_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x(MUX,25169)@212
    assign leftShiftStage2_uid25170_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25170_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_s or leftShiftStage1_uid25165_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25168_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25170_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25170_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q = leftShiftStage1_uid25165_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25170_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25168_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25170_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_100_c_compstr2835_vt_select_28(BITSELECT,9424)@212
    assign i_shl_i_i_i_i_i_i_100_c_compstr2835_vt_select_28_b = leftShiftStage2_uid25170_i_shl_i_i_i_i_i_i_100_c_compstr0_shift_x_q[28:13];

    // redist382_i_shl_i_i_i_i_i_i_100_c_compstr2835_vt_select_28_b_1(DELAY,28610)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist382_i_shl_i_i_i_i_i_i_100_c_compstr2835_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_100_c_compstr2835_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_100_c_compstr2835_vt_join(BITJOIN,9423)@213
    assign i_shl_i_i_i_i_i_i_100_c_compstr2835_vt_join_q = {redist382_i_shl_i_i_i_i_i_i_100_c_compstr2835_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_offset(CONSTANT,30738)
    assign redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_offset_q = $unsigned(8'b00111110);

    // redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_rdcnt(ADD,32187)
    assign redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_a = {1'b0, redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_wraddr_q};
    assign redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_b = {1'b0, redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_o <= $unsigned(redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_a) + $unsigned(redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_b);
        end
    end
    assign redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_q = redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_o[8:0];

    // redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_inputreg0(DELAY,32182)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl);
        end
    end

    // redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_wraddr(COUNTER,32185)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_wraddr_i <= $unsigned(redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_wraddr_q = redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_wraddr_i[7:0];

    // redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem(DUALMEM,32184)
    assign redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_ia = $unsigned(redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_inputreg0_q);
    assign redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_aa = redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_wraddr_q;
    assign redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_ab = redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_aa),
        .data_a(redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_ab),
        .q_b(redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_q = redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_iq[15:0];

    // redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_outputreg0(DELAY,32183)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_outputreg0_q <= $unsigned(redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_mem_q);
        end
    end

    // redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_rdcnt(ADD,30739)
    assign redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_a = {1'b0, redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_wraddr_q};
    assign redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_b = {1'b0, redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_o <= $unsigned(redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_a) + $unsigned(redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_b);
        end
    end
    assign redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_q = redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_o[8:0];

    // redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_inputreg0(DELAY,30734)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl);
        end
    end

    // redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_wraddr(COUNTER,30737)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_wraddr_i <= $unsigned(redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_wraddr_q = redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_wraddr_i[7:0];

    // redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem(DUALMEM,30736)
    assign redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_ia = $unsigned(redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_inputreg0_q);
    assign redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_aa = redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_wraddr_q;
    assign redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_ab = redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_aa),
        .data_a(redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_ab),
        .q_b(redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_q = redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_iq[15:0];

    // redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_outputreg0(DELAY,30735)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_outputreg0_q <= $unsigned(redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_mem_q);
        end
    end

    // redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_rdcnt(ADD,30745)
    assign redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_a = {1'b0, redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_wraddr_q};
    assign redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_b = {1'b0, redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_o <= $unsigned(redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_a) + $unsigned(redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_b);
        end
    end
    assign redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_q = redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_o[8:0];

    // redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_inputreg0(DELAY,30740)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl);
        end
    end

    // redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_wraddr(COUNTER,30743)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_wraddr_i <= $unsigned(redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_wraddr_q = redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_wraddr_i[7:0];

    // redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem(DUALMEM,30742)
    assign redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_ia = $unsigned(redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_inputreg0_q);
    assign redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_aa = redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_wraddr_q;
    assign redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_ab = redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_aa),
        .data_a(redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_ab),
        .q_b(redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_q = redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_iq[15:0];

    // redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_outputreg0(DELAY,30741)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_outputreg0_q <= $unsigned(redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_mem_q);
        end
    end

    // redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_rdcnt(ADD,32181)
    assign redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_a = {1'b0, redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_wraddr_q};
    assign redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_b = {1'b0, redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_o <= $unsigned(redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_a) + $unsigned(redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_b);
        end
    end
    assign redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_q = redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_o[8:0];

    // redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_inputreg0(DELAY,32176)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl);
        end
    end

    // redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_wraddr(COUNTER,32179)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_wraddr_i <= $unsigned(redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_wraddr_q = redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_wraddr_i[7:0];

    // redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem(DUALMEM,32178)
    assign redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_ia = $unsigned(redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_inputreg0_q);
    assign redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_aa = redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_wraddr_q;
    assign redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_ab = redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_aa),
        .data_a(redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_ab),
        .q_b(redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_q = redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_iq[15:0];

    // redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_outputreg0(DELAY,32177)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_outputreg0_q <= $unsigned(redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28061)@207 + 5
    // out q@213
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836(ADD,8522)@213
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod541_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_b = $unsigned({{5{i_shl_i_i_i_i_i_i_100_c_compstr2835_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_100_c_compstr2835_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_o[33:0];

    // rightShiftStage0_uid21169_dupName_401_i_unnamed_c_compstr0_shift_x(MUX,21168)@213
    assign rightShiftStage0_uid21169_dupName_401_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21169_dupName_401_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_q or rightShiftStage0Idx1_uid21167_dupName_401_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21169_dupName_401_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21169_dupName_401_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_q;
            1'b1 : rightShiftStage0_uid21169_dupName_401_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21167_dupName_401_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21169_dupName_401_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21174_dupName_401_i_unnamed_c_compstr0_shift_x(MUX,21173)@213
    assign rightShiftStage1_uid21174_dupName_401_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21174_dupName_401_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21169_dupName_401_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21172_dupName_401_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21174_dupName_401_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21174_dupName_401_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21169_dupName_401_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21174_dupName_401_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21172_dupName_401_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21174_dupName_401_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21179_dupName_401_i_unnamed_c_compstr0_shift_x(MUX,21178)@213
    assign rightShiftStage2_uid21179_dupName_401_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21179_dupName_401_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21174_dupName_401_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21177_dupName_401_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21179_dupName_401_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21179_dupName_401_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21174_dupName_401_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21179_dupName_401_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21177_dupName_401_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21179_dupName_401_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2837_vt_select_20(BITSELECT,11400)@213
    assign i_unnamed_c_compstr2837_vt_select_20_b = rightShiftStage2_uid21179_dupName_401_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2837_vt_join(BITJOIN,11399)@213
    assign i_unnamed_c_compstr2837_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2837_vt_select_20_b};

    // i_conv_i_i_i_i_i_100_c_compstr2838_sel_x(BITSELECT,3713)@213
    assign i_conv_i_i_i_i_i_100_c_compstr2838_sel_x_b = i_unnamed_c_compstr2837_vt_join_q[15:0];

    // redist1152_i_conv_i_i_i_i_i_100_c_compstr2838_sel_x_b_1(DELAY,29380)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1152_i_conv_i_i_i_i_i_100_c_compstr2838_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_100_c_compstr2838_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21188_dupName_402_i_unnamed_c_compstr0_shift_x(BITSELECT,21187)@213
    assign rightShiftStage1Idx1Rng8_uid21188_dupName_402_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21187_dupName_402_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21190_dupName_402_i_unnamed_c_compstr0_shift_x(BITJOIN,21189)@213
    assign rightShiftStage1Idx1_uid21190_dupName_402_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21188_dupName_402_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21183_dupName_402_i_unnamed_c_compstr0_shift_x(BITSELECT,21182)@213
    assign rightShiftStage0Idx1Rng4_uid21183_dupName_402_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_q[33:4];

    // rightShiftStage0Idx1_uid21185_dupName_402_i_unnamed_c_compstr0_shift_x(BITJOIN,21184)@213
    assign rightShiftStage0Idx1_uid21185_dupName_402_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21183_dupName_402_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21187_dupName_402_i_unnamed_c_compstr0_shift_x(MUX,21186)@213
    assign rightShiftStage0_uid21187_dupName_402_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21187_dupName_402_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_q or rightShiftStage0Idx1_uid21185_dupName_402_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21187_dupName_402_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21187_dupName_402_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compstr2836_q;
            1'b1 : rightShiftStage0_uid21187_dupName_402_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21185_dupName_402_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21187_dupName_402_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21192_dupName_402_i_unnamed_c_compstr0_shift_x(MUX,21191)@213
    assign rightShiftStage1_uid21192_dupName_402_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21192_dupName_402_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21187_dupName_402_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21190_dupName_402_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21192_dupName_402_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21192_dupName_402_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21187_dupName_402_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21192_dupName_402_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21190_dupName_402_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21192_dupName_402_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2839_vt_select_21(BITSELECT,11403)@213
    assign i_unnamed_c_compstr2839_vt_select_21_b = rightShiftStage1_uid21192_dupName_402_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2839_vt_join(BITJOIN,11402)@213
    assign i_unnamed_c_compstr2839_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2839_vt_select_21_b};

    // i_unnamed_c_compstr2840_sel_x(BITSELECT,6180)@213
    assign i_unnamed_c_compstr2840_sel_x_b = i_unnamed_c_compstr2839_vt_join_q[15:0];

    // i_unnamed_c_compstr2841_BitSelect_for_a(BITSELECT,27749)@213
    assign i_unnamed_c_compstr2841_BitSelect_for_a_b = i_unnamed_c_compstr2840_sel_x_b[0:0];

    // i_unnamed_c_compstr2841_join(BITJOIN,27750)@213
    assign i_unnamed_c_compstr2841_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2841_BitSelect_for_a_b};

    // i_unnamed_c_compstr2841_vt_select_0(BITSELECT,11408)@213
    assign i_unnamed_c_compstr2841_vt_select_0_b = i_unnamed_c_compstr2841_join_q[0:0];

    // redist111_i_unnamed_c_compstr2841_vt_select_0_b_1(DELAY,28339)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist111_i_unnamed_c_compstr2841_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2841_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2841_vt_join(BITJOIN,11407)@214
    assign i_unnamed_c_compstr2841_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist111_i_unnamed_c_compstr2841_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_100_c_compstr2842(ADD,6980)@214
    assign i_add_i_i_i_i_i_i_100_c_compstr2842_a = {1'b0, i_unnamed_c_compstr2841_vt_join_q};
    assign i_add_i_i_i_i_i_i_100_c_compstr2842_b = {1'b0, redist1152_i_conv_i_i_i_i_i_100_c_compstr2838_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_100_c_compstr2842_o = $unsigned(i_add_i_i_i_i_i_i_100_c_compstr2842_a) + $unsigned(i_add_i_i_i_i_i_i_100_c_compstr2842_b);
    assign i_add_i_i_i_i_i_i_100_c_compstr2842_q = i_add_i_i_i_i_i_i_100_c_compstr2842_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_100_c_compstr2842_sel_x(BITSELECT,2174)@214
    assign bgTrunc_i_add_i_i_i_i_i_i_100_c_compstr2842_sel_x_b = i_add_i_i_i_i_i_i_100_c_compstr2842_q[15:0];

    // i_conv_i_i_i_i_i_i279_101_c_compstr2862_sel_x(BITSELECT,3842)@214
    assign i_conv_i_i_i_i_i_i279_101_c_compstr2862_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_100_c_compstr2842_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_101_c_compstr2862_vt_select_15(BITSELECT,7885)@214
    assign i_conv_i_i_i_i_i_i279_101_c_compstr2862_vt_select_15_b = i_conv_i_i_i_i_i_i279_101_c_compstr2862_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_101_c_compstr2862_vt_join(BITJOIN,7884)@214
    assign i_conv_i_i_i_i_i_i279_101_c_compstr2862_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_101_c_compstr2862_vt_select_15_b};

    // leftShiftStage0_uid25178_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x(MUX,25177)@214
    assign leftShiftStage0_uid25178_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25178_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_101_c_compstr2862_vt_join_q or leftShiftStage0Idx1_uid25176_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25178_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25178_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_101_c_compstr2862_vt_join_q;
            1'b1 : leftShiftStage0_uid25178_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25176_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25178_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25183_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x(MUX,25182)@214
    assign leftShiftStage1_uid25183_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25183_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_s or leftShiftStage0_uid25178_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25181_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25183_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25183_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q = leftShiftStage0_uid25178_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25183_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25181_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25183_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25188_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x(MUX,25187)@214
    assign leftShiftStage2_uid25188_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25188_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_s or leftShiftStage1_uid25183_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25186_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25188_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25188_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q = leftShiftStage1_uid25183_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25188_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25186_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25188_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_101_c_compstr2863_vt_select_28(BITSELECT,9427)@214
    assign i_shl_i_i_i_i_i_i_101_c_compstr2863_vt_select_28_b = leftShiftStage2_uid25188_i_shl_i_i_i_i_i_i_101_c_compstr0_shift_x_q[28:13];

    // redist381_i_shl_i_i_i_i_i_i_101_c_compstr2863_vt_select_28_b_1(DELAY,28609)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist381_i_shl_i_i_i_i_i_i_101_c_compstr2863_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_101_c_compstr2863_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_101_c_compstr2863_vt_join(BITJOIN,9426)@215
    assign i_shl_i_i_i_i_i_i_101_c_compstr2863_vt_join_q = {redist381_i_shl_i_i_i_i_i_i_101_c_compstr2863_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_offset(CONSTANT,30750)
    assign redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_offset_q = $unsigned(8'b00111100);

    // redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_rdcnt(ADD,32199)
    assign redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_a = {1'b0, redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_wraddr_q};
    assign redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_b = {1'b0, redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_o <= $unsigned(redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_a) + $unsigned(redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_b);
        end
    end
    assign redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_q = redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_o[8:0];

    // redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_inputreg0(DELAY,32194)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl);
        end
    end

    // redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_wraddr(COUNTER,32197)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_wraddr_i <= $unsigned(redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_wraddr_q = redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_wraddr_i[7:0];

    // redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem(DUALMEM,32196)
    assign redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_ia = $unsigned(redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_inputreg0_q);
    assign redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_aa = redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_wraddr_q;
    assign redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_ab = redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_aa),
        .data_a(redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_ab),
        .q_b(redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_q = redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_iq[15:0];

    // redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_outputreg0(DELAY,32195)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_outputreg0_q <= $unsigned(redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_mem_q);
        end
    end

    // redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_rdcnt(ADD,30751)
    assign redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_a = {1'b0, redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_wraddr_q};
    assign redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_b = {1'b0, redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_o <= $unsigned(redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_a) + $unsigned(redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_b);
        end
    end
    assign redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_q = redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_o[8:0];

    // redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_inputreg0(DELAY,30746)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl);
        end
    end

    // redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_wraddr(COUNTER,30749)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_wraddr_i <= $unsigned(redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_wraddr_q = redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_wraddr_i[7:0];

    // redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem(DUALMEM,30748)
    assign redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_ia = $unsigned(redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_inputreg0_q);
    assign redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_aa = redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_wraddr_q;
    assign redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_ab = redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_aa),
        .data_a(redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_ab),
        .q_b(redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_q = redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_iq[15:0];

    // redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_outputreg0(DELAY,30747)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_outputreg0_q <= $unsigned(redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_mem_q);
        end
    end

    // redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_rdcnt(ADD,30757)
    assign redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_a = {1'b0, redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_wraddr_q};
    assign redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_b = {1'b0, redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_o <= $unsigned(redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_a) + $unsigned(redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_b);
        end
    end
    assign redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_q = redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_o[8:0];

    // redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_inputreg0(DELAY,30752)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl);
        end
    end

    // redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_wraddr(COUNTER,30755)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_wraddr_i <= $unsigned(redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_wraddr_q = redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_wraddr_i[7:0];

    // redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem(DUALMEM,30754)
    assign redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_ia = $unsigned(redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_inputreg0_q);
    assign redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_aa = redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_wraddr_q;
    assign redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_ab = redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_aa),
        .data_a(redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_ab),
        .q_b(redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_q = redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_iq[15:0];

    // redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_outputreg0(DELAY,30753)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_outputreg0_q <= $unsigned(redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_mem_q);
        end
    end

    // redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_rdcnt(ADD,32193)
    assign redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_a = {1'b0, redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_wraddr_q};
    assign redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_b = {1'b0, redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_o <= $unsigned(redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_a) + $unsigned(redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_b);
        end
    end
    assign redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_q = redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_o[8:0];

    // redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_inputreg0(DELAY,32188)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl);
        end
    end

    // redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_wraddr(COUNTER,32191)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_wraddr_i <= $unsigned(redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_wraddr_q = redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_wraddr_i[7:0];

    // redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem(DUALMEM,32190)
    assign redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_ia = $unsigned(redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_inputreg0_q);
    assign redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_aa = redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_wraddr_q;
    assign redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_ab = redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_aa),
        .data_a(redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_ab),
        .q_b(redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_q = redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_iq[15:0];

    // redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_outputreg0(DELAY,32189)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_outputreg0_q <= $unsigned(redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28062)@209 + 5
    // out q@215
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864(ADD,8523)@215
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod546_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_b = $unsigned({{5{i_shl_i_i_i_i_i_i_101_c_compstr2863_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_101_c_compstr2863_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_o[33:0];

    // rightShiftStage0_uid21231_dupName_405_i_unnamed_c_compstr0_shift_x(MUX,21230)@215
    assign rightShiftStage0_uid21231_dupName_405_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21231_dupName_405_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_q or rightShiftStage0Idx1_uid21229_dupName_405_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21231_dupName_405_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21231_dupName_405_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_q;
            1'b1 : rightShiftStage0_uid21231_dupName_405_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21229_dupName_405_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21231_dupName_405_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21236_dupName_405_i_unnamed_c_compstr0_shift_x(MUX,21235)@215
    assign rightShiftStage1_uid21236_dupName_405_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21236_dupName_405_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21231_dupName_405_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21234_dupName_405_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21236_dupName_405_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21236_dupName_405_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21231_dupName_405_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21236_dupName_405_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21234_dupName_405_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21236_dupName_405_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21241_dupName_405_i_unnamed_c_compstr0_shift_x(MUX,21240)@215
    assign rightShiftStage2_uid21241_dupName_405_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21241_dupName_405_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21236_dupName_405_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21239_dupName_405_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21241_dupName_405_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21241_dupName_405_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21236_dupName_405_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21241_dupName_405_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21239_dupName_405_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21241_dupName_405_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2865_vt_select_20(BITSELECT,11422)@215
    assign i_unnamed_c_compstr2865_vt_select_20_b = rightShiftStage2_uid21241_dupName_405_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2865_vt_join(BITJOIN,11421)@215
    assign i_unnamed_c_compstr2865_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2865_vt_select_20_b};

    // i_conv_i_i_i_i_i_101_c_compstr2866_sel_x(BITSELECT,3714)@215
    assign i_conv_i_i_i_i_i_101_c_compstr2866_sel_x_b = i_unnamed_c_compstr2865_vt_join_q[15:0];

    // redist1151_i_conv_i_i_i_i_i_101_c_compstr2866_sel_x_b_1(DELAY,29379)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1151_i_conv_i_i_i_i_i_101_c_compstr2866_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_101_c_compstr2866_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21250_dupName_406_i_unnamed_c_compstr0_shift_x(BITSELECT,21249)@215
    assign rightShiftStage1Idx1Rng8_uid21250_dupName_406_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21249_dupName_406_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21252_dupName_406_i_unnamed_c_compstr0_shift_x(BITJOIN,21251)@215
    assign rightShiftStage1Idx1_uid21252_dupName_406_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21250_dupName_406_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21245_dupName_406_i_unnamed_c_compstr0_shift_x(BITSELECT,21244)@215
    assign rightShiftStage0Idx1Rng4_uid21245_dupName_406_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_q[33:4];

    // rightShiftStage0Idx1_uid21247_dupName_406_i_unnamed_c_compstr0_shift_x(BITJOIN,21246)@215
    assign rightShiftStage0Idx1_uid21247_dupName_406_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21245_dupName_406_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21249_dupName_406_i_unnamed_c_compstr0_shift_x(MUX,21248)@215
    assign rightShiftStage0_uid21249_dupName_406_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21249_dupName_406_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_q or rightShiftStage0Idx1_uid21247_dupName_406_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21249_dupName_406_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21249_dupName_406_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compstr2864_q;
            1'b1 : rightShiftStage0_uid21249_dupName_406_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21247_dupName_406_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21249_dupName_406_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21254_dupName_406_i_unnamed_c_compstr0_shift_x(MUX,21253)@215
    assign rightShiftStage1_uid21254_dupName_406_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21254_dupName_406_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21249_dupName_406_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21252_dupName_406_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21254_dupName_406_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21254_dupName_406_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21249_dupName_406_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21254_dupName_406_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21252_dupName_406_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21254_dupName_406_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2867_vt_select_21(BITSELECT,11425)@215
    assign i_unnamed_c_compstr2867_vt_select_21_b = rightShiftStage1_uid21254_dupName_406_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2867_vt_join(BITJOIN,11424)@215
    assign i_unnamed_c_compstr2867_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2867_vt_select_21_b};

    // i_unnamed_c_compstr2868_sel_x(BITSELECT,6182)@215
    assign i_unnamed_c_compstr2868_sel_x_b = i_unnamed_c_compstr2867_vt_join_q[15:0];

    // i_unnamed_c_compstr2869_BitSelect_for_a(BITSELECT,27753)@215
    assign i_unnamed_c_compstr2869_BitSelect_for_a_b = i_unnamed_c_compstr2868_sel_x_b[0:0];

    // i_unnamed_c_compstr2869_join(BITJOIN,27754)@215
    assign i_unnamed_c_compstr2869_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2869_BitSelect_for_a_b};

    // i_unnamed_c_compstr2869_vt_select_0(BITSELECT,11430)@215
    assign i_unnamed_c_compstr2869_vt_select_0_b = i_unnamed_c_compstr2869_join_q[0:0];

    // redist109_i_unnamed_c_compstr2869_vt_select_0_b_1(DELAY,28337)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist109_i_unnamed_c_compstr2869_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2869_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2869_vt_join(BITJOIN,11429)@216
    assign i_unnamed_c_compstr2869_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist109_i_unnamed_c_compstr2869_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_101_c_compstr2870(ADD,6981)@216
    assign i_add_i_i_i_i_i_i_101_c_compstr2870_a = {1'b0, i_unnamed_c_compstr2869_vt_join_q};
    assign i_add_i_i_i_i_i_i_101_c_compstr2870_b = {1'b0, redist1151_i_conv_i_i_i_i_i_101_c_compstr2866_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_101_c_compstr2870_o = $unsigned(i_add_i_i_i_i_i_i_101_c_compstr2870_a) + $unsigned(i_add_i_i_i_i_i_i_101_c_compstr2870_b);
    assign i_add_i_i_i_i_i_i_101_c_compstr2870_q = i_add_i_i_i_i_i_i_101_c_compstr2870_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_101_c_compstr2870_sel_x(BITSELECT,2175)@216
    assign bgTrunc_i_add_i_i_i_i_i_i_101_c_compstr2870_sel_x_b = i_add_i_i_i_i_i_i_101_c_compstr2870_q[15:0];

    // i_conv_i_i_i_i_i_i279_102_c_compstr2890_sel_x(BITSELECT,3843)@216
    assign i_conv_i_i_i_i_i_i279_102_c_compstr2890_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_101_c_compstr2870_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_102_c_compstr2890_vt_select_15(BITSELECT,7889)@216
    assign i_conv_i_i_i_i_i_i279_102_c_compstr2890_vt_select_15_b = i_conv_i_i_i_i_i_i279_102_c_compstr2890_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_102_c_compstr2890_vt_join(BITJOIN,7888)@216
    assign i_conv_i_i_i_i_i_i279_102_c_compstr2890_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_102_c_compstr2890_vt_select_15_b};

    // leftShiftStage0_uid25196_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x(MUX,25195)@216
    assign leftShiftStage0_uid25196_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25196_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_102_c_compstr2890_vt_join_q or leftShiftStage0Idx1_uid25194_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25196_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25196_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_102_c_compstr2890_vt_join_q;
            1'b1 : leftShiftStage0_uid25196_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25194_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25196_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25201_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x(MUX,25200)@216
    assign leftShiftStage1_uid25201_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25201_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_s or leftShiftStage0_uid25196_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25199_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25201_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25201_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q = leftShiftStage0_uid25196_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25201_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25199_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25201_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25206_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x(MUX,25205)@216
    assign leftShiftStage2_uid25206_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25206_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_s or leftShiftStage1_uid25201_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25204_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25206_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25206_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q = leftShiftStage1_uid25201_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25206_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25204_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25206_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_102_c_compstr2891_vt_select_28(BITSELECT,9430)@216
    assign i_shl_i_i_i_i_i_i_102_c_compstr2891_vt_select_28_b = leftShiftStage2_uid25206_i_shl_i_i_i_i_i_i_102_c_compstr0_shift_x_q[28:13];

    // redist380_i_shl_i_i_i_i_i_i_102_c_compstr2891_vt_select_28_b_1(DELAY,28608)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist380_i_shl_i_i_i_i_i_i_102_c_compstr2891_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_102_c_compstr2891_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_102_c_compstr2891_vt_join(BITJOIN,9429)@217
    assign i_shl_i_i_i_i_i_i_102_c_compstr2891_vt_join_q = {redist380_i_shl_i_i_i_i_i_i_102_c_compstr2891_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_offset(CONSTANT,30762)
    assign redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_offset_q = $unsigned(8'b00111010);

    // redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_rdcnt(ADD,32211)
    assign redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_a = {1'b0, redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_wraddr_q};
    assign redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_b = {1'b0, redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_o <= $unsigned(redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_a) + $unsigned(redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_b);
        end
    end
    assign redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_q = redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_o[8:0];

    // redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_inputreg0(DELAY,32206)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl);
        end
    end

    // redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_wraddr(COUNTER,32209)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_wraddr_i <= $unsigned(redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_wraddr_q = redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_wraddr_i[7:0];

    // redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem(DUALMEM,32208)
    assign redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_ia = $unsigned(redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_inputreg0_q);
    assign redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_aa = redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_wraddr_q;
    assign redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_ab = redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_aa),
        .data_a(redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_ab),
        .q_b(redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_q = redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_iq[15:0];

    // redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_outputreg0(DELAY,32207)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_outputreg0_q <= $unsigned(redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_mem_q);
        end
    end

    // redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_rdcnt(ADD,30763)
    assign redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_a = {1'b0, redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_wraddr_q};
    assign redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_b = {1'b0, redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_o <= $unsigned(redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_a) + $unsigned(redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_b);
        end
    end
    assign redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_q = redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_o[8:0];

    // redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_inputreg0(DELAY,30758)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl);
        end
    end

    // redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_wraddr(COUNTER,30761)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_wraddr_i <= $unsigned(redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_wraddr_q = redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_wraddr_i[7:0];

    // redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem(DUALMEM,30760)
    assign redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_ia = $unsigned(redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_inputreg0_q);
    assign redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_aa = redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_wraddr_q;
    assign redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_ab = redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_aa),
        .data_a(redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_ab),
        .q_b(redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_q = redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_iq[15:0];

    // redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_outputreg0(DELAY,30759)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_outputreg0_q <= $unsigned(redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_mem_q);
        end
    end

    // redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_rdcnt(ADD,30769)
    assign redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_a = {1'b0, redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_wraddr_q};
    assign redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_b = {1'b0, redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_o <= $unsigned(redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_a) + $unsigned(redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_b);
        end
    end
    assign redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_q = redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_o[8:0];

    // redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_inputreg0(DELAY,30764)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl);
        end
    end

    // redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_wraddr(COUNTER,30767)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_wraddr_i <= $unsigned(redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_wraddr_q = redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_wraddr_i[7:0];

    // redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem(DUALMEM,30766)
    assign redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_ia = $unsigned(redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_inputreg0_q);
    assign redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_aa = redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_wraddr_q;
    assign redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_ab = redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_aa),
        .data_a(redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_ab),
        .q_b(redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_q = redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_iq[15:0];

    // redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_outputreg0(DELAY,30765)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_outputreg0_q <= $unsigned(redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_mem_q);
        end
    end

    // redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_rdcnt(ADD,32205)
    assign redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_a = {1'b0, redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_wraddr_q};
    assign redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_b = {1'b0, redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_o <= $unsigned(redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_a) + $unsigned(redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_b);
        end
    end
    assign redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_q = redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_o[8:0];

    // redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_inputreg0(DELAY,32200)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl);
        end
    end

    // redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_wraddr(COUNTER,32203)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_wraddr_i <= $unsigned(redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_wraddr_q = redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_wraddr_i[7:0];

    // redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem(DUALMEM,32202)
    assign redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_ia = $unsigned(redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_inputreg0_q);
    assign redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_aa = redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_wraddr_q;
    assign redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_ab = redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_aa),
        .data_a(redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_ab),
        .q_b(redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_q = redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_iq[15:0];

    // redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_outputreg0(DELAY,32201)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_outputreg0_q <= $unsigned(redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28063)@211 + 5
    // out q@217
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892(ADD,8524)@217
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod551_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_b = $unsigned({{5{i_shl_i_i_i_i_i_i_102_c_compstr2891_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_102_c_compstr2891_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_o[33:0];

    // rightShiftStage0_uid21293_dupName_409_i_unnamed_c_compstr0_shift_x(MUX,21292)@217
    assign rightShiftStage0_uid21293_dupName_409_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21293_dupName_409_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_q or rightShiftStage0Idx1_uid21291_dupName_409_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21293_dupName_409_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21293_dupName_409_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_q;
            1'b1 : rightShiftStage0_uid21293_dupName_409_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21291_dupName_409_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21293_dupName_409_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21298_dupName_409_i_unnamed_c_compstr0_shift_x(MUX,21297)@217
    assign rightShiftStage1_uid21298_dupName_409_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21298_dupName_409_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21293_dupName_409_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21296_dupName_409_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21298_dupName_409_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21298_dupName_409_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21293_dupName_409_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21298_dupName_409_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21296_dupName_409_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21298_dupName_409_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21303_dupName_409_i_unnamed_c_compstr0_shift_x(MUX,21302)@217
    assign rightShiftStage2_uid21303_dupName_409_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21303_dupName_409_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21298_dupName_409_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21301_dupName_409_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21303_dupName_409_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21303_dupName_409_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21298_dupName_409_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21303_dupName_409_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21301_dupName_409_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21303_dupName_409_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2893_vt_select_20(BITSELECT,11444)@217
    assign i_unnamed_c_compstr2893_vt_select_20_b = rightShiftStage2_uid21303_dupName_409_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2893_vt_join(BITJOIN,11443)@217
    assign i_unnamed_c_compstr2893_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2893_vt_select_20_b};

    // i_conv_i_i_i_i_i_102_c_compstr2894_sel_x(BITSELECT,3715)@217
    assign i_conv_i_i_i_i_i_102_c_compstr2894_sel_x_b = i_unnamed_c_compstr2893_vt_join_q[15:0];

    // redist1150_i_conv_i_i_i_i_i_102_c_compstr2894_sel_x_b_1(DELAY,29378)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1150_i_conv_i_i_i_i_i_102_c_compstr2894_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_102_c_compstr2894_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21312_dupName_410_i_unnamed_c_compstr0_shift_x(BITSELECT,21311)@217
    assign rightShiftStage1Idx1Rng8_uid21312_dupName_410_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21311_dupName_410_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21314_dupName_410_i_unnamed_c_compstr0_shift_x(BITJOIN,21313)@217
    assign rightShiftStage1Idx1_uid21314_dupName_410_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21312_dupName_410_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21307_dupName_410_i_unnamed_c_compstr0_shift_x(BITSELECT,21306)@217
    assign rightShiftStage0Idx1Rng4_uid21307_dupName_410_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_q[33:4];

    // rightShiftStage0Idx1_uid21309_dupName_410_i_unnamed_c_compstr0_shift_x(BITJOIN,21308)@217
    assign rightShiftStage0Idx1_uid21309_dupName_410_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21307_dupName_410_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21311_dupName_410_i_unnamed_c_compstr0_shift_x(MUX,21310)@217
    assign rightShiftStage0_uid21311_dupName_410_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21311_dupName_410_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_q or rightShiftStage0Idx1_uid21309_dupName_410_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21311_dupName_410_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21311_dupName_410_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compstr2892_q;
            1'b1 : rightShiftStage0_uid21311_dupName_410_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21309_dupName_410_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21311_dupName_410_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21316_dupName_410_i_unnamed_c_compstr0_shift_x(MUX,21315)@217
    assign rightShiftStage1_uid21316_dupName_410_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21316_dupName_410_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21311_dupName_410_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21314_dupName_410_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21316_dupName_410_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21316_dupName_410_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21311_dupName_410_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21316_dupName_410_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21314_dupName_410_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21316_dupName_410_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2895_vt_select_21(BITSELECT,11447)@217
    assign i_unnamed_c_compstr2895_vt_select_21_b = rightShiftStage1_uid21316_dupName_410_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2895_vt_join(BITJOIN,11446)@217
    assign i_unnamed_c_compstr2895_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2895_vt_select_21_b};

    // i_unnamed_c_compstr2896_sel_x(BITSELECT,6184)@217
    assign i_unnamed_c_compstr2896_sel_x_b = i_unnamed_c_compstr2895_vt_join_q[15:0];

    // i_unnamed_c_compstr2897_BitSelect_for_a(BITSELECT,27757)@217
    assign i_unnamed_c_compstr2897_BitSelect_for_a_b = i_unnamed_c_compstr2896_sel_x_b[0:0];

    // i_unnamed_c_compstr2897_join(BITJOIN,27758)@217
    assign i_unnamed_c_compstr2897_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2897_BitSelect_for_a_b};

    // i_unnamed_c_compstr2897_vt_select_0(BITSELECT,11452)@217
    assign i_unnamed_c_compstr2897_vt_select_0_b = i_unnamed_c_compstr2897_join_q[0:0];

    // redist107_i_unnamed_c_compstr2897_vt_select_0_b_1(DELAY,28335)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist107_i_unnamed_c_compstr2897_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2897_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2897_vt_join(BITJOIN,11451)@218
    assign i_unnamed_c_compstr2897_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist107_i_unnamed_c_compstr2897_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_102_c_compstr2898(ADD,6982)@218
    assign i_add_i_i_i_i_i_i_102_c_compstr2898_a = {1'b0, i_unnamed_c_compstr2897_vt_join_q};
    assign i_add_i_i_i_i_i_i_102_c_compstr2898_b = {1'b0, redist1150_i_conv_i_i_i_i_i_102_c_compstr2894_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_102_c_compstr2898_o = $unsigned(i_add_i_i_i_i_i_i_102_c_compstr2898_a) + $unsigned(i_add_i_i_i_i_i_i_102_c_compstr2898_b);
    assign i_add_i_i_i_i_i_i_102_c_compstr2898_q = i_add_i_i_i_i_i_i_102_c_compstr2898_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_102_c_compstr2898_sel_x(BITSELECT,2176)@218
    assign bgTrunc_i_add_i_i_i_i_i_i_102_c_compstr2898_sel_x_b = i_add_i_i_i_i_i_i_102_c_compstr2898_q[15:0];

    // i_conv_i_i_i_i_i_i279_103_c_compstr2918_sel_x(BITSELECT,3844)@218
    assign i_conv_i_i_i_i_i_i279_103_c_compstr2918_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_102_c_compstr2898_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_103_c_compstr2918_vt_select_15(BITSELECT,7893)@218
    assign i_conv_i_i_i_i_i_i279_103_c_compstr2918_vt_select_15_b = i_conv_i_i_i_i_i_i279_103_c_compstr2918_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_103_c_compstr2918_vt_join(BITJOIN,7892)@218
    assign i_conv_i_i_i_i_i_i279_103_c_compstr2918_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_103_c_compstr2918_vt_select_15_b};

    // leftShiftStage0_uid25214_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x(MUX,25213)@218
    assign leftShiftStage0_uid25214_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25214_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_103_c_compstr2918_vt_join_q or leftShiftStage0Idx1_uid25212_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25214_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25214_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_103_c_compstr2918_vt_join_q;
            1'b1 : leftShiftStage0_uid25214_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25212_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25214_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25219_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x(MUX,25218)@218
    assign leftShiftStage1_uid25219_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25219_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_s or leftShiftStage0_uid25214_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25217_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25219_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25219_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q = leftShiftStage0_uid25214_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25219_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25217_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25219_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25224_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x(MUX,25223)@218
    assign leftShiftStage2_uid25224_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25224_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_s or leftShiftStage1_uid25219_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25222_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25224_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25224_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q = leftShiftStage1_uid25219_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25224_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25222_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25224_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_103_c_compstr2919_vt_select_28(BITSELECT,9433)@218
    assign i_shl_i_i_i_i_i_i_103_c_compstr2919_vt_select_28_b = leftShiftStage2_uid25224_i_shl_i_i_i_i_i_i_103_c_compstr0_shift_x_q[28:13];

    // redist379_i_shl_i_i_i_i_i_i_103_c_compstr2919_vt_select_28_b_1(DELAY,28607)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist379_i_shl_i_i_i_i_i_i_103_c_compstr2919_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_103_c_compstr2919_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_103_c_compstr2919_vt_join(BITJOIN,9432)@219
    assign i_shl_i_i_i_i_i_i_103_c_compstr2919_vt_join_q = {redist379_i_shl_i_i_i_i_i_i_103_c_compstr2919_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_offset(CONSTANT,30774)
    assign redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_offset_q = $unsigned(8'b00111000);

    // redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_rdcnt(ADD,32223)
    assign redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_a = {1'b0, redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_wraddr_q};
    assign redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_b = {1'b0, redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_o <= $unsigned(redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_a) + $unsigned(redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_b);
        end
    end
    assign redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_q = redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_o[8:0];

    // redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_inputreg0(DELAY,32218)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl);
        end
    end

    // redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_wraddr(COUNTER,32221)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_wraddr_i <= $unsigned(redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_wraddr_q = redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_wraddr_i[7:0];

    // redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem(DUALMEM,32220)
    assign redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_ia = $unsigned(redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_inputreg0_q);
    assign redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_aa = redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_wraddr_q;
    assign redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_ab = redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_aa),
        .data_a(redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_ab),
        .q_b(redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_q = redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_iq[15:0];

    // redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_outputreg0(DELAY,32219)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_outputreg0_q <= $unsigned(redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_mem_q);
        end
    end

    // redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_rdcnt(ADD,30775)
    assign redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_a = {1'b0, redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_wraddr_q};
    assign redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_b = {1'b0, redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_o <= $unsigned(redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_a) + $unsigned(redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_b);
        end
    end
    assign redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_q = redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_o[8:0];

    // redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_inputreg0(DELAY,30770)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl);
        end
    end

    // redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_wraddr(COUNTER,30773)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_wraddr_i <= $unsigned(redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_wraddr_q = redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_wraddr_i[7:0];

    // redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem(DUALMEM,30772)
    assign redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_ia = $unsigned(redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_inputreg0_q);
    assign redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_aa = redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_wraddr_q;
    assign redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_ab = redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_aa),
        .data_a(redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_ab),
        .q_b(redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_q = redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_iq[15:0];

    // redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_outputreg0(DELAY,30771)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_outputreg0_q <= $unsigned(redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_mem_q);
        end
    end

    // redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_rdcnt(ADD,30781)
    assign redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_a = {1'b0, redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_wraddr_q};
    assign redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_b = {1'b0, redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_o <= $unsigned(redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_a) + $unsigned(redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_b);
        end
    end
    assign redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_q = redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_o[8:0];

    // redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_inputreg0(DELAY,30776)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl);
        end
    end

    // redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_wraddr(COUNTER,30779)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_wraddr_i <= $unsigned(redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_wraddr_q = redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_wraddr_i[7:0];

    // redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem(DUALMEM,30778)
    assign redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_ia = $unsigned(redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_inputreg0_q);
    assign redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_aa = redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_wraddr_q;
    assign redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_ab = redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_aa),
        .data_a(redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_ab),
        .q_b(redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_q = redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_iq[15:0];

    // redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_outputreg0(DELAY,30777)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_outputreg0_q <= $unsigned(redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_mem_q);
        end
    end

    // redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_rdcnt(ADD,32217)
    assign redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_a = {1'b0, redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_wraddr_q};
    assign redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_b = {1'b0, redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_o <= $unsigned(redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_a) + $unsigned(redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_b);
        end
    end
    assign redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_q = redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_o[8:0];

    // redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_inputreg0(DELAY,32212)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl);
        end
    end

    // redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_wraddr(COUNTER,32215)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_wraddr_i <= $unsigned(redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_wraddr_q = redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_wraddr_i[7:0];

    // redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem(DUALMEM,32214)
    assign redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_ia = $unsigned(redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_inputreg0_q);
    assign redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_aa = redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_wraddr_q;
    assign redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_ab = redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_aa),
        .data_a(redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_ab),
        .q_b(redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_q = redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_iq[15:0];

    // redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_outputreg0(DELAY,32213)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_outputreg0_q <= $unsigned(redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28064)@213 + 5
    // out q@219
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920(ADD,8525)@219
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod556_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_b = $unsigned({{5{i_shl_i_i_i_i_i_i_103_c_compstr2919_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_103_c_compstr2919_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_o[33:0];

    // rightShiftStage0_uid21355_dupName_413_i_unnamed_c_compstr0_shift_x(MUX,21354)@219
    assign rightShiftStage0_uid21355_dupName_413_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21355_dupName_413_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_q or rightShiftStage0Idx1_uid21353_dupName_413_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21355_dupName_413_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21355_dupName_413_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_q;
            1'b1 : rightShiftStage0_uid21355_dupName_413_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21353_dupName_413_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21355_dupName_413_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21360_dupName_413_i_unnamed_c_compstr0_shift_x(MUX,21359)@219
    assign rightShiftStage1_uid21360_dupName_413_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21360_dupName_413_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21355_dupName_413_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21358_dupName_413_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21360_dupName_413_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21360_dupName_413_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21355_dupName_413_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21360_dupName_413_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21358_dupName_413_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21360_dupName_413_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21365_dupName_413_i_unnamed_c_compstr0_shift_x(MUX,21364)@219
    assign rightShiftStage2_uid21365_dupName_413_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21365_dupName_413_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21360_dupName_413_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21363_dupName_413_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21365_dupName_413_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21365_dupName_413_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21360_dupName_413_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21365_dupName_413_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21363_dupName_413_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21365_dupName_413_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2921_vt_select_20(BITSELECT,11472)@219
    assign i_unnamed_c_compstr2921_vt_select_20_b = rightShiftStage2_uid21365_dupName_413_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2921_vt_join(BITJOIN,11471)@219
    assign i_unnamed_c_compstr2921_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2921_vt_select_20_b};

    // i_conv_i_i_i_i_i_103_c_compstr2922_sel_x(BITSELECT,3716)@219
    assign i_conv_i_i_i_i_i_103_c_compstr2922_sel_x_b = i_unnamed_c_compstr2921_vt_join_q[15:0];

    // redist1149_i_conv_i_i_i_i_i_103_c_compstr2922_sel_x_b_1(DELAY,29377)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1149_i_conv_i_i_i_i_i_103_c_compstr2922_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_103_c_compstr2922_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21374_dupName_414_i_unnamed_c_compstr0_shift_x(BITSELECT,21373)@219
    assign rightShiftStage1Idx1Rng8_uid21374_dupName_414_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21373_dupName_414_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21376_dupName_414_i_unnamed_c_compstr0_shift_x(BITJOIN,21375)@219
    assign rightShiftStage1Idx1_uid21376_dupName_414_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21374_dupName_414_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21369_dupName_414_i_unnamed_c_compstr0_shift_x(BITSELECT,21368)@219
    assign rightShiftStage0Idx1Rng4_uid21369_dupName_414_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_q[33:4];

    // rightShiftStage0Idx1_uid21371_dupName_414_i_unnamed_c_compstr0_shift_x(BITJOIN,21370)@219
    assign rightShiftStage0Idx1_uid21371_dupName_414_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21369_dupName_414_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21373_dupName_414_i_unnamed_c_compstr0_shift_x(MUX,21372)@219
    assign rightShiftStage0_uid21373_dupName_414_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21373_dupName_414_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_q or rightShiftStage0Idx1_uid21371_dupName_414_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21373_dupName_414_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21373_dupName_414_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compstr2920_q;
            1'b1 : rightShiftStage0_uid21373_dupName_414_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21371_dupName_414_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21373_dupName_414_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21378_dupName_414_i_unnamed_c_compstr0_shift_x(MUX,21377)@219
    assign rightShiftStage1_uid21378_dupName_414_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21378_dupName_414_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21373_dupName_414_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21376_dupName_414_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21378_dupName_414_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21378_dupName_414_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21373_dupName_414_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21378_dupName_414_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21376_dupName_414_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21378_dupName_414_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2923_vt_select_21(BITSELECT,11475)@219
    assign i_unnamed_c_compstr2923_vt_select_21_b = rightShiftStage1_uid21378_dupName_414_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2923_vt_join(BITJOIN,11474)@219
    assign i_unnamed_c_compstr2923_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2923_vt_select_21_b};

    // i_unnamed_c_compstr2924_sel_x(BITSELECT,6187)@219
    assign i_unnamed_c_compstr2924_sel_x_b = i_unnamed_c_compstr2923_vt_join_q[15:0];

    // i_unnamed_c_compstr2925_BitSelect_for_a(BITSELECT,27761)@219
    assign i_unnamed_c_compstr2925_BitSelect_for_a_b = i_unnamed_c_compstr2924_sel_x_b[0:0];

    // i_unnamed_c_compstr2925_join(BITJOIN,27762)@219
    assign i_unnamed_c_compstr2925_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2925_BitSelect_for_a_b};

    // i_unnamed_c_compstr2925_vt_select_0(BITSELECT,11480)@219
    assign i_unnamed_c_compstr2925_vt_select_0_b = i_unnamed_c_compstr2925_join_q[0:0];

    // redist105_i_unnamed_c_compstr2925_vt_select_0_b_1(DELAY,28333)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist105_i_unnamed_c_compstr2925_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2925_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2925_vt_join(BITJOIN,11479)@220
    assign i_unnamed_c_compstr2925_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist105_i_unnamed_c_compstr2925_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_103_c_compstr2926(ADD,6983)@220
    assign i_add_i_i_i_i_i_i_103_c_compstr2926_a = {1'b0, i_unnamed_c_compstr2925_vt_join_q};
    assign i_add_i_i_i_i_i_i_103_c_compstr2926_b = {1'b0, redist1149_i_conv_i_i_i_i_i_103_c_compstr2922_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_103_c_compstr2926_o = $unsigned(i_add_i_i_i_i_i_i_103_c_compstr2926_a) + $unsigned(i_add_i_i_i_i_i_i_103_c_compstr2926_b);
    assign i_add_i_i_i_i_i_i_103_c_compstr2926_q = i_add_i_i_i_i_i_i_103_c_compstr2926_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_103_c_compstr2926_sel_x(BITSELECT,2177)@220
    assign bgTrunc_i_add_i_i_i_i_i_i_103_c_compstr2926_sel_x_b = i_add_i_i_i_i_i_i_103_c_compstr2926_q[15:0];

    // i_conv_i_i_i_i_i_i279_104_c_compstr2946_sel_x(BITSELECT,3845)@220
    assign i_conv_i_i_i_i_i_i279_104_c_compstr2946_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_103_c_compstr2926_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_104_c_compstr2946_vt_select_15(BITSELECT,7897)@220
    assign i_conv_i_i_i_i_i_i279_104_c_compstr2946_vt_select_15_b = i_conv_i_i_i_i_i_i279_104_c_compstr2946_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_104_c_compstr2946_vt_join(BITJOIN,7896)@220
    assign i_conv_i_i_i_i_i_i279_104_c_compstr2946_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_104_c_compstr2946_vt_select_15_b};

    // leftShiftStage0_uid25232_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x(MUX,25231)@220
    assign leftShiftStage0_uid25232_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25232_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_104_c_compstr2946_vt_join_q or leftShiftStage0Idx1_uid25230_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25232_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25232_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_104_c_compstr2946_vt_join_q;
            1'b1 : leftShiftStage0_uid25232_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25230_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25232_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25237_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x(MUX,25236)@220
    assign leftShiftStage1_uid25237_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25237_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_s or leftShiftStage0_uid25232_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25235_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25237_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25237_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q = leftShiftStage0_uid25232_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25237_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25235_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25237_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25242_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x(MUX,25241)@220
    assign leftShiftStage2_uid25242_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25242_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_s or leftShiftStage1_uid25237_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25240_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25242_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25242_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q = leftShiftStage1_uid25237_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25242_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25240_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25242_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_104_c_compstr2947_vt_select_28(BITSELECT,9436)@220
    assign i_shl_i_i_i_i_i_i_104_c_compstr2947_vt_select_28_b = leftShiftStage2_uid25242_i_shl_i_i_i_i_i_i_104_c_compstr0_shift_x_q[28:13];

    // redist378_i_shl_i_i_i_i_i_i_104_c_compstr2947_vt_select_28_b_1(DELAY,28606)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist378_i_shl_i_i_i_i_i_i_104_c_compstr2947_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_104_c_compstr2947_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_104_c_compstr2947_vt_join(BITJOIN,9435)@221
    assign i_shl_i_i_i_i_i_i_104_c_compstr2947_vt_join_q = {redist378_i_shl_i_i_i_i_i_i_104_c_compstr2947_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_offset(CONSTANT,30786)
    assign redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_offset_q = $unsigned(8'b00110110);

    // redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_rdcnt(ADD,32235)
    assign redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_a = {1'b0, redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_wraddr_q};
    assign redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_b = {1'b0, redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_o <= $unsigned(redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_a) + $unsigned(redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_b);
        end
    end
    assign redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_q = redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_o[8:0];

    // redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_inputreg0(DELAY,32230)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl);
        end
    end

    // redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_wraddr(COUNTER,32233)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_wraddr_i <= $unsigned(redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_wraddr_q = redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_wraddr_i[7:0];

    // redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem(DUALMEM,32232)
    assign redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_ia = $unsigned(redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_inputreg0_q);
    assign redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_aa = redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_wraddr_q;
    assign redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_ab = redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_aa),
        .data_a(redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_ab),
        .q_b(redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_q = redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_iq[15:0];

    // redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_outputreg0(DELAY,32231)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_outputreg0_q <= $unsigned(redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_mem_q);
        end
    end

    // redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_rdcnt(ADD,30787)
    assign redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_a = {1'b0, redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_wraddr_q};
    assign redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_b = {1'b0, redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_o <= $unsigned(redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_a) + $unsigned(redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_b);
        end
    end
    assign redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_q = redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_o[8:0];

    // redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_inputreg0(DELAY,30782)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl);
        end
    end

    // redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_wraddr(COUNTER,30785)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_wraddr_i <= $unsigned(redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_wraddr_q = redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_wraddr_i[7:0];

    // redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem(DUALMEM,30784)
    assign redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_ia = $unsigned(redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_inputreg0_q);
    assign redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_aa = redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_wraddr_q;
    assign redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_ab = redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_aa),
        .data_a(redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_ab),
        .q_b(redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_q = redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_iq[15:0];

    // redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_outputreg0(DELAY,30783)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_outputreg0_q <= $unsigned(redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_mem_q);
        end
    end

    // redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_rdcnt(ADD,30793)
    assign redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_a = {1'b0, redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_wraddr_q};
    assign redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_b = {1'b0, redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_o <= $unsigned(redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_a) + $unsigned(redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_b);
        end
    end
    assign redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_q = redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_o[8:0];

    // redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_inputreg0(DELAY,30788)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl);
        end
    end

    // redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_wraddr(COUNTER,30791)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_wraddr_i <= $unsigned(redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_wraddr_q = redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_wraddr_i[7:0];

    // redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem(DUALMEM,30790)
    assign redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_ia = $unsigned(redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_inputreg0_q);
    assign redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_aa = redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_wraddr_q;
    assign redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_ab = redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_aa),
        .data_a(redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_ab),
        .q_b(redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_q = redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_iq[15:0];

    // redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_outputreg0(DELAY,30789)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_outputreg0_q <= $unsigned(redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_mem_q);
        end
    end

    // redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_rdcnt(ADD,32229)
    assign redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_a = {1'b0, redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_wraddr_q};
    assign redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_b = {1'b0, redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_o <= $unsigned(redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_a) + $unsigned(redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_b);
        end
    end
    assign redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_q = redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_o[8:0];

    // redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_inputreg0(DELAY,32224)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl);
        end
    end

    // redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_wraddr(COUNTER,32227)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_wraddr_i <= $unsigned(redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_wraddr_q = redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_wraddr_i[7:0];

    // redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem(DUALMEM,32226)
    assign redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_ia = $unsigned(redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_inputreg0_q);
    assign redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_aa = redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_wraddr_q;
    assign redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_ab = redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_aa),
        .data_a(redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_ab),
        .q_b(redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_q = redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_iq[15:0];

    // redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_outputreg0(DELAY,32225)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_outputreg0_q <= $unsigned(redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28065)@215 + 5
    // out q@221
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948(ADD,8526)@221
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod561_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_b = $unsigned({{5{i_shl_i_i_i_i_i_i_104_c_compstr2947_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_104_c_compstr2947_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_o[33:0];

    // rightShiftStage0_uid21417_dupName_417_i_unnamed_c_compstr0_shift_x(MUX,21416)@221
    assign rightShiftStage0_uid21417_dupName_417_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21417_dupName_417_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_q or rightShiftStage0Idx1_uid21415_dupName_417_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21417_dupName_417_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21417_dupName_417_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_q;
            1'b1 : rightShiftStage0_uid21417_dupName_417_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21415_dupName_417_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21417_dupName_417_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21422_dupName_417_i_unnamed_c_compstr0_shift_x(MUX,21421)@221
    assign rightShiftStage1_uid21422_dupName_417_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21422_dupName_417_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21417_dupName_417_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21420_dupName_417_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21422_dupName_417_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21422_dupName_417_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21417_dupName_417_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21422_dupName_417_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21420_dupName_417_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21422_dupName_417_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21427_dupName_417_i_unnamed_c_compstr0_shift_x(MUX,21426)@221
    assign rightShiftStage2_uid21427_dupName_417_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21427_dupName_417_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21422_dupName_417_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21425_dupName_417_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21427_dupName_417_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21427_dupName_417_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21422_dupName_417_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21427_dupName_417_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21425_dupName_417_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21427_dupName_417_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2949_vt_select_20(BITSELECT,11499)@221
    assign i_unnamed_c_compstr2949_vt_select_20_b = rightShiftStage2_uid21427_dupName_417_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2949_vt_join(BITJOIN,11498)@221
    assign i_unnamed_c_compstr2949_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2949_vt_select_20_b};

    // i_conv_i_i_i_i_i_104_c_compstr2950_sel_x(BITSELECT,3717)@221
    assign i_conv_i_i_i_i_i_104_c_compstr2950_sel_x_b = i_unnamed_c_compstr2949_vt_join_q[15:0];

    // redist1148_i_conv_i_i_i_i_i_104_c_compstr2950_sel_x_b_1(DELAY,29376)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1148_i_conv_i_i_i_i_i_104_c_compstr2950_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_104_c_compstr2950_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21436_dupName_418_i_unnamed_c_compstr0_shift_x(BITSELECT,21435)@221
    assign rightShiftStage1Idx1Rng8_uid21436_dupName_418_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21435_dupName_418_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21438_dupName_418_i_unnamed_c_compstr0_shift_x(BITJOIN,21437)@221
    assign rightShiftStage1Idx1_uid21438_dupName_418_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21436_dupName_418_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21431_dupName_418_i_unnamed_c_compstr0_shift_x(BITSELECT,21430)@221
    assign rightShiftStage0Idx1Rng4_uid21431_dupName_418_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_q[33:4];

    // rightShiftStage0Idx1_uid21433_dupName_418_i_unnamed_c_compstr0_shift_x(BITJOIN,21432)@221
    assign rightShiftStage0Idx1_uid21433_dupName_418_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21431_dupName_418_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21435_dupName_418_i_unnamed_c_compstr0_shift_x(MUX,21434)@221
    assign rightShiftStage0_uid21435_dupName_418_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21435_dupName_418_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_q or rightShiftStage0Idx1_uid21433_dupName_418_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21435_dupName_418_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21435_dupName_418_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compstr2948_q;
            1'b1 : rightShiftStage0_uid21435_dupName_418_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21433_dupName_418_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21435_dupName_418_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21440_dupName_418_i_unnamed_c_compstr0_shift_x(MUX,21439)@221
    assign rightShiftStage1_uid21440_dupName_418_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21440_dupName_418_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21435_dupName_418_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21438_dupName_418_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21440_dupName_418_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21440_dupName_418_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21435_dupName_418_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21440_dupName_418_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21438_dupName_418_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21440_dupName_418_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2951_vt_select_21(BITSELECT,11502)@221
    assign i_unnamed_c_compstr2951_vt_select_21_b = rightShiftStage1_uid21440_dupName_418_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2951_vt_join(BITJOIN,11501)@221
    assign i_unnamed_c_compstr2951_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2951_vt_select_21_b};

    // i_unnamed_c_compstr2952_sel_x(BITSELECT,6189)@221
    assign i_unnamed_c_compstr2952_sel_x_b = i_unnamed_c_compstr2951_vt_join_q[15:0];

    // i_unnamed_c_compstr2953_BitSelect_for_a(BITSELECT,27767)@221
    assign i_unnamed_c_compstr2953_BitSelect_for_a_b = i_unnamed_c_compstr2952_sel_x_b[0:0];

    // i_unnamed_c_compstr2953_join(BITJOIN,27768)@221
    assign i_unnamed_c_compstr2953_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2953_BitSelect_for_a_b};

    // i_unnamed_c_compstr2953_vt_select_0(BITSELECT,11507)@221
    assign i_unnamed_c_compstr2953_vt_select_0_b = i_unnamed_c_compstr2953_join_q[0:0];

    // redist102_i_unnamed_c_compstr2953_vt_select_0_b_1(DELAY,28330)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist102_i_unnamed_c_compstr2953_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2953_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2953_vt_join(BITJOIN,11506)@222
    assign i_unnamed_c_compstr2953_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist102_i_unnamed_c_compstr2953_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_104_c_compstr2954(ADD,6984)@222
    assign i_add_i_i_i_i_i_i_104_c_compstr2954_a = {1'b0, i_unnamed_c_compstr2953_vt_join_q};
    assign i_add_i_i_i_i_i_i_104_c_compstr2954_b = {1'b0, redist1148_i_conv_i_i_i_i_i_104_c_compstr2950_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_104_c_compstr2954_o = $unsigned(i_add_i_i_i_i_i_i_104_c_compstr2954_a) + $unsigned(i_add_i_i_i_i_i_i_104_c_compstr2954_b);
    assign i_add_i_i_i_i_i_i_104_c_compstr2954_q = i_add_i_i_i_i_i_i_104_c_compstr2954_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_104_c_compstr2954_sel_x(BITSELECT,2178)@222
    assign bgTrunc_i_add_i_i_i_i_i_i_104_c_compstr2954_sel_x_b = i_add_i_i_i_i_i_i_104_c_compstr2954_q[15:0];

    // i_conv_i_i_i_i_i_i279_105_c_compstr2974_sel_x(BITSELECT,3846)@222
    assign i_conv_i_i_i_i_i_i279_105_c_compstr2974_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_104_c_compstr2954_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_105_c_compstr2974_vt_select_15(BITSELECT,7901)@222
    assign i_conv_i_i_i_i_i_i279_105_c_compstr2974_vt_select_15_b = i_conv_i_i_i_i_i_i279_105_c_compstr2974_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_105_c_compstr2974_vt_join(BITJOIN,7900)@222
    assign i_conv_i_i_i_i_i_i279_105_c_compstr2974_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_105_c_compstr2974_vt_select_15_b};

    // leftShiftStage0_uid25250_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x(MUX,25249)@222
    assign leftShiftStage0_uid25250_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25250_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_105_c_compstr2974_vt_join_q or leftShiftStage0Idx1_uid25248_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25250_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25250_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_105_c_compstr2974_vt_join_q;
            1'b1 : leftShiftStage0_uid25250_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25248_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25250_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25255_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x(MUX,25254)@222
    assign leftShiftStage1_uid25255_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25255_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_s or leftShiftStage0_uid25250_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25253_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25255_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25255_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q = leftShiftStage0_uid25250_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25255_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25253_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25255_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25260_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x(MUX,25259)@222
    assign leftShiftStage2_uid25260_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25260_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_s or leftShiftStage1_uid25255_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25258_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25260_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25260_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q = leftShiftStage1_uid25255_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25260_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25258_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25260_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_105_c_compstr2975_vt_select_28(BITSELECT,9439)@222
    assign i_shl_i_i_i_i_i_i_105_c_compstr2975_vt_select_28_b = leftShiftStage2_uid25260_i_shl_i_i_i_i_i_i_105_c_compstr0_shift_x_q[28:13];

    // redist377_i_shl_i_i_i_i_i_i_105_c_compstr2975_vt_select_28_b_1(DELAY,28605)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist377_i_shl_i_i_i_i_i_i_105_c_compstr2975_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_105_c_compstr2975_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_105_c_compstr2975_vt_join(BITJOIN,9438)@223
    assign i_shl_i_i_i_i_i_i_105_c_compstr2975_vt_join_q = {redist377_i_shl_i_i_i_i_i_i_105_c_compstr2975_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_offset(CONSTANT,30798)
    assign redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_offset_q = $unsigned(8'b00110100);

    // redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_rdcnt(ADD,32247)
    assign redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_a = {1'b0, redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_wraddr_q};
    assign redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_b = {1'b0, redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_o <= $unsigned(redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_a) + $unsigned(redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_b);
        end
    end
    assign redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_q = redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_o[8:0];

    // redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_inputreg0(DELAY,32242)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl);
        end
    end

    // redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_wraddr(COUNTER,32245)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_wraddr_i <= $unsigned(redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_wraddr_q = redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_wraddr_i[7:0];

    // redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem(DUALMEM,32244)
    assign redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_ia = $unsigned(redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_inputreg0_q);
    assign redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_aa = redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_wraddr_q;
    assign redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_ab = redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_aa),
        .data_a(redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_ab),
        .q_b(redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_q = redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_iq[15:0];

    // redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_outputreg0(DELAY,32243)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_outputreg0_q <= $unsigned(redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_mem_q);
        end
    end

    // redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_rdcnt(ADD,30799)
    assign redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_a = {1'b0, redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_wraddr_q};
    assign redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_b = {1'b0, redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_o <= $unsigned(redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_a) + $unsigned(redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_b);
        end
    end
    assign redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_q = redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_o[8:0];

    // redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_inputreg0(DELAY,30794)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl);
        end
    end

    // redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_wraddr(COUNTER,30797)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_wraddr_i <= $unsigned(redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_wraddr_q = redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_wraddr_i[7:0];

    // redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem(DUALMEM,30796)
    assign redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_ia = $unsigned(redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_inputreg0_q);
    assign redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_aa = redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_wraddr_q;
    assign redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_ab = redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_aa),
        .data_a(redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_ab),
        .q_b(redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_q = redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_iq[15:0];

    // redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_outputreg0(DELAY,30795)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_outputreg0_q <= $unsigned(redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_mem_q);
        end
    end

    // redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_rdcnt(ADD,30805)
    assign redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_a = {1'b0, redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_wraddr_q};
    assign redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_b = {1'b0, redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_o <= $unsigned(redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_a) + $unsigned(redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_b);
        end
    end
    assign redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_q = redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_o[8:0];

    // redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_inputreg0(DELAY,30800)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl);
        end
    end

    // redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_wraddr(COUNTER,30803)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_wraddr_i <= $unsigned(redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_wraddr_q = redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_wraddr_i[7:0];

    // redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem(DUALMEM,30802)
    assign redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_ia = $unsigned(redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_inputreg0_q);
    assign redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_aa = redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_wraddr_q;
    assign redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_ab = redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_aa),
        .data_a(redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_ab),
        .q_b(redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_q = redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_iq[15:0];

    // redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_outputreg0(DELAY,30801)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_outputreg0_q <= $unsigned(redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_mem_q);
        end
    end

    // redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_rdcnt(ADD,32241)
    assign redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_a = {1'b0, redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_wraddr_q};
    assign redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_b = {1'b0, redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_o <= $unsigned(redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_a) + $unsigned(redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_b);
        end
    end
    assign redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_q = redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_o[8:0];

    // redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_inputreg0(DELAY,32236)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl);
        end
    end

    // redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_wraddr(COUNTER,32239)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_wraddr_i <= $unsigned(redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_wraddr_q = redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_wraddr_i[7:0];

    // redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem(DUALMEM,32238)
    assign redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_ia = $unsigned(redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_inputreg0_q);
    assign redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_aa = redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_wraddr_q;
    assign redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_ab = redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_aa),
        .data_a(redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_ab),
        .q_b(redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_q = redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_iq[15:0];

    // redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_outputreg0(DELAY,32237)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_outputreg0_q <= $unsigned(redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28066)@217 + 5
    // out q@223
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976(ADD,8527)@223
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod566_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_b = $unsigned({{5{i_shl_i_i_i_i_i_i_105_c_compstr2975_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_105_c_compstr2975_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_o[33:0];

    // rightShiftStage0_uid21479_dupName_421_i_unnamed_c_compstr0_shift_x(MUX,21478)@223
    assign rightShiftStage0_uid21479_dupName_421_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21479_dupName_421_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_q or rightShiftStage0Idx1_uid21477_dupName_421_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21479_dupName_421_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21479_dupName_421_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_q;
            1'b1 : rightShiftStage0_uid21479_dupName_421_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21477_dupName_421_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21479_dupName_421_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21484_dupName_421_i_unnamed_c_compstr0_shift_x(MUX,21483)@223
    assign rightShiftStage1_uid21484_dupName_421_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21484_dupName_421_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21479_dupName_421_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21482_dupName_421_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21484_dupName_421_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21484_dupName_421_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21479_dupName_421_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21484_dupName_421_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21482_dupName_421_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21484_dupName_421_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21489_dupName_421_i_unnamed_c_compstr0_shift_x(MUX,21488)@223
    assign rightShiftStage2_uid21489_dupName_421_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21489_dupName_421_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21484_dupName_421_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21487_dupName_421_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21489_dupName_421_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21489_dupName_421_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21484_dupName_421_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21489_dupName_421_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21487_dupName_421_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21489_dupName_421_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2977_vt_select_20(BITSELECT,11521)@223
    assign i_unnamed_c_compstr2977_vt_select_20_b = rightShiftStage2_uid21489_dupName_421_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2977_vt_join(BITJOIN,11520)@223
    assign i_unnamed_c_compstr2977_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2977_vt_select_20_b};

    // i_conv_i_i_i_i_i_105_c_compstr2978_sel_x(BITSELECT,3718)@223
    assign i_conv_i_i_i_i_i_105_c_compstr2978_sel_x_b = i_unnamed_c_compstr2977_vt_join_q[15:0];

    // redist1147_i_conv_i_i_i_i_i_105_c_compstr2978_sel_x_b_1(DELAY,29375)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1147_i_conv_i_i_i_i_i_105_c_compstr2978_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_105_c_compstr2978_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21498_dupName_422_i_unnamed_c_compstr0_shift_x(BITSELECT,21497)@223
    assign rightShiftStage1Idx1Rng8_uid21498_dupName_422_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21497_dupName_422_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21500_dupName_422_i_unnamed_c_compstr0_shift_x(BITJOIN,21499)@223
    assign rightShiftStage1Idx1_uid21500_dupName_422_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21498_dupName_422_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21493_dupName_422_i_unnamed_c_compstr0_shift_x(BITSELECT,21492)@223
    assign rightShiftStage0Idx1Rng4_uid21493_dupName_422_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_q[33:4];

    // rightShiftStage0Idx1_uid21495_dupName_422_i_unnamed_c_compstr0_shift_x(BITJOIN,21494)@223
    assign rightShiftStage0Idx1_uid21495_dupName_422_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21493_dupName_422_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21497_dupName_422_i_unnamed_c_compstr0_shift_x(MUX,21496)@223
    assign rightShiftStage0_uid21497_dupName_422_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21497_dupName_422_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_q or rightShiftStage0Idx1_uid21495_dupName_422_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21497_dupName_422_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21497_dupName_422_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compstr2976_q;
            1'b1 : rightShiftStage0_uid21497_dupName_422_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21495_dupName_422_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21497_dupName_422_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21502_dupName_422_i_unnamed_c_compstr0_shift_x(MUX,21501)@223
    assign rightShiftStage1_uid21502_dupName_422_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21502_dupName_422_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21497_dupName_422_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21500_dupName_422_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21502_dupName_422_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21502_dupName_422_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21497_dupName_422_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21502_dupName_422_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21500_dupName_422_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21502_dupName_422_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2979_vt_select_21(BITSELECT,11524)@223
    assign i_unnamed_c_compstr2979_vt_select_21_b = rightShiftStage1_uid21502_dupName_422_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2979_vt_join(BITJOIN,11523)@223
    assign i_unnamed_c_compstr2979_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2979_vt_select_21_b};

    // i_unnamed_c_compstr2980_sel_x(BITSELECT,6191)@223
    assign i_unnamed_c_compstr2980_sel_x_b = i_unnamed_c_compstr2979_vt_join_q[15:0];

    // i_unnamed_c_compstr2981_BitSelect_for_a(BITSELECT,27771)@223
    assign i_unnamed_c_compstr2981_BitSelect_for_a_b = i_unnamed_c_compstr2980_sel_x_b[0:0];

    // i_unnamed_c_compstr2981_join(BITJOIN,27772)@223
    assign i_unnamed_c_compstr2981_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2981_BitSelect_for_a_b};

    // i_unnamed_c_compstr2981_vt_select_0(BITSELECT,11529)@223
    assign i_unnamed_c_compstr2981_vt_select_0_b = i_unnamed_c_compstr2981_join_q[0:0];

    // redist100_i_unnamed_c_compstr2981_vt_select_0_b_1(DELAY,28328)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist100_i_unnamed_c_compstr2981_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2981_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2981_vt_join(BITJOIN,11528)@224
    assign i_unnamed_c_compstr2981_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist100_i_unnamed_c_compstr2981_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_105_c_compstr2982(ADD,6985)@224
    assign i_add_i_i_i_i_i_i_105_c_compstr2982_a = {1'b0, i_unnamed_c_compstr2981_vt_join_q};
    assign i_add_i_i_i_i_i_i_105_c_compstr2982_b = {1'b0, redist1147_i_conv_i_i_i_i_i_105_c_compstr2978_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_105_c_compstr2982_o = $unsigned(i_add_i_i_i_i_i_i_105_c_compstr2982_a) + $unsigned(i_add_i_i_i_i_i_i_105_c_compstr2982_b);
    assign i_add_i_i_i_i_i_i_105_c_compstr2982_q = i_add_i_i_i_i_i_i_105_c_compstr2982_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_105_c_compstr2982_sel_x(BITSELECT,2179)@224
    assign bgTrunc_i_add_i_i_i_i_i_i_105_c_compstr2982_sel_x_b = i_add_i_i_i_i_i_i_105_c_compstr2982_q[15:0];

    // i_conv_i_i_i_i_i_i279_106_c_compstr3002_sel_x(BITSELECT,3847)@224
    assign i_conv_i_i_i_i_i_i279_106_c_compstr3002_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_105_c_compstr2982_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_106_c_compstr3002_vt_select_15(BITSELECT,7905)@224
    assign i_conv_i_i_i_i_i_i279_106_c_compstr3002_vt_select_15_b = i_conv_i_i_i_i_i_i279_106_c_compstr3002_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_106_c_compstr3002_vt_join(BITJOIN,7904)@224
    assign i_conv_i_i_i_i_i_i279_106_c_compstr3002_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_106_c_compstr3002_vt_select_15_b};

    // leftShiftStage0_uid25268_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x(MUX,25267)@224
    assign leftShiftStage0_uid25268_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25268_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_106_c_compstr3002_vt_join_q or leftShiftStage0Idx1_uid25266_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25268_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25268_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_106_c_compstr3002_vt_join_q;
            1'b1 : leftShiftStage0_uid25268_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25266_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25268_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25273_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x(MUX,25272)@224
    assign leftShiftStage1_uid25273_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25273_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_s or leftShiftStage0_uid25268_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25271_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25273_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25273_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q = leftShiftStage0_uid25268_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25273_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25271_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25273_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25278_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x(MUX,25277)@224
    assign leftShiftStage2_uid25278_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25278_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_s or leftShiftStage1_uid25273_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25276_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25278_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25278_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q = leftShiftStage1_uid25273_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25278_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25276_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25278_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_106_c_compstr3003_vt_select_28(BITSELECT,9442)@224
    assign i_shl_i_i_i_i_i_i_106_c_compstr3003_vt_select_28_b = leftShiftStage2_uid25278_i_shl_i_i_i_i_i_i_106_c_compstr0_shift_x_q[28:13];

    // redist376_i_shl_i_i_i_i_i_i_106_c_compstr3003_vt_select_28_b_1(DELAY,28604)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist376_i_shl_i_i_i_i_i_i_106_c_compstr3003_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_106_c_compstr3003_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_106_c_compstr3003_vt_join(BITJOIN,9441)@225
    assign i_shl_i_i_i_i_i_i_106_c_compstr3003_vt_join_q = {redist376_i_shl_i_i_i_i_i_i_106_c_compstr3003_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_offset(CONSTANT,30810)
    assign redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_offset_q = $unsigned(8'b00110010);

    // redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_rdcnt(ADD,32259)
    assign redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_a = {1'b0, redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_wraddr_q};
    assign redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_b = {1'b0, redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_o <= $unsigned(redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_a) + $unsigned(redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_b);
        end
    end
    assign redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_q = redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_o[8:0];

    // redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_inputreg0(DELAY,32254)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl);
        end
    end

    // redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_wraddr(COUNTER,32257)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_wraddr_i <= $unsigned(redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_wraddr_q = redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_wraddr_i[7:0];

    // redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem(DUALMEM,32256)
    assign redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_ia = $unsigned(redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_inputreg0_q);
    assign redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_aa = redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_wraddr_q;
    assign redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_ab = redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_aa),
        .data_a(redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_ab),
        .q_b(redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_q = redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_iq[15:0];

    // redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_outputreg0(DELAY,32255)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_outputreg0_q <= $unsigned(redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_mem_q);
        end
    end

    // redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_rdcnt(ADD,30811)
    assign redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_a = {1'b0, redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_wraddr_q};
    assign redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_b = {1'b0, redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_o <= $unsigned(redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_a) + $unsigned(redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_b);
        end
    end
    assign redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_q = redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_o[8:0];

    // redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_inputreg0(DELAY,30806)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl);
        end
    end

    // redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_wraddr(COUNTER,30809)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_wraddr_i <= $unsigned(redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_wraddr_q = redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_wraddr_i[7:0];

    // redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem(DUALMEM,30808)
    assign redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_ia = $unsigned(redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_inputreg0_q);
    assign redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_aa = redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_wraddr_q;
    assign redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_ab = redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_aa),
        .data_a(redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_ab),
        .q_b(redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_q = redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_iq[15:0];

    // redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_outputreg0(DELAY,30807)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_outputreg0_q <= $unsigned(redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_mem_q);
        end
    end

    // redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_rdcnt(ADD,30817)
    assign redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_a = {1'b0, redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_wraddr_q};
    assign redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_b = {1'b0, redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_o <= $unsigned(redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_a) + $unsigned(redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_b);
        end
    end
    assign redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_q = redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_o[8:0];

    // redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_inputreg0(DELAY,30812)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl);
        end
    end

    // redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_wraddr(COUNTER,30815)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_wraddr_i <= $unsigned(redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_wraddr_q = redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_wraddr_i[7:0];

    // redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem(DUALMEM,30814)
    assign redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_ia = $unsigned(redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_inputreg0_q);
    assign redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_aa = redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_wraddr_q;
    assign redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_ab = redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_aa),
        .data_a(redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_ab),
        .q_b(redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_q = redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_iq[15:0];

    // redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_outputreg0(DELAY,30813)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_outputreg0_q <= $unsigned(redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_mem_q);
        end
    end

    // redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_rdcnt(ADD,32253)
    assign redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_a = {1'b0, redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_wraddr_q};
    assign redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_b = {1'b0, redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_o <= $unsigned(redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_a) + $unsigned(redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_b);
        end
    end
    assign redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_q = redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_o[8:0];

    // redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_inputreg0(DELAY,32248)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl);
        end
    end

    // redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_wraddr(COUNTER,32251)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_wraddr_i <= $unsigned(redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_wraddr_q = redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_wraddr_i[7:0];

    // redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem(DUALMEM,32250)
    assign redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_ia = $unsigned(redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_inputreg0_q);
    assign redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_aa = redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_wraddr_q;
    assign redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_ab = redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_aa),
        .data_a(redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_ab),
        .q_b(redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_q = redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_iq[15:0];

    // redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_outputreg0(DELAY,32249)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_outputreg0_q <= $unsigned(redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28068)@219 + 5
    // out q@225
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004(ADD,8528)@225
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod571_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_b = $unsigned({{5{i_shl_i_i_i_i_i_i_106_c_compstr3003_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_106_c_compstr3003_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_o[33:0];

    // rightShiftStage0_uid21541_dupName_425_i_unnamed_c_compstr0_shift_x(MUX,21540)@225
    assign rightShiftStage0_uid21541_dupName_425_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21541_dupName_425_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_q or rightShiftStage0Idx1_uid21539_dupName_425_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21541_dupName_425_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21541_dupName_425_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_q;
            1'b1 : rightShiftStage0_uid21541_dupName_425_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21539_dupName_425_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21541_dupName_425_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21546_dupName_425_i_unnamed_c_compstr0_shift_x(MUX,21545)@225
    assign rightShiftStage1_uid21546_dupName_425_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21546_dupName_425_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21541_dupName_425_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21544_dupName_425_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21546_dupName_425_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21546_dupName_425_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21541_dupName_425_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21546_dupName_425_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21544_dupName_425_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21546_dupName_425_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21551_dupName_425_i_unnamed_c_compstr0_shift_x(MUX,21550)@225
    assign rightShiftStage2_uid21551_dupName_425_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21551_dupName_425_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21546_dupName_425_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21549_dupName_425_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21551_dupName_425_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21551_dupName_425_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21546_dupName_425_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21551_dupName_425_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21549_dupName_425_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21551_dupName_425_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3005_vt_select_20(BITSELECT,11543)@225
    assign i_unnamed_c_compstr3005_vt_select_20_b = rightShiftStage2_uid21551_dupName_425_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3005_vt_join(BITJOIN,11542)@225
    assign i_unnamed_c_compstr3005_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3005_vt_select_20_b};

    // i_conv_i_i_i_i_i_106_c_compstr3006_sel_x(BITSELECT,3719)@225
    assign i_conv_i_i_i_i_i_106_c_compstr3006_sel_x_b = i_unnamed_c_compstr3005_vt_join_q[15:0];

    // redist1146_i_conv_i_i_i_i_i_106_c_compstr3006_sel_x_b_1(DELAY,29374)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1146_i_conv_i_i_i_i_i_106_c_compstr3006_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_106_c_compstr3006_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21560_dupName_426_i_unnamed_c_compstr0_shift_x(BITSELECT,21559)@225
    assign rightShiftStage1Idx1Rng8_uid21560_dupName_426_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21559_dupName_426_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21562_dupName_426_i_unnamed_c_compstr0_shift_x(BITJOIN,21561)@225
    assign rightShiftStage1Idx1_uid21562_dupName_426_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21560_dupName_426_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21555_dupName_426_i_unnamed_c_compstr0_shift_x(BITSELECT,21554)@225
    assign rightShiftStage0Idx1Rng4_uid21555_dupName_426_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_q[33:4];

    // rightShiftStage0Idx1_uid21557_dupName_426_i_unnamed_c_compstr0_shift_x(BITJOIN,21556)@225
    assign rightShiftStage0Idx1_uid21557_dupName_426_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21555_dupName_426_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21559_dupName_426_i_unnamed_c_compstr0_shift_x(MUX,21558)@225
    assign rightShiftStage0_uid21559_dupName_426_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21559_dupName_426_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_q or rightShiftStage0Idx1_uid21557_dupName_426_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21559_dupName_426_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21559_dupName_426_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compstr3004_q;
            1'b1 : rightShiftStage0_uid21559_dupName_426_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21557_dupName_426_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21559_dupName_426_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21564_dupName_426_i_unnamed_c_compstr0_shift_x(MUX,21563)@225
    assign rightShiftStage1_uid21564_dupName_426_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21564_dupName_426_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21559_dupName_426_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21562_dupName_426_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21564_dupName_426_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21564_dupName_426_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21559_dupName_426_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21564_dupName_426_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21562_dupName_426_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21564_dupName_426_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3007_vt_select_21(BITSELECT,11546)@225
    assign i_unnamed_c_compstr3007_vt_select_21_b = rightShiftStage1_uid21564_dupName_426_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3007_vt_join(BITJOIN,11545)@225
    assign i_unnamed_c_compstr3007_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3007_vt_select_21_b};

    // i_unnamed_c_compstr3008_sel_x(BITSELECT,6193)@225
    assign i_unnamed_c_compstr3008_sel_x_b = i_unnamed_c_compstr3007_vt_join_q[15:0];

    // i_unnamed_c_compstr3009_BitSelect_for_a(BITSELECT,27775)@225
    assign i_unnamed_c_compstr3009_BitSelect_for_a_b = i_unnamed_c_compstr3008_sel_x_b[0:0];

    // i_unnamed_c_compstr3009_join(BITJOIN,27776)@225
    assign i_unnamed_c_compstr3009_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3009_BitSelect_for_a_b};

    // i_unnamed_c_compstr3009_vt_select_0(BITSELECT,11551)@225
    assign i_unnamed_c_compstr3009_vt_select_0_b = i_unnamed_c_compstr3009_join_q[0:0];

    // redist98_i_unnamed_c_compstr3009_vt_select_0_b_1(DELAY,28326)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist98_i_unnamed_c_compstr3009_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3009_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3009_vt_join(BITJOIN,11550)@226
    assign i_unnamed_c_compstr3009_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist98_i_unnamed_c_compstr3009_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_106_c_compstr3010(ADD,6986)@226
    assign i_add_i_i_i_i_i_i_106_c_compstr3010_a = {1'b0, i_unnamed_c_compstr3009_vt_join_q};
    assign i_add_i_i_i_i_i_i_106_c_compstr3010_b = {1'b0, redist1146_i_conv_i_i_i_i_i_106_c_compstr3006_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_106_c_compstr3010_o = $unsigned(i_add_i_i_i_i_i_i_106_c_compstr3010_a) + $unsigned(i_add_i_i_i_i_i_i_106_c_compstr3010_b);
    assign i_add_i_i_i_i_i_i_106_c_compstr3010_q = i_add_i_i_i_i_i_i_106_c_compstr3010_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_106_c_compstr3010_sel_x(BITSELECT,2180)@226
    assign bgTrunc_i_add_i_i_i_i_i_i_106_c_compstr3010_sel_x_b = i_add_i_i_i_i_i_i_106_c_compstr3010_q[15:0];

    // i_conv_i_i_i_i_i_i279_107_c_compstr3030_sel_x(BITSELECT,3848)@226
    assign i_conv_i_i_i_i_i_i279_107_c_compstr3030_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_106_c_compstr3010_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_107_c_compstr3030_vt_select_15(BITSELECT,7909)@226
    assign i_conv_i_i_i_i_i_i279_107_c_compstr3030_vt_select_15_b = i_conv_i_i_i_i_i_i279_107_c_compstr3030_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_107_c_compstr3030_vt_join(BITJOIN,7908)@226
    assign i_conv_i_i_i_i_i_i279_107_c_compstr3030_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_107_c_compstr3030_vt_select_15_b};

    // leftShiftStage0_uid25286_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x(MUX,25285)@226
    assign leftShiftStage0_uid25286_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25286_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_107_c_compstr3030_vt_join_q or leftShiftStage0Idx1_uid25284_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25286_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25286_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_107_c_compstr3030_vt_join_q;
            1'b1 : leftShiftStage0_uid25286_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25284_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25286_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25291_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x(MUX,25290)@226
    assign leftShiftStage1_uid25291_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25291_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_s or leftShiftStage0_uid25286_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25289_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25291_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25291_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q = leftShiftStage0_uid25286_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25291_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25289_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25291_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25296_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x(MUX,25295)@226
    assign leftShiftStage2_uid25296_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25296_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_s or leftShiftStage1_uid25291_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25294_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25296_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25296_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q = leftShiftStage1_uid25291_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25296_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25294_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25296_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_107_c_compstr3031_vt_select_28(BITSELECT,9445)@226
    assign i_shl_i_i_i_i_i_i_107_c_compstr3031_vt_select_28_b = leftShiftStage2_uid25296_i_shl_i_i_i_i_i_i_107_c_compstr0_shift_x_q[28:13];

    // redist375_i_shl_i_i_i_i_i_i_107_c_compstr3031_vt_select_28_b_1(DELAY,28603)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist375_i_shl_i_i_i_i_i_i_107_c_compstr3031_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_107_c_compstr3031_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_107_c_compstr3031_vt_join(BITJOIN,9444)@227
    assign i_shl_i_i_i_i_i_i_107_c_compstr3031_vt_join_q = {redist375_i_shl_i_i_i_i_i_i_107_c_compstr3031_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_offset(CONSTANT,30822)
    assign redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_offset_q = $unsigned(8'b00110000);

    // redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_rdcnt(ADD,32271)
    assign redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_a = {1'b0, redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_wraddr_q};
    assign redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_b = {1'b0, redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_o <= $unsigned(redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_a) + $unsigned(redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_b);
        end
    end
    assign redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_q = redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_o[8:0];

    // redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_inputreg0(DELAY,32266)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl);
        end
    end

    // redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_wraddr(COUNTER,32269)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_wraddr_i <= $unsigned(redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_wraddr_q = redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_wraddr_i[7:0];

    // redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem(DUALMEM,32268)
    assign redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_ia = $unsigned(redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_inputreg0_q);
    assign redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_aa = redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_wraddr_q;
    assign redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_ab = redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_aa),
        .data_a(redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_ab),
        .q_b(redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_q = redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_iq[15:0];

    // redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_outputreg0(DELAY,32267)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_outputreg0_q <= $unsigned(redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_mem_q);
        end
    end

    // redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_rdcnt(ADD,30823)
    assign redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_a = {1'b0, redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_wraddr_q};
    assign redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_b = {1'b0, redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_o <= $unsigned(redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_a) + $unsigned(redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_b);
        end
    end
    assign redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_q = redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_o[8:0];

    // redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_inputreg0(DELAY,30818)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl);
        end
    end

    // redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_wraddr(COUNTER,30821)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_wraddr_i <= $unsigned(redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_wraddr_q = redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_wraddr_i[7:0];

    // redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem(DUALMEM,30820)
    assign redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_ia = $unsigned(redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_inputreg0_q);
    assign redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_aa = redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_wraddr_q;
    assign redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_ab = redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_aa),
        .data_a(redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_ab),
        .q_b(redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_q = redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_iq[15:0];

    // redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_outputreg0(DELAY,30819)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_outputreg0_q <= $unsigned(redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_mem_q);
        end
    end

    // redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_rdcnt(ADD,30829)
    assign redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_a = {1'b0, redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_wraddr_q};
    assign redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_b = {1'b0, redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_o <= $unsigned(redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_a) + $unsigned(redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_b);
        end
    end
    assign redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_q = redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_o[8:0];

    // redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_inputreg0(DELAY,30824)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl);
        end
    end

    // redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_wraddr(COUNTER,30827)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_wraddr_i <= $unsigned(redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_wraddr_q = redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_wraddr_i[7:0];

    // redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem(DUALMEM,30826)
    assign redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_ia = $unsigned(redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_inputreg0_q);
    assign redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_aa = redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_wraddr_q;
    assign redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_ab = redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_aa),
        .data_a(redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_ab),
        .q_b(redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_q = redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_iq[15:0];

    // redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_outputreg0(DELAY,30825)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_outputreg0_q <= $unsigned(redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_mem_q);
        end
    end

    // redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_rdcnt(ADD,32265)
    assign redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_a = {1'b0, redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_wraddr_q};
    assign redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_b = {1'b0, redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_o <= $unsigned(redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_a) + $unsigned(redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_b);
        end
    end
    assign redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_q = redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_o[8:0];

    // redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_inputreg0(DELAY,32260)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl);
        end
    end

    // redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_wraddr(COUNTER,32263)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_wraddr_i <= $unsigned(redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_wraddr_q = redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_wraddr_i[7:0];

    // redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem(DUALMEM,32262)
    assign redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_ia = $unsigned(redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_inputreg0_q);
    assign redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_aa = redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_wraddr_q;
    assign redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_ab = redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_aa),
        .data_a(redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_ab),
        .q_b(redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_q = redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_iq[15:0];

    // redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_outputreg0(DELAY,32261)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_outputreg0_q <= $unsigned(redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28069)@221 + 5
    // out q@227
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032(ADD,8529)@227
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod576_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_b = $unsigned({{5{i_shl_i_i_i_i_i_i_107_c_compstr3031_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_107_c_compstr3031_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_o[33:0];

    // rightShiftStage0_uid21603_dupName_429_i_unnamed_c_compstr0_shift_x(MUX,21602)@227
    assign rightShiftStage0_uid21603_dupName_429_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21603_dupName_429_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_q or rightShiftStage0Idx1_uid21601_dupName_429_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21603_dupName_429_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21603_dupName_429_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_q;
            1'b1 : rightShiftStage0_uid21603_dupName_429_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21601_dupName_429_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21603_dupName_429_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21608_dupName_429_i_unnamed_c_compstr0_shift_x(MUX,21607)@227
    assign rightShiftStage1_uid21608_dupName_429_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21608_dupName_429_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21603_dupName_429_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21606_dupName_429_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21608_dupName_429_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21608_dupName_429_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21603_dupName_429_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21608_dupName_429_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21606_dupName_429_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21608_dupName_429_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21613_dupName_429_i_unnamed_c_compstr0_shift_x(MUX,21612)@227
    assign rightShiftStage2_uid21613_dupName_429_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21613_dupName_429_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21608_dupName_429_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21611_dupName_429_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21613_dupName_429_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21613_dupName_429_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21608_dupName_429_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21613_dupName_429_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21611_dupName_429_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21613_dupName_429_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3033_vt_select_20(BITSELECT,11568)@227
    assign i_unnamed_c_compstr3033_vt_select_20_b = rightShiftStage2_uid21613_dupName_429_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3033_vt_join(BITJOIN,11567)@227
    assign i_unnamed_c_compstr3033_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3033_vt_select_20_b};

    // i_conv_i_i_i_i_i_107_c_compstr3034_sel_x(BITSELECT,3720)@227
    assign i_conv_i_i_i_i_i_107_c_compstr3034_sel_x_b = i_unnamed_c_compstr3033_vt_join_q[15:0];

    // redist1145_i_conv_i_i_i_i_i_107_c_compstr3034_sel_x_b_1(DELAY,29373)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1145_i_conv_i_i_i_i_i_107_c_compstr3034_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_107_c_compstr3034_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21622_dupName_430_i_unnamed_c_compstr0_shift_x(BITSELECT,21621)@227
    assign rightShiftStage1Idx1Rng8_uid21622_dupName_430_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21621_dupName_430_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21624_dupName_430_i_unnamed_c_compstr0_shift_x(BITJOIN,21623)@227
    assign rightShiftStage1Idx1_uid21624_dupName_430_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21622_dupName_430_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21617_dupName_430_i_unnamed_c_compstr0_shift_x(BITSELECT,21616)@227
    assign rightShiftStage0Idx1Rng4_uid21617_dupName_430_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_q[33:4];

    // rightShiftStage0Idx1_uid21619_dupName_430_i_unnamed_c_compstr0_shift_x(BITJOIN,21618)@227
    assign rightShiftStage0Idx1_uid21619_dupName_430_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21617_dupName_430_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21621_dupName_430_i_unnamed_c_compstr0_shift_x(MUX,21620)@227
    assign rightShiftStage0_uid21621_dupName_430_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21621_dupName_430_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_q or rightShiftStage0Idx1_uid21619_dupName_430_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21621_dupName_430_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21621_dupName_430_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compstr3032_q;
            1'b1 : rightShiftStage0_uid21621_dupName_430_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21619_dupName_430_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21621_dupName_430_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21626_dupName_430_i_unnamed_c_compstr0_shift_x(MUX,21625)@227
    assign rightShiftStage1_uid21626_dupName_430_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21626_dupName_430_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21621_dupName_430_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21624_dupName_430_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21626_dupName_430_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21626_dupName_430_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21621_dupName_430_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21626_dupName_430_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21624_dupName_430_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21626_dupName_430_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3035_vt_select_21(BITSELECT,11571)@227
    assign i_unnamed_c_compstr3035_vt_select_21_b = rightShiftStage1_uid21626_dupName_430_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3035_vt_join(BITJOIN,11570)@227
    assign i_unnamed_c_compstr3035_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3035_vt_select_21_b};

    // i_unnamed_c_compstr3036_sel_x(BITSELECT,6195)@227
    assign i_unnamed_c_compstr3036_sel_x_b = i_unnamed_c_compstr3035_vt_join_q[15:0];

    // i_unnamed_c_compstr3037_BitSelect_for_a(BITSELECT,27779)@227
    assign i_unnamed_c_compstr3037_BitSelect_for_a_b = i_unnamed_c_compstr3036_sel_x_b[0:0];

    // i_unnamed_c_compstr3037_join(BITJOIN,27780)@227
    assign i_unnamed_c_compstr3037_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3037_BitSelect_for_a_b};

    // i_unnamed_c_compstr3037_vt_select_0(BITSELECT,11576)@227
    assign i_unnamed_c_compstr3037_vt_select_0_b = i_unnamed_c_compstr3037_join_q[0:0];

    // redist96_i_unnamed_c_compstr3037_vt_select_0_b_1(DELAY,28324)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist96_i_unnamed_c_compstr3037_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3037_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3037_vt_join(BITJOIN,11575)@228
    assign i_unnamed_c_compstr3037_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist96_i_unnamed_c_compstr3037_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_107_c_compstr3038(ADD,6987)@228
    assign i_add_i_i_i_i_i_i_107_c_compstr3038_a = {1'b0, i_unnamed_c_compstr3037_vt_join_q};
    assign i_add_i_i_i_i_i_i_107_c_compstr3038_b = {1'b0, redist1145_i_conv_i_i_i_i_i_107_c_compstr3034_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_107_c_compstr3038_o = $unsigned(i_add_i_i_i_i_i_i_107_c_compstr3038_a) + $unsigned(i_add_i_i_i_i_i_i_107_c_compstr3038_b);
    assign i_add_i_i_i_i_i_i_107_c_compstr3038_q = i_add_i_i_i_i_i_i_107_c_compstr3038_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_107_c_compstr3038_sel_x(BITSELECT,2181)@228
    assign bgTrunc_i_add_i_i_i_i_i_i_107_c_compstr3038_sel_x_b = i_add_i_i_i_i_i_i_107_c_compstr3038_q[15:0];

    // i_conv_i_i_i_i_i_i279_108_c_compstr3058_sel_x(BITSELECT,3849)@228
    assign i_conv_i_i_i_i_i_i279_108_c_compstr3058_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_107_c_compstr3038_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_108_c_compstr3058_vt_select_15(BITSELECT,7913)@228
    assign i_conv_i_i_i_i_i_i279_108_c_compstr3058_vt_select_15_b = i_conv_i_i_i_i_i_i279_108_c_compstr3058_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_108_c_compstr3058_vt_join(BITJOIN,7912)@228
    assign i_conv_i_i_i_i_i_i279_108_c_compstr3058_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_108_c_compstr3058_vt_select_15_b};

    // leftShiftStage0_uid25304_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x(MUX,25303)@228
    assign leftShiftStage0_uid25304_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25304_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_108_c_compstr3058_vt_join_q or leftShiftStage0Idx1_uid25302_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25304_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25304_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_108_c_compstr3058_vt_join_q;
            1'b1 : leftShiftStage0_uid25304_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25302_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25304_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25309_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x(MUX,25308)@228
    assign leftShiftStage1_uid25309_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25309_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_s or leftShiftStage0_uid25304_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25307_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25309_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25309_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q = leftShiftStage0_uid25304_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25309_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25307_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25309_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25314_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x(MUX,25313)@228
    assign leftShiftStage2_uid25314_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25314_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_s or leftShiftStage1_uid25309_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25312_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25314_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25314_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q = leftShiftStage1_uid25309_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25314_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25312_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25314_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_108_c_compstr3059_vt_select_28(BITSELECT,9448)@228
    assign i_shl_i_i_i_i_i_i_108_c_compstr3059_vt_select_28_b = leftShiftStage2_uid25314_i_shl_i_i_i_i_i_i_108_c_compstr0_shift_x_q[28:13];

    // redist374_i_shl_i_i_i_i_i_i_108_c_compstr3059_vt_select_28_b_1(DELAY,28602)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist374_i_shl_i_i_i_i_i_i_108_c_compstr3059_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_108_c_compstr3059_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_108_c_compstr3059_vt_join(BITJOIN,9447)@229
    assign i_shl_i_i_i_i_i_i_108_c_compstr3059_vt_join_q = {redist374_i_shl_i_i_i_i_i_i_108_c_compstr3059_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_offset(CONSTANT,30834)
    assign redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_offset_q = $unsigned(8'b00101110);

    // redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_rdcnt(ADD,32283)
    assign redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_a = {1'b0, redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_wraddr_q};
    assign redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_b = {1'b0, redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_o <= $unsigned(redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_a) + $unsigned(redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_b);
        end
    end
    assign redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_q = redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_o[8:0];

    // redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_inputreg0(DELAY,32278)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl);
        end
    end

    // redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_wraddr(COUNTER,32281)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_wraddr_i <= $unsigned(redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_wraddr_q = redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_wraddr_i[7:0];

    // redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem(DUALMEM,32280)
    assign redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_ia = $unsigned(redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_inputreg0_q);
    assign redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_aa = redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_wraddr_q;
    assign redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_ab = redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_aa),
        .data_a(redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_ab),
        .q_b(redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_q = redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_iq[15:0];

    // redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_outputreg0(DELAY,32279)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_outputreg0_q <= $unsigned(redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_mem_q);
        end
    end

    // redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_rdcnt(ADD,30835)
    assign redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_a = {1'b0, redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_wraddr_q};
    assign redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_b = {1'b0, redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_o <= $unsigned(redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_a) + $unsigned(redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_b);
        end
    end
    assign redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_q = redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_o[8:0];

    // redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_inputreg0(DELAY,30830)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl);
        end
    end

    // redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_wraddr(COUNTER,30833)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_wraddr_i <= $unsigned(redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_wraddr_q = redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_wraddr_i[7:0];

    // redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem(DUALMEM,30832)
    assign redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_ia = $unsigned(redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_inputreg0_q);
    assign redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_aa = redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_wraddr_q;
    assign redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_ab = redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_aa),
        .data_a(redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_ab),
        .q_b(redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_q = redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_iq[15:0];

    // redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_outputreg0(DELAY,30831)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_outputreg0_q <= $unsigned(redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_mem_q);
        end
    end

    // redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_rdcnt(ADD,30841)
    assign redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_a = {1'b0, redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_wraddr_q};
    assign redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_b = {1'b0, redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_o <= $unsigned(redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_a) + $unsigned(redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_b);
        end
    end
    assign redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_q = redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_o[8:0];

    // redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_inputreg0(DELAY,30836)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl);
        end
    end

    // redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_wraddr(COUNTER,30839)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_wraddr_i <= $unsigned(redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_wraddr_q = redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_wraddr_i[7:0];

    // redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem(DUALMEM,30838)
    assign redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_ia = $unsigned(redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_inputreg0_q);
    assign redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_aa = redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_wraddr_q;
    assign redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_ab = redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_aa),
        .data_a(redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_ab),
        .q_b(redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_q = redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_iq[15:0];

    // redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_outputreg0(DELAY,30837)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_outputreg0_q <= $unsigned(redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_mem_q);
        end
    end

    // redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_rdcnt(ADD,32277)
    assign redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_a = {1'b0, redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_wraddr_q};
    assign redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_b = {1'b0, redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_o <= $unsigned(redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_a) + $unsigned(redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_b);
        end
    end
    assign redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_q = redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_o[8:0];

    // redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_inputreg0(DELAY,32272)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl);
        end
    end

    // redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_wraddr(COUNTER,32275)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_wraddr_i <= $unsigned(redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_wraddr_q = redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_wraddr_i[7:0];

    // redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem(DUALMEM,32274)
    assign redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_ia = $unsigned(redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_inputreg0_q);
    assign redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_aa = redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_wraddr_q;
    assign redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_ab = redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_aa),
        .data_a(redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_ab),
        .q_b(redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_q = redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_iq[15:0];

    // redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_outputreg0(DELAY,32273)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_outputreg0_q <= $unsigned(redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28070)@223 + 5
    // out q@229
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060(ADD,8530)@229
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod581_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_b = $unsigned({{5{i_shl_i_i_i_i_i_i_108_c_compstr3059_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_108_c_compstr3059_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_o[33:0];

    // rightShiftStage0_uid21665_dupName_433_i_unnamed_c_compstr0_shift_x(MUX,21664)@229
    assign rightShiftStage0_uid21665_dupName_433_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21665_dupName_433_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_q or rightShiftStage0Idx1_uid21663_dupName_433_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21665_dupName_433_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21665_dupName_433_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_q;
            1'b1 : rightShiftStage0_uid21665_dupName_433_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21663_dupName_433_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21665_dupName_433_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21670_dupName_433_i_unnamed_c_compstr0_shift_x(MUX,21669)@229
    assign rightShiftStage1_uid21670_dupName_433_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21670_dupName_433_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21665_dupName_433_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21668_dupName_433_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21670_dupName_433_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21670_dupName_433_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21665_dupName_433_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21670_dupName_433_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21668_dupName_433_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21670_dupName_433_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21675_dupName_433_i_unnamed_c_compstr0_shift_x(MUX,21674)@229
    assign rightShiftStage2_uid21675_dupName_433_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21675_dupName_433_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21670_dupName_433_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21673_dupName_433_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21675_dupName_433_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21675_dupName_433_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21670_dupName_433_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21675_dupName_433_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21673_dupName_433_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21675_dupName_433_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3061_vt_select_20(BITSELECT,11598)@229
    assign i_unnamed_c_compstr3061_vt_select_20_b = rightShiftStage2_uid21675_dupName_433_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3061_vt_join(BITJOIN,11597)@229
    assign i_unnamed_c_compstr3061_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3061_vt_select_20_b};

    // i_conv_i_i_i_i_i_108_c_compstr3062_sel_x(BITSELECT,3721)@229
    assign i_conv_i_i_i_i_i_108_c_compstr3062_sel_x_b = i_unnamed_c_compstr3061_vt_join_q[15:0];

    // redist1144_i_conv_i_i_i_i_i_108_c_compstr3062_sel_x_b_1(DELAY,29372)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1144_i_conv_i_i_i_i_i_108_c_compstr3062_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_108_c_compstr3062_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21684_dupName_434_i_unnamed_c_compstr0_shift_x(BITSELECT,21683)@229
    assign rightShiftStage1Idx1Rng8_uid21684_dupName_434_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21683_dupName_434_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21686_dupName_434_i_unnamed_c_compstr0_shift_x(BITJOIN,21685)@229
    assign rightShiftStage1Idx1_uid21686_dupName_434_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21684_dupName_434_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21679_dupName_434_i_unnamed_c_compstr0_shift_x(BITSELECT,21678)@229
    assign rightShiftStage0Idx1Rng4_uid21679_dupName_434_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_q[33:4];

    // rightShiftStage0Idx1_uid21681_dupName_434_i_unnamed_c_compstr0_shift_x(BITJOIN,21680)@229
    assign rightShiftStage0Idx1_uid21681_dupName_434_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21679_dupName_434_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21683_dupName_434_i_unnamed_c_compstr0_shift_x(MUX,21682)@229
    assign rightShiftStage0_uid21683_dupName_434_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21683_dupName_434_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_q or rightShiftStage0Idx1_uid21681_dupName_434_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21683_dupName_434_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21683_dupName_434_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compstr3060_q;
            1'b1 : rightShiftStage0_uid21683_dupName_434_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21681_dupName_434_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21683_dupName_434_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21688_dupName_434_i_unnamed_c_compstr0_shift_x(MUX,21687)@229
    assign rightShiftStage1_uid21688_dupName_434_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21688_dupName_434_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21683_dupName_434_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21686_dupName_434_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21688_dupName_434_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21688_dupName_434_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21683_dupName_434_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21688_dupName_434_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21686_dupName_434_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21688_dupName_434_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3063_vt_select_21(BITSELECT,11601)@229
    assign i_unnamed_c_compstr3063_vt_select_21_b = rightShiftStage1_uid21688_dupName_434_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3063_vt_join(BITJOIN,11600)@229
    assign i_unnamed_c_compstr3063_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3063_vt_select_21_b};

    // i_unnamed_c_compstr3064_sel_x(BITSELECT,6198)@229
    assign i_unnamed_c_compstr3064_sel_x_b = i_unnamed_c_compstr3063_vt_join_q[15:0];

    // i_unnamed_c_compstr3065_BitSelect_for_a(BITSELECT,27785)@229
    assign i_unnamed_c_compstr3065_BitSelect_for_a_b = i_unnamed_c_compstr3064_sel_x_b[0:0];

    // i_unnamed_c_compstr3065_join(BITJOIN,27786)@229
    assign i_unnamed_c_compstr3065_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3065_BitSelect_for_a_b};

    // i_unnamed_c_compstr3065_vt_select_0(BITSELECT,11606)@229
    assign i_unnamed_c_compstr3065_vt_select_0_b = i_unnamed_c_compstr3065_join_q[0:0];

    // redist93_i_unnamed_c_compstr3065_vt_select_0_b_1(DELAY,28321)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist93_i_unnamed_c_compstr3065_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3065_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3065_vt_join(BITJOIN,11605)@230
    assign i_unnamed_c_compstr3065_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist93_i_unnamed_c_compstr3065_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_108_c_compstr3066(ADD,6988)@230
    assign i_add_i_i_i_i_i_i_108_c_compstr3066_a = {1'b0, i_unnamed_c_compstr3065_vt_join_q};
    assign i_add_i_i_i_i_i_i_108_c_compstr3066_b = {1'b0, redist1144_i_conv_i_i_i_i_i_108_c_compstr3062_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_108_c_compstr3066_o = $unsigned(i_add_i_i_i_i_i_i_108_c_compstr3066_a) + $unsigned(i_add_i_i_i_i_i_i_108_c_compstr3066_b);
    assign i_add_i_i_i_i_i_i_108_c_compstr3066_q = i_add_i_i_i_i_i_i_108_c_compstr3066_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_108_c_compstr3066_sel_x(BITSELECT,2182)@230
    assign bgTrunc_i_add_i_i_i_i_i_i_108_c_compstr3066_sel_x_b = i_add_i_i_i_i_i_i_108_c_compstr3066_q[15:0];

    // i_conv_i_i_i_i_i_i279_109_c_compstr3086_sel_x(BITSELECT,3850)@230
    assign i_conv_i_i_i_i_i_i279_109_c_compstr3086_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_108_c_compstr3066_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_109_c_compstr3086_vt_select_15(BITSELECT,7917)@230
    assign i_conv_i_i_i_i_i_i279_109_c_compstr3086_vt_select_15_b = i_conv_i_i_i_i_i_i279_109_c_compstr3086_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_109_c_compstr3086_vt_join(BITJOIN,7916)@230
    assign i_conv_i_i_i_i_i_i279_109_c_compstr3086_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_109_c_compstr3086_vt_select_15_b};

    // leftShiftStage0_uid25322_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x(MUX,25321)@230
    assign leftShiftStage0_uid25322_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25322_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_109_c_compstr3086_vt_join_q or leftShiftStage0Idx1_uid25320_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25322_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25322_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_109_c_compstr3086_vt_join_q;
            1'b1 : leftShiftStage0_uid25322_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25320_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25322_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25327_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x(MUX,25326)@230
    assign leftShiftStage1_uid25327_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25327_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_s or leftShiftStage0_uid25322_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25325_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25327_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25327_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q = leftShiftStage0_uid25322_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25327_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25325_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25327_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25332_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x(MUX,25331)@230
    assign leftShiftStage2_uid25332_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25332_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_s or leftShiftStage1_uid25327_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25330_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25332_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25332_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q = leftShiftStage1_uid25327_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25332_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25330_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25332_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_109_c_compstr3087_vt_select_28(BITSELECT,9451)@230
    assign i_shl_i_i_i_i_i_i_109_c_compstr3087_vt_select_28_b = leftShiftStage2_uid25332_i_shl_i_i_i_i_i_i_109_c_compstr0_shift_x_q[28:13];

    // redist373_i_shl_i_i_i_i_i_i_109_c_compstr3087_vt_select_28_b_1(DELAY,28601)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist373_i_shl_i_i_i_i_i_i_109_c_compstr3087_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_109_c_compstr3087_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_109_c_compstr3087_vt_join(BITJOIN,9450)@231
    assign i_shl_i_i_i_i_i_i_109_c_compstr3087_vt_join_q = {redist373_i_shl_i_i_i_i_i_i_109_c_compstr3087_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_offset(CONSTANT,30846)
    assign redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_offset_q = $unsigned(8'b00101100);

    // redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_rdcnt(ADD,32295)
    assign redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_a = {1'b0, redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_wraddr_q};
    assign redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_b = {1'b0, redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_o <= $unsigned(redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_a) + $unsigned(redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_b);
        end
    end
    assign redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_q = redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_o[8:0];

    // redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_inputreg0(DELAY,32290)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl);
        end
    end

    // redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_wraddr(COUNTER,32293)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_wraddr_i <= $unsigned(redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_wraddr_q = redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_wraddr_i[7:0];

    // redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem(DUALMEM,32292)
    assign redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_ia = $unsigned(redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_inputreg0_q);
    assign redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_aa = redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_wraddr_q;
    assign redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_ab = redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_aa),
        .data_a(redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_ab),
        .q_b(redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_q = redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_iq[15:0];

    // redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_outputreg0(DELAY,32291)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_outputreg0_q <= $unsigned(redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_mem_q);
        end
    end

    // redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_rdcnt(ADD,30847)
    assign redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_a = {1'b0, redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_wraddr_q};
    assign redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_b = {1'b0, redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_o <= $unsigned(redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_a) + $unsigned(redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_b);
        end
    end
    assign redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_q = redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_o[8:0];

    // redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_inputreg0(DELAY,30842)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl);
        end
    end

    // redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_wraddr(COUNTER,30845)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_wraddr_i <= $unsigned(redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_wraddr_q = redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_wraddr_i[7:0];

    // redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem(DUALMEM,30844)
    assign redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_ia = $unsigned(redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_inputreg0_q);
    assign redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_aa = redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_wraddr_q;
    assign redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_ab = redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_aa),
        .data_a(redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_ab),
        .q_b(redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_q = redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_iq[15:0];

    // redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_outputreg0(DELAY,30843)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_outputreg0_q <= $unsigned(redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_mem_q);
        end
    end

    // redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_rdcnt(ADD,30853)
    assign redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_a = {1'b0, redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_wraddr_q};
    assign redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_b = {1'b0, redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_o <= $unsigned(redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_a) + $unsigned(redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_b);
        end
    end
    assign redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_q = redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_o[8:0];

    // redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_inputreg0(DELAY,30848)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl);
        end
    end

    // redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_wraddr(COUNTER,30851)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_wraddr_i <= $unsigned(redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_wraddr_q = redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_wraddr_i[7:0];

    // redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem(DUALMEM,30850)
    assign redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_ia = $unsigned(redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_inputreg0_q);
    assign redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_aa = redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_wraddr_q;
    assign redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_ab = redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_aa),
        .data_a(redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_ab),
        .q_b(redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_q = redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_iq[15:0];

    // redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_outputreg0(DELAY,30849)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_outputreg0_q <= $unsigned(redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_mem_q);
        end
    end

    // redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_rdcnt(ADD,32289)
    assign redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_a = {1'b0, redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_wraddr_q};
    assign redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_b = {1'b0, redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_o <= $unsigned(redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_a) + $unsigned(redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_b);
        end
    end
    assign redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_q = redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_o[8:0];

    // redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_inputreg0(DELAY,32284)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl);
        end
    end

    // redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_wraddr(COUNTER,32287)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_wraddr_i <= $unsigned(redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_wraddr_q = redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_wraddr_i[7:0];

    // redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem(DUALMEM,32286)
    assign redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_ia = $unsigned(redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_inputreg0_q);
    assign redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_aa = redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_wraddr_q;
    assign redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_ab = redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_aa),
        .data_a(redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_ab),
        .q_b(redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_q = redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_iq[15:0];

    // redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_outputreg0(DELAY,32285)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_outputreg0_q <= $unsigned(redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28071)@225 + 5
    // out q@231
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088(ADD,8531)@231
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod586_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_b = $unsigned({{5{i_shl_i_i_i_i_i_i_109_c_compstr3087_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_109_c_compstr3087_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_o[33:0];

    // rightShiftStage0_uid21727_dupName_437_i_unnamed_c_compstr0_shift_x(MUX,21726)@231
    assign rightShiftStage0_uid21727_dupName_437_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21727_dupName_437_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_q or rightShiftStage0Idx1_uid21725_dupName_437_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21727_dupName_437_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21727_dupName_437_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_q;
            1'b1 : rightShiftStage0_uid21727_dupName_437_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21725_dupName_437_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21727_dupName_437_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21732_dupName_437_i_unnamed_c_compstr0_shift_x(MUX,21731)@231
    assign rightShiftStage1_uid21732_dupName_437_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21732_dupName_437_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21727_dupName_437_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21730_dupName_437_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21732_dupName_437_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21732_dupName_437_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21727_dupName_437_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21732_dupName_437_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21730_dupName_437_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21732_dupName_437_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21737_dupName_437_i_unnamed_c_compstr0_shift_x(MUX,21736)@231
    assign rightShiftStage2_uid21737_dupName_437_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21737_dupName_437_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21732_dupName_437_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21735_dupName_437_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21737_dupName_437_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21737_dupName_437_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21732_dupName_437_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21737_dupName_437_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21735_dupName_437_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21737_dupName_437_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3089_vt_select_20(BITSELECT,11620)@231
    assign i_unnamed_c_compstr3089_vt_select_20_b = rightShiftStage2_uid21737_dupName_437_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3089_vt_join(BITJOIN,11619)@231
    assign i_unnamed_c_compstr3089_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3089_vt_select_20_b};

    // i_conv_i_i_i_i_i_109_c_compstr3090_sel_x(BITSELECT,3722)@231
    assign i_conv_i_i_i_i_i_109_c_compstr3090_sel_x_b = i_unnamed_c_compstr3089_vt_join_q[15:0];

    // redist1143_i_conv_i_i_i_i_i_109_c_compstr3090_sel_x_b_1(DELAY,29371)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1143_i_conv_i_i_i_i_i_109_c_compstr3090_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_109_c_compstr3090_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21746_dupName_438_i_unnamed_c_compstr0_shift_x(BITSELECT,21745)@231
    assign rightShiftStage1Idx1Rng8_uid21746_dupName_438_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21745_dupName_438_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21748_dupName_438_i_unnamed_c_compstr0_shift_x(BITJOIN,21747)@231
    assign rightShiftStage1Idx1_uid21748_dupName_438_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21746_dupName_438_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21741_dupName_438_i_unnamed_c_compstr0_shift_x(BITSELECT,21740)@231
    assign rightShiftStage0Idx1Rng4_uid21741_dupName_438_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_q[33:4];

    // rightShiftStage0Idx1_uid21743_dupName_438_i_unnamed_c_compstr0_shift_x(BITJOIN,21742)@231
    assign rightShiftStage0Idx1_uid21743_dupName_438_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21741_dupName_438_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21745_dupName_438_i_unnamed_c_compstr0_shift_x(MUX,21744)@231
    assign rightShiftStage0_uid21745_dupName_438_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21745_dupName_438_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_q or rightShiftStage0Idx1_uid21743_dupName_438_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21745_dupName_438_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21745_dupName_438_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compstr3088_q;
            1'b1 : rightShiftStage0_uid21745_dupName_438_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21743_dupName_438_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21745_dupName_438_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21750_dupName_438_i_unnamed_c_compstr0_shift_x(MUX,21749)@231
    assign rightShiftStage1_uid21750_dupName_438_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21750_dupName_438_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21745_dupName_438_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21748_dupName_438_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21750_dupName_438_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21750_dupName_438_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21745_dupName_438_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21750_dupName_438_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21748_dupName_438_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21750_dupName_438_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3091_vt_select_21(BITSELECT,11623)@231
    assign i_unnamed_c_compstr3091_vt_select_21_b = rightShiftStage1_uid21750_dupName_438_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3091_vt_join(BITJOIN,11622)@231
    assign i_unnamed_c_compstr3091_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3091_vt_select_21_b};

    // i_unnamed_c_compstr3092_sel_x(BITSELECT,6200)@231
    assign i_unnamed_c_compstr3092_sel_x_b = i_unnamed_c_compstr3091_vt_join_q[15:0];

    // i_unnamed_c_compstr3093_BitSelect_for_a(BITSELECT,27789)@231
    assign i_unnamed_c_compstr3093_BitSelect_for_a_b = i_unnamed_c_compstr3092_sel_x_b[0:0];

    // i_unnamed_c_compstr3093_join(BITJOIN,27790)@231
    assign i_unnamed_c_compstr3093_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3093_BitSelect_for_a_b};

    // i_unnamed_c_compstr3093_vt_select_0(BITSELECT,11628)@231
    assign i_unnamed_c_compstr3093_vt_select_0_b = i_unnamed_c_compstr3093_join_q[0:0];

    // redist91_i_unnamed_c_compstr3093_vt_select_0_b_1(DELAY,28319)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist91_i_unnamed_c_compstr3093_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3093_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3093_vt_join(BITJOIN,11627)@232
    assign i_unnamed_c_compstr3093_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist91_i_unnamed_c_compstr3093_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_109_c_compstr3094(ADD,6989)@232
    assign i_add_i_i_i_i_i_i_109_c_compstr3094_a = {1'b0, i_unnamed_c_compstr3093_vt_join_q};
    assign i_add_i_i_i_i_i_i_109_c_compstr3094_b = {1'b0, redist1143_i_conv_i_i_i_i_i_109_c_compstr3090_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_109_c_compstr3094_o = $unsigned(i_add_i_i_i_i_i_i_109_c_compstr3094_a) + $unsigned(i_add_i_i_i_i_i_i_109_c_compstr3094_b);
    assign i_add_i_i_i_i_i_i_109_c_compstr3094_q = i_add_i_i_i_i_i_i_109_c_compstr3094_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_109_c_compstr3094_sel_x(BITSELECT,2183)@232
    assign bgTrunc_i_add_i_i_i_i_i_i_109_c_compstr3094_sel_x_b = i_add_i_i_i_i_i_i_109_c_compstr3094_q[15:0];

    // i_conv_i_i_i_i_i_i279_110_c_compstr3114_sel_x(BITSELECT,3852)@232
    assign i_conv_i_i_i_i_i_i279_110_c_compstr3114_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_109_c_compstr3094_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_110_c_compstr3114_vt_select_15(BITSELECT,7925)@232
    assign i_conv_i_i_i_i_i_i279_110_c_compstr3114_vt_select_15_b = i_conv_i_i_i_i_i_i279_110_c_compstr3114_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_110_c_compstr3114_vt_join(BITJOIN,7924)@232
    assign i_conv_i_i_i_i_i_i279_110_c_compstr3114_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_110_c_compstr3114_vt_select_15_b};

    // leftShiftStage0_uid25358_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x(MUX,25357)@232
    assign leftShiftStage0_uid25358_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25358_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_110_c_compstr3114_vt_join_q or leftShiftStage0Idx1_uid25356_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25358_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25358_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_110_c_compstr3114_vt_join_q;
            1'b1 : leftShiftStage0_uid25358_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25356_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25358_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25363_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x(MUX,25362)@232
    assign leftShiftStage1_uid25363_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25363_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_s or leftShiftStage0_uid25358_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25361_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25363_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25363_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q = leftShiftStage0_uid25358_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25363_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25361_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25363_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25368_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x(MUX,25367)@232
    assign leftShiftStage2_uid25368_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25368_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_s or leftShiftStage1_uid25363_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25366_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25368_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25368_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q = leftShiftStage1_uid25363_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25368_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25366_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25368_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_110_c_compstr3115_vt_select_28(BITSELECT,9457)@232
    assign i_shl_i_i_i_i_i_i_110_c_compstr3115_vt_select_28_b = leftShiftStage2_uid25368_i_shl_i_i_i_i_i_i_110_c_compstr0_shift_x_q[28:13];

    // redist371_i_shl_i_i_i_i_i_i_110_c_compstr3115_vt_select_28_b_1(DELAY,28599)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist371_i_shl_i_i_i_i_i_i_110_c_compstr3115_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_110_c_compstr3115_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_110_c_compstr3115_vt_join(BITJOIN,9456)@233
    assign i_shl_i_i_i_i_i_i_110_c_compstr3115_vt_join_q = {redist371_i_shl_i_i_i_i_i_i_110_c_compstr3115_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_offset(CONSTANT,30858)
    assign redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_offset_q = $unsigned(8'b00101010);

    // redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_rdcnt(ADD,32307)
    assign redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_a = {1'b0, redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_wraddr_q};
    assign redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_b = {1'b0, redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_o <= $unsigned(redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_a) + $unsigned(redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_b);
        end
    end
    assign redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_q = redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_o[8:0];

    // redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_inputreg0(DELAY,32302)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl);
        end
    end

    // redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_wraddr(COUNTER,32305)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_wraddr_i <= $unsigned(redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_wraddr_q = redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_wraddr_i[7:0];

    // redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem(DUALMEM,32304)
    assign redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_ia = $unsigned(redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_inputreg0_q);
    assign redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_aa = redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_wraddr_q;
    assign redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_ab = redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_aa),
        .data_a(redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_ab),
        .q_b(redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_q = redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_iq[15:0];

    // redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_outputreg0(DELAY,32303)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_outputreg0_q <= $unsigned(redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_mem_q);
        end
    end

    // redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_rdcnt(ADD,30859)
    assign redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_a = {1'b0, redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_wraddr_q};
    assign redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_b = {1'b0, redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_o <= $unsigned(redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_a) + $unsigned(redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_b);
        end
    end
    assign redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_q = redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_o[8:0];

    // redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_inputreg0(DELAY,30854)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl);
        end
    end

    // redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_wraddr(COUNTER,30857)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_wraddr_i <= $unsigned(redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_wraddr_q = redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_wraddr_i[7:0];

    // redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem(DUALMEM,30856)
    assign redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_ia = $unsigned(redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_inputreg0_q);
    assign redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_aa = redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_wraddr_q;
    assign redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_ab = redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_aa),
        .data_a(redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_ab),
        .q_b(redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_q = redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_iq[15:0];

    // redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_outputreg0(DELAY,30855)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_outputreg0_q <= $unsigned(redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_mem_q);
        end
    end

    // redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_rdcnt(ADD,30865)
    assign redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_a = {1'b0, redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_wraddr_q};
    assign redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_b = {1'b0, redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_o <= $unsigned(redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_a) + $unsigned(redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_b);
        end
    end
    assign redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_q = redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_o[8:0];

    // redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_inputreg0(DELAY,30860)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl);
        end
    end

    // redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_wraddr(COUNTER,30863)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_wraddr_i <= $unsigned(redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_wraddr_q = redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_wraddr_i[7:0];

    // redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem(DUALMEM,30862)
    assign redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_ia = $unsigned(redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_inputreg0_q);
    assign redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_aa = redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_wraddr_q;
    assign redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_ab = redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_aa),
        .data_a(redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_ab),
        .q_b(redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_q = redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_iq[15:0];

    // redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_outputreg0(DELAY,30861)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_outputreg0_q <= $unsigned(redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_mem_q);
        end
    end

    // redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_rdcnt(ADD,32301)
    assign redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_a = {1'b0, redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_wraddr_q};
    assign redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_b = {1'b0, redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_o <= $unsigned(redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_a) + $unsigned(redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_b);
        end
    end
    assign redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_q = redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_o[8:0];

    // redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_inputreg0(DELAY,32296)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl);
        end
    end

    // redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_wraddr(COUNTER,32299)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_wraddr_i <= $unsigned(redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_wraddr_q = redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_wraddr_i[7:0];

    // redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem(DUALMEM,32298)
    assign redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_ia = $unsigned(redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_inputreg0_q);
    assign redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_aa = redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_wraddr_q;
    assign redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_ab = redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_aa),
        .data_a(redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_ab),
        .q_b(redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_q = redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_iq[15:0];

    // redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_outputreg0(DELAY,32297)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_outputreg0_q <= $unsigned(redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28072)@227 + 5
    // out q@233
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116(ADD,8533)@233
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod591_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_b = $unsigned({{5{i_shl_i_i_i_i_i_i_110_c_compstr3115_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_110_c_compstr3115_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_o[33:0];

    // rightShiftStage0_uid21789_dupName_441_i_unnamed_c_compstr0_shift_x(MUX,21788)@233
    assign rightShiftStage0_uid21789_dupName_441_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21789_dupName_441_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_q or rightShiftStage0Idx1_uid21787_dupName_441_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21789_dupName_441_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21789_dupName_441_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_q;
            1'b1 : rightShiftStage0_uid21789_dupName_441_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21787_dupName_441_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21789_dupName_441_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21794_dupName_441_i_unnamed_c_compstr0_shift_x(MUX,21793)@233
    assign rightShiftStage1_uid21794_dupName_441_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21794_dupName_441_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21789_dupName_441_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21792_dupName_441_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21794_dupName_441_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21794_dupName_441_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21789_dupName_441_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21794_dupName_441_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21792_dupName_441_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21794_dupName_441_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21799_dupName_441_i_unnamed_c_compstr0_shift_x(MUX,21798)@233
    assign rightShiftStage2_uid21799_dupName_441_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21799_dupName_441_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21794_dupName_441_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21797_dupName_441_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21799_dupName_441_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21799_dupName_441_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21794_dupName_441_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21799_dupName_441_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21797_dupName_441_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21799_dupName_441_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3117_vt_select_20(BITSELECT,11642)@233
    assign i_unnamed_c_compstr3117_vt_select_20_b = rightShiftStage2_uid21799_dupName_441_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3117_vt_join(BITJOIN,11641)@233
    assign i_unnamed_c_compstr3117_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3117_vt_select_20_b};

    // i_conv_i_i_i_i_i_110_c_compstr3118_sel_x(BITSELECT,3724)@233
    assign i_conv_i_i_i_i_i_110_c_compstr3118_sel_x_b = i_unnamed_c_compstr3117_vt_join_q[15:0];

    // redist1141_i_conv_i_i_i_i_i_110_c_compstr3118_sel_x_b_1(DELAY,29369)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1141_i_conv_i_i_i_i_i_110_c_compstr3118_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_110_c_compstr3118_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21808_dupName_442_i_unnamed_c_compstr0_shift_x(BITSELECT,21807)@233
    assign rightShiftStage1Idx1Rng8_uid21808_dupName_442_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21807_dupName_442_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21810_dupName_442_i_unnamed_c_compstr0_shift_x(BITJOIN,21809)@233
    assign rightShiftStage1Idx1_uid21810_dupName_442_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21808_dupName_442_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21803_dupName_442_i_unnamed_c_compstr0_shift_x(BITSELECT,21802)@233
    assign rightShiftStage0Idx1Rng4_uid21803_dupName_442_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_q[33:4];

    // rightShiftStage0Idx1_uid21805_dupName_442_i_unnamed_c_compstr0_shift_x(BITJOIN,21804)@233
    assign rightShiftStage0Idx1_uid21805_dupName_442_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21803_dupName_442_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21807_dupName_442_i_unnamed_c_compstr0_shift_x(MUX,21806)@233
    assign rightShiftStage0_uid21807_dupName_442_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21807_dupName_442_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_q or rightShiftStage0Idx1_uid21805_dupName_442_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21807_dupName_442_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21807_dupName_442_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compstr3116_q;
            1'b1 : rightShiftStage0_uid21807_dupName_442_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21805_dupName_442_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21807_dupName_442_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21812_dupName_442_i_unnamed_c_compstr0_shift_x(MUX,21811)@233
    assign rightShiftStage1_uid21812_dupName_442_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21812_dupName_442_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21807_dupName_442_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21810_dupName_442_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21812_dupName_442_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21812_dupName_442_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21807_dupName_442_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21812_dupName_442_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21810_dupName_442_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21812_dupName_442_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3119_vt_select_21(BITSELECT,11645)@233
    assign i_unnamed_c_compstr3119_vt_select_21_b = rightShiftStage1_uid21812_dupName_442_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3119_vt_join(BITJOIN,11644)@233
    assign i_unnamed_c_compstr3119_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3119_vt_select_21_b};

    // i_unnamed_c_compstr3120_sel_x(BITSELECT,6202)@233
    assign i_unnamed_c_compstr3120_sel_x_b = i_unnamed_c_compstr3119_vt_join_q[15:0];

    // i_unnamed_c_compstr3121_BitSelect_for_a(BITSELECT,27793)@233
    assign i_unnamed_c_compstr3121_BitSelect_for_a_b = i_unnamed_c_compstr3120_sel_x_b[0:0];

    // i_unnamed_c_compstr3121_join(BITJOIN,27794)@233
    assign i_unnamed_c_compstr3121_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3121_BitSelect_for_a_b};

    // i_unnamed_c_compstr3121_vt_select_0(BITSELECT,11650)@233
    assign i_unnamed_c_compstr3121_vt_select_0_b = i_unnamed_c_compstr3121_join_q[0:0];

    // redist89_i_unnamed_c_compstr3121_vt_select_0_b_1(DELAY,28317)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist89_i_unnamed_c_compstr3121_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3121_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3121_vt_join(BITJOIN,11649)@234
    assign i_unnamed_c_compstr3121_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist89_i_unnamed_c_compstr3121_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_110_c_compstr3122(ADD,6991)@234
    assign i_add_i_i_i_i_i_i_110_c_compstr3122_a = {1'b0, i_unnamed_c_compstr3121_vt_join_q};
    assign i_add_i_i_i_i_i_i_110_c_compstr3122_b = {1'b0, redist1141_i_conv_i_i_i_i_i_110_c_compstr3118_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_110_c_compstr3122_o = $unsigned(i_add_i_i_i_i_i_i_110_c_compstr3122_a) + $unsigned(i_add_i_i_i_i_i_i_110_c_compstr3122_b);
    assign i_add_i_i_i_i_i_i_110_c_compstr3122_q = i_add_i_i_i_i_i_i_110_c_compstr3122_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_110_c_compstr3122_sel_x(BITSELECT,2185)@234
    assign bgTrunc_i_add_i_i_i_i_i_i_110_c_compstr3122_sel_x_b = i_add_i_i_i_i_i_i_110_c_compstr3122_q[15:0];

    // i_conv_i_i_i_i_i_i279_111_c_compstr3142_sel_x(BITSELECT,3853)@234
    assign i_conv_i_i_i_i_i_i279_111_c_compstr3142_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_110_c_compstr3122_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_111_c_compstr3142_vt_select_15(BITSELECT,7929)@234
    assign i_conv_i_i_i_i_i_i279_111_c_compstr3142_vt_select_15_b = i_conv_i_i_i_i_i_i279_111_c_compstr3142_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_111_c_compstr3142_vt_join(BITJOIN,7928)@234
    assign i_conv_i_i_i_i_i_i279_111_c_compstr3142_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_111_c_compstr3142_vt_select_15_b};

    // leftShiftStage0_uid25376_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x(MUX,25375)@234
    assign leftShiftStage0_uid25376_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25376_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_111_c_compstr3142_vt_join_q or leftShiftStage0Idx1_uid25374_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25376_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25376_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_111_c_compstr3142_vt_join_q;
            1'b1 : leftShiftStage0_uid25376_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25374_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25376_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25381_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x(MUX,25380)@234
    assign leftShiftStage1_uid25381_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25381_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_s or leftShiftStage0_uid25376_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25379_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25381_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25381_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q = leftShiftStage0_uid25376_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25381_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25379_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25381_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25386_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x(MUX,25385)@234
    assign leftShiftStage2_uid25386_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25386_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_s or leftShiftStage1_uid25381_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25384_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25386_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25386_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q = leftShiftStage1_uid25381_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25386_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25384_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25386_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_111_c_compstr3143_vt_select_28(BITSELECT,9460)@234
    assign i_shl_i_i_i_i_i_i_111_c_compstr3143_vt_select_28_b = leftShiftStage2_uid25386_i_shl_i_i_i_i_i_i_111_c_compstr0_shift_x_q[28:13];

    // redist370_i_shl_i_i_i_i_i_i_111_c_compstr3143_vt_select_28_b_1(DELAY,28598)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist370_i_shl_i_i_i_i_i_i_111_c_compstr3143_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_111_c_compstr3143_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_111_c_compstr3143_vt_join(BITJOIN,9459)@235
    assign i_shl_i_i_i_i_i_i_111_c_compstr3143_vt_join_q = {redist370_i_shl_i_i_i_i_i_i_111_c_compstr3143_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_offset(CONSTANT,30870)
    assign redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_offset_q = $unsigned(8'b00101000);

    // redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_rdcnt(ADD,32319)
    assign redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_a = {1'b0, redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_wraddr_q};
    assign redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_b = {1'b0, redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_o <= $unsigned(redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_a) + $unsigned(redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_b);
        end
    end
    assign redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_q = redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_o[8:0];

    // redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_inputreg0(DELAY,32314)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl);
        end
    end

    // redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_wraddr(COUNTER,32317)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_wraddr_i <= $unsigned(redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_wraddr_q = redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_wraddr_i[7:0];

    // redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem(DUALMEM,32316)
    assign redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_ia = $unsigned(redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_inputreg0_q);
    assign redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_aa = redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_wraddr_q;
    assign redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_ab = redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_aa),
        .data_a(redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_ab),
        .q_b(redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_q = redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_iq[15:0];

    // redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_outputreg0(DELAY,32315)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_outputreg0_q <= $unsigned(redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_mem_q);
        end
    end

    // redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_rdcnt(ADD,30871)
    assign redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_a = {1'b0, redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_wraddr_q};
    assign redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_b = {1'b0, redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_o <= $unsigned(redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_a) + $unsigned(redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_b);
        end
    end
    assign redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_q = redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_o[8:0];

    // redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_inputreg0(DELAY,30866)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl);
        end
    end

    // redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_wraddr(COUNTER,30869)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_wraddr_i <= $unsigned(redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_wraddr_q = redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_wraddr_i[7:0];

    // redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem(DUALMEM,30868)
    assign redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_ia = $unsigned(redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_inputreg0_q);
    assign redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_aa = redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_wraddr_q;
    assign redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_ab = redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_aa),
        .data_a(redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_ab),
        .q_b(redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_q = redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_iq[15:0];

    // redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_outputreg0(DELAY,30867)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_outputreg0_q <= $unsigned(redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_mem_q);
        end
    end

    // redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_rdcnt(ADD,30877)
    assign redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_a = {1'b0, redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_wraddr_q};
    assign redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_b = {1'b0, redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_o <= $unsigned(redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_a) + $unsigned(redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_b);
        end
    end
    assign redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_q = redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_o[8:0];

    // redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_inputreg0(DELAY,30872)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl);
        end
    end

    // redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_wraddr(COUNTER,30875)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_wraddr_i <= $unsigned(redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_wraddr_q = redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_wraddr_i[7:0];

    // redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem(DUALMEM,30874)
    assign redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_ia = $unsigned(redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_inputreg0_q);
    assign redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_aa = redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_wraddr_q;
    assign redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_ab = redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_aa),
        .data_a(redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_ab),
        .q_b(redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_q = redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_iq[15:0];

    // redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_outputreg0(DELAY,30873)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_outputreg0_q <= $unsigned(redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_mem_q);
        end
    end

    // redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_rdcnt(ADD,32313)
    assign redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_a = {1'b0, redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_wraddr_q};
    assign redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_b = {1'b0, redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_o <= $unsigned(redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_a) + $unsigned(redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_b);
        end
    end
    assign redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_q = redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_o[8:0];

    // redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_inputreg0(DELAY,32308)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl);
        end
    end

    // redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_wraddr(COUNTER,32311)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_wraddr_i <= $unsigned(redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_wraddr_q = redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_wraddr_i[7:0];

    // redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem(DUALMEM,32310)
    assign redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_ia = $unsigned(redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_inputreg0_q);
    assign redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_aa = redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_wraddr_q;
    assign redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_ab = redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_aa),
        .data_a(redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_ab),
        .q_b(redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_q = redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_iq[15:0];

    // redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_outputreg0(DELAY,32309)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_outputreg0_q <= $unsigned(redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28073)@229 + 5
    // out q@235
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144(ADD,8534)@235
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod596_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_b = $unsigned({{5{i_shl_i_i_i_i_i_i_111_c_compstr3143_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_111_c_compstr3143_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_o[33:0];

    // rightShiftStage0_uid21851_dupName_445_i_unnamed_c_compstr0_shift_x(MUX,21850)@235
    assign rightShiftStage0_uid21851_dupName_445_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21851_dupName_445_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_q or rightShiftStage0Idx1_uid21849_dupName_445_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21851_dupName_445_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21851_dupName_445_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_q;
            1'b1 : rightShiftStage0_uid21851_dupName_445_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21849_dupName_445_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21851_dupName_445_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21856_dupName_445_i_unnamed_c_compstr0_shift_x(MUX,21855)@235
    assign rightShiftStage1_uid21856_dupName_445_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21856_dupName_445_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21851_dupName_445_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21854_dupName_445_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21856_dupName_445_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21856_dupName_445_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21851_dupName_445_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21856_dupName_445_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21854_dupName_445_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21856_dupName_445_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21861_dupName_445_i_unnamed_c_compstr0_shift_x(MUX,21860)@235
    assign rightShiftStage2_uid21861_dupName_445_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21861_dupName_445_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21856_dupName_445_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21859_dupName_445_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21861_dupName_445_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21861_dupName_445_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21856_dupName_445_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21861_dupName_445_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21859_dupName_445_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21861_dupName_445_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3145_vt_select_20(BITSELECT,11664)@235
    assign i_unnamed_c_compstr3145_vt_select_20_b = rightShiftStage2_uid21861_dupName_445_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3145_vt_join(BITJOIN,11663)@235
    assign i_unnamed_c_compstr3145_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3145_vt_select_20_b};

    // i_conv_i_i_i_i_i_111_c_compstr3146_sel_x(BITSELECT,3725)@235
    assign i_conv_i_i_i_i_i_111_c_compstr3146_sel_x_b = i_unnamed_c_compstr3145_vt_join_q[15:0];

    // redist1140_i_conv_i_i_i_i_i_111_c_compstr3146_sel_x_b_1(DELAY,29368)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1140_i_conv_i_i_i_i_i_111_c_compstr3146_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_111_c_compstr3146_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21870_dupName_446_i_unnamed_c_compstr0_shift_x(BITSELECT,21869)@235
    assign rightShiftStage1Idx1Rng8_uid21870_dupName_446_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21869_dupName_446_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21872_dupName_446_i_unnamed_c_compstr0_shift_x(BITJOIN,21871)@235
    assign rightShiftStage1Idx1_uid21872_dupName_446_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21870_dupName_446_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21865_dupName_446_i_unnamed_c_compstr0_shift_x(BITSELECT,21864)@235
    assign rightShiftStage0Idx1Rng4_uid21865_dupName_446_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_q[33:4];

    // rightShiftStage0Idx1_uid21867_dupName_446_i_unnamed_c_compstr0_shift_x(BITJOIN,21866)@235
    assign rightShiftStage0Idx1_uid21867_dupName_446_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21865_dupName_446_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21869_dupName_446_i_unnamed_c_compstr0_shift_x(MUX,21868)@235
    assign rightShiftStage0_uid21869_dupName_446_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21869_dupName_446_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_q or rightShiftStage0Idx1_uid21867_dupName_446_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21869_dupName_446_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21869_dupName_446_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compstr3144_q;
            1'b1 : rightShiftStage0_uid21869_dupName_446_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21867_dupName_446_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21869_dupName_446_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21874_dupName_446_i_unnamed_c_compstr0_shift_x(MUX,21873)@235
    assign rightShiftStage1_uid21874_dupName_446_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21874_dupName_446_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21869_dupName_446_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21872_dupName_446_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21874_dupName_446_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21874_dupName_446_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21869_dupName_446_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21874_dupName_446_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21872_dupName_446_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21874_dupName_446_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3147_vt_select_21(BITSELECT,11667)@235
    assign i_unnamed_c_compstr3147_vt_select_21_b = rightShiftStage1_uid21874_dupName_446_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3147_vt_join(BITJOIN,11666)@235
    assign i_unnamed_c_compstr3147_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3147_vt_select_21_b};

    // i_unnamed_c_compstr3148_sel_x(BITSELECT,6204)@235
    assign i_unnamed_c_compstr3148_sel_x_b = i_unnamed_c_compstr3147_vt_join_q[15:0];

    // i_unnamed_c_compstr3149_BitSelect_for_a(BITSELECT,27797)@235
    assign i_unnamed_c_compstr3149_BitSelect_for_a_b = i_unnamed_c_compstr3148_sel_x_b[0:0];

    // i_unnamed_c_compstr3149_join(BITJOIN,27798)@235
    assign i_unnamed_c_compstr3149_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3149_BitSelect_for_a_b};

    // i_unnamed_c_compstr3149_vt_select_0(BITSELECT,11672)@235
    assign i_unnamed_c_compstr3149_vt_select_0_b = i_unnamed_c_compstr3149_join_q[0:0];

    // redist87_i_unnamed_c_compstr3149_vt_select_0_b_1(DELAY,28315)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist87_i_unnamed_c_compstr3149_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3149_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3149_vt_join(BITJOIN,11671)@236
    assign i_unnamed_c_compstr3149_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist87_i_unnamed_c_compstr3149_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_111_c_compstr3150(ADD,6992)@236
    assign i_add_i_i_i_i_i_i_111_c_compstr3150_a = {1'b0, i_unnamed_c_compstr3149_vt_join_q};
    assign i_add_i_i_i_i_i_i_111_c_compstr3150_b = {1'b0, redist1140_i_conv_i_i_i_i_i_111_c_compstr3146_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_111_c_compstr3150_o = $unsigned(i_add_i_i_i_i_i_i_111_c_compstr3150_a) + $unsigned(i_add_i_i_i_i_i_i_111_c_compstr3150_b);
    assign i_add_i_i_i_i_i_i_111_c_compstr3150_q = i_add_i_i_i_i_i_i_111_c_compstr3150_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_111_c_compstr3150_sel_x(BITSELECT,2186)@236
    assign bgTrunc_i_add_i_i_i_i_i_i_111_c_compstr3150_sel_x_b = i_add_i_i_i_i_i_i_111_c_compstr3150_q[15:0];

    // i_conv_i_i_i_i_i_i279_112_c_compstr3170_sel_x(BITSELECT,3854)@236
    assign i_conv_i_i_i_i_i_i279_112_c_compstr3170_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_111_c_compstr3150_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_112_c_compstr3170_vt_select_15(BITSELECT,7933)@236
    assign i_conv_i_i_i_i_i_i279_112_c_compstr3170_vt_select_15_b = i_conv_i_i_i_i_i_i279_112_c_compstr3170_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_112_c_compstr3170_vt_join(BITJOIN,7932)@236
    assign i_conv_i_i_i_i_i_i279_112_c_compstr3170_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_112_c_compstr3170_vt_select_15_b};

    // leftShiftStage0_uid25394_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x(MUX,25393)@236
    assign leftShiftStage0_uid25394_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25394_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_112_c_compstr3170_vt_join_q or leftShiftStage0Idx1_uid25392_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25394_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25394_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_112_c_compstr3170_vt_join_q;
            1'b1 : leftShiftStage0_uid25394_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25392_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25394_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25399_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x(MUX,25398)@236
    assign leftShiftStage1_uid25399_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25399_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_s or leftShiftStage0_uid25394_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25397_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25399_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25399_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q = leftShiftStage0_uid25394_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25399_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25397_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25399_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25404_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x(MUX,25403)@236
    assign leftShiftStage2_uid25404_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25404_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_s or leftShiftStage1_uid25399_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25402_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25404_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25404_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q = leftShiftStage1_uid25399_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25404_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25402_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25404_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_112_c_compstr3171_vt_select_28(BITSELECT,9463)@236
    assign i_shl_i_i_i_i_i_i_112_c_compstr3171_vt_select_28_b = leftShiftStage2_uid25404_i_shl_i_i_i_i_i_i_112_c_compstr0_shift_x_q[28:13];

    // redist369_i_shl_i_i_i_i_i_i_112_c_compstr3171_vt_select_28_b_1(DELAY,28597)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist369_i_shl_i_i_i_i_i_i_112_c_compstr3171_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_112_c_compstr3171_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_112_c_compstr3171_vt_join(BITJOIN,9462)@237
    assign i_shl_i_i_i_i_i_i_112_c_compstr3171_vt_join_q = {redist369_i_shl_i_i_i_i_i_i_112_c_compstr3171_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_offset(CONSTANT,30882)
    assign redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_offset_q = $unsigned(8'b00100110);

    // redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_rdcnt(ADD,32331)
    assign redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_a = {1'b0, redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_wraddr_q};
    assign redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_b = {1'b0, redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_o <= $unsigned(redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_a) + $unsigned(redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_b);
        end
    end
    assign redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_q = redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_o[8:0];

    // redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_inputreg0(DELAY,32326)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl);
        end
    end

    // redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_wraddr(COUNTER,32329)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_wraddr_i <= $unsigned(redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_wraddr_q = redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_wraddr_i[7:0];

    // redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem(DUALMEM,32328)
    assign redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_ia = $unsigned(redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_inputreg0_q);
    assign redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_aa = redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_wraddr_q;
    assign redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_ab = redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_aa),
        .data_a(redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_ab),
        .q_b(redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_q = redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_iq[15:0];

    // redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_outputreg0(DELAY,32327)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_outputreg0_q <= $unsigned(redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_mem_q);
        end
    end

    // redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_rdcnt(ADD,30883)
    assign redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_a = {1'b0, redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_wraddr_q};
    assign redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_b = {1'b0, redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_o <= $unsigned(redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_a) + $unsigned(redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_b);
        end
    end
    assign redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_q = redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_o[8:0];

    // redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_inputreg0(DELAY,30878)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl);
        end
    end

    // redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_wraddr(COUNTER,30881)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_wraddr_i <= $unsigned(redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_wraddr_q = redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_wraddr_i[7:0];

    // redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem(DUALMEM,30880)
    assign redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_ia = $unsigned(redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_inputreg0_q);
    assign redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_aa = redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_wraddr_q;
    assign redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_ab = redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_aa),
        .data_a(redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_ab),
        .q_b(redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_q = redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_iq[15:0];

    // redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_outputreg0(DELAY,30879)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_outputreg0_q <= $unsigned(redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_mem_q);
        end
    end

    // redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_rdcnt(ADD,30889)
    assign redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_a = {1'b0, redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_wraddr_q};
    assign redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_b = {1'b0, redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_o <= $unsigned(redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_a) + $unsigned(redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_b);
        end
    end
    assign redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_q = redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_o[8:0];

    // redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_inputreg0(DELAY,30884)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl);
        end
    end

    // redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_wraddr(COUNTER,30887)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_wraddr_i <= $unsigned(redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_wraddr_q = redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_wraddr_i[7:0];

    // redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem(DUALMEM,30886)
    assign redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_ia = $unsigned(redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_inputreg0_q);
    assign redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_aa = redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_wraddr_q;
    assign redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_ab = redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_aa),
        .data_a(redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_ab),
        .q_b(redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_q = redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_iq[15:0];

    // redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_outputreg0(DELAY,30885)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_outputreg0_q <= $unsigned(redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_mem_q);
        end
    end

    // redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_rdcnt(ADD,32325)
    assign redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_a = {1'b0, redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_wraddr_q};
    assign redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_b = {1'b0, redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_o <= $unsigned(redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_a) + $unsigned(redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_b);
        end
    end
    assign redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_q = redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_o[8:0];

    // redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_inputreg0(DELAY,32320)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl);
        end
    end

    // redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_wraddr(COUNTER,32323)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_wraddr_i <= $unsigned(redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_wraddr_q = redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_wraddr_i[7:0];

    // redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem(DUALMEM,32322)
    assign redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_ia = $unsigned(redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_inputreg0_q);
    assign redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_aa = redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_wraddr_q;
    assign redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_ab = redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_aa),
        .data_a(redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_ab),
        .q_b(redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_q = redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_iq[15:0];

    // redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_outputreg0(DELAY,32321)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_outputreg0_q <= $unsigned(redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28074)@231 + 5
    // out q@237
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172(ADD,8535)@237
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod601_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_b = $unsigned({{5{i_shl_i_i_i_i_i_i_112_c_compstr3171_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_112_c_compstr3171_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_o[33:0];

    // rightShiftStage0_uid21913_dupName_449_i_unnamed_c_compstr0_shift_x(MUX,21912)@237
    assign rightShiftStage0_uid21913_dupName_449_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21913_dupName_449_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_q or rightShiftStage0Idx1_uid21911_dupName_449_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21913_dupName_449_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21913_dupName_449_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_q;
            1'b1 : rightShiftStage0_uid21913_dupName_449_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21911_dupName_449_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21913_dupName_449_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21918_dupName_449_i_unnamed_c_compstr0_shift_x(MUX,21917)@237
    assign rightShiftStage1_uid21918_dupName_449_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21918_dupName_449_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21913_dupName_449_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21916_dupName_449_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21918_dupName_449_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21918_dupName_449_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21913_dupName_449_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21918_dupName_449_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21916_dupName_449_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21918_dupName_449_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21923_dupName_449_i_unnamed_c_compstr0_shift_x(MUX,21922)@237
    assign rightShiftStage2_uid21923_dupName_449_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21923_dupName_449_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21918_dupName_449_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21921_dupName_449_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21923_dupName_449_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21923_dupName_449_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21918_dupName_449_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21923_dupName_449_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21921_dupName_449_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21923_dupName_449_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3173_vt_select_20(BITSELECT,11686)@237
    assign i_unnamed_c_compstr3173_vt_select_20_b = rightShiftStage2_uid21923_dupName_449_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3173_vt_join(BITJOIN,11685)@237
    assign i_unnamed_c_compstr3173_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3173_vt_select_20_b};

    // i_conv_i_i_i_i_i_112_c_compstr3174_sel_x(BITSELECT,3726)@237
    assign i_conv_i_i_i_i_i_112_c_compstr3174_sel_x_b = i_unnamed_c_compstr3173_vt_join_q[15:0];

    // redist1139_i_conv_i_i_i_i_i_112_c_compstr3174_sel_x_b_1(DELAY,29367)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1139_i_conv_i_i_i_i_i_112_c_compstr3174_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_112_c_compstr3174_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21932_dupName_450_i_unnamed_c_compstr0_shift_x(BITSELECT,21931)@237
    assign rightShiftStage1Idx1Rng8_uid21932_dupName_450_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21931_dupName_450_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21934_dupName_450_i_unnamed_c_compstr0_shift_x(BITJOIN,21933)@237
    assign rightShiftStage1Idx1_uid21934_dupName_450_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21932_dupName_450_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21927_dupName_450_i_unnamed_c_compstr0_shift_x(BITSELECT,21926)@237
    assign rightShiftStage0Idx1Rng4_uid21927_dupName_450_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_q[33:4];

    // rightShiftStage0Idx1_uid21929_dupName_450_i_unnamed_c_compstr0_shift_x(BITJOIN,21928)@237
    assign rightShiftStage0Idx1_uid21929_dupName_450_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21927_dupName_450_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21931_dupName_450_i_unnamed_c_compstr0_shift_x(MUX,21930)@237
    assign rightShiftStage0_uid21931_dupName_450_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21931_dupName_450_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_q or rightShiftStage0Idx1_uid21929_dupName_450_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21931_dupName_450_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21931_dupName_450_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compstr3172_q;
            1'b1 : rightShiftStage0_uid21931_dupName_450_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21929_dupName_450_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21931_dupName_450_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21936_dupName_450_i_unnamed_c_compstr0_shift_x(MUX,21935)@237
    assign rightShiftStage1_uid21936_dupName_450_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21936_dupName_450_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21931_dupName_450_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21934_dupName_450_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21936_dupName_450_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21936_dupName_450_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21931_dupName_450_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21936_dupName_450_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21934_dupName_450_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21936_dupName_450_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3175_vt_select_21(BITSELECT,11689)@237
    assign i_unnamed_c_compstr3175_vt_select_21_b = rightShiftStage1_uid21936_dupName_450_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3175_vt_join(BITJOIN,11688)@237
    assign i_unnamed_c_compstr3175_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3175_vt_select_21_b};

    // i_unnamed_c_compstr3176_sel_x(BITSELECT,6206)@237
    assign i_unnamed_c_compstr3176_sel_x_b = i_unnamed_c_compstr3175_vt_join_q[15:0];

    // i_unnamed_c_compstr3177_BitSelect_for_a(BITSELECT,27801)@237
    assign i_unnamed_c_compstr3177_BitSelect_for_a_b = i_unnamed_c_compstr3176_sel_x_b[0:0];

    // i_unnamed_c_compstr3177_join(BITJOIN,27802)@237
    assign i_unnamed_c_compstr3177_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3177_BitSelect_for_a_b};

    // i_unnamed_c_compstr3177_vt_select_0(BITSELECT,11694)@237
    assign i_unnamed_c_compstr3177_vt_select_0_b = i_unnamed_c_compstr3177_join_q[0:0];

    // redist85_i_unnamed_c_compstr3177_vt_select_0_b_1(DELAY,28313)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist85_i_unnamed_c_compstr3177_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3177_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3177_vt_join(BITJOIN,11693)@238
    assign i_unnamed_c_compstr3177_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist85_i_unnamed_c_compstr3177_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_112_c_compstr3178(ADD,6993)@238
    assign i_add_i_i_i_i_i_i_112_c_compstr3178_a = {1'b0, i_unnamed_c_compstr3177_vt_join_q};
    assign i_add_i_i_i_i_i_i_112_c_compstr3178_b = {1'b0, redist1139_i_conv_i_i_i_i_i_112_c_compstr3174_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_112_c_compstr3178_o = $unsigned(i_add_i_i_i_i_i_i_112_c_compstr3178_a) + $unsigned(i_add_i_i_i_i_i_i_112_c_compstr3178_b);
    assign i_add_i_i_i_i_i_i_112_c_compstr3178_q = i_add_i_i_i_i_i_i_112_c_compstr3178_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_112_c_compstr3178_sel_x(BITSELECT,2187)@238
    assign bgTrunc_i_add_i_i_i_i_i_i_112_c_compstr3178_sel_x_b = i_add_i_i_i_i_i_i_112_c_compstr3178_q[15:0];

    // i_conv_i_i_i_i_i_i279_113_c_compstr3198_sel_x(BITSELECT,3855)@238
    assign i_conv_i_i_i_i_i_i279_113_c_compstr3198_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_112_c_compstr3178_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_113_c_compstr3198_vt_select_15(BITSELECT,7937)@238
    assign i_conv_i_i_i_i_i_i279_113_c_compstr3198_vt_select_15_b = i_conv_i_i_i_i_i_i279_113_c_compstr3198_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_113_c_compstr3198_vt_join(BITJOIN,7936)@238
    assign i_conv_i_i_i_i_i_i279_113_c_compstr3198_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_113_c_compstr3198_vt_select_15_b};

    // leftShiftStage0_uid25412_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x(MUX,25411)@238
    assign leftShiftStage0_uid25412_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25412_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_113_c_compstr3198_vt_join_q or leftShiftStage0Idx1_uid25410_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25412_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25412_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_113_c_compstr3198_vt_join_q;
            1'b1 : leftShiftStage0_uid25412_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25410_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25412_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25417_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x(MUX,25416)@238
    assign leftShiftStage1_uid25417_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25417_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_s or leftShiftStage0_uid25412_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25415_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25417_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25417_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q = leftShiftStage0_uid25412_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25417_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25415_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25417_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25422_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x(MUX,25421)@238
    assign leftShiftStage2_uid25422_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25422_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_s or leftShiftStage1_uid25417_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25420_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25422_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25422_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q = leftShiftStage1_uid25417_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25422_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25420_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25422_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_113_c_compstr3199_vt_select_28(BITSELECT,9466)@238
    assign i_shl_i_i_i_i_i_i_113_c_compstr3199_vt_select_28_b = leftShiftStage2_uid25422_i_shl_i_i_i_i_i_i_113_c_compstr0_shift_x_q[28:13];

    // redist368_i_shl_i_i_i_i_i_i_113_c_compstr3199_vt_select_28_b_1(DELAY,28596)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist368_i_shl_i_i_i_i_i_i_113_c_compstr3199_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_113_c_compstr3199_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_113_c_compstr3199_vt_join(BITJOIN,9465)@239
    assign i_shl_i_i_i_i_i_i_113_c_compstr3199_vt_join_q = {redist368_i_shl_i_i_i_i_i_i_113_c_compstr3199_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_offset(CONSTANT,30894)
    assign redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_offset_q = $unsigned(8'b00100100);

    // redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_rdcnt(ADD,32343)
    assign redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_a = {1'b0, redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_wraddr_q};
    assign redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_b = {1'b0, redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_o <= $unsigned(redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_a) + $unsigned(redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_b);
        end
    end
    assign redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_q = redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_o[8:0];

    // redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_inputreg0(DELAY,32338)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl);
        end
    end

    // redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_wraddr(COUNTER,32341)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_wraddr_i <= $unsigned(redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_wraddr_q = redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_wraddr_i[7:0];

    // redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem(DUALMEM,32340)
    assign redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_ia = $unsigned(redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_inputreg0_q);
    assign redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_aa = redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_wraddr_q;
    assign redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_ab = redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_aa),
        .data_a(redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_ab),
        .q_b(redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_q = redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_iq[15:0];

    // redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_outputreg0(DELAY,32339)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_outputreg0_q <= $unsigned(redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_mem_q);
        end
    end

    // redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_rdcnt(ADD,30895)
    assign redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_a = {1'b0, redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_wraddr_q};
    assign redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_b = {1'b0, redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_o <= $unsigned(redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_a) + $unsigned(redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_b);
        end
    end
    assign redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_q = redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_o[8:0];

    // redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_inputreg0(DELAY,30890)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl);
        end
    end

    // redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_wraddr(COUNTER,30893)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_wraddr_i <= $unsigned(redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_wraddr_q = redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_wraddr_i[7:0];

    // redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem(DUALMEM,30892)
    assign redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_ia = $unsigned(redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_inputreg0_q);
    assign redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_aa = redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_wraddr_q;
    assign redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_ab = redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_aa),
        .data_a(redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_ab),
        .q_b(redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_q = redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_iq[15:0];

    // redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_outputreg0(DELAY,30891)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_outputreg0_q <= $unsigned(redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_mem_q);
        end
    end

    // redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_rdcnt(ADD,30901)
    assign redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_a = {1'b0, redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_wraddr_q};
    assign redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_b = {1'b0, redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_o <= $unsigned(redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_a) + $unsigned(redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_b);
        end
    end
    assign redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_q = redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_o[8:0];

    // redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_inputreg0(DELAY,30896)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl);
        end
    end

    // redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_wraddr(COUNTER,30899)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_wraddr_i <= $unsigned(redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_wraddr_q = redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_wraddr_i[7:0];

    // redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem(DUALMEM,30898)
    assign redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_ia = $unsigned(redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_inputreg0_q);
    assign redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_aa = redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_wraddr_q;
    assign redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_ab = redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_aa),
        .data_a(redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_ab),
        .q_b(redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_q = redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_iq[15:0];

    // redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_outputreg0(DELAY,30897)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_outputreg0_q <= $unsigned(redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_mem_q);
        end
    end

    // redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_rdcnt(ADD,32337)
    assign redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_a = {1'b0, redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_wraddr_q};
    assign redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_b = {1'b0, redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_o <= $unsigned(redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_a) + $unsigned(redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_b);
        end
    end
    assign redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_q = redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_o[8:0];

    // redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_inputreg0(DELAY,32332)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl);
        end
    end

    // redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_wraddr(COUNTER,32335)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_wraddr_i <= $unsigned(redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_wraddr_q = redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_wraddr_i[7:0];

    // redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem(DUALMEM,32334)
    assign redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_ia = $unsigned(redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_inputreg0_q);
    assign redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_aa = redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_wraddr_q;
    assign redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_ab = redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_aa),
        .data_a(redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_ab),
        .q_b(redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_q = redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_iq[15:0];

    // redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_outputreg0(DELAY,32333)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_outputreg0_q <= $unsigned(redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28075)@233 + 5
    // out q@239
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200(ADD,8536)@239
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod606_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_b = $unsigned({{5{i_shl_i_i_i_i_i_i_113_c_compstr3199_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_113_c_compstr3199_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_o[33:0];

    // rightShiftStage0_uid21975_dupName_453_i_unnamed_c_compstr0_shift_x(MUX,21974)@239
    assign rightShiftStage0_uid21975_dupName_453_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21975_dupName_453_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_q or rightShiftStage0Idx1_uid21973_dupName_453_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21975_dupName_453_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21975_dupName_453_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_q;
            1'b1 : rightShiftStage0_uid21975_dupName_453_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21973_dupName_453_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21975_dupName_453_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21980_dupName_453_i_unnamed_c_compstr0_shift_x(MUX,21979)@239
    assign rightShiftStage1_uid21980_dupName_453_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21980_dupName_453_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21975_dupName_453_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21978_dupName_453_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21980_dupName_453_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21980_dupName_453_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21975_dupName_453_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21980_dupName_453_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21978_dupName_453_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21980_dupName_453_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21985_dupName_453_i_unnamed_c_compstr0_shift_x(MUX,21984)@239
    assign rightShiftStage2_uid21985_dupName_453_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21985_dupName_453_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21980_dupName_453_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21983_dupName_453_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21985_dupName_453_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21985_dupName_453_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21980_dupName_453_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21985_dupName_453_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21983_dupName_453_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21985_dupName_453_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3201_vt_select_20(BITSELECT,11714)@239
    assign i_unnamed_c_compstr3201_vt_select_20_b = rightShiftStage2_uid21985_dupName_453_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3201_vt_join(BITJOIN,11713)@239
    assign i_unnamed_c_compstr3201_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3201_vt_select_20_b};

    // i_conv_i_i_i_i_i_113_c_compstr3202_sel_x(BITSELECT,3727)@239
    assign i_conv_i_i_i_i_i_113_c_compstr3202_sel_x_b = i_unnamed_c_compstr3201_vt_join_q[15:0];

    // redist1138_i_conv_i_i_i_i_i_113_c_compstr3202_sel_x_b_1(DELAY,29366)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1138_i_conv_i_i_i_i_i_113_c_compstr3202_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_113_c_compstr3202_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21994_dupName_454_i_unnamed_c_compstr0_shift_x(BITSELECT,21993)@239
    assign rightShiftStage1Idx1Rng8_uid21994_dupName_454_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21993_dupName_454_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21996_dupName_454_i_unnamed_c_compstr0_shift_x(BITJOIN,21995)@239
    assign rightShiftStage1Idx1_uid21996_dupName_454_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21994_dupName_454_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21989_dupName_454_i_unnamed_c_compstr0_shift_x(BITSELECT,21988)@239
    assign rightShiftStage0Idx1Rng4_uid21989_dupName_454_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_q[33:4];

    // rightShiftStage0Idx1_uid21991_dupName_454_i_unnamed_c_compstr0_shift_x(BITJOIN,21990)@239
    assign rightShiftStage0Idx1_uid21991_dupName_454_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21989_dupName_454_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21993_dupName_454_i_unnamed_c_compstr0_shift_x(MUX,21992)@239
    assign rightShiftStage0_uid21993_dupName_454_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21993_dupName_454_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_q or rightShiftStage0Idx1_uid21991_dupName_454_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21993_dupName_454_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21993_dupName_454_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compstr3200_q;
            1'b1 : rightShiftStage0_uid21993_dupName_454_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21991_dupName_454_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21993_dupName_454_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21998_dupName_454_i_unnamed_c_compstr0_shift_x(MUX,21997)@239
    assign rightShiftStage1_uid21998_dupName_454_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21998_dupName_454_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21993_dupName_454_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21996_dupName_454_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21998_dupName_454_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21998_dupName_454_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21993_dupName_454_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21998_dupName_454_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21996_dupName_454_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21998_dupName_454_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3203_vt_select_21(BITSELECT,11717)@239
    assign i_unnamed_c_compstr3203_vt_select_21_b = rightShiftStage1_uid21998_dupName_454_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3203_vt_join(BITJOIN,11716)@239
    assign i_unnamed_c_compstr3203_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3203_vt_select_21_b};

    // i_unnamed_c_compstr3204_sel_x(BITSELECT,6209)@239
    assign i_unnamed_c_compstr3204_sel_x_b = i_unnamed_c_compstr3203_vt_join_q[15:0];

    // i_unnamed_c_compstr3205_BitSelect_for_a(BITSELECT,27805)@239
    assign i_unnamed_c_compstr3205_BitSelect_for_a_b = i_unnamed_c_compstr3204_sel_x_b[0:0];

    // i_unnamed_c_compstr3205_join(BITJOIN,27806)@239
    assign i_unnamed_c_compstr3205_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3205_BitSelect_for_a_b};

    // i_unnamed_c_compstr3205_vt_select_0(BITSELECT,11722)@239
    assign i_unnamed_c_compstr3205_vt_select_0_b = i_unnamed_c_compstr3205_join_q[0:0];

    // redist83_i_unnamed_c_compstr3205_vt_select_0_b_1(DELAY,28311)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist83_i_unnamed_c_compstr3205_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3205_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3205_vt_join(BITJOIN,11721)@240
    assign i_unnamed_c_compstr3205_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist83_i_unnamed_c_compstr3205_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_113_c_compstr3206(ADD,6994)@240
    assign i_add_i_i_i_i_i_i_113_c_compstr3206_a = {1'b0, i_unnamed_c_compstr3205_vt_join_q};
    assign i_add_i_i_i_i_i_i_113_c_compstr3206_b = {1'b0, redist1138_i_conv_i_i_i_i_i_113_c_compstr3202_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_113_c_compstr3206_o = $unsigned(i_add_i_i_i_i_i_i_113_c_compstr3206_a) + $unsigned(i_add_i_i_i_i_i_i_113_c_compstr3206_b);
    assign i_add_i_i_i_i_i_i_113_c_compstr3206_q = i_add_i_i_i_i_i_i_113_c_compstr3206_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_113_c_compstr3206_sel_x(BITSELECT,2188)@240
    assign bgTrunc_i_add_i_i_i_i_i_i_113_c_compstr3206_sel_x_b = i_add_i_i_i_i_i_i_113_c_compstr3206_q[15:0];

    // i_conv_i_i_i_i_i_i279_114_c_compstr3226_sel_x(BITSELECT,3856)@240
    assign i_conv_i_i_i_i_i_i279_114_c_compstr3226_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_113_c_compstr3206_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_114_c_compstr3226_vt_select_15(BITSELECT,7941)@240
    assign i_conv_i_i_i_i_i_i279_114_c_compstr3226_vt_select_15_b = i_conv_i_i_i_i_i_i279_114_c_compstr3226_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_114_c_compstr3226_vt_join(BITJOIN,7940)@240
    assign i_conv_i_i_i_i_i_i279_114_c_compstr3226_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_114_c_compstr3226_vt_select_15_b};

    // leftShiftStage0_uid25430_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x(MUX,25429)@240
    assign leftShiftStage0_uid25430_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25430_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_114_c_compstr3226_vt_join_q or leftShiftStage0Idx1_uid25428_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25430_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25430_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_114_c_compstr3226_vt_join_q;
            1'b1 : leftShiftStage0_uid25430_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25428_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25430_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25435_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x(MUX,25434)@240
    assign leftShiftStage1_uid25435_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25435_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_s or leftShiftStage0_uid25430_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25433_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25435_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25435_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q = leftShiftStage0_uid25430_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25435_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25433_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25435_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25440_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x(MUX,25439)@240
    assign leftShiftStage2_uid25440_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25440_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_s or leftShiftStage1_uid25435_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25438_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25440_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25440_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q = leftShiftStage1_uid25435_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25440_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25438_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25440_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_114_c_compstr3227_vt_select_28(BITSELECT,9469)@240
    assign i_shl_i_i_i_i_i_i_114_c_compstr3227_vt_select_28_b = leftShiftStage2_uid25440_i_shl_i_i_i_i_i_i_114_c_compstr0_shift_x_q[28:13];

    // redist367_i_shl_i_i_i_i_i_i_114_c_compstr3227_vt_select_28_b_1(DELAY,28595)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist367_i_shl_i_i_i_i_i_i_114_c_compstr3227_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_114_c_compstr3227_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_114_c_compstr3227_vt_join(BITJOIN,9468)@241
    assign i_shl_i_i_i_i_i_i_114_c_compstr3227_vt_join_q = {redist367_i_shl_i_i_i_i_i_i_114_c_compstr3227_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_offset(CONSTANT,30906)
    assign redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_offset_q = $unsigned(8'b00100010);

    // redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_rdcnt(ADD,32355)
    assign redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_a = {1'b0, redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_wraddr_q};
    assign redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_b = {1'b0, redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_o <= $unsigned(redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_a) + $unsigned(redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_b);
        end
    end
    assign redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_q = redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_o[8:0];

    // redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_inputreg0(DELAY,32350)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl);
        end
    end

    // redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_wraddr(COUNTER,32353)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_wraddr_i <= $unsigned(redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_wraddr_q = redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_wraddr_i[7:0];

    // redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem(DUALMEM,32352)
    assign redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_ia = $unsigned(redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_inputreg0_q);
    assign redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_aa = redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_wraddr_q;
    assign redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_ab = redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_aa),
        .data_a(redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_ab),
        .q_b(redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_q = redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_iq[15:0];

    // redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_outputreg0(DELAY,32351)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_outputreg0_q <= $unsigned(redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_mem_q);
        end
    end

    // redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_rdcnt(ADD,30907)
    assign redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_a = {1'b0, redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_wraddr_q};
    assign redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_b = {1'b0, redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_o <= $unsigned(redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_a) + $unsigned(redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_b);
        end
    end
    assign redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_q = redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_o[8:0];

    // redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_inputreg0(DELAY,30902)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl);
        end
    end

    // redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_wraddr(COUNTER,30905)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_wraddr_i <= $unsigned(redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_wraddr_q = redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_wraddr_i[7:0];

    // redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem(DUALMEM,30904)
    assign redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_ia = $unsigned(redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_inputreg0_q);
    assign redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_aa = redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_wraddr_q;
    assign redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_ab = redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_aa),
        .data_a(redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_ab),
        .q_b(redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_q = redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_iq[15:0];

    // redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_outputreg0(DELAY,30903)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_outputreg0_q <= $unsigned(redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_mem_q);
        end
    end

    // redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_rdcnt(ADD,30913)
    assign redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_a = {1'b0, redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_wraddr_q};
    assign redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_b = {1'b0, redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_o <= $unsigned(redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_a) + $unsigned(redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_b);
        end
    end
    assign redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_q = redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_o[8:0];

    // redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_inputreg0(DELAY,30908)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl);
        end
    end

    // redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_wraddr(COUNTER,30911)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_wraddr_i <= $unsigned(redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_wraddr_q = redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_wraddr_i[7:0];

    // redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem(DUALMEM,30910)
    assign redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_ia = $unsigned(redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_inputreg0_q);
    assign redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_aa = redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_wraddr_q;
    assign redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_ab = redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_aa),
        .data_a(redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_ab),
        .q_b(redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_q = redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_iq[15:0];

    // redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_outputreg0(DELAY,30909)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_outputreg0_q <= $unsigned(redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_mem_q);
        end
    end

    // redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_rdcnt(ADD,32349)
    assign redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_a = {1'b0, redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_wraddr_q};
    assign redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_b = {1'b0, redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_o <= $unsigned(redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_a) + $unsigned(redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_b);
        end
    end
    assign redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_q = redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_o[8:0];

    // redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_inputreg0(DELAY,32344)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl);
        end
    end

    // redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_wraddr(COUNTER,32347)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_wraddr_i <= $unsigned(redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_wraddr_q = redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_wraddr_i[7:0];

    // redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem(DUALMEM,32346)
    assign redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_ia = $unsigned(redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_inputreg0_q);
    assign redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_aa = redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_wraddr_q;
    assign redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_ab = redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_aa),
        .data_a(redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_ab),
        .q_b(redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_q = redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_iq[15:0];

    // redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_outputreg0(DELAY,32345)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_outputreg0_q <= $unsigned(redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28076)@235 + 5
    // out q@241
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228(ADD,8537)@241
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod611_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_b = $unsigned({{5{i_shl_i_i_i_i_i_i_114_c_compstr3227_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_114_c_compstr3227_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_o[33:0];

    // rightShiftStage0_uid22037_dupName_457_i_unnamed_c_compstr0_shift_x(MUX,22036)@241
    assign rightShiftStage0_uid22037_dupName_457_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22037_dupName_457_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_q or rightShiftStage0Idx1_uid22035_dupName_457_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22037_dupName_457_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22037_dupName_457_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_q;
            1'b1 : rightShiftStage0_uid22037_dupName_457_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22035_dupName_457_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22037_dupName_457_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22042_dupName_457_i_unnamed_c_compstr0_shift_x(MUX,22041)@241
    assign rightShiftStage1_uid22042_dupName_457_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22042_dupName_457_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22037_dupName_457_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22040_dupName_457_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22042_dupName_457_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22042_dupName_457_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22037_dupName_457_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22042_dupName_457_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22040_dupName_457_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22042_dupName_457_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22047_dupName_457_i_unnamed_c_compstr0_shift_x(MUX,22046)@241
    assign rightShiftStage2_uid22047_dupName_457_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22047_dupName_457_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22042_dupName_457_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22045_dupName_457_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22047_dupName_457_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22047_dupName_457_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22042_dupName_457_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22047_dupName_457_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22045_dupName_457_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22047_dupName_457_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3229_vt_select_20(BITSELECT,11741)@241
    assign i_unnamed_c_compstr3229_vt_select_20_b = rightShiftStage2_uid22047_dupName_457_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3229_vt_join(BITJOIN,11740)@241
    assign i_unnamed_c_compstr3229_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3229_vt_select_20_b};

    // i_conv_i_i_i_i_i_114_c_compstr3230_sel_x(BITSELECT,3728)@241
    assign i_conv_i_i_i_i_i_114_c_compstr3230_sel_x_b = i_unnamed_c_compstr3229_vt_join_q[15:0];

    // redist1137_i_conv_i_i_i_i_i_114_c_compstr3230_sel_x_b_1(DELAY,29365)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1137_i_conv_i_i_i_i_i_114_c_compstr3230_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_114_c_compstr3230_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22056_dupName_458_i_unnamed_c_compstr0_shift_x(BITSELECT,22055)@241
    assign rightShiftStage1Idx1Rng8_uid22056_dupName_458_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22055_dupName_458_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22058_dupName_458_i_unnamed_c_compstr0_shift_x(BITJOIN,22057)@241
    assign rightShiftStage1Idx1_uid22058_dupName_458_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22056_dupName_458_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22051_dupName_458_i_unnamed_c_compstr0_shift_x(BITSELECT,22050)@241
    assign rightShiftStage0Idx1Rng4_uid22051_dupName_458_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_q[33:4];

    // rightShiftStage0Idx1_uid22053_dupName_458_i_unnamed_c_compstr0_shift_x(BITJOIN,22052)@241
    assign rightShiftStage0Idx1_uid22053_dupName_458_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22051_dupName_458_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22055_dupName_458_i_unnamed_c_compstr0_shift_x(MUX,22054)@241
    assign rightShiftStage0_uid22055_dupName_458_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22055_dupName_458_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_q or rightShiftStage0Idx1_uid22053_dupName_458_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22055_dupName_458_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22055_dupName_458_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compstr3228_q;
            1'b1 : rightShiftStage0_uid22055_dupName_458_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22053_dupName_458_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22055_dupName_458_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22060_dupName_458_i_unnamed_c_compstr0_shift_x(MUX,22059)@241
    assign rightShiftStage1_uid22060_dupName_458_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22060_dupName_458_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22055_dupName_458_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22058_dupName_458_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22060_dupName_458_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22060_dupName_458_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22055_dupName_458_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22060_dupName_458_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22058_dupName_458_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22060_dupName_458_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3231_vt_select_21(BITSELECT,11744)@241
    assign i_unnamed_c_compstr3231_vt_select_21_b = rightShiftStage1_uid22060_dupName_458_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3231_vt_join(BITJOIN,11743)@241
    assign i_unnamed_c_compstr3231_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3231_vt_select_21_b};

    // i_unnamed_c_compstr3232_sel_x(BITSELECT,6211)@241
    assign i_unnamed_c_compstr3232_sel_x_b = i_unnamed_c_compstr3231_vt_join_q[15:0];

    // i_unnamed_c_compstr3233_BitSelect_for_a(BITSELECT,27811)@241
    assign i_unnamed_c_compstr3233_BitSelect_for_a_b = i_unnamed_c_compstr3232_sel_x_b[0:0];

    // i_unnamed_c_compstr3233_join(BITJOIN,27812)@241
    assign i_unnamed_c_compstr3233_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3233_BitSelect_for_a_b};

    // i_unnamed_c_compstr3233_vt_select_0(BITSELECT,11749)@241
    assign i_unnamed_c_compstr3233_vt_select_0_b = i_unnamed_c_compstr3233_join_q[0:0];

    // redist80_i_unnamed_c_compstr3233_vt_select_0_b_1(DELAY,28308)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist80_i_unnamed_c_compstr3233_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3233_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3233_vt_join(BITJOIN,11748)@242
    assign i_unnamed_c_compstr3233_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist80_i_unnamed_c_compstr3233_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_114_c_compstr3234(ADD,6995)@242
    assign i_add_i_i_i_i_i_i_114_c_compstr3234_a = {1'b0, i_unnamed_c_compstr3233_vt_join_q};
    assign i_add_i_i_i_i_i_i_114_c_compstr3234_b = {1'b0, redist1137_i_conv_i_i_i_i_i_114_c_compstr3230_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_114_c_compstr3234_o = $unsigned(i_add_i_i_i_i_i_i_114_c_compstr3234_a) + $unsigned(i_add_i_i_i_i_i_i_114_c_compstr3234_b);
    assign i_add_i_i_i_i_i_i_114_c_compstr3234_q = i_add_i_i_i_i_i_i_114_c_compstr3234_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_114_c_compstr3234_sel_x(BITSELECT,2189)@242
    assign bgTrunc_i_add_i_i_i_i_i_i_114_c_compstr3234_sel_x_b = i_add_i_i_i_i_i_i_114_c_compstr3234_q[15:0];

    // i_conv_i_i_i_i_i_i279_115_c_compstr3254_sel_x(BITSELECT,3857)@242
    assign i_conv_i_i_i_i_i_i279_115_c_compstr3254_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_114_c_compstr3234_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_115_c_compstr3254_vt_select_15(BITSELECT,7945)@242
    assign i_conv_i_i_i_i_i_i279_115_c_compstr3254_vt_select_15_b = i_conv_i_i_i_i_i_i279_115_c_compstr3254_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_115_c_compstr3254_vt_join(BITJOIN,7944)@242
    assign i_conv_i_i_i_i_i_i279_115_c_compstr3254_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_115_c_compstr3254_vt_select_15_b};

    // leftShiftStage0_uid25448_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x(MUX,25447)@242
    assign leftShiftStage0_uid25448_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25448_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_115_c_compstr3254_vt_join_q or leftShiftStage0Idx1_uid25446_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25448_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25448_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_115_c_compstr3254_vt_join_q;
            1'b1 : leftShiftStage0_uid25448_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25446_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25448_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25453_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x(MUX,25452)@242
    assign leftShiftStage1_uid25453_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25453_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_s or leftShiftStage0_uid25448_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25451_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25453_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25453_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q = leftShiftStage0_uid25448_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25453_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25451_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25453_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25458_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x(MUX,25457)@242
    assign leftShiftStage2_uid25458_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25458_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_s or leftShiftStage1_uid25453_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25456_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25458_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25458_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q = leftShiftStage1_uid25453_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25458_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25456_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25458_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_115_c_compstr3255_vt_select_28(BITSELECT,9472)@242
    assign i_shl_i_i_i_i_i_i_115_c_compstr3255_vt_select_28_b = leftShiftStage2_uid25458_i_shl_i_i_i_i_i_i_115_c_compstr0_shift_x_q[28:13];

    // redist366_i_shl_i_i_i_i_i_i_115_c_compstr3255_vt_select_28_b_1(DELAY,28594)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist366_i_shl_i_i_i_i_i_i_115_c_compstr3255_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_115_c_compstr3255_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_115_c_compstr3255_vt_join(BITJOIN,9471)@243
    assign i_shl_i_i_i_i_i_i_115_c_compstr3255_vt_join_q = {redist366_i_shl_i_i_i_i_i_i_115_c_compstr3255_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_offset(CONSTANT,30918)
    assign redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_offset_q = $unsigned(8'b00100000);

    // redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_rdcnt(ADD,32367)
    assign redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_a = {1'b0, redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_wraddr_q};
    assign redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_b = {1'b0, redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_o <= $unsigned(redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_a) + $unsigned(redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_b);
        end
    end
    assign redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_q = redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_o[8:0];

    // redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_inputreg0(DELAY,32362)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl);
        end
    end

    // redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_wraddr(COUNTER,32365)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_wraddr_i <= $unsigned(redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_wraddr_q = redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_wraddr_i[7:0];

    // redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem(DUALMEM,32364)
    assign redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_ia = $unsigned(redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_inputreg0_q);
    assign redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_aa = redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_wraddr_q;
    assign redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_ab = redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_aa),
        .data_a(redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_ab),
        .q_b(redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_q = redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_iq[15:0];

    // redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_outputreg0(DELAY,32363)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_outputreg0_q <= $unsigned(redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_mem_q);
        end
    end

    // redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_rdcnt(ADD,30919)
    assign redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_a = {1'b0, redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_wraddr_q};
    assign redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_b = {1'b0, redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_o <= $unsigned(redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_a) + $unsigned(redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_b);
        end
    end
    assign redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_q = redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_o[8:0];

    // redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_inputreg0(DELAY,30914)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl);
        end
    end

    // redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_wraddr(COUNTER,30917)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_wraddr_i <= $unsigned(redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_wraddr_q = redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_wraddr_i[7:0];

    // redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem(DUALMEM,30916)
    assign redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_ia = $unsigned(redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_inputreg0_q);
    assign redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_aa = redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_wraddr_q;
    assign redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_ab = redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_aa),
        .data_a(redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_ab),
        .q_b(redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_q = redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_iq[15:0];

    // redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_outputreg0(DELAY,30915)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_outputreg0_q <= $unsigned(redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_mem_q);
        end
    end

    // redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_rdcnt(ADD,30925)
    assign redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_a = {1'b0, redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_wraddr_q};
    assign redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_b = {1'b0, redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_o <= $unsigned(redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_a) + $unsigned(redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_b);
        end
    end
    assign redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_q = redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_o[8:0];

    // redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_inputreg0(DELAY,30920)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl);
        end
    end

    // redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_wraddr(COUNTER,30923)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_wraddr_i <= $unsigned(redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_wraddr_q = redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_wraddr_i[7:0];

    // redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem(DUALMEM,30922)
    assign redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_ia = $unsigned(redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_inputreg0_q);
    assign redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_aa = redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_wraddr_q;
    assign redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_ab = redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_aa),
        .data_a(redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_ab),
        .q_b(redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_q = redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_iq[15:0];

    // redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_outputreg0(DELAY,30921)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_outputreg0_q <= $unsigned(redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_mem_q);
        end
    end

    // redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_rdcnt(ADD,32361)
    assign redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_a = {1'b0, redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_wraddr_q};
    assign redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_b = {1'b0, redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_o <= $unsigned(redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_a) + $unsigned(redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_b);
        end
    end
    assign redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_q = redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_o[8:0];

    // redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_inputreg0(DELAY,32356)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl);
        end
    end

    // redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_wraddr(COUNTER,32359)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_wraddr_i <= $unsigned(redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_wraddr_q = redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_wraddr_i[7:0];

    // redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem(DUALMEM,32358)
    assign redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_ia = $unsigned(redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_inputreg0_q);
    assign redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_aa = redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_wraddr_q;
    assign redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_ab = redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_aa),
        .data_a(redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_ab),
        .q_b(redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_q = redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_iq[15:0];

    // redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_outputreg0(DELAY,32357)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_outputreg0_q <= $unsigned(redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28077)@237 + 5
    // out q@243
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256(ADD,8538)@243
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod616_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_b = $unsigned({{5{i_shl_i_i_i_i_i_i_115_c_compstr3255_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_115_c_compstr3255_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_o[33:0];

    // rightShiftStage0_uid22099_dupName_461_i_unnamed_c_compstr0_shift_x(MUX,22098)@243
    assign rightShiftStage0_uid22099_dupName_461_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22099_dupName_461_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_q or rightShiftStage0Idx1_uid22097_dupName_461_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22099_dupName_461_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22099_dupName_461_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_q;
            1'b1 : rightShiftStage0_uid22099_dupName_461_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22097_dupName_461_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22099_dupName_461_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22104_dupName_461_i_unnamed_c_compstr0_shift_x(MUX,22103)@243
    assign rightShiftStage1_uid22104_dupName_461_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22104_dupName_461_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22099_dupName_461_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22102_dupName_461_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22104_dupName_461_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22104_dupName_461_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22099_dupName_461_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22104_dupName_461_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22102_dupName_461_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22104_dupName_461_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22109_dupName_461_i_unnamed_c_compstr0_shift_x(MUX,22108)@243
    assign rightShiftStage2_uid22109_dupName_461_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22109_dupName_461_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22104_dupName_461_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22107_dupName_461_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22109_dupName_461_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22109_dupName_461_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22104_dupName_461_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22109_dupName_461_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22107_dupName_461_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22109_dupName_461_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3257_vt_select_20(BITSELECT,11763)@243
    assign i_unnamed_c_compstr3257_vt_select_20_b = rightShiftStage2_uid22109_dupName_461_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3257_vt_join(BITJOIN,11762)@243
    assign i_unnamed_c_compstr3257_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3257_vt_select_20_b};

    // i_conv_i_i_i_i_i_115_c_compstr3258_sel_x(BITSELECT,3729)@243
    assign i_conv_i_i_i_i_i_115_c_compstr3258_sel_x_b = i_unnamed_c_compstr3257_vt_join_q[15:0];

    // redist1136_i_conv_i_i_i_i_i_115_c_compstr3258_sel_x_b_1(DELAY,29364)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1136_i_conv_i_i_i_i_i_115_c_compstr3258_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_115_c_compstr3258_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22118_dupName_462_i_unnamed_c_compstr0_shift_x(BITSELECT,22117)@243
    assign rightShiftStage1Idx1Rng8_uid22118_dupName_462_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22117_dupName_462_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22120_dupName_462_i_unnamed_c_compstr0_shift_x(BITJOIN,22119)@243
    assign rightShiftStage1Idx1_uid22120_dupName_462_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22118_dupName_462_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22113_dupName_462_i_unnamed_c_compstr0_shift_x(BITSELECT,22112)@243
    assign rightShiftStage0Idx1Rng4_uid22113_dupName_462_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_q[33:4];

    // rightShiftStage0Idx1_uid22115_dupName_462_i_unnamed_c_compstr0_shift_x(BITJOIN,22114)@243
    assign rightShiftStage0Idx1_uid22115_dupName_462_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22113_dupName_462_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22117_dupName_462_i_unnamed_c_compstr0_shift_x(MUX,22116)@243
    assign rightShiftStage0_uid22117_dupName_462_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22117_dupName_462_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_q or rightShiftStage0Idx1_uid22115_dupName_462_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22117_dupName_462_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22117_dupName_462_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compstr3256_q;
            1'b1 : rightShiftStage0_uid22117_dupName_462_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22115_dupName_462_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22117_dupName_462_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22122_dupName_462_i_unnamed_c_compstr0_shift_x(MUX,22121)@243
    assign rightShiftStage1_uid22122_dupName_462_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22122_dupName_462_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22117_dupName_462_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22120_dupName_462_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22122_dupName_462_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22122_dupName_462_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22117_dupName_462_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22122_dupName_462_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22120_dupName_462_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22122_dupName_462_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3259_vt_select_21(BITSELECT,11766)@243
    assign i_unnamed_c_compstr3259_vt_select_21_b = rightShiftStage1_uid22122_dupName_462_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3259_vt_join(BITJOIN,11765)@243
    assign i_unnamed_c_compstr3259_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3259_vt_select_21_b};

    // i_unnamed_c_compstr3260_sel_x(BITSELECT,6213)@243
    assign i_unnamed_c_compstr3260_sel_x_b = i_unnamed_c_compstr3259_vt_join_q[15:0];

    // i_unnamed_c_compstr3261_BitSelect_for_a(BITSELECT,27815)@243
    assign i_unnamed_c_compstr3261_BitSelect_for_a_b = i_unnamed_c_compstr3260_sel_x_b[0:0];

    // i_unnamed_c_compstr3261_join(BITJOIN,27816)@243
    assign i_unnamed_c_compstr3261_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3261_BitSelect_for_a_b};

    // i_unnamed_c_compstr3261_vt_select_0(BITSELECT,11771)@243
    assign i_unnamed_c_compstr3261_vt_select_0_b = i_unnamed_c_compstr3261_join_q[0:0];

    // redist78_i_unnamed_c_compstr3261_vt_select_0_b_1(DELAY,28306)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist78_i_unnamed_c_compstr3261_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3261_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3261_vt_join(BITJOIN,11770)@244
    assign i_unnamed_c_compstr3261_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist78_i_unnamed_c_compstr3261_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_115_c_compstr3262(ADD,6996)@244
    assign i_add_i_i_i_i_i_i_115_c_compstr3262_a = {1'b0, i_unnamed_c_compstr3261_vt_join_q};
    assign i_add_i_i_i_i_i_i_115_c_compstr3262_b = {1'b0, redist1136_i_conv_i_i_i_i_i_115_c_compstr3258_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_115_c_compstr3262_o = $unsigned(i_add_i_i_i_i_i_i_115_c_compstr3262_a) + $unsigned(i_add_i_i_i_i_i_i_115_c_compstr3262_b);
    assign i_add_i_i_i_i_i_i_115_c_compstr3262_q = i_add_i_i_i_i_i_i_115_c_compstr3262_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_115_c_compstr3262_sel_x(BITSELECT,2190)@244
    assign bgTrunc_i_add_i_i_i_i_i_i_115_c_compstr3262_sel_x_b = i_add_i_i_i_i_i_i_115_c_compstr3262_q[15:0];

    // i_conv_i_i_i_i_i_i279_116_c_compstr3282_sel_x(BITSELECT,3858)@244
    assign i_conv_i_i_i_i_i_i279_116_c_compstr3282_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_115_c_compstr3262_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_116_c_compstr3282_vt_select_15(BITSELECT,7949)@244
    assign i_conv_i_i_i_i_i_i279_116_c_compstr3282_vt_select_15_b = i_conv_i_i_i_i_i_i279_116_c_compstr3282_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_116_c_compstr3282_vt_join(BITJOIN,7948)@244
    assign i_conv_i_i_i_i_i_i279_116_c_compstr3282_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_116_c_compstr3282_vt_select_15_b};

    // leftShiftStage0_uid25466_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x(MUX,25465)@244
    assign leftShiftStage0_uid25466_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25466_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_116_c_compstr3282_vt_join_q or leftShiftStage0Idx1_uid25464_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25466_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25466_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_116_c_compstr3282_vt_join_q;
            1'b1 : leftShiftStage0_uid25466_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25464_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25466_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25471_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x(MUX,25470)@244
    assign leftShiftStage1_uid25471_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25471_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_s or leftShiftStage0_uid25466_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25469_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25471_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25471_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q = leftShiftStage0_uid25466_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25471_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25469_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25471_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25476_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x(MUX,25475)@244
    assign leftShiftStage2_uid25476_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25476_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_s or leftShiftStage1_uid25471_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25474_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25476_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25476_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q = leftShiftStage1_uid25471_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25476_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25474_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25476_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_116_c_compstr3283_vt_select_28(BITSELECT,9475)@244
    assign i_shl_i_i_i_i_i_i_116_c_compstr3283_vt_select_28_b = leftShiftStage2_uid25476_i_shl_i_i_i_i_i_i_116_c_compstr0_shift_x_q[28:13];

    // redist365_i_shl_i_i_i_i_i_i_116_c_compstr3283_vt_select_28_b_1(DELAY,28593)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist365_i_shl_i_i_i_i_i_i_116_c_compstr3283_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_116_c_compstr3283_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_116_c_compstr3283_vt_join(BITJOIN,9474)@245
    assign i_shl_i_i_i_i_i_i_116_c_compstr3283_vt_join_q = {redist365_i_shl_i_i_i_i_i_i_116_c_compstr3283_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_offset(CONSTANT,30930)
    assign redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_offset_q = $unsigned(8'b00011110);

    // redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_rdcnt(ADD,32379)
    assign redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_a = {1'b0, redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_wraddr_q};
    assign redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_b = {1'b0, redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_o <= $unsigned(redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_a) + $unsigned(redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_b);
        end
    end
    assign redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_q = redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_o[8:0];

    // redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_inputreg0(DELAY,32374)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl);
        end
    end

    // redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_wraddr(COUNTER,32377)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_wraddr_i <= $unsigned(redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_wraddr_q = redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_wraddr_i[7:0];

    // redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem(DUALMEM,32376)
    assign redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_ia = $unsigned(redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_inputreg0_q);
    assign redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_aa = redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_wraddr_q;
    assign redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_ab = redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_aa),
        .data_a(redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_ab),
        .q_b(redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_q = redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_iq[15:0];

    // redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_outputreg0(DELAY,32375)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_outputreg0_q <= $unsigned(redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_mem_q);
        end
    end

    // redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_rdcnt(ADD,30931)
    assign redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_a = {1'b0, redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_wraddr_q};
    assign redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_b = {1'b0, redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_o <= $unsigned(redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_a) + $unsigned(redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_b);
        end
    end
    assign redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_q = redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_o[8:0];

    // redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_inputreg0(DELAY,30926)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl);
        end
    end

    // redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_wraddr(COUNTER,30929)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_wraddr_i <= $unsigned(redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_wraddr_q = redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_wraddr_i[7:0];

    // redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem(DUALMEM,30928)
    assign redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_ia = $unsigned(redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_inputreg0_q);
    assign redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_aa = redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_wraddr_q;
    assign redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_ab = redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_aa),
        .data_a(redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_ab),
        .q_b(redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_q = redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_iq[15:0];

    // redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_outputreg0(DELAY,30927)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_outputreg0_q <= $unsigned(redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_mem_q);
        end
    end

    // redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_rdcnt(ADD,30937)
    assign redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_a = {1'b0, redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_wraddr_q};
    assign redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_b = {1'b0, redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_o <= $unsigned(redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_a) + $unsigned(redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_b);
        end
    end
    assign redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_q = redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_o[8:0];

    // redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_inputreg0(DELAY,30932)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl);
        end
    end

    // redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_wraddr(COUNTER,30935)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_wraddr_i <= $unsigned(redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_wraddr_q = redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_wraddr_i[7:0];

    // redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem(DUALMEM,30934)
    assign redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_ia = $unsigned(redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_inputreg0_q);
    assign redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_aa = redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_wraddr_q;
    assign redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_ab = redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_aa),
        .data_a(redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_ab),
        .q_b(redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_q = redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_iq[15:0];

    // redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_outputreg0(DELAY,30933)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_outputreg0_q <= $unsigned(redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_mem_q);
        end
    end

    // redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_rdcnt(ADD,32373)
    assign redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_a = {1'b0, redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_wraddr_q};
    assign redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_b = {1'b0, redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_o <= $unsigned(redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_a) + $unsigned(redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_b);
        end
    end
    assign redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_q = redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_o[8:0];

    // redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_inputreg0(DELAY,32368)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl);
        end
    end

    // redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_wraddr(COUNTER,32371)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_wraddr_i <= $unsigned(redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_wraddr_q = redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_wraddr_i[7:0];

    // redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem(DUALMEM,32370)
    assign redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_ia = $unsigned(redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_inputreg0_q);
    assign redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_aa = redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_wraddr_q;
    assign redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_ab = redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_aa),
        .data_a(redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_ab),
        .q_b(redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_q = redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_iq[15:0];

    // redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_outputreg0(DELAY,32369)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_outputreg0_q <= $unsigned(redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28079)@239 + 5
    // out q@245
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284(ADD,8539)@245
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod621_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_b = $unsigned({{5{i_shl_i_i_i_i_i_i_116_c_compstr3283_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_116_c_compstr3283_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_o[33:0];

    // rightShiftStage0_uid22161_dupName_465_i_unnamed_c_compstr0_shift_x(MUX,22160)@245
    assign rightShiftStage0_uid22161_dupName_465_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22161_dupName_465_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_q or rightShiftStage0Idx1_uid22159_dupName_465_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22161_dupName_465_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22161_dupName_465_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_q;
            1'b1 : rightShiftStage0_uid22161_dupName_465_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22159_dupName_465_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22161_dupName_465_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22166_dupName_465_i_unnamed_c_compstr0_shift_x(MUX,22165)@245
    assign rightShiftStage1_uid22166_dupName_465_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22166_dupName_465_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22161_dupName_465_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22164_dupName_465_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22166_dupName_465_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22166_dupName_465_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22161_dupName_465_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22166_dupName_465_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22164_dupName_465_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22166_dupName_465_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22171_dupName_465_i_unnamed_c_compstr0_shift_x(MUX,22170)@245
    assign rightShiftStage2_uid22171_dupName_465_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22171_dupName_465_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22166_dupName_465_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22169_dupName_465_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22171_dupName_465_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22171_dupName_465_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22166_dupName_465_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22171_dupName_465_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22169_dupName_465_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22171_dupName_465_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3285_vt_select_20(BITSELECT,11785)@245
    assign i_unnamed_c_compstr3285_vt_select_20_b = rightShiftStage2_uid22171_dupName_465_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3285_vt_join(BITJOIN,11784)@245
    assign i_unnamed_c_compstr3285_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3285_vt_select_20_b};

    // i_conv_i_i_i_i_i_116_c_compstr3286_sel_x(BITSELECT,3730)@245
    assign i_conv_i_i_i_i_i_116_c_compstr3286_sel_x_b = i_unnamed_c_compstr3285_vt_join_q[15:0];

    // redist1135_i_conv_i_i_i_i_i_116_c_compstr3286_sel_x_b_1(DELAY,29363)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1135_i_conv_i_i_i_i_i_116_c_compstr3286_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_116_c_compstr3286_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22180_dupName_466_i_unnamed_c_compstr0_shift_x(BITSELECT,22179)@245
    assign rightShiftStage1Idx1Rng8_uid22180_dupName_466_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22179_dupName_466_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22182_dupName_466_i_unnamed_c_compstr0_shift_x(BITJOIN,22181)@245
    assign rightShiftStage1Idx1_uid22182_dupName_466_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22180_dupName_466_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22175_dupName_466_i_unnamed_c_compstr0_shift_x(BITSELECT,22174)@245
    assign rightShiftStage0Idx1Rng4_uid22175_dupName_466_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_q[33:4];

    // rightShiftStage0Idx1_uid22177_dupName_466_i_unnamed_c_compstr0_shift_x(BITJOIN,22176)@245
    assign rightShiftStage0Idx1_uid22177_dupName_466_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22175_dupName_466_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22179_dupName_466_i_unnamed_c_compstr0_shift_x(MUX,22178)@245
    assign rightShiftStage0_uid22179_dupName_466_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22179_dupName_466_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_q or rightShiftStage0Idx1_uid22177_dupName_466_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22179_dupName_466_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22179_dupName_466_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compstr3284_q;
            1'b1 : rightShiftStage0_uid22179_dupName_466_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22177_dupName_466_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22179_dupName_466_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22184_dupName_466_i_unnamed_c_compstr0_shift_x(MUX,22183)@245
    assign rightShiftStage1_uid22184_dupName_466_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22184_dupName_466_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22179_dupName_466_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22182_dupName_466_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22184_dupName_466_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22184_dupName_466_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22179_dupName_466_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22184_dupName_466_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22182_dupName_466_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22184_dupName_466_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3287_vt_select_21(BITSELECT,11788)@245
    assign i_unnamed_c_compstr3287_vt_select_21_b = rightShiftStage1_uid22184_dupName_466_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3287_vt_join(BITJOIN,11787)@245
    assign i_unnamed_c_compstr3287_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3287_vt_select_21_b};

    // i_unnamed_c_compstr3288_sel_x(BITSELECT,6215)@245
    assign i_unnamed_c_compstr3288_sel_x_b = i_unnamed_c_compstr3287_vt_join_q[15:0];

    // i_unnamed_c_compstr3289_BitSelect_for_a(BITSELECT,27819)@245
    assign i_unnamed_c_compstr3289_BitSelect_for_a_b = i_unnamed_c_compstr3288_sel_x_b[0:0];

    // i_unnamed_c_compstr3289_join(BITJOIN,27820)@245
    assign i_unnamed_c_compstr3289_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3289_BitSelect_for_a_b};

    // i_unnamed_c_compstr3289_vt_select_0(BITSELECT,11793)@245
    assign i_unnamed_c_compstr3289_vt_select_0_b = i_unnamed_c_compstr3289_join_q[0:0];

    // redist76_i_unnamed_c_compstr3289_vt_select_0_b_1(DELAY,28304)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist76_i_unnamed_c_compstr3289_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3289_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3289_vt_join(BITJOIN,11792)@246
    assign i_unnamed_c_compstr3289_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist76_i_unnamed_c_compstr3289_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_116_c_compstr3290(ADD,6997)@246
    assign i_add_i_i_i_i_i_i_116_c_compstr3290_a = {1'b0, i_unnamed_c_compstr3289_vt_join_q};
    assign i_add_i_i_i_i_i_i_116_c_compstr3290_b = {1'b0, redist1135_i_conv_i_i_i_i_i_116_c_compstr3286_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_116_c_compstr3290_o = $unsigned(i_add_i_i_i_i_i_i_116_c_compstr3290_a) + $unsigned(i_add_i_i_i_i_i_i_116_c_compstr3290_b);
    assign i_add_i_i_i_i_i_i_116_c_compstr3290_q = i_add_i_i_i_i_i_i_116_c_compstr3290_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_116_c_compstr3290_sel_x(BITSELECT,2191)@246
    assign bgTrunc_i_add_i_i_i_i_i_i_116_c_compstr3290_sel_x_b = i_add_i_i_i_i_i_i_116_c_compstr3290_q[15:0];

    // i_conv_i_i_i_i_i_i279_117_c_compstr3310_sel_x(BITSELECT,3859)@246
    assign i_conv_i_i_i_i_i_i279_117_c_compstr3310_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_116_c_compstr3290_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_117_c_compstr3310_vt_select_15(BITSELECT,7953)@246
    assign i_conv_i_i_i_i_i_i279_117_c_compstr3310_vt_select_15_b = i_conv_i_i_i_i_i_i279_117_c_compstr3310_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_117_c_compstr3310_vt_join(BITJOIN,7952)@246
    assign i_conv_i_i_i_i_i_i279_117_c_compstr3310_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_117_c_compstr3310_vt_select_15_b};

    // leftShiftStage0_uid25484_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x(MUX,25483)@246
    assign leftShiftStage0_uid25484_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25484_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_117_c_compstr3310_vt_join_q or leftShiftStage0Idx1_uid25482_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25484_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25484_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_117_c_compstr3310_vt_join_q;
            1'b1 : leftShiftStage0_uid25484_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25482_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25484_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25489_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x(MUX,25488)@246
    assign leftShiftStage1_uid25489_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25489_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_s or leftShiftStage0_uid25484_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25487_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25489_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25489_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q = leftShiftStage0_uid25484_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25489_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25487_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25489_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25494_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x(MUX,25493)@246
    assign leftShiftStage2_uid25494_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25494_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_s or leftShiftStage1_uid25489_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25492_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25494_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25494_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q = leftShiftStage1_uid25489_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25494_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25492_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25494_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_117_c_compstr3311_vt_select_28(BITSELECT,9478)@246
    assign i_shl_i_i_i_i_i_i_117_c_compstr3311_vt_select_28_b = leftShiftStage2_uid25494_i_shl_i_i_i_i_i_i_117_c_compstr0_shift_x_q[28:13];

    // redist364_i_shl_i_i_i_i_i_i_117_c_compstr3311_vt_select_28_b_1(DELAY,28592)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist364_i_shl_i_i_i_i_i_i_117_c_compstr3311_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_117_c_compstr3311_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_117_c_compstr3311_vt_join(BITJOIN,9477)@247
    assign i_shl_i_i_i_i_i_i_117_c_compstr3311_vt_join_q = {redist364_i_shl_i_i_i_i_i_i_117_c_compstr3311_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_offset(CONSTANT,30942)
    assign redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_offset_q = $unsigned(8'b00011100);

    // redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_rdcnt(ADD,32391)
    assign redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_a = {1'b0, redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_wraddr_q};
    assign redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_b = {1'b0, redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_o <= $unsigned(redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_a) + $unsigned(redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_b);
        end
    end
    assign redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_q = redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_o[8:0];

    // redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_inputreg0(DELAY,32386)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl);
        end
    end

    // redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_wraddr(COUNTER,32389)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_wraddr_i <= $unsigned(redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_wraddr_q = redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_wraddr_i[7:0];

    // redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem(DUALMEM,32388)
    assign redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_ia = $unsigned(redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_inputreg0_q);
    assign redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_aa = redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_wraddr_q;
    assign redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_ab = redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_aa),
        .data_a(redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_ab),
        .q_b(redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_q = redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_iq[15:0];

    // redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_outputreg0(DELAY,32387)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_outputreg0_q <= $unsigned(redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_mem_q);
        end
    end

    // redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_rdcnt(ADD,30943)
    assign redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_a = {1'b0, redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_wraddr_q};
    assign redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_b = {1'b0, redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_o <= $unsigned(redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_a) + $unsigned(redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_b);
        end
    end
    assign redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_q = redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_o[8:0];

    // redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_inputreg0(DELAY,30938)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl);
        end
    end

    // redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_wraddr(COUNTER,30941)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_wraddr_i <= $unsigned(redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_wraddr_q = redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_wraddr_i[7:0];

    // redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem(DUALMEM,30940)
    assign redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_ia = $unsigned(redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_inputreg0_q);
    assign redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_aa = redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_wraddr_q;
    assign redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_ab = redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_aa),
        .data_a(redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_ab),
        .q_b(redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_q = redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_iq[15:0];

    // redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_outputreg0(DELAY,30939)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_outputreg0_q <= $unsigned(redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_mem_q);
        end
    end

    // redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_rdcnt(ADD,30949)
    assign redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_a = {1'b0, redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_wraddr_q};
    assign redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_b = {1'b0, redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_o <= $unsigned(redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_a) + $unsigned(redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_b);
        end
    end
    assign redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_q = redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_o[8:0];

    // redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_inputreg0(DELAY,30944)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl);
        end
    end

    // redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_wraddr(COUNTER,30947)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_wraddr_i <= $unsigned(redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_wraddr_q = redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_wraddr_i[7:0];

    // redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem(DUALMEM,30946)
    assign redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_ia = $unsigned(redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_inputreg0_q);
    assign redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_aa = redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_wraddr_q;
    assign redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_ab = redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_aa),
        .data_a(redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_ab),
        .q_b(redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_q = redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_iq[15:0];

    // redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_outputreg0(DELAY,30945)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_outputreg0_q <= $unsigned(redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_mem_q);
        end
    end

    // redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_rdcnt(ADD,32385)
    assign redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_a = {1'b0, redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_wraddr_q};
    assign redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_b = {1'b0, redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_o <= $unsigned(redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_a) + $unsigned(redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_b);
        end
    end
    assign redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_q = redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_o[8:0];

    // redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_inputreg0(DELAY,32380)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl);
        end
    end

    // redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_wraddr(COUNTER,32383)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_wraddr_i <= $unsigned(redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_wraddr_q = redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_wraddr_i[7:0];

    // redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem(DUALMEM,32382)
    assign redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_ia = $unsigned(redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_inputreg0_q);
    assign redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_aa = redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_wraddr_q;
    assign redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_ab = redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_aa),
        .data_a(redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_ab),
        .q_b(redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_q = redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_iq[15:0];

    // redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_outputreg0(DELAY,32381)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_outputreg0_q <= $unsigned(redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28080)@241 + 5
    // out q@247
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312(ADD,8540)@247
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod626_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_b = $unsigned({{5{i_shl_i_i_i_i_i_i_117_c_compstr3311_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_117_c_compstr3311_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_o[33:0];

    // rightShiftStage0_uid22223_dupName_469_i_unnamed_c_compstr0_shift_x(MUX,22222)@247
    assign rightShiftStage0_uid22223_dupName_469_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22223_dupName_469_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_q or rightShiftStage0Idx1_uid22221_dupName_469_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22223_dupName_469_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22223_dupName_469_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_q;
            1'b1 : rightShiftStage0_uid22223_dupName_469_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22221_dupName_469_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22223_dupName_469_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22228_dupName_469_i_unnamed_c_compstr0_shift_x(MUX,22227)@247
    assign rightShiftStage1_uid22228_dupName_469_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22228_dupName_469_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22223_dupName_469_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22226_dupName_469_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22228_dupName_469_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22228_dupName_469_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22223_dupName_469_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22228_dupName_469_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22226_dupName_469_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22228_dupName_469_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22233_dupName_469_i_unnamed_c_compstr0_shift_x(MUX,22232)@247
    assign rightShiftStage2_uid22233_dupName_469_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22233_dupName_469_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22228_dupName_469_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22231_dupName_469_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22233_dupName_469_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22233_dupName_469_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22228_dupName_469_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22233_dupName_469_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22231_dupName_469_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22233_dupName_469_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3313_vt_select_20(BITSELECT,11810)@247
    assign i_unnamed_c_compstr3313_vt_select_20_b = rightShiftStage2_uid22233_dupName_469_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3313_vt_join(BITJOIN,11809)@247
    assign i_unnamed_c_compstr3313_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3313_vt_select_20_b};

    // i_conv_i_i_i_i_i_117_c_compstr3314_sel_x(BITSELECT,3731)@247
    assign i_conv_i_i_i_i_i_117_c_compstr3314_sel_x_b = i_unnamed_c_compstr3313_vt_join_q[15:0];

    // redist1134_i_conv_i_i_i_i_i_117_c_compstr3314_sel_x_b_1(DELAY,29362)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1134_i_conv_i_i_i_i_i_117_c_compstr3314_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_117_c_compstr3314_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22242_dupName_470_i_unnamed_c_compstr0_shift_x(BITSELECT,22241)@247
    assign rightShiftStage1Idx1Rng8_uid22242_dupName_470_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22241_dupName_470_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22244_dupName_470_i_unnamed_c_compstr0_shift_x(BITJOIN,22243)@247
    assign rightShiftStage1Idx1_uid22244_dupName_470_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22242_dupName_470_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22237_dupName_470_i_unnamed_c_compstr0_shift_x(BITSELECT,22236)@247
    assign rightShiftStage0Idx1Rng4_uid22237_dupName_470_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_q[33:4];

    // rightShiftStage0Idx1_uid22239_dupName_470_i_unnamed_c_compstr0_shift_x(BITJOIN,22238)@247
    assign rightShiftStage0Idx1_uid22239_dupName_470_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22237_dupName_470_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22241_dupName_470_i_unnamed_c_compstr0_shift_x(MUX,22240)@247
    assign rightShiftStage0_uid22241_dupName_470_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22241_dupName_470_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_q or rightShiftStage0Idx1_uid22239_dupName_470_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22241_dupName_470_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22241_dupName_470_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compstr3312_q;
            1'b1 : rightShiftStage0_uid22241_dupName_470_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22239_dupName_470_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22241_dupName_470_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22246_dupName_470_i_unnamed_c_compstr0_shift_x(MUX,22245)@247
    assign rightShiftStage1_uid22246_dupName_470_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22246_dupName_470_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22241_dupName_470_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22244_dupName_470_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22246_dupName_470_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22246_dupName_470_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22241_dupName_470_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22246_dupName_470_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22244_dupName_470_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22246_dupName_470_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3315_vt_select_21(BITSELECT,11813)@247
    assign i_unnamed_c_compstr3315_vt_select_21_b = rightShiftStage1_uid22246_dupName_470_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3315_vt_join(BITJOIN,11812)@247
    assign i_unnamed_c_compstr3315_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3315_vt_select_21_b};

    // i_unnamed_c_compstr3316_sel_x(BITSELECT,6217)@247
    assign i_unnamed_c_compstr3316_sel_x_b = i_unnamed_c_compstr3315_vt_join_q[15:0];

    // i_unnamed_c_compstr3317_BitSelect_for_a(BITSELECT,27823)@247
    assign i_unnamed_c_compstr3317_BitSelect_for_a_b = i_unnamed_c_compstr3316_sel_x_b[0:0];

    // i_unnamed_c_compstr3317_join(BITJOIN,27824)@247
    assign i_unnamed_c_compstr3317_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3317_BitSelect_for_a_b};

    // i_unnamed_c_compstr3317_vt_select_0(BITSELECT,11818)@247
    assign i_unnamed_c_compstr3317_vt_select_0_b = i_unnamed_c_compstr3317_join_q[0:0];

    // redist74_i_unnamed_c_compstr3317_vt_select_0_b_1(DELAY,28302)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist74_i_unnamed_c_compstr3317_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3317_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3317_vt_join(BITJOIN,11817)@248
    assign i_unnamed_c_compstr3317_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist74_i_unnamed_c_compstr3317_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_117_c_compstr3318(ADD,6998)@248
    assign i_add_i_i_i_i_i_i_117_c_compstr3318_a = {1'b0, i_unnamed_c_compstr3317_vt_join_q};
    assign i_add_i_i_i_i_i_i_117_c_compstr3318_b = {1'b0, redist1134_i_conv_i_i_i_i_i_117_c_compstr3314_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_117_c_compstr3318_o = $unsigned(i_add_i_i_i_i_i_i_117_c_compstr3318_a) + $unsigned(i_add_i_i_i_i_i_i_117_c_compstr3318_b);
    assign i_add_i_i_i_i_i_i_117_c_compstr3318_q = i_add_i_i_i_i_i_i_117_c_compstr3318_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_117_c_compstr3318_sel_x(BITSELECT,2192)@248
    assign bgTrunc_i_add_i_i_i_i_i_i_117_c_compstr3318_sel_x_b = i_add_i_i_i_i_i_i_117_c_compstr3318_q[15:0];

    // i_conv_i_i_i_i_i_i279_118_c_compstr3338_sel_x(BITSELECT,3860)@248
    assign i_conv_i_i_i_i_i_i279_118_c_compstr3338_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_117_c_compstr3318_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_118_c_compstr3338_vt_select_15(BITSELECT,7957)@248
    assign i_conv_i_i_i_i_i_i279_118_c_compstr3338_vt_select_15_b = i_conv_i_i_i_i_i_i279_118_c_compstr3338_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_118_c_compstr3338_vt_join(BITJOIN,7956)@248
    assign i_conv_i_i_i_i_i_i279_118_c_compstr3338_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_118_c_compstr3338_vt_select_15_b};

    // leftShiftStage0_uid25502_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x(MUX,25501)@248
    assign leftShiftStage0_uid25502_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25502_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_118_c_compstr3338_vt_join_q or leftShiftStage0Idx1_uid25500_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25502_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25502_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_118_c_compstr3338_vt_join_q;
            1'b1 : leftShiftStage0_uid25502_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25500_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25502_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25507_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x(MUX,25506)@248
    assign leftShiftStage1_uid25507_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25507_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_s or leftShiftStage0_uid25502_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25505_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25507_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25507_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q = leftShiftStage0_uid25502_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25507_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25505_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25507_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25512_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x(MUX,25511)@248
    assign leftShiftStage2_uid25512_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25512_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_s or leftShiftStage1_uid25507_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25510_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25512_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25512_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q = leftShiftStage1_uid25507_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25512_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25510_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25512_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_118_c_compstr3339_vt_select_28(BITSELECT,9481)@248
    assign i_shl_i_i_i_i_i_i_118_c_compstr3339_vt_select_28_b = leftShiftStage2_uid25512_i_shl_i_i_i_i_i_i_118_c_compstr0_shift_x_q[28:13];

    // redist363_i_shl_i_i_i_i_i_i_118_c_compstr3339_vt_select_28_b_1(DELAY,28591)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist363_i_shl_i_i_i_i_i_i_118_c_compstr3339_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_118_c_compstr3339_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_118_c_compstr3339_vt_join(BITJOIN,9480)@249
    assign i_shl_i_i_i_i_i_i_118_c_compstr3339_vt_join_q = {redist363_i_shl_i_i_i_i_i_i_118_c_compstr3339_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_offset(CONSTANT,30954)
    assign redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_offset_q = $unsigned(8'b00011010);

    // redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_rdcnt(ADD,32403)
    assign redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_a = {1'b0, redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_wraddr_q};
    assign redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_b = {1'b0, redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_o <= $unsigned(redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_a) + $unsigned(redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_b);
        end
    end
    assign redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_q = redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_o[8:0];

    // redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_inputreg0(DELAY,32398)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl);
        end
    end

    // redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_wraddr(COUNTER,32401)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_wraddr_i <= $unsigned(redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_wraddr_q = redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_wraddr_i[7:0];

    // redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem(DUALMEM,32400)
    assign redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_ia = $unsigned(redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_inputreg0_q);
    assign redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_aa = redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_wraddr_q;
    assign redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_ab = redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_aa),
        .data_a(redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_ab),
        .q_b(redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_q = redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_iq[15:0];

    // redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_outputreg0(DELAY,32399)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_outputreg0_q <= $unsigned(redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_mem_q);
        end
    end

    // redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_rdcnt(ADD,30955)
    assign redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_a = {1'b0, redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_wraddr_q};
    assign redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_b = {1'b0, redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_o <= $unsigned(redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_a) + $unsigned(redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_b);
        end
    end
    assign redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_q = redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_o[8:0];

    // redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_inputreg0(DELAY,30950)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl);
        end
    end

    // redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_wraddr(COUNTER,30953)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_wraddr_i <= $unsigned(redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_wraddr_q = redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_wraddr_i[7:0];

    // redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem(DUALMEM,30952)
    assign redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_ia = $unsigned(redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_inputreg0_q);
    assign redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_aa = redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_wraddr_q;
    assign redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_ab = redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_aa),
        .data_a(redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_ab),
        .q_b(redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_q = redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_iq[15:0];

    // redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_outputreg0(DELAY,30951)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_outputreg0_q <= $unsigned(redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_mem_q);
        end
    end

    // redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_rdcnt(ADD,30961)
    assign redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_a = {1'b0, redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_wraddr_q};
    assign redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_b = {1'b0, redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_o <= $unsigned(redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_a) + $unsigned(redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_b);
        end
    end
    assign redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_q = redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_o[8:0];

    // redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_inputreg0(DELAY,30956)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl);
        end
    end

    // redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_wraddr(COUNTER,30959)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_wraddr_i <= $unsigned(redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_wraddr_q = redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_wraddr_i[7:0];

    // redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem(DUALMEM,30958)
    assign redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_ia = $unsigned(redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_inputreg0_q);
    assign redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_aa = redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_wraddr_q;
    assign redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_ab = redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_aa),
        .data_a(redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_ab),
        .q_b(redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_q = redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_iq[15:0];

    // redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_outputreg0(DELAY,30957)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_outputreg0_q <= $unsigned(redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_mem_q);
        end
    end

    // redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_rdcnt(ADD,32397)
    assign redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_a = {1'b0, redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_wraddr_q};
    assign redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_b = {1'b0, redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_o <= $unsigned(redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_a) + $unsigned(redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_b);
        end
    end
    assign redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_q = redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_o[8:0];

    // redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_inputreg0(DELAY,32392)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl);
        end
    end

    // redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_wraddr(COUNTER,32395)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_wraddr_i <= $unsigned(redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_wraddr_q = redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_wraddr_i[7:0];

    // redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem(DUALMEM,32394)
    assign redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_ia = $unsigned(redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_inputreg0_q);
    assign redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_aa = redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_wraddr_q;
    assign redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_ab = redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_aa),
        .data_a(redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_ab),
        .q_b(redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_q = redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_iq[15:0];

    // redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_outputreg0(DELAY,32393)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_outputreg0_q <= $unsigned(redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28081)@243 + 5
    // out q@249
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340(ADD,8541)@249
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod631_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_b = $unsigned({{5{i_shl_i_i_i_i_i_i_118_c_compstr3339_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_118_c_compstr3339_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_o[33:0];

    // rightShiftStage0_uid22285_dupName_473_i_unnamed_c_compstr0_shift_x(MUX,22284)@249
    assign rightShiftStage0_uid22285_dupName_473_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22285_dupName_473_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_q or rightShiftStage0Idx1_uid22283_dupName_473_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22285_dupName_473_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22285_dupName_473_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_q;
            1'b1 : rightShiftStage0_uid22285_dupName_473_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22283_dupName_473_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22285_dupName_473_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22290_dupName_473_i_unnamed_c_compstr0_shift_x(MUX,22289)@249
    assign rightShiftStage1_uid22290_dupName_473_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22290_dupName_473_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22285_dupName_473_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22288_dupName_473_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22290_dupName_473_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22290_dupName_473_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22285_dupName_473_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22290_dupName_473_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22288_dupName_473_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22290_dupName_473_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22295_dupName_473_i_unnamed_c_compstr0_shift_x(MUX,22294)@249
    assign rightShiftStage2_uid22295_dupName_473_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22295_dupName_473_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22290_dupName_473_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22293_dupName_473_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22295_dupName_473_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22295_dupName_473_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22290_dupName_473_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22295_dupName_473_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22293_dupName_473_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22295_dupName_473_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3341_vt_select_20(BITSELECT,11840)@249
    assign i_unnamed_c_compstr3341_vt_select_20_b = rightShiftStage2_uid22295_dupName_473_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3341_vt_join(BITJOIN,11839)@249
    assign i_unnamed_c_compstr3341_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3341_vt_select_20_b};

    // i_conv_i_i_i_i_i_118_c_compstr3342_sel_x(BITSELECT,3732)@249
    assign i_conv_i_i_i_i_i_118_c_compstr3342_sel_x_b = i_unnamed_c_compstr3341_vt_join_q[15:0];

    // redist1133_i_conv_i_i_i_i_i_118_c_compstr3342_sel_x_b_1(DELAY,29361)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1133_i_conv_i_i_i_i_i_118_c_compstr3342_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_118_c_compstr3342_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22304_dupName_474_i_unnamed_c_compstr0_shift_x(BITSELECT,22303)@249
    assign rightShiftStage1Idx1Rng8_uid22304_dupName_474_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22303_dupName_474_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22306_dupName_474_i_unnamed_c_compstr0_shift_x(BITJOIN,22305)@249
    assign rightShiftStage1Idx1_uid22306_dupName_474_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22304_dupName_474_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22299_dupName_474_i_unnamed_c_compstr0_shift_x(BITSELECT,22298)@249
    assign rightShiftStage0Idx1Rng4_uid22299_dupName_474_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_q[33:4];

    // rightShiftStage0Idx1_uid22301_dupName_474_i_unnamed_c_compstr0_shift_x(BITJOIN,22300)@249
    assign rightShiftStage0Idx1_uid22301_dupName_474_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22299_dupName_474_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22303_dupName_474_i_unnamed_c_compstr0_shift_x(MUX,22302)@249
    assign rightShiftStage0_uid22303_dupName_474_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22303_dupName_474_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_q or rightShiftStage0Idx1_uid22301_dupName_474_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22303_dupName_474_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22303_dupName_474_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compstr3340_q;
            1'b1 : rightShiftStage0_uid22303_dupName_474_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22301_dupName_474_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22303_dupName_474_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22308_dupName_474_i_unnamed_c_compstr0_shift_x(MUX,22307)@249
    assign rightShiftStage1_uid22308_dupName_474_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22308_dupName_474_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22303_dupName_474_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22306_dupName_474_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22308_dupName_474_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22308_dupName_474_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22303_dupName_474_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22308_dupName_474_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22306_dupName_474_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22308_dupName_474_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3343_vt_select_21(BITSELECT,11843)@249
    assign i_unnamed_c_compstr3343_vt_select_21_b = rightShiftStage1_uid22308_dupName_474_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3343_vt_join(BITJOIN,11842)@249
    assign i_unnamed_c_compstr3343_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3343_vt_select_21_b};

    // i_unnamed_c_compstr3344_sel_x(BITSELECT,6220)@249
    assign i_unnamed_c_compstr3344_sel_x_b = i_unnamed_c_compstr3343_vt_join_q[15:0];

    // i_unnamed_c_compstr3345_BitSelect_for_a(BITSELECT,27829)@249
    assign i_unnamed_c_compstr3345_BitSelect_for_a_b = i_unnamed_c_compstr3344_sel_x_b[0:0];

    // i_unnamed_c_compstr3345_join(BITJOIN,27830)@249
    assign i_unnamed_c_compstr3345_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3345_BitSelect_for_a_b};

    // i_unnamed_c_compstr3345_vt_select_0(BITSELECT,11848)@249
    assign i_unnamed_c_compstr3345_vt_select_0_b = i_unnamed_c_compstr3345_join_q[0:0];

    // redist71_i_unnamed_c_compstr3345_vt_select_0_b_1(DELAY,28299)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist71_i_unnamed_c_compstr3345_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3345_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3345_vt_join(BITJOIN,11847)@250
    assign i_unnamed_c_compstr3345_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist71_i_unnamed_c_compstr3345_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_118_c_compstr3346(ADD,6999)@250
    assign i_add_i_i_i_i_i_i_118_c_compstr3346_a = {1'b0, i_unnamed_c_compstr3345_vt_join_q};
    assign i_add_i_i_i_i_i_i_118_c_compstr3346_b = {1'b0, redist1133_i_conv_i_i_i_i_i_118_c_compstr3342_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_118_c_compstr3346_o = $unsigned(i_add_i_i_i_i_i_i_118_c_compstr3346_a) + $unsigned(i_add_i_i_i_i_i_i_118_c_compstr3346_b);
    assign i_add_i_i_i_i_i_i_118_c_compstr3346_q = i_add_i_i_i_i_i_i_118_c_compstr3346_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_118_c_compstr3346_sel_x(BITSELECT,2193)@250
    assign bgTrunc_i_add_i_i_i_i_i_i_118_c_compstr3346_sel_x_b = i_add_i_i_i_i_i_i_118_c_compstr3346_q[15:0];

    // i_conv_i_i_i_i_i_i279_119_c_compstr3366_sel_x(BITSELECT,3861)@250
    assign i_conv_i_i_i_i_i_i279_119_c_compstr3366_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_118_c_compstr3346_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_119_c_compstr3366_vt_select_15(BITSELECT,7961)@250
    assign i_conv_i_i_i_i_i_i279_119_c_compstr3366_vt_select_15_b = i_conv_i_i_i_i_i_i279_119_c_compstr3366_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_119_c_compstr3366_vt_join(BITJOIN,7960)@250
    assign i_conv_i_i_i_i_i_i279_119_c_compstr3366_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_119_c_compstr3366_vt_select_15_b};

    // leftShiftStage0_uid25520_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x(MUX,25519)@250
    assign leftShiftStage0_uid25520_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25520_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_119_c_compstr3366_vt_join_q or leftShiftStage0Idx1_uid25518_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25520_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25520_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_119_c_compstr3366_vt_join_q;
            1'b1 : leftShiftStage0_uid25520_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25518_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25520_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25525_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x(MUX,25524)@250
    assign leftShiftStage1_uid25525_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25525_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_s or leftShiftStage0_uid25520_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25523_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25525_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25525_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q = leftShiftStage0_uid25520_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25525_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25523_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25525_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25530_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x(MUX,25529)@250
    assign leftShiftStage2_uid25530_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25530_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_s or leftShiftStage1_uid25525_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25528_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25530_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25530_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q = leftShiftStage1_uid25525_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25530_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25528_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25530_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_119_c_compstr3367_vt_select_28(BITSELECT,9484)@250
    assign i_shl_i_i_i_i_i_i_119_c_compstr3367_vt_select_28_b = leftShiftStage2_uid25530_i_shl_i_i_i_i_i_i_119_c_compstr0_shift_x_q[28:13];

    // redist362_i_shl_i_i_i_i_i_i_119_c_compstr3367_vt_select_28_b_1(DELAY,28590)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist362_i_shl_i_i_i_i_i_i_119_c_compstr3367_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_119_c_compstr3367_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_119_c_compstr3367_vt_join(BITJOIN,9483)@251
    assign i_shl_i_i_i_i_i_i_119_c_compstr3367_vt_join_q = {redist362_i_shl_i_i_i_i_i_i_119_c_compstr3367_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_offset(CONSTANT,30966)
    assign redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_offset_q = $unsigned(8'b00011000);

    // redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_rdcnt(ADD,32415)
    assign redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_a = {1'b0, redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_wraddr_q};
    assign redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_b = {1'b0, redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_o <= $unsigned(redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_a) + $unsigned(redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_b);
        end
    end
    assign redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_q = redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_o[8:0];

    // redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_inputreg0(DELAY,32410)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl);
        end
    end

    // redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_wraddr(COUNTER,32413)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_wraddr_i <= $unsigned(redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_wraddr_q = redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_wraddr_i[7:0];

    // redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem(DUALMEM,32412)
    assign redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_ia = $unsigned(redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_inputreg0_q);
    assign redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_aa = redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_wraddr_q;
    assign redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_ab = redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_aa),
        .data_a(redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_ab),
        .q_b(redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_q = redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_iq[15:0];

    // redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_outputreg0(DELAY,32411)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_outputreg0_q <= $unsigned(redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_mem_q);
        end
    end

    // redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_rdcnt(ADD,30967)
    assign redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_a = {1'b0, redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_wraddr_q};
    assign redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_b = {1'b0, redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_o <= $unsigned(redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_a) + $unsigned(redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_b);
        end
    end
    assign redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_q = redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_o[8:0];

    // redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_inputreg0(DELAY,30962)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl);
        end
    end

    // redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_wraddr(COUNTER,30965)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_wraddr_i <= $unsigned(redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_wraddr_q = redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_wraddr_i[7:0];

    // redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem(DUALMEM,30964)
    assign redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_ia = $unsigned(redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_inputreg0_q);
    assign redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_aa = redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_wraddr_q;
    assign redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_ab = redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_aa),
        .data_a(redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_ab),
        .q_b(redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_q = redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_iq[15:0];

    // redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_outputreg0(DELAY,30963)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_outputreg0_q <= $unsigned(redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_mem_q);
        end
    end

    // redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_rdcnt(ADD,30973)
    assign redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_a = {1'b0, redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_wraddr_q};
    assign redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_b = {1'b0, redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_o <= $unsigned(redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_a) + $unsigned(redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_b);
        end
    end
    assign redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_q = redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_o[8:0];

    // redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_inputreg0(DELAY,30968)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl);
        end
    end

    // redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_wraddr(COUNTER,30971)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_wraddr_i <= $unsigned(redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_wraddr_q = redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_wraddr_i[7:0];

    // redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem(DUALMEM,30970)
    assign redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_ia = $unsigned(redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_inputreg0_q);
    assign redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_aa = redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_wraddr_q;
    assign redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_ab = redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_aa),
        .data_a(redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_ab),
        .q_b(redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_q = redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_iq[15:0];

    // redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_outputreg0(DELAY,30969)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_outputreg0_q <= $unsigned(redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_mem_q);
        end
    end

    // redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_rdcnt(ADD,32409)
    assign redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_a = {1'b0, redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_wraddr_q};
    assign redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_b = {1'b0, redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_o <= $unsigned(redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_a) + $unsigned(redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_b);
        end
    end
    assign redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_q = redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_o[8:0];

    // redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_inputreg0(DELAY,32404)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl);
        end
    end

    // redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_wraddr(COUNTER,32407)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_wraddr_i <= $unsigned(redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_wraddr_q = redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_wraddr_i[7:0];

    // redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem(DUALMEM,32406)
    assign redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_ia = $unsigned(redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_inputreg0_q);
    assign redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_aa = redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_wraddr_q;
    assign redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_ab = redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_aa),
        .data_a(redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_ab),
        .q_b(redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_q = redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_iq[15:0];

    // redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_outputreg0(DELAY,32405)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_outputreg0_q <= $unsigned(redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28082)@245 + 5
    // out q@251
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368(ADD,8542)@251
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod636_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_b = $unsigned({{5{i_shl_i_i_i_i_i_i_119_c_compstr3367_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_119_c_compstr3367_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_o[33:0];

    // rightShiftStage0_uid22347_dupName_477_i_unnamed_c_compstr0_shift_x(MUX,22346)@251
    assign rightShiftStage0_uid22347_dupName_477_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22347_dupName_477_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_q or rightShiftStage0Idx1_uid22345_dupName_477_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22347_dupName_477_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22347_dupName_477_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_q;
            1'b1 : rightShiftStage0_uid22347_dupName_477_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22345_dupName_477_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22347_dupName_477_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22352_dupName_477_i_unnamed_c_compstr0_shift_x(MUX,22351)@251
    assign rightShiftStage1_uid22352_dupName_477_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22352_dupName_477_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22347_dupName_477_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22350_dupName_477_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22352_dupName_477_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22352_dupName_477_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22347_dupName_477_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22352_dupName_477_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22350_dupName_477_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22352_dupName_477_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22357_dupName_477_i_unnamed_c_compstr0_shift_x(MUX,22356)@251
    assign rightShiftStage2_uid22357_dupName_477_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22357_dupName_477_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22352_dupName_477_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22355_dupName_477_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22357_dupName_477_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22357_dupName_477_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22352_dupName_477_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22357_dupName_477_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22355_dupName_477_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22357_dupName_477_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3369_vt_select_20(BITSELECT,11862)@251
    assign i_unnamed_c_compstr3369_vt_select_20_b = rightShiftStage2_uid22357_dupName_477_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3369_vt_join(BITJOIN,11861)@251
    assign i_unnamed_c_compstr3369_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3369_vt_select_20_b};

    // i_conv_i_i_i_i_i_119_c_compstr3370_sel_x(BITSELECT,3733)@251
    assign i_conv_i_i_i_i_i_119_c_compstr3370_sel_x_b = i_unnamed_c_compstr3369_vt_join_q[15:0];

    // redist1132_i_conv_i_i_i_i_i_119_c_compstr3370_sel_x_b_1(DELAY,29360)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1132_i_conv_i_i_i_i_i_119_c_compstr3370_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_119_c_compstr3370_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22366_dupName_478_i_unnamed_c_compstr0_shift_x(BITSELECT,22365)@251
    assign rightShiftStage1Idx1Rng8_uid22366_dupName_478_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22365_dupName_478_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22368_dupName_478_i_unnamed_c_compstr0_shift_x(BITJOIN,22367)@251
    assign rightShiftStage1Idx1_uid22368_dupName_478_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22366_dupName_478_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22361_dupName_478_i_unnamed_c_compstr0_shift_x(BITSELECT,22360)@251
    assign rightShiftStage0Idx1Rng4_uid22361_dupName_478_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_q[33:4];

    // rightShiftStage0Idx1_uid22363_dupName_478_i_unnamed_c_compstr0_shift_x(BITJOIN,22362)@251
    assign rightShiftStage0Idx1_uid22363_dupName_478_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22361_dupName_478_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22365_dupName_478_i_unnamed_c_compstr0_shift_x(MUX,22364)@251
    assign rightShiftStage0_uid22365_dupName_478_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22365_dupName_478_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_q or rightShiftStage0Idx1_uid22363_dupName_478_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22365_dupName_478_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22365_dupName_478_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compstr3368_q;
            1'b1 : rightShiftStage0_uid22365_dupName_478_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22363_dupName_478_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22365_dupName_478_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22370_dupName_478_i_unnamed_c_compstr0_shift_x(MUX,22369)@251
    assign rightShiftStage1_uid22370_dupName_478_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22370_dupName_478_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22365_dupName_478_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22368_dupName_478_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22370_dupName_478_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22370_dupName_478_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22365_dupName_478_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22370_dupName_478_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22368_dupName_478_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22370_dupName_478_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3371_vt_select_21(BITSELECT,11865)@251
    assign i_unnamed_c_compstr3371_vt_select_21_b = rightShiftStage1_uid22370_dupName_478_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3371_vt_join(BITJOIN,11864)@251
    assign i_unnamed_c_compstr3371_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3371_vt_select_21_b};

    // i_unnamed_c_compstr3372_sel_x(BITSELECT,6222)@251
    assign i_unnamed_c_compstr3372_sel_x_b = i_unnamed_c_compstr3371_vt_join_q[15:0];

    // i_unnamed_c_compstr3373_BitSelect_for_a(BITSELECT,27833)@251
    assign i_unnamed_c_compstr3373_BitSelect_for_a_b = i_unnamed_c_compstr3372_sel_x_b[0:0];

    // i_unnamed_c_compstr3373_join(BITJOIN,27834)@251
    assign i_unnamed_c_compstr3373_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3373_BitSelect_for_a_b};

    // i_unnamed_c_compstr3373_vt_select_0(BITSELECT,11870)@251
    assign i_unnamed_c_compstr3373_vt_select_0_b = i_unnamed_c_compstr3373_join_q[0:0];

    // redist69_i_unnamed_c_compstr3373_vt_select_0_b_1(DELAY,28297)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist69_i_unnamed_c_compstr3373_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3373_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3373_vt_join(BITJOIN,11869)@252
    assign i_unnamed_c_compstr3373_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist69_i_unnamed_c_compstr3373_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_119_c_compstr3374(ADD,7000)@252
    assign i_add_i_i_i_i_i_i_119_c_compstr3374_a = {1'b0, i_unnamed_c_compstr3373_vt_join_q};
    assign i_add_i_i_i_i_i_i_119_c_compstr3374_b = {1'b0, redist1132_i_conv_i_i_i_i_i_119_c_compstr3370_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_119_c_compstr3374_o = $unsigned(i_add_i_i_i_i_i_i_119_c_compstr3374_a) + $unsigned(i_add_i_i_i_i_i_i_119_c_compstr3374_b);
    assign i_add_i_i_i_i_i_i_119_c_compstr3374_q = i_add_i_i_i_i_i_i_119_c_compstr3374_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_119_c_compstr3374_sel_x(BITSELECT,2194)@252
    assign bgTrunc_i_add_i_i_i_i_i_i_119_c_compstr3374_sel_x_b = i_add_i_i_i_i_i_i_119_c_compstr3374_q[15:0];

    // i_conv_i_i_i_i_i_i279_120_c_compstr3394_sel_x(BITSELECT,3863)@252
    assign i_conv_i_i_i_i_i_i279_120_c_compstr3394_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_119_c_compstr3374_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_120_c_compstr3394_vt_select_15(BITSELECT,7969)@252
    assign i_conv_i_i_i_i_i_i279_120_c_compstr3394_vt_select_15_b = i_conv_i_i_i_i_i_i279_120_c_compstr3394_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_120_c_compstr3394_vt_join(BITJOIN,7968)@252
    assign i_conv_i_i_i_i_i_i279_120_c_compstr3394_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_120_c_compstr3394_vt_select_15_b};

    // leftShiftStage0_uid25556_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x(MUX,25555)@252
    assign leftShiftStage0_uid25556_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25556_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_120_c_compstr3394_vt_join_q or leftShiftStage0Idx1_uid25554_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25556_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25556_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_120_c_compstr3394_vt_join_q;
            1'b1 : leftShiftStage0_uid25556_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25554_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25556_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25561_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x(MUX,25560)@252
    assign leftShiftStage1_uid25561_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25561_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_s or leftShiftStage0_uid25556_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25559_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25561_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25561_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q = leftShiftStage0_uid25556_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25561_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25559_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25561_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25566_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x(MUX,25565)@252
    assign leftShiftStage2_uid25566_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25566_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_s or leftShiftStage1_uid25561_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25564_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25566_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25566_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q = leftShiftStage1_uid25561_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25566_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25564_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25566_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_120_c_compstr3395_vt_select_28(BITSELECT,9490)@252
    assign i_shl_i_i_i_i_i_i_120_c_compstr3395_vt_select_28_b = leftShiftStage2_uid25566_i_shl_i_i_i_i_i_i_120_c_compstr0_shift_x_q[28:13];

    // redist360_i_shl_i_i_i_i_i_i_120_c_compstr3395_vt_select_28_b_1(DELAY,28588)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist360_i_shl_i_i_i_i_i_i_120_c_compstr3395_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_120_c_compstr3395_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_120_c_compstr3395_vt_join(BITJOIN,9489)@253
    assign i_shl_i_i_i_i_i_i_120_c_compstr3395_vt_join_q = {redist360_i_shl_i_i_i_i_i_i_120_c_compstr3395_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_offset(CONSTANT,30978)
    assign redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_offset_q = $unsigned(8'b00010110);

    // redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_rdcnt(ADD,32427)
    assign redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_a = {1'b0, redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_wraddr_q};
    assign redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_b = {1'b0, redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_o <= $unsigned(redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_a) + $unsigned(redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_b);
        end
    end
    assign redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_q = redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_o[8:0];

    // redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_inputreg0(DELAY,32422)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl);
        end
    end

    // redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_wraddr(COUNTER,32425)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_wraddr_i <= $unsigned(redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_wraddr_q = redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_wraddr_i[7:0];

    // redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem(DUALMEM,32424)
    assign redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_ia = $unsigned(redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_inputreg0_q);
    assign redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_aa = redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_wraddr_q;
    assign redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_ab = redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_aa),
        .data_a(redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_ab),
        .q_b(redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_q = redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_iq[15:0];

    // redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_outputreg0(DELAY,32423)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_outputreg0_q <= $unsigned(redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_mem_q);
        end
    end

    // redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_rdcnt(ADD,30979)
    assign redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_a = {1'b0, redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_wraddr_q};
    assign redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_b = {1'b0, redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_o <= $unsigned(redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_a) + $unsigned(redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_b);
        end
    end
    assign redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_q = redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_o[8:0];

    // redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_inputreg0(DELAY,30974)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl);
        end
    end

    // redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_wraddr(COUNTER,30977)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_wraddr_i <= $unsigned(redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_wraddr_q = redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_wraddr_i[7:0];

    // redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem(DUALMEM,30976)
    assign redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_ia = $unsigned(redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_inputreg0_q);
    assign redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_aa = redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_wraddr_q;
    assign redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_ab = redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_aa),
        .data_a(redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_ab),
        .q_b(redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_q = redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_iq[15:0];

    // redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_outputreg0(DELAY,30975)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_outputreg0_q <= $unsigned(redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_mem_q);
        end
    end

    // redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_rdcnt(ADD,30985)
    assign redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_a = {1'b0, redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_wraddr_q};
    assign redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_b = {1'b0, redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_o <= $unsigned(redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_a) + $unsigned(redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_b);
        end
    end
    assign redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_q = redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_o[8:0];

    // redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_inputreg0(DELAY,30980)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl);
        end
    end

    // redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_wraddr(COUNTER,30983)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_wraddr_i <= $unsigned(redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_wraddr_q = redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_wraddr_i[7:0];

    // redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem(DUALMEM,30982)
    assign redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_ia = $unsigned(redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_inputreg0_q);
    assign redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_aa = redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_wraddr_q;
    assign redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_ab = redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_aa),
        .data_a(redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_ab),
        .q_b(redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_q = redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_iq[15:0];

    // redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_outputreg0(DELAY,30981)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_outputreg0_q <= $unsigned(redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_mem_q);
        end
    end

    // redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_rdcnt(ADD,32421)
    assign redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_a = {1'b0, redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_wraddr_q};
    assign redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_b = {1'b0, redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_o <= $unsigned(redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_a) + $unsigned(redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_b);
        end
    end
    assign redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_q = redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_o[8:0];

    // redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_inputreg0(DELAY,32416)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl);
        end
    end

    // redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_wraddr(COUNTER,32419)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_wraddr_i <= $unsigned(redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_wraddr_q = redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_wraddr_i[7:0];

    // redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem(DUALMEM,32418)
    assign redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_ia = $unsigned(redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_inputreg0_q);
    assign redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_aa = redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_wraddr_q;
    assign redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_ab = redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_aa),
        .data_a(redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_ab),
        .q_b(redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_q = redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_iq[15:0];

    // redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_outputreg0(DELAY,32417)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_outputreg0_q <= $unsigned(redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28083)@247 + 5
    // out q@253
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396(ADD,8544)@253
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod641_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_b = $unsigned({{5{i_shl_i_i_i_i_i_i_120_c_compstr3395_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_120_c_compstr3395_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_o[33:0];

    // rightShiftStage0_uid22409_dupName_481_i_unnamed_c_compstr0_shift_x(MUX,22408)@253
    assign rightShiftStage0_uid22409_dupName_481_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22409_dupName_481_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_q or rightShiftStage0Idx1_uid22407_dupName_481_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22409_dupName_481_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22409_dupName_481_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_q;
            1'b1 : rightShiftStage0_uid22409_dupName_481_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22407_dupName_481_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22409_dupName_481_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22414_dupName_481_i_unnamed_c_compstr0_shift_x(MUX,22413)@253
    assign rightShiftStage1_uid22414_dupName_481_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22414_dupName_481_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22409_dupName_481_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22412_dupName_481_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22414_dupName_481_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22414_dupName_481_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22409_dupName_481_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22414_dupName_481_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22412_dupName_481_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22414_dupName_481_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22419_dupName_481_i_unnamed_c_compstr0_shift_x(MUX,22418)@253
    assign rightShiftStage2_uid22419_dupName_481_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22419_dupName_481_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22414_dupName_481_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22417_dupName_481_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22419_dupName_481_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22419_dupName_481_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22414_dupName_481_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22419_dupName_481_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22417_dupName_481_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22419_dupName_481_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3397_vt_select_20(BITSELECT,11884)@253
    assign i_unnamed_c_compstr3397_vt_select_20_b = rightShiftStage2_uid22419_dupName_481_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3397_vt_join(BITJOIN,11883)@253
    assign i_unnamed_c_compstr3397_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3397_vt_select_20_b};

    // i_conv_i_i_i_i_i_120_c_compstr3398_sel_x(BITSELECT,3735)@253
    assign i_conv_i_i_i_i_i_120_c_compstr3398_sel_x_b = i_unnamed_c_compstr3397_vt_join_q[15:0];

    // redist1130_i_conv_i_i_i_i_i_120_c_compstr3398_sel_x_b_1(DELAY,29358)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1130_i_conv_i_i_i_i_i_120_c_compstr3398_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_120_c_compstr3398_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22428_dupName_482_i_unnamed_c_compstr0_shift_x(BITSELECT,22427)@253
    assign rightShiftStage1Idx1Rng8_uid22428_dupName_482_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22427_dupName_482_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22430_dupName_482_i_unnamed_c_compstr0_shift_x(BITJOIN,22429)@253
    assign rightShiftStage1Idx1_uid22430_dupName_482_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22428_dupName_482_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22423_dupName_482_i_unnamed_c_compstr0_shift_x(BITSELECT,22422)@253
    assign rightShiftStage0Idx1Rng4_uid22423_dupName_482_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_q[33:4];

    // rightShiftStage0Idx1_uid22425_dupName_482_i_unnamed_c_compstr0_shift_x(BITJOIN,22424)@253
    assign rightShiftStage0Idx1_uid22425_dupName_482_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22423_dupName_482_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22427_dupName_482_i_unnamed_c_compstr0_shift_x(MUX,22426)@253
    assign rightShiftStage0_uid22427_dupName_482_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22427_dupName_482_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_q or rightShiftStage0Idx1_uid22425_dupName_482_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22427_dupName_482_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22427_dupName_482_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compstr3396_q;
            1'b1 : rightShiftStage0_uid22427_dupName_482_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22425_dupName_482_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22427_dupName_482_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22432_dupName_482_i_unnamed_c_compstr0_shift_x(MUX,22431)@253
    assign rightShiftStage1_uid22432_dupName_482_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22432_dupName_482_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22427_dupName_482_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22430_dupName_482_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22432_dupName_482_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22432_dupName_482_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22427_dupName_482_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22432_dupName_482_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22430_dupName_482_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22432_dupName_482_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3399_vt_select_21(BITSELECT,11887)@253
    assign i_unnamed_c_compstr3399_vt_select_21_b = rightShiftStage1_uid22432_dupName_482_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3399_vt_join(BITJOIN,11886)@253
    assign i_unnamed_c_compstr3399_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3399_vt_select_21_b};

    // i_unnamed_c_compstr3400_sel_x(BITSELECT,6224)@253
    assign i_unnamed_c_compstr3400_sel_x_b = i_unnamed_c_compstr3399_vt_join_q[15:0];

    // i_unnamed_c_compstr3401_BitSelect_for_a(BITSELECT,27837)@253
    assign i_unnamed_c_compstr3401_BitSelect_for_a_b = i_unnamed_c_compstr3400_sel_x_b[0:0];

    // i_unnamed_c_compstr3401_join(BITJOIN,27838)@253
    assign i_unnamed_c_compstr3401_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3401_BitSelect_for_a_b};

    // i_unnamed_c_compstr3401_vt_select_0(BITSELECT,11892)@253
    assign i_unnamed_c_compstr3401_vt_select_0_b = i_unnamed_c_compstr3401_join_q[0:0];

    // redist67_i_unnamed_c_compstr3401_vt_select_0_b_1(DELAY,28295)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist67_i_unnamed_c_compstr3401_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3401_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3401_vt_join(BITJOIN,11891)@254
    assign i_unnamed_c_compstr3401_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist67_i_unnamed_c_compstr3401_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_120_c_compstr3402(ADD,7002)@254
    assign i_add_i_i_i_i_i_i_120_c_compstr3402_a = {1'b0, i_unnamed_c_compstr3401_vt_join_q};
    assign i_add_i_i_i_i_i_i_120_c_compstr3402_b = {1'b0, redist1130_i_conv_i_i_i_i_i_120_c_compstr3398_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_120_c_compstr3402_o = $unsigned(i_add_i_i_i_i_i_i_120_c_compstr3402_a) + $unsigned(i_add_i_i_i_i_i_i_120_c_compstr3402_b);
    assign i_add_i_i_i_i_i_i_120_c_compstr3402_q = i_add_i_i_i_i_i_i_120_c_compstr3402_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_120_c_compstr3402_sel_x(BITSELECT,2196)@254
    assign bgTrunc_i_add_i_i_i_i_i_i_120_c_compstr3402_sel_x_b = i_add_i_i_i_i_i_i_120_c_compstr3402_q[15:0];

    // i_conv_i_i_i_i_i_i279_121_c_compstr3422_sel_x(BITSELECT,3864)@254
    assign i_conv_i_i_i_i_i_i279_121_c_compstr3422_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_120_c_compstr3402_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_121_c_compstr3422_vt_select_15(BITSELECT,7973)@254
    assign i_conv_i_i_i_i_i_i279_121_c_compstr3422_vt_select_15_b = i_conv_i_i_i_i_i_i279_121_c_compstr3422_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_121_c_compstr3422_vt_join(BITJOIN,7972)@254
    assign i_conv_i_i_i_i_i_i279_121_c_compstr3422_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_121_c_compstr3422_vt_select_15_b};

    // leftShiftStage0_uid25574_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x(MUX,25573)@254
    assign leftShiftStage0_uid25574_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25574_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_121_c_compstr3422_vt_join_q or leftShiftStage0Idx1_uid25572_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25574_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25574_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_121_c_compstr3422_vt_join_q;
            1'b1 : leftShiftStage0_uid25574_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25572_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25574_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25579_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x(MUX,25578)@254
    assign leftShiftStage1_uid25579_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25579_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_s or leftShiftStage0_uid25574_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25577_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25579_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25579_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q = leftShiftStage0_uid25574_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25579_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25577_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25579_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25584_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x(MUX,25583)@254
    assign leftShiftStage2_uid25584_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25584_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_s or leftShiftStage1_uid25579_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25582_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25584_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25584_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q = leftShiftStage1_uid25579_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25584_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25582_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25584_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_121_c_compstr3423_vt_select_28(BITSELECT,9493)@254
    assign i_shl_i_i_i_i_i_i_121_c_compstr3423_vt_select_28_b = leftShiftStage2_uid25584_i_shl_i_i_i_i_i_i_121_c_compstr0_shift_x_q[28:13];

    // redist359_i_shl_i_i_i_i_i_i_121_c_compstr3423_vt_select_28_b_1(DELAY,28587)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist359_i_shl_i_i_i_i_i_i_121_c_compstr3423_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_121_c_compstr3423_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_121_c_compstr3423_vt_join(BITJOIN,9492)@255
    assign i_shl_i_i_i_i_i_i_121_c_compstr3423_vt_join_q = {redist359_i_shl_i_i_i_i_i_i_121_c_compstr3423_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_offset(CONSTANT,30990)
    assign redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_offset_q = $unsigned(8'b00010100);

    // redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_rdcnt(ADD,32439)
    assign redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_a = {1'b0, redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_wraddr_q};
    assign redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_b = {1'b0, redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_o <= $unsigned(redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_a) + $unsigned(redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_b);
        end
    end
    assign redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_q = redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_o[8:0];

    // redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_inputreg0(DELAY,32434)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl);
        end
    end

    // redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_wraddr(COUNTER,32437)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_wraddr_i <= $unsigned(redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_wraddr_q = redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_wraddr_i[7:0];

    // redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem(DUALMEM,32436)
    assign redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_ia = $unsigned(redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_inputreg0_q);
    assign redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_aa = redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_wraddr_q;
    assign redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_ab = redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_aa),
        .data_a(redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_ab),
        .q_b(redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_q = redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_iq[15:0];

    // redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_outputreg0(DELAY,32435)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_outputreg0_q <= $unsigned(redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_mem_q);
        end
    end

    // redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_rdcnt(ADD,30991)
    assign redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_a = {1'b0, redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_wraddr_q};
    assign redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_b = {1'b0, redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_o <= $unsigned(redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_a) + $unsigned(redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_b);
        end
    end
    assign redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_q = redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_o[8:0];

    // redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_inputreg0(DELAY,30986)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl);
        end
    end

    // redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_wraddr(COUNTER,30989)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_wraddr_i <= $unsigned(redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_wraddr_q = redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_wraddr_i[7:0];

    // redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem(DUALMEM,30988)
    assign redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_ia = $unsigned(redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_inputreg0_q);
    assign redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_aa = redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_wraddr_q;
    assign redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_ab = redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_aa),
        .data_a(redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_ab),
        .q_b(redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_q = redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_iq[15:0];

    // redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_outputreg0(DELAY,30987)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_outputreg0_q <= $unsigned(redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_mem_q);
        end
    end

    // redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_rdcnt(ADD,30997)
    assign redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_a = {1'b0, redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_wraddr_q};
    assign redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_b = {1'b0, redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_o <= $unsigned(redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_a) + $unsigned(redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_b);
        end
    end
    assign redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_q = redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_o[8:0];

    // redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_inputreg0(DELAY,30992)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl);
        end
    end

    // redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_wraddr(COUNTER,30995)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_wraddr_i <= $unsigned(redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_wraddr_q = redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_wraddr_i[7:0];

    // redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem(DUALMEM,30994)
    assign redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_ia = $unsigned(redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_inputreg0_q);
    assign redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_aa = redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_wraddr_q;
    assign redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_ab = redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_aa),
        .data_a(redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_ab),
        .q_b(redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_q = redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_iq[15:0];

    // redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_outputreg0(DELAY,30993)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_outputreg0_q <= $unsigned(redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_mem_q);
        end
    end

    // redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_rdcnt(ADD,32433)
    assign redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_a = {1'b0, redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_wraddr_q};
    assign redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_b = {1'b0, redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_o <= $unsigned(redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_a) + $unsigned(redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_b);
        end
    end
    assign redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_q = redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_o[8:0];

    // redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_inputreg0(DELAY,32428)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl);
        end
    end

    // redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_wraddr(COUNTER,32431)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_wraddr_i <= $unsigned(redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_wraddr_q = redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_wraddr_i[7:0];

    // redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem(DUALMEM,32430)
    assign redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_ia = $unsigned(redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_inputreg0_q);
    assign redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_aa = redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_wraddr_q;
    assign redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_ab = redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_aa),
        .data_a(redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_ab),
        .q_b(redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_q = redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_iq[15:0];

    // redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_outputreg0(DELAY,32429)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_outputreg0_q <= $unsigned(redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28084)@249 + 5
    // out q@255
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424(ADD,8545)@255
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod646_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_b = $unsigned({{5{i_shl_i_i_i_i_i_i_121_c_compstr3423_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_121_c_compstr3423_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_o[33:0];

    // rightShiftStage0_uid22471_dupName_485_i_unnamed_c_compstr0_shift_x(MUX,22470)@255
    assign rightShiftStage0_uid22471_dupName_485_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22471_dupName_485_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_q or rightShiftStage0Idx1_uid22469_dupName_485_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22471_dupName_485_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22471_dupName_485_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_q;
            1'b1 : rightShiftStage0_uid22471_dupName_485_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22469_dupName_485_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22471_dupName_485_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22476_dupName_485_i_unnamed_c_compstr0_shift_x(MUX,22475)@255
    assign rightShiftStage1_uid22476_dupName_485_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22476_dupName_485_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22471_dupName_485_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22474_dupName_485_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22476_dupName_485_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22476_dupName_485_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22471_dupName_485_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22476_dupName_485_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22474_dupName_485_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22476_dupName_485_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22481_dupName_485_i_unnamed_c_compstr0_shift_x(MUX,22480)@255
    assign rightShiftStage2_uid22481_dupName_485_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22481_dupName_485_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22476_dupName_485_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22479_dupName_485_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22481_dupName_485_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22481_dupName_485_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22476_dupName_485_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22481_dupName_485_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22479_dupName_485_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22481_dupName_485_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3425_vt_select_20(BITSELECT,11906)@255
    assign i_unnamed_c_compstr3425_vt_select_20_b = rightShiftStage2_uid22481_dupName_485_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3425_vt_join(BITJOIN,11905)@255
    assign i_unnamed_c_compstr3425_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3425_vt_select_20_b};

    // i_conv_i_i_i_i_i_121_c_compstr3426_sel_x(BITSELECT,3736)@255
    assign i_conv_i_i_i_i_i_121_c_compstr3426_sel_x_b = i_unnamed_c_compstr3425_vt_join_q[15:0];

    // redist1129_i_conv_i_i_i_i_i_121_c_compstr3426_sel_x_b_1(DELAY,29357)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1129_i_conv_i_i_i_i_i_121_c_compstr3426_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_121_c_compstr3426_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22490_dupName_486_i_unnamed_c_compstr0_shift_x(BITSELECT,22489)@255
    assign rightShiftStage1Idx1Rng8_uid22490_dupName_486_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22489_dupName_486_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22492_dupName_486_i_unnamed_c_compstr0_shift_x(BITJOIN,22491)@255
    assign rightShiftStage1Idx1_uid22492_dupName_486_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22490_dupName_486_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22485_dupName_486_i_unnamed_c_compstr0_shift_x(BITSELECT,22484)@255
    assign rightShiftStage0Idx1Rng4_uid22485_dupName_486_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_q[33:4];

    // rightShiftStage0Idx1_uid22487_dupName_486_i_unnamed_c_compstr0_shift_x(BITJOIN,22486)@255
    assign rightShiftStage0Idx1_uid22487_dupName_486_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22485_dupName_486_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22489_dupName_486_i_unnamed_c_compstr0_shift_x(MUX,22488)@255
    assign rightShiftStage0_uid22489_dupName_486_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22489_dupName_486_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_q or rightShiftStage0Idx1_uid22487_dupName_486_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22489_dupName_486_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22489_dupName_486_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compstr3424_q;
            1'b1 : rightShiftStage0_uid22489_dupName_486_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22487_dupName_486_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22489_dupName_486_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22494_dupName_486_i_unnamed_c_compstr0_shift_x(MUX,22493)@255
    assign rightShiftStage1_uid22494_dupName_486_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22494_dupName_486_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22489_dupName_486_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22492_dupName_486_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22494_dupName_486_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22494_dupName_486_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22489_dupName_486_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22494_dupName_486_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22492_dupName_486_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22494_dupName_486_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3427_vt_select_21(BITSELECT,11909)@255
    assign i_unnamed_c_compstr3427_vt_select_21_b = rightShiftStage1_uid22494_dupName_486_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3427_vt_join(BITJOIN,11908)@255
    assign i_unnamed_c_compstr3427_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3427_vt_select_21_b};

    // i_unnamed_c_compstr3428_sel_x(BITSELECT,6226)@255
    assign i_unnamed_c_compstr3428_sel_x_b = i_unnamed_c_compstr3427_vt_join_q[15:0];

    // i_unnamed_c_compstr3429_BitSelect_for_a(BITSELECT,27841)@255
    assign i_unnamed_c_compstr3429_BitSelect_for_a_b = i_unnamed_c_compstr3428_sel_x_b[0:0];

    // i_unnamed_c_compstr3429_join(BITJOIN,27842)@255
    assign i_unnamed_c_compstr3429_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3429_BitSelect_for_a_b};

    // i_unnamed_c_compstr3429_vt_select_0(BITSELECT,11914)@255
    assign i_unnamed_c_compstr3429_vt_select_0_b = i_unnamed_c_compstr3429_join_q[0:0];

    // redist65_i_unnamed_c_compstr3429_vt_select_0_b_1(DELAY,28293)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist65_i_unnamed_c_compstr3429_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3429_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3429_vt_join(BITJOIN,11913)@256
    assign i_unnamed_c_compstr3429_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist65_i_unnamed_c_compstr3429_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_121_c_compstr3430(ADD,7003)@256
    assign i_add_i_i_i_i_i_i_121_c_compstr3430_a = {1'b0, i_unnamed_c_compstr3429_vt_join_q};
    assign i_add_i_i_i_i_i_i_121_c_compstr3430_b = {1'b0, redist1129_i_conv_i_i_i_i_i_121_c_compstr3426_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_121_c_compstr3430_o = $unsigned(i_add_i_i_i_i_i_i_121_c_compstr3430_a) + $unsigned(i_add_i_i_i_i_i_i_121_c_compstr3430_b);
    assign i_add_i_i_i_i_i_i_121_c_compstr3430_q = i_add_i_i_i_i_i_i_121_c_compstr3430_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_121_c_compstr3430_sel_x(BITSELECT,2197)@256
    assign bgTrunc_i_add_i_i_i_i_i_i_121_c_compstr3430_sel_x_b = i_add_i_i_i_i_i_i_121_c_compstr3430_q[15:0];

    // i_conv_i_i_i_i_i_i279_122_c_compstr3450_sel_x(BITSELECT,3865)@256
    assign i_conv_i_i_i_i_i_i279_122_c_compstr3450_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_121_c_compstr3430_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_122_c_compstr3450_vt_select_15(BITSELECT,7977)@256
    assign i_conv_i_i_i_i_i_i279_122_c_compstr3450_vt_select_15_b = i_conv_i_i_i_i_i_i279_122_c_compstr3450_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_122_c_compstr3450_vt_join(BITJOIN,7976)@256
    assign i_conv_i_i_i_i_i_i279_122_c_compstr3450_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_122_c_compstr3450_vt_select_15_b};

    // leftShiftStage0_uid25592_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x(MUX,25591)@256
    assign leftShiftStage0_uid25592_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25592_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_122_c_compstr3450_vt_join_q or leftShiftStage0Idx1_uid25590_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25592_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25592_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_122_c_compstr3450_vt_join_q;
            1'b1 : leftShiftStage0_uid25592_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25590_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25592_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25597_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x(MUX,25596)@256
    assign leftShiftStage1_uid25597_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25597_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_s or leftShiftStage0_uid25592_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25595_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25597_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25597_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q = leftShiftStage0_uid25592_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25597_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25595_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25597_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25602_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x(MUX,25601)@256
    assign leftShiftStage2_uid25602_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25602_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_s or leftShiftStage1_uid25597_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25600_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25602_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25602_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q = leftShiftStage1_uid25597_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25602_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25600_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25602_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_122_c_compstr3451_vt_select_28(BITSELECT,9496)@256
    assign i_shl_i_i_i_i_i_i_122_c_compstr3451_vt_select_28_b = leftShiftStage2_uid25602_i_shl_i_i_i_i_i_i_122_c_compstr0_shift_x_q[28:13];

    // redist358_i_shl_i_i_i_i_i_i_122_c_compstr3451_vt_select_28_b_1(DELAY,28586)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist358_i_shl_i_i_i_i_i_i_122_c_compstr3451_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_122_c_compstr3451_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_122_c_compstr3451_vt_join(BITJOIN,9495)@257
    assign i_shl_i_i_i_i_i_i_122_c_compstr3451_vt_join_q = {redist358_i_shl_i_i_i_i_i_i_122_c_compstr3451_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_offset(CONSTANT,31002)
    assign redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_offset_q = $unsigned(8'b00010010);

    // redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_rdcnt(ADD,32451)
    assign redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_a = {1'b0, redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_wraddr_q};
    assign redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_b = {1'b0, redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_o <= $unsigned(redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_a) + $unsigned(redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_b);
        end
    end
    assign redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_q = redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_o[8:0];

    // redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_inputreg0(DELAY,32446)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl);
        end
    end

    // redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_wraddr(COUNTER,32449)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_wraddr_i <= $unsigned(redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_wraddr_q = redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_wraddr_i[7:0];

    // redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem(DUALMEM,32448)
    assign redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_ia = $unsigned(redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_inputreg0_q);
    assign redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_aa = redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_wraddr_q;
    assign redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_ab = redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_aa),
        .data_a(redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_ab),
        .q_b(redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_q = redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_iq[15:0];

    // redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_outputreg0(DELAY,32447)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_outputreg0_q <= $unsigned(redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_mem_q);
        end
    end

    // redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_rdcnt(ADD,31003)
    assign redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_a = {1'b0, redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_wraddr_q};
    assign redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_b = {1'b0, redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_o <= $unsigned(redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_a) + $unsigned(redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_b);
        end
    end
    assign redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_q = redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_o[8:0];

    // redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_inputreg0(DELAY,30998)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl);
        end
    end

    // redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_wraddr(COUNTER,31001)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_wraddr_i <= $unsigned(redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_wraddr_q = redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_wraddr_i[7:0];

    // redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem(DUALMEM,31000)
    assign redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_ia = $unsigned(redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_inputreg0_q);
    assign redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_aa = redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_wraddr_q;
    assign redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_ab = redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_aa),
        .data_a(redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_ab),
        .q_b(redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_q = redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_iq[15:0];

    // redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_outputreg0(DELAY,30999)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_outputreg0_q <= $unsigned(redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_mem_q);
        end
    end

    // redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_rdcnt(ADD,31009)
    assign redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_a = {1'b0, redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_wraddr_q};
    assign redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_b = {1'b0, redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_o <= $unsigned(redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_a) + $unsigned(redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_b);
        end
    end
    assign redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_q = redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_o[8:0];

    // redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_inputreg0(DELAY,31004)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl);
        end
    end

    // redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_wraddr(COUNTER,31007)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_wraddr_i <= $unsigned(redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_wraddr_q = redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_wraddr_i[7:0];

    // redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem(DUALMEM,31006)
    assign redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_ia = $unsigned(redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_inputreg0_q);
    assign redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_aa = redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_wraddr_q;
    assign redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_ab = redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_aa),
        .data_a(redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_ab),
        .q_b(redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_q = redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_iq[15:0];

    // redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_outputreg0(DELAY,31005)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_outputreg0_q <= $unsigned(redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_mem_q);
        end
    end

    // redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_rdcnt(ADD,32445)
    assign redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_a = {1'b0, redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_wraddr_q};
    assign redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_b = {1'b0, redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_o <= $unsigned(redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_a) + $unsigned(redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_b);
        end
    end
    assign redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_q = redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_o[8:0];

    // redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_inputreg0(DELAY,32440)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl);
        end
    end

    // redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_wraddr(COUNTER,32443)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_wraddr_i <= $unsigned(redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_wraddr_q = redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_wraddr_i[7:0];

    // redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem(DUALMEM,32442)
    assign redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_ia = $unsigned(redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_inputreg0_q);
    assign redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_aa = redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_wraddr_q;
    assign redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_ab = redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_aa),
        .data_a(redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_ab),
        .q_b(redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_q = redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_iq[15:0];

    // redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_outputreg0(DELAY,32441)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_outputreg0_q <= $unsigned(redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28085)@251 + 5
    // out q@257
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452(ADD,8546)@257
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod651_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_b = $unsigned({{5{i_shl_i_i_i_i_i_i_122_c_compstr3451_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_122_c_compstr3451_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_o[33:0];

    // rightShiftStage0_uid22533_dupName_489_i_unnamed_c_compstr0_shift_x(MUX,22532)@257
    assign rightShiftStage0_uid22533_dupName_489_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22533_dupName_489_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_q or rightShiftStage0Idx1_uid22531_dupName_489_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22533_dupName_489_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22533_dupName_489_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_q;
            1'b1 : rightShiftStage0_uid22533_dupName_489_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22531_dupName_489_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22533_dupName_489_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22538_dupName_489_i_unnamed_c_compstr0_shift_x(MUX,22537)@257
    assign rightShiftStage1_uid22538_dupName_489_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22538_dupName_489_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22533_dupName_489_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22536_dupName_489_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22538_dupName_489_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22538_dupName_489_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22533_dupName_489_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22538_dupName_489_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22536_dupName_489_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22538_dupName_489_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22543_dupName_489_i_unnamed_c_compstr0_shift_x(MUX,22542)@257
    assign rightShiftStage2_uid22543_dupName_489_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22543_dupName_489_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22538_dupName_489_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22541_dupName_489_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22543_dupName_489_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22543_dupName_489_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22538_dupName_489_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22543_dupName_489_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22541_dupName_489_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22543_dupName_489_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3453_vt_select_20(BITSELECT,11928)@257
    assign i_unnamed_c_compstr3453_vt_select_20_b = rightShiftStage2_uid22543_dupName_489_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3453_vt_join(BITJOIN,11927)@257
    assign i_unnamed_c_compstr3453_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3453_vt_select_20_b};

    // i_conv_i_i_i_i_i_122_c_compstr3454_sel_x(BITSELECT,3737)@257
    assign i_conv_i_i_i_i_i_122_c_compstr3454_sel_x_b = i_unnamed_c_compstr3453_vt_join_q[15:0];

    // redist1128_i_conv_i_i_i_i_i_122_c_compstr3454_sel_x_b_1(DELAY,29356)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1128_i_conv_i_i_i_i_i_122_c_compstr3454_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_122_c_compstr3454_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22552_dupName_490_i_unnamed_c_compstr0_shift_x(BITSELECT,22551)@257
    assign rightShiftStage1Idx1Rng8_uid22552_dupName_490_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22551_dupName_490_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22554_dupName_490_i_unnamed_c_compstr0_shift_x(BITJOIN,22553)@257
    assign rightShiftStage1Idx1_uid22554_dupName_490_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22552_dupName_490_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22547_dupName_490_i_unnamed_c_compstr0_shift_x(BITSELECT,22546)@257
    assign rightShiftStage0Idx1Rng4_uid22547_dupName_490_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_q[33:4];

    // rightShiftStage0Idx1_uid22549_dupName_490_i_unnamed_c_compstr0_shift_x(BITJOIN,22548)@257
    assign rightShiftStage0Idx1_uid22549_dupName_490_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22547_dupName_490_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22551_dupName_490_i_unnamed_c_compstr0_shift_x(MUX,22550)@257
    assign rightShiftStage0_uid22551_dupName_490_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22551_dupName_490_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_q or rightShiftStage0Idx1_uid22549_dupName_490_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22551_dupName_490_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22551_dupName_490_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compstr3452_q;
            1'b1 : rightShiftStage0_uid22551_dupName_490_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22549_dupName_490_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22551_dupName_490_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22556_dupName_490_i_unnamed_c_compstr0_shift_x(MUX,22555)@257
    assign rightShiftStage1_uid22556_dupName_490_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22556_dupName_490_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22551_dupName_490_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22554_dupName_490_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22556_dupName_490_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22556_dupName_490_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22551_dupName_490_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22556_dupName_490_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22554_dupName_490_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22556_dupName_490_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3455_vt_select_21(BITSELECT,11931)@257
    assign i_unnamed_c_compstr3455_vt_select_21_b = rightShiftStage1_uid22556_dupName_490_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3455_vt_join(BITJOIN,11930)@257
    assign i_unnamed_c_compstr3455_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3455_vt_select_21_b};

    // i_unnamed_c_compstr3456_sel_x(BITSELECT,6228)@257
    assign i_unnamed_c_compstr3456_sel_x_b = i_unnamed_c_compstr3455_vt_join_q[15:0];

    // i_unnamed_c_compstr3457_BitSelect_for_a(BITSELECT,27845)@257
    assign i_unnamed_c_compstr3457_BitSelect_for_a_b = i_unnamed_c_compstr3456_sel_x_b[0:0];

    // i_unnamed_c_compstr3457_join(BITJOIN,27846)@257
    assign i_unnamed_c_compstr3457_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3457_BitSelect_for_a_b};

    // i_unnamed_c_compstr3457_vt_select_0(BITSELECT,11936)@257
    assign i_unnamed_c_compstr3457_vt_select_0_b = i_unnamed_c_compstr3457_join_q[0:0];

    // redist63_i_unnamed_c_compstr3457_vt_select_0_b_1(DELAY,28291)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist63_i_unnamed_c_compstr3457_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3457_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3457_vt_join(BITJOIN,11935)@258
    assign i_unnamed_c_compstr3457_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist63_i_unnamed_c_compstr3457_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_122_c_compstr3458(ADD,7004)@258
    assign i_add_i_i_i_i_i_i_122_c_compstr3458_a = {1'b0, i_unnamed_c_compstr3457_vt_join_q};
    assign i_add_i_i_i_i_i_i_122_c_compstr3458_b = {1'b0, redist1128_i_conv_i_i_i_i_i_122_c_compstr3454_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_122_c_compstr3458_o = $unsigned(i_add_i_i_i_i_i_i_122_c_compstr3458_a) + $unsigned(i_add_i_i_i_i_i_i_122_c_compstr3458_b);
    assign i_add_i_i_i_i_i_i_122_c_compstr3458_q = i_add_i_i_i_i_i_i_122_c_compstr3458_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_122_c_compstr3458_sel_x(BITSELECT,2198)@258
    assign bgTrunc_i_add_i_i_i_i_i_i_122_c_compstr3458_sel_x_b = i_add_i_i_i_i_i_i_122_c_compstr3458_q[15:0];

    // i_conv_i_i_i_i_i_i279_123_c_compstr3478_sel_x(BITSELECT,3866)@258
    assign i_conv_i_i_i_i_i_i279_123_c_compstr3478_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_122_c_compstr3458_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_123_c_compstr3478_vt_select_15(BITSELECT,7981)@258
    assign i_conv_i_i_i_i_i_i279_123_c_compstr3478_vt_select_15_b = i_conv_i_i_i_i_i_i279_123_c_compstr3478_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_123_c_compstr3478_vt_join(BITJOIN,7980)@258
    assign i_conv_i_i_i_i_i_i279_123_c_compstr3478_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_123_c_compstr3478_vt_select_15_b};

    // leftShiftStage0_uid25610_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x(MUX,25609)@258
    assign leftShiftStage0_uid25610_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25610_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_123_c_compstr3478_vt_join_q or leftShiftStage0Idx1_uid25608_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25610_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25610_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_123_c_compstr3478_vt_join_q;
            1'b1 : leftShiftStage0_uid25610_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25608_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25610_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25615_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x(MUX,25614)@258
    assign leftShiftStage1_uid25615_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25615_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_s or leftShiftStage0_uid25610_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25613_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25615_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25615_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q = leftShiftStage0_uid25610_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25615_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25613_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25615_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25620_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x(MUX,25619)@258
    assign leftShiftStage2_uid25620_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25620_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_s or leftShiftStage1_uid25615_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25618_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25620_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25620_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q = leftShiftStage1_uid25615_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25620_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25618_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25620_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_123_c_compstr3479_vt_select_28(BITSELECT,9499)@258
    assign i_shl_i_i_i_i_i_i_123_c_compstr3479_vt_select_28_b = leftShiftStage2_uid25620_i_shl_i_i_i_i_i_i_123_c_compstr0_shift_x_q[28:13];

    // redist357_i_shl_i_i_i_i_i_i_123_c_compstr3479_vt_select_28_b_1(DELAY,28585)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist357_i_shl_i_i_i_i_i_i_123_c_compstr3479_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_123_c_compstr3479_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_123_c_compstr3479_vt_join(BITJOIN,9498)@259
    assign i_shl_i_i_i_i_i_i_123_c_compstr3479_vt_join_q = {redist357_i_shl_i_i_i_i_i_i_123_c_compstr3479_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_offset(CONSTANT,31014)
    assign redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_offset_q = $unsigned(8'b00010000);

    // redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_rdcnt(ADD,32463)
    assign redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_a = {1'b0, redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_wraddr_q};
    assign redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_b = {1'b0, redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_o <= $unsigned(redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_a) + $unsigned(redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_b);
        end
    end
    assign redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_q = redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_o[8:0];

    // redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_inputreg0(DELAY,32458)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl);
        end
    end

    // redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_wraddr(COUNTER,32461)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_wraddr_i <= $unsigned(redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_wraddr_q = redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_wraddr_i[7:0];

    // redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem(DUALMEM,32460)
    assign redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_ia = $unsigned(redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_inputreg0_q);
    assign redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_aa = redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_wraddr_q;
    assign redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_ab = redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_aa),
        .data_a(redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_ab),
        .q_b(redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_q = redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_iq[15:0];

    // redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_outputreg0(DELAY,32459)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_outputreg0_q <= $unsigned(redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_mem_q);
        end
    end

    // redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_rdcnt(ADD,31015)
    assign redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_a = {1'b0, redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_wraddr_q};
    assign redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_b = {1'b0, redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_o <= $unsigned(redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_a) + $unsigned(redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_b);
        end
    end
    assign redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_q = redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_o[8:0];

    // redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_inputreg0(DELAY,31010)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl);
        end
    end

    // redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_wraddr(COUNTER,31013)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_wraddr_i <= $unsigned(redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_wraddr_q = redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_wraddr_i[7:0];

    // redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem(DUALMEM,31012)
    assign redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_ia = $unsigned(redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_inputreg0_q);
    assign redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_aa = redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_wraddr_q;
    assign redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_ab = redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_aa),
        .data_a(redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_ab),
        .q_b(redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_q = redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_iq[15:0];

    // redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_outputreg0(DELAY,31011)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_outputreg0_q <= $unsigned(redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_mem_q);
        end
    end

    // redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_rdcnt(ADD,31021)
    assign redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_a = {1'b0, redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_wraddr_q};
    assign redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_b = {1'b0, redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_o <= $unsigned(redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_a) + $unsigned(redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_b);
        end
    end
    assign redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_q = redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_o[8:0];

    // redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_inputreg0(DELAY,31016)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl);
        end
    end

    // redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_wraddr(COUNTER,31019)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_wraddr_i <= $unsigned(redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_wraddr_q = redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_wraddr_i[7:0];

    // redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem(DUALMEM,31018)
    assign redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_ia = $unsigned(redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_inputreg0_q);
    assign redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_aa = redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_wraddr_q;
    assign redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_ab = redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_aa),
        .data_a(redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_ab),
        .q_b(redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_q = redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_iq[15:0];

    // redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_outputreg0(DELAY,31017)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_outputreg0_q <= $unsigned(redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_mem_q);
        end
    end

    // redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_rdcnt(ADD,32457)
    assign redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_a = {1'b0, redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_wraddr_q};
    assign redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_b = {1'b0, redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_o <= $unsigned(redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_a) + $unsigned(redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_b);
        end
    end
    assign redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_q = redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_o[8:0];

    // redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_inputreg0(DELAY,32452)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl);
        end
    end

    // redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_wraddr(COUNTER,32455)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_wraddr_i <= $unsigned(redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_wraddr_q = redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_wraddr_i[7:0];

    // redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem(DUALMEM,32454)
    assign redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_ia = $unsigned(redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_inputreg0_q);
    assign redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_aa = redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_wraddr_q;
    assign redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_ab = redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_aa),
        .data_a(redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_ab),
        .q_b(redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_q = redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_iq[15:0];

    // redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_outputreg0(DELAY,32453)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_outputreg0_q <= $unsigned(redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28086)@253 + 5
    // out q@259
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480(ADD,8547)@259
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod656_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_b = $unsigned({{5{i_shl_i_i_i_i_i_i_123_c_compstr3479_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_123_c_compstr3479_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_o[33:0];

    // rightShiftStage0_uid22595_dupName_493_i_unnamed_c_compstr0_shift_x(MUX,22594)@259
    assign rightShiftStage0_uid22595_dupName_493_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22595_dupName_493_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_q or rightShiftStage0Idx1_uid22593_dupName_493_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22595_dupName_493_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22595_dupName_493_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_q;
            1'b1 : rightShiftStage0_uid22595_dupName_493_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22593_dupName_493_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22595_dupName_493_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22600_dupName_493_i_unnamed_c_compstr0_shift_x(MUX,22599)@259
    assign rightShiftStage1_uid22600_dupName_493_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22600_dupName_493_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22595_dupName_493_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22598_dupName_493_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22600_dupName_493_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22600_dupName_493_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22595_dupName_493_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22600_dupName_493_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22598_dupName_493_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22600_dupName_493_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22605_dupName_493_i_unnamed_c_compstr0_shift_x(MUX,22604)@259
    assign rightShiftStage2_uid22605_dupName_493_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22605_dupName_493_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22600_dupName_493_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22603_dupName_493_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22605_dupName_493_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22605_dupName_493_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22600_dupName_493_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22605_dupName_493_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22603_dupName_493_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22605_dupName_493_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3481_vt_select_20(BITSELECT,11956)@259
    assign i_unnamed_c_compstr3481_vt_select_20_b = rightShiftStage2_uid22605_dupName_493_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3481_vt_join(BITJOIN,11955)@259
    assign i_unnamed_c_compstr3481_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3481_vt_select_20_b};

    // i_conv_i_i_i_i_i_123_c_compstr3482_sel_x(BITSELECT,3738)@259
    assign i_conv_i_i_i_i_i_123_c_compstr3482_sel_x_b = i_unnamed_c_compstr3481_vt_join_q[15:0];

    // redist1127_i_conv_i_i_i_i_i_123_c_compstr3482_sel_x_b_1(DELAY,29355)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1127_i_conv_i_i_i_i_i_123_c_compstr3482_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_123_c_compstr3482_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22614_dupName_494_i_unnamed_c_compstr0_shift_x(BITSELECT,22613)@259
    assign rightShiftStage1Idx1Rng8_uid22614_dupName_494_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22613_dupName_494_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22616_dupName_494_i_unnamed_c_compstr0_shift_x(BITJOIN,22615)@259
    assign rightShiftStage1Idx1_uid22616_dupName_494_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22614_dupName_494_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22609_dupName_494_i_unnamed_c_compstr0_shift_x(BITSELECT,22608)@259
    assign rightShiftStage0Idx1Rng4_uid22609_dupName_494_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_q[33:4];

    // rightShiftStage0Idx1_uid22611_dupName_494_i_unnamed_c_compstr0_shift_x(BITJOIN,22610)@259
    assign rightShiftStage0Idx1_uid22611_dupName_494_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22609_dupName_494_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22613_dupName_494_i_unnamed_c_compstr0_shift_x(MUX,22612)@259
    assign rightShiftStage0_uid22613_dupName_494_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22613_dupName_494_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_q or rightShiftStage0Idx1_uid22611_dupName_494_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22613_dupName_494_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22613_dupName_494_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compstr3480_q;
            1'b1 : rightShiftStage0_uid22613_dupName_494_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22611_dupName_494_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22613_dupName_494_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22618_dupName_494_i_unnamed_c_compstr0_shift_x(MUX,22617)@259
    assign rightShiftStage1_uid22618_dupName_494_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22618_dupName_494_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22613_dupName_494_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22616_dupName_494_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22618_dupName_494_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22618_dupName_494_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22613_dupName_494_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22618_dupName_494_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22616_dupName_494_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22618_dupName_494_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3483_vt_select_21(BITSELECT,11959)@259
    assign i_unnamed_c_compstr3483_vt_select_21_b = rightShiftStage1_uid22618_dupName_494_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3483_vt_join(BITJOIN,11958)@259
    assign i_unnamed_c_compstr3483_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3483_vt_select_21_b};

    // i_unnamed_c_compstr3484_sel_x(BITSELECT,6231)@259
    assign i_unnamed_c_compstr3484_sel_x_b = i_unnamed_c_compstr3483_vt_join_q[15:0];

    // i_unnamed_c_compstr3485_BitSelect_for_a(BITSELECT,27849)@259
    assign i_unnamed_c_compstr3485_BitSelect_for_a_b = i_unnamed_c_compstr3484_sel_x_b[0:0];

    // i_unnamed_c_compstr3485_join(BITJOIN,27850)@259
    assign i_unnamed_c_compstr3485_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3485_BitSelect_for_a_b};

    // i_unnamed_c_compstr3485_vt_select_0(BITSELECT,11964)@259
    assign i_unnamed_c_compstr3485_vt_select_0_b = i_unnamed_c_compstr3485_join_q[0:0];

    // redist61_i_unnamed_c_compstr3485_vt_select_0_b_1(DELAY,28289)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist61_i_unnamed_c_compstr3485_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3485_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3485_vt_join(BITJOIN,11963)@260
    assign i_unnamed_c_compstr3485_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist61_i_unnamed_c_compstr3485_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_123_c_compstr3486(ADD,7005)@260
    assign i_add_i_i_i_i_i_i_123_c_compstr3486_a = {1'b0, i_unnamed_c_compstr3485_vt_join_q};
    assign i_add_i_i_i_i_i_i_123_c_compstr3486_b = {1'b0, redist1127_i_conv_i_i_i_i_i_123_c_compstr3482_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_123_c_compstr3486_o = $unsigned(i_add_i_i_i_i_i_i_123_c_compstr3486_a) + $unsigned(i_add_i_i_i_i_i_i_123_c_compstr3486_b);
    assign i_add_i_i_i_i_i_i_123_c_compstr3486_q = i_add_i_i_i_i_i_i_123_c_compstr3486_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_123_c_compstr3486_sel_x(BITSELECT,2199)@260
    assign bgTrunc_i_add_i_i_i_i_i_i_123_c_compstr3486_sel_x_b = i_add_i_i_i_i_i_i_123_c_compstr3486_q[15:0];

    // i_conv_i_i_i_i_i_i279_124_c_compstr3506_sel_x(BITSELECT,3867)@260
    assign i_conv_i_i_i_i_i_i279_124_c_compstr3506_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_123_c_compstr3486_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_124_c_compstr3506_vt_select_15(BITSELECT,7985)@260
    assign i_conv_i_i_i_i_i_i279_124_c_compstr3506_vt_select_15_b = i_conv_i_i_i_i_i_i279_124_c_compstr3506_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_124_c_compstr3506_vt_join(BITJOIN,7984)@260
    assign i_conv_i_i_i_i_i_i279_124_c_compstr3506_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_124_c_compstr3506_vt_select_15_b};

    // leftShiftStage0_uid25628_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x(MUX,25627)@260
    assign leftShiftStage0_uid25628_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25628_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_124_c_compstr3506_vt_join_q or leftShiftStage0Idx1_uid25626_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25628_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25628_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_124_c_compstr3506_vt_join_q;
            1'b1 : leftShiftStage0_uid25628_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25626_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25628_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25633_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x(MUX,25632)@260
    assign leftShiftStage1_uid25633_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25633_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_s or leftShiftStage0_uid25628_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25631_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25633_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25633_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q = leftShiftStage0_uid25628_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25633_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25631_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25633_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25638_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x(MUX,25637)@260
    assign leftShiftStage2_uid25638_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25638_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_s or leftShiftStage1_uid25633_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25636_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25638_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25638_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q = leftShiftStage1_uid25633_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25638_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25636_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25638_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_124_c_compstr3507_vt_select_28(BITSELECT,9502)@260
    assign i_shl_i_i_i_i_i_i_124_c_compstr3507_vt_select_28_b = leftShiftStage2_uid25638_i_shl_i_i_i_i_i_i_124_c_compstr0_shift_x_q[28:13];

    // redist356_i_shl_i_i_i_i_i_i_124_c_compstr3507_vt_select_28_b_1(DELAY,28584)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist356_i_shl_i_i_i_i_i_i_124_c_compstr3507_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_124_c_compstr3507_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_124_c_compstr3507_vt_join(BITJOIN,9501)@261
    assign i_shl_i_i_i_i_i_i_124_c_compstr3507_vt_join_q = {redist356_i_shl_i_i_i_i_i_i_124_c_compstr3507_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_offset(CONSTANT,31026)
    assign redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_offset_q = $unsigned(8'b00001110);

    // redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_rdcnt(ADD,32475)
    assign redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_a = {1'b0, redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_wraddr_q};
    assign redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_b = {1'b0, redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_o <= $unsigned(redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_a) + $unsigned(redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_b);
        end
    end
    assign redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_q = redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_o[8:0];

    // redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_inputreg0(DELAY,32470)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl);
        end
    end

    // redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_wraddr(COUNTER,32473)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_wraddr_i <= $unsigned(redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_wraddr_q = redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_wraddr_i[7:0];

    // redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem(DUALMEM,32472)
    assign redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_ia = $unsigned(redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_inputreg0_q);
    assign redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_aa = redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_wraddr_q;
    assign redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_ab = redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_aa),
        .data_a(redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_ab),
        .q_b(redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_q = redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_iq[15:0];

    // redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_outputreg0(DELAY,32471)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_outputreg0_q <= $unsigned(redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_mem_q);
        end
    end

    // redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_rdcnt(ADD,31027)
    assign redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_a = {1'b0, redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_wraddr_q};
    assign redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_b = {1'b0, redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_o <= $unsigned(redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_a) + $unsigned(redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_b);
        end
    end
    assign redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_q = redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_o[8:0];

    // redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_inputreg0(DELAY,31022)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl);
        end
    end

    // redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_wraddr(COUNTER,31025)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_wraddr_i <= $unsigned(redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_wraddr_q = redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_wraddr_i[7:0];

    // redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem(DUALMEM,31024)
    assign redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_ia = $unsigned(redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_inputreg0_q);
    assign redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_aa = redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_wraddr_q;
    assign redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_ab = redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_aa),
        .data_a(redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_ab),
        .q_b(redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_q = redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_iq[15:0];

    // redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_outputreg0(DELAY,31023)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_outputreg0_q <= $unsigned(redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_mem_q);
        end
    end

    // redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_rdcnt(ADD,31033)
    assign redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_a = {1'b0, redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_wraddr_q};
    assign redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_b = {1'b0, redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_o <= $unsigned(redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_a) + $unsigned(redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_b);
        end
    end
    assign redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_q = redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_o[8:0];

    // redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_inputreg0(DELAY,31028)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl);
        end
    end

    // redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_wraddr(COUNTER,31031)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_wraddr_i <= $unsigned(redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_wraddr_q = redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_wraddr_i[7:0];

    // redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem(DUALMEM,31030)
    assign redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_ia = $unsigned(redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_inputreg0_q);
    assign redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_aa = redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_wraddr_q;
    assign redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_ab = redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_aa),
        .data_a(redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_ab),
        .q_b(redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_q = redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_iq[15:0];

    // redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_outputreg0(DELAY,31029)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_outputreg0_q <= $unsigned(redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_mem_q);
        end
    end

    // redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_rdcnt(ADD,32469)
    assign redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_a = {1'b0, redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_wraddr_q};
    assign redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_b = {1'b0, redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_o <= $unsigned(redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_a) + $unsigned(redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_b);
        end
    end
    assign redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_q = redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_o[8:0];

    // redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_inputreg0(DELAY,32464)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl);
        end
    end

    // redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_wraddr(COUNTER,32467)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_wraddr_i <= $unsigned(redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_wraddr_q = redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_wraddr_i[7:0];

    // redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem(DUALMEM,32466)
    assign redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_ia = $unsigned(redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_inputreg0_q);
    assign redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_aa = redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_wraddr_q;
    assign redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_ab = redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_aa),
        .data_a(redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_ab),
        .q_b(redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_q = redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_iq[15:0];

    // redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_outputreg0(DELAY,32465)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_outputreg0_q <= $unsigned(redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28087)@255 + 5
    // out q@261
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508(ADD,8548)@261
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod661_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_b = $unsigned({{5{i_shl_i_i_i_i_i_i_124_c_compstr3507_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_124_c_compstr3507_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_o[33:0];

    // rightShiftStage0_uid22657_dupName_497_i_unnamed_c_compstr0_shift_x(MUX,22656)@261
    assign rightShiftStage0_uid22657_dupName_497_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22657_dupName_497_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_q or rightShiftStage0Idx1_uid22655_dupName_497_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22657_dupName_497_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22657_dupName_497_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_q;
            1'b1 : rightShiftStage0_uid22657_dupName_497_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22655_dupName_497_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22657_dupName_497_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22662_dupName_497_i_unnamed_c_compstr0_shift_x(MUX,22661)@261
    assign rightShiftStage1_uid22662_dupName_497_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22662_dupName_497_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22657_dupName_497_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22660_dupName_497_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22662_dupName_497_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22662_dupName_497_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22657_dupName_497_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22662_dupName_497_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22660_dupName_497_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22662_dupName_497_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22667_dupName_497_i_unnamed_c_compstr0_shift_x(MUX,22666)@261
    assign rightShiftStage2_uid22667_dupName_497_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22667_dupName_497_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22662_dupName_497_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22665_dupName_497_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22667_dupName_497_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22667_dupName_497_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22662_dupName_497_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22667_dupName_497_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22665_dupName_497_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22667_dupName_497_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3509_vt_select_20(BITSELECT,11983)@261
    assign i_unnamed_c_compstr3509_vt_select_20_b = rightShiftStage2_uid22667_dupName_497_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3509_vt_join(BITJOIN,11982)@261
    assign i_unnamed_c_compstr3509_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3509_vt_select_20_b};

    // i_conv_i_i_i_i_i_124_c_compstr3510_sel_x(BITSELECT,3739)@261
    assign i_conv_i_i_i_i_i_124_c_compstr3510_sel_x_b = i_unnamed_c_compstr3509_vt_join_q[15:0];

    // redist1126_i_conv_i_i_i_i_i_124_c_compstr3510_sel_x_b_1(DELAY,29354)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1126_i_conv_i_i_i_i_i_124_c_compstr3510_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_124_c_compstr3510_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22676_dupName_498_i_unnamed_c_compstr0_shift_x(BITSELECT,22675)@261
    assign rightShiftStage1Idx1Rng8_uid22676_dupName_498_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22675_dupName_498_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22678_dupName_498_i_unnamed_c_compstr0_shift_x(BITJOIN,22677)@261
    assign rightShiftStage1Idx1_uid22678_dupName_498_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22676_dupName_498_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22671_dupName_498_i_unnamed_c_compstr0_shift_x(BITSELECT,22670)@261
    assign rightShiftStage0Idx1Rng4_uid22671_dupName_498_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_q[33:4];

    // rightShiftStage0Idx1_uid22673_dupName_498_i_unnamed_c_compstr0_shift_x(BITJOIN,22672)@261
    assign rightShiftStage0Idx1_uid22673_dupName_498_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22671_dupName_498_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22675_dupName_498_i_unnamed_c_compstr0_shift_x(MUX,22674)@261
    assign rightShiftStage0_uid22675_dupName_498_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22675_dupName_498_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_q or rightShiftStage0Idx1_uid22673_dupName_498_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22675_dupName_498_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22675_dupName_498_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compstr3508_q;
            1'b1 : rightShiftStage0_uid22675_dupName_498_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22673_dupName_498_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22675_dupName_498_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22680_dupName_498_i_unnamed_c_compstr0_shift_x(MUX,22679)@261
    assign rightShiftStage1_uid22680_dupName_498_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22680_dupName_498_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22675_dupName_498_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22678_dupName_498_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22680_dupName_498_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22680_dupName_498_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22675_dupName_498_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22680_dupName_498_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22678_dupName_498_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22680_dupName_498_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3511_vt_select_21(BITSELECT,11986)@261
    assign i_unnamed_c_compstr3511_vt_select_21_b = rightShiftStage1_uid22680_dupName_498_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3511_vt_join(BITJOIN,11985)@261
    assign i_unnamed_c_compstr3511_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3511_vt_select_21_b};

    // i_unnamed_c_compstr3512_sel_x(BITSELECT,6233)@261
    assign i_unnamed_c_compstr3512_sel_x_b = i_unnamed_c_compstr3511_vt_join_q[15:0];

    // i_unnamed_c_compstr3513_BitSelect_for_a(BITSELECT,27855)@261
    assign i_unnamed_c_compstr3513_BitSelect_for_a_b = i_unnamed_c_compstr3512_sel_x_b[0:0];

    // i_unnamed_c_compstr3513_join(BITJOIN,27856)@261
    assign i_unnamed_c_compstr3513_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3513_BitSelect_for_a_b};

    // i_unnamed_c_compstr3513_vt_select_0(BITSELECT,11991)@261
    assign i_unnamed_c_compstr3513_vt_select_0_b = i_unnamed_c_compstr3513_join_q[0:0];

    // redist58_i_unnamed_c_compstr3513_vt_select_0_b_1(DELAY,28286)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist58_i_unnamed_c_compstr3513_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3513_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3513_vt_join(BITJOIN,11990)@262
    assign i_unnamed_c_compstr3513_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist58_i_unnamed_c_compstr3513_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_124_c_compstr3514(ADD,7006)@262
    assign i_add_i_i_i_i_i_i_124_c_compstr3514_a = {1'b0, i_unnamed_c_compstr3513_vt_join_q};
    assign i_add_i_i_i_i_i_i_124_c_compstr3514_b = {1'b0, redist1126_i_conv_i_i_i_i_i_124_c_compstr3510_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_124_c_compstr3514_o = $unsigned(i_add_i_i_i_i_i_i_124_c_compstr3514_a) + $unsigned(i_add_i_i_i_i_i_i_124_c_compstr3514_b);
    assign i_add_i_i_i_i_i_i_124_c_compstr3514_q = i_add_i_i_i_i_i_i_124_c_compstr3514_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_124_c_compstr3514_sel_x(BITSELECT,2200)@262
    assign bgTrunc_i_add_i_i_i_i_i_i_124_c_compstr3514_sel_x_b = i_add_i_i_i_i_i_i_124_c_compstr3514_q[15:0];

    // i_conv_i_i_i_i_i_i279_125_c_compstr3534_sel_x(BITSELECT,3868)@262
    assign i_conv_i_i_i_i_i_i279_125_c_compstr3534_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_124_c_compstr3514_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_125_c_compstr3534_vt_select_15(BITSELECT,7989)@262
    assign i_conv_i_i_i_i_i_i279_125_c_compstr3534_vt_select_15_b = i_conv_i_i_i_i_i_i279_125_c_compstr3534_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_125_c_compstr3534_vt_join(BITJOIN,7988)@262
    assign i_conv_i_i_i_i_i_i279_125_c_compstr3534_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_125_c_compstr3534_vt_select_15_b};

    // leftShiftStage0_uid25646_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x(MUX,25645)@262
    assign leftShiftStage0_uid25646_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25646_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_125_c_compstr3534_vt_join_q or leftShiftStage0Idx1_uid25644_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25646_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25646_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_125_c_compstr3534_vt_join_q;
            1'b1 : leftShiftStage0_uid25646_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25644_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25646_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25651_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x(MUX,25650)@262
    assign leftShiftStage1_uid25651_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25651_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_s or leftShiftStage0_uid25646_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25649_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25651_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25651_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q = leftShiftStage0_uid25646_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25651_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25649_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25651_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25656_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x(MUX,25655)@262
    assign leftShiftStage2_uid25656_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25656_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_s or leftShiftStage1_uid25651_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25654_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25656_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25656_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q = leftShiftStage1_uid25651_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25656_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25654_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25656_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_125_c_compstr3535_vt_select_28(BITSELECT,9505)@262
    assign i_shl_i_i_i_i_i_i_125_c_compstr3535_vt_select_28_b = leftShiftStage2_uid25656_i_shl_i_i_i_i_i_i_125_c_compstr0_shift_x_q[28:13];

    // redist355_i_shl_i_i_i_i_i_i_125_c_compstr3535_vt_select_28_b_1(DELAY,28583)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist355_i_shl_i_i_i_i_i_i_125_c_compstr3535_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_125_c_compstr3535_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_125_c_compstr3535_vt_join(BITJOIN,9504)@263
    assign i_shl_i_i_i_i_i_i_125_c_compstr3535_vt_join_q = {redist355_i_shl_i_i_i_i_i_i_125_c_compstr3535_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_offset(CONSTANT,31038)
    assign redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_offset_q = $unsigned(8'b00001100);

    // redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_rdcnt(ADD,32487)
    assign redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_a = {1'b0, redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_wraddr_q};
    assign redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_b = {1'b0, redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_o <= $unsigned(redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_a) + $unsigned(redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_b);
        end
    end
    assign redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_q = redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_o[8:0];

    // redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_inputreg0(DELAY,32482)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl);
        end
    end

    // redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_wraddr(COUNTER,32485)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_wraddr_i <= $unsigned(redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_wraddr_q = redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_wraddr_i[7:0];

    // redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem(DUALMEM,32484)
    assign redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_ia = $unsigned(redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_inputreg0_q);
    assign redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_aa = redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_wraddr_q;
    assign redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_ab = redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_aa),
        .data_a(redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_ab),
        .q_b(redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_q = redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_iq[15:0];

    // redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_outputreg0(DELAY,32483)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_outputreg0_q <= $unsigned(redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_mem_q);
        end
    end

    // redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_rdcnt(ADD,31039)
    assign redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_a = {1'b0, redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_wraddr_q};
    assign redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_b = {1'b0, redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_o <= $unsigned(redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_a) + $unsigned(redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_b);
        end
    end
    assign redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_q = redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_o[8:0];

    // redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_inputreg0(DELAY,31034)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl);
        end
    end

    // redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_wraddr(COUNTER,31037)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_wraddr_i <= $unsigned(redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_wraddr_q = redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_wraddr_i[7:0];

    // redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem(DUALMEM,31036)
    assign redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_ia = $unsigned(redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_inputreg0_q);
    assign redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_aa = redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_wraddr_q;
    assign redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_ab = redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_aa),
        .data_a(redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_ab),
        .q_b(redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_q = redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_iq[15:0];

    // redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_outputreg0(DELAY,31035)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_outputreg0_q <= $unsigned(redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_mem_q);
        end
    end

    // redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_rdcnt(ADD,31045)
    assign redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_a = {1'b0, redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_wraddr_q};
    assign redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_b = {1'b0, redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_o <= $unsigned(redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_a) + $unsigned(redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_b);
        end
    end
    assign redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_q = redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_o[8:0];

    // redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_inputreg0(DELAY,31040)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl);
        end
    end

    // redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_wraddr(COUNTER,31043)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_wraddr_i <= $unsigned(redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_wraddr_q = redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_wraddr_i[7:0];

    // redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem(DUALMEM,31042)
    assign redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_ia = $unsigned(redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_inputreg0_q);
    assign redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_aa = redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_wraddr_q;
    assign redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_ab = redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_aa),
        .data_a(redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_ab),
        .q_b(redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_q = redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_iq[15:0];

    // redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_outputreg0(DELAY,31041)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_outputreg0_q <= $unsigned(redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_mem_q);
        end
    end

    // redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_rdcnt(ADD,32481)
    assign redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_a = {1'b0, redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_wraddr_q};
    assign redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_b = {1'b0, redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_o <= $unsigned(redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_a) + $unsigned(redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_b);
        end
    end
    assign redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_q = redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_o[8:0];

    // redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_inputreg0(DELAY,32476)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl);
        end
    end

    // redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_wraddr(COUNTER,32479)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_wraddr_i <= $unsigned(redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_wraddr_q = redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_wraddr_i[7:0];

    // redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem(DUALMEM,32478)
    assign redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_ia = $unsigned(redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_inputreg0_q);
    assign redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_aa = redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_wraddr_q;
    assign redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_ab = redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_aa),
        .data_a(redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_ab),
        .q_b(redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_q = redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_iq[15:0];

    // redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_outputreg0(DELAY,32477)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_outputreg0_q <= $unsigned(redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28088)@257 + 5
    // out q@263
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536(ADD,8549)@263
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod666_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_b = $unsigned({{5{i_shl_i_i_i_i_i_i_125_c_compstr3535_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_125_c_compstr3535_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_o[33:0];

    // rightShiftStage0_uid22719_dupName_501_i_unnamed_c_compstr0_shift_x(MUX,22718)@263
    assign rightShiftStage0_uid22719_dupName_501_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22719_dupName_501_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_q or rightShiftStage0Idx1_uid22717_dupName_501_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22719_dupName_501_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22719_dupName_501_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_q;
            1'b1 : rightShiftStage0_uid22719_dupName_501_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22717_dupName_501_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22719_dupName_501_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22724_dupName_501_i_unnamed_c_compstr0_shift_x(MUX,22723)@263
    assign rightShiftStage1_uid22724_dupName_501_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22724_dupName_501_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22719_dupName_501_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22722_dupName_501_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22724_dupName_501_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22724_dupName_501_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22719_dupName_501_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22724_dupName_501_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22722_dupName_501_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22724_dupName_501_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22729_dupName_501_i_unnamed_c_compstr0_shift_x(MUX,22728)@263
    assign rightShiftStage2_uid22729_dupName_501_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22729_dupName_501_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22724_dupName_501_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22727_dupName_501_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22729_dupName_501_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22729_dupName_501_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22724_dupName_501_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22729_dupName_501_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22727_dupName_501_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22729_dupName_501_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3537_vt_select_20(BITSELECT,12005)@263
    assign i_unnamed_c_compstr3537_vt_select_20_b = rightShiftStage2_uid22729_dupName_501_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3537_vt_join(BITJOIN,12004)@263
    assign i_unnamed_c_compstr3537_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3537_vt_select_20_b};

    // i_conv_i_i_i_i_i_125_c_compstr3538_sel_x(BITSELECT,3740)@263
    assign i_conv_i_i_i_i_i_125_c_compstr3538_sel_x_b = i_unnamed_c_compstr3537_vt_join_q[15:0];

    // redist1125_i_conv_i_i_i_i_i_125_c_compstr3538_sel_x_b_1(DELAY,29353)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1125_i_conv_i_i_i_i_i_125_c_compstr3538_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_125_c_compstr3538_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22738_dupName_502_i_unnamed_c_compstr0_shift_x(BITSELECT,22737)@263
    assign rightShiftStage1Idx1Rng8_uid22738_dupName_502_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22737_dupName_502_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22740_dupName_502_i_unnamed_c_compstr0_shift_x(BITJOIN,22739)@263
    assign rightShiftStage1Idx1_uid22740_dupName_502_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22738_dupName_502_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22733_dupName_502_i_unnamed_c_compstr0_shift_x(BITSELECT,22732)@263
    assign rightShiftStage0Idx1Rng4_uid22733_dupName_502_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_q[33:4];

    // rightShiftStage0Idx1_uid22735_dupName_502_i_unnamed_c_compstr0_shift_x(BITJOIN,22734)@263
    assign rightShiftStage0Idx1_uid22735_dupName_502_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22733_dupName_502_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22737_dupName_502_i_unnamed_c_compstr0_shift_x(MUX,22736)@263
    assign rightShiftStage0_uid22737_dupName_502_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22737_dupName_502_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_q or rightShiftStage0Idx1_uid22735_dupName_502_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22737_dupName_502_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22737_dupName_502_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compstr3536_q;
            1'b1 : rightShiftStage0_uid22737_dupName_502_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22735_dupName_502_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22737_dupName_502_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22742_dupName_502_i_unnamed_c_compstr0_shift_x(MUX,22741)@263
    assign rightShiftStage1_uid22742_dupName_502_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22742_dupName_502_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22737_dupName_502_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22740_dupName_502_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22742_dupName_502_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22742_dupName_502_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22737_dupName_502_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22742_dupName_502_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22740_dupName_502_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22742_dupName_502_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3539_vt_select_21(BITSELECT,12008)@263
    assign i_unnamed_c_compstr3539_vt_select_21_b = rightShiftStage1_uid22742_dupName_502_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3539_vt_join(BITJOIN,12007)@263
    assign i_unnamed_c_compstr3539_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3539_vt_select_21_b};

    // i_unnamed_c_compstr3540_sel_x(BITSELECT,6235)@263
    assign i_unnamed_c_compstr3540_sel_x_b = i_unnamed_c_compstr3539_vt_join_q[15:0];

    // i_unnamed_c_compstr3541_BitSelect_for_a(BITSELECT,27859)@263
    assign i_unnamed_c_compstr3541_BitSelect_for_a_b = i_unnamed_c_compstr3540_sel_x_b[0:0];

    // i_unnamed_c_compstr3541_join(BITJOIN,27860)@263
    assign i_unnamed_c_compstr3541_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3541_BitSelect_for_a_b};

    // i_unnamed_c_compstr3541_vt_select_0(BITSELECT,12013)@263
    assign i_unnamed_c_compstr3541_vt_select_0_b = i_unnamed_c_compstr3541_join_q[0:0];

    // redist56_i_unnamed_c_compstr3541_vt_select_0_b_1(DELAY,28284)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist56_i_unnamed_c_compstr3541_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3541_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3541_vt_join(BITJOIN,12012)@264
    assign i_unnamed_c_compstr3541_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist56_i_unnamed_c_compstr3541_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_125_c_compstr3542(ADD,7007)@264
    assign i_add_i_i_i_i_i_i_125_c_compstr3542_a = {1'b0, i_unnamed_c_compstr3541_vt_join_q};
    assign i_add_i_i_i_i_i_i_125_c_compstr3542_b = {1'b0, redist1125_i_conv_i_i_i_i_i_125_c_compstr3538_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_125_c_compstr3542_o = $unsigned(i_add_i_i_i_i_i_i_125_c_compstr3542_a) + $unsigned(i_add_i_i_i_i_i_i_125_c_compstr3542_b);
    assign i_add_i_i_i_i_i_i_125_c_compstr3542_q = i_add_i_i_i_i_i_i_125_c_compstr3542_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_125_c_compstr3542_sel_x(BITSELECT,2201)@264
    assign bgTrunc_i_add_i_i_i_i_i_i_125_c_compstr3542_sel_x_b = i_add_i_i_i_i_i_i_125_c_compstr3542_q[15:0];

    // i_conv_i_i_i_i_i_i279_126_c_compstr3562_sel_x(BITSELECT,3869)@264
    assign i_conv_i_i_i_i_i_i279_126_c_compstr3562_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_125_c_compstr3542_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_126_c_compstr3562_vt_select_15(BITSELECT,7993)@264
    assign i_conv_i_i_i_i_i_i279_126_c_compstr3562_vt_select_15_b = i_conv_i_i_i_i_i_i279_126_c_compstr3562_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_126_c_compstr3562_vt_join(BITJOIN,7992)@264
    assign i_conv_i_i_i_i_i_i279_126_c_compstr3562_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_126_c_compstr3562_vt_select_15_b};

    // leftShiftStage0_uid25664_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x(MUX,25663)@264
    assign leftShiftStage0_uid25664_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25664_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_126_c_compstr3562_vt_join_q or leftShiftStage0Idx1_uid25662_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25664_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25664_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_126_c_compstr3562_vt_join_q;
            1'b1 : leftShiftStage0_uid25664_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25662_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25664_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25669_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x(MUX,25668)@264
    assign leftShiftStage1_uid25669_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25669_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_s or leftShiftStage0_uid25664_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25667_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25669_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25669_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q = leftShiftStage0_uid25664_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25669_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25667_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25669_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25674_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x(MUX,25673)@264
    assign leftShiftStage2_uid25674_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25674_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_s or leftShiftStage1_uid25669_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25672_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25674_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25674_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q = leftShiftStage1_uid25669_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25674_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25672_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25674_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_126_c_compstr3563_vt_select_28(BITSELECT,9508)@264
    assign i_shl_i_i_i_i_i_i_126_c_compstr3563_vt_select_28_b = leftShiftStage2_uid25674_i_shl_i_i_i_i_i_i_126_c_compstr0_shift_x_q[28:13];

    // redist354_i_shl_i_i_i_i_i_i_126_c_compstr3563_vt_select_28_b_1(DELAY,28582)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist354_i_shl_i_i_i_i_i_i_126_c_compstr3563_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_126_c_compstr3563_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_126_c_compstr3563_vt_join(BITJOIN,9507)@265
    assign i_shl_i_i_i_i_i_i_126_c_compstr3563_vt_join_q = {redist354_i_shl_i_i_i_i_i_i_126_c_compstr3563_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_offset(CONSTANT,31050)
    assign redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_offset_q = $unsigned(8'b00001010);

    // redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_rdcnt(ADD,32499)
    assign redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_a = {1'b0, redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_wraddr_q};
    assign redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_b = {1'b0, redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_o <= $unsigned(redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_a) + $unsigned(redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_b);
        end
    end
    assign redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_q = redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_o[8:0];

    // redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_inputreg0(DELAY,32494)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl);
        end
    end

    // redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_wraddr(COUNTER,32497)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_wraddr_i <= $unsigned(redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_wraddr_q = redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_wraddr_i[7:0];

    // redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem(DUALMEM,32496)
    assign redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_ia = $unsigned(redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_inputreg0_q);
    assign redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_aa = redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_wraddr_q;
    assign redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_ab = redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_aa),
        .data_a(redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_ab),
        .q_b(redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_q = redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_iq[15:0];

    // redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_outputreg0(DELAY,32495)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_outputreg0_q <= $unsigned(redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_mem_q);
        end
    end

    // redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_rdcnt(ADD,31051)
    assign redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_a = {1'b0, redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_wraddr_q};
    assign redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_b = {1'b0, redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_o <= $unsigned(redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_a) + $unsigned(redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_b);
        end
    end
    assign redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_q = redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_o[8:0];

    // redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_inputreg0(DELAY,31046)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl);
        end
    end

    // redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_wraddr(COUNTER,31049)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_wraddr_i <= $unsigned(redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_wraddr_q = redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_wraddr_i[7:0];

    // redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem(DUALMEM,31048)
    assign redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_ia = $unsigned(redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_inputreg0_q);
    assign redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_aa = redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_wraddr_q;
    assign redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_ab = redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_aa),
        .data_a(redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_ab),
        .q_b(redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_q = redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_iq[15:0];

    // redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_outputreg0(DELAY,31047)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_outputreg0_q <= $unsigned(redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_mem_q);
        end
    end

    // redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_rdcnt(ADD,31057)
    assign redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_a = {1'b0, redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_wraddr_q};
    assign redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_b = {1'b0, redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_o <= $unsigned(redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_a) + $unsigned(redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_b);
        end
    end
    assign redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_q = redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_o[8:0];

    // redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_inputreg0(DELAY,31052)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl);
        end
    end

    // redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_wraddr(COUNTER,31055)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_wraddr_i <= $unsigned(redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_wraddr_q = redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_wraddr_i[7:0];

    // redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem(DUALMEM,31054)
    assign redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_ia = $unsigned(redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_inputreg0_q);
    assign redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_aa = redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_wraddr_q;
    assign redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_ab = redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_aa),
        .data_a(redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_ab),
        .q_b(redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_q = redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_iq[15:0];

    // redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_outputreg0(DELAY,31053)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_outputreg0_q <= $unsigned(redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_mem_q);
        end
    end

    // redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_rdcnt(ADD,32493)
    assign redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_a = {1'b0, redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_wraddr_q};
    assign redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_b = {1'b0, redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_o <= $unsigned(redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_a) + $unsigned(redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_b);
        end
    end
    assign redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_q = redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_o[8:0];

    // redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_inputreg0(DELAY,32488)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl);
        end
    end

    // redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_wraddr(COUNTER,32491)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_wraddr_i <= $unsigned(redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_wraddr_q = redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_wraddr_i[7:0];

    // redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem(DUALMEM,32490)
    assign redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_ia = $unsigned(redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_inputreg0_q);
    assign redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_aa = redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_wraddr_q;
    assign redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_ab = redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_aa),
        .data_a(redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_ab),
        .q_b(redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_q = redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_iq[15:0];

    // redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_outputreg0(DELAY,32489)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_outputreg0_q <= $unsigned(redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28090)@259 + 5
    // out q@265
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564(ADD,8550)@265
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod671_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_b = $unsigned({{5{i_shl_i_i_i_i_i_i_126_c_compstr3563_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_126_c_compstr3563_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_o[33:0];

    // rightShiftStage0_uid22781_dupName_505_i_unnamed_c_compstr0_shift_x(MUX,22780)@265
    assign rightShiftStage0_uid22781_dupName_505_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22781_dupName_505_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_q or rightShiftStage0Idx1_uid22779_dupName_505_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22781_dupName_505_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22781_dupName_505_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_q;
            1'b1 : rightShiftStage0_uid22781_dupName_505_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22779_dupName_505_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22781_dupName_505_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22786_dupName_505_i_unnamed_c_compstr0_shift_x(MUX,22785)@265
    assign rightShiftStage1_uid22786_dupName_505_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22786_dupName_505_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22781_dupName_505_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22784_dupName_505_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22786_dupName_505_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22786_dupName_505_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22781_dupName_505_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22786_dupName_505_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22784_dupName_505_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22786_dupName_505_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22791_dupName_505_i_unnamed_c_compstr0_shift_x(MUX,22790)@265
    assign rightShiftStage2_uid22791_dupName_505_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22791_dupName_505_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22786_dupName_505_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22789_dupName_505_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22791_dupName_505_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22791_dupName_505_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22786_dupName_505_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22791_dupName_505_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22789_dupName_505_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22791_dupName_505_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3565_vt_select_20(BITSELECT,12027)@265
    assign i_unnamed_c_compstr3565_vt_select_20_b = rightShiftStage2_uid22791_dupName_505_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3565_vt_join(BITJOIN,12026)@265
    assign i_unnamed_c_compstr3565_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3565_vt_select_20_b};

    // i_conv_i_i_i_i_i_126_c_compstr3566_sel_x(BITSELECT,3741)@265
    assign i_conv_i_i_i_i_i_126_c_compstr3566_sel_x_b = i_unnamed_c_compstr3565_vt_join_q[15:0];

    // redist1124_i_conv_i_i_i_i_i_126_c_compstr3566_sel_x_b_1(DELAY,29352)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1124_i_conv_i_i_i_i_i_126_c_compstr3566_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_126_c_compstr3566_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22800_dupName_506_i_unnamed_c_compstr0_shift_x(BITSELECT,22799)@265
    assign rightShiftStage1Idx1Rng8_uid22800_dupName_506_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22799_dupName_506_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22802_dupName_506_i_unnamed_c_compstr0_shift_x(BITJOIN,22801)@265
    assign rightShiftStage1Idx1_uid22802_dupName_506_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22800_dupName_506_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22795_dupName_506_i_unnamed_c_compstr0_shift_x(BITSELECT,22794)@265
    assign rightShiftStage0Idx1Rng4_uid22795_dupName_506_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_q[33:4];

    // rightShiftStage0Idx1_uid22797_dupName_506_i_unnamed_c_compstr0_shift_x(BITJOIN,22796)@265
    assign rightShiftStage0Idx1_uid22797_dupName_506_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22795_dupName_506_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22799_dupName_506_i_unnamed_c_compstr0_shift_x(MUX,22798)@265
    assign rightShiftStage0_uid22799_dupName_506_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22799_dupName_506_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_q or rightShiftStage0Idx1_uid22797_dupName_506_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22799_dupName_506_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22799_dupName_506_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compstr3564_q;
            1'b1 : rightShiftStage0_uid22799_dupName_506_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22797_dupName_506_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22799_dupName_506_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22804_dupName_506_i_unnamed_c_compstr0_shift_x(MUX,22803)@265
    assign rightShiftStage1_uid22804_dupName_506_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22804_dupName_506_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22799_dupName_506_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22802_dupName_506_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22804_dupName_506_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22804_dupName_506_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22799_dupName_506_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22804_dupName_506_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22802_dupName_506_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22804_dupName_506_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3567_vt_select_21(BITSELECT,12030)@265
    assign i_unnamed_c_compstr3567_vt_select_21_b = rightShiftStage1_uid22804_dupName_506_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3567_vt_join(BITJOIN,12029)@265
    assign i_unnamed_c_compstr3567_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3567_vt_select_21_b};

    // i_unnamed_c_compstr3568_sel_x(BITSELECT,6237)@265
    assign i_unnamed_c_compstr3568_sel_x_b = i_unnamed_c_compstr3567_vt_join_q[15:0];

    // i_unnamed_c_compstr3569_BitSelect_for_a(BITSELECT,27863)@265
    assign i_unnamed_c_compstr3569_BitSelect_for_a_b = i_unnamed_c_compstr3568_sel_x_b[0:0];

    // i_unnamed_c_compstr3569_join(BITJOIN,27864)@265
    assign i_unnamed_c_compstr3569_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3569_BitSelect_for_a_b};

    // i_unnamed_c_compstr3569_vt_select_0(BITSELECT,12035)@265
    assign i_unnamed_c_compstr3569_vt_select_0_b = i_unnamed_c_compstr3569_join_q[0:0];

    // redist54_i_unnamed_c_compstr3569_vt_select_0_b_1(DELAY,28282)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist54_i_unnamed_c_compstr3569_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3569_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3569_vt_join(BITJOIN,12034)@266
    assign i_unnamed_c_compstr3569_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist54_i_unnamed_c_compstr3569_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_126_c_compstr3570(ADD,7008)@266
    assign i_add_i_i_i_i_i_i_126_c_compstr3570_a = {1'b0, i_unnamed_c_compstr3569_vt_join_q};
    assign i_add_i_i_i_i_i_i_126_c_compstr3570_b = {1'b0, redist1124_i_conv_i_i_i_i_i_126_c_compstr3566_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_126_c_compstr3570_o = $unsigned(i_add_i_i_i_i_i_i_126_c_compstr3570_a) + $unsigned(i_add_i_i_i_i_i_i_126_c_compstr3570_b);
    assign i_add_i_i_i_i_i_i_126_c_compstr3570_q = i_add_i_i_i_i_i_i_126_c_compstr3570_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_126_c_compstr3570_sel_x(BITSELECT,2202)@266
    assign bgTrunc_i_add_i_i_i_i_i_i_126_c_compstr3570_sel_x_b = i_add_i_i_i_i_i_i_126_c_compstr3570_q[15:0];

    // i_conv_i_i_i_i_i_i279_127_c_compstr3590_sel_x(BITSELECT,3870)@266
    assign i_conv_i_i_i_i_i_i279_127_c_compstr3590_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_126_c_compstr3570_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i279_127_c_compstr3590_vt_select_15(BITSELECT,7997)@266
    assign i_conv_i_i_i_i_i_i279_127_c_compstr3590_vt_select_15_b = i_conv_i_i_i_i_i_i279_127_c_compstr3590_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i279_127_c_compstr3590_vt_join(BITJOIN,7996)@266
    assign i_conv_i_i_i_i_i_i279_127_c_compstr3590_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i_i279_127_c_compstr3590_vt_select_15_b};

    // leftShiftStage0_uid25682_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x(MUX,25681)@266
    assign leftShiftStage0_uid25682_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25682_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_s or i_conv_i_i_i_i_i_i279_127_c_compstr3590_vt_join_q or leftShiftStage0Idx1_uid25680_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25682_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25682_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q = i_conv_i_i_i_i_i_i279_127_c_compstr3590_vt_join_q;
            1'b1 : leftShiftStage0_uid25682_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25680_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25682_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25687_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x(MUX,25686)@266
    assign leftShiftStage1_uid25687_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25687_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_s or leftShiftStage0_uid25682_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25685_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25687_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25687_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q = leftShiftStage0_uid25682_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25687_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25685_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25687_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25692_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x(MUX,25691)@266
    assign leftShiftStage2_uid25692_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25692_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_s or leftShiftStage1_uid25687_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25690_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25692_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25692_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q = leftShiftStage1_uid25687_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25692_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25690_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25692_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_127_c_compstr3591_vt_select_28(BITSELECT,9511)@266
    assign i_shl_i_i_i_i_i_i_127_c_compstr3591_vt_select_28_b = leftShiftStage2_uid25692_i_shl_i_i_i_i_i_i_127_c_compstr0_shift_x_q[28:13];

    // redist353_i_shl_i_i_i_i_i_i_127_c_compstr3591_vt_select_28_b_1(DELAY,28581)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist353_i_shl_i_i_i_i_i_i_127_c_compstr3591_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_127_c_compstr3591_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_127_c_compstr3591_vt_join(BITJOIN,9510)@267
    assign i_shl_i_i_i_i_i_i_127_c_compstr3591_vt_join_q = {redist353_i_shl_i_i_i_i_i_i_127_c_compstr3591_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_offset(CONSTANT,31062)
    assign redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_offset_q = $unsigned(8'b00001000);

    // redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_rdcnt(ADD,32511)
    assign redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_a = {1'b0, redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_wraddr_q};
    assign redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_b = {1'b0, redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_o <= $unsigned(redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_a) + $unsigned(redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_b);
        end
    end
    assign redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_q = redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_o[8:0];

    // redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_inputreg0(DELAY,32506)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl);
        end
    end

    // redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_wraddr(COUNTER,32509)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_wraddr_i <= $unsigned(redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_wraddr_q = redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_wraddr_i[7:0];

    // redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem(DUALMEM,32508)
    assign redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_ia = $unsigned(redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_inputreg0_q);
    assign redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_aa = redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_wraddr_q;
    assign redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_ab = redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_aa),
        .data_a(redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_ab),
        .q_b(redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_q = redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_iq[15:0];

    // redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_outputreg0(DELAY,32507)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_outputreg0_q <= $unsigned(redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_mem_q);
        end
    end

    // redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_rdcnt(ADD,31063)
    assign redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_a = {1'b0, redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_wraddr_q};
    assign redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_b = {1'b0, redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_o <= $unsigned(redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_a) + $unsigned(redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_b);
        end
    end
    assign redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_q = redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_o[8:0];

    // redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_inputreg0(DELAY,31058)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl);
        end
    end

    // redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_wraddr(COUNTER,31061)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_wraddr_i <= $unsigned(redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_wraddr_q = redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_wraddr_i[7:0];

    // redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem(DUALMEM,31060)
    assign redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_ia = $unsigned(redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_inputreg0_q);
    assign redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_aa = redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_wraddr_q;
    assign redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_ab = redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_aa),
        .data_a(redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_ab),
        .q_b(redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_q = redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_iq[15:0];

    // redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_outputreg0(DELAY,31059)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_outputreg0_q <= $unsigned(redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_mem_q);
        end
    end

    // redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_rdcnt(ADD,31069)
    assign redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_a = {1'b0, redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_wraddr_q};
    assign redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_b = {1'b0, redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_o <= $unsigned(redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_a) + $unsigned(redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_b);
        end
    end
    assign redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_q = redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_o[8:0];

    // redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_inputreg0(DELAY,31064)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl);
        end
    end

    // redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_wraddr(COUNTER,31067)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_wraddr_i <= $unsigned(redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_wraddr_q = redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_wraddr_i[7:0];

    // redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem(DUALMEM,31066)
    assign redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_ia = $unsigned(redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_inputreg0_q);
    assign redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_aa = redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_wraddr_q;
    assign redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_ab = redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_aa),
        .data_a(redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_ab),
        .q_b(redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_q = redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_iq[15:0];

    // redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_outputreg0(DELAY,31065)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_outputreg0_q <= $unsigned(redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_mem_q);
        end
    end

    // redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_rdcnt(ADD,32505)
    assign redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_a = {1'b0, redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_wraddr_q};
    assign redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_b = {1'b0, redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_o <= $unsigned(redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_a) + $unsigned(redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_b);
        end
    end
    assign redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_q = redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_o[8:0];

    // redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_inputreg0(DELAY,32500)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_inputreg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl);
        end
    end

    // redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_wraddr(COUNTER,32503)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_wraddr_i <= $unsigned(redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_wraddr_q = redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_wraddr_i[7:0];

    // redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem(DUALMEM,32502)
    assign redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_ia = $unsigned(redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_inputreg0_q);
    assign redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_aa = redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_wraddr_q;
    assign redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_ab = redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_aa),
        .data_a(redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_ab),
        .q_b(redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_q = redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_iq[15:0];

    // redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_outputreg0(DELAY,32501)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_outputreg0_q <= $unsigned(redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_mem_q);
        end
    end

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28091)@261 + 5
    // out q@267
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_outputreg0_q;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592(ADD,8551)@267
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod676_c_compstr0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_b = $unsigned({{5{i_shl_i_i_i_i_i_i_127_c_compstr3591_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_127_c_compstr3591_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_o[33:0];

    // rightShiftStage0_uid22843_dupName_509_i_unnamed_c_compstr0_shift_x(MUX,22842)@267
    assign rightShiftStage0_uid22843_dupName_509_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22843_dupName_509_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_q or rightShiftStage0Idx1_uid22841_dupName_509_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22843_dupName_509_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22843_dupName_509_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_q;
            1'b1 : rightShiftStage0_uid22843_dupName_509_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22841_dupName_509_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22843_dupName_509_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22848_dupName_509_i_unnamed_c_compstr0_shift_x(MUX,22847)@267
    assign rightShiftStage1_uid22848_dupName_509_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22848_dupName_509_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22843_dupName_509_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22846_dupName_509_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22848_dupName_509_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22848_dupName_509_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22843_dupName_509_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22848_dupName_509_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22846_dupName_509_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22848_dupName_509_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22853_dupName_509_i_unnamed_c_compstr0_shift_x(MUX,22852)@267
    assign rightShiftStage2_uid22853_dupName_509_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22853_dupName_509_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22848_dupName_509_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22851_dupName_509_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22853_dupName_509_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22853_dupName_509_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22848_dupName_509_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22853_dupName_509_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22851_dupName_509_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22853_dupName_509_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3593_vt_select_20(BITSELECT,12052)@267
    assign i_unnamed_c_compstr3593_vt_select_20_b = rightShiftStage2_uid22853_dupName_509_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3593_vt_join(BITJOIN,12051)@267
    assign i_unnamed_c_compstr3593_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3593_vt_select_20_b};

    // i_conv_i_i_i_i_i_127_c_compstr3594_sel_x(BITSELECT,3742)@267
    assign i_conv_i_i_i_i_i_127_c_compstr3594_sel_x_b = i_unnamed_c_compstr3593_vt_join_q[15:0];

    // redist1123_i_conv_i_i_i_i_i_127_c_compstr3594_sel_x_b_1(DELAY,29351)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1123_i_conv_i_i_i_i_i_127_c_compstr3594_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_127_c_compstr3594_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22862_dupName_510_i_unnamed_c_compstr0_shift_x(BITSELECT,22861)@267
    assign rightShiftStage1Idx1Rng8_uid22862_dupName_510_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22861_dupName_510_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22864_dupName_510_i_unnamed_c_compstr0_shift_x(BITJOIN,22863)@267
    assign rightShiftStage1Idx1_uid22864_dupName_510_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22862_dupName_510_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22857_dupName_510_i_unnamed_c_compstr0_shift_x(BITSELECT,22856)@267
    assign rightShiftStage0Idx1Rng4_uid22857_dupName_510_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_q[33:4];

    // rightShiftStage0Idx1_uid22859_dupName_510_i_unnamed_c_compstr0_shift_x(BITJOIN,22858)@267
    assign rightShiftStage0Idx1_uid22859_dupName_510_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22857_dupName_510_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22861_dupName_510_i_unnamed_c_compstr0_shift_x(MUX,22860)@267
    assign rightShiftStage0_uid22861_dupName_510_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22861_dupName_510_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_q or rightShiftStage0Idx1_uid22859_dupName_510_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22861_dupName_510_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22861_dupName_510_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compstr3592_q;
            1'b1 : rightShiftStage0_uid22861_dupName_510_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22859_dupName_510_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22861_dupName_510_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22866_dupName_510_i_unnamed_c_compstr0_shift_x(MUX,22865)@267
    assign rightShiftStage1_uid22866_dupName_510_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22866_dupName_510_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22861_dupName_510_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22864_dupName_510_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22866_dupName_510_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22866_dupName_510_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22861_dupName_510_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22866_dupName_510_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22864_dupName_510_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22866_dupName_510_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3595_vt_select_21(BITSELECT,12055)@267
    assign i_unnamed_c_compstr3595_vt_select_21_b = rightShiftStage1_uid22866_dupName_510_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3595_vt_join(BITJOIN,12054)@267
    assign i_unnamed_c_compstr3595_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3595_vt_select_21_b};

    // i_unnamed_c_compstr3596_sel_x(BITSELECT,6239)@267
    assign i_unnamed_c_compstr3596_sel_x_b = i_unnamed_c_compstr3595_vt_join_q[15:0];

    // i_unnamed_c_compstr3597_BitSelect_for_a(BITSELECT,27867)@267
    assign i_unnamed_c_compstr3597_BitSelect_for_a_b = i_unnamed_c_compstr3596_sel_x_b[0:0];

    // i_unnamed_c_compstr3597_join(BITJOIN,27868)@267
    assign i_unnamed_c_compstr3597_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3597_BitSelect_for_a_b};

    // i_unnamed_c_compstr3597_vt_select_0(BITSELECT,12060)@267
    assign i_unnamed_c_compstr3597_vt_select_0_b = i_unnamed_c_compstr3597_join_q[0:0];

    // redist52_i_unnamed_c_compstr3597_vt_select_0_b_1(DELAY,28280)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist52_i_unnamed_c_compstr3597_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3597_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3597_vt_join(BITJOIN,12059)@268
    assign i_unnamed_c_compstr3597_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist52_i_unnamed_c_compstr3597_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_127_c_compstr3598(ADD,7009)@268
    assign i_add_i_i_i_i_i_i_127_c_compstr3598_a = {1'b0, i_unnamed_c_compstr3597_vt_join_q};
    assign i_add_i_i_i_i_i_i_127_c_compstr3598_b = {1'b0, redist1123_i_conv_i_i_i_i_i_127_c_compstr3594_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_127_c_compstr3598_o = $unsigned(i_add_i_i_i_i_i_i_127_c_compstr3598_a) + $unsigned(i_add_i_i_i_i_i_i_127_c_compstr3598_b);
    assign i_add_i_i_i_i_i_i_127_c_compstr3598_q = i_add_i_i_i_i_i_i_127_c_compstr3598_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_127_c_compstr3598_sel_x(BITSELECT,2203)@268
    assign bgTrunc_i_add_i_i_i_i_i_i_127_c_compstr3598_sel_x_b = i_add_i_i_i_i_i_i_127_c_compstr3598_q[15:0];

    // rightShiftStage2Idx1Rng8_uid22818_dupName_507_i_unnamed_c_compstr0_shift_x(BITSELECT,22817)@267
    assign rightShiftStage2Idx1Rng8_uid22818_dupName_507_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22817_dupName_507_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22820_dupName_507_i_unnamed_c_compstr0_shift_x(BITJOIN,22819)@267
    assign rightShiftStage2Idx1_uid22820_dupName_507_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22818_dupName_507_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22813_dupName_507_i_unnamed_c_compstr0_shift_x(BITSELECT,22812)@267
    assign rightShiftStage1Idx1Rng4_uid22813_dupName_507_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22812_dupName_507_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22815_dupName_507_i_unnamed_c_compstr0_shift_x(BITJOIN,22814)@267
    assign rightShiftStage1Idx1_uid22815_dupName_507_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22813_dupName_507_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22808_dupName_507_i_unnamed_c_compstr0_shift_x(BITSELECT,22807)@267
    assign rightShiftStage0Idx1Rng1_uid22808_dupName_507_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_q[33:1];

    // rightShiftStage0Idx1_uid22810_dupName_507_i_unnamed_c_compstr0_shift_x(BITJOIN,22809)@267
    assign rightShiftStage0Idx1_uid22810_dupName_507_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22808_dupName_507_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23403_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x(BITSELECT,23402)@266
    assign leftShiftStage2Idx1Rng8_uid23403_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_in = leftShiftStage1_uid23401_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23403_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23403_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23404_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x(BITJOIN,23403)@266
    assign leftShiftStage2Idx1_uid23404_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23403_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23398_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x(BITSELECT,23397)@266
    assign leftShiftStage1Idx1Rng4_uid23398_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_in = leftShiftStage0_uid23396_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23398_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23398_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23399_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x(BITJOIN,23398)@266
    assign leftShiftStage1Idx1_uid23399_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23398_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23393_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x(BITSELECT,23392)@266
    assign leftShiftStage0Idx1Rng1_uid23393_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_127_c_compstr3574_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23393_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23393_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23394_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x(BITJOIN,23393)@266
    assign leftShiftStage0Idx1_uid23394_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23393_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22756_dupName_503_i_unnamed_c_compstr0_shift_x(BITSELECT,22755)@265
    assign rightShiftStage2Idx1Rng8_uid22756_dupName_503_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22755_dupName_503_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22758_dupName_503_i_unnamed_c_compstr0_shift_x(BITJOIN,22757)@265
    assign rightShiftStage2Idx1_uid22758_dupName_503_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22756_dupName_503_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22751_dupName_503_i_unnamed_c_compstr0_shift_x(BITSELECT,22750)@265
    assign rightShiftStage1Idx1Rng4_uid22751_dupName_503_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22750_dupName_503_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22753_dupName_503_i_unnamed_c_compstr0_shift_x(BITJOIN,22752)@265
    assign rightShiftStage1Idx1_uid22753_dupName_503_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22751_dupName_503_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22746_dupName_503_i_unnamed_c_compstr0_shift_x(BITSELECT,22745)@265
    assign rightShiftStage0Idx1Rng1_uid22746_dupName_503_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_q[33:1];

    // rightShiftStage0Idx1_uid22748_dupName_503_i_unnamed_c_compstr0_shift_x(BITJOIN,22747)@265
    assign rightShiftStage0Idx1_uid22748_dupName_503_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22746_dupName_503_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23385_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x(BITSELECT,23384)@264
    assign leftShiftStage2Idx1Rng8_uid23385_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_in = leftShiftStage1_uid23383_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23385_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23385_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23386_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x(BITJOIN,23385)@264
    assign leftShiftStage2Idx1_uid23386_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23385_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23380_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x(BITSELECT,23379)@264
    assign leftShiftStage1Idx1Rng4_uid23380_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_in = leftShiftStage0_uid23378_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23380_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23380_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23381_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x(BITJOIN,23380)@264
    assign leftShiftStage1Idx1_uid23381_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23380_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23375_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x(BITSELECT,23374)@264
    assign leftShiftStage0Idx1Rng1_uid23375_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_126_c_compstr3546_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23375_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23375_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23376_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x(BITJOIN,23375)@264
    assign leftShiftStage0Idx1_uid23376_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23375_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22694_dupName_499_i_unnamed_c_compstr0_shift_x(BITSELECT,22693)@263
    assign rightShiftStage2Idx1Rng8_uid22694_dupName_499_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22693_dupName_499_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22696_dupName_499_i_unnamed_c_compstr0_shift_x(BITJOIN,22695)@263
    assign rightShiftStage2Idx1_uid22696_dupName_499_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22694_dupName_499_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22689_dupName_499_i_unnamed_c_compstr0_shift_x(BITSELECT,22688)@263
    assign rightShiftStage1Idx1Rng4_uid22689_dupName_499_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22688_dupName_499_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22691_dupName_499_i_unnamed_c_compstr0_shift_x(BITJOIN,22690)@263
    assign rightShiftStage1Idx1_uid22691_dupName_499_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22689_dupName_499_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22684_dupName_499_i_unnamed_c_compstr0_shift_x(BITSELECT,22683)@263
    assign rightShiftStage0Idx1Rng1_uid22684_dupName_499_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_q[33:1];

    // rightShiftStage0Idx1_uid22686_dupName_499_i_unnamed_c_compstr0_shift_x(BITJOIN,22685)@263
    assign rightShiftStage0Idx1_uid22686_dupName_499_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22684_dupName_499_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23367_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x(BITSELECT,23366)@262
    assign leftShiftStage2Idx1Rng8_uid23367_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_in = leftShiftStage1_uid23365_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23367_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23367_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23368_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x(BITJOIN,23367)@262
    assign leftShiftStage2Idx1_uid23368_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23367_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23362_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x(BITSELECT,23361)@262
    assign leftShiftStage1Idx1Rng4_uid23362_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_in = leftShiftStage0_uid23360_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23362_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23362_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23363_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x(BITJOIN,23362)@262
    assign leftShiftStage1Idx1_uid23363_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23362_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23357_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x(BITSELECT,23356)@262
    assign leftShiftStage0Idx1Rng1_uid23357_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_125_c_compstr3518_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23357_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23357_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23358_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x(BITJOIN,23357)@262
    assign leftShiftStage0Idx1_uid23358_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23357_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22632_dupName_495_i_unnamed_c_compstr0_shift_x(BITSELECT,22631)@261
    assign rightShiftStage2Idx1Rng8_uid22632_dupName_495_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22631_dupName_495_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22634_dupName_495_i_unnamed_c_compstr0_shift_x(BITJOIN,22633)@261
    assign rightShiftStage2Idx1_uid22634_dupName_495_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22632_dupName_495_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22627_dupName_495_i_unnamed_c_compstr0_shift_x(BITSELECT,22626)@261
    assign rightShiftStage1Idx1Rng4_uid22627_dupName_495_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22626_dupName_495_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22629_dupName_495_i_unnamed_c_compstr0_shift_x(BITJOIN,22628)@261
    assign rightShiftStage1Idx1_uid22629_dupName_495_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22627_dupName_495_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22622_dupName_495_i_unnamed_c_compstr0_shift_x(BITSELECT,22621)@261
    assign rightShiftStage0Idx1Rng1_uid22622_dupName_495_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_q[33:1];

    // rightShiftStage0Idx1_uid22624_dupName_495_i_unnamed_c_compstr0_shift_x(BITJOIN,22623)@261
    assign rightShiftStage0Idx1_uid22624_dupName_495_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22622_dupName_495_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23349_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x(BITSELECT,23348)@260
    assign leftShiftStage2Idx1Rng8_uid23349_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_in = leftShiftStage1_uid23347_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23349_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23349_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23350_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x(BITJOIN,23349)@260
    assign leftShiftStage2Idx1_uid23350_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23349_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23344_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x(BITSELECT,23343)@260
    assign leftShiftStage1Idx1Rng4_uid23344_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_in = leftShiftStage0_uid23342_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23344_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23344_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23345_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x(BITJOIN,23344)@260
    assign leftShiftStage1Idx1_uid23345_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23344_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23339_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x(BITSELECT,23338)@260
    assign leftShiftStage0Idx1Rng1_uid23339_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_124_c_compstr3490_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23339_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23339_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23340_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x(BITJOIN,23339)@260
    assign leftShiftStage0Idx1_uid23340_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23339_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22570_dupName_491_i_unnamed_c_compstr0_shift_x(BITSELECT,22569)@259
    assign rightShiftStage2Idx1Rng8_uid22570_dupName_491_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22569_dupName_491_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22572_dupName_491_i_unnamed_c_compstr0_shift_x(BITJOIN,22571)@259
    assign rightShiftStage2Idx1_uid22572_dupName_491_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22570_dupName_491_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22565_dupName_491_i_unnamed_c_compstr0_shift_x(BITSELECT,22564)@259
    assign rightShiftStage1Idx1Rng4_uid22565_dupName_491_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22564_dupName_491_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22567_dupName_491_i_unnamed_c_compstr0_shift_x(BITJOIN,22566)@259
    assign rightShiftStage1Idx1_uid22567_dupName_491_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22565_dupName_491_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22560_dupName_491_i_unnamed_c_compstr0_shift_x(BITSELECT,22559)@259
    assign rightShiftStage0Idx1Rng1_uid22560_dupName_491_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_q[33:1];

    // rightShiftStage0Idx1_uid22562_dupName_491_i_unnamed_c_compstr0_shift_x(BITJOIN,22561)@259
    assign rightShiftStage0Idx1_uid22562_dupName_491_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22560_dupName_491_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23331_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x(BITSELECT,23330)@258
    assign leftShiftStage2Idx1Rng8_uid23331_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_in = leftShiftStage1_uid23329_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23331_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23331_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23332_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x(BITJOIN,23331)@258
    assign leftShiftStage2Idx1_uid23332_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23331_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23326_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x(BITSELECT,23325)@258
    assign leftShiftStage1Idx1Rng4_uid23326_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_in = leftShiftStage0_uid23324_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23326_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23326_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23327_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x(BITJOIN,23326)@258
    assign leftShiftStage1Idx1_uid23327_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23326_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23321_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x(BITSELECT,23320)@258
    assign leftShiftStage0Idx1Rng1_uid23321_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_123_c_compstr3462_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23321_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23321_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23322_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x(BITJOIN,23321)@258
    assign leftShiftStage0Idx1_uid23322_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23321_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22508_dupName_487_i_unnamed_c_compstr0_shift_x(BITSELECT,22507)@257
    assign rightShiftStage2Idx1Rng8_uid22508_dupName_487_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22507_dupName_487_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22510_dupName_487_i_unnamed_c_compstr0_shift_x(BITJOIN,22509)@257
    assign rightShiftStage2Idx1_uid22510_dupName_487_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22508_dupName_487_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22503_dupName_487_i_unnamed_c_compstr0_shift_x(BITSELECT,22502)@257
    assign rightShiftStage1Idx1Rng4_uid22503_dupName_487_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22502_dupName_487_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22505_dupName_487_i_unnamed_c_compstr0_shift_x(BITJOIN,22504)@257
    assign rightShiftStage1Idx1_uid22505_dupName_487_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22503_dupName_487_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22498_dupName_487_i_unnamed_c_compstr0_shift_x(BITSELECT,22497)@257
    assign rightShiftStage0Idx1Rng1_uid22498_dupName_487_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_q[33:1];

    // rightShiftStage0Idx1_uid22500_dupName_487_i_unnamed_c_compstr0_shift_x(BITJOIN,22499)@257
    assign rightShiftStage0Idx1_uid22500_dupName_487_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22498_dupName_487_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23313_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x(BITSELECT,23312)@256
    assign leftShiftStage2Idx1Rng8_uid23313_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_in = leftShiftStage1_uid23311_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23313_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23313_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23314_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x(BITJOIN,23313)@256
    assign leftShiftStage2Idx1_uid23314_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23313_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23308_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x(BITSELECT,23307)@256
    assign leftShiftStage1Idx1Rng4_uid23308_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_in = leftShiftStage0_uid23306_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23308_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23308_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23309_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x(BITJOIN,23308)@256
    assign leftShiftStage1Idx1_uid23309_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23308_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23303_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x(BITSELECT,23302)@256
    assign leftShiftStage0Idx1Rng1_uid23303_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_122_c_compstr3434_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23303_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23303_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23304_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x(BITJOIN,23303)@256
    assign leftShiftStage0Idx1_uid23304_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23303_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22446_dupName_483_i_unnamed_c_compstr0_shift_x(BITSELECT,22445)@255
    assign rightShiftStage2Idx1Rng8_uid22446_dupName_483_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22445_dupName_483_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22448_dupName_483_i_unnamed_c_compstr0_shift_x(BITJOIN,22447)@255
    assign rightShiftStage2Idx1_uid22448_dupName_483_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22446_dupName_483_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22441_dupName_483_i_unnamed_c_compstr0_shift_x(BITSELECT,22440)@255
    assign rightShiftStage1Idx1Rng4_uid22441_dupName_483_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22440_dupName_483_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22443_dupName_483_i_unnamed_c_compstr0_shift_x(BITJOIN,22442)@255
    assign rightShiftStage1Idx1_uid22443_dupName_483_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22441_dupName_483_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22436_dupName_483_i_unnamed_c_compstr0_shift_x(BITSELECT,22435)@255
    assign rightShiftStage0Idx1Rng1_uid22436_dupName_483_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_q[33:1];

    // rightShiftStage0Idx1_uid22438_dupName_483_i_unnamed_c_compstr0_shift_x(BITJOIN,22437)@255
    assign rightShiftStage0Idx1_uid22438_dupName_483_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22436_dupName_483_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23295_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x(BITSELECT,23294)@254
    assign leftShiftStage2Idx1Rng8_uid23295_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_in = leftShiftStage1_uid23293_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23295_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23295_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23296_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x(BITJOIN,23295)@254
    assign leftShiftStage2Idx1_uid23296_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23295_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23290_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x(BITSELECT,23289)@254
    assign leftShiftStage1Idx1Rng4_uid23290_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_in = leftShiftStage0_uid23288_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23290_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23290_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23291_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x(BITJOIN,23290)@254
    assign leftShiftStage1Idx1_uid23291_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23290_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23285_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x(BITSELECT,23284)@254
    assign leftShiftStage0Idx1Rng1_uid23285_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_121_c_compstr3406_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23285_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23285_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23286_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x(BITJOIN,23285)@254
    assign leftShiftStage0Idx1_uid23286_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23285_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22384_dupName_479_i_unnamed_c_compstr0_shift_x(BITSELECT,22383)@253
    assign rightShiftStage2Idx1Rng8_uid22384_dupName_479_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22383_dupName_479_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22386_dupName_479_i_unnamed_c_compstr0_shift_x(BITJOIN,22385)@253
    assign rightShiftStage2Idx1_uid22386_dupName_479_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22384_dupName_479_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22379_dupName_479_i_unnamed_c_compstr0_shift_x(BITSELECT,22378)@253
    assign rightShiftStage1Idx1Rng4_uid22379_dupName_479_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22378_dupName_479_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22381_dupName_479_i_unnamed_c_compstr0_shift_x(BITJOIN,22380)@253
    assign rightShiftStage1Idx1_uid22381_dupName_479_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22379_dupName_479_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22374_dupName_479_i_unnamed_c_compstr0_shift_x(BITSELECT,22373)@253
    assign rightShiftStage0Idx1Rng1_uid22374_dupName_479_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_q[33:1];

    // rightShiftStage0Idx1_uid22376_dupName_479_i_unnamed_c_compstr0_shift_x(BITJOIN,22375)@253
    assign rightShiftStage0Idx1_uid22376_dupName_479_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22374_dupName_479_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23277_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x(BITSELECT,23276)@252
    assign leftShiftStage2Idx1Rng8_uid23277_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_in = leftShiftStage1_uid23275_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23277_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23277_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23278_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x(BITJOIN,23277)@252
    assign leftShiftStage2Idx1_uid23278_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23277_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23272_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x(BITSELECT,23271)@252
    assign leftShiftStage1Idx1Rng4_uid23272_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_in = leftShiftStage0_uid23270_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23272_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23272_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23273_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x(BITJOIN,23272)@252
    assign leftShiftStage1Idx1_uid23273_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23272_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23267_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x(BITSELECT,23266)@252
    assign leftShiftStage0Idx1Rng1_uid23267_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_120_c_compstr3378_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23267_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23267_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23268_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x(BITJOIN,23267)@252
    assign leftShiftStage0Idx1_uid23268_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23267_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22322_dupName_475_i_unnamed_c_compstr0_shift_x(BITSELECT,22321)@251
    assign rightShiftStage2Idx1Rng8_uid22322_dupName_475_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22321_dupName_475_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22324_dupName_475_i_unnamed_c_compstr0_shift_x(BITJOIN,22323)@251
    assign rightShiftStage2Idx1_uid22324_dupName_475_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22322_dupName_475_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22317_dupName_475_i_unnamed_c_compstr0_shift_x(BITSELECT,22316)@251
    assign rightShiftStage1Idx1Rng4_uid22317_dupName_475_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22316_dupName_475_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22319_dupName_475_i_unnamed_c_compstr0_shift_x(BITJOIN,22318)@251
    assign rightShiftStage1Idx1_uid22319_dupName_475_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22317_dupName_475_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22312_dupName_475_i_unnamed_c_compstr0_shift_x(BITSELECT,22311)@251
    assign rightShiftStage0Idx1Rng1_uid22312_dupName_475_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_q[33:1];

    // rightShiftStage0Idx1_uid22314_dupName_475_i_unnamed_c_compstr0_shift_x(BITJOIN,22313)@251
    assign rightShiftStage0Idx1_uid22314_dupName_475_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22312_dupName_475_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23241_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x(BITSELECT,23240)@250
    assign leftShiftStage2Idx1Rng8_uid23241_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_in = leftShiftStage1_uid23239_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23241_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23241_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23242_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x(BITJOIN,23241)@250
    assign leftShiftStage2Idx1_uid23242_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23241_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23236_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x(BITSELECT,23235)@250
    assign leftShiftStage1Idx1Rng4_uid23236_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_in = leftShiftStage0_uid23234_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23236_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23236_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23237_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x(BITJOIN,23236)@250
    assign leftShiftStage1Idx1_uid23237_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23236_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23231_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x(BITSELECT,23230)@250
    assign leftShiftStage0Idx1Rng1_uid23231_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_119_c_compstr3350_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23231_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23231_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23232_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x(BITJOIN,23231)@250
    assign leftShiftStage0Idx1_uid23232_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23231_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22260_dupName_471_i_unnamed_c_compstr0_shift_x(BITSELECT,22259)@249
    assign rightShiftStage2Idx1Rng8_uid22260_dupName_471_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22259_dupName_471_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22262_dupName_471_i_unnamed_c_compstr0_shift_x(BITJOIN,22261)@249
    assign rightShiftStage2Idx1_uid22262_dupName_471_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22260_dupName_471_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22255_dupName_471_i_unnamed_c_compstr0_shift_x(BITSELECT,22254)@249
    assign rightShiftStage1Idx1Rng4_uid22255_dupName_471_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22254_dupName_471_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22257_dupName_471_i_unnamed_c_compstr0_shift_x(BITJOIN,22256)@249
    assign rightShiftStage1Idx1_uid22257_dupName_471_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22255_dupName_471_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22250_dupName_471_i_unnamed_c_compstr0_shift_x(BITSELECT,22249)@249
    assign rightShiftStage0Idx1Rng1_uid22250_dupName_471_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_q[33:1];

    // rightShiftStage0Idx1_uid22252_dupName_471_i_unnamed_c_compstr0_shift_x(BITJOIN,22251)@249
    assign rightShiftStage0Idx1_uid22252_dupName_471_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22250_dupName_471_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23223_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x(BITSELECT,23222)@248
    assign leftShiftStage2Idx1Rng8_uid23223_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_in = leftShiftStage1_uid23221_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23223_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23223_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23224_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x(BITJOIN,23223)@248
    assign leftShiftStage2Idx1_uid23224_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23223_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23218_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x(BITSELECT,23217)@248
    assign leftShiftStage1Idx1Rng4_uid23218_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_in = leftShiftStage0_uid23216_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23218_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23218_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23219_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x(BITJOIN,23218)@248
    assign leftShiftStage1Idx1_uid23219_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23218_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23213_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x(BITSELECT,23212)@248
    assign leftShiftStage0Idx1Rng1_uid23213_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_118_c_compstr3322_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23213_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23213_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23214_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x(BITJOIN,23213)@248
    assign leftShiftStage0Idx1_uid23214_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23213_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22198_dupName_467_i_unnamed_c_compstr0_shift_x(BITSELECT,22197)@247
    assign rightShiftStage2Idx1Rng8_uid22198_dupName_467_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22197_dupName_467_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22200_dupName_467_i_unnamed_c_compstr0_shift_x(BITJOIN,22199)@247
    assign rightShiftStage2Idx1_uid22200_dupName_467_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22198_dupName_467_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22193_dupName_467_i_unnamed_c_compstr0_shift_x(BITSELECT,22192)@247
    assign rightShiftStage1Idx1Rng4_uid22193_dupName_467_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22192_dupName_467_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22195_dupName_467_i_unnamed_c_compstr0_shift_x(BITJOIN,22194)@247
    assign rightShiftStage1Idx1_uid22195_dupName_467_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22193_dupName_467_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22188_dupName_467_i_unnamed_c_compstr0_shift_x(BITSELECT,22187)@247
    assign rightShiftStage0Idx1Rng1_uid22188_dupName_467_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_q[33:1];

    // rightShiftStage0Idx1_uid22190_dupName_467_i_unnamed_c_compstr0_shift_x(BITJOIN,22189)@247
    assign rightShiftStage0Idx1_uid22190_dupName_467_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22188_dupName_467_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23205_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x(BITSELECT,23204)@246
    assign leftShiftStage2Idx1Rng8_uid23205_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_in = leftShiftStage1_uid23203_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23205_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23205_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23206_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x(BITJOIN,23205)@246
    assign leftShiftStage2Idx1_uid23206_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23205_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23200_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x(BITSELECT,23199)@246
    assign leftShiftStage1Idx1Rng4_uid23200_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_in = leftShiftStage0_uid23198_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23200_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23200_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23201_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x(BITJOIN,23200)@246
    assign leftShiftStage1Idx1_uid23201_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23200_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23195_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x(BITSELECT,23194)@246
    assign leftShiftStage0Idx1Rng1_uid23195_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_117_c_compstr3294_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23195_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23195_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23196_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x(BITJOIN,23195)@246
    assign leftShiftStage0Idx1_uid23196_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23195_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22136_dupName_463_i_unnamed_c_compstr0_shift_x(BITSELECT,22135)@245
    assign rightShiftStage2Idx1Rng8_uid22136_dupName_463_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22135_dupName_463_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22138_dupName_463_i_unnamed_c_compstr0_shift_x(BITJOIN,22137)@245
    assign rightShiftStage2Idx1_uid22138_dupName_463_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22136_dupName_463_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22131_dupName_463_i_unnamed_c_compstr0_shift_x(BITSELECT,22130)@245
    assign rightShiftStage1Idx1Rng4_uid22131_dupName_463_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22130_dupName_463_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22133_dupName_463_i_unnamed_c_compstr0_shift_x(BITJOIN,22132)@245
    assign rightShiftStage1Idx1_uid22133_dupName_463_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22131_dupName_463_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22126_dupName_463_i_unnamed_c_compstr0_shift_x(BITSELECT,22125)@245
    assign rightShiftStage0Idx1Rng1_uid22126_dupName_463_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_q[33:1];

    // rightShiftStage0Idx1_uid22128_dupName_463_i_unnamed_c_compstr0_shift_x(BITJOIN,22127)@245
    assign rightShiftStage0Idx1_uid22128_dupName_463_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22126_dupName_463_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23187_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x(BITSELECT,23186)@244
    assign leftShiftStage2Idx1Rng8_uid23187_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_in = leftShiftStage1_uid23185_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23187_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23187_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23188_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x(BITJOIN,23187)@244
    assign leftShiftStage2Idx1_uid23188_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23187_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23182_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x(BITSELECT,23181)@244
    assign leftShiftStage1Idx1Rng4_uid23182_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_in = leftShiftStage0_uid23180_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23182_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23182_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23183_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x(BITJOIN,23182)@244
    assign leftShiftStage1Idx1_uid23183_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23182_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23177_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x(BITSELECT,23176)@244
    assign leftShiftStage0Idx1Rng1_uid23177_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_116_c_compstr3266_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23177_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23177_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23178_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x(BITJOIN,23177)@244
    assign leftShiftStage0Idx1_uid23178_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23177_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22074_dupName_459_i_unnamed_c_compstr0_shift_x(BITSELECT,22073)@243
    assign rightShiftStage2Idx1Rng8_uid22074_dupName_459_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22073_dupName_459_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22076_dupName_459_i_unnamed_c_compstr0_shift_x(BITJOIN,22075)@243
    assign rightShiftStage2Idx1_uid22076_dupName_459_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22074_dupName_459_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22069_dupName_459_i_unnamed_c_compstr0_shift_x(BITSELECT,22068)@243
    assign rightShiftStage1Idx1Rng4_uid22069_dupName_459_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22068_dupName_459_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22071_dupName_459_i_unnamed_c_compstr0_shift_x(BITJOIN,22070)@243
    assign rightShiftStage1Idx1_uid22071_dupName_459_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22069_dupName_459_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22064_dupName_459_i_unnamed_c_compstr0_shift_x(BITSELECT,22063)@243
    assign rightShiftStage0Idx1Rng1_uid22064_dupName_459_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_q[33:1];

    // rightShiftStage0Idx1_uid22066_dupName_459_i_unnamed_c_compstr0_shift_x(BITJOIN,22065)@243
    assign rightShiftStage0Idx1_uid22066_dupName_459_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22064_dupName_459_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23169_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x(BITSELECT,23168)@242
    assign leftShiftStage2Idx1Rng8_uid23169_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_in = leftShiftStage1_uid23167_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23169_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23169_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23170_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x(BITJOIN,23169)@242
    assign leftShiftStage2Idx1_uid23170_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23169_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23164_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x(BITSELECT,23163)@242
    assign leftShiftStage1Idx1Rng4_uid23164_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_in = leftShiftStage0_uid23162_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23164_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23164_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23165_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x(BITJOIN,23164)@242
    assign leftShiftStage1Idx1_uid23165_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23164_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23159_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x(BITSELECT,23158)@242
    assign leftShiftStage0Idx1Rng1_uid23159_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_115_c_compstr3238_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23159_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23159_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23160_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x(BITJOIN,23159)@242
    assign leftShiftStage0Idx1_uid23160_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23159_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22012_dupName_455_i_unnamed_c_compstr0_shift_x(BITSELECT,22011)@241
    assign rightShiftStage2Idx1Rng8_uid22012_dupName_455_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid22011_dupName_455_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22014_dupName_455_i_unnamed_c_compstr0_shift_x(BITJOIN,22013)@241
    assign rightShiftStage2Idx1_uid22014_dupName_455_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid22012_dupName_455_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22007_dupName_455_i_unnamed_c_compstr0_shift_x(BITSELECT,22006)@241
    assign rightShiftStage1Idx1Rng4_uid22007_dupName_455_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22006_dupName_455_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22009_dupName_455_i_unnamed_c_compstr0_shift_x(BITJOIN,22008)@241
    assign rightShiftStage1Idx1_uid22009_dupName_455_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid22007_dupName_455_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22002_dupName_455_i_unnamed_c_compstr0_shift_x(BITSELECT,22001)@241
    assign rightShiftStage0Idx1Rng1_uid22002_dupName_455_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_q[33:1];

    // rightShiftStage0Idx1_uid22004_dupName_455_i_unnamed_c_compstr0_shift_x(BITJOIN,22003)@241
    assign rightShiftStage0Idx1_uid22004_dupName_455_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22002_dupName_455_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23151_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x(BITSELECT,23150)@240
    assign leftShiftStage2Idx1Rng8_uid23151_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_in = leftShiftStage1_uid23149_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23151_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23151_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23152_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x(BITJOIN,23151)@240
    assign leftShiftStage2Idx1_uid23152_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23151_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23146_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x(BITSELECT,23145)@240
    assign leftShiftStage1Idx1Rng4_uid23146_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_in = leftShiftStage0_uid23144_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23146_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23146_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23147_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x(BITJOIN,23146)@240
    assign leftShiftStage1Idx1_uid23147_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23146_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23141_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x(BITSELECT,23140)@240
    assign leftShiftStage0Idx1Rng1_uid23141_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_114_c_compstr3210_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23141_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23141_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23142_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x(BITJOIN,23141)@240
    assign leftShiftStage0Idx1_uid23142_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23141_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21950_dupName_451_i_unnamed_c_compstr0_shift_x(BITSELECT,21949)@239
    assign rightShiftStage2Idx1Rng8_uid21950_dupName_451_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21949_dupName_451_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21952_dupName_451_i_unnamed_c_compstr0_shift_x(BITJOIN,21951)@239
    assign rightShiftStage2Idx1_uid21952_dupName_451_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21950_dupName_451_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21945_dupName_451_i_unnamed_c_compstr0_shift_x(BITSELECT,21944)@239
    assign rightShiftStage1Idx1Rng4_uid21945_dupName_451_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21944_dupName_451_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21947_dupName_451_i_unnamed_c_compstr0_shift_x(BITJOIN,21946)@239
    assign rightShiftStage1Idx1_uid21947_dupName_451_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21945_dupName_451_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21940_dupName_451_i_unnamed_c_compstr0_shift_x(BITSELECT,21939)@239
    assign rightShiftStage0Idx1Rng1_uid21940_dupName_451_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_q[33:1];

    // rightShiftStage0Idx1_uid21942_dupName_451_i_unnamed_c_compstr0_shift_x(BITJOIN,21941)@239
    assign rightShiftStage0Idx1_uid21942_dupName_451_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21940_dupName_451_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23133_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x(BITSELECT,23132)@238
    assign leftShiftStage2Idx1Rng8_uid23133_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_in = leftShiftStage1_uid23131_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23133_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23133_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23134_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x(BITJOIN,23133)@238
    assign leftShiftStage2Idx1_uid23134_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23133_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23128_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x(BITSELECT,23127)@238
    assign leftShiftStage1Idx1Rng4_uid23128_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_in = leftShiftStage0_uid23126_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23128_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23128_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23129_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x(BITJOIN,23128)@238
    assign leftShiftStage1Idx1_uid23129_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23128_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23123_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x(BITSELECT,23122)@238
    assign leftShiftStage0Idx1Rng1_uid23123_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_113_c_compstr3182_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23123_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23123_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23124_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x(BITJOIN,23123)@238
    assign leftShiftStage0Idx1_uid23124_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23123_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21888_dupName_447_i_unnamed_c_compstr0_shift_x(BITSELECT,21887)@237
    assign rightShiftStage2Idx1Rng8_uid21888_dupName_447_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21887_dupName_447_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21890_dupName_447_i_unnamed_c_compstr0_shift_x(BITJOIN,21889)@237
    assign rightShiftStage2Idx1_uid21890_dupName_447_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21888_dupName_447_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21883_dupName_447_i_unnamed_c_compstr0_shift_x(BITSELECT,21882)@237
    assign rightShiftStage1Idx1Rng4_uid21883_dupName_447_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21882_dupName_447_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21885_dupName_447_i_unnamed_c_compstr0_shift_x(BITJOIN,21884)@237
    assign rightShiftStage1Idx1_uid21885_dupName_447_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21883_dupName_447_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21878_dupName_447_i_unnamed_c_compstr0_shift_x(BITSELECT,21877)@237
    assign rightShiftStage0Idx1Rng1_uid21878_dupName_447_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_q[33:1];

    // rightShiftStage0Idx1_uid21880_dupName_447_i_unnamed_c_compstr0_shift_x(BITJOIN,21879)@237
    assign rightShiftStage0Idx1_uid21880_dupName_447_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21878_dupName_447_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23115_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x(BITSELECT,23114)@236
    assign leftShiftStage2Idx1Rng8_uid23115_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_in = leftShiftStage1_uid23113_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23115_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23115_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23116_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x(BITJOIN,23115)@236
    assign leftShiftStage2Idx1_uid23116_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23115_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23110_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x(BITSELECT,23109)@236
    assign leftShiftStage1Idx1Rng4_uid23110_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_in = leftShiftStage0_uid23108_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23110_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23110_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23111_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x(BITJOIN,23110)@236
    assign leftShiftStage1Idx1_uid23111_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23110_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23105_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x(BITSELECT,23104)@236
    assign leftShiftStage0Idx1Rng1_uid23105_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_112_c_compstr3154_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23105_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23105_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23106_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x(BITJOIN,23105)@236
    assign leftShiftStage0Idx1_uid23106_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23105_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21826_dupName_443_i_unnamed_c_compstr0_shift_x(BITSELECT,21825)@235
    assign rightShiftStage2Idx1Rng8_uid21826_dupName_443_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21825_dupName_443_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21828_dupName_443_i_unnamed_c_compstr0_shift_x(BITJOIN,21827)@235
    assign rightShiftStage2Idx1_uid21828_dupName_443_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21826_dupName_443_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21821_dupName_443_i_unnamed_c_compstr0_shift_x(BITSELECT,21820)@235
    assign rightShiftStage1Idx1Rng4_uid21821_dupName_443_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21820_dupName_443_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21823_dupName_443_i_unnamed_c_compstr0_shift_x(BITJOIN,21822)@235
    assign rightShiftStage1Idx1_uid21823_dupName_443_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21821_dupName_443_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21816_dupName_443_i_unnamed_c_compstr0_shift_x(BITSELECT,21815)@235
    assign rightShiftStage0Idx1Rng1_uid21816_dupName_443_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_q[33:1];

    // rightShiftStage0Idx1_uid21818_dupName_443_i_unnamed_c_compstr0_shift_x(BITJOIN,21817)@235
    assign rightShiftStage0Idx1_uid21818_dupName_443_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21816_dupName_443_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23097_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x(BITSELECT,23096)@234
    assign leftShiftStage2Idx1Rng8_uid23097_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_in = leftShiftStage1_uid23095_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23097_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23097_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23098_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x(BITJOIN,23097)@234
    assign leftShiftStage2Idx1_uid23098_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23097_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23092_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x(BITSELECT,23091)@234
    assign leftShiftStage1Idx1Rng4_uid23092_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_in = leftShiftStage0_uid23090_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23092_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23092_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23093_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x(BITJOIN,23092)@234
    assign leftShiftStage1Idx1_uid23093_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23092_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23087_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x(BITSELECT,23086)@234
    assign leftShiftStage0Idx1Rng1_uid23087_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_111_c_compstr3126_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23087_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23087_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23088_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x(BITJOIN,23087)@234
    assign leftShiftStage0Idx1_uid23088_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23087_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21764_dupName_439_i_unnamed_c_compstr0_shift_x(BITSELECT,21763)@233
    assign rightShiftStage2Idx1Rng8_uid21764_dupName_439_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21763_dupName_439_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21766_dupName_439_i_unnamed_c_compstr0_shift_x(BITJOIN,21765)@233
    assign rightShiftStage2Idx1_uid21766_dupName_439_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21764_dupName_439_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21759_dupName_439_i_unnamed_c_compstr0_shift_x(BITSELECT,21758)@233
    assign rightShiftStage1Idx1Rng4_uid21759_dupName_439_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21758_dupName_439_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21761_dupName_439_i_unnamed_c_compstr0_shift_x(BITJOIN,21760)@233
    assign rightShiftStage1Idx1_uid21761_dupName_439_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21759_dupName_439_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21754_dupName_439_i_unnamed_c_compstr0_shift_x(BITSELECT,21753)@233
    assign rightShiftStage0Idx1Rng1_uid21754_dupName_439_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_q[33:1];

    // rightShiftStage0Idx1_uid21756_dupName_439_i_unnamed_c_compstr0_shift_x(BITJOIN,21755)@233
    assign rightShiftStage0Idx1_uid21756_dupName_439_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21754_dupName_439_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23079_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x(BITSELECT,23078)@232
    assign leftShiftStage2Idx1Rng8_uid23079_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_in = leftShiftStage1_uid23077_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23079_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23079_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23080_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x(BITJOIN,23079)@232
    assign leftShiftStage2Idx1_uid23080_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23079_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23074_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x(BITSELECT,23073)@232
    assign leftShiftStage1Idx1Rng4_uid23074_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_in = leftShiftStage0_uid23072_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23074_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23074_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23075_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x(BITJOIN,23074)@232
    assign leftShiftStage1Idx1_uid23075_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23074_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23069_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x(BITSELECT,23068)@232
    assign leftShiftStage0Idx1Rng1_uid23069_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_110_c_compstr3098_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23069_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23069_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23070_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x(BITJOIN,23069)@232
    assign leftShiftStage0Idx1_uid23070_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23069_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21702_dupName_435_i_unnamed_c_compstr0_shift_x(BITSELECT,21701)@231
    assign rightShiftStage2Idx1Rng8_uid21702_dupName_435_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21701_dupName_435_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21704_dupName_435_i_unnamed_c_compstr0_shift_x(BITJOIN,21703)@231
    assign rightShiftStage2Idx1_uid21704_dupName_435_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21702_dupName_435_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21697_dupName_435_i_unnamed_c_compstr0_shift_x(BITSELECT,21696)@231
    assign rightShiftStage1Idx1Rng4_uid21697_dupName_435_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21696_dupName_435_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21699_dupName_435_i_unnamed_c_compstr0_shift_x(BITJOIN,21698)@231
    assign rightShiftStage1Idx1_uid21699_dupName_435_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21697_dupName_435_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21692_dupName_435_i_unnamed_c_compstr0_shift_x(BITSELECT,21691)@231
    assign rightShiftStage0Idx1Rng1_uid21692_dupName_435_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_q[33:1];

    // rightShiftStage0Idx1_uid21694_dupName_435_i_unnamed_c_compstr0_shift_x(BITJOIN,21693)@231
    assign rightShiftStage0Idx1_uid21694_dupName_435_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21692_dupName_435_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23043_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x(BITSELECT,23042)@230
    assign leftShiftStage2Idx1Rng8_uid23043_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_in = leftShiftStage1_uid23041_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23043_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23043_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23044_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x(BITJOIN,23043)@230
    assign leftShiftStage2Idx1_uid23044_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23043_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23038_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x(BITSELECT,23037)@230
    assign leftShiftStage1Idx1Rng4_uid23038_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_in = leftShiftStage0_uid23036_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23038_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23038_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23039_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x(BITJOIN,23038)@230
    assign leftShiftStage1Idx1_uid23039_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23038_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23033_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x(BITSELECT,23032)@230
    assign leftShiftStage0Idx1Rng1_uid23033_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_109_c_compstr3070_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23033_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23033_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23034_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x(BITJOIN,23033)@230
    assign leftShiftStage0Idx1_uid23034_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23033_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21640_dupName_431_i_unnamed_c_compstr0_shift_x(BITSELECT,21639)@229
    assign rightShiftStage2Idx1Rng8_uid21640_dupName_431_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21639_dupName_431_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21642_dupName_431_i_unnamed_c_compstr0_shift_x(BITJOIN,21641)@229
    assign rightShiftStage2Idx1_uid21642_dupName_431_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21640_dupName_431_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21635_dupName_431_i_unnamed_c_compstr0_shift_x(BITSELECT,21634)@229
    assign rightShiftStage1Idx1Rng4_uid21635_dupName_431_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21634_dupName_431_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21637_dupName_431_i_unnamed_c_compstr0_shift_x(BITJOIN,21636)@229
    assign rightShiftStage1Idx1_uid21637_dupName_431_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21635_dupName_431_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21630_dupName_431_i_unnamed_c_compstr0_shift_x(BITSELECT,21629)@229
    assign rightShiftStage0Idx1Rng1_uid21630_dupName_431_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_q[33:1];

    // rightShiftStage0Idx1_uid21632_dupName_431_i_unnamed_c_compstr0_shift_x(BITJOIN,21631)@229
    assign rightShiftStage0Idx1_uid21632_dupName_431_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21630_dupName_431_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23025_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x(BITSELECT,23024)@228
    assign leftShiftStage2Idx1Rng8_uid23025_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_in = leftShiftStage1_uid23023_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23025_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23025_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23026_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x(BITJOIN,23025)@228
    assign leftShiftStage2Idx1_uid23026_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23025_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23020_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x(BITSELECT,23019)@228
    assign leftShiftStage1Idx1Rng4_uid23020_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_in = leftShiftStage0_uid23018_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23020_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23020_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23021_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x(BITJOIN,23020)@228
    assign leftShiftStage1Idx1_uid23021_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23020_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23015_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x(BITSELECT,23014)@228
    assign leftShiftStage0Idx1Rng1_uid23015_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_108_c_compstr3042_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23015_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23015_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23016_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x(BITJOIN,23015)@228
    assign leftShiftStage0Idx1_uid23016_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23015_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21578_dupName_427_i_unnamed_c_compstr0_shift_x(BITSELECT,21577)@227
    assign rightShiftStage2Idx1Rng8_uid21578_dupName_427_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21577_dupName_427_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21580_dupName_427_i_unnamed_c_compstr0_shift_x(BITJOIN,21579)@227
    assign rightShiftStage2Idx1_uid21580_dupName_427_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21578_dupName_427_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21573_dupName_427_i_unnamed_c_compstr0_shift_x(BITSELECT,21572)@227
    assign rightShiftStage1Idx1Rng4_uid21573_dupName_427_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21572_dupName_427_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21575_dupName_427_i_unnamed_c_compstr0_shift_x(BITJOIN,21574)@227
    assign rightShiftStage1Idx1_uid21575_dupName_427_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21573_dupName_427_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21568_dupName_427_i_unnamed_c_compstr0_shift_x(BITSELECT,21567)@227
    assign rightShiftStage0Idx1Rng1_uid21568_dupName_427_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_q[33:1];

    // rightShiftStage0Idx1_uid21570_dupName_427_i_unnamed_c_compstr0_shift_x(BITJOIN,21569)@227
    assign rightShiftStage0Idx1_uid21570_dupName_427_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21568_dupName_427_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23007_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x(BITSELECT,23006)@226
    assign leftShiftStage2Idx1Rng8_uid23007_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_in = leftShiftStage1_uid23005_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23007_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23007_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23008_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x(BITJOIN,23007)@226
    assign leftShiftStage2Idx1_uid23008_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23007_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23002_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x(BITSELECT,23001)@226
    assign leftShiftStage1Idx1Rng4_uid23002_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_in = leftShiftStage0_uid23000_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23002_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23002_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23003_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x(BITJOIN,23002)@226
    assign leftShiftStage1Idx1_uid23003_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23002_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid22997_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x(BITSELECT,22996)@226
    assign leftShiftStage0Idx1Rng1_uid22997_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_107_c_compstr3014_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid22997_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid22997_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid22998_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x(BITJOIN,22997)@226
    assign leftShiftStage0Idx1_uid22998_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid22997_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21516_dupName_423_i_unnamed_c_compstr0_shift_x(BITSELECT,21515)@225
    assign rightShiftStage2Idx1Rng8_uid21516_dupName_423_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21515_dupName_423_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21518_dupName_423_i_unnamed_c_compstr0_shift_x(BITJOIN,21517)@225
    assign rightShiftStage2Idx1_uid21518_dupName_423_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21516_dupName_423_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21511_dupName_423_i_unnamed_c_compstr0_shift_x(BITSELECT,21510)@225
    assign rightShiftStage1Idx1Rng4_uid21511_dupName_423_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21510_dupName_423_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21513_dupName_423_i_unnamed_c_compstr0_shift_x(BITJOIN,21512)@225
    assign rightShiftStage1Idx1_uid21513_dupName_423_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21511_dupName_423_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21506_dupName_423_i_unnamed_c_compstr0_shift_x(BITSELECT,21505)@225
    assign rightShiftStage0Idx1Rng1_uid21506_dupName_423_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_q[33:1];

    // rightShiftStage0Idx1_uid21508_dupName_423_i_unnamed_c_compstr0_shift_x(BITJOIN,21507)@225
    assign rightShiftStage0Idx1_uid21508_dupName_423_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21506_dupName_423_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid22989_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x(BITSELECT,22988)@224
    assign leftShiftStage2Idx1Rng8_uid22989_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_in = leftShiftStage1_uid22987_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid22989_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid22989_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid22990_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x(BITJOIN,22989)@224
    assign leftShiftStage2Idx1_uid22990_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid22989_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid22984_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x(BITSELECT,22983)@224
    assign leftShiftStage1Idx1Rng4_uid22984_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_in = leftShiftStage0_uid22982_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid22984_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid22984_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid22985_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x(BITJOIN,22984)@224
    assign leftShiftStage1Idx1_uid22985_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid22984_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid22979_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x(BITSELECT,22978)@224
    assign leftShiftStage0Idx1Rng1_uid22979_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_106_c_compstr2986_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid22979_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid22979_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid22980_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x(BITJOIN,22979)@224
    assign leftShiftStage0Idx1_uid22980_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid22979_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21454_dupName_419_i_unnamed_c_compstr0_shift_x(BITSELECT,21453)@223
    assign rightShiftStage2Idx1Rng8_uid21454_dupName_419_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21453_dupName_419_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21456_dupName_419_i_unnamed_c_compstr0_shift_x(BITJOIN,21455)@223
    assign rightShiftStage2Idx1_uid21456_dupName_419_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21454_dupName_419_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21449_dupName_419_i_unnamed_c_compstr0_shift_x(BITSELECT,21448)@223
    assign rightShiftStage1Idx1Rng4_uid21449_dupName_419_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21448_dupName_419_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21451_dupName_419_i_unnamed_c_compstr0_shift_x(BITJOIN,21450)@223
    assign rightShiftStage1Idx1_uid21451_dupName_419_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21449_dupName_419_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21444_dupName_419_i_unnamed_c_compstr0_shift_x(BITSELECT,21443)@223
    assign rightShiftStage0Idx1Rng1_uid21444_dupName_419_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_q[33:1];

    // rightShiftStage0Idx1_uid21446_dupName_419_i_unnamed_c_compstr0_shift_x(BITJOIN,21445)@223
    assign rightShiftStage0Idx1_uid21446_dupName_419_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21444_dupName_419_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid22971_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x(BITSELECT,22970)@222
    assign leftShiftStage2Idx1Rng8_uid22971_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_in = leftShiftStage1_uid22969_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid22971_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid22971_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid22972_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x(BITJOIN,22971)@222
    assign leftShiftStage2Idx1_uid22972_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid22971_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid22966_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x(BITSELECT,22965)@222
    assign leftShiftStage1Idx1Rng4_uid22966_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_in = leftShiftStage0_uid22964_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid22966_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid22966_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid22967_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x(BITJOIN,22966)@222
    assign leftShiftStage1Idx1_uid22967_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid22966_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid22961_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x(BITSELECT,22960)@222
    assign leftShiftStage0Idx1Rng1_uid22961_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_105_c_compstr2958_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid22961_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid22961_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid22962_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x(BITJOIN,22961)@222
    assign leftShiftStage0Idx1_uid22962_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid22961_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21392_dupName_415_i_unnamed_c_compstr0_shift_x(BITSELECT,21391)@221
    assign rightShiftStage2Idx1Rng8_uid21392_dupName_415_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21391_dupName_415_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21394_dupName_415_i_unnamed_c_compstr0_shift_x(BITJOIN,21393)@221
    assign rightShiftStage2Idx1_uid21394_dupName_415_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21392_dupName_415_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21387_dupName_415_i_unnamed_c_compstr0_shift_x(BITSELECT,21386)@221
    assign rightShiftStage1Idx1Rng4_uid21387_dupName_415_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21386_dupName_415_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21389_dupName_415_i_unnamed_c_compstr0_shift_x(BITJOIN,21388)@221
    assign rightShiftStage1Idx1_uid21389_dupName_415_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21387_dupName_415_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21382_dupName_415_i_unnamed_c_compstr0_shift_x(BITSELECT,21381)@221
    assign rightShiftStage0Idx1Rng1_uid21382_dupName_415_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_q[33:1];

    // rightShiftStage0Idx1_uid21384_dupName_415_i_unnamed_c_compstr0_shift_x(BITJOIN,21383)@221
    assign rightShiftStage0Idx1_uid21384_dupName_415_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21382_dupName_415_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid22953_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x(BITSELECT,22952)@220
    assign leftShiftStage2Idx1Rng8_uid22953_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_in = leftShiftStage1_uid22951_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid22953_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid22953_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid22954_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x(BITJOIN,22953)@220
    assign leftShiftStage2Idx1_uid22954_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid22953_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid22948_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x(BITSELECT,22947)@220
    assign leftShiftStage1Idx1Rng4_uid22948_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_in = leftShiftStage0_uid22946_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid22948_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid22948_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid22949_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x(BITJOIN,22948)@220
    assign leftShiftStage1Idx1_uid22949_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid22948_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid22943_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x(BITSELECT,22942)@220
    assign leftShiftStage0Idx1Rng1_uid22943_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_104_c_compstr2930_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid22943_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid22943_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid22944_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x(BITJOIN,22943)@220
    assign leftShiftStage0Idx1_uid22944_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid22943_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21330_dupName_411_i_unnamed_c_compstr0_shift_x(BITSELECT,21329)@219
    assign rightShiftStage2Idx1Rng8_uid21330_dupName_411_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21329_dupName_411_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21332_dupName_411_i_unnamed_c_compstr0_shift_x(BITJOIN,21331)@219
    assign rightShiftStage2Idx1_uid21332_dupName_411_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21330_dupName_411_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21325_dupName_411_i_unnamed_c_compstr0_shift_x(BITSELECT,21324)@219
    assign rightShiftStage1Idx1Rng4_uid21325_dupName_411_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21324_dupName_411_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21327_dupName_411_i_unnamed_c_compstr0_shift_x(BITJOIN,21326)@219
    assign rightShiftStage1Idx1_uid21327_dupName_411_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21325_dupName_411_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21320_dupName_411_i_unnamed_c_compstr0_shift_x(BITSELECT,21319)@219
    assign rightShiftStage0Idx1Rng1_uid21320_dupName_411_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_q[33:1];

    // rightShiftStage0Idx1_uid21322_dupName_411_i_unnamed_c_compstr0_shift_x(BITJOIN,21321)@219
    assign rightShiftStage0Idx1_uid21322_dupName_411_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21320_dupName_411_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid22935_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x(BITSELECT,22934)@218
    assign leftShiftStage2Idx1Rng8_uid22935_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_in = leftShiftStage1_uid22933_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid22935_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid22935_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid22936_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x(BITJOIN,22935)@218
    assign leftShiftStage2Idx1_uid22936_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid22935_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid22930_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x(BITSELECT,22929)@218
    assign leftShiftStage1Idx1Rng4_uid22930_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_in = leftShiftStage0_uid22928_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid22930_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid22930_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid22931_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x(BITJOIN,22930)@218
    assign leftShiftStage1Idx1_uid22931_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid22930_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid22925_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x(BITSELECT,22924)@218
    assign leftShiftStage0Idx1Rng1_uid22925_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_103_c_compstr2902_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid22925_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid22925_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid22926_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x(BITJOIN,22925)@218
    assign leftShiftStage0Idx1_uid22926_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid22925_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21268_dupName_407_i_unnamed_c_compstr0_shift_x(BITSELECT,21267)@217
    assign rightShiftStage2Idx1Rng8_uid21268_dupName_407_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21267_dupName_407_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21270_dupName_407_i_unnamed_c_compstr0_shift_x(BITJOIN,21269)@217
    assign rightShiftStage2Idx1_uid21270_dupName_407_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21268_dupName_407_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21263_dupName_407_i_unnamed_c_compstr0_shift_x(BITSELECT,21262)@217
    assign rightShiftStage1Idx1Rng4_uid21263_dupName_407_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21262_dupName_407_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21265_dupName_407_i_unnamed_c_compstr0_shift_x(BITJOIN,21264)@217
    assign rightShiftStage1Idx1_uid21265_dupName_407_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21263_dupName_407_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21258_dupName_407_i_unnamed_c_compstr0_shift_x(BITSELECT,21257)@217
    assign rightShiftStage0Idx1Rng1_uid21258_dupName_407_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_q[33:1];

    // rightShiftStage0Idx1_uid21260_dupName_407_i_unnamed_c_compstr0_shift_x(BITJOIN,21259)@217
    assign rightShiftStage0Idx1_uid21260_dupName_407_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21258_dupName_407_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid22917_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x(BITSELECT,22916)@216
    assign leftShiftStage2Idx1Rng8_uid22917_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_in = leftShiftStage1_uid22915_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid22917_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid22917_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid22918_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x(BITJOIN,22917)@216
    assign leftShiftStage2Idx1_uid22918_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid22917_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid22912_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x(BITSELECT,22911)@216
    assign leftShiftStage1Idx1Rng4_uid22912_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_in = leftShiftStage0_uid22910_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid22912_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid22912_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid22913_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x(BITJOIN,22912)@216
    assign leftShiftStage1Idx1_uid22913_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid22912_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid22907_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x(BITSELECT,22906)@216
    assign leftShiftStage0Idx1Rng1_uid22907_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_102_c_compstr2874_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid22907_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid22907_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid22908_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x(BITJOIN,22907)@216
    assign leftShiftStage0Idx1_uid22908_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid22907_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21206_dupName_403_i_unnamed_c_compstr0_shift_x(BITSELECT,21205)@215
    assign rightShiftStage2Idx1Rng8_uid21206_dupName_403_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21205_dupName_403_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21208_dupName_403_i_unnamed_c_compstr0_shift_x(BITJOIN,21207)@215
    assign rightShiftStage2Idx1_uid21208_dupName_403_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21206_dupName_403_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21201_dupName_403_i_unnamed_c_compstr0_shift_x(BITSELECT,21200)@215
    assign rightShiftStage1Idx1Rng4_uid21201_dupName_403_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21200_dupName_403_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21203_dupName_403_i_unnamed_c_compstr0_shift_x(BITJOIN,21202)@215
    assign rightShiftStage1Idx1_uid21203_dupName_403_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21201_dupName_403_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21196_dupName_403_i_unnamed_c_compstr0_shift_x(BITSELECT,21195)@215
    assign rightShiftStage0Idx1Rng1_uid21196_dupName_403_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_q[33:1];

    // rightShiftStage0Idx1_uid21198_dupName_403_i_unnamed_c_compstr0_shift_x(BITJOIN,21197)@215
    assign rightShiftStage0Idx1_uid21198_dupName_403_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21196_dupName_403_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid22899_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x(BITSELECT,22898)@214
    assign leftShiftStage2Idx1Rng8_uid22899_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_in = leftShiftStage1_uid22897_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid22899_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid22899_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid22900_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x(BITJOIN,22899)@214
    assign leftShiftStage2Idx1_uid22900_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid22899_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid22894_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x(BITSELECT,22893)@214
    assign leftShiftStage1Idx1Rng4_uid22894_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_in = leftShiftStage0_uid22892_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid22894_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid22894_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid22895_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x(BITJOIN,22894)@214
    assign leftShiftStage1Idx1_uid22895_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid22894_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid22889_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x(BITSELECT,22888)@214
    assign leftShiftStage0Idx1Rng1_uid22889_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_101_c_compstr2846_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid22889_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid22889_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid22890_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x(BITJOIN,22889)@214
    assign leftShiftStage0Idx1_uid22890_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid22889_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21144_dupName_399_i_unnamed_c_compstr0_shift_x(BITSELECT,21143)@213
    assign rightShiftStage2Idx1Rng8_uid21144_dupName_399_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21143_dupName_399_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21146_dupName_399_i_unnamed_c_compstr0_shift_x(BITJOIN,21145)@213
    assign rightShiftStage2Idx1_uid21146_dupName_399_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21144_dupName_399_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21139_dupName_399_i_unnamed_c_compstr0_shift_x(BITSELECT,21138)@213
    assign rightShiftStage1Idx1Rng4_uid21139_dupName_399_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21138_dupName_399_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21141_dupName_399_i_unnamed_c_compstr0_shift_x(BITJOIN,21140)@213
    assign rightShiftStage1Idx1_uid21141_dupName_399_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21139_dupName_399_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21134_dupName_399_i_unnamed_c_compstr0_shift_x(BITSELECT,21133)@213
    assign rightShiftStage0Idx1Rng1_uid21134_dupName_399_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_q[33:1];

    // rightShiftStage0Idx1_uid21136_dupName_399_i_unnamed_c_compstr0_shift_x(BITJOIN,21135)@213
    assign rightShiftStage0Idx1_uid21136_dupName_399_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21134_dupName_399_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid22881_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x(BITSELECT,22880)@212
    assign leftShiftStage2Idx1Rng8_uid22881_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_in = leftShiftStage1_uid22879_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid22881_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid22881_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid22882_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x(BITJOIN,22881)@212
    assign leftShiftStage2Idx1_uid22882_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid22881_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid22876_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x(BITSELECT,22875)@212
    assign leftShiftStage1Idx1Rng4_uid22876_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_in = leftShiftStage0_uid22874_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid22876_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid22876_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid22877_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x(BITJOIN,22876)@212
    assign leftShiftStage1Idx1_uid22877_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid22876_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid22871_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x(BITSELECT,22870)@212
    assign leftShiftStage0Idx1Rng1_uid22871_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid22871_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid22871_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid22872_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x(BITJOIN,22871)@212
    assign leftShiftStage0Idx1_uid22872_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid22871_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21082_dupName_395_i_unnamed_c_compstr0_shift_x(BITSELECT,21081)@211
    assign rightShiftStage2Idx1Rng8_uid21082_dupName_395_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21081_dupName_395_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21084_dupName_395_i_unnamed_c_compstr0_shift_x(BITJOIN,21083)@211
    assign rightShiftStage2Idx1_uid21084_dupName_395_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21082_dupName_395_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21077_dupName_395_i_unnamed_c_compstr0_shift_x(BITSELECT,21076)@211
    assign rightShiftStage1Idx1Rng4_uid21077_dupName_395_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21076_dupName_395_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21079_dupName_395_i_unnamed_c_compstr0_shift_x(BITJOIN,21078)@211
    assign rightShiftStage1Idx1_uid21079_dupName_395_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21077_dupName_395_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21072_dupName_395_i_unnamed_c_compstr0_shift_x(BITSELECT,21071)@211
    assign rightShiftStage0Idx1Rng1_uid21072_dupName_395_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_q[33:1];

    // rightShiftStage0Idx1_uid21074_dupName_395_i_unnamed_c_compstr0_shift_x(BITJOIN,21073)@211
    assign rightShiftStage0Idx1_uid21074_dupName_395_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21072_dupName_395_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25131_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x(BITSELECT,25130)@210
    assign leftShiftStage2Idx1Rng8_uid25131_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_in = leftShiftStage1_uid25129_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25131_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25131_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25132_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x(BITJOIN,25131)@210
    assign leftShiftStage2Idx1_uid25132_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25131_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25126_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x(BITSELECT,25125)@210
    assign leftShiftStage1Idx1Rng4_uid25126_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_in = leftShiftStage0_uid25124_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25126_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25126_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25127_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x(BITJOIN,25126)@210
    assign leftShiftStage1Idx1_uid25127_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25126_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25121_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x(BITSELECT,25120)@210
    assign leftShiftStage0Idx1Rng1_uid25121_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_99_c_compstr2790_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25121_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25121_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25122_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x(BITJOIN,25121)@210
    assign leftShiftStage0Idx1_uid25122_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25121_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21020_dupName_391_i_unnamed_c_compstr0_shift_x(BITSELECT,21019)@209
    assign rightShiftStage2Idx1Rng8_uid21020_dupName_391_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid21019_dupName_391_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21022_dupName_391_i_unnamed_c_compstr0_shift_x(BITJOIN,21021)@209
    assign rightShiftStage2Idx1_uid21022_dupName_391_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid21020_dupName_391_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21015_dupName_391_i_unnamed_c_compstr0_shift_x(BITSELECT,21014)@209
    assign rightShiftStage1Idx1Rng4_uid21015_dupName_391_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21014_dupName_391_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21017_dupName_391_i_unnamed_c_compstr0_shift_x(BITJOIN,21016)@209
    assign rightShiftStage1Idx1_uid21017_dupName_391_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid21015_dupName_391_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21010_dupName_391_i_unnamed_c_compstr0_shift_x(BITSELECT,21009)@209
    assign rightShiftStage0Idx1Rng1_uid21010_dupName_391_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_q[33:1];

    // rightShiftStage0Idx1_uid21012_dupName_391_i_unnamed_c_compstr0_shift_x(BITJOIN,21011)@209
    assign rightShiftStage0Idx1_uid21012_dupName_391_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21010_dupName_391_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25113_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x(BITSELECT,25112)@208
    assign leftShiftStage2Idx1Rng8_uid25113_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_in = leftShiftStage1_uid25111_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25113_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25113_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25114_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x(BITJOIN,25113)@208
    assign leftShiftStage2Idx1_uid25114_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25113_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25108_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x(BITSELECT,25107)@208
    assign leftShiftStage1Idx1Rng4_uid25108_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_in = leftShiftStage0_uid25106_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25108_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25108_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25109_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x(BITJOIN,25108)@208
    assign leftShiftStage1Idx1_uid25109_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25108_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25103_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x(BITSELECT,25102)@208
    assign leftShiftStage0Idx1Rng1_uid25103_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_98_c_compstr2762_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25103_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25103_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25104_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x(BITJOIN,25103)@208
    assign leftShiftStage0Idx1_uid25104_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25103_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20958_dupName_387_i_unnamed_c_compstr0_shift_x(BITSELECT,20957)@207
    assign rightShiftStage2Idx1Rng8_uid20958_dupName_387_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20957_dupName_387_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20960_dupName_387_i_unnamed_c_compstr0_shift_x(BITJOIN,20959)@207
    assign rightShiftStage2Idx1_uid20960_dupName_387_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20958_dupName_387_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20953_dupName_387_i_unnamed_c_compstr0_shift_x(BITSELECT,20952)@207
    assign rightShiftStage1Idx1Rng4_uid20953_dupName_387_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20952_dupName_387_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20955_dupName_387_i_unnamed_c_compstr0_shift_x(BITJOIN,20954)@207
    assign rightShiftStage1Idx1_uid20955_dupName_387_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20953_dupName_387_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20948_dupName_387_i_unnamed_c_compstr0_shift_x(BITSELECT,20947)@207
    assign rightShiftStage0Idx1Rng1_uid20948_dupName_387_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_q[33:1];

    // rightShiftStage0Idx1_uid20950_dupName_387_i_unnamed_c_compstr0_shift_x(BITJOIN,20949)@207
    assign rightShiftStage0Idx1_uid20950_dupName_387_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20948_dupName_387_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25095_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x(BITSELECT,25094)@206
    assign leftShiftStage2Idx1Rng8_uid25095_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_in = leftShiftStage1_uid25093_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25095_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25095_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25096_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x(BITJOIN,25095)@206
    assign leftShiftStage2Idx1_uid25096_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25095_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25090_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x(BITSELECT,25089)@206
    assign leftShiftStage1Idx1Rng4_uid25090_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_in = leftShiftStage0_uid25088_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25090_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25090_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25091_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x(BITJOIN,25090)@206
    assign leftShiftStage1Idx1_uid25091_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25090_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25085_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x(BITSELECT,25084)@206
    assign leftShiftStage0Idx1Rng1_uid25085_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_97_c_compstr2734_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25085_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25085_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25086_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x(BITJOIN,25085)@206
    assign leftShiftStage0Idx1_uid25086_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25085_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20896_dupName_383_i_unnamed_c_compstr0_shift_x(BITSELECT,20895)@205
    assign rightShiftStage2Idx1Rng8_uid20896_dupName_383_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20895_dupName_383_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20898_dupName_383_i_unnamed_c_compstr0_shift_x(BITJOIN,20897)@205
    assign rightShiftStage2Idx1_uid20898_dupName_383_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20896_dupName_383_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20891_dupName_383_i_unnamed_c_compstr0_shift_x(BITSELECT,20890)@205
    assign rightShiftStage1Idx1Rng4_uid20891_dupName_383_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20890_dupName_383_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20893_dupName_383_i_unnamed_c_compstr0_shift_x(BITJOIN,20892)@205
    assign rightShiftStage1Idx1_uid20893_dupName_383_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20891_dupName_383_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20886_dupName_383_i_unnamed_c_compstr0_shift_x(BITSELECT,20885)@205
    assign rightShiftStage0Idx1Rng1_uid20886_dupName_383_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_q[33:1];

    // rightShiftStage0Idx1_uid20888_dupName_383_i_unnamed_c_compstr0_shift_x(BITJOIN,20887)@205
    assign rightShiftStage0Idx1_uid20888_dupName_383_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20886_dupName_383_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25077_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x(BITSELECT,25076)@204
    assign leftShiftStage2Idx1Rng8_uid25077_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_in = leftShiftStage1_uid25075_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25077_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25077_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25078_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x(BITJOIN,25077)@204
    assign leftShiftStage2Idx1_uid25078_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25077_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25072_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x(BITSELECT,25071)@204
    assign leftShiftStage1Idx1Rng4_uid25072_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_in = leftShiftStage0_uid25070_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25072_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25072_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25073_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x(BITJOIN,25072)@204
    assign leftShiftStage1Idx1_uid25073_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25072_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25067_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x(BITSELECT,25066)@204
    assign leftShiftStage0Idx1Rng1_uid25067_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_96_c_compstr2706_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25067_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25067_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25068_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x(BITJOIN,25067)@204
    assign leftShiftStage0Idx1_uid25068_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25067_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20834_dupName_379_i_unnamed_c_compstr0_shift_x(BITSELECT,20833)@203
    assign rightShiftStage2Idx1Rng8_uid20834_dupName_379_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20833_dupName_379_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20836_dupName_379_i_unnamed_c_compstr0_shift_x(BITJOIN,20835)@203
    assign rightShiftStage2Idx1_uid20836_dupName_379_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20834_dupName_379_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20829_dupName_379_i_unnamed_c_compstr0_shift_x(BITSELECT,20828)@203
    assign rightShiftStage1Idx1Rng4_uid20829_dupName_379_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20828_dupName_379_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20831_dupName_379_i_unnamed_c_compstr0_shift_x(BITJOIN,20830)@203
    assign rightShiftStage1Idx1_uid20831_dupName_379_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20829_dupName_379_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20824_dupName_379_i_unnamed_c_compstr0_shift_x(BITSELECT,20823)@203
    assign rightShiftStage0Idx1Rng1_uid20824_dupName_379_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_q[33:1];

    // rightShiftStage0Idx1_uid20826_dupName_379_i_unnamed_c_compstr0_shift_x(BITJOIN,20825)@203
    assign rightShiftStage0Idx1_uid20826_dupName_379_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20824_dupName_379_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25059_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x(BITSELECT,25058)@202
    assign leftShiftStage2Idx1Rng8_uid25059_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_in = leftShiftStage1_uid25057_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25059_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25059_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25060_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x(BITJOIN,25059)@202
    assign leftShiftStage2Idx1_uid25060_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25059_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25054_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x(BITSELECT,25053)@202
    assign leftShiftStage1Idx1Rng4_uid25054_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_in = leftShiftStage0_uid25052_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25054_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25054_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25055_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x(BITJOIN,25054)@202
    assign leftShiftStage1Idx1_uid25055_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25054_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25049_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x(BITSELECT,25048)@202
    assign leftShiftStage0Idx1Rng1_uid25049_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_95_c_compstr2678_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25049_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25049_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25050_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x(BITJOIN,25049)@202
    assign leftShiftStage0Idx1_uid25050_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25049_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20772_dupName_375_i_unnamed_c_compstr0_shift_x(BITSELECT,20771)@201
    assign rightShiftStage2Idx1Rng8_uid20772_dupName_375_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20771_dupName_375_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20774_dupName_375_i_unnamed_c_compstr0_shift_x(BITJOIN,20773)@201
    assign rightShiftStage2Idx1_uid20774_dupName_375_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20772_dupName_375_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20767_dupName_375_i_unnamed_c_compstr0_shift_x(BITSELECT,20766)@201
    assign rightShiftStage1Idx1Rng4_uid20767_dupName_375_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20766_dupName_375_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20769_dupName_375_i_unnamed_c_compstr0_shift_x(BITJOIN,20768)@201
    assign rightShiftStage1Idx1_uid20769_dupName_375_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20767_dupName_375_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20762_dupName_375_i_unnamed_c_compstr0_shift_x(BITSELECT,20761)@201
    assign rightShiftStage0Idx1Rng1_uid20762_dupName_375_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_q[33:1];

    // rightShiftStage0Idx1_uid20764_dupName_375_i_unnamed_c_compstr0_shift_x(BITJOIN,20763)@201
    assign rightShiftStage0Idx1_uid20764_dupName_375_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20762_dupName_375_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25041_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x(BITSELECT,25040)@200
    assign leftShiftStage2Idx1Rng8_uid25041_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_in = leftShiftStage1_uid25039_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25041_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25041_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25042_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x(BITJOIN,25041)@200
    assign leftShiftStage2Idx1_uid25042_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25041_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25036_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x(BITSELECT,25035)@200
    assign leftShiftStage1Idx1Rng4_uid25036_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_in = leftShiftStage0_uid25034_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25036_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25036_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25037_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x(BITJOIN,25036)@200
    assign leftShiftStage1Idx1_uid25037_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25036_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25031_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x(BITSELECT,25030)@200
    assign leftShiftStage0Idx1Rng1_uid25031_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_94_c_compstr2650_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25031_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25031_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25032_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x(BITJOIN,25031)@200
    assign leftShiftStage0Idx1_uid25032_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25031_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20710_dupName_371_i_unnamed_c_compstr0_shift_x(BITSELECT,20709)@199
    assign rightShiftStage2Idx1Rng8_uid20710_dupName_371_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20709_dupName_371_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20712_dupName_371_i_unnamed_c_compstr0_shift_x(BITJOIN,20711)@199
    assign rightShiftStage2Idx1_uid20712_dupName_371_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20710_dupName_371_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20705_dupName_371_i_unnamed_c_compstr0_shift_x(BITSELECT,20704)@199
    assign rightShiftStage1Idx1Rng4_uid20705_dupName_371_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20704_dupName_371_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20707_dupName_371_i_unnamed_c_compstr0_shift_x(BITJOIN,20706)@199
    assign rightShiftStage1Idx1_uid20707_dupName_371_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20705_dupName_371_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20700_dupName_371_i_unnamed_c_compstr0_shift_x(BITSELECT,20699)@199
    assign rightShiftStage0Idx1Rng1_uid20700_dupName_371_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_q[33:1];

    // rightShiftStage0Idx1_uid20702_dupName_371_i_unnamed_c_compstr0_shift_x(BITJOIN,20701)@199
    assign rightShiftStage0Idx1_uid20702_dupName_371_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20700_dupName_371_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25023_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x(BITSELECT,25022)@198
    assign leftShiftStage2Idx1Rng8_uid25023_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_in = leftShiftStage1_uid25021_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25023_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25023_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25024_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x(BITJOIN,25023)@198
    assign leftShiftStage2Idx1_uid25024_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25023_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25018_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x(BITSELECT,25017)@198
    assign leftShiftStage1Idx1Rng4_uid25018_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_in = leftShiftStage0_uid25016_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25018_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25018_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25019_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x(BITJOIN,25018)@198
    assign leftShiftStage1Idx1_uid25019_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25018_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25013_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x(BITSELECT,25012)@198
    assign leftShiftStage0Idx1Rng1_uid25013_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_93_c_compstr2622_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25013_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25013_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25014_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x(BITJOIN,25013)@198
    assign leftShiftStage0Idx1_uid25014_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25013_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20648_dupName_367_i_unnamed_c_compstr0_shift_x(BITSELECT,20647)@197
    assign rightShiftStage2Idx1Rng8_uid20648_dupName_367_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20647_dupName_367_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20650_dupName_367_i_unnamed_c_compstr0_shift_x(BITJOIN,20649)@197
    assign rightShiftStage2Idx1_uid20650_dupName_367_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20648_dupName_367_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20643_dupName_367_i_unnamed_c_compstr0_shift_x(BITSELECT,20642)@197
    assign rightShiftStage1Idx1Rng4_uid20643_dupName_367_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20642_dupName_367_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20645_dupName_367_i_unnamed_c_compstr0_shift_x(BITJOIN,20644)@197
    assign rightShiftStage1Idx1_uid20645_dupName_367_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20643_dupName_367_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20638_dupName_367_i_unnamed_c_compstr0_shift_x(BITSELECT,20637)@197
    assign rightShiftStage0Idx1Rng1_uid20638_dupName_367_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_q[33:1];

    // rightShiftStage0Idx1_uid20640_dupName_367_i_unnamed_c_compstr0_shift_x(BITJOIN,20639)@197
    assign rightShiftStage0Idx1_uid20640_dupName_367_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20638_dupName_367_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25005_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x(BITSELECT,25004)@196
    assign leftShiftStage2Idx1Rng8_uid25005_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_in = leftShiftStage1_uid25003_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25005_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25005_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25006_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x(BITJOIN,25005)@196
    assign leftShiftStage2Idx1_uid25006_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25005_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25000_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x(BITSELECT,24999)@196
    assign leftShiftStage1Idx1Rng4_uid25000_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_in = leftShiftStage0_uid24998_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25000_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25000_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25001_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x(BITJOIN,25000)@196
    assign leftShiftStage1Idx1_uid25001_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25000_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24995_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x(BITSELECT,24994)@196
    assign leftShiftStage0Idx1Rng1_uid24995_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_92_c_compstr2594_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24995_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24995_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24996_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x(BITJOIN,24995)@196
    assign leftShiftStage0Idx1_uid24996_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24995_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20586_dupName_363_i_unnamed_c_compstr0_shift_x(BITSELECT,20585)@195
    assign rightShiftStage2Idx1Rng8_uid20586_dupName_363_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20585_dupName_363_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20588_dupName_363_i_unnamed_c_compstr0_shift_x(BITJOIN,20587)@195
    assign rightShiftStage2Idx1_uid20588_dupName_363_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20586_dupName_363_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20581_dupName_363_i_unnamed_c_compstr0_shift_x(BITSELECT,20580)@195
    assign rightShiftStage1Idx1Rng4_uid20581_dupName_363_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20580_dupName_363_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20583_dupName_363_i_unnamed_c_compstr0_shift_x(BITJOIN,20582)@195
    assign rightShiftStage1Idx1_uid20583_dupName_363_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20581_dupName_363_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20576_dupName_363_i_unnamed_c_compstr0_shift_x(BITSELECT,20575)@195
    assign rightShiftStage0Idx1Rng1_uid20576_dupName_363_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_q[33:1];

    // rightShiftStage0Idx1_uid20578_dupName_363_i_unnamed_c_compstr0_shift_x(BITJOIN,20577)@195
    assign rightShiftStage0Idx1_uid20578_dupName_363_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20576_dupName_363_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24987_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x(BITSELECT,24986)@194
    assign leftShiftStage2Idx1Rng8_uid24987_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_in = leftShiftStage1_uid24985_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24987_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24987_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24988_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x(BITJOIN,24987)@194
    assign leftShiftStage2Idx1_uid24988_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24987_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24982_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x(BITSELECT,24981)@194
    assign leftShiftStage1Idx1Rng4_uid24982_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_in = leftShiftStage0_uid24980_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24982_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24982_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24983_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x(BITJOIN,24982)@194
    assign leftShiftStage1Idx1_uid24983_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24982_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24977_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x(BITSELECT,24976)@194
    assign leftShiftStage0Idx1Rng1_uid24977_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_91_c_compstr2566_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24977_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24977_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24978_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x(BITJOIN,24977)@194
    assign leftShiftStage0Idx1_uid24978_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24977_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20524_dupName_359_i_unnamed_c_compstr0_shift_x(BITSELECT,20523)@193
    assign rightShiftStage2Idx1Rng8_uid20524_dupName_359_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20523_dupName_359_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20526_dupName_359_i_unnamed_c_compstr0_shift_x(BITJOIN,20525)@193
    assign rightShiftStage2Idx1_uid20526_dupName_359_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20524_dupName_359_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20519_dupName_359_i_unnamed_c_compstr0_shift_x(BITSELECT,20518)@193
    assign rightShiftStage1Idx1Rng4_uid20519_dupName_359_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20518_dupName_359_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20521_dupName_359_i_unnamed_c_compstr0_shift_x(BITJOIN,20520)@193
    assign rightShiftStage1Idx1_uid20521_dupName_359_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20519_dupName_359_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20514_dupName_359_i_unnamed_c_compstr0_shift_x(BITSELECT,20513)@193
    assign rightShiftStage0Idx1Rng1_uid20514_dupName_359_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_q[33:1];

    // rightShiftStage0Idx1_uid20516_dupName_359_i_unnamed_c_compstr0_shift_x(BITJOIN,20515)@193
    assign rightShiftStage0Idx1_uid20516_dupName_359_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20514_dupName_359_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24969_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x(BITSELECT,24968)@192
    assign leftShiftStage2Idx1Rng8_uid24969_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_in = leftShiftStage1_uid24967_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24969_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24969_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24970_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x(BITJOIN,24969)@192
    assign leftShiftStage2Idx1_uid24970_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24969_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24964_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x(BITSELECT,24963)@192
    assign leftShiftStage1Idx1Rng4_uid24964_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_in = leftShiftStage0_uid24962_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24964_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24964_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24965_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x(BITJOIN,24964)@192
    assign leftShiftStage1Idx1_uid24965_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24964_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24959_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x(BITSELECT,24958)@192
    assign leftShiftStage0Idx1Rng1_uid24959_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_90_c_compstr2538_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24959_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24959_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24960_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x(BITJOIN,24959)@192
    assign leftShiftStage0Idx1_uid24960_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24959_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20462_dupName_355_i_unnamed_c_compstr0_shift_x(BITSELECT,20461)@191
    assign rightShiftStage2Idx1Rng8_uid20462_dupName_355_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20461_dupName_355_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20464_dupName_355_i_unnamed_c_compstr0_shift_x(BITJOIN,20463)@191
    assign rightShiftStage2Idx1_uid20464_dupName_355_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20462_dupName_355_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20457_dupName_355_i_unnamed_c_compstr0_shift_x(BITSELECT,20456)@191
    assign rightShiftStage1Idx1Rng4_uid20457_dupName_355_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20456_dupName_355_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20459_dupName_355_i_unnamed_c_compstr0_shift_x(BITJOIN,20458)@191
    assign rightShiftStage1Idx1_uid20459_dupName_355_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20457_dupName_355_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20452_dupName_355_i_unnamed_c_compstr0_shift_x(BITSELECT,20451)@191
    assign rightShiftStage0Idx1Rng1_uid20452_dupName_355_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_q[33:1];

    // rightShiftStage0Idx1_uid20454_dupName_355_i_unnamed_c_compstr0_shift_x(BITJOIN,20453)@191
    assign rightShiftStage0Idx1_uid20454_dupName_355_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20452_dupName_355_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24933_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x(BITSELECT,24932)@190
    assign leftShiftStage2Idx1Rng8_uid24933_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_in = leftShiftStage1_uid24931_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24933_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24933_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24934_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x(BITJOIN,24933)@190
    assign leftShiftStage2Idx1_uid24934_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24933_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24928_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x(BITSELECT,24927)@190
    assign leftShiftStage1Idx1Rng4_uid24928_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_in = leftShiftStage0_uid24926_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24928_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24928_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24929_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x(BITJOIN,24928)@190
    assign leftShiftStage1Idx1_uid24929_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24928_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24923_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x(BITSELECT,24922)@190
    assign leftShiftStage0Idx1Rng1_uid24923_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_89_c_compstr2510_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24923_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24923_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24924_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x(BITJOIN,24923)@190
    assign leftShiftStage0Idx1_uid24924_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24923_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20400_dupName_351_i_unnamed_c_compstr0_shift_x(BITSELECT,20399)@189
    assign rightShiftStage2Idx1Rng8_uid20400_dupName_351_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20399_dupName_351_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20402_dupName_351_i_unnamed_c_compstr0_shift_x(BITJOIN,20401)@189
    assign rightShiftStage2Idx1_uid20402_dupName_351_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20400_dupName_351_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20395_dupName_351_i_unnamed_c_compstr0_shift_x(BITSELECT,20394)@189
    assign rightShiftStage1Idx1Rng4_uid20395_dupName_351_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20394_dupName_351_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20397_dupName_351_i_unnamed_c_compstr0_shift_x(BITJOIN,20396)@189
    assign rightShiftStage1Idx1_uid20397_dupName_351_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20395_dupName_351_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20390_dupName_351_i_unnamed_c_compstr0_shift_x(BITSELECT,20389)@189
    assign rightShiftStage0Idx1Rng1_uid20390_dupName_351_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_q[33:1];

    // rightShiftStage0Idx1_uid20392_dupName_351_i_unnamed_c_compstr0_shift_x(BITJOIN,20391)@189
    assign rightShiftStage0Idx1_uid20392_dupName_351_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20390_dupName_351_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24915_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x(BITSELECT,24914)@188
    assign leftShiftStage2Idx1Rng8_uid24915_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_in = leftShiftStage1_uid24913_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24915_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24915_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24916_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x(BITJOIN,24915)@188
    assign leftShiftStage2Idx1_uid24916_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24915_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24910_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x(BITSELECT,24909)@188
    assign leftShiftStage1Idx1Rng4_uid24910_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_in = leftShiftStage0_uid24908_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24910_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24910_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24911_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x(BITJOIN,24910)@188
    assign leftShiftStage1Idx1_uid24911_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24910_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24905_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x(BITSELECT,24904)@188
    assign leftShiftStage0Idx1Rng1_uid24905_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_88_c_compstr2482_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24905_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24905_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24906_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x(BITJOIN,24905)@188
    assign leftShiftStage0Idx1_uid24906_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24905_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20338_dupName_347_i_unnamed_c_compstr0_shift_x(BITSELECT,20337)@187
    assign rightShiftStage2Idx1Rng8_uid20338_dupName_347_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20337_dupName_347_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20340_dupName_347_i_unnamed_c_compstr0_shift_x(BITJOIN,20339)@187
    assign rightShiftStage2Idx1_uid20340_dupName_347_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20338_dupName_347_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20333_dupName_347_i_unnamed_c_compstr0_shift_x(BITSELECT,20332)@187
    assign rightShiftStage1Idx1Rng4_uid20333_dupName_347_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20332_dupName_347_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20335_dupName_347_i_unnamed_c_compstr0_shift_x(BITJOIN,20334)@187
    assign rightShiftStage1Idx1_uid20335_dupName_347_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20333_dupName_347_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20328_dupName_347_i_unnamed_c_compstr0_shift_x(BITSELECT,20327)@187
    assign rightShiftStage0Idx1Rng1_uid20328_dupName_347_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_q[33:1];

    // rightShiftStage0Idx1_uid20330_dupName_347_i_unnamed_c_compstr0_shift_x(BITJOIN,20329)@187
    assign rightShiftStage0Idx1_uid20330_dupName_347_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20328_dupName_347_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24897_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x(BITSELECT,24896)@186
    assign leftShiftStage2Idx1Rng8_uid24897_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_in = leftShiftStage1_uid24895_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24897_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24897_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24898_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x(BITJOIN,24897)@186
    assign leftShiftStage2Idx1_uid24898_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24897_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24892_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x(BITSELECT,24891)@186
    assign leftShiftStage1Idx1Rng4_uid24892_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_in = leftShiftStage0_uid24890_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24892_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24892_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24893_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x(BITJOIN,24892)@186
    assign leftShiftStage1Idx1_uid24893_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24892_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24887_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x(BITSELECT,24886)@186
    assign leftShiftStage0Idx1Rng1_uid24887_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_87_c_compstr2454_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24887_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24887_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24888_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x(BITJOIN,24887)@186
    assign leftShiftStage0Idx1_uid24888_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24887_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20276_dupName_343_i_unnamed_c_compstr0_shift_x(BITSELECT,20275)@185
    assign rightShiftStage2Idx1Rng8_uid20276_dupName_343_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20275_dupName_343_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20278_dupName_343_i_unnamed_c_compstr0_shift_x(BITJOIN,20277)@185
    assign rightShiftStage2Idx1_uid20278_dupName_343_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20276_dupName_343_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20271_dupName_343_i_unnamed_c_compstr0_shift_x(BITSELECT,20270)@185
    assign rightShiftStage1Idx1Rng4_uid20271_dupName_343_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20270_dupName_343_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20273_dupName_343_i_unnamed_c_compstr0_shift_x(BITJOIN,20272)@185
    assign rightShiftStage1Idx1_uid20273_dupName_343_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20271_dupName_343_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20266_dupName_343_i_unnamed_c_compstr0_shift_x(BITSELECT,20265)@185
    assign rightShiftStage0Idx1Rng1_uid20266_dupName_343_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_q[33:1];

    // rightShiftStage0Idx1_uid20268_dupName_343_i_unnamed_c_compstr0_shift_x(BITJOIN,20267)@185
    assign rightShiftStage0Idx1_uid20268_dupName_343_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20266_dupName_343_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24879_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x(BITSELECT,24878)@184
    assign leftShiftStage2Idx1Rng8_uid24879_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_in = leftShiftStage1_uid24877_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24879_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24879_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24880_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x(BITJOIN,24879)@184
    assign leftShiftStage2Idx1_uid24880_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24879_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24874_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x(BITSELECT,24873)@184
    assign leftShiftStage1Idx1Rng4_uid24874_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_in = leftShiftStage0_uid24872_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24874_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24874_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24875_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x(BITJOIN,24874)@184
    assign leftShiftStage1Idx1_uid24875_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24874_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24869_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x(BITSELECT,24868)@184
    assign leftShiftStage0Idx1Rng1_uid24869_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_86_c_compstr2426_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24869_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24869_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24870_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x(BITJOIN,24869)@184
    assign leftShiftStage0Idx1_uid24870_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24869_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20214_dupName_339_i_unnamed_c_compstr0_shift_x(BITSELECT,20213)@183
    assign rightShiftStage2Idx1Rng8_uid20214_dupName_339_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20213_dupName_339_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20216_dupName_339_i_unnamed_c_compstr0_shift_x(BITJOIN,20215)@183
    assign rightShiftStage2Idx1_uid20216_dupName_339_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20214_dupName_339_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20209_dupName_339_i_unnamed_c_compstr0_shift_x(BITSELECT,20208)@183
    assign rightShiftStage1Idx1Rng4_uid20209_dupName_339_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20208_dupName_339_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20211_dupName_339_i_unnamed_c_compstr0_shift_x(BITJOIN,20210)@183
    assign rightShiftStage1Idx1_uid20211_dupName_339_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20209_dupName_339_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20204_dupName_339_i_unnamed_c_compstr0_shift_x(BITSELECT,20203)@183
    assign rightShiftStage0Idx1Rng1_uid20204_dupName_339_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_q[33:1];

    // rightShiftStage0Idx1_uid20206_dupName_339_i_unnamed_c_compstr0_shift_x(BITJOIN,20205)@183
    assign rightShiftStage0Idx1_uid20206_dupName_339_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20204_dupName_339_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24861_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x(BITSELECT,24860)@182
    assign leftShiftStage2Idx1Rng8_uid24861_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_in = leftShiftStage1_uid24859_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24861_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24861_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24862_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x(BITJOIN,24861)@182
    assign leftShiftStage2Idx1_uid24862_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24861_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24856_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x(BITSELECT,24855)@182
    assign leftShiftStage1Idx1Rng4_uid24856_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_in = leftShiftStage0_uid24854_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24856_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24856_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24857_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x(BITJOIN,24856)@182
    assign leftShiftStage1Idx1_uid24857_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24856_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24851_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x(BITSELECT,24850)@182
    assign leftShiftStage0Idx1Rng1_uid24851_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_85_c_compstr2398_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24851_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24851_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24852_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x(BITJOIN,24851)@182
    assign leftShiftStage0Idx1_uid24852_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24851_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20152_dupName_335_i_unnamed_c_compstr0_shift_x(BITSELECT,20151)@181
    assign rightShiftStage2Idx1Rng8_uid20152_dupName_335_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20151_dupName_335_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20154_dupName_335_i_unnamed_c_compstr0_shift_x(BITJOIN,20153)@181
    assign rightShiftStage2Idx1_uid20154_dupName_335_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20152_dupName_335_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20147_dupName_335_i_unnamed_c_compstr0_shift_x(BITSELECT,20146)@181
    assign rightShiftStage1Idx1Rng4_uid20147_dupName_335_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20146_dupName_335_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20149_dupName_335_i_unnamed_c_compstr0_shift_x(BITJOIN,20148)@181
    assign rightShiftStage1Idx1_uid20149_dupName_335_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20147_dupName_335_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20142_dupName_335_i_unnamed_c_compstr0_shift_x(BITSELECT,20141)@181
    assign rightShiftStage0Idx1Rng1_uid20142_dupName_335_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_q[33:1];

    // rightShiftStage0Idx1_uid20144_dupName_335_i_unnamed_c_compstr0_shift_x(BITJOIN,20143)@181
    assign rightShiftStage0Idx1_uid20144_dupName_335_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20142_dupName_335_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24843_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x(BITSELECT,24842)@180
    assign leftShiftStage2Idx1Rng8_uid24843_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_in = leftShiftStage1_uid24841_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24843_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24843_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24844_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x(BITJOIN,24843)@180
    assign leftShiftStage2Idx1_uid24844_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24843_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24838_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x(BITSELECT,24837)@180
    assign leftShiftStage1Idx1Rng4_uid24838_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_in = leftShiftStage0_uid24836_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24838_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24838_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24839_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x(BITJOIN,24838)@180
    assign leftShiftStage1Idx1_uid24839_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24838_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24833_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x(BITSELECT,24832)@180
    assign leftShiftStage0Idx1Rng1_uid24833_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_84_c_compstr2370_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24833_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24833_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24834_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x(BITJOIN,24833)@180
    assign leftShiftStage0Idx1_uid24834_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24833_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20090_dupName_331_i_unnamed_c_compstr0_shift_x(BITSELECT,20089)@179
    assign rightShiftStage2Idx1Rng8_uid20090_dupName_331_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20089_dupName_331_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20092_dupName_331_i_unnamed_c_compstr0_shift_x(BITJOIN,20091)@179
    assign rightShiftStage2Idx1_uid20092_dupName_331_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20090_dupName_331_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20085_dupName_331_i_unnamed_c_compstr0_shift_x(BITSELECT,20084)@179
    assign rightShiftStage1Idx1Rng4_uid20085_dupName_331_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20084_dupName_331_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20087_dupName_331_i_unnamed_c_compstr0_shift_x(BITJOIN,20086)@179
    assign rightShiftStage1Idx1_uid20087_dupName_331_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20085_dupName_331_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20080_dupName_331_i_unnamed_c_compstr0_shift_x(BITSELECT,20079)@179
    assign rightShiftStage0Idx1Rng1_uid20080_dupName_331_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_q[33:1];

    // rightShiftStage0Idx1_uid20082_dupName_331_i_unnamed_c_compstr0_shift_x(BITJOIN,20081)@179
    assign rightShiftStage0Idx1_uid20082_dupName_331_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20080_dupName_331_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24825_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x(BITSELECT,24824)@178
    assign leftShiftStage2Idx1Rng8_uid24825_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_in = leftShiftStage1_uid24823_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24825_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24825_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24826_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x(BITJOIN,24825)@178
    assign leftShiftStage2Idx1_uid24826_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24825_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24820_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x(BITSELECT,24819)@178
    assign leftShiftStage1Idx1Rng4_uid24820_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_in = leftShiftStage0_uid24818_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24820_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24820_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24821_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x(BITJOIN,24820)@178
    assign leftShiftStage1Idx1_uid24821_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24820_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24815_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x(BITSELECT,24814)@178
    assign leftShiftStage0Idx1Rng1_uid24815_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_83_c_compstr2342_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24815_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24815_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24816_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x(BITJOIN,24815)@178
    assign leftShiftStage0Idx1_uid24816_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24815_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20028_dupName_327_i_unnamed_c_compstr0_shift_x(BITSELECT,20027)@177
    assign rightShiftStage2Idx1Rng8_uid20028_dupName_327_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid20027_dupName_327_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20030_dupName_327_i_unnamed_c_compstr0_shift_x(BITJOIN,20029)@177
    assign rightShiftStage2Idx1_uid20030_dupName_327_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid20028_dupName_327_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20023_dupName_327_i_unnamed_c_compstr0_shift_x(BITSELECT,20022)@177
    assign rightShiftStage1Idx1Rng4_uid20023_dupName_327_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20022_dupName_327_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20025_dupName_327_i_unnamed_c_compstr0_shift_x(BITJOIN,20024)@177
    assign rightShiftStage1Idx1_uid20025_dupName_327_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid20023_dupName_327_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20018_dupName_327_i_unnamed_c_compstr0_shift_x(BITSELECT,20017)@177
    assign rightShiftStage0Idx1Rng1_uid20018_dupName_327_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_q[33:1];

    // rightShiftStage0Idx1_uid20020_dupName_327_i_unnamed_c_compstr0_shift_x(BITJOIN,20019)@177
    assign rightShiftStage0Idx1_uid20020_dupName_327_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20018_dupName_327_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24807_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x(BITSELECT,24806)@176
    assign leftShiftStage2Idx1Rng8_uid24807_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_in = leftShiftStage1_uid24805_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24807_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24807_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24808_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x(BITJOIN,24807)@176
    assign leftShiftStage2Idx1_uid24808_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24807_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24802_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x(BITSELECT,24801)@176
    assign leftShiftStage1Idx1Rng4_uid24802_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_in = leftShiftStage0_uid24800_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24802_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24802_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24803_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x(BITJOIN,24802)@176
    assign leftShiftStage1Idx1_uid24803_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24802_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24797_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x(BITSELECT,24796)@176
    assign leftShiftStage0Idx1Rng1_uid24797_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_82_c_compstr2314_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24797_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24797_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24798_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x(BITJOIN,24797)@176
    assign leftShiftStage0Idx1_uid24798_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24797_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19966_dupName_323_i_unnamed_c_compstr0_shift_x(BITSELECT,19965)@175
    assign rightShiftStage2Idx1Rng8_uid19966_dupName_323_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19965_dupName_323_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19968_dupName_323_i_unnamed_c_compstr0_shift_x(BITJOIN,19967)@175
    assign rightShiftStage2Idx1_uid19968_dupName_323_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19966_dupName_323_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19961_dupName_323_i_unnamed_c_compstr0_shift_x(BITSELECT,19960)@175
    assign rightShiftStage1Idx1Rng4_uid19961_dupName_323_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19960_dupName_323_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19963_dupName_323_i_unnamed_c_compstr0_shift_x(BITJOIN,19962)@175
    assign rightShiftStage1Idx1_uid19963_dupName_323_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19961_dupName_323_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19956_dupName_323_i_unnamed_c_compstr0_shift_x(BITSELECT,19955)@175
    assign rightShiftStage0Idx1Rng1_uid19956_dupName_323_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_q[33:1];

    // rightShiftStage0Idx1_uid19958_dupName_323_i_unnamed_c_compstr0_shift_x(BITJOIN,19957)@175
    assign rightShiftStage0Idx1_uid19958_dupName_323_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19956_dupName_323_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24789_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x(BITSELECT,24788)@174
    assign leftShiftStage2Idx1Rng8_uid24789_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_in = leftShiftStage1_uid24787_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24789_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24789_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24790_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x(BITJOIN,24789)@174
    assign leftShiftStage2Idx1_uid24790_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24789_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24784_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x(BITSELECT,24783)@174
    assign leftShiftStage1Idx1Rng4_uid24784_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_in = leftShiftStage0_uid24782_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24784_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24784_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24785_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x(BITJOIN,24784)@174
    assign leftShiftStage1Idx1_uid24785_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24784_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24779_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x(BITSELECT,24778)@174
    assign leftShiftStage0Idx1Rng1_uid24779_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_81_c_compstr2286_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24779_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24779_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24780_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x(BITJOIN,24779)@174
    assign leftShiftStage0Idx1_uid24780_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24779_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19904_dupName_319_i_unnamed_c_compstr0_shift_x(BITSELECT,19903)@173
    assign rightShiftStage2Idx1Rng8_uid19904_dupName_319_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19903_dupName_319_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19906_dupName_319_i_unnamed_c_compstr0_shift_x(BITJOIN,19905)@173
    assign rightShiftStage2Idx1_uid19906_dupName_319_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19904_dupName_319_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19899_dupName_319_i_unnamed_c_compstr0_shift_x(BITSELECT,19898)@173
    assign rightShiftStage1Idx1Rng4_uid19899_dupName_319_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19898_dupName_319_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19901_dupName_319_i_unnamed_c_compstr0_shift_x(BITJOIN,19900)@173
    assign rightShiftStage1Idx1_uid19901_dupName_319_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19899_dupName_319_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19894_dupName_319_i_unnamed_c_compstr0_shift_x(BITSELECT,19893)@173
    assign rightShiftStage0Idx1Rng1_uid19894_dupName_319_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_q[33:1];

    // rightShiftStage0Idx1_uid19896_dupName_319_i_unnamed_c_compstr0_shift_x(BITJOIN,19895)@173
    assign rightShiftStage0Idx1_uid19896_dupName_319_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19894_dupName_319_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24771_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x(BITSELECT,24770)@172
    assign leftShiftStage2Idx1Rng8_uid24771_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_in = leftShiftStage1_uid24769_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24771_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24771_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24772_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x(BITJOIN,24771)@172
    assign leftShiftStage2Idx1_uid24772_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24771_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24766_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x(BITSELECT,24765)@172
    assign leftShiftStage1Idx1Rng4_uid24766_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_in = leftShiftStage0_uid24764_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24766_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24766_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24767_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x(BITJOIN,24766)@172
    assign leftShiftStage1Idx1_uid24767_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24766_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24761_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x(BITSELECT,24760)@172
    assign leftShiftStage0Idx1Rng1_uid24761_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_80_c_compstr2258_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24761_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24761_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24762_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x(BITJOIN,24761)@172
    assign leftShiftStage0Idx1_uid24762_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24761_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19842_dupName_315_i_unnamed_c_compstr0_shift_x(BITSELECT,19841)@171
    assign rightShiftStage2Idx1Rng8_uid19842_dupName_315_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19841_dupName_315_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19844_dupName_315_i_unnamed_c_compstr0_shift_x(BITJOIN,19843)@171
    assign rightShiftStage2Idx1_uid19844_dupName_315_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19842_dupName_315_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19837_dupName_315_i_unnamed_c_compstr0_shift_x(BITSELECT,19836)@171
    assign rightShiftStage1Idx1Rng4_uid19837_dupName_315_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19836_dupName_315_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19839_dupName_315_i_unnamed_c_compstr0_shift_x(BITJOIN,19838)@171
    assign rightShiftStage1Idx1_uid19839_dupName_315_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19837_dupName_315_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19832_dupName_315_i_unnamed_c_compstr0_shift_x(BITSELECT,19831)@171
    assign rightShiftStage0Idx1Rng1_uid19832_dupName_315_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_q[33:1];

    // rightShiftStage0Idx1_uid19834_dupName_315_i_unnamed_c_compstr0_shift_x(BITJOIN,19833)@171
    assign rightShiftStage0Idx1_uid19834_dupName_315_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19832_dupName_315_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24735_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x(BITSELECT,24734)@170
    assign leftShiftStage2Idx1Rng8_uid24735_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_in = leftShiftStage1_uid24733_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24735_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24735_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24736_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x(BITJOIN,24735)@170
    assign leftShiftStage2Idx1_uid24736_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24735_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24730_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x(BITSELECT,24729)@170
    assign leftShiftStage1Idx1Rng4_uid24730_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_in = leftShiftStage0_uid24728_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24730_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24730_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24731_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x(BITJOIN,24730)@170
    assign leftShiftStage1Idx1_uid24731_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24730_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24725_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x(BITSELECT,24724)@170
    assign leftShiftStage0Idx1Rng1_uid24725_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_79_c_compstr2230_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24725_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24725_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24726_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x(BITJOIN,24725)@170
    assign leftShiftStage0Idx1_uid24726_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24725_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19780_dupName_311_i_unnamed_c_compstr0_shift_x(BITSELECT,19779)@169
    assign rightShiftStage2Idx1Rng8_uid19780_dupName_311_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19779_dupName_311_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19782_dupName_311_i_unnamed_c_compstr0_shift_x(BITJOIN,19781)@169
    assign rightShiftStage2Idx1_uid19782_dupName_311_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19780_dupName_311_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19775_dupName_311_i_unnamed_c_compstr0_shift_x(BITSELECT,19774)@169
    assign rightShiftStage1Idx1Rng4_uid19775_dupName_311_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19774_dupName_311_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19777_dupName_311_i_unnamed_c_compstr0_shift_x(BITJOIN,19776)@169
    assign rightShiftStage1Idx1_uid19777_dupName_311_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19775_dupName_311_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19770_dupName_311_i_unnamed_c_compstr0_shift_x(BITSELECT,19769)@169
    assign rightShiftStage0Idx1Rng1_uid19770_dupName_311_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_q[33:1];

    // rightShiftStage0Idx1_uid19772_dupName_311_i_unnamed_c_compstr0_shift_x(BITJOIN,19771)@169
    assign rightShiftStage0Idx1_uid19772_dupName_311_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19770_dupName_311_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24717_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x(BITSELECT,24716)@168
    assign leftShiftStage2Idx1Rng8_uid24717_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_in = leftShiftStage1_uid24715_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24717_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24717_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24718_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x(BITJOIN,24717)@168
    assign leftShiftStage2Idx1_uid24718_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24717_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24712_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x(BITSELECT,24711)@168
    assign leftShiftStage1Idx1Rng4_uid24712_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_in = leftShiftStage0_uid24710_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24712_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24712_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24713_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x(BITJOIN,24712)@168
    assign leftShiftStage1Idx1_uid24713_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24712_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24707_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x(BITSELECT,24706)@168
    assign leftShiftStage0Idx1Rng1_uid24707_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_78_c_compstr2202_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24707_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24707_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24708_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x(BITJOIN,24707)@168
    assign leftShiftStage0Idx1_uid24708_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24707_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19718_dupName_307_i_unnamed_c_compstr0_shift_x(BITSELECT,19717)@167
    assign rightShiftStage2Idx1Rng8_uid19718_dupName_307_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19717_dupName_307_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19720_dupName_307_i_unnamed_c_compstr0_shift_x(BITJOIN,19719)@167
    assign rightShiftStage2Idx1_uid19720_dupName_307_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19718_dupName_307_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19713_dupName_307_i_unnamed_c_compstr0_shift_x(BITSELECT,19712)@167
    assign rightShiftStage1Idx1Rng4_uid19713_dupName_307_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19712_dupName_307_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19715_dupName_307_i_unnamed_c_compstr0_shift_x(BITJOIN,19714)@167
    assign rightShiftStage1Idx1_uid19715_dupName_307_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19713_dupName_307_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19708_dupName_307_i_unnamed_c_compstr0_shift_x(BITSELECT,19707)@167
    assign rightShiftStage0Idx1Rng1_uid19708_dupName_307_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_q[33:1];

    // rightShiftStage0Idx1_uid19710_dupName_307_i_unnamed_c_compstr0_shift_x(BITJOIN,19709)@167
    assign rightShiftStage0Idx1_uid19710_dupName_307_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19708_dupName_307_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24699_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x(BITSELECT,24698)@166
    assign leftShiftStage2Idx1Rng8_uid24699_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_in = leftShiftStage1_uid24697_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24699_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24699_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24700_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x(BITJOIN,24699)@166
    assign leftShiftStage2Idx1_uid24700_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24699_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24694_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x(BITSELECT,24693)@166
    assign leftShiftStage1Idx1Rng4_uid24694_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_in = leftShiftStage0_uid24692_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24694_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24694_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24695_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x(BITJOIN,24694)@166
    assign leftShiftStage1Idx1_uid24695_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24694_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24689_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x(BITSELECT,24688)@166
    assign leftShiftStage0Idx1Rng1_uid24689_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_77_c_compstr2174_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24689_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24689_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24690_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x(BITJOIN,24689)@166
    assign leftShiftStage0Idx1_uid24690_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24689_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19656_dupName_303_i_unnamed_c_compstr0_shift_x(BITSELECT,19655)@165
    assign rightShiftStage2Idx1Rng8_uid19656_dupName_303_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19655_dupName_303_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19658_dupName_303_i_unnamed_c_compstr0_shift_x(BITJOIN,19657)@165
    assign rightShiftStage2Idx1_uid19658_dupName_303_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19656_dupName_303_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19651_dupName_303_i_unnamed_c_compstr0_shift_x(BITSELECT,19650)@165
    assign rightShiftStage1Idx1Rng4_uid19651_dupName_303_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19650_dupName_303_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19653_dupName_303_i_unnamed_c_compstr0_shift_x(BITJOIN,19652)@165
    assign rightShiftStage1Idx1_uid19653_dupName_303_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19651_dupName_303_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19646_dupName_303_i_unnamed_c_compstr0_shift_x(BITSELECT,19645)@165
    assign rightShiftStage0Idx1Rng1_uid19646_dupName_303_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_q[33:1];

    // rightShiftStage0Idx1_uid19648_dupName_303_i_unnamed_c_compstr0_shift_x(BITJOIN,19647)@165
    assign rightShiftStage0Idx1_uid19648_dupName_303_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19646_dupName_303_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24681_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x(BITSELECT,24680)@164
    assign leftShiftStage2Idx1Rng8_uid24681_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_in = leftShiftStage1_uid24679_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24681_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24681_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24682_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x(BITJOIN,24681)@164
    assign leftShiftStage2Idx1_uid24682_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24681_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24676_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x(BITSELECT,24675)@164
    assign leftShiftStage1Idx1Rng4_uid24676_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_in = leftShiftStage0_uid24674_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24676_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24676_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24677_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x(BITJOIN,24676)@164
    assign leftShiftStage1Idx1_uid24677_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24676_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24671_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x(BITSELECT,24670)@164
    assign leftShiftStage0Idx1Rng1_uid24671_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_76_c_compstr2146_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24671_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24671_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24672_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x(BITJOIN,24671)@164
    assign leftShiftStage0Idx1_uid24672_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24671_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19594_dupName_299_i_unnamed_c_compstr0_shift_x(BITSELECT,19593)@163
    assign rightShiftStage2Idx1Rng8_uid19594_dupName_299_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19593_dupName_299_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19596_dupName_299_i_unnamed_c_compstr0_shift_x(BITJOIN,19595)@163
    assign rightShiftStage2Idx1_uid19596_dupName_299_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19594_dupName_299_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19589_dupName_299_i_unnamed_c_compstr0_shift_x(BITSELECT,19588)@163
    assign rightShiftStage1Idx1Rng4_uid19589_dupName_299_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19588_dupName_299_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19591_dupName_299_i_unnamed_c_compstr0_shift_x(BITJOIN,19590)@163
    assign rightShiftStage1Idx1_uid19591_dupName_299_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19589_dupName_299_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19584_dupName_299_i_unnamed_c_compstr0_shift_x(BITSELECT,19583)@163
    assign rightShiftStage0Idx1Rng1_uid19584_dupName_299_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_q[33:1];

    // rightShiftStage0Idx1_uid19586_dupName_299_i_unnamed_c_compstr0_shift_x(BITJOIN,19585)@163
    assign rightShiftStage0Idx1_uid19586_dupName_299_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19584_dupName_299_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24663_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x(BITSELECT,24662)@162
    assign leftShiftStage2Idx1Rng8_uid24663_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_in = leftShiftStage1_uid24661_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24663_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24663_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24664_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x(BITJOIN,24663)@162
    assign leftShiftStage2Idx1_uid24664_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24663_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24658_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x(BITSELECT,24657)@162
    assign leftShiftStage1Idx1Rng4_uid24658_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_in = leftShiftStage0_uid24656_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24658_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24658_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24659_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x(BITJOIN,24658)@162
    assign leftShiftStage1Idx1_uid24659_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24658_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24653_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x(BITSELECT,24652)@162
    assign leftShiftStage0Idx1Rng1_uid24653_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_75_c_compstr2118_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24653_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24653_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24654_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x(BITJOIN,24653)@162
    assign leftShiftStage0Idx1_uid24654_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24653_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19532_dupName_295_i_unnamed_c_compstr0_shift_x(BITSELECT,19531)@161
    assign rightShiftStage2Idx1Rng8_uid19532_dupName_295_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19531_dupName_295_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19534_dupName_295_i_unnamed_c_compstr0_shift_x(BITJOIN,19533)@161
    assign rightShiftStage2Idx1_uid19534_dupName_295_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19532_dupName_295_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19527_dupName_295_i_unnamed_c_compstr0_shift_x(BITSELECT,19526)@161
    assign rightShiftStage1Idx1Rng4_uid19527_dupName_295_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19526_dupName_295_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19529_dupName_295_i_unnamed_c_compstr0_shift_x(BITJOIN,19528)@161
    assign rightShiftStage1Idx1_uid19529_dupName_295_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19527_dupName_295_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19522_dupName_295_i_unnamed_c_compstr0_shift_x(BITSELECT,19521)@161
    assign rightShiftStage0Idx1Rng1_uid19522_dupName_295_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_q[33:1];

    // rightShiftStage0Idx1_uid19524_dupName_295_i_unnamed_c_compstr0_shift_x(BITJOIN,19523)@161
    assign rightShiftStage0Idx1_uid19524_dupName_295_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19522_dupName_295_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24645_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x(BITSELECT,24644)@160
    assign leftShiftStage2Idx1Rng8_uid24645_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_in = leftShiftStage1_uid24643_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24645_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24645_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24646_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x(BITJOIN,24645)@160
    assign leftShiftStage2Idx1_uid24646_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24645_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24640_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x(BITSELECT,24639)@160
    assign leftShiftStage1Idx1Rng4_uid24640_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_in = leftShiftStage0_uid24638_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24640_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24640_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24641_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x(BITJOIN,24640)@160
    assign leftShiftStage1Idx1_uid24641_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24640_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24635_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x(BITSELECT,24634)@160
    assign leftShiftStage0Idx1Rng1_uid24635_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_74_c_compstr2090_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24635_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24635_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24636_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x(BITJOIN,24635)@160
    assign leftShiftStage0Idx1_uid24636_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24635_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19470_dupName_291_i_unnamed_c_compstr0_shift_x(BITSELECT,19469)@159
    assign rightShiftStage2Idx1Rng8_uid19470_dupName_291_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19469_dupName_291_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19472_dupName_291_i_unnamed_c_compstr0_shift_x(BITJOIN,19471)@159
    assign rightShiftStage2Idx1_uid19472_dupName_291_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19470_dupName_291_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19465_dupName_291_i_unnamed_c_compstr0_shift_x(BITSELECT,19464)@159
    assign rightShiftStage1Idx1Rng4_uid19465_dupName_291_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19464_dupName_291_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19467_dupName_291_i_unnamed_c_compstr0_shift_x(BITJOIN,19466)@159
    assign rightShiftStage1Idx1_uid19467_dupName_291_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19465_dupName_291_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19460_dupName_291_i_unnamed_c_compstr0_shift_x(BITSELECT,19459)@159
    assign rightShiftStage0Idx1Rng1_uid19460_dupName_291_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_q[33:1];

    // rightShiftStage0Idx1_uid19462_dupName_291_i_unnamed_c_compstr0_shift_x(BITJOIN,19461)@159
    assign rightShiftStage0Idx1_uid19462_dupName_291_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19460_dupName_291_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24627_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x(BITSELECT,24626)@158
    assign leftShiftStage2Idx1Rng8_uid24627_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_in = leftShiftStage1_uid24625_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24627_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24627_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24628_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x(BITJOIN,24627)@158
    assign leftShiftStage2Idx1_uid24628_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24627_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24622_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x(BITSELECT,24621)@158
    assign leftShiftStage1Idx1Rng4_uid24622_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_in = leftShiftStage0_uid24620_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24622_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24622_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24623_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x(BITJOIN,24622)@158
    assign leftShiftStage1Idx1_uid24623_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24622_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24617_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x(BITSELECT,24616)@158
    assign leftShiftStage0Idx1Rng1_uid24617_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_73_c_compstr2062_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24617_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24617_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24618_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x(BITJOIN,24617)@158
    assign leftShiftStage0Idx1_uid24618_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24617_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19408_dupName_287_i_unnamed_c_compstr0_shift_x(BITSELECT,19407)@157
    assign rightShiftStage2Idx1Rng8_uid19408_dupName_287_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19407_dupName_287_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19410_dupName_287_i_unnamed_c_compstr0_shift_x(BITJOIN,19409)@157
    assign rightShiftStage2Idx1_uid19410_dupName_287_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19408_dupName_287_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19403_dupName_287_i_unnamed_c_compstr0_shift_x(BITSELECT,19402)@157
    assign rightShiftStage1Idx1Rng4_uid19403_dupName_287_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19402_dupName_287_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19405_dupName_287_i_unnamed_c_compstr0_shift_x(BITJOIN,19404)@157
    assign rightShiftStage1Idx1_uid19405_dupName_287_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19403_dupName_287_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19398_dupName_287_i_unnamed_c_compstr0_shift_x(BITSELECT,19397)@157
    assign rightShiftStage0Idx1Rng1_uid19398_dupName_287_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_q[33:1];

    // rightShiftStage0Idx1_uid19400_dupName_287_i_unnamed_c_compstr0_shift_x(BITJOIN,19399)@157
    assign rightShiftStage0Idx1_uid19400_dupName_287_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19398_dupName_287_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24609_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x(BITSELECT,24608)@156
    assign leftShiftStage2Idx1Rng8_uid24609_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_in = leftShiftStage1_uid24607_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24609_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24609_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24610_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x(BITJOIN,24609)@156
    assign leftShiftStage2Idx1_uid24610_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24609_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24604_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x(BITSELECT,24603)@156
    assign leftShiftStage1Idx1Rng4_uid24604_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_in = leftShiftStage0_uid24602_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24604_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24604_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24605_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x(BITJOIN,24604)@156
    assign leftShiftStage1Idx1_uid24605_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24604_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24599_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x(BITSELECT,24598)@156
    assign leftShiftStage0Idx1Rng1_uid24599_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_72_c_compstr2034_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24599_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24599_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24600_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x(BITJOIN,24599)@156
    assign leftShiftStage0Idx1_uid24600_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24599_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19346_dupName_283_i_unnamed_c_compstr0_shift_x(BITSELECT,19345)@155
    assign rightShiftStage2Idx1Rng8_uid19346_dupName_283_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19345_dupName_283_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19348_dupName_283_i_unnamed_c_compstr0_shift_x(BITJOIN,19347)@155
    assign rightShiftStage2Idx1_uid19348_dupName_283_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19346_dupName_283_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19341_dupName_283_i_unnamed_c_compstr0_shift_x(BITSELECT,19340)@155
    assign rightShiftStage1Idx1Rng4_uid19341_dupName_283_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19340_dupName_283_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19343_dupName_283_i_unnamed_c_compstr0_shift_x(BITJOIN,19342)@155
    assign rightShiftStage1Idx1_uid19343_dupName_283_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19341_dupName_283_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19336_dupName_283_i_unnamed_c_compstr0_shift_x(BITSELECT,19335)@155
    assign rightShiftStage0Idx1Rng1_uid19336_dupName_283_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_q[33:1];

    // rightShiftStage0Idx1_uid19338_dupName_283_i_unnamed_c_compstr0_shift_x(BITJOIN,19337)@155
    assign rightShiftStage0Idx1_uid19338_dupName_283_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19336_dupName_283_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24591_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x(BITSELECT,24590)@154
    assign leftShiftStage2Idx1Rng8_uid24591_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_in = leftShiftStage1_uid24589_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24591_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24591_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24592_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x(BITJOIN,24591)@154
    assign leftShiftStage2Idx1_uid24592_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24591_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24586_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x(BITSELECT,24585)@154
    assign leftShiftStage1Idx1Rng4_uid24586_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_in = leftShiftStage0_uid24584_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24586_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24586_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24587_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x(BITJOIN,24586)@154
    assign leftShiftStage1Idx1_uid24587_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24586_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24581_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x(BITSELECT,24580)@154
    assign leftShiftStage0Idx1Rng1_uid24581_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_71_c_compstr2006_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24581_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24581_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24582_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x(BITJOIN,24581)@154
    assign leftShiftStage0Idx1_uid24582_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24581_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19284_dupName_279_i_unnamed_c_compstr0_shift_x(BITSELECT,19283)@153
    assign rightShiftStage2Idx1Rng8_uid19284_dupName_279_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19283_dupName_279_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19286_dupName_279_i_unnamed_c_compstr0_shift_x(BITJOIN,19285)@153
    assign rightShiftStage2Idx1_uid19286_dupName_279_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19284_dupName_279_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19279_dupName_279_i_unnamed_c_compstr0_shift_x(BITSELECT,19278)@153
    assign rightShiftStage1Idx1Rng4_uid19279_dupName_279_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19278_dupName_279_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19281_dupName_279_i_unnamed_c_compstr0_shift_x(BITJOIN,19280)@153
    assign rightShiftStage1Idx1_uid19281_dupName_279_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19279_dupName_279_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19274_dupName_279_i_unnamed_c_compstr0_shift_x(BITSELECT,19273)@153
    assign rightShiftStage0Idx1Rng1_uid19274_dupName_279_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_q[33:1];

    // rightShiftStage0Idx1_uid19276_dupName_279_i_unnamed_c_compstr0_shift_x(BITJOIN,19275)@153
    assign rightShiftStage0Idx1_uid19276_dupName_279_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19274_dupName_279_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24573_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x(BITSELECT,24572)@152
    assign leftShiftStage2Idx1Rng8_uid24573_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_in = leftShiftStage1_uid24571_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24573_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24573_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24574_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x(BITJOIN,24573)@152
    assign leftShiftStage2Idx1_uid24574_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24573_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24568_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x(BITSELECT,24567)@152
    assign leftShiftStage1Idx1Rng4_uid24568_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_in = leftShiftStage0_uid24566_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24568_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24568_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24569_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x(BITJOIN,24568)@152
    assign leftShiftStage1Idx1_uid24569_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24568_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24563_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x(BITSELECT,24562)@152
    assign leftShiftStage0Idx1Rng1_uid24563_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_70_c_compstr1978_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24563_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24563_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24564_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x(BITJOIN,24563)@152
    assign leftShiftStage0Idx1_uid24564_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24563_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19222_dupName_275_i_unnamed_c_compstr0_shift_x(BITSELECT,19221)@151
    assign rightShiftStage2Idx1Rng8_uid19222_dupName_275_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19221_dupName_275_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19224_dupName_275_i_unnamed_c_compstr0_shift_x(BITJOIN,19223)@151
    assign rightShiftStage2Idx1_uid19224_dupName_275_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19222_dupName_275_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19217_dupName_275_i_unnamed_c_compstr0_shift_x(BITSELECT,19216)@151
    assign rightShiftStage1Idx1Rng4_uid19217_dupName_275_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19216_dupName_275_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19219_dupName_275_i_unnamed_c_compstr0_shift_x(BITJOIN,19218)@151
    assign rightShiftStage1Idx1_uid19219_dupName_275_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19217_dupName_275_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19212_dupName_275_i_unnamed_c_compstr0_shift_x(BITSELECT,19211)@151
    assign rightShiftStage0Idx1Rng1_uid19212_dupName_275_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_q[33:1];

    // rightShiftStage0Idx1_uid19214_dupName_275_i_unnamed_c_compstr0_shift_x(BITJOIN,19213)@151
    assign rightShiftStage0Idx1_uid19214_dupName_275_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19212_dupName_275_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24537_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x(BITSELECT,24536)@150
    assign leftShiftStage2Idx1Rng8_uid24537_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_in = leftShiftStage1_uid24535_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24537_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24537_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24538_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x(BITJOIN,24537)@150
    assign leftShiftStage2Idx1_uid24538_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24537_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24532_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x(BITSELECT,24531)@150
    assign leftShiftStage1Idx1Rng4_uid24532_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_in = leftShiftStage0_uid24530_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24532_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24532_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24533_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x(BITJOIN,24532)@150
    assign leftShiftStage1Idx1_uid24533_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24532_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24527_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x(BITSELECT,24526)@150
    assign leftShiftStage0Idx1Rng1_uid24527_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_69_c_compstr1950_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24527_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24527_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24528_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x(BITJOIN,24527)@150
    assign leftShiftStage0Idx1_uid24528_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24527_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19160_dupName_271_i_unnamed_c_compstr0_shift_x(BITSELECT,19159)@149
    assign rightShiftStage2Idx1Rng8_uid19160_dupName_271_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19159_dupName_271_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19162_dupName_271_i_unnamed_c_compstr0_shift_x(BITJOIN,19161)@149
    assign rightShiftStage2Idx1_uid19162_dupName_271_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19160_dupName_271_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19155_dupName_271_i_unnamed_c_compstr0_shift_x(BITSELECT,19154)@149
    assign rightShiftStage1Idx1Rng4_uid19155_dupName_271_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19154_dupName_271_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19157_dupName_271_i_unnamed_c_compstr0_shift_x(BITJOIN,19156)@149
    assign rightShiftStage1Idx1_uid19157_dupName_271_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19155_dupName_271_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19150_dupName_271_i_unnamed_c_compstr0_shift_x(BITSELECT,19149)@149
    assign rightShiftStage0Idx1Rng1_uid19150_dupName_271_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_q[33:1];

    // rightShiftStage0Idx1_uid19152_dupName_271_i_unnamed_c_compstr0_shift_x(BITJOIN,19151)@149
    assign rightShiftStage0Idx1_uid19152_dupName_271_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19150_dupName_271_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24519_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x(BITSELECT,24518)@148
    assign leftShiftStage2Idx1Rng8_uid24519_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_in = leftShiftStage1_uid24517_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24519_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24519_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24520_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x(BITJOIN,24519)@148
    assign leftShiftStage2Idx1_uid24520_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24519_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24514_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x(BITSELECT,24513)@148
    assign leftShiftStage1Idx1Rng4_uid24514_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_in = leftShiftStage0_uid24512_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24514_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24514_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24515_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x(BITJOIN,24514)@148
    assign leftShiftStage1Idx1_uid24515_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24514_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24509_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x(BITSELECT,24508)@148
    assign leftShiftStage0Idx1Rng1_uid24509_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_68_c_compstr1922_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24509_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24509_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24510_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x(BITJOIN,24509)@148
    assign leftShiftStage0Idx1_uid24510_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24509_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19098_dupName_267_i_unnamed_c_compstr0_shift_x(BITSELECT,19097)@147
    assign rightShiftStage2Idx1Rng8_uid19098_dupName_267_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19097_dupName_267_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19100_dupName_267_i_unnamed_c_compstr0_shift_x(BITJOIN,19099)@147
    assign rightShiftStage2Idx1_uid19100_dupName_267_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19098_dupName_267_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19093_dupName_267_i_unnamed_c_compstr0_shift_x(BITSELECT,19092)@147
    assign rightShiftStage1Idx1Rng4_uid19093_dupName_267_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19092_dupName_267_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19095_dupName_267_i_unnamed_c_compstr0_shift_x(BITJOIN,19094)@147
    assign rightShiftStage1Idx1_uid19095_dupName_267_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19093_dupName_267_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19088_dupName_267_i_unnamed_c_compstr0_shift_x(BITSELECT,19087)@147
    assign rightShiftStage0Idx1Rng1_uid19088_dupName_267_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_q[33:1];

    // rightShiftStage0Idx1_uid19090_dupName_267_i_unnamed_c_compstr0_shift_x(BITJOIN,19089)@147
    assign rightShiftStage0Idx1_uid19090_dupName_267_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19088_dupName_267_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24501_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x(BITSELECT,24500)@146
    assign leftShiftStage2Idx1Rng8_uid24501_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_in = leftShiftStage1_uid24499_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24501_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24501_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24502_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x(BITJOIN,24501)@146
    assign leftShiftStage2Idx1_uid24502_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24501_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24496_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x(BITSELECT,24495)@146
    assign leftShiftStage1Idx1Rng4_uid24496_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_in = leftShiftStage0_uid24494_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24496_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24496_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24497_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x(BITJOIN,24496)@146
    assign leftShiftStage1Idx1_uid24497_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24496_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24491_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x(BITSELECT,24490)@146
    assign leftShiftStage0Idx1Rng1_uid24491_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_67_c_compstr1894_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24491_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24491_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24492_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x(BITJOIN,24491)@146
    assign leftShiftStage0Idx1_uid24492_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24491_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19036_dupName_263_i_unnamed_c_compstr0_shift_x(BITSELECT,19035)@145
    assign rightShiftStage2Idx1Rng8_uid19036_dupName_263_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid19035_dupName_263_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19038_dupName_263_i_unnamed_c_compstr0_shift_x(BITJOIN,19037)@145
    assign rightShiftStage2Idx1_uid19038_dupName_263_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid19036_dupName_263_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19031_dupName_263_i_unnamed_c_compstr0_shift_x(BITSELECT,19030)@145
    assign rightShiftStage1Idx1Rng4_uid19031_dupName_263_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19030_dupName_263_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19033_dupName_263_i_unnamed_c_compstr0_shift_x(BITJOIN,19032)@145
    assign rightShiftStage1Idx1_uid19033_dupName_263_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid19031_dupName_263_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19026_dupName_263_i_unnamed_c_compstr0_shift_x(BITSELECT,19025)@145
    assign rightShiftStage0Idx1Rng1_uid19026_dupName_263_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_q[33:1];

    // rightShiftStage0Idx1_uid19028_dupName_263_i_unnamed_c_compstr0_shift_x(BITJOIN,19027)@145
    assign rightShiftStage0Idx1_uid19028_dupName_263_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19026_dupName_263_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24483_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x(BITSELECT,24482)@144
    assign leftShiftStage2Idx1Rng8_uid24483_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_in = leftShiftStage1_uid24481_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24483_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24483_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24484_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x(BITJOIN,24483)@144
    assign leftShiftStage2Idx1_uid24484_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24483_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24478_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x(BITSELECT,24477)@144
    assign leftShiftStage1Idx1Rng4_uid24478_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_in = leftShiftStage0_uid24476_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24478_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24478_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24479_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x(BITJOIN,24478)@144
    assign leftShiftStage1Idx1_uid24479_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24478_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24473_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x(BITSELECT,24472)@144
    assign leftShiftStage0Idx1Rng1_uid24473_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_66_c_compstr1866_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24473_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24473_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24474_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x(BITJOIN,24473)@144
    assign leftShiftStage0Idx1_uid24474_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24473_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18974_dupName_259_i_unnamed_c_compstr0_shift_x(BITSELECT,18973)@143
    assign rightShiftStage2Idx1Rng8_uid18974_dupName_259_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18973_dupName_259_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18976_dupName_259_i_unnamed_c_compstr0_shift_x(BITJOIN,18975)@143
    assign rightShiftStage2Idx1_uid18976_dupName_259_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18974_dupName_259_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18969_dupName_259_i_unnamed_c_compstr0_shift_x(BITSELECT,18968)@143
    assign rightShiftStage1Idx1Rng4_uid18969_dupName_259_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18968_dupName_259_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18971_dupName_259_i_unnamed_c_compstr0_shift_x(BITJOIN,18970)@143
    assign rightShiftStage1Idx1_uid18971_dupName_259_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18969_dupName_259_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18964_dupName_259_i_unnamed_c_compstr0_shift_x(BITSELECT,18963)@143
    assign rightShiftStage0Idx1Rng1_uid18964_dupName_259_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_q[33:1];

    // rightShiftStage0Idx1_uid18966_dupName_259_i_unnamed_c_compstr0_shift_x(BITJOIN,18965)@143
    assign rightShiftStage0Idx1_uid18966_dupName_259_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18964_dupName_259_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24465_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x(BITSELECT,24464)@142
    assign leftShiftStage2Idx1Rng8_uid24465_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_in = leftShiftStage1_uid24463_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24465_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24465_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24466_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x(BITJOIN,24465)@142
    assign leftShiftStage2Idx1_uid24466_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24465_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24460_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x(BITSELECT,24459)@142
    assign leftShiftStage1Idx1Rng4_uid24460_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_in = leftShiftStage0_uid24458_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24460_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24460_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24461_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x(BITJOIN,24460)@142
    assign leftShiftStage1Idx1_uid24461_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24460_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24455_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x(BITSELECT,24454)@142
    assign leftShiftStage0Idx1Rng1_uid24455_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_65_c_compstr1838_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24455_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24455_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24456_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x(BITJOIN,24455)@142
    assign leftShiftStage0Idx1_uid24456_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24455_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18912_dupName_255_i_unnamed_c_compstr0_shift_x(BITSELECT,18911)@141
    assign rightShiftStage2Idx1Rng8_uid18912_dupName_255_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18911_dupName_255_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18914_dupName_255_i_unnamed_c_compstr0_shift_x(BITJOIN,18913)@141
    assign rightShiftStage2Idx1_uid18914_dupName_255_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18912_dupName_255_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18907_dupName_255_i_unnamed_c_compstr0_shift_x(BITSELECT,18906)@141
    assign rightShiftStage1Idx1Rng4_uid18907_dupName_255_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18906_dupName_255_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18909_dupName_255_i_unnamed_c_compstr0_shift_x(BITJOIN,18908)@141
    assign rightShiftStage1Idx1_uid18909_dupName_255_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18907_dupName_255_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18902_dupName_255_i_unnamed_c_compstr0_shift_x(BITSELECT,18901)@141
    assign rightShiftStage0Idx1Rng1_uid18902_dupName_255_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_q[33:1];

    // rightShiftStage0Idx1_uid18904_dupName_255_i_unnamed_c_compstr0_shift_x(BITJOIN,18903)@141
    assign rightShiftStage0Idx1_uid18904_dupName_255_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18902_dupName_255_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24447_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x(BITSELECT,24446)@140
    assign leftShiftStage2Idx1Rng8_uid24447_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_in = leftShiftStage1_uid24445_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24447_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24447_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24448_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x(BITJOIN,24447)@140
    assign leftShiftStage2Idx1_uid24448_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24447_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24442_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x(BITSELECT,24441)@140
    assign leftShiftStage1Idx1Rng4_uid24442_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_in = leftShiftStage0_uid24440_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24442_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24442_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24443_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x(BITJOIN,24442)@140
    assign leftShiftStage1Idx1_uid24443_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24442_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24437_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x(BITSELECT,24436)@140
    assign leftShiftStage0Idx1Rng1_uid24437_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_64_c_compstr1810_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24437_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24437_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24438_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x(BITJOIN,24437)@140
    assign leftShiftStage0Idx1_uid24438_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24437_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18850_dupName_251_i_unnamed_c_compstr0_shift_x(BITSELECT,18849)@139
    assign rightShiftStage2Idx1Rng8_uid18850_dupName_251_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18849_dupName_251_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18852_dupName_251_i_unnamed_c_compstr0_shift_x(BITJOIN,18851)@139
    assign rightShiftStage2Idx1_uid18852_dupName_251_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18850_dupName_251_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18845_dupName_251_i_unnamed_c_compstr0_shift_x(BITSELECT,18844)@139
    assign rightShiftStage1Idx1Rng4_uid18845_dupName_251_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18844_dupName_251_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18847_dupName_251_i_unnamed_c_compstr0_shift_x(BITJOIN,18846)@139
    assign rightShiftStage1Idx1_uid18847_dupName_251_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18845_dupName_251_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18840_dupName_251_i_unnamed_c_compstr0_shift_x(BITSELECT,18839)@139
    assign rightShiftStage0Idx1Rng1_uid18840_dupName_251_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_q[33:1];

    // rightShiftStage0Idx1_uid18842_dupName_251_i_unnamed_c_compstr0_shift_x(BITJOIN,18841)@139
    assign rightShiftStage0Idx1_uid18842_dupName_251_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18840_dupName_251_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24429_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x(BITSELECT,24428)@138
    assign leftShiftStage2Idx1Rng8_uid24429_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_in = leftShiftStage1_uid24427_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24429_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24429_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24430_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x(BITJOIN,24429)@138
    assign leftShiftStage2Idx1_uid24430_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24429_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24424_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x(BITSELECT,24423)@138
    assign leftShiftStage1Idx1Rng4_uid24424_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_in = leftShiftStage0_uid24422_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24424_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24424_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24425_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x(BITJOIN,24424)@138
    assign leftShiftStage1Idx1_uid24425_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24424_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24419_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x(BITSELECT,24418)@138
    assign leftShiftStage0Idx1Rng1_uid24419_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_63_c_compstr1782_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24419_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24419_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24420_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x(BITJOIN,24419)@138
    assign leftShiftStage0Idx1_uid24420_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24419_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18788_dupName_247_i_unnamed_c_compstr0_shift_x(BITSELECT,18787)@137
    assign rightShiftStage2Idx1Rng8_uid18788_dupName_247_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18787_dupName_247_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18790_dupName_247_i_unnamed_c_compstr0_shift_x(BITJOIN,18789)@137
    assign rightShiftStage2Idx1_uid18790_dupName_247_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18788_dupName_247_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18783_dupName_247_i_unnamed_c_compstr0_shift_x(BITSELECT,18782)@137
    assign rightShiftStage1Idx1Rng4_uid18783_dupName_247_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18782_dupName_247_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18785_dupName_247_i_unnamed_c_compstr0_shift_x(BITJOIN,18784)@137
    assign rightShiftStage1Idx1_uid18785_dupName_247_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18783_dupName_247_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18778_dupName_247_i_unnamed_c_compstr0_shift_x(BITSELECT,18777)@137
    assign rightShiftStage0Idx1Rng1_uid18778_dupName_247_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_q[33:1];

    // rightShiftStage0Idx1_uid18780_dupName_247_i_unnamed_c_compstr0_shift_x(BITJOIN,18779)@137
    assign rightShiftStage0Idx1_uid18780_dupName_247_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18778_dupName_247_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24411_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x(BITSELECT,24410)@136
    assign leftShiftStage2Idx1Rng8_uid24411_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_in = leftShiftStage1_uid24409_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24411_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24411_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24412_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x(BITJOIN,24411)@136
    assign leftShiftStage2Idx1_uid24412_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24411_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24406_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x(BITSELECT,24405)@136
    assign leftShiftStage1Idx1Rng4_uid24406_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_in = leftShiftStage0_uid24404_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24406_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24406_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24407_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x(BITJOIN,24406)@136
    assign leftShiftStage1Idx1_uid24407_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24406_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24401_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x(BITSELECT,24400)@136
    assign leftShiftStage0Idx1Rng1_uid24401_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_62_c_compstr1754_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24401_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24401_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24402_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x(BITJOIN,24401)@136
    assign leftShiftStage0Idx1_uid24402_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24401_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18726_dupName_243_i_unnamed_c_compstr0_shift_x(BITSELECT,18725)@135
    assign rightShiftStage2Idx1Rng8_uid18726_dupName_243_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18725_dupName_243_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18728_dupName_243_i_unnamed_c_compstr0_shift_x(BITJOIN,18727)@135
    assign rightShiftStage2Idx1_uid18728_dupName_243_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18726_dupName_243_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18721_dupName_243_i_unnamed_c_compstr0_shift_x(BITSELECT,18720)@135
    assign rightShiftStage1Idx1Rng4_uid18721_dupName_243_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18720_dupName_243_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18723_dupName_243_i_unnamed_c_compstr0_shift_x(BITJOIN,18722)@135
    assign rightShiftStage1Idx1_uid18723_dupName_243_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18721_dupName_243_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18716_dupName_243_i_unnamed_c_compstr0_shift_x(BITSELECT,18715)@135
    assign rightShiftStage0Idx1Rng1_uid18716_dupName_243_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_q[33:1];

    // rightShiftStage0Idx1_uid18718_dupName_243_i_unnamed_c_compstr0_shift_x(BITJOIN,18717)@135
    assign rightShiftStage0Idx1_uid18718_dupName_243_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18716_dupName_243_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24393_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x(BITSELECT,24392)@134
    assign leftShiftStage2Idx1Rng8_uid24393_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_in = leftShiftStage1_uid24391_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24393_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24393_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24394_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x(BITJOIN,24393)@134
    assign leftShiftStage2Idx1_uid24394_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24393_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24388_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x(BITSELECT,24387)@134
    assign leftShiftStage1Idx1Rng4_uid24388_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_in = leftShiftStage0_uid24386_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24388_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24388_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24389_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x(BITJOIN,24388)@134
    assign leftShiftStage1Idx1_uid24389_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24388_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24383_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x(BITSELECT,24382)@134
    assign leftShiftStage0Idx1Rng1_uid24383_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_61_c_compstr1726_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24383_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24383_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24384_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x(BITJOIN,24383)@134
    assign leftShiftStage0Idx1_uid24384_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24383_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18664_dupName_239_i_unnamed_c_compstr0_shift_x(BITSELECT,18663)@133
    assign rightShiftStage2Idx1Rng8_uid18664_dupName_239_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18663_dupName_239_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18666_dupName_239_i_unnamed_c_compstr0_shift_x(BITJOIN,18665)@133
    assign rightShiftStage2Idx1_uid18666_dupName_239_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18664_dupName_239_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18659_dupName_239_i_unnamed_c_compstr0_shift_x(BITSELECT,18658)@133
    assign rightShiftStage1Idx1Rng4_uid18659_dupName_239_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18658_dupName_239_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18661_dupName_239_i_unnamed_c_compstr0_shift_x(BITJOIN,18660)@133
    assign rightShiftStage1Idx1_uid18661_dupName_239_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18659_dupName_239_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18654_dupName_239_i_unnamed_c_compstr0_shift_x(BITSELECT,18653)@133
    assign rightShiftStage0Idx1Rng1_uid18654_dupName_239_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_q[33:1];

    // rightShiftStage0Idx1_uid18656_dupName_239_i_unnamed_c_compstr0_shift_x(BITJOIN,18655)@133
    assign rightShiftStage0Idx1_uid18656_dupName_239_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18654_dupName_239_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24375_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x(BITSELECT,24374)@132
    assign leftShiftStage2Idx1Rng8_uid24375_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_in = leftShiftStage1_uid24373_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24375_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24375_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24376_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x(BITJOIN,24375)@132
    assign leftShiftStage2Idx1_uid24376_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24375_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24370_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x(BITSELECT,24369)@132
    assign leftShiftStage1Idx1Rng4_uid24370_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_in = leftShiftStage0_uid24368_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24370_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24370_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24371_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x(BITJOIN,24370)@132
    assign leftShiftStage1Idx1_uid24371_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24370_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24365_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x(BITSELECT,24364)@132
    assign leftShiftStage0Idx1Rng1_uid24365_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_60_c_compstr1698_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24365_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24365_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24366_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x(BITJOIN,24365)@132
    assign leftShiftStage0Idx1_uid24366_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24365_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18602_dupName_235_i_unnamed_c_compstr0_shift_x(BITSELECT,18601)@131
    assign rightShiftStage2Idx1Rng8_uid18602_dupName_235_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18601_dupName_235_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18604_dupName_235_i_unnamed_c_compstr0_shift_x(BITJOIN,18603)@131
    assign rightShiftStage2Idx1_uid18604_dupName_235_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18602_dupName_235_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18597_dupName_235_i_unnamed_c_compstr0_shift_x(BITSELECT,18596)@131
    assign rightShiftStage1Idx1Rng4_uid18597_dupName_235_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18596_dupName_235_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18599_dupName_235_i_unnamed_c_compstr0_shift_x(BITJOIN,18598)@131
    assign rightShiftStage1Idx1_uid18599_dupName_235_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18597_dupName_235_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18592_dupName_235_i_unnamed_c_compstr0_shift_x(BITSELECT,18591)@131
    assign rightShiftStage0Idx1Rng1_uid18592_dupName_235_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_q[33:1];

    // rightShiftStage0Idx1_uid18594_dupName_235_i_unnamed_c_compstr0_shift_x(BITJOIN,18593)@131
    assign rightShiftStage0Idx1_uid18594_dupName_235_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18592_dupName_235_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24339_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x(BITSELECT,24338)@130
    assign leftShiftStage2Idx1Rng8_uid24339_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_in = leftShiftStage1_uid24337_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24339_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24339_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24340_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x(BITJOIN,24339)@130
    assign leftShiftStage2Idx1_uid24340_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24339_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24334_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x(BITSELECT,24333)@130
    assign leftShiftStage1Idx1Rng4_uid24334_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_in = leftShiftStage0_uid24332_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24334_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24334_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24335_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x(BITJOIN,24334)@130
    assign leftShiftStage1Idx1_uid24335_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24334_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24329_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x(BITSELECT,24328)@130
    assign leftShiftStage0Idx1Rng1_uid24329_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_59_c_compstr1670_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24329_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24329_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24330_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x(BITJOIN,24329)@130
    assign leftShiftStage0Idx1_uid24330_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24329_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18540_dupName_231_i_unnamed_c_compstr0_shift_x(BITSELECT,18539)@129
    assign rightShiftStage2Idx1Rng8_uid18540_dupName_231_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18539_dupName_231_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18542_dupName_231_i_unnamed_c_compstr0_shift_x(BITJOIN,18541)@129
    assign rightShiftStage2Idx1_uid18542_dupName_231_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18540_dupName_231_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18535_dupName_231_i_unnamed_c_compstr0_shift_x(BITSELECT,18534)@129
    assign rightShiftStage1Idx1Rng4_uid18535_dupName_231_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18534_dupName_231_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18537_dupName_231_i_unnamed_c_compstr0_shift_x(BITJOIN,18536)@129
    assign rightShiftStage1Idx1_uid18537_dupName_231_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18535_dupName_231_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18530_dupName_231_i_unnamed_c_compstr0_shift_x(BITSELECT,18529)@129
    assign rightShiftStage0Idx1Rng1_uid18530_dupName_231_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_q[33:1];

    // rightShiftStage0Idx1_uid18532_dupName_231_i_unnamed_c_compstr0_shift_x(BITJOIN,18531)@129
    assign rightShiftStage0Idx1_uid18532_dupName_231_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18530_dupName_231_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24321_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x(BITSELECT,24320)@128
    assign leftShiftStage2Idx1Rng8_uid24321_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_in = leftShiftStage1_uid24319_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24321_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24321_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24322_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x(BITJOIN,24321)@128
    assign leftShiftStage2Idx1_uid24322_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24321_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24316_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x(BITSELECT,24315)@128
    assign leftShiftStage1Idx1Rng4_uid24316_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_in = leftShiftStage0_uid24314_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24316_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24316_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24317_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x(BITJOIN,24316)@128
    assign leftShiftStage1Idx1_uid24317_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24316_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24311_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x(BITSELECT,24310)@128
    assign leftShiftStage0Idx1Rng1_uid24311_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_58_c_compstr1642_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24311_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24311_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24312_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x(BITJOIN,24311)@128
    assign leftShiftStage0Idx1_uid24312_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24311_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18478_dupName_227_i_unnamed_c_compstr0_shift_x(BITSELECT,18477)@127
    assign rightShiftStage2Idx1Rng8_uid18478_dupName_227_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18477_dupName_227_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18480_dupName_227_i_unnamed_c_compstr0_shift_x(BITJOIN,18479)@127
    assign rightShiftStage2Idx1_uid18480_dupName_227_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18478_dupName_227_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18473_dupName_227_i_unnamed_c_compstr0_shift_x(BITSELECT,18472)@127
    assign rightShiftStage1Idx1Rng4_uid18473_dupName_227_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18472_dupName_227_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18475_dupName_227_i_unnamed_c_compstr0_shift_x(BITJOIN,18474)@127
    assign rightShiftStage1Idx1_uid18475_dupName_227_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18473_dupName_227_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18468_dupName_227_i_unnamed_c_compstr0_shift_x(BITSELECT,18467)@127
    assign rightShiftStage0Idx1Rng1_uid18468_dupName_227_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_q[33:1];

    // rightShiftStage0Idx1_uid18470_dupName_227_i_unnamed_c_compstr0_shift_x(BITJOIN,18469)@127
    assign rightShiftStage0Idx1_uid18470_dupName_227_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18468_dupName_227_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24303_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x(BITSELECT,24302)@126
    assign leftShiftStage2Idx1Rng8_uid24303_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_in = leftShiftStage1_uid24301_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24303_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24303_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24304_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x(BITJOIN,24303)@126
    assign leftShiftStage2Idx1_uid24304_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24303_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24298_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x(BITSELECT,24297)@126
    assign leftShiftStage1Idx1Rng4_uid24298_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_in = leftShiftStage0_uid24296_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24298_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24298_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24299_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x(BITJOIN,24298)@126
    assign leftShiftStage1Idx1_uid24299_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24298_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24293_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x(BITSELECT,24292)@126
    assign leftShiftStage0Idx1Rng1_uid24293_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_57_c_compstr1614_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24293_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24293_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24294_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x(BITJOIN,24293)@126
    assign leftShiftStage0Idx1_uid24294_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24293_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18416_dupName_223_i_unnamed_c_compstr0_shift_x(BITSELECT,18415)@125
    assign rightShiftStage2Idx1Rng8_uid18416_dupName_223_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18415_dupName_223_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18418_dupName_223_i_unnamed_c_compstr0_shift_x(BITJOIN,18417)@125
    assign rightShiftStage2Idx1_uid18418_dupName_223_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18416_dupName_223_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18411_dupName_223_i_unnamed_c_compstr0_shift_x(BITSELECT,18410)@125
    assign rightShiftStage1Idx1Rng4_uid18411_dupName_223_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18410_dupName_223_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18413_dupName_223_i_unnamed_c_compstr0_shift_x(BITJOIN,18412)@125
    assign rightShiftStage1Idx1_uid18413_dupName_223_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18411_dupName_223_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18406_dupName_223_i_unnamed_c_compstr0_shift_x(BITSELECT,18405)@125
    assign rightShiftStage0Idx1Rng1_uid18406_dupName_223_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_q[33:1];

    // rightShiftStage0Idx1_uid18408_dupName_223_i_unnamed_c_compstr0_shift_x(BITJOIN,18407)@125
    assign rightShiftStage0Idx1_uid18408_dupName_223_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18406_dupName_223_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24285_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x(BITSELECT,24284)@124
    assign leftShiftStage2Idx1Rng8_uid24285_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_in = leftShiftStage1_uid24283_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24285_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24285_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24286_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x(BITJOIN,24285)@124
    assign leftShiftStage2Idx1_uid24286_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24285_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24280_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x(BITSELECT,24279)@124
    assign leftShiftStage1Idx1Rng4_uid24280_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_in = leftShiftStage0_uid24278_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24280_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24280_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24281_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x(BITJOIN,24280)@124
    assign leftShiftStage1Idx1_uid24281_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24280_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24275_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x(BITSELECT,24274)@124
    assign leftShiftStage0Idx1Rng1_uid24275_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_56_c_compstr1586_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24275_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24275_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24276_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x(BITJOIN,24275)@124
    assign leftShiftStage0Idx1_uid24276_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24275_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18354_dupName_219_i_unnamed_c_compstr0_shift_x(BITSELECT,18353)@123
    assign rightShiftStage2Idx1Rng8_uid18354_dupName_219_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18353_dupName_219_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18356_dupName_219_i_unnamed_c_compstr0_shift_x(BITJOIN,18355)@123
    assign rightShiftStage2Idx1_uid18356_dupName_219_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18354_dupName_219_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18349_dupName_219_i_unnamed_c_compstr0_shift_x(BITSELECT,18348)@123
    assign rightShiftStage1Idx1Rng4_uid18349_dupName_219_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18348_dupName_219_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18351_dupName_219_i_unnamed_c_compstr0_shift_x(BITJOIN,18350)@123
    assign rightShiftStage1Idx1_uid18351_dupName_219_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18349_dupName_219_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18344_dupName_219_i_unnamed_c_compstr0_shift_x(BITSELECT,18343)@123
    assign rightShiftStage0Idx1Rng1_uid18344_dupName_219_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_q[33:1];

    // rightShiftStage0Idx1_uid18346_dupName_219_i_unnamed_c_compstr0_shift_x(BITJOIN,18345)@123
    assign rightShiftStage0Idx1_uid18346_dupName_219_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18344_dupName_219_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24267_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x(BITSELECT,24266)@122
    assign leftShiftStage2Idx1Rng8_uid24267_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_in = leftShiftStage1_uid24265_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24267_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24267_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24268_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x(BITJOIN,24267)@122
    assign leftShiftStage2Idx1_uid24268_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24267_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24262_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x(BITSELECT,24261)@122
    assign leftShiftStage1Idx1Rng4_uid24262_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_in = leftShiftStage0_uid24260_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24262_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24262_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24263_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x(BITJOIN,24262)@122
    assign leftShiftStage1Idx1_uid24263_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24262_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24257_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x(BITSELECT,24256)@122
    assign leftShiftStage0Idx1Rng1_uid24257_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_55_c_compstr1558_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24257_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24257_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24258_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x(BITJOIN,24257)@122
    assign leftShiftStage0Idx1_uid24258_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24257_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18292_dupName_215_i_unnamed_c_compstr0_shift_x(BITSELECT,18291)@121
    assign rightShiftStage2Idx1Rng8_uid18292_dupName_215_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18291_dupName_215_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18294_dupName_215_i_unnamed_c_compstr0_shift_x(BITJOIN,18293)@121
    assign rightShiftStage2Idx1_uid18294_dupName_215_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18292_dupName_215_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18287_dupName_215_i_unnamed_c_compstr0_shift_x(BITSELECT,18286)@121
    assign rightShiftStage1Idx1Rng4_uid18287_dupName_215_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18286_dupName_215_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18289_dupName_215_i_unnamed_c_compstr0_shift_x(BITJOIN,18288)@121
    assign rightShiftStage1Idx1_uid18289_dupName_215_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18287_dupName_215_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18282_dupName_215_i_unnamed_c_compstr0_shift_x(BITSELECT,18281)@121
    assign rightShiftStage0Idx1Rng1_uid18282_dupName_215_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_q[33:1];

    // rightShiftStage0Idx1_uid18284_dupName_215_i_unnamed_c_compstr0_shift_x(BITJOIN,18283)@121
    assign rightShiftStage0Idx1_uid18284_dupName_215_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18282_dupName_215_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24249_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x(BITSELECT,24248)@120
    assign leftShiftStage2Idx1Rng8_uid24249_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_in = leftShiftStage1_uid24247_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24249_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24249_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24250_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x(BITJOIN,24249)@120
    assign leftShiftStage2Idx1_uid24250_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24249_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24244_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x(BITSELECT,24243)@120
    assign leftShiftStage1Idx1Rng4_uid24244_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_in = leftShiftStage0_uid24242_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24244_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24244_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24245_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x(BITJOIN,24244)@120
    assign leftShiftStage1Idx1_uid24245_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24244_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24239_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x(BITSELECT,24238)@120
    assign leftShiftStage0Idx1Rng1_uid24239_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_54_c_compstr1530_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24239_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24239_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24240_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x(BITJOIN,24239)@120
    assign leftShiftStage0Idx1_uid24240_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24239_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18230_dupName_211_i_unnamed_c_compstr0_shift_x(BITSELECT,18229)@119
    assign rightShiftStage2Idx1Rng8_uid18230_dupName_211_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18229_dupName_211_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18232_dupName_211_i_unnamed_c_compstr0_shift_x(BITJOIN,18231)@119
    assign rightShiftStage2Idx1_uid18232_dupName_211_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18230_dupName_211_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18225_dupName_211_i_unnamed_c_compstr0_shift_x(BITSELECT,18224)@119
    assign rightShiftStage1Idx1Rng4_uid18225_dupName_211_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18224_dupName_211_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18227_dupName_211_i_unnamed_c_compstr0_shift_x(BITJOIN,18226)@119
    assign rightShiftStage1Idx1_uid18227_dupName_211_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18225_dupName_211_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18220_dupName_211_i_unnamed_c_compstr0_shift_x(BITSELECT,18219)@119
    assign rightShiftStage0Idx1Rng1_uid18220_dupName_211_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_q[33:1];

    // rightShiftStage0Idx1_uid18222_dupName_211_i_unnamed_c_compstr0_shift_x(BITJOIN,18221)@119
    assign rightShiftStage0Idx1_uid18222_dupName_211_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18220_dupName_211_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24231_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x(BITSELECT,24230)@118
    assign leftShiftStage2Idx1Rng8_uid24231_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_in = leftShiftStage1_uid24229_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24231_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24231_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24232_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x(BITJOIN,24231)@118
    assign leftShiftStage2Idx1_uid24232_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24231_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24226_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x(BITSELECT,24225)@118
    assign leftShiftStage1Idx1Rng4_uid24226_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_in = leftShiftStage0_uid24224_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24226_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24226_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24227_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x(BITJOIN,24226)@118
    assign leftShiftStage1Idx1_uid24227_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24226_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24221_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x(BITSELECT,24220)@118
    assign leftShiftStage0Idx1Rng1_uid24221_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_53_c_compstr1502_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24221_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24221_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24222_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x(BITJOIN,24221)@118
    assign leftShiftStage0Idx1_uid24222_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24221_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18168_dupName_207_i_unnamed_c_compstr0_shift_x(BITSELECT,18167)@117
    assign rightShiftStage2Idx1Rng8_uid18168_dupName_207_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18167_dupName_207_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18170_dupName_207_i_unnamed_c_compstr0_shift_x(BITJOIN,18169)@117
    assign rightShiftStage2Idx1_uid18170_dupName_207_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18168_dupName_207_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18163_dupName_207_i_unnamed_c_compstr0_shift_x(BITSELECT,18162)@117
    assign rightShiftStage1Idx1Rng4_uid18163_dupName_207_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18162_dupName_207_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18165_dupName_207_i_unnamed_c_compstr0_shift_x(BITJOIN,18164)@117
    assign rightShiftStage1Idx1_uid18165_dupName_207_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18163_dupName_207_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18158_dupName_207_i_unnamed_c_compstr0_shift_x(BITSELECT,18157)@117
    assign rightShiftStage0Idx1Rng1_uid18158_dupName_207_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_q[33:1];

    // rightShiftStage0Idx1_uid18160_dupName_207_i_unnamed_c_compstr0_shift_x(BITJOIN,18159)@117
    assign rightShiftStage0Idx1_uid18160_dupName_207_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18158_dupName_207_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24213_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x(BITSELECT,24212)@116
    assign leftShiftStage2Idx1Rng8_uid24213_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_in = leftShiftStage1_uid24211_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24213_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24213_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24214_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x(BITJOIN,24213)@116
    assign leftShiftStage2Idx1_uid24214_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24213_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24208_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x(BITSELECT,24207)@116
    assign leftShiftStage1Idx1Rng4_uid24208_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_in = leftShiftStage0_uid24206_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24208_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24208_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24209_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x(BITJOIN,24208)@116
    assign leftShiftStage1Idx1_uid24209_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24208_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24203_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x(BITSELECT,24202)@116
    assign leftShiftStage0Idx1Rng1_uid24203_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_52_c_compstr1474_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24203_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24203_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24204_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x(BITJOIN,24203)@116
    assign leftShiftStage0Idx1_uid24204_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24203_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18106_dupName_203_i_unnamed_c_compstr0_shift_x(BITSELECT,18105)@115
    assign rightShiftStage2Idx1Rng8_uid18106_dupName_203_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18105_dupName_203_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18108_dupName_203_i_unnamed_c_compstr0_shift_x(BITJOIN,18107)@115
    assign rightShiftStage2Idx1_uid18108_dupName_203_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18106_dupName_203_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18101_dupName_203_i_unnamed_c_compstr0_shift_x(BITSELECT,18100)@115
    assign rightShiftStage1Idx1Rng4_uid18101_dupName_203_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18100_dupName_203_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18103_dupName_203_i_unnamed_c_compstr0_shift_x(BITJOIN,18102)@115
    assign rightShiftStage1Idx1_uid18103_dupName_203_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18101_dupName_203_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18096_dupName_203_i_unnamed_c_compstr0_shift_x(BITSELECT,18095)@115
    assign rightShiftStage0Idx1Rng1_uid18096_dupName_203_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_q[33:1];

    // rightShiftStage0Idx1_uid18098_dupName_203_i_unnamed_c_compstr0_shift_x(BITJOIN,18097)@115
    assign rightShiftStage0Idx1_uid18098_dupName_203_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18096_dupName_203_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24195_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x(BITSELECT,24194)@114
    assign leftShiftStage2Idx1Rng8_uid24195_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_in = leftShiftStage1_uid24193_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24195_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24195_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24196_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x(BITJOIN,24195)@114
    assign leftShiftStage2Idx1_uid24196_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24195_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24190_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x(BITSELECT,24189)@114
    assign leftShiftStage1Idx1Rng4_uid24190_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_in = leftShiftStage0_uid24188_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24190_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24190_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24191_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x(BITJOIN,24190)@114
    assign leftShiftStage1Idx1_uid24191_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24190_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24185_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x(BITSELECT,24184)@114
    assign leftShiftStage0Idx1Rng1_uid24185_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_51_c_compstr1446_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24185_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24185_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24186_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x(BITJOIN,24185)@114
    assign leftShiftStage0Idx1_uid24186_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24185_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18044_dupName_199_i_unnamed_c_compstr0_shift_x(BITSELECT,18043)@113
    assign rightShiftStage2Idx1Rng8_uid18044_dupName_199_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid18043_dupName_199_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18046_dupName_199_i_unnamed_c_compstr0_shift_x(BITJOIN,18045)@113
    assign rightShiftStage2Idx1_uid18046_dupName_199_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid18044_dupName_199_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18039_dupName_199_i_unnamed_c_compstr0_shift_x(BITSELECT,18038)@113
    assign rightShiftStage1Idx1Rng4_uid18039_dupName_199_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18038_dupName_199_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18041_dupName_199_i_unnamed_c_compstr0_shift_x(BITJOIN,18040)@113
    assign rightShiftStage1Idx1_uid18041_dupName_199_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid18039_dupName_199_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18034_dupName_199_i_unnamed_c_compstr0_shift_x(BITSELECT,18033)@113
    assign rightShiftStage0Idx1Rng1_uid18034_dupName_199_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_q[33:1];

    // rightShiftStage0Idx1_uid18036_dupName_199_i_unnamed_c_compstr0_shift_x(BITJOIN,18035)@113
    assign rightShiftStage0Idx1_uid18036_dupName_199_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18034_dupName_199_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24177_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x(BITSELECT,24176)@112
    assign leftShiftStage2Idx1Rng8_uid24177_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_in = leftShiftStage1_uid24175_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24177_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24177_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24178_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x(BITJOIN,24177)@112
    assign leftShiftStage2Idx1_uid24178_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24177_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24172_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x(BITSELECT,24171)@112
    assign leftShiftStage1Idx1Rng4_uid24172_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_in = leftShiftStage0_uid24170_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24172_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24172_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24173_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x(BITJOIN,24172)@112
    assign leftShiftStage1Idx1_uid24173_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24172_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24167_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x(BITSELECT,24166)@112
    assign leftShiftStage0Idx1Rng1_uid24167_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_50_c_compstr1418_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24167_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24167_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24168_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x(BITJOIN,24167)@112
    assign leftShiftStage0Idx1_uid24168_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24167_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17982_dupName_195_i_unnamed_c_compstr0_shift_x(BITSELECT,17981)@111
    assign rightShiftStage2Idx1Rng8_uid17982_dupName_195_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17981_dupName_195_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17984_dupName_195_i_unnamed_c_compstr0_shift_x(BITJOIN,17983)@111
    assign rightShiftStage2Idx1_uid17984_dupName_195_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17982_dupName_195_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17977_dupName_195_i_unnamed_c_compstr0_shift_x(BITSELECT,17976)@111
    assign rightShiftStage1Idx1Rng4_uid17977_dupName_195_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17976_dupName_195_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17979_dupName_195_i_unnamed_c_compstr0_shift_x(BITJOIN,17978)@111
    assign rightShiftStage1Idx1_uid17979_dupName_195_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17977_dupName_195_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17972_dupName_195_i_unnamed_c_compstr0_shift_x(BITSELECT,17971)@111
    assign rightShiftStage0Idx1Rng1_uid17972_dupName_195_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_q[33:1];

    // rightShiftStage0Idx1_uid17974_dupName_195_i_unnamed_c_compstr0_shift_x(BITJOIN,17973)@111
    assign rightShiftStage0Idx1_uid17974_dupName_195_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17972_dupName_195_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24141_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x(BITSELECT,24140)@110
    assign leftShiftStage2Idx1Rng8_uid24141_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_in = leftShiftStage1_uid24139_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24141_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24141_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24142_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x(BITJOIN,24141)@110
    assign leftShiftStage2Idx1_uid24142_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24141_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24136_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x(BITSELECT,24135)@110
    assign leftShiftStage1Idx1Rng4_uid24136_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_in = leftShiftStage0_uid24134_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24136_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24136_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24137_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x(BITJOIN,24136)@110
    assign leftShiftStage1Idx1_uid24137_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24136_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24131_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x(BITSELECT,24130)@110
    assign leftShiftStage0Idx1Rng1_uid24131_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_49_c_compstr1390_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24131_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24131_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24132_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x(BITJOIN,24131)@110
    assign leftShiftStage0Idx1_uid24132_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24131_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17920_dupName_191_i_unnamed_c_compstr0_shift_x(BITSELECT,17919)@109
    assign rightShiftStage2Idx1Rng8_uid17920_dupName_191_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17919_dupName_191_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17922_dupName_191_i_unnamed_c_compstr0_shift_x(BITJOIN,17921)@109
    assign rightShiftStage2Idx1_uid17922_dupName_191_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17920_dupName_191_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17915_dupName_191_i_unnamed_c_compstr0_shift_x(BITSELECT,17914)@109
    assign rightShiftStage1Idx1Rng4_uid17915_dupName_191_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17914_dupName_191_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17917_dupName_191_i_unnamed_c_compstr0_shift_x(BITJOIN,17916)@109
    assign rightShiftStage1Idx1_uid17917_dupName_191_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17915_dupName_191_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17910_dupName_191_i_unnamed_c_compstr0_shift_x(BITSELECT,17909)@109
    assign rightShiftStage0Idx1Rng1_uid17910_dupName_191_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_q[33:1];

    // rightShiftStage0Idx1_uid17912_dupName_191_i_unnamed_c_compstr0_shift_x(BITJOIN,17911)@109
    assign rightShiftStage0Idx1_uid17912_dupName_191_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17910_dupName_191_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24123_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x(BITSELECT,24122)@108
    assign leftShiftStage2Idx1Rng8_uid24123_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_in = leftShiftStage1_uid24121_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24123_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24123_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24124_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x(BITJOIN,24123)@108
    assign leftShiftStage2Idx1_uid24124_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24123_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24118_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x(BITSELECT,24117)@108
    assign leftShiftStage1Idx1Rng4_uid24118_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_in = leftShiftStage0_uid24116_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24118_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24118_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24119_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x(BITJOIN,24118)@108
    assign leftShiftStage1Idx1_uid24119_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24118_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24113_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x(BITSELECT,24112)@108
    assign leftShiftStage0Idx1Rng1_uid24113_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_48_c_compstr1362_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24113_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24113_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24114_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x(BITJOIN,24113)@108
    assign leftShiftStage0Idx1_uid24114_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24113_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17858_dupName_187_i_unnamed_c_compstr0_shift_x(BITSELECT,17857)@107
    assign rightShiftStage2Idx1Rng8_uid17858_dupName_187_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17857_dupName_187_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17860_dupName_187_i_unnamed_c_compstr0_shift_x(BITJOIN,17859)@107
    assign rightShiftStage2Idx1_uid17860_dupName_187_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17858_dupName_187_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17853_dupName_187_i_unnamed_c_compstr0_shift_x(BITSELECT,17852)@107
    assign rightShiftStage1Idx1Rng4_uid17853_dupName_187_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17852_dupName_187_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17855_dupName_187_i_unnamed_c_compstr0_shift_x(BITJOIN,17854)@107
    assign rightShiftStage1Idx1_uid17855_dupName_187_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17853_dupName_187_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17848_dupName_187_i_unnamed_c_compstr0_shift_x(BITSELECT,17847)@107
    assign rightShiftStage0Idx1Rng1_uid17848_dupName_187_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_q[33:1];

    // rightShiftStage0Idx1_uid17850_dupName_187_i_unnamed_c_compstr0_shift_x(BITJOIN,17849)@107
    assign rightShiftStage0Idx1_uid17850_dupName_187_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17848_dupName_187_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24105_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x(BITSELECT,24104)@106
    assign leftShiftStage2Idx1Rng8_uid24105_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_in = leftShiftStage1_uid24103_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24105_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24105_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24106_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x(BITJOIN,24105)@106
    assign leftShiftStage2Idx1_uid24106_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24105_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24100_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x(BITSELECT,24099)@106
    assign leftShiftStage1Idx1Rng4_uid24100_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_in = leftShiftStage0_uid24098_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24100_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24100_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24101_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x(BITJOIN,24100)@106
    assign leftShiftStage1Idx1_uid24101_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24100_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24095_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x(BITSELECT,24094)@106
    assign leftShiftStage0Idx1Rng1_uid24095_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_47_c_compstr1334_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24095_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24095_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24096_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x(BITJOIN,24095)@106
    assign leftShiftStage0Idx1_uid24096_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24095_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17796_dupName_183_i_unnamed_c_compstr0_shift_x(BITSELECT,17795)@105
    assign rightShiftStage2Idx1Rng8_uid17796_dupName_183_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17795_dupName_183_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17798_dupName_183_i_unnamed_c_compstr0_shift_x(BITJOIN,17797)@105
    assign rightShiftStage2Idx1_uid17798_dupName_183_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17796_dupName_183_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17791_dupName_183_i_unnamed_c_compstr0_shift_x(BITSELECT,17790)@105
    assign rightShiftStage1Idx1Rng4_uid17791_dupName_183_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17790_dupName_183_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17793_dupName_183_i_unnamed_c_compstr0_shift_x(BITJOIN,17792)@105
    assign rightShiftStage1Idx1_uid17793_dupName_183_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17791_dupName_183_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17786_dupName_183_i_unnamed_c_compstr0_shift_x(BITSELECT,17785)@105
    assign rightShiftStage0Idx1Rng1_uid17786_dupName_183_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_q[33:1];

    // rightShiftStage0Idx1_uid17788_dupName_183_i_unnamed_c_compstr0_shift_x(BITJOIN,17787)@105
    assign rightShiftStage0Idx1_uid17788_dupName_183_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17786_dupName_183_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24087_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x(BITSELECT,24086)@104
    assign leftShiftStage2Idx1Rng8_uid24087_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_in = leftShiftStage1_uid24085_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24087_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24087_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24088_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x(BITJOIN,24087)@104
    assign leftShiftStage2Idx1_uid24088_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24087_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24082_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x(BITSELECT,24081)@104
    assign leftShiftStage1Idx1Rng4_uid24082_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_in = leftShiftStage0_uid24080_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24082_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24082_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24083_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x(BITJOIN,24082)@104
    assign leftShiftStage1Idx1_uid24083_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24082_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24077_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x(BITSELECT,24076)@104
    assign leftShiftStage0Idx1Rng1_uid24077_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_46_c_compstr1306_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24077_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24077_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24078_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x(BITJOIN,24077)@104
    assign leftShiftStage0Idx1_uid24078_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24077_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17734_dupName_179_i_unnamed_c_compstr0_shift_x(BITSELECT,17733)@103
    assign rightShiftStage2Idx1Rng8_uid17734_dupName_179_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17733_dupName_179_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17736_dupName_179_i_unnamed_c_compstr0_shift_x(BITJOIN,17735)@103
    assign rightShiftStage2Idx1_uid17736_dupName_179_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17734_dupName_179_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17729_dupName_179_i_unnamed_c_compstr0_shift_x(BITSELECT,17728)@103
    assign rightShiftStage1Idx1Rng4_uid17729_dupName_179_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17728_dupName_179_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17731_dupName_179_i_unnamed_c_compstr0_shift_x(BITJOIN,17730)@103
    assign rightShiftStage1Idx1_uid17731_dupName_179_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17729_dupName_179_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17724_dupName_179_i_unnamed_c_compstr0_shift_x(BITSELECT,17723)@103
    assign rightShiftStage0Idx1Rng1_uid17724_dupName_179_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_q[33:1];

    // rightShiftStage0Idx1_uid17726_dupName_179_i_unnamed_c_compstr0_shift_x(BITJOIN,17725)@103
    assign rightShiftStage0Idx1_uid17726_dupName_179_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17724_dupName_179_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24069_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x(BITSELECT,24068)@102
    assign leftShiftStage2Idx1Rng8_uid24069_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_in = leftShiftStage1_uid24067_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24069_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24069_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24070_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x(BITJOIN,24069)@102
    assign leftShiftStage2Idx1_uid24070_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24069_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24064_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x(BITSELECT,24063)@102
    assign leftShiftStage1Idx1Rng4_uid24064_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_in = leftShiftStage0_uid24062_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24064_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24064_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24065_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x(BITJOIN,24064)@102
    assign leftShiftStage1Idx1_uid24065_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24064_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24059_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x(BITSELECT,24058)@102
    assign leftShiftStage0Idx1Rng1_uid24059_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_45_c_compstr1278_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24059_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24059_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24060_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x(BITJOIN,24059)@102
    assign leftShiftStage0Idx1_uid24060_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24059_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17672_dupName_175_i_unnamed_c_compstr0_shift_x(BITSELECT,17671)@101
    assign rightShiftStage2Idx1Rng8_uid17672_dupName_175_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17671_dupName_175_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17674_dupName_175_i_unnamed_c_compstr0_shift_x(BITJOIN,17673)@101
    assign rightShiftStage2Idx1_uid17674_dupName_175_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17672_dupName_175_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17667_dupName_175_i_unnamed_c_compstr0_shift_x(BITSELECT,17666)@101
    assign rightShiftStage1Idx1Rng4_uid17667_dupName_175_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17666_dupName_175_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17669_dupName_175_i_unnamed_c_compstr0_shift_x(BITJOIN,17668)@101
    assign rightShiftStage1Idx1_uid17669_dupName_175_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17667_dupName_175_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17662_dupName_175_i_unnamed_c_compstr0_shift_x(BITSELECT,17661)@101
    assign rightShiftStage0Idx1Rng1_uid17662_dupName_175_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_q[33:1];

    // rightShiftStage0Idx1_uid17664_dupName_175_i_unnamed_c_compstr0_shift_x(BITJOIN,17663)@101
    assign rightShiftStage0Idx1_uid17664_dupName_175_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17662_dupName_175_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24051_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x(BITSELECT,24050)@100
    assign leftShiftStage2Idx1Rng8_uid24051_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_in = leftShiftStage1_uid24049_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24051_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24051_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24052_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x(BITJOIN,24051)@100
    assign leftShiftStage2Idx1_uid24052_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24051_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24046_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x(BITSELECT,24045)@100
    assign leftShiftStage1Idx1Rng4_uid24046_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_in = leftShiftStage0_uid24044_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24046_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24046_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24047_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x(BITJOIN,24046)@100
    assign leftShiftStage1Idx1_uid24047_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24046_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24041_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x(BITSELECT,24040)@100
    assign leftShiftStage0Idx1Rng1_uid24041_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_44_c_compstr1250_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24041_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24041_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24042_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x(BITJOIN,24041)@100
    assign leftShiftStage0Idx1_uid24042_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24041_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17610_dupName_171_i_unnamed_c_compstr0_shift_x(BITSELECT,17609)@99
    assign rightShiftStage2Idx1Rng8_uid17610_dupName_171_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17609_dupName_171_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17612_dupName_171_i_unnamed_c_compstr0_shift_x(BITJOIN,17611)@99
    assign rightShiftStage2Idx1_uid17612_dupName_171_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17610_dupName_171_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17605_dupName_171_i_unnamed_c_compstr0_shift_x(BITSELECT,17604)@99
    assign rightShiftStage1Idx1Rng4_uid17605_dupName_171_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17604_dupName_171_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17607_dupName_171_i_unnamed_c_compstr0_shift_x(BITJOIN,17606)@99
    assign rightShiftStage1Idx1_uid17607_dupName_171_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17605_dupName_171_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17600_dupName_171_i_unnamed_c_compstr0_shift_x(BITSELECT,17599)@99
    assign rightShiftStage0Idx1Rng1_uid17600_dupName_171_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_q[33:1];

    // rightShiftStage0Idx1_uid17602_dupName_171_i_unnamed_c_compstr0_shift_x(BITJOIN,17601)@99
    assign rightShiftStage0Idx1_uid17602_dupName_171_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17600_dupName_171_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24033_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x(BITSELECT,24032)@98
    assign leftShiftStage2Idx1Rng8_uid24033_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_in = leftShiftStage1_uid24031_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24033_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24033_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24034_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x(BITJOIN,24033)@98
    assign leftShiftStage2Idx1_uid24034_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24033_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24028_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x(BITSELECT,24027)@98
    assign leftShiftStage1Idx1Rng4_uid24028_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_in = leftShiftStage0_uid24026_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24028_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24028_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24029_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x(BITJOIN,24028)@98
    assign leftShiftStage1Idx1_uid24029_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24028_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24023_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x(BITSELECT,24022)@98
    assign leftShiftStage0Idx1Rng1_uid24023_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_43_c_compstr1222_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24023_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24023_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24024_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x(BITJOIN,24023)@98
    assign leftShiftStage0Idx1_uid24024_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24023_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17548_dupName_167_i_unnamed_c_compstr0_shift_x(BITSELECT,17547)@97
    assign rightShiftStage2Idx1Rng8_uid17548_dupName_167_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17547_dupName_167_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17550_dupName_167_i_unnamed_c_compstr0_shift_x(BITJOIN,17549)@97
    assign rightShiftStage2Idx1_uid17550_dupName_167_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17548_dupName_167_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17543_dupName_167_i_unnamed_c_compstr0_shift_x(BITSELECT,17542)@97
    assign rightShiftStage1Idx1Rng4_uid17543_dupName_167_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17542_dupName_167_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17545_dupName_167_i_unnamed_c_compstr0_shift_x(BITJOIN,17544)@97
    assign rightShiftStage1Idx1_uid17545_dupName_167_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17543_dupName_167_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17538_dupName_167_i_unnamed_c_compstr0_shift_x(BITSELECT,17537)@97
    assign rightShiftStage0Idx1Rng1_uid17538_dupName_167_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_q[33:1];

    // rightShiftStage0Idx1_uid17540_dupName_167_i_unnamed_c_compstr0_shift_x(BITJOIN,17539)@97
    assign rightShiftStage0Idx1_uid17540_dupName_167_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17538_dupName_167_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24015_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x(BITSELECT,24014)@96
    assign leftShiftStage2Idx1Rng8_uid24015_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_in = leftShiftStage1_uid24013_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24015_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24015_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24016_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x(BITJOIN,24015)@96
    assign leftShiftStage2Idx1_uid24016_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24015_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24010_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x(BITSELECT,24009)@96
    assign leftShiftStage1Idx1Rng4_uid24010_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_in = leftShiftStage0_uid24008_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24010_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24010_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24011_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x(BITJOIN,24010)@96
    assign leftShiftStage1Idx1_uid24011_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24010_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24005_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x(BITSELECT,24004)@96
    assign leftShiftStage0Idx1Rng1_uid24005_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_42_c_compstr1194_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24005_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24005_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24006_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x(BITJOIN,24005)@96
    assign leftShiftStage0Idx1_uid24006_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24005_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17486_dupName_163_i_unnamed_c_compstr0_shift_x(BITSELECT,17485)@95
    assign rightShiftStage2Idx1Rng8_uid17486_dupName_163_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17485_dupName_163_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17488_dupName_163_i_unnamed_c_compstr0_shift_x(BITJOIN,17487)@95
    assign rightShiftStage2Idx1_uid17488_dupName_163_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17486_dupName_163_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17481_dupName_163_i_unnamed_c_compstr0_shift_x(BITSELECT,17480)@95
    assign rightShiftStage1Idx1Rng4_uid17481_dupName_163_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17480_dupName_163_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17483_dupName_163_i_unnamed_c_compstr0_shift_x(BITJOIN,17482)@95
    assign rightShiftStage1Idx1_uid17483_dupName_163_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17481_dupName_163_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17476_dupName_163_i_unnamed_c_compstr0_shift_x(BITSELECT,17475)@95
    assign rightShiftStage0Idx1Rng1_uid17476_dupName_163_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_q[33:1];

    // rightShiftStage0Idx1_uid17478_dupName_163_i_unnamed_c_compstr0_shift_x(BITJOIN,17477)@95
    assign rightShiftStage0Idx1_uid17478_dupName_163_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17476_dupName_163_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23997_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x(BITSELECT,23996)@94
    assign leftShiftStage2Idx1Rng8_uid23997_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_in = leftShiftStage1_uid23995_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23997_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23997_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23998_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x(BITJOIN,23997)@94
    assign leftShiftStage2Idx1_uid23998_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23997_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23992_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x(BITSELECT,23991)@94
    assign leftShiftStage1Idx1Rng4_uid23992_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_in = leftShiftStage0_uid23990_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23992_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23992_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23993_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x(BITJOIN,23992)@94
    assign leftShiftStage1Idx1_uid23993_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23992_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23987_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x(BITSELECT,23986)@94
    assign leftShiftStage0Idx1Rng1_uid23987_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_41_c_compstr1166_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23987_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23987_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23988_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x(BITJOIN,23987)@94
    assign leftShiftStage0Idx1_uid23988_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23987_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17424_dupName_159_i_unnamed_c_compstr0_shift_x(BITSELECT,17423)@93
    assign rightShiftStage2Idx1Rng8_uid17424_dupName_159_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17423_dupName_159_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17426_dupName_159_i_unnamed_c_compstr0_shift_x(BITJOIN,17425)@93
    assign rightShiftStage2Idx1_uid17426_dupName_159_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17424_dupName_159_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17419_dupName_159_i_unnamed_c_compstr0_shift_x(BITSELECT,17418)@93
    assign rightShiftStage1Idx1Rng4_uid17419_dupName_159_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17418_dupName_159_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17421_dupName_159_i_unnamed_c_compstr0_shift_x(BITJOIN,17420)@93
    assign rightShiftStage1Idx1_uid17421_dupName_159_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17419_dupName_159_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17414_dupName_159_i_unnamed_c_compstr0_shift_x(BITSELECT,17413)@93
    assign rightShiftStage0Idx1Rng1_uid17414_dupName_159_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_q[33:1];

    // rightShiftStage0Idx1_uid17416_dupName_159_i_unnamed_c_compstr0_shift_x(BITJOIN,17415)@93
    assign rightShiftStage0Idx1_uid17416_dupName_159_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17414_dupName_159_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23979_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x(BITSELECT,23978)@92
    assign leftShiftStage2Idx1Rng8_uid23979_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_in = leftShiftStage1_uid23977_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23979_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23979_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23980_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x(BITJOIN,23979)@92
    assign leftShiftStage2Idx1_uid23980_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23979_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23974_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x(BITSELECT,23973)@92
    assign leftShiftStage1Idx1Rng4_uid23974_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_in = leftShiftStage0_uid23972_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23974_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23974_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23975_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x(BITJOIN,23974)@92
    assign leftShiftStage1Idx1_uid23975_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23974_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23969_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x(BITSELECT,23968)@92
    assign leftShiftStage0Idx1Rng1_uid23969_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_40_c_compstr1138_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23969_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23969_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23970_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x(BITJOIN,23969)@92
    assign leftShiftStage0Idx1_uid23970_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23969_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17362_dupName_155_i_unnamed_c_compstr0_shift_x(BITSELECT,17361)@91
    assign rightShiftStage2Idx1Rng8_uid17362_dupName_155_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17361_dupName_155_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17364_dupName_155_i_unnamed_c_compstr0_shift_x(BITJOIN,17363)@91
    assign rightShiftStage2Idx1_uid17364_dupName_155_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17362_dupName_155_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17357_dupName_155_i_unnamed_c_compstr0_shift_x(BITSELECT,17356)@91
    assign rightShiftStage1Idx1Rng4_uid17357_dupName_155_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17356_dupName_155_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17359_dupName_155_i_unnamed_c_compstr0_shift_x(BITJOIN,17358)@91
    assign rightShiftStage1Idx1_uid17359_dupName_155_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17357_dupName_155_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17352_dupName_155_i_unnamed_c_compstr0_shift_x(BITSELECT,17351)@91
    assign rightShiftStage0Idx1Rng1_uid17352_dupName_155_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_q[33:1];

    // rightShiftStage0Idx1_uid17354_dupName_155_i_unnamed_c_compstr0_shift_x(BITJOIN,17353)@91
    assign rightShiftStage0Idx1_uid17354_dupName_155_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17352_dupName_155_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23943_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x(BITSELECT,23942)@90
    assign leftShiftStage2Idx1Rng8_uid23943_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_in = leftShiftStage1_uid23941_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23943_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23943_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23944_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x(BITJOIN,23943)@90
    assign leftShiftStage2Idx1_uid23944_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23943_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23938_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x(BITSELECT,23937)@90
    assign leftShiftStage1Idx1Rng4_uid23938_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_in = leftShiftStage0_uid23936_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23938_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23938_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23939_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x(BITJOIN,23938)@90
    assign leftShiftStage1Idx1_uid23939_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23938_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23933_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x(BITSELECT,23932)@90
    assign leftShiftStage0Idx1Rng1_uid23933_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_39_c_compstr1110_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23933_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23933_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23934_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x(BITJOIN,23933)@90
    assign leftShiftStage0Idx1_uid23934_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23933_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17300_dupName_151_i_unnamed_c_compstr0_shift_x(BITSELECT,17299)@89
    assign rightShiftStage2Idx1Rng8_uid17300_dupName_151_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17299_dupName_151_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17302_dupName_151_i_unnamed_c_compstr0_shift_x(BITJOIN,17301)@89
    assign rightShiftStage2Idx1_uid17302_dupName_151_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17300_dupName_151_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17295_dupName_151_i_unnamed_c_compstr0_shift_x(BITSELECT,17294)@89
    assign rightShiftStage1Idx1Rng4_uid17295_dupName_151_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17294_dupName_151_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17297_dupName_151_i_unnamed_c_compstr0_shift_x(BITJOIN,17296)@89
    assign rightShiftStage1Idx1_uid17297_dupName_151_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17295_dupName_151_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17290_dupName_151_i_unnamed_c_compstr0_shift_x(BITSELECT,17289)@89
    assign rightShiftStage0Idx1Rng1_uid17290_dupName_151_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_q[33:1];

    // rightShiftStage0Idx1_uid17292_dupName_151_i_unnamed_c_compstr0_shift_x(BITJOIN,17291)@89
    assign rightShiftStage0Idx1_uid17292_dupName_151_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17290_dupName_151_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23925_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x(BITSELECT,23924)@88
    assign leftShiftStage2Idx1Rng8_uid23925_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_in = leftShiftStage1_uid23923_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23925_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23925_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23926_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x(BITJOIN,23925)@88
    assign leftShiftStage2Idx1_uid23926_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23925_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23920_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x(BITSELECT,23919)@88
    assign leftShiftStage1Idx1Rng4_uid23920_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_in = leftShiftStage0_uid23918_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23920_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23920_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23921_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x(BITJOIN,23920)@88
    assign leftShiftStage1Idx1_uid23921_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23920_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23915_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x(BITSELECT,23914)@88
    assign leftShiftStage0Idx1Rng1_uid23915_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_38_c_compstr1082_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23915_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23915_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23916_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x(BITJOIN,23915)@88
    assign leftShiftStage0Idx1_uid23916_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23915_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17238_dupName_147_i_unnamed_c_compstr0_shift_x(BITSELECT,17237)@87
    assign rightShiftStage2Idx1Rng8_uid17238_dupName_147_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17237_dupName_147_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17240_dupName_147_i_unnamed_c_compstr0_shift_x(BITJOIN,17239)@87
    assign rightShiftStage2Idx1_uid17240_dupName_147_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17238_dupName_147_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17233_dupName_147_i_unnamed_c_compstr0_shift_x(BITSELECT,17232)@87
    assign rightShiftStage1Idx1Rng4_uid17233_dupName_147_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17232_dupName_147_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17235_dupName_147_i_unnamed_c_compstr0_shift_x(BITJOIN,17234)@87
    assign rightShiftStage1Idx1_uid17235_dupName_147_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17233_dupName_147_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17228_dupName_147_i_unnamed_c_compstr0_shift_x(BITSELECT,17227)@87
    assign rightShiftStage0Idx1Rng1_uid17228_dupName_147_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_q[33:1];

    // rightShiftStage0Idx1_uid17230_dupName_147_i_unnamed_c_compstr0_shift_x(BITJOIN,17229)@87
    assign rightShiftStage0Idx1_uid17230_dupName_147_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17228_dupName_147_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23907_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x(BITSELECT,23906)@86
    assign leftShiftStage2Idx1Rng8_uid23907_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_in = leftShiftStage1_uid23905_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23907_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23907_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23908_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x(BITJOIN,23907)@86
    assign leftShiftStage2Idx1_uid23908_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23907_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23902_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x(BITSELECT,23901)@86
    assign leftShiftStage1Idx1Rng4_uid23902_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_in = leftShiftStage0_uid23900_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23902_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23902_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23903_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x(BITJOIN,23902)@86
    assign leftShiftStage1Idx1_uid23903_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23902_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23897_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x(BITSELECT,23896)@86
    assign leftShiftStage0Idx1Rng1_uid23897_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_37_c_compstr1054_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23897_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23897_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23898_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x(BITJOIN,23897)@86
    assign leftShiftStage0Idx1_uid23898_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23897_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17176_dupName_143_i_unnamed_c_compstr0_shift_x(BITSELECT,17175)@85
    assign rightShiftStage2Idx1Rng8_uid17176_dupName_143_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17175_dupName_143_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17178_dupName_143_i_unnamed_c_compstr0_shift_x(BITJOIN,17177)@85
    assign rightShiftStage2Idx1_uid17178_dupName_143_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17176_dupName_143_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17171_dupName_143_i_unnamed_c_compstr0_shift_x(BITSELECT,17170)@85
    assign rightShiftStage1Idx1Rng4_uid17171_dupName_143_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17170_dupName_143_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17173_dupName_143_i_unnamed_c_compstr0_shift_x(BITJOIN,17172)@85
    assign rightShiftStage1Idx1_uid17173_dupName_143_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17171_dupName_143_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17166_dupName_143_i_unnamed_c_compstr0_shift_x(BITSELECT,17165)@85
    assign rightShiftStage0Idx1Rng1_uid17166_dupName_143_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_q[33:1];

    // rightShiftStage0Idx1_uid17168_dupName_143_i_unnamed_c_compstr0_shift_x(BITJOIN,17167)@85
    assign rightShiftStage0Idx1_uid17168_dupName_143_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17166_dupName_143_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23889_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x(BITSELECT,23888)@84
    assign leftShiftStage2Idx1Rng8_uid23889_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_in = leftShiftStage1_uid23887_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23889_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23889_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23890_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x(BITJOIN,23889)@84
    assign leftShiftStage2Idx1_uid23890_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23889_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23884_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x(BITSELECT,23883)@84
    assign leftShiftStage1Idx1Rng4_uid23884_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_in = leftShiftStage0_uid23882_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23884_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23884_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23885_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x(BITJOIN,23884)@84
    assign leftShiftStage1Idx1_uid23885_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23884_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23879_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x(BITSELECT,23878)@84
    assign leftShiftStage0Idx1Rng1_uid23879_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_36_c_compstr1026_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23879_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23879_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23880_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x(BITJOIN,23879)@84
    assign leftShiftStage0Idx1_uid23880_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23879_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17114_dupName_139_i_unnamed_c_compstr0_shift_x(BITSELECT,17113)@83
    assign rightShiftStage2Idx1Rng8_uid17114_dupName_139_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17113_dupName_139_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17116_dupName_139_i_unnamed_c_compstr0_shift_x(BITJOIN,17115)@83
    assign rightShiftStage2Idx1_uid17116_dupName_139_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17114_dupName_139_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17109_dupName_139_i_unnamed_c_compstr0_shift_x(BITSELECT,17108)@83
    assign rightShiftStage1Idx1Rng4_uid17109_dupName_139_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17108_dupName_139_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17111_dupName_139_i_unnamed_c_compstr0_shift_x(BITJOIN,17110)@83
    assign rightShiftStage1Idx1_uid17111_dupName_139_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17109_dupName_139_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17104_dupName_139_i_unnamed_c_compstr0_shift_x(BITSELECT,17103)@83
    assign rightShiftStage0Idx1Rng1_uid17104_dupName_139_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_q[33:1];

    // rightShiftStage0Idx1_uid17106_dupName_139_i_unnamed_c_compstr0_shift_x(BITJOIN,17105)@83
    assign rightShiftStage0Idx1_uid17106_dupName_139_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17104_dupName_139_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23871_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x(BITSELECT,23870)@82
    assign leftShiftStage2Idx1Rng8_uid23871_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_in = leftShiftStage1_uid23869_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23871_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23871_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23872_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x(BITJOIN,23871)@82
    assign leftShiftStage2Idx1_uid23872_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23871_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23866_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x(BITSELECT,23865)@82
    assign leftShiftStage1Idx1Rng4_uid23866_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_in = leftShiftStage0_uid23864_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23866_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23866_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23867_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x(BITJOIN,23866)@82
    assign leftShiftStage1Idx1_uid23867_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23866_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23861_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x(BITSELECT,23860)@82
    assign leftShiftStage0Idx1Rng1_uid23861_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_35_c_compstr998_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23861_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23861_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23862_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x(BITJOIN,23861)@82
    assign leftShiftStage0Idx1_uid23862_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23861_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17052_dupName_135_i_unnamed_c_compstr0_shift_x(BITSELECT,17051)@81
    assign rightShiftStage2Idx1Rng8_uid17052_dupName_135_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid17051_dupName_135_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17054_dupName_135_i_unnamed_c_compstr0_shift_x(BITJOIN,17053)@81
    assign rightShiftStage2Idx1_uid17054_dupName_135_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid17052_dupName_135_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17047_dupName_135_i_unnamed_c_compstr0_shift_x(BITSELECT,17046)@81
    assign rightShiftStage1Idx1Rng4_uid17047_dupName_135_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17046_dupName_135_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17049_dupName_135_i_unnamed_c_compstr0_shift_x(BITJOIN,17048)@81
    assign rightShiftStage1Idx1_uid17049_dupName_135_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid17047_dupName_135_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17042_dupName_135_i_unnamed_c_compstr0_shift_x(BITSELECT,17041)@81
    assign rightShiftStage0Idx1Rng1_uid17042_dupName_135_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_q[33:1];

    // rightShiftStage0Idx1_uid17044_dupName_135_i_unnamed_c_compstr0_shift_x(BITJOIN,17043)@81
    assign rightShiftStage0Idx1_uid17044_dupName_135_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17042_dupName_135_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23853_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x(BITSELECT,23852)@80
    assign leftShiftStage2Idx1Rng8_uid23853_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_in = leftShiftStage1_uid23851_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23853_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23853_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23854_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x(BITJOIN,23853)@80
    assign leftShiftStage2Idx1_uid23854_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23853_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23848_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x(BITSELECT,23847)@80
    assign leftShiftStage1Idx1Rng4_uid23848_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_in = leftShiftStage0_uid23846_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23848_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23848_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23849_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x(BITJOIN,23848)@80
    assign leftShiftStage1Idx1_uid23849_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23848_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23843_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x(BITSELECT,23842)@80
    assign leftShiftStage0Idx1Rng1_uid23843_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_34_c_compstr970_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23843_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23843_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23844_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x(BITJOIN,23843)@80
    assign leftShiftStage0Idx1_uid23844_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23843_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16990_dupName_131_i_unnamed_c_compstr0_shift_x(BITSELECT,16989)@79
    assign rightShiftStage2Idx1Rng8_uid16990_dupName_131_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16989_dupName_131_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16992_dupName_131_i_unnamed_c_compstr0_shift_x(BITJOIN,16991)@79
    assign rightShiftStage2Idx1_uid16992_dupName_131_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16990_dupName_131_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16985_dupName_131_i_unnamed_c_compstr0_shift_x(BITSELECT,16984)@79
    assign rightShiftStage1Idx1Rng4_uid16985_dupName_131_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16984_dupName_131_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16987_dupName_131_i_unnamed_c_compstr0_shift_x(BITJOIN,16986)@79
    assign rightShiftStage1Idx1_uid16987_dupName_131_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16985_dupName_131_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16980_dupName_131_i_unnamed_c_compstr0_shift_x(BITSELECT,16979)@79
    assign rightShiftStage0Idx1Rng1_uid16980_dupName_131_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_q[33:1];

    // rightShiftStage0Idx1_uid16982_dupName_131_i_unnamed_c_compstr0_shift_x(BITJOIN,16981)@79
    assign rightShiftStage0Idx1_uid16982_dupName_131_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16980_dupName_131_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23835_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x(BITSELECT,23834)@78
    assign leftShiftStage2Idx1Rng8_uid23835_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_in = leftShiftStage1_uid23833_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23835_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23835_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23836_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x(BITJOIN,23835)@78
    assign leftShiftStage2Idx1_uid23836_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23835_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23830_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x(BITSELECT,23829)@78
    assign leftShiftStage1Idx1Rng4_uid23830_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_in = leftShiftStage0_uid23828_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23830_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23830_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23831_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x(BITJOIN,23830)@78
    assign leftShiftStage1Idx1_uid23831_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23830_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23825_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x(BITSELECT,23824)@78
    assign leftShiftStage0Idx1Rng1_uid23825_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_33_c_compstr942_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23825_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23825_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23826_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x(BITJOIN,23825)@78
    assign leftShiftStage0Idx1_uid23826_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23825_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16928_dupName_127_i_unnamed_c_compstr0_shift_x(BITSELECT,16927)@77
    assign rightShiftStage2Idx1Rng8_uid16928_dupName_127_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16927_dupName_127_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16930_dupName_127_i_unnamed_c_compstr0_shift_x(BITJOIN,16929)@77
    assign rightShiftStage2Idx1_uid16930_dupName_127_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16928_dupName_127_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16923_dupName_127_i_unnamed_c_compstr0_shift_x(BITSELECT,16922)@77
    assign rightShiftStage1Idx1Rng4_uid16923_dupName_127_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16922_dupName_127_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16925_dupName_127_i_unnamed_c_compstr0_shift_x(BITJOIN,16924)@77
    assign rightShiftStage1Idx1_uid16925_dupName_127_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16923_dupName_127_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16918_dupName_127_i_unnamed_c_compstr0_shift_x(BITSELECT,16917)@77
    assign rightShiftStage0Idx1Rng1_uid16918_dupName_127_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_q[33:1];

    // rightShiftStage0Idx1_uid16920_dupName_127_i_unnamed_c_compstr0_shift_x(BITJOIN,16919)@77
    assign rightShiftStage0Idx1_uid16920_dupName_127_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16918_dupName_127_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23817_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x(BITSELECT,23816)@76
    assign leftShiftStage2Idx1Rng8_uid23817_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_in = leftShiftStage1_uid23815_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23817_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23817_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23818_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x(BITJOIN,23817)@76
    assign leftShiftStage2Idx1_uid23818_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23817_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23812_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x(BITSELECT,23811)@76
    assign leftShiftStage1Idx1Rng4_uid23812_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_in = leftShiftStage0_uid23810_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23812_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23812_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23813_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x(BITJOIN,23812)@76
    assign leftShiftStage1Idx1_uid23813_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23812_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23807_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x(BITSELECT,23806)@76
    assign leftShiftStage0Idx1Rng1_uid23807_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_32_c_compstr914_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23807_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23807_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23808_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x(BITJOIN,23807)@76
    assign leftShiftStage0Idx1_uid23808_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23807_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16866_dupName_123_i_unnamed_c_compstr0_shift_x(BITSELECT,16865)@75
    assign rightShiftStage2Idx1Rng8_uid16866_dupName_123_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16865_dupName_123_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16868_dupName_123_i_unnamed_c_compstr0_shift_x(BITJOIN,16867)@75
    assign rightShiftStage2Idx1_uid16868_dupName_123_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16866_dupName_123_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16861_dupName_123_i_unnamed_c_compstr0_shift_x(BITSELECT,16860)@75
    assign rightShiftStage1Idx1Rng4_uid16861_dupName_123_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16860_dupName_123_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16863_dupName_123_i_unnamed_c_compstr0_shift_x(BITJOIN,16862)@75
    assign rightShiftStage1Idx1_uid16863_dupName_123_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16861_dupName_123_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16856_dupName_123_i_unnamed_c_compstr0_shift_x(BITSELECT,16855)@75
    assign rightShiftStage0Idx1Rng1_uid16856_dupName_123_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_q[33:1];

    // rightShiftStage0Idx1_uid16858_dupName_123_i_unnamed_c_compstr0_shift_x(BITJOIN,16857)@75
    assign rightShiftStage0Idx1_uid16858_dupName_123_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16856_dupName_123_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23799_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x(BITSELECT,23798)@74
    assign leftShiftStage2Idx1Rng8_uid23799_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_in = leftShiftStage1_uid23797_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23799_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23799_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23800_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x(BITJOIN,23799)@74
    assign leftShiftStage2Idx1_uid23800_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23799_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23794_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x(BITSELECT,23793)@74
    assign leftShiftStage1Idx1Rng4_uid23794_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_in = leftShiftStage0_uid23792_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23794_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23794_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23795_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x(BITJOIN,23794)@74
    assign leftShiftStage1Idx1_uid23795_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23794_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23789_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x(BITSELECT,23788)@74
    assign leftShiftStage0Idx1Rng1_uid23789_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_31_c_compstr886_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23789_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23789_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23790_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x(BITJOIN,23789)@74
    assign leftShiftStage0Idx1_uid23790_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23789_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16804_dupName_119_i_unnamed_c_compstr0_shift_x(BITSELECT,16803)@73
    assign rightShiftStage2Idx1Rng8_uid16804_dupName_119_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16803_dupName_119_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16806_dupName_119_i_unnamed_c_compstr0_shift_x(BITJOIN,16805)@73
    assign rightShiftStage2Idx1_uid16806_dupName_119_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16804_dupName_119_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16799_dupName_119_i_unnamed_c_compstr0_shift_x(BITSELECT,16798)@73
    assign rightShiftStage1Idx1Rng4_uid16799_dupName_119_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16798_dupName_119_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16801_dupName_119_i_unnamed_c_compstr0_shift_x(BITJOIN,16800)@73
    assign rightShiftStage1Idx1_uid16801_dupName_119_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16799_dupName_119_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16794_dupName_119_i_unnamed_c_compstr0_shift_x(BITSELECT,16793)@73
    assign rightShiftStage0Idx1Rng1_uid16794_dupName_119_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_q[33:1];

    // rightShiftStage0Idx1_uid16796_dupName_119_i_unnamed_c_compstr0_shift_x(BITJOIN,16795)@73
    assign rightShiftStage0Idx1_uid16796_dupName_119_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16794_dupName_119_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23781_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x(BITSELECT,23780)@72
    assign leftShiftStage2Idx1Rng8_uid23781_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_in = leftShiftStage1_uid23779_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23781_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23781_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23782_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x(BITJOIN,23781)@72
    assign leftShiftStage2Idx1_uid23782_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23781_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23776_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x(BITSELECT,23775)@72
    assign leftShiftStage1Idx1Rng4_uid23776_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_in = leftShiftStage0_uid23774_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23776_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23776_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23777_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x(BITJOIN,23776)@72
    assign leftShiftStage1Idx1_uid23777_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23776_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23771_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x(BITSELECT,23770)@72
    assign leftShiftStage0Idx1Rng1_uid23771_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_30_c_compstr858_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23771_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23771_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23772_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x(BITJOIN,23771)@72
    assign leftShiftStage0Idx1_uid23772_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23771_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16742_dupName_115_i_unnamed_c_compstr0_shift_x(BITSELECT,16741)@71
    assign rightShiftStage2Idx1Rng8_uid16742_dupName_115_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16741_dupName_115_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16744_dupName_115_i_unnamed_c_compstr0_shift_x(BITJOIN,16743)@71
    assign rightShiftStage2Idx1_uid16744_dupName_115_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16742_dupName_115_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16737_dupName_115_i_unnamed_c_compstr0_shift_x(BITSELECT,16736)@71
    assign rightShiftStage1Idx1Rng4_uid16737_dupName_115_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16736_dupName_115_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16739_dupName_115_i_unnamed_c_compstr0_shift_x(BITJOIN,16738)@71
    assign rightShiftStage1Idx1_uid16739_dupName_115_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16737_dupName_115_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16732_dupName_115_i_unnamed_c_compstr0_shift_x(BITSELECT,16731)@71
    assign rightShiftStage0Idx1Rng1_uid16732_dupName_115_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_q[33:1];

    // rightShiftStage0Idx1_uid16734_dupName_115_i_unnamed_c_compstr0_shift_x(BITJOIN,16733)@71
    assign rightShiftStage0Idx1_uid16734_dupName_115_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16732_dupName_115_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23745_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x(BITSELECT,23744)@70
    assign leftShiftStage2Idx1Rng8_uid23745_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_in = leftShiftStage1_uid23743_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23745_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23745_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23746_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x(BITJOIN,23745)@70
    assign leftShiftStage2Idx1_uid23746_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23745_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23740_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x(BITSELECT,23739)@70
    assign leftShiftStage1Idx1Rng4_uid23740_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_in = leftShiftStage0_uid23738_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23740_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23740_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23741_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x(BITJOIN,23740)@70
    assign leftShiftStage1Idx1_uid23741_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23740_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23735_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x(BITSELECT,23734)@70
    assign leftShiftStage0Idx1Rng1_uid23735_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_29_c_compstr830_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23735_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23735_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23736_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x(BITJOIN,23735)@70
    assign leftShiftStage0Idx1_uid23736_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23735_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16680_dupName_111_i_unnamed_c_compstr0_shift_x(BITSELECT,16679)@69
    assign rightShiftStage2Idx1Rng8_uid16680_dupName_111_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16679_dupName_111_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16682_dupName_111_i_unnamed_c_compstr0_shift_x(BITJOIN,16681)@69
    assign rightShiftStage2Idx1_uid16682_dupName_111_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16680_dupName_111_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16675_dupName_111_i_unnamed_c_compstr0_shift_x(BITSELECT,16674)@69
    assign rightShiftStage1Idx1Rng4_uid16675_dupName_111_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16674_dupName_111_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16677_dupName_111_i_unnamed_c_compstr0_shift_x(BITJOIN,16676)@69
    assign rightShiftStage1Idx1_uid16677_dupName_111_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16675_dupName_111_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16670_dupName_111_i_unnamed_c_compstr0_shift_x(BITSELECT,16669)@69
    assign rightShiftStage0Idx1Rng1_uid16670_dupName_111_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_q[33:1];

    // rightShiftStage0Idx1_uid16672_dupName_111_i_unnamed_c_compstr0_shift_x(BITJOIN,16671)@69
    assign rightShiftStage0Idx1_uid16672_dupName_111_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16670_dupName_111_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23727_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x(BITSELECT,23726)@68
    assign leftShiftStage2Idx1Rng8_uid23727_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_in = leftShiftStage1_uid23725_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23727_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23727_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23728_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x(BITJOIN,23727)@68
    assign leftShiftStage2Idx1_uid23728_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23727_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23722_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x(BITSELECT,23721)@68
    assign leftShiftStage1Idx1Rng4_uid23722_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_in = leftShiftStage0_uid23720_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23722_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23722_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23723_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x(BITJOIN,23722)@68
    assign leftShiftStage1Idx1_uid23723_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23722_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23717_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x(BITSELECT,23716)@68
    assign leftShiftStage0Idx1Rng1_uid23717_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_28_c_compstr802_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23717_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23717_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23718_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x(BITJOIN,23717)@68
    assign leftShiftStage0Idx1_uid23718_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23717_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16618_dupName_107_i_unnamed_c_compstr0_shift_x(BITSELECT,16617)@67
    assign rightShiftStage2Idx1Rng8_uid16618_dupName_107_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16617_dupName_107_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16620_dupName_107_i_unnamed_c_compstr0_shift_x(BITJOIN,16619)@67
    assign rightShiftStage2Idx1_uid16620_dupName_107_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16618_dupName_107_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16613_dupName_107_i_unnamed_c_compstr0_shift_x(BITSELECT,16612)@67
    assign rightShiftStage1Idx1Rng4_uid16613_dupName_107_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16612_dupName_107_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16615_dupName_107_i_unnamed_c_compstr0_shift_x(BITJOIN,16614)@67
    assign rightShiftStage1Idx1_uid16615_dupName_107_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16613_dupName_107_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16608_dupName_107_i_unnamed_c_compstr0_shift_x(BITSELECT,16607)@67
    assign rightShiftStage0Idx1Rng1_uid16608_dupName_107_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_q[33:1];

    // rightShiftStage0Idx1_uid16610_dupName_107_i_unnamed_c_compstr0_shift_x(BITJOIN,16609)@67
    assign rightShiftStage0Idx1_uid16610_dupName_107_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16608_dupName_107_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23709_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x(BITSELECT,23708)@66
    assign leftShiftStage2Idx1Rng8_uid23709_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_in = leftShiftStage1_uid23707_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23709_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23709_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23710_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x(BITJOIN,23709)@66
    assign leftShiftStage2Idx1_uid23710_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23709_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23704_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x(BITSELECT,23703)@66
    assign leftShiftStage1Idx1Rng4_uid23704_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_in = leftShiftStage0_uid23702_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23704_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23704_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23705_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x(BITJOIN,23704)@66
    assign leftShiftStage1Idx1_uid23705_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23704_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23699_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x(BITSELECT,23698)@66
    assign leftShiftStage0Idx1Rng1_uid23699_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_27_c_compstr774_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23699_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23699_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23700_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x(BITJOIN,23699)@66
    assign leftShiftStage0Idx1_uid23700_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23699_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16556_dupName_103_i_unnamed_c_compstr0_shift_x(BITSELECT,16555)@65
    assign rightShiftStage2Idx1Rng8_uid16556_dupName_103_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16555_dupName_103_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16558_dupName_103_i_unnamed_c_compstr0_shift_x(BITJOIN,16557)@65
    assign rightShiftStage2Idx1_uid16558_dupName_103_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16556_dupName_103_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16551_dupName_103_i_unnamed_c_compstr0_shift_x(BITSELECT,16550)@65
    assign rightShiftStage1Idx1Rng4_uid16551_dupName_103_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16550_dupName_103_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16553_dupName_103_i_unnamed_c_compstr0_shift_x(BITJOIN,16552)@65
    assign rightShiftStage1Idx1_uid16553_dupName_103_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16551_dupName_103_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16546_dupName_103_i_unnamed_c_compstr0_shift_x(BITSELECT,16545)@65
    assign rightShiftStage0Idx1Rng1_uid16546_dupName_103_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_q[33:1];

    // rightShiftStage0Idx1_uid16548_dupName_103_i_unnamed_c_compstr0_shift_x(BITJOIN,16547)@65
    assign rightShiftStage0Idx1_uid16548_dupName_103_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16546_dupName_103_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23691_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x(BITSELECT,23690)@64
    assign leftShiftStage2Idx1Rng8_uid23691_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_in = leftShiftStage1_uid23689_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23691_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23691_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23692_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x(BITJOIN,23691)@64
    assign leftShiftStage2Idx1_uid23692_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23691_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23686_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x(BITSELECT,23685)@64
    assign leftShiftStage1Idx1Rng4_uid23686_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_in = leftShiftStage0_uid23684_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23686_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23686_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23687_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x(BITJOIN,23686)@64
    assign leftShiftStage1Idx1_uid23687_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23686_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23681_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x(BITSELECT,23680)@64
    assign leftShiftStage0Idx1Rng1_uid23681_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_26_c_compstr746_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23681_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23681_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23682_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x(BITJOIN,23681)@64
    assign leftShiftStage0Idx1_uid23682_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23681_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16494_dupName_99_i_unnamed_c_compstr0_shift_x(BITSELECT,16493)@63
    assign rightShiftStage2Idx1Rng8_uid16494_dupName_99_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16493_dupName_99_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16496_dupName_99_i_unnamed_c_compstr0_shift_x(BITJOIN,16495)@63
    assign rightShiftStage2Idx1_uid16496_dupName_99_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16494_dupName_99_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16489_dupName_99_i_unnamed_c_compstr0_shift_x(BITSELECT,16488)@63
    assign rightShiftStage1Idx1Rng4_uid16489_dupName_99_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16488_dupName_99_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16491_dupName_99_i_unnamed_c_compstr0_shift_x(BITJOIN,16490)@63
    assign rightShiftStage1Idx1_uid16491_dupName_99_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16489_dupName_99_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16484_dupName_99_i_unnamed_c_compstr0_shift_x(BITSELECT,16483)@63
    assign rightShiftStage0Idx1Rng1_uid16484_dupName_99_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_q[33:1];

    // rightShiftStage0Idx1_uid16486_dupName_99_i_unnamed_c_compstr0_shift_x(BITJOIN,16485)@63
    assign rightShiftStage0Idx1_uid16486_dupName_99_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16484_dupName_99_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23673_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x(BITSELECT,23672)@62
    assign leftShiftStage2Idx1Rng8_uid23673_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_in = leftShiftStage1_uid23671_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23673_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23673_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23674_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x(BITJOIN,23673)@62
    assign leftShiftStage2Idx1_uid23674_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23673_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23668_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x(BITSELECT,23667)@62
    assign leftShiftStage1Idx1Rng4_uid23668_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_in = leftShiftStage0_uid23666_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23668_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23668_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23669_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x(BITJOIN,23668)@62
    assign leftShiftStage1Idx1_uid23669_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23668_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23663_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x(BITSELECT,23662)@62
    assign leftShiftStage0Idx1Rng1_uid23663_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_25_c_compstr718_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23663_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23663_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23664_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x(BITJOIN,23663)@62
    assign leftShiftStage0Idx1_uid23664_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23663_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16432_dupName_95_i_unnamed_c_compstr0_shift_x(BITSELECT,16431)@61
    assign rightShiftStage2Idx1Rng8_uid16432_dupName_95_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16431_dupName_95_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16434_dupName_95_i_unnamed_c_compstr0_shift_x(BITJOIN,16433)@61
    assign rightShiftStage2Idx1_uid16434_dupName_95_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16432_dupName_95_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16427_dupName_95_i_unnamed_c_compstr0_shift_x(BITSELECT,16426)@61
    assign rightShiftStage1Idx1Rng4_uid16427_dupName_95_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16426_dupName_95_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16429_dupName_95_i_unnamed_c_compstr0_shift_x(BITJOIN,16428)@61
    assign rightShiftStage1Idx1_uid16429_dupName_95_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16427_dupName_95_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16422_dupName_95_i_unnamed_c_compstr0_shift_x(BITSELECT,16421)@61
    assign rightShiftStage0Idx1Rng1_uid16422_dupName_95_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_q[33:1];

    // rightShiftStage0Idx1_uid16424_dupName_95_i_unnamed_c_compstr0_shift_x(BITJOIN,16423)@61
    assign rightShiftStage0Idx1_uid16424_dupName_95_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16422_dupName_95_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23655_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x(BITSELECT,23654)@60
    assign leftShiftStage2Idx1Rng8_uid23655_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_in = leftShiftStage1_uid23653_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23655_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23655_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23656_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x(BITJOIN,23655)@60
    assign leftShiftStage2Idx1_uid23656_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23655_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23650_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x(BITSELECT,23649)@60
    assign leftShiftStage1Idx1Rng4_uid23650_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_in = leftShiftStage0_uid23648_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23650_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23650_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23651_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x(BITJOIN,23650)@60
    assign leftShiftStage1Idx1_uid23651_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23650_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23645_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x(BITSELECT,23644)@60
    assign leftShiftStage0Idx1Rng1_uid23645_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_24_c_compstr690_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23645_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23645_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23646_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x(BITJOIN,23645)@60
    assign leftShiftStage0Idx1_uid23646_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23645_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16370_dupName_91_i_unnamed_c_compstr0_shift_x(BITSELECT,16369)@59
    assign rightShiftStage2Idx1Rng8_uid16370_dupName_91_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16369_dupName_91_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16372_dupName_91_i_unnamed_c_compstr0_shift_x(BITJOIN,16371)@59
    assign rightShiftStage2Idx1_uid16372_dupName_91_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16370_dupName_91_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16365_dupName_91_i_unnamed_c_compstr0_shift_x(BITSELECT,16364)@59
    assign rightShiftStage1Idx1Rng4_uid16365_dupName_91_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16364_dupName_91_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16367_dupName_91_i_unnamed_c_compstr0_shift_x(BITJOIN,16366)@59
    assign rightShiftStage1Idx1_uid16367_dupName_91_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16365_dupName_91_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16360_dupName_91_i_unnamed_c_compstr0_shift_x(BITSELECT,16359)@59
    assign rightShiftStage0Idx1Rng1_uid16360_dupName_91_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_q[33:1];

    // rightShiftStage0Idx1_uid16362_dupName_91_i_unnamed_c_compstr0_shift_x(BITJOIN,16361)@59
    assign rightShiftStage0Idx1_uid16362_dupName_91_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16360_dupName_91_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23637_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x(BITSELECT,23636)@58
    assign leftShiftStage2Idx1Rng8_uid23637_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_in = leftShiftStage1_uid23635_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23637_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23637_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23638_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x(BITJOIN,23637)@58
    assign leftShiftStage2Idx1_uid23638_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23637_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23632_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x(BITSELECT,23631)@58
    assign leftShiftStage1Idx1Rng4_uid23632_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_in = leftShiftStage0_uid23630_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23632_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23632_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23633_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x(BITJOIN,23632)@58
    assign leftShiftStage1Idx1_uid23633_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23632_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23627_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x(BITSELECT,23626)@58
    assign leftShiftStage0Idx1Rng1_uid23627_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_23_c_compstr662_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23627_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23627_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23628_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x(BITJOIN,23627)@58
    assign leftShiftStage0Idx1_uid23628_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23627_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16308_dupName_87_i_unnamed_c_compstr0_shift_x(BITSELECT,16307)@57
    assign rightShiftStage2Idx1Rng8_uid16308_dupName_87_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16307_dupName_87_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16310_dupName_87_i_unnamed_c_compstr0_shift_x(BITJOIN,16309)@57
    assign rightShiftStage2Idx1_uid16310_dupName_87_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16308_dupName_87_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16303_dupName_87_i_unnamed_c_compstr0_shift_x(BITSELECT,16302)@57
    assign rightShiftStage1Idx1Rng4_uid16303_dupName_87_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16302_dupName_87_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16305_dupName_87_i_unnamed_c_compstr0_shift_x(BITJOIN,16304)@57
    assign rightShiftStage1Idx1_uid16305_dupName_87_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16303_dupName_87_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16298_dupName_87_i_unnamed_c_compstr0_shift_x(BITSELECT,16297)@57
    assign rightShiftStage0Idx1Rng1_uid16298_dupName_87_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_q[33:1];

    // rightShiftStage0Idx1_uid16300_dupName_87_i_unnamed_c_compstr0_shift_x(BITJOIN,16299)@57
    assign rightShiftStage0Idx1_uid16300_dupName_87_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16298_dupName_87_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23619_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x(BITSELECT,23618)@56
    assign leftShiftStage2Idx1Rng8_uid23619_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_in = leftShiftStage1_uid23617_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23619_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23619_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23620_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x(BITJOIN,23619)@56
    assign leftShiftStage2Idx1_uid23620_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23619_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23614_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x(BITSELECT,23613)@56
    assign leftShiftStage1Idx1Rng4_uid23614_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_in = leftShiftStage0_uid23612_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23614_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23614_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23615_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x(BITJOIN,23614)@56
    assign leftShiftStage1Idx1_uid23615_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23614_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23609_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x(BITSELECT,23608)@56
    assign leftShiftStage0Idx1Rng1_uid23609_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_22_c_compstr634_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23609_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23609_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23610_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x(BITJOIN,23609)@56
    assign leftShiftStage0Idx1_uid23610_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23609_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16246_dupName_83_i_unnamed_c_compstr0_shift_x(BITSELECT,16245)@55
    assign rightShiftStage2Idx1Rng8_uid16246_dupName_83_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16245_dupName_83_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16248_dupName_83_i_unnamed_c_compstr0_shift_x(BITJOIN,16247)@55
    assign rightShiftStage2Idx1_uid16248_dupName_83_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16246_dupName_83_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16241_dupName_83_i_unnamed_c_compstr0_shift_x(BITSELECT,16240)@55
    assign rightShiftStage1Idx1Rng4_uid16241_dupName_83_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16240_dupName_83_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16243_dupName_83_i_unnamed_c_compstr0_shift_x(BITJOIN,16242)@55
    assign rightShiftStage1Idx1_uid16243_dupName_83_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16241_dupName_83_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16236_dupName_83_i_unnamed_c_compstr0_shift_x(BITSELECT,16235)@55
    assign rightShiftStage0Idx1Rng1_uid16236_dupName_83_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_q[33:1];

    // rightShiftStage0Idx1_uid16238_dupName_83_i_unnamed_c_compstr0_shift_x(BITJOIN,16237)@55
    assign rightShiftStage0Idx1_uid16238_dupName_83_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16236_dupName_83_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23601_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x(BITSELECT,23600)@54
    assign leftShiftStage2Idx1Rng8_uid23601_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_in = leftShiftStage1_uid23599_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23601_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23601_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23602_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x(BITJOIN,23601)@54
    assign leftShiftStage2Idx1_uid23602_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23601_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23596_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x(BITSELECT,23595)@54
    assign leftShiftStage1Idx1Rng4_uid23596_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_in = leftShiftStage0_uid23594_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23596_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23596_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23597_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x(BITJOIN,23596)@54
    assign leftShiftStage1Idx1_uid23597_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23596_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23591_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x(BITSELECT,23590)@54
    assign leftShiftStage0Idx1Rng1_uid23591_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_21_c_compstr606_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23591_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23591_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23592_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x(BITJOIN,23591)@54
    assign leftShiftStage0Idx1_uid23592_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23591_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16184_dupName_79_i_unnamed_c_compstr0_shift_x(BITSELECT,16183)@53
    assign rightShiftStage2Idx1Rng8_uid16184_dupName_79_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16183_dupName_79_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16186_dupName_79_i_unnamed_c_compstr0_shift_x(BITJOIN,16185)@53
    assign rightShiftStage2Idx1_uid16186_dupName_79_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16184_dupName_79_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16179_dupName_79_i_unnamed_c_compstr0_shift_x(BITSELECT,16178)@53
    assign rightShiftStage1Idx1Rng4_uid16179_dupName_79_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16178_dupName_79_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16181_dupName_79_i_unnamed_c_compstr0_shift_x(BITJOIN,16180)@53
    assign rightShiftStage1Idx1_uid16181_dupName_79_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16179_dupName_79_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16174_dupName_79_i_unnamed_c_compstr0_shift_x(BITSELECT,16173)@53
    assign rightShiftStage0Idx1Rng1_uid16174_dupName_79_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_q[33:1];

    // rightShiftStage0Idx1_uid16176_dupName_79_i_unnamed_c_compstr0_shift_x(BITJOIN,16175)@53
    assign rightShiftStage0Idx1_uid16176_dupName_79_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16174_dupName_79_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23583_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x(BITSELECT,23582)@52
    assign leftShiftStage2Idx1Rng8_uid23583_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_in = leftShiftStage1_uid23581_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23583_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23583_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23584_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x(BITJOIN,23583)@52
    assign leftShiftStage2Idx1_uid23584_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23583_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23578_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x(BITSELECT,23577)@52
    assign leftShiftStage1Idx1Rng4_uid23578_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_in = leftShiftStage0_uid23576_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23578_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23578_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23579_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x(BITJOIN,23578)@52
    assign leftShiftStage1Idx1_uid23579_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23578_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23573_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x(BITSELECT,23572)@52
    assign leftShiftStage0Idx1Rng1_uid23573_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_20_c_compstr578_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23573_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23573_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23574_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x(BITJOIN,23573)@52
    assign leftShiftStage0Idx1_uid23574_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23573_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16122_dupName_75_i_unnamed_c_compstr0_shift_x(BITSELECT,16121)@51
    assign rightShiftStage2Idx1Rng8_uid16122_dupName_75_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16121_dupName_75_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16124_dupName_75_i_unnamed_c_compstr0_shift_x(BITJOIN,16123)@51
    assign rightShiftStage2Idx1_uid16124_dupName_75_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16122_dupName_75_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16117_dupName_75_i_unnamed_c_compstr0_shift_x(BITSELECT,16116)@51
    assign rightShiftStage1Idx1Rng4_uid16117_dupName_75_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16116_dupName_75_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16119_dupName_75_i_unnamed_c_compstr0_shift_x(BITJOIN,16118)@51
    assign rightShiftStage1Idx1_uid16119_dupName_75_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16117_dupName_75_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16112_dupName_75_i_unnamed_c_compstr0_shift_x(BITSELECT,16111)@51
    assign rightShiftStage0Idx1Rng1_uid16112_dupName_75_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_q[33:1];

    // rightShiftStage0Idx1_uid16114_dupName_75_i_unnamed_c_compstr0_shift_x(BITJOIN,16113)@51
    assign rightShiftStage0Idx1_uid16114_dupName_75_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16112_dupName_75_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23547_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x(BITSELECT,23546)@50
    assign leftShiftStage2Idx1Rng8_uid23547_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_in = leftShiftStage1_uid23545_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23547_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23547_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23548_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x(BITJOIN,23547)@50
    assign leftShiftStage2Idx1_uid23548_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23547_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23542_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x(BITSELECT,23541)@50
    assign leftShiftStage1Idx1Rng4_uid23542_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_in = leftShiftStage0_uid23540_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23542_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23542_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23543_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x(BITJOIN,23542)@50
    assign leftShiftStage1Idx1_uid23543_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23542_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23537_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x(BITSELECT,23536)@50
    assign leftShiftStage0Idx1Rng1_uid23537_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_19_c_compstr550_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23537_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23537_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23538_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x(BITJOIN,23537)@50
    assign leftShiftStage0Idx1_uid23538_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23537_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16060_dupName_71_i_unnamed_c_compstr0_shift_x(BITSELECT,16059)@49
    assign rightShiftStage2Idx1Rng8_uid16060_dupName_71_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid16059_dupName_71_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16062_dupName_71_i_unnamed_c_compstr0_shift_x(BITJOIN,16061)@49
    assign rightShiftStage2Idx1_uid16062_dupName_71_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid16060_dupName_71_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16055_dupName_71_i_unnamed_c_compstr0_shift_x(BITSELECT,16054)@49
    assign rightShiftStage1Idx1Rng4_uid16055_dupName_71_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16054_dupName_71_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16057_dupName_71_i_unnamed_c_compstr0_shift_x(BITJOIN,16056)@49
    assign rightShiftStage1Idx1_uid16057_dupName_71_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid16055_dupName_71_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16050_dupName_71_i_unnamed_c_compstr0_shift_x(BITSELECT,16049)@49
    assign rightShiftStage0Idx1Rng1_uid16050_dupName_71_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_q[33:1];

    // rightShiftStage0Idx1_uid16052_dupName_71_i_unnamed_c_compstr0_shift_x(BITJOIN,16051)@49
    assign rightShiftStage0Idx1_uid16052_dupName_71_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16050_dupName_71_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23529_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x(BITSELECT,23528)@48
    assign leftShiftStage2Idx1Rng8_uid23529_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_in = leftShiftStage1_uid23527_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23529_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23529_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23530_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x(BITJOIN,23529)@48
    assign leftShiftStage2Idx1_uid23530_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23529_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23524_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x(BITSELECT,23523)@48
    assign leftShiftStage1Idx1Rng4_uid23524_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_in = leftShiftStage0_uid23522_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23524_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23524_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23525_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x(BITJOIN,23524)@48
    assign leftShiftStage1Idx1_uid23525_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23524_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23519_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x(BITSELECT,23518)@48
    assign leftShiftStage0Idx1Rng1_uid23519_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_18_c_compstr522_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23519_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23519_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23520_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x(BITJOIN,23519)@48
    assign leftShiftStage0Idx1_uid23520_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23519_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15998_dupName_67_i_unnamed_c_compstr0_shift_x(BITSELECT,15997)@47
    assign rightShiftStage2Idx1Rng8_uid15998_dupName_67_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15997_dupName_67_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16000_dupName_67_i_unnamed_c_compstr0_shift_x(BITJOIN,15999)@47
    assign rightShiftStage2Idx1_uid16000_dupName_67_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15998_dupName_67_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15993_dupName_67_i_unnamed_c_compstr0_shift_x(BITSELECT,15992)@47
    assign rightShiftStage1Idx1Rng4_uid15993_dupName_67_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15992_dupName_67_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15995_dupName_67_i_unnamed_c_compstr0_shift_x(BITJOIN,15994)@47
    assign rightShiftStage1Idx1_uid15995_dupName_67_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15993_dupName_67_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15988_dupName_67_i_unnamed_c_compstr0_shift_x(BITSELECT,15987)@47
    assign rightShiftStage0Idx1Rng1_uid15988_dupName_67_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_q[33:1];

    // rightShiftStage0Idx1_uid15990_dupName_67_i_unnamed_c_compstr0_shift_x(BITJOIN,15989)@47
    assign rightShiftStage0Idx1_uid15990_dupName_67_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15988_dupName_67_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23511_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x(BITSELECT,23510)@46
    assign leftShiftStage2Idx1Rng8_uid23511_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_in = leftShiftStage1_uid23509_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23511_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23511_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23512_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x(BITJOIN,23511)@46
    assign leftShiftStage2Idx1_uid23512_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23511_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23506_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x(BITSELECT,23505)@46
    assign leftShiftStage1Idx1Rng4_uid23506_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_in = leftShiftStage0_uid23504_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23506_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23506_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23507_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x(BITJOIN,23506)@46
    assign leftShiftStage1Idx1_uid23507_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23506_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23501_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x(BITSELECT,23500)@46
    assign leftShiftStage0Idx1Rng1_uid23501_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_17_c_compstr494_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23501_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23501_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23502_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x(BITJOIN,23501)@46
    assign leftShiftStage0Idx1_uid23502_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23501_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15936_dupName_63_i_unnamed_c_compstr0_shift_x(BITSELECT,15935)@45
    assign rightShiftStage2Idx1Rng8_uid15936_dupName_63_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15935_dupName_63_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15938_dupName_63_i_unnamed_c_compstr0_shift_x(BITJOIN,15937)@45
    assign rightShiftStage2Idx1_uid15938_dupName_63_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15936_dupName_63_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15931_dupName_63_i_unnamed_c_compstr0_shift_x(BITSELECT,15930)@45
    assign rightShiftStage1Idx1Rng4_uid15931_dupName_63_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15930_dupName_63_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15933_dupName_63_i_unnamed_c_compstr0_shift_x(BITJOIN,15932)@45
    assign rightShiftStage1Idx1_uid15933_dupName_63_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15931_dupName_63_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15926_dupName_63_i_unnamed_c_compstr0_shift_x(BITSELECT,15925)@45
    assign rightShiftStage0Idx1Rng1_uid15926_dupName_63_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_q[33:1];

    // rightShiftStage0Idx1_uid15928_dupName_63_i_unnamed_c_compstr0_shift_x(BITJOIN,15927)@45
    assign rightShiftStage0Idx1_uid15928_dupName_63_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15926_dupName_63_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23493_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x(BITSELECT,23492)@44
    assign leftShiftStage2Idx1Rng8_uid23493_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_in = leftShiftStage1_uid23491_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23493_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23493_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23494_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x(BITJOIN,23493)@44
    assign leftShiftStage2Idx1_uid23494_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23493_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23488_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x(BITSELECT,23487)@44
    assign leftShiftStage1Idx1Rng4_uid23488_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_in = leftShiftStage0_uid23486_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23488_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23488_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23489_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x(BITJOIN,23488)@44
    assign leftShiftStage1Idx1_uid23489_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23488_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23483_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x(BITSELECT,23482)@44
    assign leftShiftStage0Idx1Rng1_uid23483_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_16_c_compstr466_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23483_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23483_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23484_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x(BITJOIN,23483)@44
    assign leftShiftStage0Idx1_uid23484_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23483_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15874_dupName_59_i_unnamed_c_compstr0_shift_x(BITSELECT,15873)@43
    assign rightShiftStage2Idx1Rng8_uid15874_dupName_59_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15873_dupName_59_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15876_dupName_59_i_unnamed_c_compstr0_shift_x(BITJOIN,15875)@43
    assign rightShiftStage2Idx1_uid15876_dupName_59_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15874_dupName_59_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15869_dupName_59_i_unnamed_c_compstr0_shift_x(BITSELECT,15868)@43
    assign rightShiftStage1Idx1Rng4_uid15869_dupName_59_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15868_dupName_59_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15871_dupName_59_i_unnamed_c_compstr0_shift_x(BITJOIN,15870)@43
    assign rightShiftStage1Idx1_uid15871_dupName_59_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15869_dupName_59_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15864_dupName_59_i_unnamed_c_compstr0_shift_x(BITSELECT,15863)@43
    assign rightShiftStage0Idx1Rng1_uid15864_dupName_59_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_q[33:1];

    // rightShiftStage0Idx1_uid15866_dupName_59_i_unnamed_c_compstr0_shift_x(BITJOIN,15865)@43
    assign rightShiftStage0Idx1_uid15866_dupName_59_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15864_dupName_59_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23475_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x(BITSELECT,23474)@42
    assign leftShiftStage2Idx1Rng8_uid23475_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_in = leftShiftStage1_uid23473_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23475_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23475_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23476_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x(BITJOIN,23475)@42
    assign leftShiftStage2Idx1_uid23476_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23475_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23470_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x(BITSELECT,23469)@42
    assign leftShiftStage1Idx1Rng4_uid23470_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_in = leftShiftStage0_uid23468_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23470_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23470_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23471_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x(BITJOIN,23470)@42
    assign leftShiftStage1Idx1_uid23471_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23470_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23465_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x(BITSELECT,23464)@42
    assign leftShiftStage0Idx1Rng1_uid23465_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_15_c_compstr438_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23465_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23465_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23466_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x(BITJOIN,23465)@42
    assign leftShiftStage0Idx1_uid23466_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23465_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15812_dupName_55_i_unnamed_c_compstr0_shift_x(BITSELECT,15811)@41
    assign rightShiftStage2Idx1Rng8_uid15812_dupName_55_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15811_dupName_55_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15814_dupName_55_i_unnamed_c_compstr0_shift_x(BITJOIN,15813)@41
    assign rightShiftStage2Idx1_uid15814_dupName_55_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15812_dupName_55_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15807_dupName_55_i_unnamed_c_compstr0_shift_x(BITSELECT,15806)@41
    assign rightShiftStage1Idx1Rng4_uid15807_dupName_55_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15806_dupName_55_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15809_dupName_55_i_unnamed_c_compstr0_shift_x(BITJOIN,15808)@41
    assign rightShiftStage1Idx1_uid15809_dupName_55_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15807_dupName_55_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15802_dupName_55_i_unnamed_c_compstr0_shift_x(BITSELECT,15801)@41
    assign rightShiftStage0Idx1Rng1_uid15802_dupName_55_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_q[33:1];

    // rightShiftStage0Idx1_uid15804_dupName_55_i_unnamed_c_compstr0_shift_x(BITJOIN,15803)@41
    assign rightShiftStage0Idx1_uid15804_dupName_55_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15802_dupName_55_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23457_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x(BITSELECT,23456)@40
    assign leftShiftStage2Idx1Rng8_uid23457_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_in = leftShiftStage1_uid23455_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23457_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23457_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23458_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x(BITJOIN,23457)@40
    assign leftShiftStage2Idx1_uid23458_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23457_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23452_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x(BITSELECT,23451)@40
    assign leftShiftStage1Idx1Rng4_uid23452_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_in = leftShiftStage0_uid23450_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23452_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23452_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23453_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x(BITJOIN,23452)@40
    assign leftShiftStage1Idx1_uid23453_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23452_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23447_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x(BITSELECT,23446)@40
    assign leftShiftStage0Idx1Rng1_uid23447_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_14_c_compstr410_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23447_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23447_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23448_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x(BITJOIN,23447)@40
    assign leftShiftStage0Idx1_uid23448_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23447_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15750_dupName_51_i_unnamed_c_compstr0_shift_x(BITSELECT,15749)@39
    assign rightShiftStage2Idx1Rng8_uid15750_dupName_51_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15749_dupName_51_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15752_dupName_51_i_unnamed_c_compstr0_shift_x(BITJOIN,15751)@39
    assign rightShiftStage2Idx1_uid15752_dupName_51_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15750_dupName_51_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15745_dupName_51_i_unnamed_c_compstr0_shift_x(BITSELECT,15744)@39
    assign rightShiftStage1Idx1Rng4_uid15745_dupName_51_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15744_dupName_51_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15747_dupName_51_i_unnamed_c_compstr0_shift_x(BITJOIN,15746)@39
    assign rightShiftStage1Idx1_uid15747_dupName_51_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15745_dupName_51_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15740_dupName_51_i_unnamed_c_compstr0_shift_x(BITSELECT,15739)@39
    assign rightShiftStage0Idx1Rng1_uid15740_dupName_51_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_q[33:1];

    // rightShiftStage0Idx1_uid15742_dupName_51_i_unnamed_c_compstr0_shift_x(BITJOIN,15741)@39
    assign rightShiftStage0Idx1_uid15742_dupName_51_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15740_dupName_51_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23439_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x(BITSELECT,23438)@38
    assign leftShiftStage2Idx1Rng8_uid23439_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_in = leftShiftStage1_uid23437_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23439_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23439_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23440_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x(BITJOIN,23439)@38
    assign leftShiftStage2Idx1_uid23440_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23439_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23434_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x(BITSELECT,23433)@38
    assign leftShiftStage1Idx1Rng4_uid23434_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_in = leftShiftStage0_uid23432_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23434_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23434_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23435_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x(BITJOIN,23434)@38
    assign leftShiftStage1Idx1_uid23435_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23434_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23429_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x(BITSELECT,23428)@38
    assign leftShiftStage0Idx1Rng1_uid23429_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_13_c_compstr382_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23429_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23429_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23430_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x(BITJOIN,23429)@38
    assign leftShiftStage0Idx1_uid23430_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23429_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15688_dupName_47_i_unnamed_c_compstr0_shift_x(BITSELECT,15687)@37
    assign rightShiftStage2Idx1Rng8_uid15688_dupName_47_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15687_dupName_47_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15690_dupName_47_i_unnamed_c_compstr0_shift_x(BITJOIN,15689)@37
    assign rightShiftStage2Idx1_uid15690_dupName_47_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15688_dupName_47_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15683_dupName_47_i_unnamed_c_compstr0_shift_x(BITSELECT,15682)@37
    assign rightShiftStage1Idx1Rng4_uid15683_dupName_47_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15682_dupName_47_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15685_dupName_47_i_unnamed_c_compstr0_shift_x(BITJOIN,15684)@37
    assign rightShiftStage1Idx1_uid15685_dupName_47_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15683_dupName_47_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15678_dupName_47_i_unnamed_c_compstr0_shift_x(BITSELECT,15677)@37
    assign rightShiftStage0Idx1Rng1_uid15678_dupName_47_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_q[33:1];

    // rightShiftStage0Idx1_uid15680_dupName_47_i_unnamed_c_compstr0_shift_x(BITJOIN,15679)@37
    assign rightShiftStage0Idx1_uid15680_dupName_47_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15678_dupName_47_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23421_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x(BITSELECT,23420)@36
    assign leftShiftStage2Idx1Rng8_uid23421_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_in = leftShiftStage1_uid23419_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23421_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23421_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23422_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x(BITJOIN,23421)@36
    assign leftShiftStage2Idx1_uid23422_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23421_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23416_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x(BITSELECT,23415)@36
    assign leftShiftStage1Idx1Rng4_uid23416_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_in = leftShiftStage0_uid23414_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23416_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23416_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23417_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x(BITJOIN,23416)@36
    assign leftShiftStage1Idx1_uid23417_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23416_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23411_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x(BITSELECT,23410)@36
    assign leftShiftStage0Idx1Rng1_uid23411_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_12_c_compstr354_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23411_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23411_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23412_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x(BITJOIN,23411)@36
    assign leftShiftStage0Idx1_uid23412_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23411_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15626_dupName_43_i_unnamed_c_compstr0_shift_x(BITSELECT,15625)@35
    assign rightShiftStage2Idx1Rng8_uid15626_dupName_43_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15625_dupName_43_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15628_dupName_43_i_unnamed_c_compstr0_shift_x(BITJOIN,15627)@35
    assign rightShiftStage2Idx1_uid15628_dupName_43_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15626_dupName_43_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15621_dupName_43_i_unnamed_c_compstr0_shift_x(BITSELECT,15620)@35
    assign rightShiftStage1Idx1Rng4_uid15621_dupName_43_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15620_dupName_43_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15623_dupName_43_i_unnamed_c_compstr0_shift_x(BITJOIN,15622)@35
    assign rightShiftStage1Idx1_uid15623_dupName_43_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15621_dupName_43_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15616_dupName_43_i_unnamed_c_compstr0_shift_x(BITSELECT,15615)@35
    assign rightShiftStage0Idx1Rng1_uid15616_dupName_43_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_q[33:1];

    // rightShiftStage0Idx1_uid15618_dupName_43_i_unnamed_c_compstr0_shift_x(BITJOIN,15617)@35
    assign rightShiftStage0Idx1_uid15618_dupName_43_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15616_dupName_43_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23259_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x(BITSELECT,23258)@34
    assign leftShiftStage2Idx1Rng8_uid23259_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_in = leftShiftStage1_uid23257_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23259_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23259_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23260_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x(BITJOIN,23259)@34
    assign leftShiftStage2Idx1_uid23260_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23259_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23254_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x(BITSELECT,23253)@34
    assign leftShiftStage1Idx1Rng4_uid23254_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_in = leftShiftStage0_uid23252_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23254_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23254_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23255_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x(BITJOIN,23254)@34
    assign leftShiftStage1Idx1_uid23255_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23254_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23249_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x(BITSELECT,23248)@34
    assign leftShiftStage0Idx1Rng1_uid23249_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_11_c_compstr326_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23249_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23249_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23250_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x(BITJOIN,23249)@34
    assign leftShiftStage0Idx1_uid23250_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23249_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15564_dupName_39_i_unnamed_c_compstr0_shift_x(BITSELECT,15563)@33
    assign rightShiftStage2Idx1Rng8_uid15564_dupName_39_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15563_dupName_39_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15566_dupName_39_i_unnamed_c_compstr0_shift_x(BITJOIN,15565)@33
    assign rightShiftStage2Idx1_uid15566_dupName_39_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15564_dupName_39_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15559_dupName_39_i_unnamed_c_compstr0_shift_x(BITSELECT,15558)@33
    assign rightShiftStage1Idx1Rng4_uid15559_dupName_39_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15558_dupName_39_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15561_dupName_39_i_unnamed_c_compstr0_shift_x(BITJOIN,15560)@33
    assign rightShiftStage1Idx1_uid15561_dupName_39_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15559_dupName_39_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15554_dupName_39_i_unnamed_c_compstr0_shift_x(BITSELECT,15553)@33
    assign rightShiftStage0Idx1Rng1_uid15554_dupName_39_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_q[33:1];

    // rightShiftStage0Idx1_uid15556_dupName_39_i_unnamed_c_compstr0_shift_x(BITJOIN,15555)@33
    assign rightShiftStage0Idx1_uid15556_dupName_39_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15554_dupName_39_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23061_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x(BITSELECT,23060)@32
    assign leftShiftStage2Idx1Rng8_uid23061_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_in = leftShiftStage1_uid23059_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23061_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23061_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23062_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x(BITJOIN,23061)@32
    assign leftShiftStage2Idx1_uid23062_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23061_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23056_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x(BITSELECT,23055)@32
    assign leftShiftStage1Idx1Rng4_uid23056_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_in = leftShiftStage0_uid23054_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23056_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23056_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23057_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x(BITJOIN,23056)@32
    assign leftShiftStage1Idx1_uid23057_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23056_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23051_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x(BITSELECT,23050)@32
    assign leftShiftStage0Idx1Rng1_uid23051_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_10_c_compstr298_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23051_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23051_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23052_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x(BITJOIN,23051)@32
    assign leftShiftStage0Idx1_uid23052_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23051_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15502_dupName_35_i_unnamed_c_compstr0_shift_x(BITSELECT,15501)@31
    assign rightShiftStage2Idx1Rng8_uid15502_dupName_35_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15501_dupName_35_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15504_dupName_35_i_unnamed_c_compstr0_shift_x(BITJOIN,15503)@31
    assign rightShiftStage2Idx1_uid15504_dupName_35_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15502_dupName_35_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15497_dupName_35_i_unnamed_c_compstr0_shift_x(BITSELECT,15496)@31
    assign rightShiftStage1Idx1Rng4_uid15497_dupName_35_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15496_dupName_35_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15499_dupName_35_i_unnamed_c_compstr0_shift_x(BITJOIN,15498)@31
    assign rightShiftStage1Idx1_uid15499_dupName_35_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15497_dupName_35_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15492_dupName_35_i_unnamed_c_compstr0_shift_x(BITSELECT,15491)@31
    assign rightShiftStage0Idx1Rng1_uid15492_dupName_35_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_q[33:1];

    // rightShiftStage0Idx1_uid15494_dupName_35_i_unnamed_c_compstr0_shift_x(BITJOIN,15493)@31
    assign rightShiftStage0Idx1_uid15494_dupName_35_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15492_dupName_35_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25149_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x(BITSELECT,25148)@30
    assign leftShiftStage2Idx1Rng8_uid25149_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_in = leftShiftStage1_uid25147_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25149_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid25149_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25150_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x(BITJOIN,25149)@30
    assign leftShiftStage2Idx1_uid25150_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25149_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25144_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x(BITSELECT,25143)@30
    assign leftShiftStage1Idx1Rng4_uid25144_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_in = leftShiftStage0_uid25142_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25144_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid25144_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25145_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x(BITJOIN,25144)@30
    assign leftShiftStage1Idx1_uid25145_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25144_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25139_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x(BITSELECT,25138)@30
    assign leftShiftStage0Idx1Rng1_uid25139_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_9_c_compstr270_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25139_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid25139_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25140_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x(BITJOIN,25139)@30
    assign leftShiftStage0Idx1_uid25140_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25139_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15440_dupName_31_i_unnamed_c_compstr0_shift_x(BITSELECT,15439)@29
    assign rightShiftStage2Idx1Rng8_uid15440_dupName_31_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15439_dupName_31_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15442_dupName_31_i_unnamed_c_compstr0_shift_x(BITJOIN,15441)@29
    assign rightShiftStage2Idx1_uid15442_dupName_31_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15440_dupName_31_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15435_dupName_31_i_unnamed_c_compstr0_shift_x(BITSELECT,15434)@29
    assign rightShiftStage1Idx1Rng4_uid15435_dupName_31_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15434_dupName_31_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15437_dupName_31_i_unnamed_c_compstr0_shift_x(BITJOIN,15436)@29
    assign rightShiftStage1Idx1_uid15437_dupName_31_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15435_dupName_31_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15430_dupName_31_i_unnamed_c_compstr0_shift_x(BITSELECT,15429)@29
    assign rightShiftStage0Idx1Rng1_uid15430_dupName_31_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_q[33:1];

    // rightShiftStage0Idx1_uid15432_dupName_31_i_unnamed_c_compstr0_shift_x(BITJOIN,15431)@29
    assign rightShiftStage0Idx1_uid15432_dupName_31_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15430_dupName_31_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24951_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x(BITSELECT,24950)@28
    assign leftShiftStage2Idx1Rng8_uid24951_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_in = leftShiftStage1_uid24949_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24951_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24951_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24952_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x(BITJOIN,24951)@28
    assign leftShiftStage2Idx1_uid24952_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24951_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24946_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x(BITSELECT,24945)@28
    assign leftShiftStage1Idx1Rng4_uid24946_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_in = leftShiftStage0_uid24944_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24946_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24946_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24947_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x(BITJOIN,24946)@28
    assign leftShiftStage1Idx1_uid24947_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24946_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24941_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x(BITSELECT,24940)@28
    assign leftShiftStage0Idx1Rng1_uid24941_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_8_c_compstr242_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24941_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24941_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24942_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x(BITJOIN,24941)@28
    assign leftShiftStage0Idx1_uid24942_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24941_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15378_dupName_27_i_unnamed_c_compstr0_shift_x(BITSELECT,15377)@27
    assign rightShiftStage2Idx1Rng8_uid15378_dupName_27_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15377_dupName_27_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15380_dupName_27_i_unnamed_c_compstr0_shift_x(BITJOIN,15379)@27
    assign rightShiftStage2Idx1_uid15380_dupName_27_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15378_dupName_27_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15373_dupName_27_i_unnamed_c_compstr0_shift_x(BITSELECT,15372)@27
    assign rightShiftStage1Idx1Rng4_uid15373_dupName_27_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15372_dupName_27_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15375_dupName_27_i_unnamed_c_compstr0_shift_x(BITJOIN,15374)@27
    assign rightShiftStage1Idx1_uid15375_dupName_27_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15373_dupName_27_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15368_dupName_27_i_unnamed_c_compstr0_shift_x(BITSELECT,15367)@27
    assign rightShiftStage0Idx1Rng1_uid15368_dupName_27_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_q[33:1];

    // rightShiftStage0Idx1_uid15370_dupName_27_i_unnamed_c_compstr0_shift_x(BITJOIN,15369)@27
    assign rightShiftStage0Idx1_uid15370_dupName_27_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15368_dupName_27_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24753_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x(BITSELECT,24752)@26
    assign leftShiftStage2Idx1Rng8_uid24753_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_in = leftShiftStage1_uid24751_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24753_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24753_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24754_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x(BITJOIN,24753)@26
    assign leftShiftStage2Idx1_uid24754_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24753_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24748_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x(BITSELECT,24747)@26
    assign leftShiftStage1Idx1Rng4_uid24748_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_in = leftShiftStage0_uid24746_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24748_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24748_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24749_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x(BITJOIN,24748)@26
    assign leftShiftStage1Idx1_uid24749_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24748_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24743_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x(BITSELECT,24742)@26
    assign leftShiftStage0Idx1Rng1_uid24743_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_7_c_compstr214_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24743_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24743_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24744_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x(BITJOIN,24743)@26
    assign leftShiftStage0Idx1_uid24744_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24743_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15316_dupName_23_i_unnamed_c_compstr0_shift_x(BITSELECT,15315)@25
    assign rightShiftStage2Idx1Rng8_uid15316_dupName_23_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15315_dupName_23_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15318_dupName_23_i_unnamed_c_compstr0_shift_x(BITJOIN,15317)@25
    assign rightShiftStage2Idx1_uid15318_dupName_23_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15316_dupName_23_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15311_dupName_23_i_unnamed_c_compstr0_shift_x(BITSELECT,15310)@25
    assign rightShiftStage1Idx1Rng4_uid15311_dupName_23_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15310_dupName_23_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15313_dupName_23_i_unnamed_c_compstr0_shift_x(BITJOIN,15312)@25
    assign rightShiftStage1Idx1_uid15313_dupName_23_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15311_dupName_23_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15306_dupName_23_i_unnamed_c_compstr0_shift_x(BITSELECT,15305)@25
    assign rightShiftStage0Idx1Rng1_uid15306_dupName_23_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_q[33:1];

    // rightShiftStage0Idx1_uid15308_dupName_23_i_unnamed_c_compstr0_shift_x(BITJOIN,15307)@25
    assign rightShiftStage0Idx1_uid15308_dupName_23_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15306_dupName_23_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24555_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x(BITSELECT,24554)@24
    assign leftShiftStage2Idx1Rng8_uid24555_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_in = leftShiftStage1_uid24553_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24555_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24555_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24556_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x(BITJOIN,24555)@24
    assign leftShiftStage2Idx1_uid24556_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24555_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24550_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x(BITSELECT,24549)@24
    assign leftShiftStage1Idx1Rng4_uid24550_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_in = leftShiftStage0_uid24548_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24550_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24550_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24551_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x(BITJOIN,24550)@24
    assign leftShiftStage1Idx1_uid24551_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24550_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24545_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x(BITSELECT,24544)@24
    assign leftShiftStage0Idx1Rng1_uid24545_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_6_c_compstr186_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24545_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24545_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24546_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x(BITJOIN,24545)@24
    assign leftShiftStage0Idx1_uid24546_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24545_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15254_dupName_19_i_unnamed_c_compstr0_shift_x(BITSELECT,15253)@23
    assign rightShiftStage2Idx1Rng8_uid15254_dupName_19_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15253_dupName_19_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15256_dupName_19_i_unnamed_c_compstr0_shift_x(BITJOIN,15255)@23
    assign rightShiftStage2Idx1_uid15256_dupName_19_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15254_dupName_19_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15249_dupName_19_i_unnamed_c_compstr0_shift_x(BITSELECT,15248)@23
    assign rightShiftStage1Idx1Rng4_uid15249_dupName_19_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15248_dupName_19_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15251_dupName_19_i_unnamed_c_compstr0_shift_x(BITJOIN,15250)@23
    assign rightShiftStage1Idx1_uid15251_dupName_19_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15249_dupName_19_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15244_dupName_19_i_unnamed_c_compstr0_shift_x(BITSELECT,15243)@23
    assign rightShiftStage0Idx1Rng1_uid15244_dupName_19_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_q[33:1];

    // rightShiftStage0Idx1_uid15246_dupName_19_i_unnamed_c_compstr0_shift_x(BITJOIN,15245)@23
    assign rightShiftStage0Idx1_uid15246_dupName_19_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15244_dupName_19_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24357_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x(BITSELECT,24356)@22
    assign leftShiftStage2Idx1Rng8_uid24357_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_in = leftShiftStage1_uid24355_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24357_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24357_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24358_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x(BITJOIN,24357)@22
    assign leftShiftStage2Idx1_uid24358_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24357_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24352_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x(BITSELECT,24351)@22
    assign leftShiftStage1Idx1Rng4_uid24352_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_in = leftShiftStage0_uid24350_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24352_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24352_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24353_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x(BITJOIN,24352)@22
    assign leftShiftStage1Idx1_uid24353_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24352_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24347_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x(BITSELECT,24346)@22
    assign leftShiftStage0Idx1Rng1_uid24347_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_5_c_compstr158_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24347_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24347_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24348_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x(BITJOIN,24347)@22
    assign leftShiftStage0Idx1_uid24348_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24347_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15192_dupName_15_i_unnamed_c_compstr0_shift_x(BITSELECT,15191)@21
    assign rightShiftStage2Idx1Rng8_uid15192_dupName_15_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15191_dupName_15_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15194_dupName_15_i_unnamed_c_compstr0_shift_x(BITJOIN,15193)@21
    assign rightShiftStage2Idx1_uid15194_dupName_15_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15192_dupName_15_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15187_dupName_15_i_unnamed_c_compstr0_shift_x(BITSELECT,15186)@21
    assign rightShiftStage1Idx1Rng4_uid15187_dupName_15_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15186_dupName_15_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15189_dupName_15_i_unnamed_c_compstr0_shift_x(BITJOIN,15188)@21
    assign rightShiftStage1Idx1_uid15189_dupName_15_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15187_dupName_15_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15182_dupName_15_i_unnamed_c_compstr0_shift_x(BITSELECT,15181)@21
    assign rightShiftStage0Idx1Rng1_uid15182_dupName_15_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_q[33:1];

    // rightShiftStage0Idx1_uid15184_dupName_15_i_unnamed_c_compstr0_shift_x(BITJOIN,15183)@21
    assign rightShiftStage0Idx1_uid15184_dupName_15_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15182_dupName_15_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24159_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x(BITSELECT,24158)@20
    assign leftShiftStage2Idx1Rng8_uid24159_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_in = leftShiftStage1_uid24157_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24159_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid24159_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24160_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x(BITJOIN,24159)@20
    assign leftShiftStage2Idx1_uid24160_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24159_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24154_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x(BITSELECT,24153)@20
    assign leftShiftStage1Idx1Rng4_uid24154_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_in = leftShiftStage0_uid24152_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24154_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid24154_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24155_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x(BITJOIN,24154)@20
    assign leftShiftStage1Idx1_uid24155_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24154_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24149_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x(BITSELECT,24148)@20
    assign leftShiftStage0Idx1Rng1_uid24149_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_4_c_compstr130_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24149_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid24149_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24150_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x(BITJOIN,24149)@20
    assign leftShiftStage0Idx1_uid24150_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24149_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15130_dupName_11_i_unnamed_c_compstr0_shift_x(BITSELECT,15129)@19
    assign rightShiftStage2Idx1Rng8_uid15130_dupName_11_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15129_dupName_11_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15132_dupName_11_i_unnamed_c_compstr0_shift_x(BITJOIN,15131)@19
    assign rightShiftStage2Idx1_uid15132_dupName_11_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15130_dupName_11_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15125_dupName_11_i_unnamed_c_compstr0_shift_x(BITSELECT,15124)@19
    assign rightShiftStage1Idx1Rng4_uid15125_dupName_11_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15124_dupName_11_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15127_dupName_11_i_unnamed_c_compstr0_shift_x(BITJOIN,15126)@19
    assign rightShiftStage1Idx1_uid15127_dupName_11_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15125_dupName_11_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15120_dupName_11_i_unnamed_c_compstr0_shift_x(BITSELECT,15119)@19
    assign rightShiftStage0Idx1Rng1_uid15120_dupName_11_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_q[33:1];

    // rightShiftStage0Idx1_uid15122_dupName_11_i_unnamed_c_compstr0_shift_x(BITJOIN,15121)@19
    assign rightShiftStage0Idx1_uid15122_dupName_11_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15120_dupName_11_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23961_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x(BITSELECT,23960)@18
    assign leftShiftStage2Idx1Rng8_uid23961_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_in = leftShiftStage1_uid23959_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23961_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23961_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23962_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x(BITJOIN,23961)@18
    assign leftShiftStage2Idx1_uid23962_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23961_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23956_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x(BITSELECT,23955)@18
    assign leftShiftStage1Idx1Rng4_uid23956_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_in = leftShiftStage0_uid23954_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23956_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23956_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23957_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x(BITJOIN,23956)@18
    assign leftShiftStage1Idx1_uid23957_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23956_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23951_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x(BITSELECT,23950)@18
    assign leftShiftStage0Idx1Rng1_uid23951_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_3_c_compstr102_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23951_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23951_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23952_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x(BITJOIN,23951)@18
    assign leftShiftStage0Idx1_uid23952_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23951_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15068_dupName_7_i_unnamed_c_compstr0_shift_x(BITSELECT,15067)@17
    assign rightShiftStage2Idx1Rng8_uid15068_dupName_7_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15067_dupName_7_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15070_dupName_7_i_unnamed_c_compstr0_shift_x(BITJOIN,15069)@17
    assign rightShiftStage2Idx1_uid15070_dupName_7_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15068_dupName_7_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15063_dupName_7_i_unnamed_c_compstr0_shift_x(BITSELECT,15062)@17
    assign rightShiftStage1Idx1Rng4_uid15063_dupName_7_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15062_dupName_7_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15065_dupName_7_i_unnamed_c_compstr0_shift_x(BITJOIN,15064)@17
    assign rightShiftStage1Idx1_uid15065_dupName_7_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15063_dupName_7_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15058_dupName_7_i_unnamed_c_compstr0_shift_x(BITSELECT,15057)@17
    assign rightShiftStage0Idx1Rng1_uid15058_dupName_7_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_q[33:1];

    // rightShiftStage0Idx1_uid15060_dupName_7_i_unnamed_c_compstr0_shift_x(BITJOIN,15059)@17
    assign rightShiftStage0Idx1_uid15060_dupName_7_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15058_dupName_7_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23763_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x(BITSELECT,23762)@16
    assign leftShiftStage2Idx1Rng8_uid23763_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_in = leftShiftStage1_uid23761_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23763_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23763_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23764_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x(BITJOIN,23763)@16
    assign leftShiftStage2Idx1_uid23764_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23763_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23758_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x(BITSELECT,23757)@16
    assign leftShiftStage1Idx1Rng4_uid23758_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_in = leftShiftStage0_uid23756_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23758_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23758_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23759_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x(BITJOIN,23758)@16
    assign leftShiftStage1Idx1_uid23759_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23758_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23753_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x(BITSELECT,23752)@16
    assign leftShiftStage0Idx1Rng1_uid23753_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_2_c_compstr74_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23753_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23753_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23754_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x(BITJOIN,23753)@16
    assign leftShiftStage0Idx1_uid23754_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23753_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15006_dupName_3_i_unnamed_c_compstr0_shift_x(BITSELECT,15005)@15
    assign rightShiftStage2Idx1Rng8_uid15006_dupName_3_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid15005_dupName_3_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15008_dupName_3_i_unnamed_c_compstr0_shift_x(BITJOIN,15007)@15
    assign rightShiftStage2Idx1_uid15008_dupName_3_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid15006_dupName_3_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15001_dupName_3_i_unnamed_c_compstr0_shift_x(BITSELECT,15000)@15
    assign rightShiftStage1Idx1Rng4_uid15001_dupName_3_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15000_dupName_3_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15003_dupName_3_i_unnamed_c_compstr0_shift_x(BITJOIN,15002)@15
    assign rightShiftStage1Idx1_uid15003_dupName_3_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid15001_dupName_3_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid14996_dupName_3_i_unnamed_c_compstr0_shift_x(BITSELECT,14995)@15
    assign rightShiftStage0Idx1Rng1_uid14996_dupName_3_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_q[33:1];

    // rightShiftStage0Idx1_uid14998_dupName_3_i_unnamed_c_compstr0_shift_x(BITJOIN,14997)@15
    assign rightShiftStage0Idx1_uid14998_dupName_3_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid14996_dupName_3_i_unnamed_c_compstr0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23565_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x(BITSELECT,23564)@14
    assign leftShiftStage2Idx1Rng8_uid23565_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_in = leftShiftStage1_uid23563_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23565_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_b = leftShiftStage2Idx1Rng8_uid23565_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23566_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x(BITJOIN,23565)@14
    assign leftShiftStage2Idx1_uid23566_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23565_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_b, rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23560_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x(BITSELECT,23559)@14
    assign leftShiftStage1Idx1Rng4_uid23560_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_in = leftShiftStage0_uid23558_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23560_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_b = leftShiftStage1Idx1Rng4_uid23560_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23561_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x(BITJOIN,23560)@14
    assign leftShiftStage1Idx1_uid23561_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23560_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_b, rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23555_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x(BITSELECT,23554)@14
    assign leftShiftStage0Idx1Rng1_uid23555_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_in = i_conv_i_i_i_i_i75_i277_1_c_compstr46_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23555_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_b = leftShiftStage0Idx1Rng1_uid23555_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23556_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x(BITJOIN,23555)@14
    assign leftShiftStage0Idx1_uid23556_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23555_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid27452_i_unnamed_c_compstr0_shift_x(BITSELECT,27451)@14
    assign rightShiftStage2Idx1Rng8_uid27452_i_unnamed_c_compstr0_shift_x_b = rightShiftStage1_uid27451_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid27454_i_unnamed_c_compstr0_shift_x(BITJOIN,27453)@14
    assign rightShiftStage2Idx1_uid27454_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage2Idx1Rng8_uid27452_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid27447_i_unnamed_c_compstr0_shift_x(BITSELECT,27446)@14
    assign rightShiftStage1Idx1Rng4_uid27447_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid27446_i_unnamed_c_compstr0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid27449_i_unnamed_c_compstr0_shift_x(BITJOIN,27448)@14
    assign rightShiftStage1Idx1_uid27449_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng4_uid27447_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid27442_i_unnamed_c_compstr0_shift_x(BITSELECT,27441)@14
    assign rightShiftStage0Idx1Rng1_uid27442_i_unnamed_c_compstr0_shift_x_b = i_conv_i_i_i84_i_c_compstr22_sel_x_b[33:1];

    // rightShiftStage0Idx1_uid27444_i_unnamed_c_compstr0_shift_x(BITJOIN,27443)@14
    assign rightShiftStage0Idx1_uid27444_i_unnamed_c_compstr0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid27442_i_unnamed_c_compstr0_shift_x_b};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma(CHAINMULTADD,28226)@8 + 5
    // out q@14
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ah[0] <= i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_1_tpl;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ah[1] <= i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_0_tpl;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ch[0] <= i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_1_tpl;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ch[1] <= i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_0_tpl;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_qq[32:0]);

    // i_conv_i_i_i84_i_c_compstr22_sel_x(BITSELECT,3456)@14
    assign i_conv_i_i_i84_i_c_compstr22_sel_x_b = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compstr19_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compstr21_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compstr20_merged_cma_q[32:0]});

    // rightShiftStage0_uid27446_i_unnamed_c_compstr0_shift_x(MUX,27445)@14
    assign rightShiftStage0_uid27446_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid27446_i_unnamed_c_compstr0_shift_x_s or i_conv_i_i_i84_i_c_compstr22_sel_x_b or rightShiftStage0Idx1_uid27444_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid27446_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid27446_i_unnamed_c_compstr0_shift_x_q = i_conv_i_i_i84_i_c_compstr22_sel_x_b;
            1'b1 : rightShiftStage0_uid27446_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid27444_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid27446_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid27451_i_unnamed_c_compstr0_shift_x(MUX,27450)@14
    assign rightShiftStage1_uid27451_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid27451_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid27446_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid27449_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid27451_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid27451_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid27446_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid27451_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid27449_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid27451_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid27456_i_unnamed_c_compstr0_shift_x(MUX,27455)@14
    assign rightShiftStage2_uid27456_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid27456_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid27451_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid27454_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid27456_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid27456_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid27451_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid27456_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid27454_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid27456_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr23_vt_select_20(BITSELECT,11015)@14
    assign i_unnamed_c_compstr23_vt_select_20_b = rightShiftStage2_uid27456_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr23_vt_join(BITJOIN,11014)@14
    assign i_unnamed_c_compstr23_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr23_vt_select_20_b};

    // i_conv_i_i_i_i97_i_c_compstr24_sel_x(BITSELECT,3584)@14
    assign i_conv_i_i_i_i97_i_c_compstr24_sel_x_b = i_unnamed_c_compstr23_vt_join_q[15:0];

    // rightShiftStage1Idx1Rng8_uid14957_dupName_0_i_unnamed_c_compstr0_shift_x(BITSELECT,14956)@14
    assign rightShiftStage1Idx1Rng8_uid14957_dupName_0_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid14956_dupName_0_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid14959_dupName_0_i_unnamed_c_compstr0_shift_x(BITJOIN,14958)@14
    assign rightShiftStage1Idx1_uid14959_dupName_0_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid14957_dupName_0_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid14952_dupName_0_i_unnamed_c_compstr0_shift_x(BITSELECT,14951)@14
    assign rightShiftStage0Idx1Rng4_uid14952_dupName_0_i_unnamed_c_compstr0_shift_x_b = i_conv_i_i_i84_i_c_compstr22_sel_x_b[33:4];

    // rightShiftStage0Idx1_uid14954_dupName_0_i_unnamed_c_compstr0_shift_x(BITJOIN,14953)@14
    assign rightShiftStage0Idx1_uid14954_dupName_0_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid14952_dupName_0_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid14956_dupName_0_i_unnamed_c_compstr0_shift_x(MUX,14955)@14
    assign rightShiftStage0_uid14956_dupName_0_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid14956_dupName_0_i_unnamed_c_compstr0_shift_x_s or i_conv_i_i_i84_i_c_compstr22_sel_x_b or rightShiftStage0Idx1_uid14954_dupName_0_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid14956_dupName_0_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid14956_dupName_0_i_unnamed_c_compstr0_shift_x_q = i_conv_i_i_i84_i_c_compstr22_sel_x_b;
            1'b1 : rightShiftStage0_uid14956_dupName_0_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid14954_dupName_0_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid14956_dupName_0_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid14961_dupName_0_i_unnamed_c_compstr0_shift_x(MUX,14960)@14
    assign rightShiftStage1_uid14961_dupName_0_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid14961_dupName_0_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid14956_dupName_0_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid14959_dupName_0_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid14961_dupName_0_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid14961_dupName_0_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid14956_dupName_0_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid14961_dupName_0_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid14959_dupName_0_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid14961_dupName_0_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr25_vt_select_21(BITSELECT,11189)@14
    assign i_unnamed_c_compstr25_vt_select_21_b = rightShiftStage1_uid14961_dupName_0_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr25_vt_join(BITJOIN,11188)@14
    assign i_unnamed_c_compstr25_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr25_vt_select_21_b};

    // i_unnamed_c_compstr26_sel_x(BITSELECT,6160)@14
    assign i_unnamed_c_compstr26_sel_x_b = i_unnamed_c_compstr25_vt_join_q[15:0];

    // i_unnamed_c_compstr27_BitSelect_for_a(BITSELECT,27725)@14
    assign i_unnamed_c_compstr27_BitSelect_for_a_b = i_unnamed_c_compstr26_sel_x_b[0:0];

    // i_unnamed_c_compstr27_join(BITJOIN,27726)@14
    assign i_unnamed_c_compstr27_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr27_BitSelect_for_a_b};

    // i_unnamed_c_compstr27_vt_select_0(BITSELECT,11375)@14
    assign i_unnamed_c_compstr27_vt_select_0_b = i_unnamed_c_compstr27_join_q[0:0];

    // i_unnamed_c_compstr27_vt_join(BITJOIN,11374)@14
    assign i_unnamed_c_compstr27_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, i_unnamed_c_compstr27_vt_select_0_b};

    // i_add_i_i_i_i_i126_i_c_compstr28(ADD,6979)@14
    assign i_add_i_i_i_i_i126_i_c_compstr28_a = {1'b0, i_unnamed_c_compstr27_vt_join_q};
    assign i_add_i_i_i_i_i126_i_c_compstr28_b = {1'b0, i_conv_i_i_i_i97_i_c_compstr24_sel_x_b};
    assign i_add_i_i_i_i_i126_i_c_compstr28_o = $unsigned(i_add_i_i_i_i_i126_i_c_compstr28_a) + $unsigned(i_add_i_i_i_i_i126_i_c_compstr28_b);
    assign i_add_i_i_i_i_i126_i_c_compstr28_q = i_add_i_i_i_i_i126_i_c_compstr28_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_c_compstr28_sel_x(BITSELECT,2173)@14
    assign bgTrunc_i_add_i_i_i_i_i126_i_c_compstr28_sel_x_b = i_add_i_i_i_i_i126_i_c_compstr28_q[15:0];

    // i_conv_i_i_i_i_i75_i277_1_c_compstr46_sel_x(BITSELECT,3624)@14
    assign i_conv_i_i_i_i_i75_i277_1_c_compstr46_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_c_compstr28_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_1_c_compstr46_vt_select_15(BITSELECT,7397)@14
    assign i_conv_i_i_i_i_i75_i277_1_c_compstr46_vt_select_15_b = i_conv_i_i_i_i_i75_i277_1_c_compstr46_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_1_c_compstr46_vt_join(BITJOIN,7396)@14
    assign i_conv_i_i_i_i_i75_i277_1_c_compstr46_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_1_c_compstr46_vt_select_15_b};

    // leftShiftStage0_uid23558_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x(MUX,23557)@14
    assign leftShiftStage0_uid23558_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23558_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_1_c_compstr46_vt_join_q or leftShiftStage0Idx1_uid23556_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23558_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23558_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_1_c_compstr46_vt_join_q;
            1'b1 : leftShiftStage0_uid23558_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23556_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23558_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23563_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x(MUX,23562)@14
    assign leftShiftStage1_uid23563_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23563_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_s or leftShiftStage0_uid23558_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23561_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23563_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23563_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q = leftShiftStage0_uid23558_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23563_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23561_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23563_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23568_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x(MUX,23567)@14
    assign leftShiftStage2_uid23568_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23568_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_s or leftShiftStage1_uid23563_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23566_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23568_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23568_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q = leftShiftStage1_uid23563_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23568_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23566_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23568_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_1_c_compstr47_vt_select_28(BITSELECT,9157)@14
    assign i_shl_i_i_i_i_i77_i_1_c_compstr47_vt_select_28_b = leftShiftStage2_uid23568_i_shl_i_i_i_i_i77_i_1_c_compstr0_shift_x_q[28:13];

    // redist471_i_shl_i_i_i_i_i77_i_1_c_compstr47_vt_select_28_b_1(DELAY,28699)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist471_i_shl_i_i_i_i_i77_i_1_c_compstr47_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_1_c_compstr47_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_1_c_compstr47_vt_join(BITJOIN,9156)@15
    assign i_shl_i_i_i_i_i77_i_1_c_compstr47_vt_join_q = {redist471_i_shl_i_i_i_i_i77_i_1_c_compstr47_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma(CHAINMULTADD,28137)@9 + 5
    // out q@15
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ah[0] <= redist773_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_3_tpl_1_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ah[1] <= redist772_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_2_tpl_1_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ch[0] <= redist519_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_3_tpl_1_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ch[1] <= redist518_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_2_tpl_1_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48(ADD,8433)@15
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compstr43_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compstr45_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compstr44_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_1_c_compstr47_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_1_c_compstr47_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_o[33:0];

    // rightShiftStage0_uid15000_dupName_3_i_unnamed_c_compstr0_shift_x(MUX,14999)@15
    assign rightShiftStage0_uid15000_dupName_3_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15000_dupName_3_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_q or rightShiftStage0Idx1_uid14998_dupName_3_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15000_dupName_3_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15000_dupName_3_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_q;
            1'b1 : rightShiftStage0_uid15000_dupName_3_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid14998_dupName_3_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15000_dupName_3_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15005_dupName_3_i_unnamed_c_compstr0_shift_x(MUX,15004)@15
    assign rightShiftStage1_uid15005_dupName_3_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15005_dupName_3_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15000_dupName_3_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15003_dupName_3_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15005_dupName_3_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15005_dupName_3_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15000_dupName_3_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15005_dupName_3_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15003_dupName_3_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15005_dupName_3_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15010_dupName_3_i_unnamed_c_compstr0_shift_x(MUX,15009)@15
    assign rightShiftStage2_uid15010_dupName_3_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15010_dupName_3_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15005_dupName_3_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15008_dupName_3_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15010_dupName_3_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15010_dupName_3_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15005_dupName_3_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15010_dupName_3_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15008_dupName_3_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15010_dupName_3_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr49_vt_select_20(BITSELECT,12187)@15
    assign i_unnamed_c_compstr49_vt_select_20_b = rightShiftStage2_uid15010_dupName_3_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr49_vt_join(BITJOIN,12186)@15
    assign i_unnamed_c_compstr49_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr49_vt_select_20_b};

    // i_conv_i_i_i_i97_i_1_c_compstr50_sel_x(BITSELECT,3495)@15
    assign i_conv_i_i_i_i97_i_1_c_compstr50_sel_x_b = i_unnamed_c_compstr49_vt_join_q[15:0];

    // redist1241_i_conv_i_i_i_i97_i_1_c_compstr50_sel_x_b_1(DELAY,29469)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1241_i_conv_i_i_i_i97_i_1_c_compstr50_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_1_c_compstr50_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15019_dupName_4_i_unnamed_c_compstr0_shift_x(BITSELECT,15018)@15
    assign rightShiftStage1Idx1Rng8_uid15019_dupName_4_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15018_dupName_4_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15021_dupName_4_i_unnamed_c_compstr0_shift_x(BITJOIN,15020)@15
    assign rightShiftStage1Idx1_uid15021_dupName_4_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15019_dupName_4_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15014_dupName_4_i_unnamed_c_compstr0_shift_x(BITSELECT,15013)@15
    assign rightShiftStage0Idx1Rng4_uid15014_dupName_4_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_q[33:4];

    // rightShiftStage0Idx1_uid15016_dupName_4_i_unnamed_c_compstr0_shift_x(BITJOIN,15015)@15
    assign rightShiftStage0Idx1_uid15016_dupName_4_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15014_dupName_4_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15018_dupName_4_i_unnamed_c_compstr0_shift_x(MUX,15017)@15
    assign rightShiftStage0_uid15018_dupName_4_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15018_dupName_4_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_q or rightShiftStage0Idx1_uid15016_dupName_4_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15018_dupName_4_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15018_dupName_4_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compstr48_q;
            1'b1 : rightShiftStage0_uid15018_dupName_4_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15016_dupName_4_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15018_dupName_4_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15023_dupName_4_i_unnamed_c_compstr0_shift_x(MUX,15022)@15
    assign rightShiftStage1_uid15023_dupName_4_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15023_dupName_4_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15018_dupName_4_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15021_dupName_4_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15023_dupName_4_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15023_dupName_4_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15018_dupName_4_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15023_dupName_4_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15021_dupName_4_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15023_dupName_4_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr51_vt_select_21(BITSELECT,12206)@15
    assign i_unnamed_c_compstr51_vt_select_21_b = rightShiftStage1_uid15023_dupName_4_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr51_vt_join(BITJOIN,12205)@15
    assign i_unnamed_c_compstr51_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr51_vt_select_21_b};

    // i_unnamed_c_compstr52_sel_x(BITSELECT,6253)@15
    assign i_unnamed_c_compstr52_sel_x_b = i_unnamed_c_compstr51_vt_join_q[15:0];

    // i_unnamed_c_compstr53_BitSelect_for_a(BITSELECT,27897)@15
    assign i_unnamed_c_compstr53_BitSelect_for_a_b = i_unnamed_c_compstr52_sel_x_b[0:0];

    // i_unnamed_c_compstr53_join(BITJOIN,27898)@15
    assign i_unnamed_c_compstr53_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr53_BitSelect_for_a_b};

    // i_unnamed_c_compstr53_vt_select_0(BITSELECT,12222)@15
    assign i_unnamed_c_compstr53_vt_select_0_b = i_unnamed_c_compstr53_join_q[0:0];

    // redist38_i_unnamed_c_compstr53_vt_select_0_b_1(DELAY,28266)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist38_i_unnamed_c_compstr53_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr53_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr53_vt_join(BITJOIN,12221)@16
    assign i_unnamed_c_compstr53_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist38_i_unnamed_c_compstr53_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_1_c_compstr54(ADD,6890)@16
    assign i_add_i_i_i_i_i126_i_1_c_compstr54_a = {1'b0, i_unnamed_c_compstr53_vt_join_q};
    assign i_add_i_i_i_i_i126_i_1_c_compstr54_b = {1'b0, redist1241_i_conv_i_i_i_i97_i_1_c_compstr50_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_1_c_compstr54_o = $unsigned(i_add_i_i_i_i_i126_i_1_c_compstr54_a) + $unsigned(i_add_i_i_i_i_i126_i_1_c_compstr54_b);
    assign i_add_i_i_i_i_i126_i_1_c_compstr54_q = i_add_i_i_i_i_i126_i_1_c_compstr54_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_1_c_compstr54_sel_x(BITSELECT,2084)@16
    assign bgTrunc_i_add_i_i_i_i_i126_i_1_c_compstr54_sel_x_b = i_add_i_i_i_i_i126_i_1_c_compstr54_q[15:0];

    // i_conv_i_i_i_i_i75_i277_2_c_compstr74_sel_x(BITSELECT,3635)@16
    assign i_conv_i_i_i_i_i75_i277_2_c_compstr74_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_1_c_compstr54_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_2_c_compstr74_vt_select_15(BITSELECT,7441)@16
    assign i_conv_i_i_i_i_i75_i277_2_c_compstr74_vt_select_15_b = i_conv_i_i_i_i_i75_i277_2_c_compstr74_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_2_c_compstr74_vt_join(BITJOIN,7440)@16
    assign i_conv_i_i_i_i_i75_i277_2_c_compstr74_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_2_c_compstr74_vt_select_15_b};

    // leftShiftStage0_uid23756_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x(MUX,23755)@16
    assign leftShiftStage0_uid23756_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23756_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_2_c_compstr74_vt_join_q or leftShiftStage0Idx1_uid23754_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23756_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23756_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_2_c_compstr74_vt_join_q;
            1'b1 : leftShiftStage0_uid23756_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23754_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23756_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23761_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x(MUX,23760)@16
    assign leftShiftStage1_uid23761_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23761_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_s or leftShiftStage0_uid23756_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23759_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23761_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23761_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q = leftShiftStage0_uid23756_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23761_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23759_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23761_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23766_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x(MUX,23765)@16
    assign leftShiftStage2_uid23766_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23766_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_s or leftShiftStage1_uid23761_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23764_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23766_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23766_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q = leftShiftStage1_uid23761_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23766_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23764_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23766_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_2_c_compstr75_vt_select_28(BITSELECT,9190)@16
    assign i_shl_i_i_i_i_i77_i_2_c_compstr75_vt_select_28_b = leftShiftStage2_uid23766_i_shl_i_i_i_i_i77_i_2_c_compstr0_shift_x_q[28:13];

    // redist460_i_shl_i_i_i_i_i77_i_2_c_compstr75_vt_select_28_b_1(DELAY,28688)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist460_i_shl_i_i_i_i_i77_i_2_c_compstr75_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_2_c_compstr75_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_2_c_compstr75_vt_join(BITJOIN,9189)@17
    assign i_shl_i_i_i_i_i77_i_2_c_compstr75_vt_join_q = {redist460_i_shl_i_i_i_i_i77_i_2_c_compstr75_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma(CHAINMULTADD,28148)@11 + 5
    // out q@17
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ah[0] <= redist775_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_5_tpl_3_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ah[1] <= redist774_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_4_tpl_3_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ch[0] <= redist521_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_5_tpl_3_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ch[1] <= redist520_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_4_tpl_3_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76(ADD,8444)@17
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compstr71_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compstr73_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compstr72_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_2_c_compstr75_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_2_c_compstr75_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_o[33:0];

    // rightShiftStage0_uid15062_dupName_7_i_unnamed_c_compstr0_shift_x(MUX,15061)@17
    assign rightShiftStage0_uid15062_dupName_7_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15062_dupName_7_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_q or rightShiftStage0Idx1_uid15060_dupName_7_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15062_dupName_7_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15062_dupName_7_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_q;
            1'b1 : rightShiftStage0_uid15062_dupName_7_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15060_dupName_7_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15062_dupName_7_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15067_dupName_7_i_unnamed_c_compstr0_shift_x(MUX,15066)@17
    assign rightShiftStage1_uid15067_dupName_7_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15067_dupName_7_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15062_dupName_7_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15065_dupName_7_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15067_dupName_7_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15067_dupName_7_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15062_dupName_7_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15067_dupName_7_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15065_dupName_7_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15067_dupName_7_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15072_dupName_7_i_unnamed_c_compstr0_shift_x(MUX,15071)@17
    assign rightShiftStage2_uid15072_dupName_7_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15072_dupName_7_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15067_dupName_7_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15070_dupName_7_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15072_dupName_7_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15072_dupName_7_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15067_dupName_7_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15072_dupName_7_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15070_dupName_7_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15072_dupName_7_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr77_vt_select_20(BITSELECT,12429)@17
    assign i_unnamed_c_compstr77_vt_select_20_b = rightShiftStage2_uid15072_dupName_7_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr77_vt_join(BITJOIN,12428)@17
    assign i_unnamed_c_compstr77_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr77_vt_select_20_b};

    // i_conv_i_i_i_i97_i_2_c_compstr78_sel_x(BITSELECT,3506)@17
    assign i_conv_i_i_i_i97_i_2_c_compstr78_sel_x_b = i_unnamed_c_compstr77_vt_join_q[15:0];

    // redist1230_i_conv_i_i_i_i97_i_2_c_compstr78_sel_x_b_1(DELAY,29458)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1230_i_conv_i_i_i_i97_i_2_c_compstr78_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_2_c_compstr78_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15081_dupName_8_i_unnamed_c_compstr0_shift_x(BITSELECT,15080)@17
    assign rightShiftStage1Idx1Rng8_uid15081_dupName_8_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15080_dupName_8_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15083_dupName_8_i_unnamed_c_compstr0_shift_x(BITJOIN,15082)@17
    assign rightShiftStage1Idx1_uid15083_dupName_8_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15081_dupName_8_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15076_dupName_8_i_unnamed_c_compstr0_shift_x(BITSELECT,15075)@17
    assign rightShiftStage0Idx1Rng4_uid15076_dupName_8_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_q[33:4];

    // rightShiftStage0Idx1_uid15078_dupName_8_i_unnamed_c_compstr0_shift_x(BITJOIN,15077)@17
    assign rightShiftStage0Idx1_uid15078_dupName_8_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15076_dupName_8_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15080_dupName_8_i_unnamed_c_compstr0_shift_x(MUX,15079)@17
    assign rightShiftStage0_uid15080_dupName_8_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15080_dupName_8_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_q or rightShiftStage0Idx1_uid15078_dupName_8_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15080_dupName_8_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15080_dupName_8_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compstr76_q;
            1'b1 : rightShiftStage0_uid15080_dupName_8_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15078_dupName_8_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15080_dupName_8_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15085_dupName_8_i_unnamed_c_compstr0_shift_x(MUX,15084)@17
    assign rightShiftStage1_uid15085_dupName_8_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15085_dupName_8_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15080_dupName_8_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15083_dupName_8_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15085_dupName_8_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15085_dupName_8_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15080_dupName_8_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15085_dupName_8_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15083_dupName_8_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15085_dupName_8_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr79_vt_select_21(BITSELECT,12448)@17
    assign i_unnamed_c_compstr79_vt_select_21_b = rightShiftStage1_uid15085_dupName_8_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr79_vt_join(BITJOIN,12447)@17
    assign i_unnamed_c_compstr79_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr79_vt_select_21_b};

    // i_unnamed_c_compstr80_sel_x(BITSELECT,6275)@17
    assign i_unnamed_c_compstr80_sel_x_b = i_unnamed_c_compstr79_vt_join_q[15:0];

    // i_unnamed_c_compstr81_BitSelect_for_a(BITSELECT,27941)@17
    assign i_unnamed_c_compstr81_BitSelect_for_a_b = i_unnamed_c_compstr80_sel_x_b[0:0];

    // i_unnamed_c_compstr81_join(BITJOIN,27942)@17
    assign i_unnamed_c_compstr81_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr81_BitSelect_for_a_b};

    // i_unnamed_c_compstr81_vt_select_0(BITSELECT,12464)@17
    assign i_unnamed_c_compstr81_vt_select_0_b = i_unnamed_c_compstr81_join_q[0:0];

    // redist16_i_unnamed_c_compstr81_vt_select_0_b_1(DELAY,28244)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist16_i_unnamed_c_compstr81_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr81_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr81_vt_join(BITJOIN,12463)@18
    assign i_unnamed_c_compstr81_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist16_i_unnamed_c_compstr81_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_2_c_compstr82(ADD,6901)@18
    assign i_add_i_i_i_i_i126_i_2_c_compstr82_a = {1'b0, i_unnamed_c_compstr81_vt_join_q};
    assign i_add_i_i_i_i_i126_i_2_c_compstr82_b = {1'b0, redist1230_i_conv_i_i_i_i97_i_2_c_compstr78_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_2_c_compstr82_o = $unsigned(i_add_i_i_i_i_i126_i_2_c_compstr82_a) + $unsigned(i_add_i_i_i_i_i126_i_2_c_compstr82_b);
    assign i_add_i_i_i_i_i126_i_2_c_compstr82_q = i_add_i_i_i_i_i126_i_2_c_compstr82_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_2_c_compstr82_sel_x(BITSELECT,2095)@18
    assign bgTrunc_i_add_i_i_i_i_i126_i_2_c_compstr82_sel_x_b = i_add_i_i_i_i_i126_i_2_c_compstr82_q[15:0];

    // i_conv_i_i_i_i_i75_i277_3_c_compstr102_sel_x(BITSELECT,3646)@18
    assign i_conv_i_i_i_i_i75_i277_3_c_compstr102_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_2_c_compstr82_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_3_c_compstr102_vt_select_15(BITSELECT,7485)@18
    assign i_conv_i_i_i_i_i75_i277_3_c_compstr102_vt_select_15_b = i_conv_i_i_i_i_i75_i277_3_c_compstr102_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_3_c_compstr102_vt_join(BITJOIN,7484)@18
    assign i_conv_i_i_i_i_i75_i277_3_c_compstr102_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_3_c_compstr102_vt_select_15_b};

    // leftShiftStage0_uid23954_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x(MUX,23953)@18
    assign leftShiftStage0_uid23954_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23954_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_3_c_compstr102_vt_join_q or leftShiftStage0Idx1_uid23952_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23954_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23954_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_3_c_compstr102_vt_join_q;
            1'b1 : leftShiftStage0_uid23954_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23952_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23954_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23959_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x(MUX,23958)@18
    assign leftShiftStage1_uid23959_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23959_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_s or leftShiftStage0_uid23954_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23957_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23959_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23959_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q = leftShiftStage0_uid23954_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23959_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23957_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23959_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23964_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x(MUX,23963)@18
    assign leftShiftStage2_uid23964_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23964_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_s or leftShiftStage1_uid23959_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23962_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23964_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23964_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q = leftShiftStage1_uid23959_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23964_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23962_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23964_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_3_c_compstr103_vt_select_28(BITSELECT,9223)@18
    assign i_shl_i_i_i_i_i77_i_3_c_compstr103_vt_select_28_b = leftShiftStage2_uid23964_i_shl_i_i_i_i_i77_i_3_c_compstr0_shift_x_q[28:13];

    // redist449_i_shl_i_i_i_i_i77_i_3_c_compstr103_vt_select_28_b_1(DELAY,28677)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist449_i_shl_i_i_i_i_i77_i_3_c_compstr103_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_3_c_compstr103_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_3_c_compstr103_vt_join(BITJOIN,9222)@19
    assign i_shl_i_i_i_i_i77_i_3_c_compstr103_vt_join_q = {redist449_i_shl_i_i_i_i_i77_i_3_c_compstr103_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma(CHAINMULTADD,28159)@13 + 5
    // out q@19
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ah[0] <= redist777_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_7_tpl_5_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ah[1] <= redist776_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_6_tpl_5_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ch[0] <= redist523_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_7_tpl_5_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ch[1] <= redist522_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_6_tpl_5_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104(ADD,8455)@19
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compstr99_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compstr101_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compstr100_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_3_c_compstr103_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_3_c_compstr103_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_o[33:0];

    // rightShiftStage0_uid15124_dupName_11_i_unnamed_c_compstr0_shift_x(MUX,15123)@19
    assign rightShiftStage0_uid15124_dupName_11_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15124_dupName_11_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_q or rightShiftStage0Idx1_uid15122_dupName_11_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15124_dupName_11_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15124_dupName_11_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_q;
            1'b1 : rightShiftStage0_uid15124_dupName_11_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15122_dupName_11_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15124_dupName_11_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15129_dupName_11_i_unnamed_c_compstr0_shift_x(MUX,15128)@19
    assign rightShiftStage1_uid15129_dupName_11_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15129_dupName_11_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15124_dupName_11_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15127_dupName_11_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15129_dupName_11_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15129_dupName_11_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15124_dupName_11_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15129_dupName_11_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15127_dupName_11_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15129_dupName_11_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15134_dupName_11_i_unnamed_c_compstr0_shift_x(MUX,15133)@19
    assign rightShiftStage2_uid15134_dupName_11_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15134_dupName_11_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15129_dupName_11_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15132_dupName_11_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15134_dupName_11_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15134_dupName_11_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15129_dupName_11_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15134_dupName_11_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15132_dupName_11_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15134_dupName_11_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr105_vt_select_20(BITSELECT,9855)@19
    assign i_unnamed_c_compstr105_vt_select_20_b = rightShiftStage2_uid15134_dupName_11_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr105_vt_join(BITJOIN,9854)@19
    assign i_unnamed_c_compstr105_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr105_vt_select_20_b};

    // i_conv_i_i_i_i97_i_3_c_compstr106_sel_x(BITSELECT,3517)@19
    assign i_conv_i_i_i_i97_i_3_c_compstr106_sel_x_b = i_unnamed_c_compstr105_vt_join_q[15:0];

    // redist1219_i_conv_i_i_i_i97_i_3_c_compstr106_sel_x_b_1(DELAY,29447)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1219_i_conv_i_i_i_i97_i_3_c_compstr106_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_3_c_compstr106_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15143_dupName_12_i_unnamed_c_compstr0_shift_x(BITSELECT,15142)@19
    assign rightShiftStage1Idx1Rng8_uid15143_dupName_12_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15142_dupName_12_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15145_dupName_12_i_unnamed_c_compstr0_shift_x(BITJOIN,15144)@19
    assign rightShiftStage1Idx1_uid15145_dupName_12_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15143_dupName_12_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15138_dupName_12_i_unnamed_c_compstr0_shift_x(BITSELECT,15137)@19
    assign rightShiftStage0Idx1Rng4_uid15138_dupName_12_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_q[33:4];

    // rightShiftStage0Idx1_uid15140_dupName_12_i_unnamed_c_compstr0_shift_x(BITJOIN,15139)@19
    assign rightShiftStage0Idx1_uid15140_dupName_12_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15138_dupName_12_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15142_dupName_12_i_unnamed_c_compstr0_shift_x(MUX,15141)@19
    assign rightShiftStage0_uid15142_dupName_12_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15142_dupName_12_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_q or rightShiftStage0Idx1_uid15140_dupName_12_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15142_dupName_12_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15142_dupName_12_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compstr104_q;
            1'b1 : rightShiftStage0_uid15142_dupName_12_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15140_dupName_12_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15142_dupName_12_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15147_dupName_12_i_unnamed_c_compstr0_shift_x(MUX,15146)@19
    assign rightShiftStage1_uid15147_dupName_12_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15147_dupName_12_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15142_dupName_12_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15145_dupName_12_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15147_dupName_12_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15147_dupName_12_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15142_dupName_12_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15147_dupName_12_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15145_dupName_12_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15147_dupName_12_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr107_vt_select_21(BITSELECT,9874)@19
    assign i_unnamed_c_compstr107_vt_select_21_b = rightShiftStage1_uid15147_dupName_12_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr107_vt_join(BITJOIN,9873)@19
    assign i_unnamed_c_compstr107_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr107_vt_select_21_b};

    // i_unnamed_c_compstr108_sel_x(BITSELECT,6041)@19
    assign i_unnamed_c_compstr108_sel_x_b = i_unnamed_c_compstr107_vt_join_q[15:0];

    // i_unnamed_c_compstr109_BitSelect_for_a(BITSELECT,27473)@19
    assign i_unnamed_c_compstr109_BitSelect_for_a_b = i_unnamed_c_compstr108_sel_x_b[0:0];

    // i_unnamed_c_compstr109_join(BITJOIN,27474)@19
    assign i_unnamed_c_compstr109_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr109_BitSelect_for_a_b};

    // i_unnamed_c_compstr109_vt_select_0(BITSELECT,9890)@19
    assign i_unnamed_c_compstr109_vt_select_0_b = i_unnamed_c_compstr109_join_q[0:0];

    // redist248_i_unnamed_c_compstr109_vt_select_0_b_1(DELAY,28476)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist248_i_unnamed_c_compstr109_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr109_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr109_vt_join(BITJOIN,9889)@20
    assign i_unnamed_c_compstr109_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist248_i_unnamed_c_compstr109_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_3_c_compstr110(ADD,6912)@20
    assign i_add_i_i_i_i_i126_i_3_c_compstr110_a = {1'b0, i_unnamed_c_compstr109_vt_join_q};
    assign i_add_i_i_i_i_i126_i_3_c_compstr110_b = {1'b0, redist1219_i_conv_i_i_i_i97_i_3_c_compstr106_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_3_c_compstr110_o = $unsigned(i_add_i_i_i_i_i126_i_3_c_compstr110_a) + $unsigned(i_add_i_i_i_i_i126_i_3_c_compstr110_b);
    assign i_add_i_i_i_i_i126_i_3_c_compstr110_q = i_add_i_i_i_i_i126_i_3_c_compstr110_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_3_c_compstr110_sel_x(BITSELECT,2106)@20
    assign bgTrunc_i_add_i_i_i_i_i126_i_3_c_compstr110_sel_x_b = i_add_i_i_i_i_i126_i_3_c_compstr110_q[15:0];

    // i_conv_i_i_i_i_i75_i277_4_c_compstr130_sel_x(BITSELECT,3657)@20
    assign i_conv_i_i_i_i_i75_i277_4_c_compstr130_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_3_c_compstr110_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_4_c_compstr130_vt_select_15(BITSELECT,7529)@20
    assign i_conv_i_i_i_i_i75_i277_4_c_compstr130_vt_select_15_b = i_conv_i_i_i_i_i75_i277_4_c_compstr130_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_4_c_compstr130_vt_join(BITJOIN,7528)@20
    assign i_conv_i_i_i_i_i75_i277_4_c_compstr130_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_4_c_compstr130_vt_select_15_b};

    // leftShiftStage0_uid24152_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x(MUX,24151)@20
    assign leftShiftStage0_uid24152_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24152_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_4_c_compstr130_vt_join_q or leftShiftStage0Idx1_uid24150_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24152_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24152_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_4_c_compstr130_vt_join_q;
            1'b1 : leftShiftStage0_uid24152_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24150_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24152_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24157_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x(MUX,24156)@20
    assign leftShiftStage1_uid24157_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24157_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_s or leftShiftStage0_uid24152_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24155_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24157_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24157_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q = leftShiftStage0_uid24152_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24157_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24155_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24157_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24162_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x(MUX,24161)@20
    assign leftShiftStage2_uid24162_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24162_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_s or leftShiftStage1_uid24157_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24160_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24162_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24162_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q = leftShiftStage1_uid24157_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24162_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24160_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24162_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_4_c_compstr131_vt_select_28(BITSELECT,9256)@20
    assign i_shl_i_i_i_i_i77_i_4_c_compstr131_vt_select_28_b = leftShiftStage2_uid24162_i_shl_i_i_i_i_i77_i_4_c_compstr0_shift_x_q[28:13];

    // redist438_i_shl_i_i_i_i_i77_i_4_c_compstr131_vt_select_28_b_1(DELAY,28666)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist438_i_shl_i_i_i_i_i77_i_4_c_compstr131_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_4_c_compstr131_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_4_c_compstr131_vt_join(BITJOIN,9255)@21
    assign i_shl_i_i_i_i_i77_i_4_c_compstr131_vt_join_q = {redist438_i_shl_i_i_i_i_i77_i_4_c_compstr131_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma(CHAINMULTADD,28170)@15 + 5
    // out q@21
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ah[0] <= redist779_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_9_tpl_7_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ah[1] <= redist778_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_8_tpl_7_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ch[0] <= redist525_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_9_tpl_7_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ch[1] <= redist524_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_8_tpl_7_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132(ADD,8466)@21
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compstr127_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compstr129_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compstr128_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_4_c_compstr131_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_4_c_compstr131_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_o[33:0];

    // rightShiftStage0_uid15186_dupName_15_i_unnamed_c_compstr0_shift_x(MUX,15185)@21
    assign rightShiftStage0_uid15186_dupName_15_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15186_dupName_15_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_q or rightShiftStage0Idx1_uid15184_dupName_15_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15186_dupName_15_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15186_dupName_15_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_q;
            1'b1 : rightShiftStage0_uid15186_dupName_15_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15184_dupName_15_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15186_dupName_15_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15191_dupName_15_i_unnamed_c_compstr0_shift_x(MUX,15190)@21
    assign rightShiftStage1_uid15191_dupName_15_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15191_dupName_15_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15186_dupName_15_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15189_dupName_15_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15191_dupName_15_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15191_dupName_15_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15186_dupName_15_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15191_dupName_15_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15189_dupName_15_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15191_dupName_15_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15196_dupName_15_i_unnamed_c_compstr0_shift_x(MUX,15195)@21
    assign rightShiftStage2_uid15196_dupName_15_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15196_dupName_15_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15191_dupName_15_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15194_dupName_15_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15196_dupName_15_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15196_dupName_15_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15191_dupName_15_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15196_dupName_15_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15194_dupName_15_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15196_dupName_15_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr133_vt_select_20(BITSELECT,10097)@21
    assign i_unnamed_c_compstr133_vt_select_20_b = rightShiftStage2_uid15196_dupName_15_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr133_vt_join(BITJOIN,10096)@21
    assign i_unnamed_c_compstr133_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr133_vt_select_20_b};

    // i_conv_i_i_i_i97_i_4_c_compstr134_sel_x(BITSELECT,3528)@21
    assign i_conv_i_i_i_i97_i_4_c_compstr134_sel_x_b = i_unnamed_c_compstr133_vt_join_q[15:0];

    // redist1208_i_conv_i_i_i_i97_i_4_c_compstr134_sel_x_b_1(DELAY,29436)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1208_i_conv_i_i_i_i97_i_4_c_compstr134_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_4_c_compstr134_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15205_dupName_16_i_unnamed_c_compstr0_shift_x(BITSELECT,15204)@21
    assign rightShiftStage1Idx1Rng8_uid15205_dupName_16_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15204_dupName_16_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15207_dupName_16_i_unnamed_c_compstr0_shift_x(BITJOIN,15206)@21
    assign rightShiftStage1Idx1_uid15207_dupName_16_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15205_dupName_16_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15200_dupName_16_i_unnamed_c_compstr0_shift_x(BITSELECT,15199)@21
    assign rightShiftStage0Idx1Rng4_uid15200_dupName_16_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_q[33:4];

    // rightShiftStage0Idx1_uid15202_dupName_16_i_unnamed_c_compstr0_shift_x(BITJOIN,15201)@21
    assign rightShiftStage0Idx1_uid15202_dupName_16_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15200_dupName_16_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15204_dupName_16_i_unnamed_c_compstr0_shift_x(MUX,15203)@21
    assign rightShiftStage0_uid15204_dupName_16_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15204_dupName_16_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_q or rightShiftStage0Idx1_uid15202_dupName_16_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15204_dupName_16_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15204_dupName_16_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compstr132_q;
            1'b1 : rightShiftStage0_uid15204_dupName_16_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15202_dupName_16_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15204_dupName_16_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15209_dupName_16_i_unnamed_c_compstr0_shift_x(MUX,15208)@21
    assign rightShiftStage1_uid15209_dupName_16_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15209_dupName_16_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15204_dupName_16_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15207_dupName_16_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15209_dupName_16_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15209_dupName_16_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15204_dupName_16_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15209_dupName_16_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15207_dupName_16_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15209_dupName_16_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr135_vt_select_21(BITSELECT,10116)@21
    assign i_unnamed_c_compstr135_vt_select_21_b = rightShiftStage1_uid15209_dupName_16_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr135_vt_join(BITJOIN,10115)@21
    assign i_unnamed_c_compstr135_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr135_vt_select_21_b};

    // i_unnamed_c_compstr136_sel_x(BITSELECT,6063)@21
    assign i_unnamed_c_compstr136_sel_x_b = i_unnamed_c_compstr135_vt_join_q[15:0];

    // i_unnamed_c_compstr137_BitSelect_for_a(BITSELECT,27517)@21
    assign i_unnamed_c_compstr137_BitSelect_for_a_b = i_unnamed_c_compstr136_sel_x_b[0:0];

    // i_unnamed_c_compstr137_join(BITJOIN,27518)@21
    assign i_unnamed_c_compstr137_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr137_BitSelect_for_a_b};

    // i_unnamed_c_compstr137_vt_select_0(BITSELECT,10132)@21
    assign i_unnamed_c_compstr137_vt_select_0_b = i_unnamed_c_compstr137_join_q[0:0];

    // redist226_i_unnamed_c_compstr137_vt_select_0_b_1(DELAY,28454)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist226_i_unnamed_c_compstr137_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr137_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr137_vt_join(BITJOIN,10131)@22
    assign i_unnamed_c_compstr137_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist226_i_unnamed_c_compstr137_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_4_c_compstr138(ADD,6923)@22
    assign i_add_i_i_i_i_i126_i_4_c_compstr138_a = {1'b0, i_unnamed_c_compstr137_vt_join_q};
    assign i_add_i_i_i_i_i126_i_4_c_compstr138_b = {1'b0, redist1208_i_conv_i_i_i_i97_i_4_c_compstr134_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_4_c_compstr138_o = $unsigned(i_add_i_i_i_i_i126_i_4_c_compstr138_a) + $unsigned(i_add_i_i_i_i_i126_i_4_c_compstr138_b);
    assign i_add_i_i_i_i_i126_i_4_c_compstr138_q = i_add_i_i_i_i_i126_i_4_c_compstr138_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_4_c_compstr138_sel_x(BITSELECT,2117)@22
    assign bgTrunc_i_add_i_i_i_i_i126_i_4_c_compstr138_sel_x_b = i_add_i_i_i_i_i126_i_4_c_compstr138_q[15:0];

    // i_conv_i_i_i_i_i75_i277_5_c_compstr158_sel_x(BITSELECT,3668)@22
    assign i_conv_i_i_i_i_i75_i277_5_c_compstr158_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_4_c_compstr138_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_5_c_compstr158_vt_select_15(BITSELECT,7573)@22
    assign i_conv_i_i_i_i_i75_i277_5_c_compstr158_vt_select_15_b = i_conv_i_i_i_i_i75_i277_5_c_compstr158_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_5_c_compstr158_vt_join(BITJOIN,7572)@22
    assign i_conv_i_i_i_i_i75_i277_5_c_compstr158_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_5_c_compstr158_vt_select_15_b};

    // leftShiftStage0_uid24350_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x(MUX,24349)@22
    assign leftShiftStage0_uid24350_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24350_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_5_c_compstr158_vt_join_q or leftShiftStage0Idx1_uid24348_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24350_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24350_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_5_c_compstr158_vt_join_q;
            1'b1 : leftShiftStage0_uid24350_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24348_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24350_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24355_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x(MUX,24354)@22
    assign leftShiftStage1_uid24355_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24355_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_s or leftShiftStage0_uid24350_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24353_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24355_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24355_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q = leftShiftStage0_uid24350_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24355_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24353_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24355_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24360_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x(MUX,24359)@22
    assign leftShiftStage2_uid24360_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24360_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_s or leftShiftStage1_uid24355_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24358_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24360_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24360_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q = leftShiftStage1_uid24355_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24360_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24358_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24360_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_5_c_compstr159_vt_select_28(BITSELECT,9289)@22
    assign i_shl_i_i_i_i_i77_i_5_c_compstr159_vt_select_28_b = leftShiftStage2_uid24360_i_shl_i_i_i_i_i77_i_5_c_compstr0_shift_x_q[28:13];

    // redist427_i_shl_i_i_i_i_i77_i_5_c_compstr159_vt_select_28_b_1(DELAY,28655)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist427_i_shl_i_i_i_i_i77_i_5_c_compstr159_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_5_c_compstr159_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_5_c_compstr159_vt_join(BITJOIN,9288)@23
    assign i_shl_i_i_i_i_i77_i_5_c_compstr159_vt_join_q = {redist427_i_shl_i_i_i_i_i77_i_5_c_compstr159_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma(CHAINMULTADD,28181)@17 + 5
    // out q@23
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ah[0] <= redist781_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_11_tpl_9_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ah[1] <= redist780_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_10_tpl_9_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ch[0] <= redist527_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_11_tpl_9_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ch[1] <= redist526_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_10_tpl_9_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160(ADD,8477)@23
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compstr155_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compstr157_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compstr156_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_5_c_compstr159_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_5_c_compstr159_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_o[33:0];

    // rightShiftStage0_uid15248_dupName_19_i_unnamed_c_compstr0_shift_x(MUX,15247)@23
    assign rightShiftStage0_uid15248_dupName_19_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15248_dupName_19_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_q or rightShiftStage0Idx1_uid15246_dupName_19_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15248_dupName_19_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15248_dupName_19_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_q;
            1'b1 : rightShiftStage0_uid15248_dupName_19_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15246_dupName_19_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15248_dupName_19_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15253_dupName_19_i_unnamed_c_compstr0_shift_x(MUX,15252)@23
    assign rightShiftStage1_uid15253_dupName_19_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15253_dupName_19_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15248_dupName_19_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15251_dupName_19_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15253_dupName_19_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15253_dupName_19_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15248_dupName_19_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15253_dupName_19_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15251_dupName_19_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15253_dupName_19_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15258_dupName_19_i_unnamed_c_compstr0_shift_x(MUX,15257)@23
    assign rightShiftStage2_uid15258_dupName_19_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15258_dupName_19_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15253_dupName_19_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15256_dupName_19_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15258_dupName_19_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15258_dupName_19_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15253_dupName_19_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15258_dupName_19_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15256_dupName_19_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15258_dupName_19_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr161_vt_select_20(BITSELECT,10339)@23
    assign i_unnamed_c_compstr161_vt_select_20_b = rightShiftStage2_uid15258_dupName_19_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr161_vt_join(BITJOIN,10338)@23
    assign i_unnamed_c_compstr161_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr161_vt_select_20_b};

    // i_conv_i_i_i_i97_i_5_c_compstr162_sel_x(BITSELECT,3539)@23
    assign i_conv_i_i_i_i97_i_5_c_compstr162_sel_x_b = i_unnamed_c_compstr161_vt_join_q[15:0];

    // redist1197_i_conv_i_i_i_i97_i_5_c_compstr162_sel_x_b_1(DELAY,29425)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1197_i_conv_i_i_i_i97_i_5_c_compstr162_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_5_c_compstr162_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15267_dupName_20_i_unnamed_c_compstr0_shift_x(BITSELECT,15266)@23
    assign rightShiftStage1Idx1Rng8_uid15267_dupName_20_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15266_dupName_20_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15269_dupName_20_i_unnamed_c_compstr0_shift_x(BITJOIN,15268)@23
    assign rightShiftStage1Idx1_uid15269_dupName_20_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15267_dupName_20_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15262_dupName_20_i_unnamed_c_compstr0_shift_x(BITSELECT,15261)@23
    assign rightShiftStage0Idx1Rng4_uid15262_dupName_20_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_q[33:4];

    // rightShiftStage0Idx1_uid15264_dupName_20_i_unnamed_c_compstr0_shift_x(BITJOIN,15263)@23
    assign rightShiftStage0Idx1_uid15264_dupName_20_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15262_dupName_20_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15266_dupName_20_i_unnamed_c_compstr0_shift_x(MUX,15265)@23
    assign rightShiftStage0_uid15266_dupName_20_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15266_dupName_20_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_q or rightShiftStage0Idx1_uid15264_dupName_20_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15266_dupName_20_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15266_dupName_20_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compstr160_q;
            1'b1 : rightShiftStage0_uid15266_dupName_20_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15264_dupName_20_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15266_dupName_20_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15271_dupName_20_i_unnamed_c_compstr0_shift_x(MUX,15270)@23
    assign rightShiftStage1_uid15271_dupName_20_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15271_dupName_20_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15266_dupName_20_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15269_dupName_20_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15271_dupName_20_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15271_dupName_20_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15266_dupName_20_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15271_dupName_20_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15269_dupName_20_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15271_dupName_20_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr163_vt_select_21(BITSELECT,10358)@23
    assign i_unnamed_c_compstr163_vt_select_21_b = rightShiftStage1_uid15271_dupName_20_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr163_vt_join(BITJOIN,10357)@23
    assign i_unnamed_c_compstr163_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr163_vt_select_21_b};

    // i_unnamed_c_compstr164_sel_x(BITSELECT,6085)@23
    assign i_unnamed_c_compstr164_sel_x_b = i_unnamed_c_compstr163_vt_join_q[15:0];

    // i_unnamed_c_compstr165_BitSelect_for_a(BITSELECT,27561)@23
    assign i_unnamed_c_compstr165_BitSelect_for_a_b = i_unnamed_c_compstr164_sel_x_b[0:0];

    // i_unnamed_c_compstr165_join(BITJOIN,27562)@23
    assign i_unnamed_c_compstr165_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr165_BitSelect_for_a_b};

    // i_unnamed_c_compstr165_vt_select_0(BITSELECT,10374)@23
    assign i_unnamed_c_compstr165_vt_select_0_b = i_unnamed_c_compstr165_join_q[0:0];

    // redist204_i_unnamed_c_compstr165_vt_select_0_b_1(DELAY,28432)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist204_i_unnamed_c_compstr165_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr165_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr165_vt_join(BITJOIN,10373)@24
    assign i_unnamed_c_compstr165_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist204_i_unnamed_c_compstr165_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_5_c_compstr166(ADD,6934)@24
    assign i_add_i_i_i_i_i126_i_5_c_compstr166_a = {1'b0, i_unnamed_c_compstr165_vt_join_q};
    assign i_add_i_i_i_i_i126_i_5_c_compstr166_b = {1'b0, redist1197_i_conv_i_i_i_i97_i_5_c_compstr162_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_5_c_compstr166_o = $unsigned(i_add_i_i_i_i_i126_i_5_c_compstr166_a) + $unsigned(i_add_i_i_i_i_i126_i_5_c_compstr166_b);
    assign i_add_i_i_i_i_i126_i_5_c_compstr166_q = i_add_i_i_i_i_i126_i_5_c_compstr166_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_5_c_compstr166_sel_x(BITSELECT,2128)@24
    assign bgTrunc_i_add_i_i_i_i_i126_i_5_c_compstr166_sel_x_b = i_add_i_i_i_i_i126_i_5_c_compstr166_q[15:0];

    // i_conv_i_i_i_i_i75_i277_6_c_compstr186_sel_x(BITSELECT,3679)@24
    assign i_conv_i_i_i_i_i75_i277_6_c_compstr186_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_5_c_compstr166_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_6_c_compstr186_vt_select_15(BITSELECT,7617)@24
    assign i_conv_i_i_i_i_i75_i277_6_c_compstr186_vt_select_15_b = i_conv_i_i_i_i_i75_i277_6_c_compstr186_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_6_c_compstr186_vt_join(BITJOIN,7616)@24
    assign i_conv_i_i_i_i_i75_i277_6_c_compstr186_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_6_c_compstr186_vt_select_15_b};

    // leftShiftStage0_uid24548_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x(MUX,24547)@24
    assign leftShiftStage0_uid24548_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24548_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_6_c_compstr186_vt_join_q or leftShiftStage0Idx1_uid24546_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24548_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24548_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_6_c_compstr186_vt_join_q;
            1'b1 : leftShiftStage0_uid24548_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24546_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24548_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24553_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x(MUX,24552)@24
    assign leftShiftStage1_uid24553_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24553_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_s or leftShiftStage0_uid24548_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24551_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24553_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24553_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q = leftShiftStage0_uid24548_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24553_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24551_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24553_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24558_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x(MUX,24557)@24
    assign leftShiftStage2_uid24558_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24558_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_s or leftShiftStage1_uid24553_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24556_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24558_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24558_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q = leftShiftStage1_uid24553_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24558_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24556_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24558_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_6_c_compstr187_vt_select_28(BITSELECT,9322)@24
    assign i_shl_i_i_i_i_i77_i_6_c_compstr187_vt_select_28_b = leftShiftStage2_uid24558_i_shl_i_i_i_i_i77_i_6_c_compstr0_shift_x_q[28:13];

    // redist416_i_shl_i_i_i_i_i77_i_6_c_compstr187_vt_select_28_b_1(DELAY,28644)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist416_i_shl_i_i_i_i_i77_i_6_c_compstr187_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_6_c_compstr187_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_6_c_compstr187_vt_join(BITJOIN,9321)@25
    assign i_shl_i_i_i_i_i77_i_6_c_compstr187_vt_join_q = {redist416_i_shl_i_i_i_i_i77_i_6_c_compstr187_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma(CHAINMULTADD,28192)@19 + 5
    // out q@25
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ah[0] <= redist783_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_13_tpl_11_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ah[1] <= redist782_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_12_tpl_11_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ch[0] <= redist529_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_13_tpl_11_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ch[1] <= redist528_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_12_tpl_11_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188(ADD,8488)@25
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compstr183_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compstr185_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compstr184_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_6_c_compstr187_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_6_c_compstr187_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_o[33:0];

    // rightShiftStage0_uid15310_dupName_23_i_unnamed_c_compstr0_shift_x(MUX,15309)@25
    assign rightShiftStage0_uid15310_dupName_23_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15310_dupName_23_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_q or rightShiftStage0Idx1_uid15308_dupName_23_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15310_dupName_23_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15310_dupName_23_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_q;
            1'b1 : rightShiftStage0_uid15310_dupName_23_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15308_dupName_23_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15310_dupName_23_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15315_dupName_23_i_unnamed_c_compstr0_shift_x(MUX,15314)@25
    assign rightShiftStage1_uid15315_dupName_23_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15315_dupName_23_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15310_dupName_23_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15313_dupName_23_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15315_dupName_23_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15315_dupName_23_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15310_dupName_23_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15315_dupName_23_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15313_dupName_23_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15315_dupName_23_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15320_dupName_23_i_unnamed_c_compstr0_shift_x(MUX,15319)@25
    assign rightShiftStage2_uid15320_dupName_23_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15320_dupName_23_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15315_dupName_23_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15318_dupName_23_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15320_dupName_23_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15320_dupName_23_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15315_dupName_23_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15320_dupName_23_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15318_dupName_23_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15320_dupName_23_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr189_vt_select_20(BITSELECT,10581)@25
    assign i_unnamed_c_compstr189_vt_select_20_b = rightShiftStage2_uid15320_dupName_23_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr189_vt_join(BITJOIN,10580)@25
    assign i_unnamed_c_compstr189_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr189_vt_select_20_b};

    // i_conv_i_i_i_i97_i_6_c_compstr190_sel_x(BITSELECT,3550)@25
    assign i_conv_i_i_i_i97_i_6_c_compstr190_sel_x_b = i_unnamed_c_compstr189_vt_join_q[15:0];

    // redist1186_i_conv_i_i_i_i97_i_6_c_compstr190_sel_x_b_1(DELAY,29414)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1186_i_conv_i_i_i_i97_i_6_c_compstr190_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_6_c_compstr190_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15329_dupName_24_i_unnamed_c_compstr0_shift_x(BITSELECT,15328)@25
    assign rightShiftStage1Idx1Rng8_uid15329_dupName_24_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15328_dupName_24_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15331_dupName_24_i_unnamed_c_compstr0_shift_x(BITJOIN,15330)@25
    assign rightShiftStage1Idx1_uid15331_dupName_24_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15329_dupName_24_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15324_dupName_24_i_unnamed_c_compstr0_shift_x(BITSELECT,15323)@25
    assign rightShiftStage0Idx1Rng4_uid15324_dupName_24_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_q[33:4];

    // rightShiftStage0Idx1_uid15326_dupName_24_i_unnamed_c_compstr0_shift_x(BITJOIN,15325)@25
    assign rightShiftStage0Idx1_uid15326_dupName_24_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15324_dupName_24_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15328_dupName_24_i_unnamed_c_compstr0_shift_x(MUX,15327)@25
    assign rightShiftStage0_uid15328_dupName_24_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15328_dupName_24_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_q or rightShiftStage0Idx1_uid15326_dupName_24_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15328_dupName_24_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15328_dupName_24_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compstr188_q;
            1'b1 : rightShiftStage0_uid15328_dupName_24_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15326_dupName_24_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15328_dupName_24_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15333_dupName_24_i_unnamed_c_compstr0_shift_x(MUX,15332)@25
    assign rightShiftStage1_uid15333_dupName_24_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15333_dupName_24_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15328_dupName_24_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15331_dupName_24_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15333_dupName_24_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15333_dupName_24_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15328_dupName_24_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15333_dupName_24_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15331_dupName_24_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15333_dupName_24_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr191_vt_select_21(BITSELECT,10600)@25
    assign i_unnamed_c_compstr191_vt_select_21_b = rightShiftStage1_uid15333_dupName_24_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr191_vt_join(BITJOIN,10599)@25
    assign i_unnamed_c_compstr191_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr191_vt_select_21_b};

    // i_unnamed_c_compstr192_sel_x(BITSELECT,6107)@25
    assign i_unnamed_c_compstr192_sel_x_b = i_unnamed_c_compstr191_vt_join_q[15:0];

    // i_unnamed_c_compstr193_BitSelect_for_a(BITSELECT,27605)@25
    assign i_unnamed_c_compstr193_BitSelect_for_a_b = i_unnamed_c_compstr192_sel_x_b[0:0];

    // i_unnamed_c_compstr193_join(BITJOIN,27606)@25
    assign i_unnamed_c_compstr193_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr193_BitSelect_for_a_b};

    // i_unnamed_c_compstr193_vt_select_0(BITSELECT,10616)@25
    assign i_unnamed_c_compstr193_vt_select_0_b = i_unnamed_c_compstr193_join_q[0:0];

    // redist182_i_unnamed_c_compstr193_vt_select_0_b_1(DELAY,28410)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist182_i_unnamed_c_compstr193_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr193_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr193_vt_join(BITJOIN,10615)@26
    assign i_unnamed_c_compstr193_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist182_i_unnamed_c_compstr193_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_6_c_compstr194(ADD,6945)@26
    assign i_add_i_i_i_i_i126_i_6_c_compstr194_a = {1'b0, i_unnamed_c_compstr193_vt_join_q};
    assign i_add_i_i_i_i_i126_i_6_c_compstr194_b = {1'b0, redist1186_i_conv_i_i_i_i97_i_6_c_compstr190_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_6_c_compstr194_o = $unsigned(i_add_i_i_i_i_i126_i_6_c_compstr194_a) + $unsigned(i_add_i_i_i_i_i126_i_6_c_compstr194_b);
    assign i_add_i_i_i_i_i126_i_6_c_compstr194_q = i_add_i_i_i_i_i126_i_6_c_compstr194_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_6_c_compstr194_sel_x(BITSELECT,2139)@26
    assign bgTrunc_i_add_i_i_i_i_i126_i_6_c_compstr194_sel_x_b = i_add_i_i_i_i_i126_i_6_c_compstr194_q[15:0];

    // i_conv_i_i_i_i_i75_i277_7_c_compstr214_sel_x(BITSELECT,3690)@26
    assign i_conv_i_i_i_i_i75_i277_7_c_compstr214_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_6_c_compstr194_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_7_c_compstr214_vt_select_15(BITSELECT,7661)@26
    assign i_conv_i_i_i_i_i75_i277_7_c_compstr214_vt_select_15_b = i_conv_i_i_i_i_i75_i277_7_c_compstr214_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_7_c_compstr214_vt_join(BITJOIN,7660)@26
    assign i_conv_i_i_i_i_i75_i277_7_c_compstr214_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_7_c_compstr214_vt_select_15_b};

    // leftShiftStage0_uid24746_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x(MUX,24745)@26
    assign leftShiftStage0_uid24746_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24746_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_7_c_compstr214_vt_join_q or leftShiftStage0Idx1_uid24744_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24746_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24746_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_7_c_compstr214_vt_join_q;
            1'b1 : leftShiftStage0_uid24746_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24744_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24746_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24751_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x(MUX,24750)@26
    assign leftShiftStage1_uid24751_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24751_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_s or leftShiftStage0_uid24746_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24749_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24751_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24751_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q = leftShiftStage0_uid24746_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24751_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24749_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24751_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24756_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x(MUX,24755)@26
    assign leftShiftStage2_uid24756_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24756_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_s or leftShiftStage1_uid24751_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24754_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24756_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24756_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q = leftShiftStage1_uid24751_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24756_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24754_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24756_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_7_c_compstr215_vt_select_28(BITSELECT,9355)@26
    assign i_shl_i_i_i_i_i77_i_7_c_compstr215_vt_select_28_b = leftShiftStage2_uid24756_i_shl_i_i_i_i_i77_i_7_c_compstr0_shift_x_q[28:13];

    // redist405_i_shl_i_i_i_i_i77_i_7_c_compstr215_vt_select_28_b_1(DELAY,28633)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist405_i_shl_i_i_i_i_i77_i_7_c_compstr215_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_7_c_compstr215_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_7_c_compstr215_vt_join(BITJOIN,9354)@27
    assign i_shl_i_i_i_i_i77_i_7_c_compstr215_vt_join_q = {redist405_i_shl_i_i_i_i_i77_i_7_c_compstr215_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma(CHAINMULTADD,28203)@21 + 5
    // out q@27
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ah[0] <= redist785_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_15_tpl_13_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ah[1] <= redist784_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_14_tpl_13_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ch[0] <= redist531_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_15_tpl_13_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ch[1] <= redist530_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_14_tpl_13_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216(ADD,8499)@27
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compstr211_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compstr213_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compstr212_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_7_c_compstr215_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_7_c_compstr215_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_o[33:0];

    // rightShiftStage0_uid15372_dupName_27_i_unnamed_c_compstr0_shift_x(MUX,15371)@27
    assign rightShiftStage0_uid15372_dupName_27_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15372_dupName_27_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_q or rightShiftStage0Idx1_uid15370_dupName_27_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15372_dupName_27_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15372_dupName_27_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_q;
            1'b1 : rightShiftStage0_uid15372_dupName_27_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15370_dupName_27_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15372_dupName_27_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15377_dupName_27_i_unnamed_c_compstr0_shift_x(MUX,15376)@27
    assign rightShiftStage1_uid15377_dupName_27_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15377_dupName_27_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15372_dupName_27_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15375_dupName_27_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15377_dupName_27_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15377_dupName_27_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15372_dupName_27_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15377_dupName_27_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15375_dupName_27_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15377_dupName_27_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15382_dupName_27_i_unnamed_c_compstr0_shift_x(MUX,15381)@27
    assign rightShiftStage2_uid15382_dupName_27_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15382_dupName_27_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15377_dupName_27_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15380_dupName_27_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15382_dupName_27_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15382_dupName_27_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15377_dupName_27_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15382_dupName_27_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15380_dupName_27_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15382_dupName_27_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr217_vt_select_20(BITSELECT,10823)@27
    assign i_unnamed_c_compstr217_vt_select_20_b = rightShiftStage2_uid15382_dupName_27_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr217_vt_join(BITJOIN,10822)@27
    assign i_unnamed_c_compstr217_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr217_vt_select_20_b};

    // i_conv_i_i_i_i97_i_7_c_compstr218_sel_x(BITSELECT,3561)@27
    assign i_conv_i_i_i_i97_i_7_c_compstr218_sel_x_b = i_unnamed_c_compstr217_vt_join_q[15:0];

    // redist1175_i_conv_i_i_i_i97_i_7_c_compstr218_sel_x_b_1(DELAY,29403)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1175_i_conv_i_i_i_i97_i_7_c_compstr218_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_7_c_compstr218_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15391_dupName_28_i_unnamed_c_compstr0_shift_x(BITSELECT,15390)@27
    assign rightShiftStage1Idx1Rng8_uid15391_dupName_28_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15390_dupName_28_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15393_dupName_28_i_unnamed_c_compstr0_shift_x(BITJOIN,15392)@27
    assign rightShiftStage1Idx1_uid15393_dupName_28_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15391_dupName_28_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15386_dupName_28_i_unnamed_c_compstr0_shift_x(BITSELECT,15385)@27
    assign rightShiftStage0Idx1Rng4_uid15386_dupName_28_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_q[33:4];

    // rightShiftStage0Idx1_uid15388_dupName_28_i_unnamed_c_compstr0_shift_x(BITJOIN,15387)@27
    assign rightShiftStage0Idx1_uid15388_dupName_28_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15386_dupName_28_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15390_dupName_28_i_unnamed_c_compstr0_shift_x(MUX,15389)@27
    assign rightShiftStage0_uid15390_dupName_28_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15390_dupName_28_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_q or rightShiftStage0Idx1_uid15388_dupName_28_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15390_dupName_28_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15390_dupName_28_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compstr216_q;
            1'b1 : rightShiftStage0_uid15390_dupName_28_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15388_dupName_28_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15390_dupName_28_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15395_dupName_28_i_unnamed_c_compstr0_shift_x(MUX,15394)@27
    assign rightShiftStage1_uid15395_dupName_28_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15395_dupName_28_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15390_dupName_28_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15393_dupName_28_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15395_dupName_28_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15395_dupName_28_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15390_dupName_28_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15395_dupName_28_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15393_dupName_28_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15395_dupName_28_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr219_vt_select_21(BITSELECT,10842)@27
    assign i_unnamed_c_compstr219_vt_select_21_b = rightShiftStage1_uid15395_dupName_28_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr219_vt_join(BITJOIN,10841)@27
    assign i_unnamed_c_compstr219_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr219_vt_select_21_b};

    // i_unnamed_c_compstr220_sel_x(BITSELECT,6129)@27
    assign i_unnamed_c_compstr220_sel_x_b = i_unnamed_c_compstr219_vt_join_q[15:0];

    // i_unnamed_c_compstr221_BitSelect_for_a(BITSELECT,27649)@27
    assign i_unnamed_c_compstr221_BitSelect_for_a_b = i_unnamed_c_compstr220_sel_x_b[0:0];

    // i_unnamed_c_compstr221_join(BITJOIN,27650)@27
    assign i_unnamed_c_compstr221_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr221_BitSelect_for_a_b};

    // i_unnamed_c_compstr221_vt_select_0(BITSELECT,10858)@27
    assign i_unnamed_c_compstr221_vt_select_0_b = i_unnamed_c_compstr221_join_q[0:0];

    // redist160_i_unnamed_c_compstr221_vt_select_0_b_1(DELAY,28388)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist160_i_unnamed_c_compstr221_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr221_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr221_vt_join(BITJOIN,10857)@28
    assign i_unnamed_c_compstr221_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist160_i_unnamed_c_compstr221_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_7_c_compstr222(ADD,6956)@28
    assign i_add_i_i_i_i_i126_i_7_c_compstr222_a = {1'b0, i_unnamed_c_compstr221_vt_join_q};
    assign i_add_i_i_i_i_i126_i_7_c_compstr222_b = {1'b0, redist1175_i_conv_i_i_i_i97_i_7_c_compstr218_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_7_c_compstr222_o = $unsigned(i_add_i_i_i_i_i126_i_7_c_compstr222_a) + $unsigned(i_add_i_i_i_i_i126_i_7_c_compstr222_b);
    assign i_add_i_i_i_i_i126_i_7_c_compstr222_q = i_add_i_i_i_i_i126_i_7_c_compstr222_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_7_c_compstr222_sel_x(BITSELECT,2150)@28
    assign bgTrunc_i_add_i_i_i_i_i126_i_7_c_compstr222_sel_x_b = i_add_i_i_i_i_i126_i_7_c_compstr222_q[15:0];

    // i_conv_i_i_i_i_i75_i277_8_c_compstr242_sel_x(BITSELECT,3701)@28
    assign i_conv_i_i_i_i_i75_i277_8_c_compstr242_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_7_c_compstr222_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_8_c_compstr242_vt_select_15(BITSELECT,7705)@28
    assign i_conv_i_i_i_i_i75_i277_8_c_compstr242_vt_select_15_b = i_conv_i_i_i_i_i75_i277_8_c_compstr242_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_8_c_compstr242_vt_join(BITJOIN,7704)@28
    assign i_conv_i_i_i_i_i75_i277_8_c_compstr242_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_8_c_compstr242_vt_select_15_b};

    // leftShiftStage0_uid24944_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x(MUX,24943)@28
    assign leftShiftStage0_uid24944_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24944_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_8_c_compstr242_vt_join_q or leftShiftStage0Idx1_uid24942_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24944_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24944_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_8_c_compstr242_vt_join_q;
            1'b1 : leftShiftStage0_uid24944_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24942_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24944_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24949_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x(MUX,24948)@28
    assign leftShiftStage1_uid24949_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24949_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_s or leftShiftStage0_uid24944_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24947_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24949_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24949_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q = leftShiftStage0_uid24944_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24949_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24947_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24949_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24954_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x(MUX,24953)@28
    assign leftShiftStage2_uid24954_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24954_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_s or leftShiftStage1_uid24949_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24952_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24954_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24954_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q = leftShiftStage1_uid24949_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24954_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24952_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24954_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_8_c_compstr243_vt_select_28(BITSELECT,9388)@28
    assign i_shl_i_i_i_i_i77_i_8_c_compstr243_vt_select_28_b = leftShiftStage2_uid24954_i_shl_i_i_i_i_i77_i_8_c_compstr0_shift_x_q[28:13];

    // redist394_i_shl_i_i_i_i_i77_i_8_c_compstr243_vt_select_28_b_1(DELAY,28622)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist394_i_shl_i_i_i_i_i77_i_8_c_compstr243_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_8_c_compstr243_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_8_c_compstr243_vt_join(BITJOIN,9387)@29
    assign i_shl_i_i_i_i_i77_i_8_c_compstr243_vt_join_q = {redist394_i_shl_i_i_i_i_i77_i_8_c_compstr243_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma(CHAINMULTADD,28214)@23 + 5
    // out q@29
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ah[0] <= redist787_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_17_tpl_15_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ah[1] <= redist786_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_16_tpl_15_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ch[0] <= redist533_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_17_tpl_15_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ch[1] <= redist532_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_16_tpl_15_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244(ADD,8510)@29
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compstr239_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compstr241_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compstr240_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_8_c_compstr243_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_8_c_compstr243_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_o[33:0];

    // rightShiftStage0_uid15434_dupName_31_i_unnamed_c_compstr0_shift_x(MUX,15433)@29
    assign rightShiftStage0_uid15434_dupName_31_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15434_dupName_31_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_q or rightShiftStage0Idx1_uid15432_dupName_31_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15434_dupName_31_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15434_dupName_31_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_q;
            1'b1 : rightShiftStage0_uid15434_dupName_31_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15432_dupName_31_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15434_dupName_31_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15439_dupName_31_i_unnamed_c_compstr0_shift_x(MUX,15438)@29
    assign rightShiftStage1_uid15439_dupName_31_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15439_dupName_31_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15434_dupName_31_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15437_dupName_31_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15439_dupName_31_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15439_dupName_31_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15434_dupName_31_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15439_dupName_31_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15437_dupName_31_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15439_dupName_31_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15444_dupName_31_i_unnamed_c_compstr0_shift_x(MUX,15443)@29
    assign rightShiftStage2_uid15444_dupName_31_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15444_dupName_31_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15439_dupName_31_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15442_dupName_31_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15444_dupName_31_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15444_dupName_31_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15439_dupName_31_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15444_dupName_31_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15442_dupName_31_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15444_dupName_31_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr245_vt_select_20(BITSELECT,11068)@29
    assign i_unnamed_c_compstr245_vt_select_20_b = rightShiftStage2_uid15444_dupName_31_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr245_vt_join(BITJOIN,11067)@29
    assign i_unnamed_c_compstr245_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr245_vt_select_20_b};

    // i_conv_i_i_i_i97_i_8_c_compstr246_sel_x(BITSELECT,3572)@29
    assign i_conv_i_i_i_i97_i_8_c_compstr246_sel_x_b = i_unnamed_c_compstr245_vt_join_q[15:0];

    // redist1164_i_conv_i_i_i_i97_i_8_c_compstr246_sel_x_b_1(DELAY,29392)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1164_i_conv_i_i_i_i97_i_8_c_compstr246_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_8_c_compstr246_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15453_dupName_32_i_unnamed_c_compstr0_shift_x(BITSELECT,15452)@29
    assign rightShiftStage1Idx1Rng8_uid15453_dupName_32_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15452_dupName_32_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15455_dupName_32_i_unnamed_c_compstr0_shift_x(BITJOIN,15454)@29
    assign rightShiftStage1Idx1_uid15455_dupName_32_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15453_dupName_32_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15448_dupName_32_i_unnamed_c_compstr0_shift_x(BITSELECT,15447)@29
    assign rightShiftStage0Idx1Rng4_uid15448_dupName_32_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_q[33:4];

    // rightShiftStage0Idx1_uid15450_dupName_32_i_unnamed_c_compstr0_shift_x(BITJOIN,15449)@29
    assign rightShiftStage0Idx1_uid15450_dupName_32_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15448_dupName_32_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15452_dupName_32_i_unnamed_c_compstr0_shift_x(MUX,15451)@29
    assign rightShiftStage0_uid15452_dupName_32_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15452_dupName_32_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_q or rightShiftStage0Idx1_uid15450_dupName_32_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15452_dupName_32_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15452_dupName_32_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compstr244_q;
            1'b1 : rightShiftStage0_uid15452_dupName_32_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15450_dupName_32_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15452_dupName_32_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15457_dupName_32_i_unnamed_c_compstr0_shift_x(MUX,15456)@29
    assign rightShiftStage1_uid15457_dupName_32_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15457_dupName_32_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15452_dupName_32_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15455_dupName_32_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15457_dupName_32_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15457_dupName_32_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15452_dupName_32_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15457_dupName_32_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15455_dupName_32_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15457_dupName_32_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr247_vt_select_21(BITSELECT,11087)@29
    assign i_unnamed_c_compstr247_vt_select_21_b = rightShiftStage1_uid15457_dupName_32_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr247_vt_join(BITJOIN,11086)@29
    assign i_unnamed_c_compstr247_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr247_vt_select_21_b};

    // i_unnamed_c_compstr248_sel_x(BITSELECT,6151)@29
    assign i_unnamed_c_compstr248_sel_x_b = i_unnamed_c_compstr247_vt_join_q[15:0];

    // i_unnamed_c_compstr249_BitSelect_for_a(BITSELECT,27693)@29
    assign i_unnamed_c_compstr249_BitSelect_for_a_b = i_unnamed_c_compstr248_sel_x_b[0:0];

    // i_unnamed_c_compstr249_join(BITJOIN,27694)@29
    assign i_unnamed_c_compstr249_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr249_BitSelect_for_a_b};

    // i_unnamed_c_compstr249_vt_select_0(BITSELECT,11103)@29
    assign i_unnamed_c_compstr249_vt_select_0_b = i_unnamed_c_compstr249_join_q[0:0];

    // redist138_i_unnamed_c_compstr249_vt_select_0_b_1(DELAY,28366)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist138_i_unnamed_c_compstr249_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr249_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr249_vt_join(BITJOIN,11102)@30
    assign i_unnamed_c_compstr249_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist138_i_unnamed_c_compstr249_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_8_c_compstr250(ADD,6967)@30
    assign i_add_i_i_i_i_i126_i_8_c_compstr250_a = {1'b0, i_unnamed_c_compstr249_vt_join_q};
    assign i_add_i_i_i_i_i126_i_8_c_compstr250_b = {1'b0, redist1164_i_conv_i_i_i_i97_i_8_c_compstr246_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_8_c_compstr250_o = $unsigned(i_add_i_i_i_i_i126_i_8_c_compstr250_a) + $unsigned(i_add_i_i_i_i_i126_i_8_c_compstr250_b);
    assign i_add_i_i_i_i_i126_i_8_c_compstr250_q = i_add_i_i_i_i_i126_i_8_c_compstr250_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_8_c_compstr250_sel_x(BITSELECT,2161)@30
    assign bgTrunc_i_add_i_i_i_i_i126_i_8_c_compstr250_sel_x_b = i_add_i_i_i_i_i126_i_8_c_compstr250_q[15:0];

    // i_conv_i_i_i_i_i75_i277_9_c_compstr270_sel_x(BITSELECT,3712)@30
    assign i_conv_i_i_i_i_i75_i277_9_c_compstr270_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_8_c_compstr250_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_9_c_compstr270_vt_select_15(BITSELECT,7749)@30
    assign i_conv_i_i_i_i_i75_i277_9_c_compstr270_vt_select_15_b = i_conv_i_i_i_i_i75_i277_9_c_compstr270_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_9_c_compstr270_vt_join(BITJOIN,7748)@30
    assign i_conv_i_i_i_i_i75_i277_9_c_compstr270_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_9_c_compstr270_vt_select_15_b};

    // leftShiftStage0_uid25142_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x(MUX,25141)@30
    assign leftShiftStage0_uid25142_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25142_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_9_c_compstr270_vt_join_q or leftShiftStage0Idx1_uid25140_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25142_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25142_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_9_c_compstr270_vt_join_q;
            1'b1 : leftShiftStage0_uid25142_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25140_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25142_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25147_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x(MUX,25146)@30
    assign leftShiftStage1_uid25147_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25147_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_s or leftShiftStage0_uid25142_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25145_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25147_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25147_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q = leftShiftStage0_uid25142_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25147_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25145_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25147_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25152_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x(MUX,25151)@30
    assign leftShiftStage2_uid25152_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25152_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_s or leftShiftStage1_uid25147_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25150_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25152_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25152_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q = leftShiftStage1_uid25147_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25152_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25150_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25152_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_9_c_compstr271_vt_select_28(BITSELECT,9421)@30
    assign i_shl_i_i_i_i_i77_i_9_c_compstr271_vt_select_28_b = leftShiftStage2_uid25152_i_shl_i_i_i_i_i77_i_9_c_compstr0_shift_x_q[28:13];

    // redist383_i_shl_i_i_i_i_i77_i_9_c_compstr271_vt_select_28_b_1(DELAY,28611)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist383_i_shl_i_i_i_i_i77_i_9_c_compstr271_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_9_c_compstr271_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_9_c_compstr271_vt_join(BITJOIN,9420)@31
    assign i_shl_i_i_i_i_i77_i_9_c_compstr271_vt_join_q = {redist383_i_shl_i_i_i_i_i77_i_9_c_compstr271_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma(CHAINMULTADD,28225)@25 + 5
    // out q@31
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ah[0] <= redist789_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_19_tpl_17_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ah[1] <= redist788_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_18_tpl_17_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ch[0] <= redist535_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_19_tpl_17_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ch[1] <= redist534_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_18_tpl_17_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272(ADD,8521)@31
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compstr267_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compstr269_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compstr268_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_9_c_compstr271_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_9_c_compstr271_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_o[33:0];

    // rightShiftStage0_uid15496_dupName_35_i_unnamed_c_compstr0_shift_x(MUX,15495)@31
    assign rightShiftStage0_uid15496_dupName_35_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15496_dupName_35_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_q or rightShiftStage0Idx1_uid15494_dupName_35_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15496_dupName_35_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15496_dupName_35_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_q;
            1'b1 : rightShiftStage0_uid15496_dupName_35_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15494_dupName_35_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15496_dupName_35_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15501_dupName_35_i_unnamed_c_compstr0_shift_x(MUX,15500)@31
    assign rightShiftStage1_uid15501_dupName_35_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15501_dupName_35_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15496_dupName_35_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15499_dupName_35_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15501_dupName_35_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15501_dupName_35_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15496_dupName_35_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15501_dupName_35_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15499_dupName_35_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15501_dupName_35_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15506_dupName_35_i_unnamed_c_compstr0_shift_x(MUX,15505)@31
    assign rightShiftStage2_uid15506_dupName_35_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15506_dupName_35_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15501_dupName_35_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15504_dupName_35_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15506_dupName_35_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15506_dupName_35_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15501_dupName_35_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15506_dupName_35_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15504_dupName_35_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15506_dupName_35_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr273_vt_select_20(BITSELECT,11315)@31
    assign i_unnamed_c_compstr273_vt_select_20_b = rightShiftStage2_uid15506_dupName_35_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr273_vt_join(BITJOIN,11314)@31
    assign i_unnamed_c_compstr273_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr273_vt_select_20_b};

    // i_conv_i_i_i_i97_i_9_c_compstr274_sel_x(BITSELECT,3583)@31
    assign i_conv_i_i_i_i97_i_9_c_compstr274_sel_x_b = i_unnamed_c_compstr273_vt_join_q[15:0];

    // redist1153_i_conv_i_i_i_i97_i_9_c_compstr274_sel_x_b_1(DELAY,29381)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1153_i_conv_i_i_i_i97_i_9_c_compstr274_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_9_c_compstr274_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15515_dupName_36_i_unnamed_c_compstr0_shift_x(BITSELECT,15514)@31
    assign rightShiftStage1Idx1Rng8_uid15515_dupName_36_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15514_dupName_36_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15517_dupName_36_i_unnamed_c_compstr0_shift_x(BITJOIN,15516)@31
    assign rightShiftStage1Idx1_uid15517_dupName_36_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15515_dupName_36_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15510_dupName_36_i_unnamed_c_compstr0_shift_x(BITSELECT,15509)@31
    assign rightShiftStage0Idx1Rng4_uid15510_dupName_36_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_q[33:4];

    // rightShiftStage0Idx1_uid15512_dupName_36_i_unnamed_c_compstr0_shift_x(BITJOIN,15511)@31
    assign rightShiftStage0Idx1_uid15512_dupName_36_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15510_dupName_36_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15514_dupName_36_i_unnamed_c_compstr0_shift_x(MUX,15513)@31
    assign rightShiftStage0_uid15514_dupName_36_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15514_dupName_36_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_q or rightShiftStage0Idx1_uid15512_dupName_36_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15514_dupName_36_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15514_dupName_36_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compstr272_q;
            1'b1 : rightShiftStage0_uid15514_dupName_36_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15512_dupName_36_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15514_dupName_36_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15519_dupName_36_i_unnamed_c_compstr0_shift_x(MUX,15518)@31
    assign rightShiftStage1_uid15519_dupName_36_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15519_dupName_36_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15514_dupName_36_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15517_dupName_36_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15519_dupName_36_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15519_dupName_36_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15514_dupName_36_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15519_dupName_36_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15517_dupName_36_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15519_dupName_36_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr275_vt_select_21(BITSELECT,11334)@31
    assign i_unnamed_c_compstr275_vt_select_21_b = rightShiftStage1_uid15519_dupName_36_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr275_vt_join(BITJOIN,11333)@31
    assign i_unnamed_c_compstr275_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr275_vt_select_21_b};

    // i_unnamed_c_compstr276_sel_x(BITSELECT,6174)@31
    assign i_unnamed_c_compstr276_sel_x_b = i_unnamed_c_compstr275_vt_join_q[15:0];

    // i_unnamed_c_compstr277_BitSelect_for_a(BITSELECT,27739)@31
    assign i_unnamed_c_compstr277_BitSelect_for_a_b = i_unnamed_c_compstr276_sel_x_b[0:0];

    // i_unnamed_c_compstr277_join(BITJOIN,27740)@31
    assign i_unnamed_c_compstr277_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr277_BitSelect_for_a_b};

    // i_unnamed_c_compstr277_vt_select_0(BITSELECT,11350)@31
    assign i_unnamed_c_compstr277_vt_select_0_b = i_unnamed_c_compstr277_join_q[0:0];

    // redist116_i_unnamed_c_compstr277_vt_select_0_b_1(DELAY,28344)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist116_i_unnamed_c_compstr277_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr277_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr277_vt_join(BITJOIN,11349)@32
    assign i_unnamed_c_compstr277_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist116_i_unnamed_c_compstr277_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_9_c_compstr278(ADD,6978)@32
    assign i_add_i_i_i_i_i126_i_9_c_compstr278_a = {1'b0, i_unnamed_c_compstr277_vt_join_q};
    assign i_add_i_i_i_i_i126_i_9_c_compstr278_b = {1'b0, redist1153_i_conv_i_i_i_i97_i_9_c_compstr274_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_9_c_compstr278_o = $unsigned(i_add_i_i_i_i_i126_i_9_c_compstr278_a) + $unsigned(i_add_i_i_i_i_i126_i_9_c_compstr278_b);
    assign i_add_i_i_i_i_i126_i_9_c_compstr278_q = i_add_i_i_i_i_i126_i_9_c_compstr278_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_9_c_compstr278_sel_x(BITSELECT,2172)@32
    assign bgTrunc_i_add_i_i_i_i_i126_i_9_c_compstr278_sel_x_b = i_add_i_i_i_i_i126_i_9_c_compstr278_q[15:0];

    // i_conv_i_i_i_i_i75_i277_10_c_compstr298_sel_x(BITSELECT,3596)@32
    assign i_conv_i_i_i_i_i75_i277_10_c_compstr298_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_9_c_compstr278_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_10_c_compstr298_vt_select_15(BITSELECT,7285)@32
    assign i_conv_i_i_i_i_i75_i277_10_c_compstr298_vt_select_15_b = i_conv_i_i_i_i_i75_i277_10_c_compstr298_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_10_c_compstr298_vt_join(BITJOIN,7284)@32
    assign i_conv_i_i_i_i_i75_i277_10_c_compstr298_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_10_c_compstr298_vt_select_15_b};

    // leftShiftStage0_uid23054_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x(MUX,23053)@32
    assign leftShiftStage0_uid23054_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23054_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_10_c_compstr298_vt_join_q or leftShiftStage0Idx1_uid23052_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23054_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23054_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_10_c_compstr298_vt_join_q;
            1'b1 : leftShiftStage0_uid23054_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23052_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23054_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23059_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x(MUX,23058)@32
    assign leftShiftStage1_uid23059_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23059_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_s or leftShiftStage0_uid23054_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23057_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23059_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23059_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q = leftShiftStage0_uid23054_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23059_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23057_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23059_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23064_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x(MUX,23063)@32
    assign leftShiftStage2_uid23064_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23064_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_s or leftShiftStage1_uid23059_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23062_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23064_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23064_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q = leftShiftStage1_uid23059_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23064_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23062_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23064_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_10_c_compstr299_vt_select_28(BITSELECT,9073)@32
    assign i_shl_i_i_i_i_i77_i_10_c_compstr299_vt_select_28_b = leftShiftStage2_uid23064_i_shl_i_i_i_i_i77_i_10_c_compstr0_shift_x_q[28:13];

    // redist499_i_shl_i_i_i_i_i77_i_10_c_compstr299_vt_select_28_b_1(DELAY,28727)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist499_i_shl_i_i_i_i_i77_i_10_c_compstr299_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_10_c_compstr299_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_10_c_compstr299_vt_join(BITJOIN,9072)@33
    assign i_shl_i_i_i_i_i77_i_10_c_compstr299_vt_join_q = {redist499_i_shl_i_i_i_i_i77_i_10_c_compstr299_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma(CHAINMULTADD,28109)@27 + 5
    // out q@33
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ah[0] <= redist791_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_21_tpl_19_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ah[1] <= redist790_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_20_tpl_19_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ch[0] <= redist537_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_21_tpl_19_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ch[1] <= redist536_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_20_tpl_19_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300(ADD,8405)@33
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compstr295_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compstr297_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compstr296_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_10_c_compstr299_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_10_c_compstr299_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_o[33:0];

    // rightShiftStage0_uid15558_dupName_39_i_unnamed_c_compstr0_shift_x(MUX,15557)@33
    assign rightShiftStage0_uid15558_dupName_39_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15558_dupName_39_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_q or rightShiftStage0Idx1_uid15556_dupName_39_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15558_dupName_39_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15558_dupName_39_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_q;
            1'b1 : rightShiftStage0_uid15558_dupName_39_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15556_dupName_39_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15558_dupName_39_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15563_dupName_39_i_unnamed_c_compstr0_shift_x(MUX,15562)@33
    assign rightShiftStage1_uid15563_dupName_39_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15563_dupName_39_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15558_dupName_39_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15561_dupName_39_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15563_dupName_39_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15563_dupName_39_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15558_dupName_39_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15563_dupName_39_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15561_dupName_39_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15563_dupName_39_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15568_dupName_39_i_unnamed_c_compstr0_shift_x(MUX,15567)@33
    assign rightShiftStage2_uid15568_dupName_39_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15568_dupName_39_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15563_dupName_39_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15566_dupName_39_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15568_dupName_39_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15568_dupName_39_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15563_dupName_39_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15568_dupName_39_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15566_dupName_39_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15568_dupName_39_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr301_vt_select_20(BITSELECT,11560)@33
    assign i_unnamed_c_compstr301_vt_select_20_b = rightShiftStage2_uid15568_dupName_39_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr301_vt_join(BITJOIN,11559)@33
    assign i_unnamed_c_compstr301_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr301_vt_select_20_b};

    // i_conv_i_i_i_i97_i_10_c_compstr302_sel_x(BITSELECT,3467)@33
    assign i_conv_i_i_i_i97_i_10_c_compstr302_sel_x_b = i_unnamed_c_compstr301_vt_join_q[15:0];

    // redist1269_i_conv_i_i_i_i97_i_10_c_compstr302_sel_x_b_1(DELAY,29497)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1269_i_conv_i_i_i_i97_i_10_c_compstr302_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_10_c_compstr302_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15577_dupName_40_i_unnamed_c_compstr0_shift_x(BITSELECT,15576)@33
    assign rightShiftStage1Idx1Rng8_uid15577_dupName_40_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15576_dupName_40_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15579_dupName_40_i_unnamed_c_compstr0_shift_x(BITJOIN,15578)@33
    assign rightShiftStage1Idx1_uid15579_dupName_40_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15577_dupName_40_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15572_dupName_40_i_unnamed_c_compstr0_shift_x(BITSELECT,15571)@33
    assign rightShiftStage0Idx1Rng4_uid15572_dupName_40_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_q[33:4];

    // rightShiftStage0Idx1_uid15574_dupName_40_i_unnamed_c_compstr0_shift_x(BITJOIN,15573)@33
    assign rightShiftStage0Idx1_uid15574_dupName_40_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15572_dupName_40_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15576_dupName_40_i_unnamed_c_compstr0_shift_x(MUX,15575)@33
    assign rightShiftStage0_uid15576_dupName_40_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15576_dupName_40_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_q or rightShiftStage0Idx1_uid15574_dupName_40_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15576_dupName_40_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15576_dupName_40_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compstr300_q;
            1'b1 : rightShiftStage0_uid15576_dupName_40_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15574_dupName_40_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15576_dupName_40_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15581_dupName_40_i_unnamed_c_compstr0_shift_x(MUX,15580)@33
    assign rightShiftStage1_uid15581_dupName_40_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15581_dupName_40_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15576_dupName_40_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15579_dupName_40_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15581_dupName_40_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15581_dupName_40_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15576_dupName_40_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15581_dupName_40_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15579_dupName_40_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15581_dupName_40_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr303_vt_select_21(BITSELECT,11579)@33
    assign i_unnamed_c_compstr303_vt_select_21_b = rightShiftStage1_uid15581_dupName_40_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr303_vt_join(BITJOIN,11578)@33
    assign i_unnamed_c_compstr303_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr303_vt_select_21_b};

    // i_unnamed_c_compstr304_sel_x(BITSELECT,6196)@33
    assign i_unnamed_c_compstr304_sel_x_b = i_unnamed_c_compstr303_vt_join_q[15:0];

    // i_unnamed_c_compstr305_BitSelect_for_a(BITSELECT,27783)@33
    assign i_unnamed_c_compstr305_BitSelect_for_a_b = i_unnamed_c_compstr304_sel_x_b[0:0];

    // i_unnamed_c_compstr305_join(BITJOIN,27784)@33
    assign i_unnamed_c_compstr305_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr305_BitSelect_for_a_b};

    // i_unnamed_c_compstr305_vt_select_0(BITSELECT,11595)@33
    assign i_unnamed_c_compstr305_vt_select_0_b = i_unnamed_c_compstr305_join_q[0:0];

    // redist94_i_unnamed_c_compstr305_vt_select_0_b_1(DELAY,28322)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist94_i_unnamed_c_compstr305_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr305_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr305_vt_join(BITJOIN,11594)@34
    assign i_unnamed_c_compstr305_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist94_i_unnamed_c_compstr305_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_10_c_compstr306(ADD,6862)@34
    assign i_add_i_i_i_i_i126_i_10_c_compstr306_a = {1'b0, i_unnamed_c_compstr305_vt_join_q};
    assign i_add_i_i_i_i_i126_i_10_c_compstr306_b = {1'b0, redist1269_i_conv_i_i_i_i97_i_10_c_compstr302_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_10_c_compstr306_o = $unsigned(i_add_i_i_i_i_i126_i_10_c_compstr306_a) + $unsigned(i_add_i_i_i_i_i126_i_10_c_compstr306_b);
    assign i_add_i_i_i_i_i126_i_10_c_compstr306_q = i_add_i_i_i_i_i126_i_10_c_compstr306_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_10_c_compstr306_sel_x(BITSELECT,2056)@34
    assign bgTrunc_i_add_i_i_i_i_i126_i_10_c_compstr306_sel_x_b = i_add_i_i_i_i_i126_i_10_c_compstr306_q[15:0];

    // i_conv_i_i_i_i_i75_i277_11_c_compstr326_sel_x(BITSELECT,3607)@34
    assign i_conv_i_i_i_i_i75_i277_11_c_compstr326_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_10_c_compstr306_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_11_c_compstr326_vt_select_15(BITSELECT,7329)@34
    assign i_conv_i_i_i_i_i75_i277_11_c_compstr326_vt_select_15_b = i_conv_i_i_i_i_i75_i277_11_c_compstr326_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_11_c_compstr326_vt_join(BITJOIN,7328)@34
    assign i_conv_i_i_i_i_i75_i277_11_c_compstr326_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_11_c_compstr326_vt_select_15_b};

    // leftShiftStage0_uid23252_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x(MUX,23251)@34
    assign leftShiftStage0_uid23252_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23252_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_11_c_compstr326_vt_join_q or leftShiftStage0Idx1_uid23250_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23252_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23252_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_11_c_compstr326_vt_join_q;
            1'b1 : leftShiftStage0_uid23252_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23250_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23252_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23257_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x(MUX,23256)@34
    assign leftShiftStage1_uid23257_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23257_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_s or leftShiftStage0_uid23252_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23255_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23257_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23257_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q = leftShiftStage0_uid23252_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23257_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23255_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23257_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23262_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x(MUX,23261)@34
    assign leftShiftStage2_uid23262_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23262_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_s or leftShiftStage1_uid23257_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23260_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23262_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23262_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q = leftShiftStage1_uid23257_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23262_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23260_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23262_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_11_c_compstr327_vt_select_28(BITSELECT,9106)@34
    assign i_shl_i_i_i_i_i77_i_11_c_compstr327_vt_select_28_b = leftShiftStage2_uid23262_i_shl_i_i_i_i_i77_i_11_c_compstr0_shift_x_q[28:13];

    // redist488_i_shl_i_i_i_i_i77_i_11_c_compstr327_vt_select_28_b_1(DELAY,28716)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist488_i_shl_i_i_i_i_i77_i_11_c_compstr327_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_11_c_compstr327_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_11_c_compstr327_vt_join(BITJOIN,9105)@35
    assign i_shl_i_i_i_i_i77_i_11_c_compstr327_vt_join_q = {redist488_i_shl_i_i_i_i_i77_i_11_c_compstr327_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma(CHAINMULTADD,28120)@29 + 5
    // out q@35
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ah[0] <= redist793_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_23_tpl_21_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ah[1] <= redist792_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_22_tpl_21_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ch[0] <= redist539_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_23_tpl_21_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ch[1] <= redist538_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_22_tpl_21_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328(ADD,8416)@35
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compstr323_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compstr325_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compstr324_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_11_c_compstr327_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_11_c_compstr327_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_o[33:0];

    // rightShiftStage0_uid15620_dupName_43_i_unnamed_c_compstr0_shift_x(MUX,15619)@35
    assign rightShiftStage0_uid15620_dupName_43_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15620_dupName_43_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_q or rightShiftStage0Idx1_uid15618_dupName_43_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15620_dupName_43_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15620_dupName_43_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_q;
            1'b1 : rightShiftStage0_uid15620_dupName_43_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15618_dupName_43_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15620_dupName_43_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15625_dupName_43_i_unnamed_c_compstr0_shift_x(MUX,15624)@35
    assign rightShiftStage1_uid15625_dupName_43_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15625_dupName_43_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15620_dupName_43_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15623_dupName_43_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15625_dupName_43_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15625_dupName_43_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15620_dupName_43_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15625_dupName_43_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15623_dupName_43_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15625_dupName_43_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15630_dupName_43_i_unnamed_c_compstr0_shift_x(MUX,15629)@35
    assign rightShiftStage2_uid15630_dupName_43_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15630_dupName_43_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15625_dupName_43_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15628_dupName_43_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15630_dupName_43_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15630_dupName_43_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15625_dupName_43_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15630_dupName_43_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15628_dupName_43_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15630_dupName_43_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr329_vt_select_20(BITSELECT,11802)@35
    assign i_unnamed_c_compstr329_vt_select_20_b = rightShiftStage2_uid15630_dupName_43_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr329_vt_join(BITJOIN,11801)@35
    assign i_unnamed_c_compstr329_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr329_vt_select_20_b};

    // i_conv_i_i_i_i97_i_11_c_compstr330_sel_x(BITSELECT,3478)@35
    assign i_conv_i_i_i_i97_i_11_c_compstr330_sel_x_b = i_unnamed_c_compstr329_vt_join_q[15:0];

    // redist1258_i_conv_i_i_i_i97_i_11_c_compstr330_sel_x_b_1(DELAY,29486)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1258_i_conv_i_i_i_i97_i_11_c_compstr330_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_11_c_compstr330_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15639_dupName_44_i_unnamed_c_compstr0_shift_x(BITSELECT,15638)@35
    assign rightShiftStage1Idx1Rng8_uid15639_dupName_44_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15638_dupName_44_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15641_dupName_44_i_unnamed_c_compstr0_shift_x(BITJOIN,15640)@35
    assign rightShiftStage1Idx1_uid15641_dupName_44_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15639_dupName_44_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15634_dupName_44_i_unnamed_c_compstr0_shift_x(BITSELECT,15633)@35
    assign rightShiftStage0Idx1Rng4_uid15634_dupName_44_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_q[33:4];

    // rightShiftStage0Idx1_uid15636_dupName_44_i_unnamed_c_compstr0_shift_x(BITJOIN,15635)@35
    assign rightShiftStage0Idx1_uid15636_dupName_44_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15634_dupName_44_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15638_dupName_44_i_unnamed_c_compstr0_shift_x(MUX,15637)@35
    assign rightShiftStage0_uid15638_dupName_44_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15638_dupName_44_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_q or rightShiftStage0Idx1_uid15636_dupName_44_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15638_dupName_44_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15638_dupName_44_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compstr328_q;
            1'b1 : rightShiftStage0_uid15638_dupName_44_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15636_dupName_44_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15638_dupName_44_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15643_dupName_44_i_unnamed_c_compstr0_shift_x(MUX,15642)@35
    assign rightShiftStage1_uid15643_dupName_44_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15643_dupName_44_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15638_dupName_44_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15641_dupName_44_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15643_dupName_44_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15643_dupName_44_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15638_dupName_44_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15643_dupName_44_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15641_dupName_44_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15643_dupName_44_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr331_vt_select_21(BITSELECT,11821)@35
    assign i_unnamed_c_compstr331_vt_select_21_b = rightShiftStage1_uid15643_dupName_44_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr331_vt_join(BITJOIN,11820)@35
    assign i_unnamed_c_compstr331_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr331_vt_select_21_b};

    // i_unnamed_c_compstr332_sel_x(BITSELECT,6218)@35
    assign i_unnamed_c_compstr332_sel_x_b = i_unnamed_c_compstr331_vt_join_q[15:0];

    // i_unnamed_c_compstr333_BitSelect_for_a(BITSELECT,27827)@35
    assign i_unnamed_c_compstr333_BitSelect_for_a_b = i_unnamed_c_compstr332_sel_x_b[0:0];

    // i_unnamed_c_compstr333_join(BITJOIN,27828)@35
    assign i_unnamed_c_compstr333_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr333_BitSelect_for_a_b};

    // i_unnamed_c_compstr333_vt_select_0(BITSELECT,11837)@35
    assign i_unnamed_c_compstr333_vt_select_0_b = i_unnamed_c_compstr333_join_q[0:0];

    // redist72_i_unnamed_c_compstr333_vt_select_0_b_1(DELAY,28300)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist72_i_unnamed_c_compstr333_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr333_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr333_vt_join(BITJOIN,11836)@36
    assign i_unnamed_c_compstr333_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist72_i_unnamed_c_compstr333_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_11_c_compstr334(ADD,6873)@36
    assign i_add_i_i_i_i_i126_i_11_c_compstr334_a = {1'b0, i_unnamed_c_compstr333_vt_join_q};
    assign i_add_i_i_i_i_i126_i_11_c_compstr334_b = {1'b0, redist1258_i_conv_i_i_i_i97_i_11_c_compstr330_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_11_c_compstr334_o = $unsigned(i_add_i_i_i_i_i126_i_11_c_compstr334_a) + $unsigned(i_add_i_i_i_i_i126_i_11_c_compstr334_b);
    assign i_add_i_i_i_i_i126_i_11_c_compstr334_q = i_add_i_i_i_i_i126_i_11_c_compstr334_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_11_c_compstr334_sel_x(BITSELECT,2067)@36
    assign bgTrunc_i_add_i_i_i_i_i126_i_11_c_compstr334_sel_x_b = i_add_i_i_i_i_i126_i_11_c_compstr334_q[15:0];

    // i_conv_i_i_i_i_i75_i277_12_c_compstr354_sel_x(BITSELECT,3616)@36
    assign i_conv_i_i_i_i_i75_i277_12_c_compstr354_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_11_c_compstr334_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_12_c_compstr354_vt_select_15(BITSELECT,7365)@36
    assign i_conv_i_i_i_i_i75_i277_12_c_compstr354_vt_select_15_b = i_conv_i_i_i_i_i75_i277_12_c_compstr354_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_12_c_compstr354_vt_join(BITJOIN,7364)@36
    assign i_conv_i_i_i_i_i75_i277_12_c_compstr354_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_12_c_compstr354_vt_select_15_b};

    // leftShiftStage0_uid23414_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x(MUX,23413)@36
    assign leftShiftStage0_uid23414_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23414_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_12_c_compstr354_vt_join_q or leftShiftStage0Idx1_uid23412_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23414_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23414_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_12_c_compstr354_vt_join_q;
            1'b1 : leftShiftStage0_uid23414_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23412_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23414_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23419_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x(MUX,23418)@36
    assign leftShiftStage1_uid23419_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23419_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_s or leftShiftStage0_uid23414_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23417_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23419_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23419_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q = leftShiftStage0_uid23414_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23419_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23417_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23419_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23424_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x(MUX,23423)@36
    assign leftShiftStage2_uid23424_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23424_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_s or leftShiftStage1_uid23419_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23422_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23424_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23424_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q = leftShiftStage1_uid23419_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23424_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23422_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23424_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_12_c_compstr355_vt_select_28(BITSELECT,9133)@36
    assign i_shl_i_i_i_i_i77_i_12_c_compstr355_vt_select_28_b = leftShiftStage2_uid23424_i_shl_i_i_i_i_i77_i_12_c_compstr0_shift_x_q[28:13];

    // redist479_i_shl_i_i_i_i_i77_i_12_c_compstr355_vt_select_28_b_1(DELAY,28707)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist479_i_shl_i_i_i_i_i77_i_12_c_compstr355_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_12_c_compstr355_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_12_c_compstr355_vt_join(BITJOIN,9132)@37
    assign i_shl_i_i_i_i_i77_i_12_c_compstr355_vt_join_q = {redist479_i_shl_i_i_i_i_i77_i_12_c_compstr355_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma(CHAINMULTADD,28129)@31 + 5
    // out q@37
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ah[0] <= redist795_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_25_tpl_23_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ah[1] <= redist794_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_24_tpl_23_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ch[0] <= redist541_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_25_tpl_23_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ch[1] <= redist540_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_24_tpl_23_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356(ADD,8425)@37
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compstr351_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compstr353_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compstr352_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_12_c_compstr355_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_12_c_compstr355_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_o[33:0];

    // rightShiftStage0_uid15682_dupName_47_i_unnamed_c_compstr0_shift_x(MUX,15681)@37
    assign rightShiftStage0_uid15682_dupName_47_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15682_dupName_47_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_q or rightShiftStage0Idx1_uid15680_dupName_47_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15682_dupName_47_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15682_dupName_47_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_q;
            1'b1 : rightShiftStage0_uid15682_dupName_47_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15680_dupName_47_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15682_dupName_47_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15687_dupName_47_i_unnamed_c_compstr0_shift_x(MUX,15686)@37
    assign rightShiftStage1_uid15687_dupName_47_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15687_dupName_47_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15682_dupName_47_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15685_dupName_47_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15687_dupName_47_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15687_dupName_47_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15682_dupName_47_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15687_dupName_47_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15685_dupName_47_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15687_dupName_47_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15692_dupName_47_i_unnamed_c_compstr0_shift_x(MUX,15691)@37
    assign rightShiftStage2_uid15692_dupName_47_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15692_dupName_47_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15687_dupName_47_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15690_dupName_47_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15692_dupName_47_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15692_dupName_47_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15687_dupName_47_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15692_dupName_47_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15690_dupName_47_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15692_dupName_47_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr357_vt_select_20(BITSELECT,12044)@37
    assign i_unnamed_c_compstr357_vt_select_20_b = rightShiftStage2_uid15692_dupName_47_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr357_vt_join(BITJOIN,12043)@37
    assign i_unnamed_c_compstr357_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr357_vt_select_20_b};

    // i_conv_i_i_i_i97_i_12_c_compstr358_sel_x(BITSELECT,3487)@37
    assign i_conv_i_i_i_i97_i_12_c_compstr358_sel_x_b = i_unnamed_c_compstr357_vt_join_q[15:0];

    // redist1249_i_conv_i_i_i_i97_i_12_c_compstr358_sel_x_b_1(DELAY,29477)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1249_i_conv_i_i_i_i97_i_12_c_compstr358_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_12_c_compstr358_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15701_dupName_48_i_unnamed_c_compstr0_shift_x(BITSELECT,15700)@37
    assign rightShiftStage1Idx1Rng8_uid15701_dupName_48_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15700_dupName_48_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15703_dupName_48_i_unnamed_c_compstr0_shift_x(BITJOIN,15702)@37
    assign rightShiftStage1Idx1_uid15703_dupName_48_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15701_dupName_48_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15696_dupName_48_i_unnamed_c_compstr0_shift_x(BITSELECT,15695)@37
    assign rightShiftStage0Idx1Rng4_uid15696_dupName_48_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_q[33:4];

    // rightShiftStage0Idx1_uid15698_dupName_48_i_unnamed_c_compstr0_shift_x(BITJOIN,15697)@37
    assign rightShiftStage0Idx1_uid15698_dupName_48_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15696_dupName_48_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15700_dupName_48_i_unnamed_c_compstr0_shift_x(MUX,15699)@37
    assign rightShiftStage0_uid15700_dupName_48_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15700_dupName_48_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_q or rightShiftStage0Idx1_uid15698_dupName_48_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15700_dupName_48_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15700_dupName_48_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compstr356_q;
            1'b1 : rightShiftStage0_uid15700_dupName_48_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15698_dupName_48_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15700_dupName_48_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15705_dupName_48_i_unnamed_c_compstr0_shift_x(MUX,15704)@37
    assign rightShiftStage1_uid15705_dupName_48_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15705_dupName_48_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15700_dupName_48_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15703_dupName_48_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15705_dupName_48_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15705_dupName_48_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15700_dupName_48_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15705_dupName_48_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15703_dupName_48_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15705_dupName_48_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr359_vt_select_21(BITSELECT,12063)@37
    assign i_unnamed_c_compstr359_vt_select_21_b = rightShiftStage1_uid15705_dupName_48_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr359_vt_join(BITJOIN,12062)@37
    assign i_unnamed_c_compstr359_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr359_vt_select_21_b};

    // i_unnamed_c_compstr360_sel_x(BITSELECT,6240)@37
    assign i_unnamed_c_compstr360_sel_x_b = i_unnamed_c_compstr359_vt_join_q[15:0];

    // i_unnamed_c_compstr361_BitSelect_for_a(BITSELECT,27869)@37
    assign i_unnamed_c_compstr361_BitSelect_for_a_b = i_unnamed_c_compstr360_sel_x_b[0:0];

    // i_unnamed_c_compstr361_join(BITJOIN,27870)@37
    assign i_unnamed_c_compstr361_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr361_BitSelect_for_a_b};

    // i_unnamed_c_compstr361_vt_select_0(BITSELECT,12068)@37
    assign i_unnamed_c_compstr361_vt_select_0_b = i_unnamed_c_compstr361_join_q[0:0];

    // redist51_i_unnamed_c_compstr361_vt_select_0_b_1(DELAY,28279)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist51_i_unnamed_c_compstr361_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr361_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr361_vt_join(BITJOIN,12067)@38
    assign i_unnamed_c_compstr361_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist51_i_unnamed_c_compstr361_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_12_c_compstr362(ADD,6882)@38
    assign i_add_i_i_i_i_i126_i_12_c_compstr362_a = {1'b0, i_unnamed_c_compstr361_vt_join_q};
    assign i_add_i_i_i_i_i126_i_12_c_compstr362_b = {1'b0, redist1249_i_conv_i_i_i_i97_i_12_c_compstr358_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_12_c_compstr362_o = $unsigned(i_add_i_i_i_i_i126_i_12_c_compstr362_a) + $unsigned(i_add_i_i_i_i_i126_i_12_c_compstr362_b);
    assign i_add_i_i_i_i_i126_i_12_c_compstr362_q = i_add_i_i_i_i_i126_i_12_c_compstr362_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_12_c_compstr362_sel_x(BITSELECT,2076)@38
    assign bgTrunc_i_add_i_i_i_i_i126_i_12_c_compstr362_sel_x_b = i_add_i_i_i_i_i126_i_12_c_compstr362_q[15:0];

    // i_conv_i_i_i_i_i75_i277_13_c_compstr382_sel_x(BITSELECT,3617)@38
    assign i_conv_i_i_i_i_i75_i277_13_c_compstr382_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_12_c_compstr362_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_13_c_compstr382_vt_select_15(BITSELECT,7369)@38
    assign i_conv_i_i_i_i_i75_i277_13_c_compstr382_vt_select_15_b = i_conv_i_i_i_i_i75_i277_13_c_compstr382_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_13_c_compstr382_vt_join(BITJOIN,7368)@38
    assign i_conv_i_i_i_i_i75_i277_13_c_compstr382_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_13_c_compstr382_vt_select_15_b};

    // leftShiftStage0_uid23432_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x(MUX,23431)@38
    assign leftShiftStage0_uid23432_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23432_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_13_c_compstr382_vt_join_q or leftShiftStage0Idx1_uid23430_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23432_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23432_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_13_c_compstr382_vt_join_q;
            1'b1 : leftShiftStage0_uid23432_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23430_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23432_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23437_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x(MUX,23436)@38
    assign leftShiftStage1_uid23437_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23437_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_s or leftShiftStage0_uid23432_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23435_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23437_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23437_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q = leftShiftStage0_uid23432_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23437_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23435_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23437_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23442_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x(MUX,23441)@38
    assign leftShiftStage2_uid23442_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23442_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_s or leftShiftStage1_uid23437_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23440_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23442_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23442_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q = leftShiftStage1_uid23437_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23442_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23440_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23442_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_13_c_compstr383_vt_select_28(BITSELECT,9136)@38
    assign i_shl_i_i_i_i_i77_i_13_c_compstr383_vt_select_28_b = leftShiftStage2_uid23442_i_shl_i_i_i_i_i77_i_13_c_compstr0_shift_x_q[28:13];

    // redist478_i_shl_i_i_i_i_i77_i_13_c_compstr383_vt_select_28_b_1(DELAY,28706)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist478_i_shl_i_i_i_i_i77_i_13_c_compstr383_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_13_c_compstr383_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_13_c_compstr383_vt_join(BITJOIN,9135)@39
    assign i_shl_i_i_i_i_i77_i_13_c_compstr383_vt_join_q = {redist478_i_shl_i_i_i_i_i77_i_13_c_compstr383_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma(CHAINMULTADD,28130)@33 + 5
    // out q@39
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ah[0] <= redist797_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_27_tpl_25_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ah[1] <= redist796_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_26_tpl_25_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ch[0] <= redist543_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_27_tpl_25_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ch[1] <= redist542_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_26_tpl_25_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384(ADD,8426)@39
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compstr379_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compstr381_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compstr380_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_13_c_compstr383_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_13_c_compstr383_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_o[33:0];

    // rightShiftStage0_uid15744_dupName_51_i_unnamed_c_compstr0_shift_x(MUX,15743)@39
    assign rightShiftStage0_uid15744_dupName_51_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15744_dupName_51_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_q or rightShiftStage0Idx1_uid15742_dupName_51_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15744_dupName_51_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15744_dupName_51_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_q;
            1'b1 : rightShiftStage0_uid15744_dupName_51_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15742_dupName_51_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15744_dupName_51_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15749_dupName_51_i_unnamed_c_compstr0_shift_x(MUX,15748)@39
    assign rightShiftStage1_uid15749_dupName_51_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15749_dupName_51_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15744_dupName_51_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15747_dupName_51_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15749_dupName_51_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15749_dupName_51_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15744_dupName_51_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15749_dupName_51_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15747_dupName_51_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15749_dupName_51_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15754_dupName_51_i_unnamed_c_compstr0_shift_x(MUX,15753)@39
    assign rightShiftStage2_uid15754_dupName_51_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15754_dupName_51_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15749_dupName_51_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15752_dupName_51_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15754_dupName_51_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15754_dupName_51_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15749_dupName_51_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15754_dupName_51_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15752_dupName_51_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15754_dupName_51_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr385_vt_select_20(BITSELECT,12085)@39
    assign i_unnamed_c_compstr385_vt_select_20_b = rightShiftStage2_uid15754_dupName_51_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr385_vt_join(BITJOIN,12084)@39
    assign i_unnamed_c_compstr385_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr385_vt_select_20_b};

    // i_conv_i_i_i_i97_i_13_c_compstr386_sel_x(BITSELECT,3488)@39
    assign i_conv_i_i_i_i97_i_13_c_compstr386_sel_x_b = i_unnamed_c_compstr385_vt_join_q[15:0];

    // redist1248_i_conv_i_i_i_i97_i_13_c_compstr386_sel_x_b_1(DELAY,29476)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1248_i_conv_i_i_i_i97_i_13_c_compstr386_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_13_c_compstr386_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15763_dupName_52_i_unnamed_c_compstr0_shift_x(BITSELECT,15762)@39
    assign rightShiftStage1Idx1Rng8_uid15763_dupName_52_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15762_dupName_52_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15765_dupName_52_i_unnamed_c_compstr0_shift_x(BITJOIN,15764)@39
    assign rightShiftStage1Idx1_uid15765_dupName_52_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15763_dupName_52_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15758_dupName_52_i_unnamed_c_compstr0_shift_x(BITSELECT,15757)@39
    assign rightShiftStage0Idx1Rng4_uid15758_dupName_52_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_q[33:4];

    // rightShiftStage0Idx1_uid15760_dupName_52_i_unnamed_c_compstr0_shift_x(BITJOIN,15759)@39
    assign rightShiftStage0Idx1_uid15760_dupName_52_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15758_dupName_52_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15762_dupName_52_i_unnamed_c_compstr0_shift_x(MUX,15761)@39
    assign rightShiftStage0_uid15762_dupName_52_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15762_dupName_52_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_q or rightShiftStage0Idx1_uid15760_dupName_52_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15762_dupName_52_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15762_dupName_52_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compstr384_q;
            1'b1 : rightShiftStage0_uid15762_dupName_52_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15760_dupName_52_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15762_dupName_52_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15767_dupName_52_i_unnamed_c_compstr0_shift_x(MUX,15766)@39
    assign rightShiftStage1_uid15767_dupName_52_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15767_dupName_52_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15762_dupName_52_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15765_dupName_52_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15767_dupName_52_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15767_dupName_52_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15762_dupName_52_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15767_dupName_52_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15765_dupName_52_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15767_dupName_52_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr387_vt_select_21(BITSELECT,12088)@39
    assign i_unnamed_c_compstr387_vt_select_21_b = rightShiftStage1_uid15767_dupName_52_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr387_vt_join(BITJOIN,12087)@39
    assign i_unnamed_c_compstr387_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr387_vt_select_21_b};

    // i_unnamed_c_compstr388_sel_x(BITSELECT,6242)@39
    assign i_unnamed_c_compstr388_sel_x_b = i_unnamed_c_compstr387_vt_join_q[15:0];

    // i_unnamed_c_compstr389_BitSelect_for_a(BITSELECT,27873)@39
    assign i_unnamed_c_compstr389_BitSelect_for_a_b = i_unnamed_c_compstr388_sel_x_b[0:0];

    // i_unnamed_c_compstr389_join(BITJOIN,27874)@39
    assign i_unnamed_c_compstr389_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr389_BitSelect_for_a_b};

    // i_unnamed_c_compstr389_vt_select_0(BITSELECT,12093)@39
    assign i_unnamed_c_compstr389_vt_select_0_b = i_unnamed_c_compstr389_join_q[0:0];

    // redist49_i_unnamed_c_compstr389_vt_select_0_b_1(DELAY,28277)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist49_i_unnamed_c_compstr389_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr389_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr389_vt_join(BITJOIN,12092)@40
    assign i_unnamed_c_compstr389_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist49_i_unnamed_c_compstr389_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_13_c_compstr390(ADD,6883)@40
    assign i_add_i_i_i_i_i126_i_13_c_compstr390_a = {1'b0, i_unnamed_c_compstr389_vt_join_q};
    assign i_add_i_i_i_i_i126_i_13_c_compstr390_b = {1'b0, redist1248_i_conv_i_i_i_i97_i_13_c_compstr386_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_13_c_compstr390_o = $unsigned(i_add_i_i_i_i_i126_i_13_c_compstr390_a) + $unsigned(i_add_i_i_i_i_i126_i_13_c_compstr390_b);
    assign i_add_i_i_i_i_i126_i_13_c_compstr390_q = i_add_i_i_i_i_i126_i_13_c_compstr390_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_13_c_compstr390_sel_x(BITSELECT,2077)@40
    assign bgTrunc_i_add_i_i_i_i_i126_i_13_c_compstr390_sel_x_b = i_add_i_i_i_i_i126_i_13_c_compstr390_q[15:0];

    // i_conv_i_i_i_i_i75_i277_14_c_compstr410_sel_x(BITSELECT,3618)@40
    assign i_conv_i_i_i_i_i75_i277_14_c_compstr410_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_13_c_compstr390_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_14_c_compstr410_vt_select_15(BITSELECT,7373)@40
    assign i_conv_i_i_i_i_i75_i277_14_c_compstr410_vt_select_15_b = i_conv_i_i_i_i_i75_i277_14_c_compstr410_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_14_c_compstr410_vt_join(BITJOIN,7372)@40
    assign i_conv_i_i_i_i_i75_i277_14_c_compstr410_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_14_c_compstr410_vt_select_15_b};

    // leftShiftStage0_uid23450_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x(MUX,23449)@40
    assign leftShiftStage0_uid23450_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23450_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_14_c_compstr410_vt_join_q or leftShiftStage0Idx1_uid23448_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23450_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23450_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_14_c_compstr410_vt_join_q;
            1'b1 : leftShiftStage0_uid23450_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23448_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23450_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23455_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x(MUX,23454)@40
    assign leftShiftStage1_uid23455_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23455_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_s or leftShiftStage0_uid23450_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23453_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23455_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23455_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q = leftShiftStage0_uid23450_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23455_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23453_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23455_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23460_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x(MUX,23459)@40
    assign leftShiftStage2_uid23460_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23460_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_s or leftShiftStage1_uid23455_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23458_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23460_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23460_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q = leftShiftStage1_uid23455_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23460_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23458_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23460_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_14_c_compstr411_vt_select_28(BITSELECT,9139)@40
    assign i_shl_i_i_i_i_i77_i_14_c_compstr411_vt_select_28_b = leftShiftStage2_uid23460_i_shl_i_i_i_i_i77_i_14_c_compstr0_shift_x_q[28:13];

    // redist477_i_shl_i_i_i_i_i77_i_14_c_compstr411_vt_select_28_b_1(DELAY,28705)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist477_i_shl_i_i_i_i_i77_i_14_c_compstr411_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_14_c_compstr411_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_14_c_compstr411_vt_join(BITJOIN,9138)@41
    assign i_shl_i_i_i_i_i77_i_14_c_compstr411_vt_join_q = {redist477_i_shl_i_i_i_i_i77_i_14_c_compstr411_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma(CHAINMULTADD,28131)@35 + 5
    // out q@41
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ah[0] <= redist799_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_29_tpl_27_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ah[1] <= redist798_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_28_tpl_27_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ch[0] <= redist545_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_29_tpl_27_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ch[1] <= redist544_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_28_tpl_27_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412(ADD,8427)@41
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compstr407_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compstr409_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compstr408_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_14_c_compstr411_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_14_c_compstr411_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_o[33:0];

    // rightShiftStage0_uid15806_dupName_55_i_unnamed_c_compstr0_shift_x(MUX,15805)@41
    assign rightShiftStage0_uid15806_dupName_55_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15806_dupName_55_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_q or rightShiftStage0Idx1_uid15804_dupName_55_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15806_dupName_55_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15806_dupName_55_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_q;
            1'b1 : rightShiftStage0_uid15806_dupName_55_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15804_dupName_55_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15806_dupName_55_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15811_dupName_55_i_unnamed_c_compstr0_shift_x(MUX,15810)@41
    assign rightShiftStage1_uid15811_dupName_55_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15811_dupName_55_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15806_dupName_55_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15809_dupName_55_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15811_dupName_55_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15811_dupName_55_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15806_dupName_55_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15811_dupName_55_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15809_dupName_55_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15811_dupName_55_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15816_dupName_55_i_unnamed_c_compstr0_shift_x(MUX,15815)@41
    assign rightShiftStage2_uid15816_dupName_55_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15816_dupName_55_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15811_dupName_55_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15814_dupName_55_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15816_dupName_55_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15816_dupName_55_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15811_dupName_55_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15816_dupName_55_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15814_dupName_55_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15816_dupName_55_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr413_vt_select_20(BITSELECT,12112)@41
    assign i_unnamed_c_compstr413_vt_select_20_b = rightShiftStage2_uid15816_dupName_55_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr413_vt_join(BITJOIN,12111)@41
    assign i_unnamed_c_compstr413_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr413_vt_select_20_b};

    // i_conv_i_i_i_i97_i_14_c_compstr414_sel_x(BITSELECT,3489)@41
    assign i_conv_i_i_i_i97_i_14_c_compstr414_sel_x_b = i_unnamed_c_compstr413_vt_join_q[15:0];

    // redist1247_i_conv_i_i_i_i97_i_14_c_compstr414_sel_x_b_1(DELAY,29475)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1247_i_conv_i_i_i_i97_i_14_c_compstr414_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_14_c_compstr414_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15825_dupName_56_i_unnamed_c_compstr0_shift_x(BITSELECT,15824)@41
    assign rightShiftStage1Idx1Rng8_uid15825_dupName_56_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15824_dupName_56_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15827_dupName_56_i_unnamed_c_compstr0_shift_x(BITJOIN,15826)@41
    assign rightShiftStage1Idx1_uid15827_dupName_56_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15825_dupName_56_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15820_dupName_56_i_unnamed_c_compstr0_shift_x(BITSELECT,15819)@41
    assign rightShiftStage0Idx1Rng4_uid15820_dupName_56_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_q[33:4];

    // rightShiftStage0Idx1_uid15822_dupName_56_i_unnamed_c_compstr0_shift_x(BITJOIN,15821)@41
    assign rightShiftStage0Idx1_uid15822_dupName_56_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15820_dupName_56_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15824_dupName_56_i_unnamed_c_compstr0_shift_x(MUX,15823)@41
    assign rightShiftStage0_uid15824_dupName_56_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15824_dupName_56_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_q or rightShiftStage0Idx1_uid15822_dupName_56_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15824_dupName_56_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15824_dupName_56_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compstr412_q;
            1'b1 : rightShiftStage0_uid15824_dupName_56_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15822_dupName_56_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15824_dupName_56_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15829_dupName_56_i_unnamed_c_compstr0_shift_x(MUX,15828)@41
    assign rightShiftStage1_uid15829_dupName_56_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15829_dupName_56_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15824_dupName_56_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15827_dupName_56_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15829_dupName_56_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15829_dupName_56_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15824_dupName_56_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15829_dupName_56_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15827_dupName_56_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15829_dupName_56_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr415_vt_select_21(BITSELECT,12115)@41
    assign i_unnamed_c_compstr415_vt_select_21_b = rightShiftStage1_uid15829_dupName_56_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr415_vt_join(BITJOIN,12114)@41
    assign i_unnamed_c_compstr415_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr415_vt_select_21_b};

    // i_unnamed_c_compstr416_sel_x(BITSELECT,6245)@41
    assign i_unnamed_c_compstr416_sel_x_b = i_unnamed_c_compstr415_vt_join_q[15:0];

    // i_unnamed_c_compstr417_BitSelect_for_a(BITSELECT,27879)@41
    assign i_unnamed_c_compstr417_BitSelect_for_a_b = i_unnamed_c_compstr416_sel_x_b[0:0];

    // i_unnamed_c_compstr417_join(BITJOIN,27880)@41
    assign i_unnamed_c_compstr417_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr417_BitSelect_for_a_b};

    // i_unnamed_c_compstr417_vt_select_0(BITSELECT,12120)@41
    assign i_unnamed_c_compstr417_vt_select_0_b = i_unnamed_c_compstr417_join_q[0:0];

    // redist47_i_unnamed_c_compstr417_vt_select_0_b_1(DELAY,28275)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist47_i_unnamed_c_compstr417_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr417_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr417_vt_join(BITJOIN,12119)@42
    assign i_unnamed_c_compstr417_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist47_i_unnamed_c_compstr417_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_14_c_compstr418(ADD,6884)@42
    assign i_add_i_i_i_i_i126_i_14_c_compstr418_a = {1'b0, i_unnamed_c_compstr417_vt_join_q};
    assign i_add_i_i_i_i_i126_i_14_c_compstr418_b = {1'b0, redist1247_i_conv_i_i_i_i97_i_14_c_compstr414_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_14_c_compstr418_o = $unsigned(i_add_i_i_i_i_i126_i_14_c_compstr418_a) + $unsigned(i_add_i_i_i_i_i126_i_14_c_compstr418_b);
    assign i_add_i_i_i_i_i126_i_14_c_compstr418_q = i_add_i_i_i_i_i126_i_14_c_compstr418_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_14_c_compstr418_sel_x(BITSELECT,2078)@42
    assign bgTrunc_i_add_i_i_i_i_i126_i_14_c_compstr418_sel_x_b = i_add_i_i_i_i_i126_i_14_c_compstr418_q[15:0];

    // i_conv_i_i_i_i_i75_i277_15_c_compstr438_sel_x(BITSELECT,3619)@42
    assign i_conv_i_i_i_i_i75_i277_15_c_compstr438_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_14_c_compstr418_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_15_c_compstr438_vt_select_15(BITSELECT,7377)@42
    assign i_conv_i_i_i_i_i75_i277_15_c_compstr438_vt_select_15_b = i_conv_i_i_i_i_i75_i277_15_c_compstr438_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_15_c_compstr438_vt_join(BITJOIN,7376)@42
    assign i_conv_i_i_i_i_i75_i277_15_c_compstr438_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_15_c_compstr438_vt_select_15_b};

    // leftShiftStage0_uid23468_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x(MUX,23467)@42
    assign leftShiftStage0_uid23468_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23468_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_15_c_compstr438_vt_join_q or leftShiftStage0Idx1_uid23466_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23468_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23468_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_15_c_compstr438_vt_join_q;
            1'b1 : leftShiftStage0_uid23468_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23466_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23468_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23473_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x(MUX,23472)@42
    assign leftShiftStage1_uid23473_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23473_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_s or leftShiftStage0_uid23468_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23471_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23473_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23473_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q = leftShiftStage0_uid23468_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23473_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23471_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23473_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23478_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x(MUX,23477)@42
    assign leftShiftStage2_uid23478_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23478_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_s or leftShiftStage1_uid23473_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23476_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23478_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23478_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q = leftShiftStage1_uid23473_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23478_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23476_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23478_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_15_c_compstr439_vt_select_28(BITSELECT,9142)@42
    assign i_shl_i_i_i_i_i77_i_15_c_compstr439_vt_select_28_b = leftShiftStage2_uid23478_i_shl_i_i_i_i_i77_i_15_c_compstr0_shift_x_q[28:13];

    // redist476_i_shl_i_i_i_i_i77_i_15_c_compstr439_vt_select_28_b_1(DELAY,28704)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist476_i_shl_i_i_i_i_i77_i_15_c_compstr439_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_15_c_compstr439_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_15_c_compstr439_vt_join(BITJOIN,9141)@43
    assign i_shl_i_i_i_i_i77_i_15_c_compstr439_vt_join_q = {redist476_i_shl_i_i_i_i_i77_i_15_c_compstr439_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma(CHAINMULTADD,28132)@37 + 5
    // out q@43
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ah[0] <= redist801_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_31_tpl_29_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ah[1] <= redist800_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_30_tpl_29_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ch[0] <= redist547_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_31_tpl_29_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ch[1] <= redist546_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_30_tpl_29_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440(ADD,8428)@43
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compstr435_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compstr437_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compstr436_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_15_c_compstr439_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_15_c_compstr439_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_o[33:0];

    // rightShiftStage0_uid15868_dupName_59_i_unnamed_c_compstr0_shift_x(MUX,15867)@43
    assign rightShiftStage0_uid15868_dupName_59_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15868_dupName_59_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_q or rightShiftStage0Idx1_uid15866_dupName_59_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15868_dupName_59_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15868_dupName_59_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_q;
            1'b1 : rightShiftStage0_uid15868_dupName_59_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15866_dupName_59_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15868_dupName_59_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15873_dupName_59_i_unnamed_c_compstr0_shift_x(MUX,15872)@43
    assign rightShiftStage1_uid15873_dupName_59_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15873_dupName_59_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15868_dupName_59_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15871_dupName_59_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15873_dupName_59_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15873_dupName_59_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15868_dupName_59_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15873_dupName_59_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15871_dupName_59_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15873_dupName_59_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15878_dupName_59_i_unnamed_c_compstr0_shift_x(MUX,15877)@43
    assign rightShiftStage2_uid15878_dupName_59_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15878_dupName_59_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15873_dupName_59_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15876_dupName_59_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15878_dupName_59_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15878_dupName_59_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15873_dupName_59_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15878_dupName_59_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15876_dupName_59_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15878_dupName_59_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr441_vt_select_20(BITSELECT,12137)@43
    assign i_unnamed_c_compstr441_vt_select_20_b = rightShiftStage2_uid15878_dupName_59_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr441_vt_join(BITJOIN,12136)@43
    assign i_unnamed_c_compstr441_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr441_vt_select_20_b};

    // i_conv_i_i_i_i97_i_15_c_compstr442_sel_x(BITSELECT,3490)@43
    assign i_conv_i_i_i_i97_i_15_c_compstr442_sel_x_b = i_unnamed_c_compstr441_vt_join_q[15:0];

    // redist1246_i_conv_i_i_i_i97_i_15_c_compstr442_sel_x_b_1(DELAY,29474)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1246_i_conv_i_i_i_i97_i_15_c_compstr442_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_15_c_compstr442_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15887_dupName_60_i_unnamed_c_compstr0_shift_x(BITSELECT,15886)@43
    assign rightShiftStage1Idx1Rng8_uid15887_dupName_60_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15886_dupName_60_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15889_dupName_60_i_unnamed_c_compstr0_shift_x(BITJOIN,15888)@43
    assign rightShiftStage1Idx1_uid15889_dupName_60_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15887_dupName_60_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15882_dupName_60_i_unnamed_c_compstr0_shift_x(BITSELECT,15881)@43
    assign rightShiftStage0Idx1Rng4_uid15882_dupName_60_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_q[33:4];

    // rightShiftStage0Idx1_uid15884_dupName_60_i_unnamed_c_compstr0_shift_x(BITJOIN,15883)@43
    assign rightShiftStage0Idx1_uid15884_dupName_60_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15882_dupName_60_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15886_dupName_60_i_unnamed_c_compstr0_shift_x(MUX,15885)@43
    assign rightShiftStage0_uid15886_dupName_60_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15886_dupName_60_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_q or rightShiftStage0Idx1_uid15884_dupName_60_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15886_dupName_60_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15886_dupName_60_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compstr440_q;
            1'b1 : rightShiftStage0_uid15886_dupName_60_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15884_dupName_60_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15886_dupName_60_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15891_dupName_60_i_unnamed_c_compstr0_shift_x(MUX,15890)@43
    assign rightShiftStage1_uid15891_dupName_60_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15891_dupName_60_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15886_dupName_60_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15889_dupName_60_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15891_dupName_60_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15891_dupName_60_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15886_dupName_60_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15891_dupName_60_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15889_dupName_60_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15891_dupName_60_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr443_vt_select_21(BITSELECT,12140)@43
    assign i_unnamed_c_compstr443_vt_select_21_b = rightShiftStage1_uid15891_dupName_60_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr443_vt_join(BITJOIN,12139)@43
    assign i_unnamed_c_compstr443_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr443_vt_select_21_b};

    // i_unnamed_c_compstr444_sel_x(BITSELECT,6247)@43
    assign i_unnamed_c_compstr444_sel_x_b = i_unnamed_c_compstr443_vt_join_q[15:0];

    // i_unnamed_c_compstr445_BitSelect_for_a(BITSELECT,27883)@43
    assign i_unnamed_c_compstr445_BitSelect_for_a_b = i_unnamed_c_compstr444_sel_x_b[0:0];

    // i_unnamed_c_compstr445_join(BITJOIN,27884)@43
    assign i_unnamed_c_compstr445_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr445_BitSelect_for_a_b};

    // i_unnamed_c_compstr445_vt_select_0(BITSELECT,12145)@43
    assign i_unnamed_c_compstr445_vt_select_0_b = i_unnamed_c_compstr445_join_q[0:0];

    // redist45_i_unnamed_c_compstr445_vt_select_0_b_1(DELAY,28273)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist45_i_unnamed_c_compstr445_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr445_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr445_vt_join(BITJOIN,12144)@44
    assign i_unnamed_c_compstr445_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist45_i_unnamed_c_compstr445_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_15_c_compstr446(ADD,6885)@44
    assign i_add_i_i_i_i_i126_i_15_c_compstr446_a = {1'b0, i_unnamed_c_compstr445_vt_join_q};
    assign i_add_i_i_i_i_i126_i_15_c_compstr446_b = {1'b0, redist1246_i_conv_i_i_i_i97_i_15_c_compstr442_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_15_c_compstr446_o = $unsigned(i_add_i_i_i_i_i126_i_15_c_compstr446_a) + $unsigned(i_add_i_i_i_i_i126_i_15_c_compstr446_b);
    assign i_add_i_i_i_i_i126_i_15_c_compstr446_q = i_add_i_i_i_i_i126_i_15_c_compstr446_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_15_c_compstr446_sel_x(BITSELECT,2079)@44
    assign bgTrunc_i_add_i_i_i_i_i126_i_15_c_compstr446_sel_x_b = i_add_i_i_i_i_i126_i_15_c_compstr446_q[15:0];

    // i_conv_i_i_i_i_i75_i277_16_c_compstr466_sel_x(BITSELECT,3620)@44
    assign i_conv_i_i_i_i_i75_i277_16_c_compstr466_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_15_c_compstr446_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_16_c_compstr466_vt_select_15(BITSELECT,7381)@44
    assign i_conv_i_i_i_i_i75_i277_16_c_compstr466_vt_select_15_b = i_conv_i_i_i_i_i75_i277_16_c_compstr466_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_16_c_compstr466_vt_join(BITJOIN,7380)@44
    assign i_conv_i_i_i_i_i75_i277_16_c_compstr466_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_16_c_compstr466_vt_select_15_b};

    // leftShiftStage0_uid23486_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x(MUX,23485)@44
    assign leftShiftStage0_uid23486_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23486_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_16_c_compstr466_vt_join_q or leftShiftStage0Idx1_uid23484_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23486_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23486_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_16_c_compstr466_vt_join_q;
            1'b1 : leftShiftStage0_uid23486_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23484_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23486_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23491_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x(MUX,23490)@44
    assign leftShiftStage1_uid23491_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23491_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_s or leftShiftStage0_uid23486_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23489_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23491_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23491_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q = leftShiftStage0_uid23486_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23491_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23489_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23491_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23496_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x(MUX,23495)@44
    assign leftShiftStage2_uid23496_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23496_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_s or leftShiftStage1_uid23491_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23494_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23496_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23496_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q = leftShiftStage1_uid23491_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23496_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23494_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23496_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_16_c_compstr467_vt_select_28(BITSELECT,9145)@44
    assign i_shl_i_i_i_i_i77_i_16_c_compstr467_vt_select_28_b = leftShiftStage2_uid23496_i_shl_i_i_i_i_i77_i_16_c_compstr0_shift_x_q[28:13];

    // redist475_i_shl_i_i_i_i_i77_i_16_c_compstr467_vt_select_28_b_1(DELAY,28703)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist475_i_shl_i_i_i_i_i77_i_16_c_compstr467_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_16_c_compstr467_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_16_c_compstr467_vt_join(BITJOIN,9144)@45
    assign i_shl_i_i_i_i_i77_i_16_c_compstr467_vt_join_q = {redist475_i_shl_i_i_i_i_i77_i_16_c_compstr467_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma(CHAINMULTADD,28133)@39 + 5
    // out q@45
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ah[0] <= redist803_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_33_tpl_31_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ah[1] <= redist802_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_32_tpl_31_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ch[0] <= redist549_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_33_tpl_31_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ch[1] <= redist548_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_32_tpl_31_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468(ADD,8429)@45
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compstr463_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compstr465_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compstr464_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_16_c_compstr467_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_16_c_compstr467_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_o[33:0];

    // rightShiftStage0_uid15930_dupName_63_i_unnamed_c_compstr0_shift_x(MUX,15929)@45
    assign rightShiftStage0_uid15930_dupName_63_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15930_dupName_63_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_q or rightShiftStage0Idx1_uid15928_dupName_63_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15930_dupName_63_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15930_dupName_63_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_q;
            1'b1 : rightShiftStage0_uid15930_dupName_63_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15928_dupName_63_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15930_dupName_63_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15935_dupName_63_i_unnamed_c_compstr0_shift_x(MUX,15934)@45
    assign rightShiftStage1_uid15935_dupName_63_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15935_dupName_63_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15930_dupName_63_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15933_dupName_63_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15935_dupName_63_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15935_dupName_63_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15930_dupName_63_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15935_dupName_63_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15933_dupName_63_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15935_dupName_63_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15940_dupName_63_i_unnamed_c_compstr0_shift_x(MUX,15939)@45
    assign rightShiftStage2_uid15940_dupName_63_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15940_dupName_63_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15935_dupName_63_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid15938_dupName_63_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15940_dupName_63_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid15940_dupName_63_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15935_dupName_63_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid15940_dupName_63_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid15938_dupName_63_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid15940_dupName_63_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr469_vt_select_20(BITSELECT,12159)@45
    assign i_unnamed_c_compstr469_vt_select_20_b = rightShiftStage2_uid15940_dupName_63_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr469_vt_join(BITJOIN,12158)@45
    assign i_unnamed_c_compstr469_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr469_vt_select_20_b};

    // i_conv_i_i_i_i97_i_16_c_compstr470_sel_x(BITSELECT,3491)@45
    assign i_conv_i_i_i_i97_i_16_c_compstr470_sel_x_b = i_unnamed_c_compstr469_vt_join_q[15:0];

    // redist1245_i_conv_i_i_i_i97_i_16_c_compstr470_sel_x_b_1(DELAY,29473)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1245_i_conv_i_i_i_i97_i_16_c_compstr470_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_16_c_compstr470_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15949_dupName_64_i_unnamed_c_compstr0_shift_x(BITSELECT,15948)@45
    assign rightShiftStage1Idx1Rng8_uid15949_dupName_64_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid15948_dupName_64_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15951_dupName_64_i_unnamed_c_compstr0_shift_x(BITJOIN,15950)@45
    assign rightShiftStage1Idx1_uid15951_dupName_64_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid15949_dupName_64_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15944_dupName_64_i_unnamed_c_compstr0_shift_x(BITSELECT,15943)@45
    assign rightShiftStage0Idx1Rng4_uid15944_dupName_64_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_q[33:4];

    // rightShiftStage0Idx1_uid15946_dupName_64_i_unnamed_c_compstr0_shift_x(BITJOIN,15945)@45
    assign rightShiftStage0Idx1_uid15946_dupName_64_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid15944_dupName_64_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid15948_dupName_64_i_unnamed_c_compstr0_shift_x(MUX,15947)@45
    assign rightShiftStage0_uid15948_dupName_64_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15948_dupName_64_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_q or rightShiftStage0Idx1_uid15946_dupName_64_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15948_dupName_64_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15948_dupName_64_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compstr468_q;
            1'b1 : rightShiftStage0_uid15948_dupName_64_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15946_dupName_64_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15948_dupName_64_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15953_dupName_64_i_unnamed_c_compstr0_shift_x(MUX,15952)@45
    assign rightShiftStage1_uid15953_dupName_64_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15953_dupName_64_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15948_dupName_64_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15951_dupName_64_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15953_dupName_64_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15953_dupName_64_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15948_dupName_64_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15953_dupName_64_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15951_dupName_64_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15953_dupName_64_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr471_vt_select_21(BITSELECT,12162)@45
    assign i_unnamed_c_compstr471_vt_select_21_b = rightShiftStage1_uid15953_dupName_64_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr471_vt_join(BITJOIN,12161)@45
    assign i_unnamed_c_compstr471_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr471_vt_select_21_b};

    // i_unnamed_c_compstr472_sel_x(BITSELECT,6249)@45
    assign i_unnamed_c_compstr472_sel_x_b = i_unnamed_c_compstr471_vt_join_q[15:0];

    // i_unnamed_c_compstr473_BitSelect_for_a(BITSELECT,27887)@45
    assign i_unnamed_c_compstr473_BitSelect_for_a_b = i_unnamed_c_compstr472_sel_x_b[0:0];

    // i_unnamed_c_compstr473_join(BITJOIN,27888)@45
    assign i_unnamed_c_compstr473_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr473_BitSelect_for_a_b};

    // i_unnamed_c_compstr473_vt_select_0(BITSELECT,12167)@45
    assign i_unnamed_c_compstr473_vt_select_0_b = i_unnamed_c_compstr473_join_q[0:0];

    // redist43_i_unnamed_c_compstr473_vt_select_0_b_1(DELAY,28271)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist43_i_unnamed_c_compstr473_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr473_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr473_vt_join(BITJOIN,12166)@46
    assign i_unnamed_c_compstr473_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist43_i_unnamed_c_compstr473_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_16_c_compstr474(ADD,6886)@46
    assign i_add_i_i_i_i_i126_i_16_c_compstr474_a = {1'b0, i_unnamed_c_compstr473_vt_join_q};
    assign i_add_i_i_i_i_i126_i_16_c_compstr474_b = {1'b0, redist1245_i_conv_i_i_i_i97_i_16_c_compstr470_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_16_c_compstr474_o = $unsigned(i_add_i_i_i_i_i126_i_16_c_compstr474_a) + $unsigned(i_add_i_i_i_i_i126_i_16_c_compstr474_b);
    assign i_add_i_i_i_i_i126_i_16_c_compstr474_q = i_add_i_i_i_i_i126_i_16_c_compstr474_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_16_c_compstr474_sel_x(BITSELECT,2080)@46
    assign bgTrunc_i_add_i_i_i_i_i126_i_16_c_compstr474_sel_x_b = i_add_i_i_i_i_i126_i_16_c_compstr474_q[15:0];

    // i_conv_i_i_i_i_i75_i277_17_c_compstr494_sel_x(BITSELECT,3621)@46
    assign i_conv_i_i_i_i_i75_i277_17_c_compstr494_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_16_c_compstr474_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_17_c_compstr494_vt_select_15(BITSELECT,7385)@46
    assign i_conv_i_i_i_i_i75_i277_17_c_compstr494_vt_select_15_b = i_conv_i_i_i_i_i75_i277_17_c_compstr494_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_17_c_compstr494_vt_join(BITJOIN,7384)@46
    assign i_conv_i_i_i_i_i75_i277_17_c_compstr494_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_17_c_compstr494_vt_select_15_b};

    // leftShiftStage0_uid23504_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x(MUX,23503)@46
    assign leftShiftStage0_uid23504_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23504_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_17_c_compstr494_vt_join_q or leftShiftStage0Idx1_uid23502_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23504_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23504_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_17_c_compstr494_vt_join_q;
            1'b1 : leftShiftStage0_uid23504_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23502_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23504_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23509_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x(MUX,23508)@46
    assign leftShiftStage1_uid23509_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23509_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_s or leftShiftStage0_uid23504_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23507_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23509_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23509_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q = leftShiftStage0_uid23504_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23509_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23507_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23509_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23514_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x(MUX,23513)@46
    assign leftShiftStage2_uid23514_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23514_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_s or leftShiftStage1_uid23509_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23512_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23514_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23514_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q = leftShiftStage1_uid23509_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23514_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23512_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23514_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_17_c_compstr495_vt_select_28(BITSELECT,9148)@46
    assign i_shl_i_i_i_i_i77_i_17_c_compstr495_vt_select_28_b = leftShiftStage2_uid23514_i_shl_i_i_i_i_i77_i_17_c_compstr0_shift_x_q[28:13];

    // redist474_i_shl_i_i_i_i_i77_i_17_c_compstr495_vt_select_28_b_1(DELAY,28702)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist474_i_shl_i_i_i_i_i77_i_17_c_compstr495_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_17_c_compstr495_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_17_c_compstr495_vt_join(BITJOIN,9147)@47
    assign i_shl_i_i_i_i_i77_i_17_c_compstr495_vt_join_q = {redist474_i_shl_i_i_i_i_i77_i_17_c_compstr495_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma(CHAINMULTADD,28134)@41 + 5
    // out q@47
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ah[0] <= redist805_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_35_tpl_33_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ah[1] <= redist804_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_34_tpl_33_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ch[0] <= redist551_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_35_tpl_33_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ch[1] <= redist550_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_34_tpl_33_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496(ADD,8430)@47
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compstr491_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compstr493_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compstr492_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_17_c_compstr495_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_17_c_compstr495_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_o[33:0];

    // rightShiftStage0_uid15992_dupName_67_i_unnamed_c_compstr0_shift_x(MUX,15991)@47
    assign rightShiftStage0_uid15992_dupName_67_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15992_dupName_67_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_q or rightShiftStage0Idx1_uid15990_dupName_67_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15992_dupName_67_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid15992_dupName_67_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_q;
            1'b1 : rightShiftStage0_uid15992_dupName_67_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid15990_dupName_67_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid15992_dupName_67_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15997_dupName_67_i_unnamed_c_compstr0_shift_x(MUX,15996)@47
    assign rightShiftStage1_uid15997_dupName_67_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15997_dupName_67_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid15992_dupName_67_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid15995_dupName_67_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15997_dupName_67_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid15997_dupName_67_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid15992_dupName_67_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid15997_dupName_67_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid15995_dupName_67_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid15997_dupName_67_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16002_dupName_67_i_unnamed_c_compstr0_shift_x(MUX,16001)@47
    assign rightShiftStage2_uid16002_dupName_67_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16002_dupName_67_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid15997_dupName_67_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16000_dupName_67_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16002_dupName_67_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16002_dupName_67_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid15997_dupName_67_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16002_dupName_67_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16000_dupName_67_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16002_dupName_67_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr497_vt_select_20(BITSELECT,12181)@47
    assign i_unnamed_c_compstr497_vt_select_20_b = rightShiftStage2_uid16002_dupName_67_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr497_vt_join(BITJOIN,12180)@47
    assign i_unnamed_c_compstr497_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr497_vt_select_20_b};

    // i_conv_i_i_i_i97_i_17_c_compstr498_sel_x(BITSELECT,3492)@47
    assign i_conv_i_i_i_i97_i_17_c_compstr498_sel_x_b = i_unnamed_c_compstr497_vt_join_q[15:0];

    // redist1244_i_conv_i_i_i_i97_i_17_c_compstr498_sel_x_b_1(DELAY,29472)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1244_i_conv_i_i_i_i97_i_17_c_compstr498_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_17_c_compstr498_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16011_dupName_68_i_unnamed_c_compstr0_shift_x(BITSELECT,16010)@47
    assign rightShiftStage1Idx1Rng8_uid16011_dupName_68_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16010_dupName_68_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16013_dupName_68_i_unnamed_c_compstr0_shift_x(BITJOIN,16012)@47
    assign rightShiftStage1Idx1_uid16013_dupName_68_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16011_dupName_68_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16006_dupName_68_i_unnamed_c_compstr0_shift_x(BITSELECT,16005)@47
    assign rightShiftStage0Idx1Rng4_uid16006_dupName_68_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_q[33:4];

    // rightShiftStage0Idx1_uid16008_dupName_68_i_unnamed_c_compstr0_shift_x(BITJOIN,16007)@47
    assign rightShiftStage0Idx1_uid16008_dupName_68_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16006_dupName_68_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16010_dupName_68_i_unnamed_c_compstr0_shift_x(MUX,16009)@47
    assign rightShiftStage0_uid16010_dupName_68_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16010_dupName_68_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_q or rightShiftStage0Idx1_uid16008_dupName_68_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16010_dupName_68_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16010_dupName_68_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compstr496_q;
            1'b1 : rightShiftStage0_uid16010_dupName_68_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16008_dupName_68_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16010_dupName_68_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16015_dupName_68_i_unnamed_c_compstr0_shift_x(MUX,16014)@47
    assign rightShiftStage1_uid16015_dupName_68_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16015_dupName_68_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16010_dupName_68_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16013_dupName_68_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16015_dupName_68_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16015_dupName_68_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16010_dupName_68_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16015_dupName_68_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16013_dupName_68_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16015_dupName_68_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr499_vt_select_21(BITSELECT,12184)@47
    assign i_unnamed_c_compstr499_vt_select_21_b = rightShiftStage1_uid16015_dupName_68_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr499_vt_join(BITJOIN,12183)@47
    assign i_unnamed_c_compstr499_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr499_vt_select_21_b};

    // i_unnamed_c_compstr500_sel_x(BITSELECT,6251)@47
    assign i_unnamed_c_compstr500_sel_x_b = i_unnamed_c_compstr499_vt_join_q[15:0];

    // i_unnamed_c_compstr501_BitSelect_for_a(BITSELECT,27891)@47
    assign i_unnamed_c_compstr501_BitSelect_for_a_b = i_unnamed_c_compstr500_sel_x_b[0:0];

    // i_unnamed_c_compstr501_join(BITJOIN,27892)@47
    assign i_unnamed_c_compstr501_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr501_BitSelect_for_a_b};

    // i_unnamed_c_compstr501_vt_select_0(BITSELECT,12192)@47
    assign i_unnamed_c_compstr501_vt_select_0_b = i_unnamed_c_compstr501_join_q[0:0];

    // redist41_i_unnamed_c_compstr501_vt_select_0_b_1(DELAY,28269)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist41_i_unnamed_c_compstr501_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr501_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr501_vt_join(BITJOIN,12191)@48
    assign i_unnamed_c_compstr501_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist41_i_unnamed_c_compstr501_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_17_c_compstr502(ADD,6887)@48
    assign i_add_i_i_i_i_i126_i_17_c_compstr502_a = {1'b0, i_unnamed_c_compstr501_vt_join_q};
    assign i_add_i_i_i_i_i126_i_17_c_compstr502_b = {1'b0, redist1244_i_conv_i_i_i_i97_i_17_c_compstr498_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_17_c_compstr502_o = $unsigned(i_add_i_i_i_i_i126_i_17_c_compstr502_a) + $unsigned(i_add_i_i_i_i_i126_i_17_c_compstr502_b);
    assign i_add_i_i_i_i_i126_i_17_c_compstr502_q = i_add_i_i_i_i_i126_i_17_c_compstr502_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_17_c_compstr502_sel_x(BITSELECT,2081)@48
    assign bgTrunc_i_add_i_i_i_i_i126_i_17_c_compstr502_sel_x_b = i_add_i_i_i_i_i126_i_17_c_compstr502_q[15:0];

    // i_conv_i_i_i_i_i75_i277_18_c_compstr522_sel_x(BITSELECT,3622)@48
    assign i_conv_i_i_i_i_i75_i277_18_c_compstr522_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_17_c_compstr502_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_18_c_compstr522_vt_select_15(BITSELECT,7389)@48
    assign i_conv_i_i_i_i_i75_i277_18_c_compstr522_vt_select_15_b = i_conv_i_i_i_i_i75_i277_18_c_compstr522_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_18_c_compstr522_vt_join(BITJOIN,7388)@48
    assign i_conv_i_i_i_i_i75_i277_18_c_compstr522_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_18_c_compstr522_vt_select_15_b};

    // leftShiftStage0_uid23522_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x(MUX,23521)@48
    assign leftShiftStage0_uid23522_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23522_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_18_c_compstr522_vt_join_q or leftShiftStage0Idx1_uid23520_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23522_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23522_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_18_c_compstr522_vt_join_q;
            1'b1 : leftShiftStage0_uid23522_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23520_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23522_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23527_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x(MUX,23526)@48
    assign leftShiftStage1_uid23527_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23527_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_s or leftShiftStage0_uid23522_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23525_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23527_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23527_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q = leftShiftStage0_uid23522_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23527_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23525_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23527_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23532_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x(MUX,23531)@48
    assign leftShiftStage2_uid23532_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23532_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_s or leftShiftStage1_uid23527_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23530_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23532_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23532_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q = leftShiftStage1_uid23527_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23532_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23530_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23532_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_18_c_compstr523_vt_select_28(BITSELECT,9151)@48
    assign i_shl_i_i_i_i_i77_i_18_c_compstr523_vt_select_28_b = leftShiftStage2_uid23532_i_shl_i_i_i_i_i77_i_18_c_compstr0_shift_x_q[28:13];

    // redist473_i_shl_i_i_i_i_i77_i_18_c_compstr523_vt_select_28_b_1(DELAY,28701)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist473_i_shl_i_i_i_i_i77_i_18_c_compstr523_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_18_c_compstr523_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_18_c_compstr523_vt_join(BITJOIN,9150)@49
    assign i_shl_i_i_i_i_i77_i_18_c_compstr523_vt_join_q = {redist473_i_shl_i_i_i_i_i77_i_18_c_compstr523_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma(CHAINMULTADD,28135)@43 + 5
    // out q@49
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ah[0] <= redist807_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_37_tpl_35_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ah[1] <= redist806_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_36_tpl_35_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ch[0] <= redist553_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_37_tpl_35_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ch[1] <= redist552_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_36_tpl_35_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524(ADD,8431)@49
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compstr519_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compstr521_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compstr520_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_18_c_compstr523_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_18_c_compstr523_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_o[33:0];

    // rightShiftStage0_uid16054_dupName_71_i_unnamed_c_compstr0_shift_x(MUX,16053)@49
    assign rightShiftStage0_uid16054_dupName_71_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16054_dupName_71_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_q or rightShiftStage0Idx1_uid16052_dupName_71_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16054_dupName_71_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16054_dupName_71_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_q;
            1'b1 : rightShiftStage0_uid16054_dupName_71_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16052_dupName_71_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16054_dupName_71_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16059_dupName_71_i_unnamed_c_compstr0_shift_x(MUX,16058)@49
    assign rightShiftStage1_uid16059_dupName_71_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16059_dupName_71_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16054_dupName_71_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16057_dupName_71_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16059_dupName_71_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16059_dupName_71_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16054_dupName_71_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16059_dupName_71_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16057_dupName_71_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16059_dupName_71_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16064_dupName_71_i_unnamed_c_compstr0_shift_x(MUX,16063)@49
    assign rightShiftStage2_uid16064_dupName_71_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16064_dupName_71_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16059_dupName_71_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16062_dupName_71_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16064_dupName_71_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16064_dupName_71_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16059_dupName_71_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16064_dupName_71_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16062_dupName_71_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16064_dupName_71_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr525_vt_select_20(BITSELECT,12209)@49
    assign i_unnamed_c_compstr525_vt_select_20_b = rightShiftStage2_uid16064_dupName_71_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr525_vt_join(BITJOIN,12208)@49
    assign i_unnamed_c_compstr525_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr525_vt_select_20_b};

    // i_conv_i_i_i_i97_i_18_c_compstr526_sel_x(BITSELECT,3493)@49
    assign i_conv_i_i_i_i97_i_18_c_compstr526_sel_x_b = i_unnamed_c_compstr525_vt_join_q[15:0];

    // redist1243_i_conv_i_i_i_i97_i_18_c_compstr526_sel_x_b_1(DELAY,29471)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1243_i_conv_i_i_i_i97_i_18_c_compstr526_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_18_c_compstr526_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16073_dupName_72_i_unnamed_c_compstr0_shift_x(BITSELECT,16072)@49
    assign rightShiftStage1Idx1Rng8_uid16073_dupName_72_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16072_dupName_72_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16075_dupName_72_i_unnamed_c_compstr0_shift_x(BITJOIN,16074)@49
    assign rightShiftStage1Idx1_uid16075_dupName_72_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16073_dupName_72_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16068_dupName_72_i_unnamed_c_compstr0_shift_x(BITSELECT,16067)@49
    assign rightShiftStage0Idx1Rng4_uid16068_dupName_72_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_q[33:4];

    // rightShiftStage0Idx1_uid16070_dupName_72_i_unnamed_c_compstr0_shift_x(BITJOIN,16069)@49
    assign rightShiftStage0Idx1_uid16070_dupName_72_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16068_dupName_72_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16072_dupName_72_i_unnamed_c_compstr0_shift_x(MUX,16071)@49
    assign rightShiftStage0_uid16072_dupName_72_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16072_dupName_72_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_q or rightShiftStage0Idx1_uid16070_dupName_72_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16072_dupName_72_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16072_dupName_72_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compstr524_q;
            1'b1 : rightShiftStage0_uid16072_dupName_72_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16070_dupName_72_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16072_dupName_72_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16077_dupName_72_i_unnamed_c_compstr0_shift_x(MUX,16076)@49
    assign rightShiftStage1_uid16077_dupName_72_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16077_dupName_72_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16072_dupName_72_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16075_dupName_72_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16077_dupName_72_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16077_dupName_72_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16072_dupName_72_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16077_dupName_72_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16075_dupName_72_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16077_dupName_72_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr527_vt_select_21(BITSELECT,12212)@49
    assign i_unnamed_c_compstr527_vt_select_21_b = rightShiftStage1_uid16077_dupName_72_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr527_vt_join(BITJOIN,12211)@49
    assign i_unnamed_c_compstr527_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr527_vt_select_21_b};

    // i_unnamed_c_compstr528_sel_x(BITSELECT,6254)@49
    assign i_unnamed_c_compstr528_sel_x_b = i_unnamed_c_compstr527_vt_join_q[15:0];

    // i_unnamed_c_compstr529_BitSelect_for_a(BITSELECT,27895)@49
    assign i_unnamed_c_compstr529_BitSelect_for_a_b = i_unnamed_c_compstr528_sel_x_b[0:0];

    // i_unnamed_c_compstr529_join(BITJOIN,27896)@49
    assign i_unnamed_c_compstr529_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr529_BitSelect_for_a_b};

    // i_unnamed_c_compstr529_vt_select_0(BITSELECT,12217)@49
    assign i_unnamed_c_compstr529_vt_select_0_b = i_unnamed_c_compstr529_join_q[0:0];

    // redist39_i_unnamed_c_compstr529_vt_select_0_b_1(DELAY,28267)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist39_i_unnamed_c_compstr529_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr529_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr529_vt_join(BITJOIN,12216)@50
    assign i_unnamed_c_compstr529_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist39_i_unnamed_c_compstr529_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_18_c_compstr530(ADD,6888)@50
    assign i_add_i_i_i_i_i126_i_18_c_compstr530_a = {1'b0, i_unnamed_c_compstr529_vt_join_q};
    assign i_add_i_i_i_i_i126_i_18_c_compstr530_b = {1'b0, redist1243_i_conv_i_i_i_i97_i_18_c_compstr526_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_18_c_compstr530_o = $unsigned(i_add_i_i_i_i_i126_i_18_c_compstr530_a) + $unsigned(i_add_i_i_i_i_i126_i_18_c_compstr530_b);
    assign i_add_i_i_i_i_i126_i_18_c_compstr530_q = i_add_i_i_i_i_i126_i_18_c_compstr530_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_18_c_compstr530_sel_x(BITSELECT,2082)@50
    assign bgTrunc_i_add_i_i_i_i_i126_i_18_c_compstr530_sel_x_b = i_add_i_i_i_i_i126_i_18_c_compstr530_q[15:0];

    // i_conv_i_i_i_i_i75_i277_19_c_compstr550_sel_x(BITSELECT,3623)@50
    assign i_conv_i_i_i_i_i75_i277_19_c_compstr550_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_18_c_compstr530_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_19_c_compstr550_vt_select_15(BITSELECT,7393)@50
    assign i_conv_i_i_i_i_i75_i277_19_c_compstr550_vt_select_15_b = i_conv_i_i_i_i_i75_i277_19_c_compstr550_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_19_c_compstr550_vt_join(BITJOIN,7392)@50
    assign i_conv_i_i_i_i_i75_i277_19_c_compstr550_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_19_c_compstr550_vt_select_15_b};

    // leftShiftStage0_uid23540_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x(MUX,23539)@50
    assign leftShiftStage0_uid23540_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23540_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_19_c_compstr550_vt_join_q or leftShiftStage0Idx1_uid23538_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23540_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23540_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_19_c_compstr550_vt_join_q;
            1'b1 : leftShiftStage0_uid23540_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23538_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23540_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23545_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x(MUX,23544)@50
    assign leftShiftStage1_uid23545_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23545_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_s or leftShiftStage0_uid23540_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23543_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23545_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23545_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q = leftShiftStage0_uid23540_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23545_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23543_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23545_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23550_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x(MUX,23549)@50
    assign leftShiftStage2_uid23550_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23550_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_s or leftShiftStage1_uid23545_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23548_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23550_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23550_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q = leftShiftStage1_uid23545_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23550_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23548_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23550_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_19_c_compstr551_vt_select_28(BITSELECT,9154)@50
    assign i_shl_i_i_i_i_i77_i_19_c_compstr551_vt_select_28_b = leftShiftStage2_uid23550_i_shl_i_i_i_i_i77_i_19_c_compstr0_shift_x_q[28:13];

    // redist472_i_shl_i_i_i_i_i77_i_19_c_compstr551_vt_select_28_b_1(DELAY,28700)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist472_i_shl_i_i_i_i_i77_i_19_c_compstr551_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_19_c_compstr551_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_19_c_compstr551_vt_join(BITJOIN,9153)@51
    assign i_shl_i_i_i_i_i77_i_19_c_compstr551_vt_join_q = {redist472_i_shl_i_i_i_i_i77_i_19_c_compstr551_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma(CHAINMULTADD,28136)@45 + 5
    // out q@51
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ah[0] <= redist809_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_39_tpl_37_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ah[1] <= redist808_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_38_tpl_37_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ch[0] <= redist555_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_39_tpl_37_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ch[1] <= redist554_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_38_tpl_37_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552(ADD,8432)@51
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compstr547_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compstr549_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compstr548_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_19_c_compstr551_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_19_c_compstr551_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_o[33:0];

    // rightShiftStage0_uid16116_dupName_75_i_unnamed_c_compstr0_shift_x(MUX,16115)@51
    assign rightShiftStage0_uid16116_dupName_75_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16116_dupName_75_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_q or rightShiftStage0Idx1_uid16114_dupName_75_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16116_dupName_75_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16116_dupName_75_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_q;
            1'b1 : rightShiftStage0_uid16116_dupName_75_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16114_dupName_75_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16116_dupName_75_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16121_dupName_75_i_unnamed_c_compstr0_shift_x(MUX,16120)@51
    assign rightShiftStage1_uid16121_dupName_75_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16121_dupName_75_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16116_dupName_75_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16119_dupName_75_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16121_dupName_75_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16121_dupName_75_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16116_dupName_75_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16121_dupName_75_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16119_dupName_75_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16121_dupName_75_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16126_dupName_75_i_unnamed_c_compstr0_shift_x(MUX,16125)@51
    assign rightShiftStage2_uid16126_dupName_75_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16126_dupName_75_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16121_dupName_75_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16124_dupName_75_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16126_dupName_75_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16126_dupName_75_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16121_dupName_75_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16126_dupName_75_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16124_dupName_75_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16126_dupName_75_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr553_vt_select_20(BITSELECT,12236)@51
    assign i_unnamed_c_compstr553_vt_select_20_b = rightShiftStage2_uid16126_dupName_75_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr553_vt_join(BITJOIN,12235)@51
    assign i_unnamed_c_compstr553_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr553_vt_select_20_b};

    // i_conv_i_i_i_i97_i_19_c_compstr554_sel_x(BITSELECT,3494)@51
    assign i_conv_i_i_i_i97_i_19_c_compstr554_sel_x_b = i_unnamed_c_compstr553_vt_join_q[15:0];

    // redist1242_i_conv_i_i_i_i97_i_19_c_compstr554_sel_x_b_1(DELAY,29470)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1242_i_conv_i_i_i_i97_i_19_c_compstr554_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_19_c_compstr554_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16135_dupName_76_i_unnamed_c_compstr0_shift_x(BITSELECT,16134)@51
    assign rightShiftStage1Idx1Rng8_uid16135_dupName_76_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16134_dupName_76_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16137_dupName_76_i_unnamed_c_compstr0_shift_x(BITJOIN,16136)@51
    assign rightShiftStage1Idx1_uid16137_dupName_76_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16135_dupName_76_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16130_dupName_76_i_unnamed_c_compstr0_shift_x(BITSELECT,16129)@51
    assign rightShiftStage0Idx1Rng4_uid16130_dupName_76_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_q[33:4];

    // rightShiftStage0Idx1_uid16132_dupName_76_i_unnamed_c_compstr0_shift_x(BITJOIN,16131)@51
    assign rightShiftStage0Idx1_uid16132_dupName_76_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16130_dupName_76_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16134_dupName_76_i_unnamed_c_compstr0_shift_x(MUX,16133)@51
    assign rightShiftStage0_uid16134_dupName_76_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16134_dupName_76_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_q or rightShiftStage0Idx1_uid16132_dupName_76_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16134_dupName_76_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16134_dupName_76_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compstr552_q;
            1'b1 : rightShiftStage0_uid16134_dupName_76_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16132_dupName_76_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16134_dupName_76_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16139_dupName_76_i_unnamed_c_compstr0_shift_x(MUX,16138)@51
    assign rightShiftStage1_uid16139_dupName_76_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16139_dupName_76_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16134_dupName_76_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16137_dupName_76_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16139_dupName_76_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16139_dupName_76_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16134_dupName_76_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16139_dupName_76_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16137_dupName_76_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16139_dupName_76_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr555_vt_select_21(BITSELECT,12239)@51
    assign i_unnamed_c_compstr555_vt_select_21_b = rightShiftStage1_uid16139_dupName_76_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr555_vt_join(BITJOIN,12238)@51
    assign i_unnamed_c_compstr555_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr555_vt_select_21_b};

    // i_unnamed_c_compstr556_sel_x(BITSELECT,6256)@51
    assign i_unnamed_c_compstr556_sel_x_b = i_unnamed_c_compstr555_vt_join_q[15:0];

    // i_unnamed_c_compstr557_BitSelect_for_a(BITSELECT,27901)@51
    assign i_unnamed_c_compstr557_BitSelect_for_a_b = i_unnamed_c_compstr556_sel_x_b[0:0];

    // i_unnamed_c_compstr557_join(BITJOIN,27902)@51
    assign i_unnamed_c_compstr557_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr557_BitSelect_for_a_b};

    // i_unnamed_c_compstr557_vt_select_0(BITSELECT,12244)@51
    assign i_unnamed_c_compstr557_vt_select_0_b = i_unnamed_c_compstr557_join_q[0:0];

    // redist36_i_unnamed_c_compstr557_vt_select_0_b_1(DELAY,28264)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist36_i_unnamed_c_compstr557_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr557_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr557_vt_join(BITJOIN,12243)@52
    assign i_unnamed_c_compstr557_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist36_i_unnamed_c_compstr557_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_19_c_compstr558(ADD,6889)@52
    assign i_add_i_i_i_i_i126_i_19_c_compstr558_a = {1'b0, i_unnamed_c_compstr557_vt_join_q};
    assign i_add_i_i_i_i_i126_i_19_c_compstr558_b = {1'b0, redist1242_i_conv_i_i_i_i97_i_19_c_compstr554_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_19_c_compstr558_o = $unsigned(i_add_i_i_i_i_i126_i_19_c_compstr558_a) + $unsigned(i_add_i_i_i_i_i126_i_19_c_compstr558_b);
    assign i_add_i_i_i_i_i126_i_19_c_compstr558_q = i_add_i_i_i_i_i126_i_19_c_compstr558_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_19_c_compstr558_sel_x(BITSELECT,2083)@52
    assign bgTrunc_i_add_i_i_i_i_i126_i_19_c_compstr558_sel_x_b = i_add_i_i_i_i_i126_i_19_c_compstr558_q[15:0];

    // i_conv_i_i_i_i_i75_i277_20_c_compstr578_sel_x(BITSELECT,3625)@52
    assign i_conv_i_i_i_i_i75_i277_20_c_compstr578_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_19_c_compstr558_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_20_c_compstr578_vt_select_15(BITSELECT,7401)@52
    assign i_conv_i_i_i_i_i75_i277_20_c_compstr578_vt_select_15_b = i_conv_i_i_i_i_i75_i277_20_c_compstr578_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_20_c_compstr578_vt_join(BITJOIN,7400)@52
    assign i_conv_i_i_i_i_i75_i277_20_c_compstr578_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_20_c_compstr578_vt_select_15_b};

    // leftShiftStage0_uid23576_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x(MUX,23575)@52
    assign leftShiftStage0_uid23576_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23576_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_20_c_compstr578_vt_join_q or leftShiftStage0Idx1_uid23574_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23576_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23576_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_20_c_compstr578_vt_join_q;
            1'b1 : leftShiftStage0_uid23576_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23574_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23576_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23581_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x(MUX,23580)@52
    assign leftShiftStage1_uid23581_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23581_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_s or leftShiftStage0_uid23576_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23579_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23581_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23581_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q = leftShiftStage0_uid23576_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23581_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23579_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23581_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23586_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x(MUX,23585)@52
    assign leftShiftStage2_uid23586_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23586_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_s or leftShiftStage1_uid23581_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23584_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23586_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23586_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q = leftShiftStage1_uid23581_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23586_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23584_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23586_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_20_c_compstr579_vt_select_28(BITSELECT,9160)@52
    assign i_shl_i_i_i_i_i77_i_20_c_compstr579_vt_select_28_b = leftShiftStage2_uid23586_i_shl_i_i_i_i_i77_i_20_c_compstr0_shift_x_q[28:13];

    // redist470_i_shl_i_i_i_i_i77_i_20_c_compstr579_vt_select_28_b_1(DELAY,28698)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist470_i_shl_i_i_i_i_i77_i_20_c_compstr579_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_20_c_compstr579_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_20_c_compstr579_vt_join(BITJOIN,9159)@53
    assign i_shl_i_i_i_i_i77_i_20_c_compstr579_vt_join_q = {redist470_i_shl_i_i_i_i_i77_i_20_c_compstr579_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma(CHAINMULTADD,28138)@47 + 5
    // out q@53
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ah[0] <= redist811_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_41_tpl_39_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ah[1] <= redist810_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_40_tpl_39_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ch[0] <= redist557_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_41_tpl_39_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ch[1] <= redist556_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_40_tpl_39_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580(ADD,8434)@53
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compstr575_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compstr577_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compstr576_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_20_c_compstr579_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_20_c_compstr579_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_o[33:0];

    // rightShiftStage0_uid16178_dupName_79_i_unnamed_c_compstr0_shift_x(MUX,16177)@53
    assign rightShiftStage0_uid16178_dupName_79_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16178_dupName_79_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_q or rightShiftStage0Idx1_uid16176_dupName_79_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16178_dupName_79_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16178_dupName_79_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_q;
            1'b1 : rightShiftStage0_uid16178_dupName_79_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16176_dupName_79_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16178_dupName_79_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16183_dupName_79_i_unnamed_c_compstr0_shift_x(MUX,16182)@53
    assign rightShiftStage1_uid16183_dupName_79_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16183_dupName_79_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16178_dupName_79_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16181_dupName_79_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16183_dupName_79_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16183_dupName_79_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16178_dupName_79_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16183_dupName_79_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16181_dupName_79_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16183_dupName_79_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16188_dupName_79_i_unnamed_c_compstr0_shift_x(MUX,16187)@53
    assign rightShiftStage2_uid16188_dupName_79_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16188_dupName_79_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16183_dupName_79_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16186_dupName_79_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16188_dupName_79_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16188_dupName_79_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16183_dupName_79_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16188_dupName_79_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16186_dupName_79_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16188_dupName_79_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr581_vt_select_20(BITSELECT,12258)@53
    assign i_unnamed_c_compstr581_vt_select_20_b = rightShiftStage2_uid16188_dupName_79_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr581_vt_join(BITJOIN,12257)@53
    assign i_unnamed_c_compstr581_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr581_vt_select_20_b};

    // i_conv_i_i_i_i97_i_20_c_compstr582_sel_x(BITSELECT,3496)@53
    assign i_conv_i_i_i_i97_i_20_c_compstr582_sel_x_b = i_unnamed_c_compstr581_vt_join_q[15:0];

    // redist1240_i_conv_i_i_i_i97_i_20_c_compstr582_sel_x_b_1(DELAY,29468)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1240_i_conv_i_i_i_i97_i_20_c_compstr582_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_20_c_compstr582_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16197_dupName_80_i_unnamed_c_compstr0_shift_x(BITSELECT,16196)@53
    assign rightShiftStage1Idx1Rng8_uid16197_dupName_80_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16196_dupName_80_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16199_dupName_80_i_unnamed_c_compstr0_shift_x(BITJOIN,16198)@53
    assign rightShiftStage1Idx1_uid16199_dupName_80_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16197_dupName_80_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16192_dupName_80_i_unnamed_c_compstr0_shift_x(BITSELECT,16191)@53
    assign rightShiftStage0Idx1Rng4_uid16192_dupName_80_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_q[33:4];

    // rightShiftStage0Idx1_uid16194_dupName_80_i_unnamed_c_compstr0_shift_x(BITJOIN,16193)@53
    assign rightShiftStage0Idx1_uid16194_dupName_80_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16192_dupName_80_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16196_dupName_80_i_unnamed_c_compstr0_shift_x(MUX,16195)@53
    assign rightShiftStage0_uid16196_dupName_80_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16196_dupName_80_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_q or rightShiftStage0Idx1_uid16194_dupName_80_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16196_dupName_80_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16196_dupName_80_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compstr580_q;
            1'b1 : rightShiftStage0_uid16196_dupName_80_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16194_dupName_80_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16196_dupName_80_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16201_dupName_80_i_unnamed_c_compstr0_shift_x(MUX,16200)@53
    assign rightShiftStage1_uid16201_dupName_80_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16201_dupName_80_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16196_dupName_80_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16199_dupName_80_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16201_dupName_80_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16201_dupName_80_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16196_dupName_80_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16201_dupName_80_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16199_dupName_80_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16201_dupName_80_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr583_vt_select_21(BITSELECT,12261)@53
    assign i_unnamed_c_compstr583_vt_select_21_b = rightShiftStage1_uid16201_dupName_80_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr583_vt_join(BITJOIN,12260)@53
    assign i_unnamed_c_compstr583_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr583_vt_select_21_b};

    // i_unnamed_c_compstr584_sel_x(BITSELECT,6258)@53
    assign i_unnamed_c_compstr584_sel_x_b = i_unnamed_c_compstr583_vt_join_q[15:0];

    // i_unnamed_c_compstr585_BitSelect_for_a(BITSELECT,27905)@53
    assign i_unnamed_c_compstr585_BitSelect_for_a_b = i_unnamed_c_compstr584_sel_x_b[0:0];

    // i_unnamed_c_compstr585_join(BITJOIN,27906)@53
    assign i_unnamed_c_compstr585_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr585_BitSelect_for_a_b};

    // i_unnamed_c_compstr585_vt_select_0(BITSELECT,12266)@53
    assign i_unnamed_c_compstr585_vt_select_0_b = i_unnamed_c_compstr585_join_q[0:0];

    // redist34_i_unnamed_c_compstr585_vt_select_0_b_1(DELAY,28262)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist34_i_unnamed_c_compstr585_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr585_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr585_vt_join(BITJOIN,12265)@54
    assign i_unnamed_c_compstr585_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist34_i_unnamed_c_compstr585_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_20_c_compstr586(ADD,6891)@54
    assign i_add_i_i_i_i_i126_i_20_c_compstr586_a = {1'b0, i_unnamed_c_compstr585_vt_join_q};
    assign i_add_i_i_i_i_i126_i_20_c_compstr586_b = {1'b0, redist1240_i_conv_i_i_i_i97_i_20_c_compstr582_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_20_c_compstr586_o = $unsigned(i_add_i_i_i_i_i126_i_20_c_compstr586_a) + $unsigned(i_add_i_i_i_i_i126_i_20_c_compstr586_b);
    assign i_add_i_i_i_i_i126_i_20_c_compstr586_q = i_add_i_i_i_i_i126_i_20_c_compstr586_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_20_c_compstr586_sel_x(BITSELECT,2085)@54
    assign bgTrunc_i_add_i_i_i_i_i126_i_20_c_compstr586_sel_x_b = i_add_i_i_i_i_i126_i_20_c_compstr586_q[15:0];

    // i_conv_i_i_i_i_i75_i277_21_c_compstr606_sel_x(BITSELECT,3626)@54
    assign i_conv_i_i_i_i_i75_i277_21_c_compstr606_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_20_c_compstr586_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_21_c_compstr606_vt_select_15(BITSELECT,7405)@54
    assign i_conv_i_i_i_i_i75_i277_21_c_compstr606_vt_select_15_b = i_conv_i_i_i_i_i75_i277_21_c_compstr606_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_21_c_compstr606_vt_join(BITJOIN,7404)@54
    assign i_conv_i_i_i_i_i75_i277_21_c_compstr606_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_21_c_compstr606_vt_select_15_b};

    // leftShiftStage0_uid23594_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x(MUX,23593)@54
    assign leftShiftStage0_uid23594_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23594_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_21_c_compstr606_vt_join_q or leftShiftStage0Idx1_uid23592_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23594_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23594_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_21_c_compstr606_vt_join_q;
            1'b1 : leftShiftStage0_uid23594_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23592_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23594_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23599_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x(MUX,23598)@54
    assign leftShiftStage1_uid23599_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23599_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_s or leftShiftStage0_uid23594_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23597_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23599_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23599_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q = leftShiftStage0_uid23594_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23599_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23597_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23599_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23604_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x(MUX,23603)@54
    assign leftShiftStage2_uid23604_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23604_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_s or leftShiftStage1_uid23599_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23602_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23604_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23604_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q = leftShiftStage1_uid23599_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23604_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23602_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23604_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_21_c_compstr607_vt_select_28(BITSELECT,9163)@54
    assign i_shl_i_i_i_i_i77_i_21_c_compstr607_vt_select_28_b = leftShiftStage2_uid23604_i_shl_i_i_i_i_i77_i_21_c_compstr0_shift_x_q[28:13];

    // redist469_i_shl_i_i_i_i_i77_i_21_c_compstr607_vt_select_28_b_1(DELAY,28697)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist469_i_shl_i_i_i_i_i77_i_21_c_compstr607_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_21_c_compstr607_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_21_c_compstr607_vt_join(BITJOIN,9162)@55
    assign i_shl_i_i_i_i_i77_i_21_c_compstr607_vt_join_q = {redist469_i_shl_i_i_i_i_i77_i_21_c_compstr607_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma(CHAINMULTADD,28139)@49 + 5
    // out q@55
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ah[0] <= redist813_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_43_tpl_41_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ah[1] <= redist812_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_42_tpl_41_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ch[0] <= redist559_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_43_tpl_41_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ch[1] <= redist558_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_42_tpl_41_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608(ADD,8435)@55
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compstr603_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compstr605_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compstr604_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_21_c_compstr607_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_21_c_compstr607_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_o[33:0];

    // rightShiftStage0_uid16240_dupName_83_i_unnamed_c_compstr0_shift_x(MUX,16239)@55
    assign rightShiftStage0_uid16240_dupName_83_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16240_dupName_83_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_q or rightShiftStage0Idx1_uid16238_dupName_83_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16240_dupName_83_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16240_dupName_83_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_q;
            1'b1 : rightShiftStage0_uid16240_dupName_83_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16238_dupName_83_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16240_dupName_83_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16245_dupName_83_i_unnamed_c_compstr0_shift_x(MUX,16244)@55
    assign rightShiftStage1_uid16245_dupName_83_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16245_dupName_83_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16240_dupName_83_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16243_dupName_83_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16245_dupName_83_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16245_dupName_83_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16240_dupName_83_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16245_dupName_83_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16243_dupName_83_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16245_dupName_83_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16250_dupName_83_i_unnamed_c_compstr0_shift_x(MUX,16249)@55
    assign rightShiftStage2_uid16250_dupName_83_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16250_dupName_83_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16245_dupName_83_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16248_dupName_83_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16250_dupName_83_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16250_dupName_83_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16245_dupName_83_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16250_dupName_83_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16248_dupName_83_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16250_dupName_83_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr609_vt_select_20(BITSELECT,12280)@55
    assign i_unnamed_c_compstr609_vt_select_20_b = rightShiftStage2_uid16250_dupName_83_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr609_vt_join(BITJOIN,12279)@55
    assign i_unnamed_c_compstr609_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr609_vt_select_20_b};

    // i_conv_i_i_i_i97_i_21_c_compstr610_sel_x(BITSELECT,3497)@55
    assign i_conv_i_i_i_i97_i_21_c_compstr610_sel_x_b = i_unnamed_c_compstr609_vt_join_q[15:0];

    // redist1239_i_conv_i_i_i_i97_i_21_c_compstr610_sel_x_b_1(DELAY,29467)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1239_i_conv_i_i_i_i97_i_21_c_compstr610_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_21_c_compstr610_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16259_dupName_84_i_unnamed_c_compstr0_shift_x(BITSELECT,16258)@55
    assign rightShiftStage1Idx1Rng8_uid16259_dupName_84_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16258_dupName_84_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16261_dupName_84_i_unnamed_c_compstr0_shift_x(BITJOIN,16260)@55
    assign rightShiftStage1Idx1_uid16261_dupName_84_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16259_dupName_84_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16254_dupName_84_i_unnamed_c_compstr0_shift_x(BITSELECT,16253)@55
    assign rightShiftStage0Idx1Rng4_uid16254_dupName_84_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_q[33:4];

    // rightShiftStage0Idx1_uid16256_dupName_84_i_unnamed_c_compstr0_shift_x(BITJOIN,16255)@55
    assign rightShiftStage0Idx1_uid16256_dupName_84_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16254_dupName_84_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16258_dupName_84_i_unnamed_c_compstr0_shift_x(MUX,16257)@55
    assign rightShiftStage0_uid16258_dupName_84_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16258_dupName_84_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_q or rightShiftStage0Idx1_uid16256_dupName_84_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16258_dupName_84_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16258_dupName_84_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compstr608_q;
            1'b1 : rightShiftStage0_uid16258_dupName_84_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16256_dupName_84_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16258_dupName_84_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16263_dupName_84_i_unnamed_c_compstr0_shift_x(MUX,16262)@55
    assign rightShiftStage1_uid16263_dupName_84_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16263_dupName_84_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16258_dupName_84_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16261_dupName_84_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16263_dupName_84_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16263_dupName_84_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16258_dupName_84_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16263_dupName_84_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16261_dupName_84_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16263_dupName_84_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr611_vt_select_21(BITSELECT,12283)@55
    assign i_unnamed_c_compstr611_vt_select_21_b = rightShiftStage1_uid16263_dupName_84_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr611_vt_join(BITJOIN,12282)@55
    assign i_unnamed_c_compstr611_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr611_vt_select_21_b};

    // i_unnamed_c_compstr612_sel_x(BITSELECT,6260)@55
    assign i_unnamed_c_compstr612_sel_x_b = i_unnamed_c_compstr611_vt_join_q[15:0];

    // i_unnamed_c_compstr613_BitSelect_for_a(BITSELECT,27909)@55
    assign i_unnamed_c_compstr613_BitSelect_for_a_b = i_unnamed_c_compstr612_sel_x_b[0:0];

    // i_unnamed_c_compstr613_join(BITJOIN,27910)@55
    assign i_unnamed_c_compstr613_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr613_BitSelect_for_a_b};

    // i_unnamed_c_compstr613_vt_select_0(BITSELECT,12288)@55
    assign i_unnamed_c_compstr613_vt_select_0_b = i_unnamed_c_compstr613_join_q[0:0];

    // redist32_i_unnamed_c_compstr613_vt_select_0_b_1(DELAY,28260)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist32_i_unnamed_c_compstr613_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr613_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr613_vt_join(BITJOIN,12287)@56
    assign i_unnamed_c_compstr613_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist32_i_unnamed_c_compstr613_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_21_c_compstr614(ADD,6892)@56
    assign i_add_i_i_i_i_i126_i_21_c_compstr614_a = {1'b0, i_unnamed_c_compstr613_vt_join_q};
    assign i_add_i_i_i_i_i126_i_21_c_compstr614_b = {1'b0, redist1239_i_conv_i_i_i_i97_i_21_c_compstr610_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_21_c_compstr614_o = $unsigned(i_add_i_i_i_i_i126_i_21_c_compstr614_a) + $unsigned(i_add_i_i_i_i_i126_i_21_c_compstr614_b);
    assign i_add_i_i_i_i_i126_i_21_c_compstr614_q = i_add_i_i_i_i_i126_i_21_c_compstr614_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_21_c_compstr614_sel_x(BITSELECT,2086)@56
    assign bgTrunc_i_add_i_i_i_i_i126_i_21_c_compstr614_sel_x_b = i_add_i_i_i_i_i126_i_21_c_compstr614_q[15:0];

    // i_conv_i_i_i_i_i75_i277_22_c_compstr634_sel_x(BITSELECT,3627)@56
    assign i_conv_i_i_i_i_i75_i277_22_c_compstr634_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_21_c_compstr614_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_22_c_compstr634_vt_select_15(BITSELECT,7409)@56
    assign i_conv_i_i_i_i_i75_i277_22_c_compstr634_vt_select_15_b = i_conv_i_i_i_i_i75_i277_22_c_compstr634_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_22_c_compstr634_vt_join(BITJOIN,7408)@56
    assign i_conv_i_i_i_i_i75_i277_22_c_compstr634_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_22_c_compstr634_vt_select_15_b};

    // leftShiftStage0_uid23612_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x(MUX,23611)@56
    assign leftShiftStage0_uid23612_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23612_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_22_c_compstr634_vt_join_q or leftShiftStage0Idx1_uid23610_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23612_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23612_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_22_c_compstr634_vt_join_q;
            1'b1 : leftShiftStage0_uid23612_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23610_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23612_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23617_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x(MUX,23616)@56
    assign leftShiftStage1_uid23617_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23617_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_s or leftShiftStage0_uid23612_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23615_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23617_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23617_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q = leftShiftStage0_uid23612_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23617_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23615_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23617_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23622_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x(MUX,23621)@56
    assign leftShiftStage2_uid23622_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23622_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_s or leftShiftStage1_uid23617_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23620_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23622_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23622_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q = leftShiftStage1_uid23617_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23622_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23620_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23622_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_22_c_compstr635_vt_select_28(BITSELECT,9166)@56
    assign i_shl_i_i_i_i_i77_i_22_c_compstr635_vt_select_28_b = leftShiftStage2_uid23622_i_shl_i_i_i_i_i77_i_22_c_compstr0_shift_x_q[28:13];

    // redist468_i_shl_i_i_i_i_i77_i_22_c_compstr635_vt_select_28_b_1(DELAY,28696)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist468_i_shl_i_i_i_i_i77_i_22_c_compstr635_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_22_c_compstr635_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_22_c_compstr635_vt_join(BITJOIN,9165)@57
    assign i_shl_i_i_i_i_i77_i_22_c_compstr635_vt_join_q = {redist468_i_shl_i_i_i_i_i77_i_22_c_compstr635_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma(CHAINMULTADD,28140)@51 + 5
    // out q@57
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ah[0] <= redist815_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_45_tpl_43_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ah[1] <= redist814_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_44_tpl_43_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ch[0] <= redist561_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_45_tpl_43_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ch[1] <= redist560_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_44_tpl_43_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636(ADD,8436)@57
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compstr631_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compstr633_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compstr632_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_22_c_compstr635_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_22_c_compstr635_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_o[33:0];

    // rightShiftStage0_uid16302_dupName_87_i_unnamed_c_compstr0_shift_x(MUX,16301)@57
    assign rightShiftStage0_uid16302_dupName_87_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16302_dupName_87_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_q or rightShiftStage0Idx1_uid16300_dupName_87_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16302_dupName_87_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16302_dupName_87_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_q;
            1'b1 : rightShiftStage0_uid16302_dupName_87_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16300_dupName_87_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16302_dupName_87_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16307_dupName_87_i_unnamed_c_compstr0_shift_x(MUX,16306)@57
    assign rightShiftStage1_uid16307_dupName_87_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16307_dupName_87_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16302_dupName_87_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16305_dupName_87_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16307_dupName_87_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16307_dupName_87_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16302_dupName_87_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16307_dupName_87_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16305_dupName_87_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16307_dupName_87_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16312_dupName_87_i_unnamed_c_compstr0_shift_x(MUX,16311)@57
    assign rightShiftStage2_uid16312_dupName_87_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16312_dupName_87_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16307_dupName_87_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16310_dupName_87_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16312_dupName_87_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16312_dupName_87_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16307_dupName_87_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16312_dupName_87_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16310_dupName_87_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16312_dupName_87_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr637_vt_select_20(BITSELECT,12302)@57
    assign i_unnamed_c_compstr637_vt_select_20_b = rightShiftStage2_uid16312_dupName_87_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr637_vt_join(BITJOIN,12301)@57
    assign i_unnamed_c_compstr637_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr637_vt_select_20_b};

    // i_conv_i_i_i_i97_i_22_c_compstr638_sel_x(BITSELECT,3498)@57
    assign i_conv_i_i_i_i97_i_22_c_compstr638_sel_x_b = i_unnamed_c_compstr637_vt_join_q[15:0];

    // redist1238_i_conv_i_i_i_i97_i_22_c_compstr638_sel_x_b_1(DELAY,29466)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1238_i_conv_i_i_i_i97_i_22_c_compstr638_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_22_c_compstr638_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16321_dupName_88_i_unnamed_c_compstr0_shift_x(BITSELECT,16320)@57
    assign rightShiftStage1Idx1Rng8_uid16321_dupName_88_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16320_dupName_88_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16323_dupName_88_i_unnamed_c_compstr0_shift_x(BITJOIN,16322)@57
    assign rightShiftStage1Idx1_uid16323_dupName_88_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16321_dupName_88_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16316_dupName_88_i_unnamed_c_compstr0_shift_x(BITSELECT,16315)@57
    assign rightShiftStage0Idx1Rng4_uid16316_dupName_88_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_q[33:4];

    // rightShiftStage0Idx1_uid16318_dupName_88_i_unnamed_c_compstr0_shift_x(BITJOIN,16317)@57
    assign rightShiftStage0Idx1_uid16318_dupName_88_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16316_dupName_88_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16320_dupName_88_i_unnamed_c_compstr0_shift_x(MUX,16319)@57
    assign rightShiftStage0_uid16320_dupName_88_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16320_dupName_88_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_q or rightShiftStage0Idx1_uid16318_dupName_88_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16320_dupName_88_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16320_dupName_88_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compstr636_q;
            1'b1 : rightShiftStage0_uid16320_dupName_88_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16318_dupName_88_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16320_dupName_88_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16325_dupName_88_i_unnamed_c_compstr0_shift_x(MUX,16324)@57
    assign rightShiftStage1_uid16325_dupName_88_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16325_dupName_88_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16320_dupName_88_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16323_dupName_88_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16325_dupName_88_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16325_dupName_88_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16320_dupName_88_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16325_dupName_88_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16323_dupName_88_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16325_dupName_88_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr639_vt_select_21(BITSELECT,12305)@57
    assign i_unnamed_c_compstr639_vt_select_21_b = rightShiftStage1_uid16325_dupName_88_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr639_vt_join(BITJOIN,12304)@57
    assign i_unnamed_c_compstr639_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr639_vt_select_21_b};

    // i_unnamed_c_compstr640_sel_x(BITSELECT,6262)@57
    assign i_unnamed_c_compstr640_sel_x_b = i_unnamed_c_compstr639_vt_join_q[15:0];

    // i_unnamed_c_compstr641_BitSelect_for_a(BITSELECT,27913)@57
    assign i_unnamed_c_compstr641_BitSelect_for_a_b = i_unnamed_c_compstr640_sel_x_b[0:0];

    // i_unnamed_c_compstr641_join(BITJOIN,27914)@57
    assign i_unnamed_c_compstr641_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr641_BitSelect_for_a_b};

    // i_unnamed_c_compstr641_vt_select_0(BITSELECT,12310)@57
    assign i_unnamed_c_compstr641_vt_select_0_b = i_unnamed_c_compstr641_join_q[0:0];

    // redist30_i_unnamed_c_compstr641_vt_select_0_b_1(DELAY,28258)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist30_i_unnamed_c_compstr641_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr641_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr641_vt_join(BITJOIN,12309)@58
    assign i_unnamed_c_compstr641_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist30_i_unnamed_c_compstr641_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_22_c_compstr642(ADD,6893)@58
    assign i_add_i_i_i_i_i126_i_22_c_compstr642_a = {1'b0, i_unnamed_c_compstr641_vt_join_q};
    assign i_add_i_i_i_i_i126_i_22_c_compstr642_b = {1'b0, redist1238_i_conv_i_i_i_i97_i_22_c_compstr638_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_22_c_compstr642_o = $unsigned(i_add_i_i_i_i_i126_i_22_c_compstr642_a) + $unsigned(i_add_i_i_i_i_i126_i_22_c_compstr642_b);
    assign i_add_i_i_i_i_i126_i_22_c_compstr642_q = i_add_i_i_i_i_i126_i_22_c_compstr642_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_22_c_compstr642_sel_x(BITSELECT,2087)@58
    assign bgTrunc_i_add_i_i_i_i_i126_i_22_c_compstr642_sel_x_b = i_add_i_i_i_i_i126_i_22_c_compstr642_q[15:0];

    // i_conv_i_i_i_i_i75_i277_23_c_compstr662_sel_x(BITSELECT,3628)@58
    assign i_conv_i_i_i_i_i75_i277_23_c_compstr662_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_22_c_compstr642_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_23_c_compstr662_vt_select_15(BITSELECT,7413)@58
    assign i_conv_i_i_i_i_i75_i277_23_c_compstr662_vt_select_15_b = i_conv_i_i_i_i_i75_i277_23_c_compstr662_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_23_c_compstr662_vt_join(BITJOIN,7412)@58
    assign i_conv_i_i_i_i_i75_i277_23_c_compstr662_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_23_c_compstr662_vt_select_15_b};

    // leftShiftStage0_uid23630_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x(MUX,23629)@58
    assign leftShiftStage0_uid23630_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23630_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_23_c_compstr662_vt_join_q or leftShiftStage0Idx1_uid23628_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23630_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23630_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_23_c_compstr662_vt_join_q;
            1'b1 : leftShiftStage0_uid23630_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23628_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23630_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23635_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x(MUX,23634)@58
    assign leftShiftStage1_uid23635_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23635_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_s or leftShiftStage0_uid23630_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23633_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23635_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23635_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q = leftShiftStage0_uid23630_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23635_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23633_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23635_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23640_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x(MUX,23639)@58
    assign leftShiftStage2_uid23640_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23640_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_s or leftShiftStage1_uid23635_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23638_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23640_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23640_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q = leftShiftStage1_uid23635_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23640_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23638_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23640_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_23_c_compstr663_vt_select_28(BITSELECT,9169)@58
    assign i_shl_i_i_i_i_i77_i_23_c_compstr663_vt_select_28_b = leftShiftStage2_uid23640_i_shl_i_i_i_i_i77_i_23_c_compstr0_shift_x_q[28:13];

    // redist467_i_shl_i_i_i_i_i77_i_23_c_compstr663_vt_select_28_b_1(DELAY,28695)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist467_i_shl_i_i_i_i_i77_i_23_c_compstr663_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_23_c_compstr663_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_23_c_compstr663_vt_join(BITJOIN,9168)@59
    assign i_shl_i_i_i_i_i77_i_23_c_compstr663_vt_join_q = {redist467_i_shl_i_i_i_i_i77_i_23_c_compstr663_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma(CHAINMULTADD,28141)@53 + 5
    // out q@59
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ah[0] <= redist817_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_47_tpl_45_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ah[1] <= redist816_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_46_tpl_45_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ch[0] <= redist563_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_47_tpl_45_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ch[1] <= redist562_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_46_tpl_45_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664(ADD,8437)@59
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compstr659_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compstr661_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compstr660_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_23_c_compstr663_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_23_c_compstr663_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_o[33:0];

    // rightShiftStage0_uid16364_dupName_91_i_unnamed_c_compstr0_shift_x(MUX,16363)@59
    assign rightShiftStage0_uid16364_dupName_91_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16364_dupName_91_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_q or rightShiftStage0Idx1_uid16362_dupName_91_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16364_dupName_91_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16364_dupName_91_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_q;
            1'b1 : rightShiftStage0_uid16364_dupName_91_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16362_dupName_91_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16364_dupName_91_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16369_dupName_91_i_unnamed_c_compstr0_shift_x(MUX,16368)@59
    assign rightShiftStage1_uid16369_dupName_91_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16369_dupName_91_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16364_dupName_91_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16367_dupName_91_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16369_dupName_91_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16369_dupName_91_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16364_dupName_91_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16369_dupName_91_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16367_dupName_91_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16369_dupName_91_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16374_dupName_91_i_unnamed_c_compstr0_shift_x(MUX,16373)@59
    assign rightShiftStage2_uid16374_dupName_91_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16374_dupName_91_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16369_dupName_91_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16372_dupName_91_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16374_dupName_91_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16374_dupName_91_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16369_dupName_91_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16374_dupName_91_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16372_dupName_91_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16374_dupName_91_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr665_vt_select_20(BITSELECT,12327)@59
    assign i_unnamed_c_compstr665_vt_select_20_b = rightShiftStage2_uid16374_dupName_91_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr665_vt_join(BITJOIN,12326)@59
    assign i_unnamed_c_compstr665_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr665_vt_select_20_b};

    // i_conv_i_i_i_i97_i_23_c_compstr666_sel_x(BITSELECT,3499)@59
    assign i_conv_i_i_i_i97_i_23_c_compstr666_sel_x_b = i_unnamed_c_compstr665_vt_join_q[15:0];

    // redist1237_i_conv_i_i_i_i97_i_23_c_compstr666_sel_x_b_1(DELAY,29465)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1237_i_conv_i_i_i_i97_i_23_c_compstr666_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_23_c_compstr666_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16383_dupName_92_i_unnamed_c_compstr0_shift_x(BITSELECT,16382)@59
    assign rightShiftStage1Idx1Rng8_uid16383_dupName_92_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16382_dupName_92_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16385_dupName_92_i_unnamed_c_compstr0_shift_x(BITJOIN,16384)@59
    assign rightShiftStage1Idx1_uid16385_dupName_92_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16383_dupName_92_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16378_dupName_92_i_unnamed_c_compstr0_shift_x(BITSELECT,16377)@59
    assign rightShiftStage0Idx1Rng4_uid16378_dupName_92_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_q[33:4];

    // rightShiftStage0Idx1_uid16380_dupName_92_i_unnamed_c_compstr0_shift_x(BITJOIN,16379)@59
    assign rightShiftStage0Idx1_uid16380_dupName_92_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16378_dupName_92_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16382_dupName_92_i_unnamed_c_compstr0_shift_x(MUX,16381)@59
    assign rightShiftStage0_uid16382_dupName_92_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16382_dupName_92_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_q or rightShiftStage0Idx1_uid16380_dupName_92_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16382_dupName_92_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16382_dupName_92_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compstr664_q;
            1'b1 : rightShiftStage0_uid16382_dupName_92_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16380_dupName_92_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16382_dupName_92_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16387_dupName_92_i_unnamed_c_compstr0_shift_x(MUX,16386)@59
    assign rightShiftStage1_uid16387_dupName_92_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16387_dupName_92_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16382_dupName_92_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16385_dupName_92_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16387_dupName_92_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16387_dupName_92_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16382_dupName_92_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16387_dupName_92_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16385_dupName_92_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16387_dupName_92_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr667_vt_select_21(BITSELECT,12330)@59
    assign i_unnamed_c_compstr667_vt_select_21_b = rightShiftStage1_uid16387_dupName_92_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr667_vt_join(BITJOIN,12329)@59
    assign i_unnamed_c_compstr667_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr667_vt_select_21_b};

    // i_unnamed_c_compstr668_sel_x(BITSELECT,6264)@59
    assign i_unnamed_c_compstr668_sel_x_b = i_unnamed_c_compstr667_vt_join_q[15:0];

    // i_unnamed_c_compstr669_BitSelect_for_a(BITSELECT,27917)@59
    assign i_unnamed_c_compstr669_BitSelect_for_a_b = i_unnamed_c_compstr668_sel_x_b[0:0];

    // i_unnamed_c_compstr669_join(BITJOIN,27918)@59
    assign i_unnamed_c_compstr669_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr669_BitSelect_for_a_b};

    // i_unnamed_c_compstr669_vt_select_0(BITSELECT,12335)@59
    assign i_unnamed_c_compstr669_vt_select_0_b = i_unnamed_c_compstr669_join_q[0:0];

    // redist28_i_unnamed_c_compstr669_vt_select_0_b_1(DELAY,28256)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist28_i_unnamed_c_compstr669_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr669_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr669_vt_join(BITJOIN,12334)@60
    assign i_unnamed_c_compstr669_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist28_i_unnamed_c_compstr669_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_23_c_compstr670(ADD,6894)@60
    assign i_add_i_i_i_i_i126_i_23_c_compstr670_a = {1'b0, i_unnamed_c_compstr669_vt_join_q};
    assign i_add_i_i_i_i_i126_i_23_c_compstr670_b = {1'b0, redist1237_i_conv_i_i_i_i97_i_23_c_compstr666_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_23_c_compstr670_o = $unsigned(i_add_i_i_i_i_i126_i_23_c_compstr670_a) + $unsigned(i_add_i_i_i_i_i126_i_23_c_compstr670_b);
    assign i_add_i_i_i_i_i126_i_23_c_compstr670_q = i_add_i_i_i_i_i126_i_23_c_compstr670_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_23_c_compstr670_sel_x(BITSELECT,2088)@60
    assign bgTrunc_i_add_i_i_i_i_i126_i_23_c_compstr670_sel_x_b = i_add_i_i_i_i_i126_i_23_c_compstr670_q[15:0];

    // i_conv_i_i_i_i_i75_i277_24_c_compstr690_sel_x(BITSELECT,3629)@60
    assign i_conv_i_i_i_i_i75_i277_24_c_compstr690_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_23_c_compstr670_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_24_c_compstr690_vt_select_15(BITSELECT,7417)@60
    assign i_conv_i_i_i_i_i75_i277_24_c_compstr690_vt_select_15_b = i_conv_i_i_i_i_i75_i277_24_c_compstr690_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_24_c_compstr690_vt_join(BITJOIN,7416)@60
    assign i_conv_i_i_i_i_i75_i277_24_c_compstr690_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_24_c_compstr690_vt_select_15_b};

    // leftShiftStage0_uid23648_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x(MUX,23647)@60
    assign leftShiftStage0_uid23648_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23648_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_24_c_compstr690_vt_join_q or leftShiftStage0Idx1_uid23646_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23648_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23648_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_24_c_compstr690_vt_join_q;
            1'b1 : leftShiftStage0_uid23648_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23646_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23648_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23653_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x(MUX,23652)@60
    assign leftShiftStage1_uid23653_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23653_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_s or leftShiftStage0_uid23648_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23651_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23653_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23653_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q = leftShiftStage0_uid23648_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23653_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23651_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23653_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23658_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x(MUX,23657)@60
    assign leftShiftStage2_uid23658_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23658_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_s or leftShiftStage1_uid23653_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23656_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23658_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23658_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q = leftShiftStage1_uid23653_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23658_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23656_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23658_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_24_c_compstr691_vt_select_28(BITSELECT,9172)@60
    assign i_shl_i_i_i_i_i77_i_24_c_compstr691_vt_select_28_b = leftShiftStage2_uid23658_i_shl_i_i_i_i_i77_i_24_c_compstr0_shift_x_q[28:13];

    // redist466_i_shl_i_i_i_i_i77_i_24_c_compstr691_vt_select_28_b_1(DELAY,28694)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist466_i_shl_i_i_i_i_i77_i_24_c_compstr691_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_24_c_compstr691_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_24_c_compstr691_vt_join(BITJOIN,9171)@61
    assign i_shl_i_i_i_i_i77_i_24_c_compstr691_vt_join_q = {redist466_i_shl_i_i_i_i_i77_i_24_c_compstr691_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma(CHAINMULTADD,28142)@55 + 5
    // out q@61
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ah[0] <= redist819_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_49_tpl_47_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ah[1] <= redist818_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_48_tpl_47_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ch[0] <= redist565_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_49_tpl_47_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ch[1] <= redist564_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_48_tpl_47_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692(ADD,8438)@61
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compstr687_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compstr689_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compstr688_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_24_c_compstr691_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_24_c_compstr691_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_o[33:0];

    // rightShiftStage0_uid16426_dupName_95_i_unnamed_c_compstr0_shift_x(MUX,16425)@61
    assign rightShiftStage0_uid16426_dupName_95_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16426_dupName_95_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_q or rightShiftStage0Idx1_uid16424_dupName_95_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16426_dupName_95_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16426_dupName_95_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_q;
            1'b1 : rightShiftStage0_uid16426_dupName_95_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16424_dupName_95_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16426_dupName_95_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16431_dupName_95_i_unnamed_c_compstr0_shift_x(MUX,16430)@61
    assign rightShiftStage1_uid16431_dupName_95_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16431_dupName_95_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16426_dupName_95_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16429_dupName_95_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16431_dupName_95_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16431_dupName_95_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16426_dupName_95_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16431_dupName_95_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16429_dupName_95_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16431_dupName_95_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16436_dupName_95_i_unnamed_c_compstr0_shift_x(MUX,16435)@61
    assign rightShiftStage2_uid16436_dupName_95_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16436_dupName_95_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16431_dupName_95_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16434_dupName_95_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16436_dupName_95_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16436_dupName_95_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16431_dupName_95_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16436_dupName_95_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16434_dupName_95_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16436_dupName_95_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr693_vt_select_20(BITSELECT,12354)@61
    assign i_unnamed_c_compstr693_vt_select_20_b = rightShiftStage2_uid16436_dupName_95_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr693_vt_join(BITJOIN,12353)@61
    assign i_unnamed_c_compstr693_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr693_vt_select_20_b};

    // i_conv_i_i_i_i97_i_24_c_compstr694_sel_x(BITSELECT,3500)@61
    assign i_conv_i_i_i_i97_i_24_c_compstr694_sel_x_b = i_unnamed_c_compstr693_vt_join_q[15:0];

    // redist1236_i_conv_i_i_i_i97_i_24_c_compstr694_sel_x_b_1(DELAY,29464)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1236_i_conv_i_i_i_i97_i_24_c_compstr694_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_24_c_compstr694_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16445_dupName_96_i_unnamed_c_compstr0_shift_x(BITSELECT,16444)@61
    assign rightShiftStage1Idx1Rng8_uid16445_dupName_96_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16444_dupName_96_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16447_dupName_96_i_unnamed_c_compstr0_shift_x(BITJOIN,16446)@61
    assign rightShiftStage1Idx1_uid16447_dupName_96_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16445_dupName_96_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16440_dupName_96_i_unnamed_c_compstr0_shift_x(BITSELECT,16439)@61
    assign rightShiftStage0Idx1Rng4_uid16440_dupName_96_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_q[33:4];

    // rightShiftStage0Idx1_uid16442_dupName_96_i_unnamed_c_compstr0_shift_x(BITJOIN,16441)@61
    assign rightShiftStage0Idx1_uid16442_dupName_96_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16440_dupName_96_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16444_dupName_96_i_unnamed_c_compstr0_shift_x(MUX,16443)@61
    assign rightShiftStage0_uid16444_dupName_96_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16444_dupName_96_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_q or rightShiftStage0Idx1_uid16442_dupName_96_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16444_dupName_96_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16444_dupName_96_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compstr692_q;
            1'b1 : rightShiftStage0_uid16444_dupName_96_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16442_dupName_96_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16444_dupName_96_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16449_dupName_96_i_unnamed_c_compstr0_shift_x(MUX,16448)@61
    assign rightShiftStage1_uid16449_dupName_96_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16449_dupName_96_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16444_dupName_96_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16447_dupName_96_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16449_dupName_96_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16449_dupName_96_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16444_dupName_96_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16449_dupName_96_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16447_dupName_96_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16449_dupName_96_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr695_vt_select_21(BITSELECT,12357)@61
    assign i_unnamed_c_compstr695_vt_select_21_b = rightShiftStage1_uid16449_dupName_96_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr695_vt_join(BITJOIN,12356)@61
    assign i_unnamed_c_compstr695_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr695_vt_select_21_b};

    // i_unnamed_c_compstr696_sel_x(BITSELECT,6267)@61
    assign i_unnamed_c_compstr696_sel_x_b = i_unnamed_c_compstr695_vt_join_q[15:0];

    // i_unnamed_c_compstr697_BitSelect_for_a(BITSELECT,27923)@61
    assign i_unnamed_c_compstr697_BitSelect_for_a_b = i_unnamed_c_compstr696_sel_x_b[0:0];

    // i_unnamed_c_compstr697_join(BITJOIN,27924)@61
    assign i_unnamed_c_compstr697_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr697_BitSelect_for_a_b};

    // i_unnamed_c_compstr697_vt_select_0(BITSELECT,12362)@61
    assign i_unnamed_c_compstr697_vt_select_0_b = i_unnamed_c_compstr697_join_q[0:0];

    // redist26_i_unnamed_c_compstr697_vt_select_0_b_1(DELAY,28254)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist26_i_unnamed_c_compstr697_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr697_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr697_vt_join(BITJOIN,12361)@62
    assign i_unnamed_c_compstr697_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist26_i_unnamed_c_compstr697_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_24_c_compstr698(ADD,6895)@62
    assign i_add_i_i_i_i_i126_i_24_c_compstr698_a = {1'b0, i_unnamed_c_compstr697_vt_join_q};
    assign i_add_i_i_i_i_i126_i_24_c_compstr698_b = {1'b0, redist1236_i_conv_i_i_i_i97_i_24_c_compstr694_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_24_c_compstr698_o = $unsigned(i_add_i_i_i_i_i126_i_24_c_compstr698_a) + $unsigned(i_add_i_i_i_i_i126_i_24_c_compstr698_b);
    assign i_add_i_i_i_i_i126_i_24_c_compstr698_q = i_add_i_i_i_i_i126_i_24_c_compstr698_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_24_c_compstr698_sel_x(BITSELECT,2089)@62
    assign bgTrunc_i_add_i_i_i_i_i126_i_24_c_compstr698_sel_x_b = i_add_i_i_i_i_i126_i_24_c_compstr698_q[15:0];

    // i_conv_i_i_i_i_i75_i277_25_c_compstr718_sel_x(BITSELECT,3630)@62
    assign i_conv_i_i_i_i_i75_i277_25_c_compstr718_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_24_c_compstr698_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_25_c_compstr718_vt_select_15(BITSELECT,7421)@62
    assign i_conv_i_i_i_i_i75_i277_25_c_compstr718_vt_select_15_b = i_conv_i_i_i_i_i75_i277_25_c_compstr718_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_25_c_compstr718_vt_join(BITJOIN,7420)@62
    assign i_conv_i_i_i_i_i75_i277_25_c_compstr718_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_25_c_compstr718_vt_select_15_b};

    // leftShiftStage0_uid23666_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x(MUX,23665)@62
    assign leftShiftStage0_uid23666_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23666_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_25_c_compstr718_vt_join_q or leftShiftStage0Idx1_uid23664_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23666_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23666_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_25_c_compstr718_vt_join_q;
            1'b1 : leftShiftStage0_uid23666_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23664_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23666_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23671_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x(MUX,23670)@62
    assign leftShiftStage1_uid23671_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23671_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_s or leftShiftStage0_uid23666_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23669_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23671_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23671_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q = leftShiftStage0_uid23666_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23671_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23669_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23671_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23676_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x(MUX,23675)@62
    assign leftShiftStage2_uid23676_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23676_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_s or leftShiftStage1_uid23671_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23674_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23676_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23676_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q = leftShiftStage1_uid23671_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23676_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23674_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23676_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_25_c_compstr719_vt_select_28(BITSELECT,9175)@62
    assign i_shl_i_i_i_i_i77_i_25_c_compstr719_vt_select_28_b = leftShiftStage2_uid23676_i_shl_i_i_i_i_i77_i_25_c_compstr0_shift_x_q[28:13];

    // redist465_i_shl_i_i_i_i_i77_i_25_c_compstr719_vt_select_28_b_1(DELAY,28693)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist465_i_shl_i_i_i_i_i77_i_25_c_compstr719_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_25_c_compstr719_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_25_c_compstr719_vt_join(BITJOIN,9174)@63
    assign i_shl_i_i_i_i_i77_i_25_c_compstr719_vt_join_q = {redist465_i_shl_i_i_i_i_i77_i_25_c_compstr719_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma(CHAINMULTADD,28143)@57 + 5
    // out q@63
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ah[0] <= redist821_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_51_tpl_49_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ah[1] <= redist820_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_50_tpl_49_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ch[0] <= redist567_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_51_tpl_49_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ch[1] <= redist566_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_50_tpl_49_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720(ADD,8439)@63
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compstr715_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compstr717_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compstr716_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_25_c_compstr719_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_25_c_compstr719_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_o[33:0];

    // rightShiftStage0_uid16488_dupName_99_i_unnamed_c_compstr0_shift_x(MUX,16487)@63
    assign rightShiftStage0_uid16488_dupName_99_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16488_dupName_99_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_q or rightShiftStage0Idx1_uid16486_dupName_99_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16488_dupName_99_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16488_dupName_99_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_q;
            1'b1 : rightShiftStage0_uid16488_dupName_99_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16486_dupName_99_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16488_dupName_99_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16493_dupName_99_i_unnamed_c_compstr0_shift_x(MUX,16492)@63
    assign rightShiftStage1_uid16493_dupName_99_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16493_dupName_99_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16488_dupName_99_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16491_dupName_99_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16493_dupName_99_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16493_dupName_99_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16488_dupName_99_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16493_dupName_99_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16491_dupName_99_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16493_dupName_99_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16498_dupName_99_i_unnamed_c_compstr0_shift_x(MUX,16497)@63
    assign rightShiftStage2_uid16498_dupName_99_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16498_dupName_99_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16493_dupName_99_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16496_dupName_99_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16498_dupName_99_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16498_dupName_99_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16493_dupName_99_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16498_dupName_99_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16496_dupName_99_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16498_dupName_99_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr721_vt_select_20(BITSELECT,12379)@63
    assign i_unnamed_c_compstr721_vt_select_20_b = rightShiftStage2_uid16498_dupName_99_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr721_vt_join(BITJOIN,12378)@63
    assign i_unnamed_c_compstr721_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr721_vt_select_20_b};

    // i_conv_i_i_i_i97_i_25_c_compstr722_sel_x(BITSELECT,3501)@63
    assign i_conv_i_i_i_i97_i_25_c_compstr722_sel_x_b = i_unnamed_c_compstr721_vt_join_q[15:0];

    // redist1235_i_conv_i_i_i_i97_i_25_c_compstr722_sel_x_b_1(DELAY,29463)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1235_i_conv_i_i_i_i97_i_25_c_compstr722_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_25_c_compstr722_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16507_dupName_100_i_unnamed_c_compstr0_shift_x(BITSELECT,16506)@63
    assign rightShiftStage1Idx1Rng8_uid16507_dupName_100_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16506_dupName_100_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16509_dupName_100_i_unnamed_c_compstr0_shift_x(BITJOIN,16508)@63
    assign rightShiftStage1Idx1_uid16509_dupName_100_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16507_dupName_100_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16502_dupName_100_i_unnamed_c_compstr0_shift_x(BITSELECT,16501)@63
    assign rightShiftStage0Idx1Rng4_uid16502_dupName_100_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_q[33:4];

    // rightShiftStage0Idx1_uid16504_dupName_100_i_unnamed_c_compstr0_shift_x(BITJOIN,16503)@63
    assign rightShiftStage0Idx1_uid16504_dupName_100_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16502_dupName_100_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16506_dupName_100_i_unnamed_c_compstr0_shift_x(MUX,16505)@63
    assign rightShiftStage0_uid16506_dupName_100_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16506_dupName_100_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_q or rightShiftStage0Idx1_uid16504_dupName_100_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16506_dupName_100_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16506_dupName_100_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compstr720_q;
            1'b1 : rightShiftStage0_uid16506_dupName_100_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16504_dupName_100_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16506_dupName_100_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16511_dupName_100_i_unnamed_c_compstr0_shift_x(MUX,16510)@63
    assign rightShiftStage1_uid16511_dupName_100_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16511_dupName_100_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16506_dupName_100_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16509_dupName_100_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16511_dupName_100_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16511_dupName_100_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16506_dupName_100_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16511_dupName_100_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16509_dupName_100_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16511_dupName_100_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr723_vt_select_21(BITSELECT,12382)@63
    assign i_unnamed_c_compstr723_vt_select_21_b = rightShiftStage1_uid16511_dupName_100_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr723_vt_join(BITJOIN,12381)@63
    assign i_unnamed_c_compstr723_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr723_vt_select_21_b};

    // i_unnamed_c_compstr724_sel_x(BITSELECT,6269)@63
    assign i_unnamed_c_compstr724_sel_x_b = i_unnamed_c_compstr723_vt_join_q[15:0];

    // i_unnamed_c_compstr725_BitSelect_for_a(BITSELECT,27927)@63
    assign i_unnamed_c_compstr725_BitSelect_for_a_b = i_unnamed_c_compstr724_sel_x_b[0:0];

    // i_unnamed_c_compstr725_join(BITJOIN,27928)@63
    assign i_unnamed_c_compstr725_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr725_BitSelect_for_a_b};

    // i_unnamed_c_compstr725_vt_select_0(BITSELECT,12387)@63
    assign i_unnamed_c_compstr725_vt_select_0_b = i_unnamed_c_compstr725_join_q[0:0];

    // redist23_i_unnamed_c_compstr725_vt_select_0_b_1(DELAY,28251)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist23_i_unnamed_c_compstr725_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr725_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr725_vt_join(BITJOIN,12386)@64
    assign i_unnamed_c_compstr725_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist23_i_unnamed_c_compstr725_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_25_c_compstr726(ADD,6896)@64
    assign i_add_i_i_i_i_i126_i_25_c_compstr726_a = {1'b0, i_unnamed_c_compstr725_vt_join_q};
    assign i_add_i_i_i_i_i126_i_25_c_compstr726_b = {1'b0, redist1235_i_conv_i_i_i_i97_i_25_c_compstr722_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_25_c_compstr726_o = $unsigned(i_add_i_i_i_i_i126_i_25_c_compstr726_a) + $unsigned(i_add_i_i_i_i_i126_i_25_c_compstr726_b);
    assign i_add_i_i_i_i_i126_i_25_c_compstr726_q = i_add_i_i_i_i_i126_i_25_c_compstr726_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_25_c_compstr726_sel_x(BITSELECT,2090)@64
    assign bgTrunc_i_add_i_i_i_i_i126_i_25_c_compstr726_sel_x_b = i_add_i_i_i_i_i126_i_25_c_compstr726_q[15:0];

    // i_conv_i_i_i_i_i75_i277_26_c_compstr746_sel_x(BITSELECT,3631)@64
    assign i_conv_i_i_i_i_i75_i277_26_c_compstr746_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_25_c_compstr726_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_26_c_compstr746_vt_select_15(BITSELECT,7425)@64
    assign i_conv_i_i_i_i_i75_i277_26_c_compstr746_vt_select_15_b = i_conv_i_i_i_i_i75_i277_26_c_compstr746_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_26_c_compstr746_vt_join(BITJOIN,7424)@64
    assign i_conv_i_i_i_i_i75_i277_26_c_compstr746_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_26_c_compstr746_vt_select_15_b};

    // leftShiftStage0_uid23684_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x(MUX,23683)@64
    assign leftShiftStage0_uid23684_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23684_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_26_c_compstr746_vt_join_q or leftShiftStage0Idx1_uid23682_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23684_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23684_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_26_c_compstr746_vt_join_q;
            1'b1 : leftShiftStage0_uid23684_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23682_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23684_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23689_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x(MUX,23688)@64
    assign leftShiftStage1_uid23689_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23689_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_s or leftShiftStage0_uid23684_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23687_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23689_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23689_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q = leftShiftStage0_uid23684_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23689_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23687_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23689_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23694_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x(MUX,23693)@64
    assign leftShiftStage2_uid23694_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23694_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_s or leftShiftStage1_uid23689_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23692_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23694_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23694_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q = leftShiftStage1_uid23689_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23694_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23692_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23694_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_26_c_compstr747_vt_select_28(BITSELECT,9178)@64
    assign i_shl_i_i_i_i_i77_i_26_c_compstr747_vt_select_28_b = leftShiftStage2_uid23694_i_shl_i_i_i_i_i77_i_26_c_compstr0_shift_x_q[28:13];

    // redist464_i_shl_i_i_i_i_i77_i_26_c_compstr747_vt_select_28_b_1(DELAY,28692)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist464_i_shl_i_i_i_i_i77_i_26_c_compstr747_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_26_c_compstr747_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_26_c_compstr747_vt_join(BITJOIN,9177)@65
    assign i_shl_i_i_i_i_i77_i_26_c_compstr747_vt_join_q = {redist464_i_shl_i_i_i_i_i77_i_26_c_compstr747_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma(CHAINMULTADD,28144)@59 + 5
    // out q@65
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ah[0] <= redist823_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_53_tpl_51_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ah[1] <= redist822_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_52_tpl_51_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ch[0] <= redist569_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_53_tpl_51_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ch[1] <= redist568_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_52_tpl_51_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748(ADD,8440)@65
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compstr743_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compstr745_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compstr744_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_26_c_compstr747_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_26_c_compstr747_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_o[33:0];

    // rightShiftStage0_uid16550_dupName_103_i_unnamed_c_compstr0_shift_x(MUX,16549)@65
    assign rightShiftStage0_uid16550_dupName_103_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16550_dupName_103_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_q or rightShiftStage0Idx1_uid16548_dupName_103_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16550_dupName_103_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16550_dupName_103_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_q;
            1'b1 : rightShiftStage0_uid16550_dupName_103_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16548_dupName_103_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16550_dupName_103_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16555_dupName_103_i_unnamed_c_compstr0_shift_x(MUX,16554)@65
    assign rightShiftStage1_uid16555_dupName_103_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16555_dupName_103_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16550_dupName_103_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16553_dupName_103_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16555_dupName_103_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16555_dupName_103_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16550_dupName_103_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16555_dupName_103_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16553_dupName_103_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16555_dupName_103_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16560_dupName_103_i_unnamed_c_compstr0_shift_x(MUX,16559)@65
    assign rightShiftStage2_uid16560_dupName_103_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16560_dupName_103_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16555_dupName_103_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16558_dupName_103_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16560_dupName_103_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16560_dupName_103_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16555_dupName_103_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16560_dupName_103_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16558_dupName_103_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16560_dupName_103_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr749_vt_select_20(BITSELECT,12401)@65
    assign i_unnamed_c_compstr749_vt_select_20_b = rightShiftStage2_uid16560_dupName_103_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr749_vt_join(BITJOIN,12400)@65
    assign i_unnamed_c_compstr749_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr749_vt_select_20_b};

    // i_conv_i_i_i_i97_i_26_c_compstr750_sel_x(BITSELECT,3502)@65
    assign i_conv_i_i_i_i97_i_26_c_compstr750_sel_x_b = i_unnamed_c_compstr749_vt_join_q[15:0];

    // redist1234_i_conv_i_i_i_i97_i_26_c_compstr750_sel_x_b_1(DELAY,29462)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1234_i_conv_i_i_i_i97_i_26_c_compstr750_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_26_c_compstr750_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16569_dupName_104_i_unnamed_c_compstr0_shift_x(BITSELECT,16568)@65
    assign rightShiftStage1Idx1Rng8_uid16569_dupName_104_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16568_dupName_104_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16571_dupName_104_i_unnamed_c_compstr0_shift_x(BITJOIN,16570)@65
    assign rightShiftStage1Idx1_uid16571_dupName_104_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16569_dupName_104_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16564_dupName_104_i_unnamed_c_compstr0_shift_x(BITSELECT,16563)@65
    assign rightShiftStage0Idx1Rng4_uid16564_dupName_104_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_q[33:4];

    // rightShiftStage0Idx1_uid16566_dupName_104_i_unnamed_c_compstr0_shift_x(BITJOIN,16565)@65
    assign rightShiftStage0Idx1_uid16566_dupName_104_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16564_dupName_104_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16568_dupName_104_i_unnamed_c_compstr0_shift_x(MUX,16567)@65
    assign rightShiftStage0_uid16568_dupName_104_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16568_dupName_104_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_q or rightShiftStage0Idx1_uid16566_dupName_104_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16568_dupName_104_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16568_dupName_104_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compstr748_q;
            1'b1 : rightShiftStage0_uid16568_dupName_104_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16566_dupName_104_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16568_dupName_104_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16573_dupName_104_i_unnamed_c_compstr0_shift_x(MUX,16572)@65
    assign rightShiftStage1_uid16573_dupName_104_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16573_dupName_104_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16568_dupName_104_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16571_dupName_104_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16573_dupName_104_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16573_dupName_104_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16568_dupName_104_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16573_dupName_104_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16571_dupName_104_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16573_dupName_104_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr751_vt_select_21(BITSELECT,12404)@65
    assign i_unnamed_c_compstr751_vt_select_21_b = rightShiftStage1_uid16573_dupName_104_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr751_vt_join(BITJOIN,12403)@65
    assign i_unnamed_c_compstr751_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr751_vt_select_21_b};

    // i_unnamed_c_compstr752_sel_x(BITSELECT,6271)@65
    assign i_unnamed_c_compstr752_sel_x_b = i_unnamed_c_compstr751_vt_join_q[15:0];

    // i_unnamed_c_compstr753_BitSelect_for_a(BITSELECT,27931)@65
    assign i_unnamed_c_compstr753_BitSelect_for_a_b = i_unnamed_c_compstr752_sel_x_b[0:0];

    // i_unnamed_c_compstr753_join(BITJOIN,27932)@65
    assign i_unnamed_c_compstr753_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr753_BitSelect_for_a_b};

    // i_unnamed_c_compstr753_vt_select_0(BITSELECT,12409)@65
    assign i_unnamed_c_compstr753_vt_select_0_b = i_unnamed_c_compstr753_join_q[0:0];

    // redist21_i_unnamed_c_compstr753_vt_select_0_b_1(DELAY,28249)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist21_i_unnamed_c_compstr753_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr753_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr753_vt_join(BITJOIN,12408)@66
    assign i_unnamed_c_compstr753_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist21_i_unnamed_c_compstr753_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_26_c_compstr754(ADD,6897)@66
    assign i_add_i_i_i_i_i126_i_26_c_compstr754_a = {1'b0, i_unnamed_c_compstr753_vt_join_q};
    assign i_add_i_i_i_i_i126_i_26_c_compstr754_b = {1'b0, redist1234_i_conv_i_i_i_i97_i_26_c_compstr750_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_26_c_compstr754_o = $unsigned(i_add_i_i_i_i_i126_i_26_c_compstr754_a) + $unsigned(i_add_i_i_i_i_i126_i_26_c_compstr754_b);
    assign i_add_i_i_i_i_i126_i_26_c_compstr754_q = i_add_i_i_i_i_i126_i_26_c_compstr754_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_26_c_compstr754_sel_x(BITSELECT,2091)@66
    assign bgTrunc_i_add_i_i_i_i_i126_i_26_c_compstr754_sel_x_b = i_add_i_i_i_i_i126_i_26_c_compstr754_q[15:0];

    // i_conv_i_i_i_i_i75_i277_27_c_compstr774_sel_x(BITSELECT,3632)@66
    assign i_conv_i_i_i_i_i75_i277_27_c_compstr774_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_26_c_compstr754_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_27_c_compstr774_vt_select_15(BITSELECT,7429)@66
    assign i_conv_i_i_i_i_i75_i277_27_c_compstr774_vt_select_15_b = i_conv_i_i_i_i_i75_i277_27_c_compstr774_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_27_c_compstr774_vt_join(BITJOIN,7428)@66
    assign i_conv_i_i_i_i_i75_i277_27_c_compstr774_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_27_c_compstr774_vt_select_15_b};

    // leftShiftStage0_uid23702_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x(MUX,23701)@66
    assign leftShiftStage0_uid23702_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23702_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_27_c_compstr774_vt_join_q or leftShiftStage0Idx1_uid23700_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23702_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23702_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_27_c_compstr774_vt_join_q;
            1'b1 : leftShiftStage0_uid23702_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23700_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23702_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23707_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x(MUX,23706)@66
    assign leftShiftStage1_uid23707_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23707_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_s or leftShiftStage0_uid23702_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23705_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23707_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23707_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q = leftShiftStage0_uid23702_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23707_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23705_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23707_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23712_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x(MUX,23711)@66
    assign leftShiftStage2_uid23712_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23712_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_s or leftShiftStage1_uid23707_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23710_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23712_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23712_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q = leftShiftStage1_uid23707_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23712_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23710_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23712_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_27_c_compstr775_vt_select_28(BITSELECT,9181)@66
    assign i_shl_i_i_i_i_i77_i_27_c_compstr775_vt_select_28_b = leftShiftStage2_uid23712_i_shl_i_i_i_i_i77_i_27_c_compstr0_shift_x_q[28:13];

    // redist463_i_shl_i_i_i_i_i77_i_27_c_compstr775_vt_select_28_b_1(DELAY,28691)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist463_i_shl_i_i_i_i_i77_i_27_c_compstr775_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_27_c_compstr775_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_27_c_compstr775_vt_join(BITJOIN,9180)@67
    assign i_shl_i_i_i_i_i77_i_27_c_compstr775_vt_join_q = {redist463_i_shl_i_i_i_i_i77_i_27_c_compstr775_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma(CHAINMULTADD,28145)@61 + 5
    // out q@67
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ah[0] <= redist825_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_55_tpl_53_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ah[1] <= redist824_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_54_tpl_53_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ch[0] <= redist571_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_55_tpl_53_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ch[1] <= redist570_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_54_tpl_53_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776(ADD,8441)@67
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compstr771_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compstr773_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compstr772_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_27_c_compstr775_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_27_c_compstr775_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_o[33:0];

    // rightShiftStage0_uid16612_dupName_107_i_unnamed_c_compstr0_shift_x(MUX,16611)@67
    assign rightShiftStage0_uid16612_dupName_107_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16612_dupName_107_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_q or rightShiftStage0Idx1_uid16610_dupName_107_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16612_dupName_107_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16612_dupName_107_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_q;
            1'b1 : rightShiftStage0_uid16612_dupName_107_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16610_dupName_107_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16612_dupName_107_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16617_dupName_107_i_unnamed_c_compstr0_shift_x(MUX,16616)@67
    assign rightShiftStage1_uid16617_dupName_107_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16617_dupName_107_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16612_dupName_107_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16615_dupName_107_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16617_dupName_107_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16617_dupName_107_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16612_dupName_107_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16617_dupName_107_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16615_dupName_107_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16617_dupName_107_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16622_dupName_107_i_unnamed_c_compstr0_shift_x(MUX,16621)@67
    assign rightShiftStage2_uid16622_dupName_107_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16622_dupName_107_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16617_dupName_107_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16620_dupName_107_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16622_dupName_107_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16622_dupName_107_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16617_dupName_107_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16622_dupName_107_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16620_dupName_107_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16622_dupName_107_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr777_vt_select_20(BITSELECT,12423)@67
    assign i_unnamed_c_compstr777_vt_select_20_b = rightShiftStage2_uid16622_dupName_107_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr777_vt_join(BITJOIN,12422)@67
    assign i_unnamed_c_compstr777_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr777_vt_select_20_b};

    // i_conv_i_i_i_i97_i_27_c_compstr778_sel_x(BITSELECT,3503)@67
    assign i_conv_i_i_i_i97_i_27_c_compstr778_sel_x_b = i_unnamed_c_compstr777_vt_join_q[15:0];

    // redist1233_i_conv_i_i_i_i97_i_27_c_compstr778_sel_x_b_1(DELAY,29461)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1233_i_conv_i_i_i_i97_i_27_c_compstr778_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_27_c_compstr778_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16631_dupName_108_i_unnamed_c_compstr0_shift_x(BITSELECT,16630)@67
    assign rightShiftStage1Idx1Rng8_uid16631_dupName_108_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16630_dupName_108_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16633_dupName_108_i_unnamed_c_compstr0_shift_x(BITJOIN,16632)@67
    assign rightShiftStage1Idx1_uid16633_dupName_108_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16631_dupName_108_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16626_dupName_108_i_unnamed_c_compstr0_shift_x(BITSELECT,16625)@67
    assign rightShiftStage0Idx1Rng4_uid16626_dupName_108_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_q[33:4];

    // rightShiftStage0Idx1_uid16628_dupName_108_i_unnamed_c_compstr0_shift_x(BITJOIN,16627)@67
    assign rightShiftStage0Idx1_uid16628_dupName_108_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16626_dupName_108_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16630_dupName_108_i_unnamed_c_compstr0_shift_x(MUX,16629)@67
    assign rightShiftStage0_uid16630_dupName_108_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16630_dupName_108_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_q or rightShiftStage0Idx1_uid16628_dupName_108_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16630_dupName_108_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16630_dupName_108_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compstr776_q;
            1'b1 : rightShiftStage0_uid16630_dupName_108_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16628_dupName_108_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16630_dupName_108_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16635_dupName_108_i_unnamed_c_compstr0_shift_x(MUX,16634)@67
    assign rightShiftStage1_uid16635_dupName_108_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16635_dupName_108_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16630_dupName_108_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16633_dupName_108_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16635_dupName_108_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16635_dupName_108_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16630_dupName_108_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16635_dupName_108_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16633_dupName_108_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16635_dupName_108_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr779_vt_select_21(BITSELECT,12426)@67
    assign i_unnamed_c_compstr779_vt_select_21_b = rightShiftStage1_uid16635_dupName_108_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr779_vt_join(BITJOIN,12425)@67
    assign i_unnamed_c_compstr779_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr779_vt_select_21_b};

    // i_unnamed_c_compstr780_sel_x(BITSELECT,6273)@67
    assign i_unnamed_c_compstr780_sel_x_b = i_unnamed_c_compstr779_vt_join_q[15:0];

    // i_unnamed_c_compstr781_BitSelect_for_a(BITSELECT,27935)@67
    assign i_unnamed_c_compstr781_BitSelect_for_a_b = i_unnamed_c_compstr780_sel_x_b[0:0];

    // i_unnamed_c_compstr781_join(BITJOIN,27936)@67
    assign i_unnamed_c_compstr781_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr781_BitSelect_for_a_b};

    // i_unnamed_c_compstr781_vt_select_0(BITSELECT,12434)@67
    assign i_unnamed_c_compstr781_vt_select_0_b = i_unnamed_c_compstr781_join_q[0:0];

    // redist19_i_unnamed_c_compstr781_vt_select_0_b_1(DELAY,28247)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist19_i_unnamed_c_compstr781_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr781_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr781_vt_join(BITJOIN,12433)@68
    assign i_unnamed_c_compstr781_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist19_i_unnamed_c_compstr781_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_27_c_compstr782(ADD,6898)@68
    assign i_add_i_i_i_i_i126_i_27_c_compstr782_a = {1'b0, i_unnamed_c_compstr781_vt_join_q};
    assign i_add_i_i_i_i_i126_i_27_c_compstr782_b = {1'b0, redist1233_i_conv_i_i_i_i97_i_27_c_compstr778_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_27_c_compstr782_o = $unsigned(i_add_i_i_i_i_i126_i_27_c_compstr782_a) + $unsigned(i_add_i_i_i_i_i126_i_27_c_compstr782_b);
    assign i_add_i_i_i_i_i126_i_27_c_compstr782_q = i_add_i_i_i_i_i126_i_27_c_compstr782_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_27_c_compstr782_sel_x(BITSELECT,2092)@68
    assign bgTrunc_i_add_i_i_i_i_i126_i_27_c_compstr782_sel_x_b = i_add_i_i_i_i_i126_i_27_c_compstr782_q[15:0];

    // i_conv_i_i_i_i_i75_i277_28_c_compstr802_sel_x(BITSELECT,3633)@68
    assign i_conv_i_i_i_i_i75_i277_28_c_compstr802_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_27_c_compstr782_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_28_c_compstr802_vt_select_15(BITSELECT,7433)@68
    assign i_conv_i_i_i_i_i75_i277_28_c_compstr802_vt_select_15_b = i_conv_i_i_i_i_i75_i277_28_c_compstr802_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_28_c_compstr802_vt_join(BITJOIN,7432)@68
    assign i_conv_i_i_i_i_i75_i277_28_c_compstr802_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_28_c_compstr802_vt_select_15_b};

    // leftShiftStage0_uid23720_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x(MUX,23719)@68
    assign leftShiftStage0_uid23720_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23720_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_28_c_compstr802_vt_join_q or leftShiftStage0Idx1_uid23718_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23720_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23720_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_28_c_compstr802_vt_join_q;
            1'b1 : leftShiftStage0_uid23720_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23718_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23720_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23725_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x(MUX,23724)@68
    assign leftShiftStage1_uid23725_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23725_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_s or leftShiftStage0_uid23720_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23723_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23725_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23725_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q = leftShiftStage0_uid23720_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23725_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23723_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23725_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23730_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x(MUX,23729)@68
    assign leftShiftStage2_uid23730_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23730_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_s or leftShiftStage1_uid23725_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23728_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23730_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23730_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q = leftShiftStage1_uid23725_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23730_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23728_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23730_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_28_c_compstr803_vt_select_28(BITSELECT,9184)@68
    assign i_shl_i_i_i_i_i77_i_28_c_compstr803_vt_select_28_b = leftShiftStage2_uid23730_i_shl_i_i_i_i_i77_i_28_c_compstr0_shift_x_q[28:13];

    // redist462_i_shl_i_i_i_i_i77_i_28_c_compstr803_vt_select_28_b_1(DELAY,28690)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist462_i_shl_i_i_i_i_i77_i_28_c_compstr803_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_28_c_compstr803_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_28_c_compstr803_vt_join(BITJOIN,9183)@69
    assign i_shl_i_i_i_i_i77_i_28_c_compstr803_vt_join_q = {redist462_i_shl_i_i_i_i_i77_i_28_c_compstr803_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma(CHAINMULTADD,28146)@63 + 5
    // out q@69
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ah[0] <= redist827_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_57_tpl_55_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ah[1] <= redist826_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_56_tpl_55_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ch[0] <= redist573_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_57_tpl_55_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ch[1] <= redist572_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_56_tpl_55_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804(ADD,8442)@69
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compstr799_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compstr801_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compstr800_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_28_c_compstr803_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_28_c_compstr803_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_o[33:0];

    // rightShiftStage0_uid16674_dupName_111_i_unnamed_c_compstr0_shift_x(MUX,16673)@69
    assign rightShiftStage0_uid16674_dupName_111_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16674_dupName_111_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_q or rightShiftStage0Idx1_uid16672_dupName_111_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16674_dupName_111_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16674_dupName_111_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_q;
            1'b1 : rightShiftStage0_uid16674_dupName_111_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16672_dupName_111_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16674_dupName_111_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16679_dupName_111_i_unnamed_c_compstr0_shift_x(MUX,16678)@69
    assign rightShiftStage1_uid16679_dupName_111_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16679_dupName_111_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16674_dupName_111_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16677_dupName_111_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16679_dupName_111_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16679_dupName_111_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16674_dupName_111_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16679_dupName_111_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16677_dupName_111_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16679_dupName_111_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16684_dupName_111_i_unnamed_c_compstr0_shift_x(MUX,16683)@69
    assign rightShiftStage2_uid16684_dupName_111_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16684_dupName_111_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16679_dupName_111_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16682_dupName_111_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16684_dupName_111_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16684_dupName_111_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16679_dupName_111_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16684_dupName_111_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16682_dupName_111_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16684_dupName_111_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr805_vt_select_20(BITSELECT,12451)@69
    assign i_unnamed_c_compstr805_vt_select_20_b = rightShiftStage2_uid16684_dupName_111_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr805_vt_join(BITJOIN,12450)@69
    assign i_unnamed_c_compstr805_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr805_vt_select_20_b};

    // i_conv_i_i_i_i97_i_28_c_compstr806_sel_x(BITSELECT,3504)@69
    assign i_conv_i_i_i_i97_i_28_c_compstr806_sel_x_b = i_unnamed_c_compstr805_vt_join_q[15:0];

    // redist1232_i_conv_i_i_i_i97_i_28_c_compstr806_sel_x_b_1(DELAY,29460)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1232_i_conv_i_i_i_i97_i_28_c_compstr806_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_28_c_compstr806_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16693_dupName_112_i_unnamed_c_compstr0_shift_x(BITSELECT,16692)@69
    assign rightShiftStage1Idx1Rng8_uid16693_dupName_112_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16692_dupName_112_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16695_dupName_112_i_unnamed_c_compstr0_shift_x(BITJOIN,16694)@69
    assign rightShiftStage1Idx1_uid16695_dupName_112_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16693_dupName_112_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16688_dupName_112_i_unnamed_c_compstr0_shift_x(BITSELECT,16687)@69
    assign rightShiftStage0Idx1Rng4_uid16688_dupName_112_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_q[33:4];

    // rightShiftStage0Idx1_uid16690_dupName_112_i_unnamed_c_compstr0_shift_x(BITJOIN,16689)@69
    assign rightShiftStage0Idx1_uid16690_dupName_112_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16688_dupName_112_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16692_dupName_112_i_unnamed_c_compstr0_shift_x(MUX,16691)@69
    assign rightShiftStage0_uid16692_dupName_112_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16692_dupName_112_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_q or rightShiftStage0Idx1_uid16690_dupName_112_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16692_dupName_112_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16692_dupName_112_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compstr804_q;
            1'b1 : rightShiftStage0_uid16692_dupName_112_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16690_dupName_112_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16692_dupName_112_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16697_dupName_112_i_unnamed_c_compstr0_shift_x(MUX,16696)@69
    assign rightShiftStage1_uid16697_dupName_112_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16697_dupName_112_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16692_dupName_112_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16695_dupName_112_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16697_dupName_112_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16697_dupName_112_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16692_dupName_112_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16697_dupName_112_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16695_dupName_112_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16697_dupName_112_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr807_vt_select_21(BITSELECT,12454)@69
    assign i_unnamed_c_compstr807_vt_select_21_b = rightShiftStage1_uid16697_dupName_112_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr807_vt_join(BITJOIN,12453)@69
    assign i_unnamed_c_compstr807_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr807_vt_select_21_b};

    // i_unnamed_c_compstr808_sel_x(BITSELECT,6276)@69
    assign i_unnamed_c_compstr808_sel_x_b = i_unnamed_c_compstr807_vt_join_q[15:0];

    // i_unnamed_c_compstr809_BitSelect_for_a(BITSELECT,27939)@69
    assign i_unnamed_c_compstr809_BitSelect_for_a_b = i_unnamed_c_compstr808_sel_x_b[0:0];

    // i_unnamed_c_compstr809_join(BITJOIN,27940)@69
    assign i_unnamed_c_compstr809_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr809_BitSelect_for_a_b};

    // i_unnamed_c_compstr809_vt_select_0(BITSELECT,12459)@69
    assign i_unnamed_c_compstr809_vt_select_0_b = i_unnamed_c_compstr809_join_q[0:0];

    // redist17_i_unnamed_c_compstr809_vt_select_0_b_1(DELAY,28245)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist17_i_unnamed_c_compstr809_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr809_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr809_vt_join(BITJOIN,12458)@70
    assign i_unnamed_c_compstr809_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist17_i_unnamed_c_compstr809_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_28_c_compstr810(ADD,6899)@70
    assign i_add_i_i_i_i_i126_i_28_c_compstr810_a = {1'b0, i_unnamed_c_compstr809_vt_join_q};
    assign i_add_i_i_i_i_i126_i_28_c_compstr810_b = {1'b0, redist1232_i_conv_i_i_i_i97_i_28_c_compstr806_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_28_c_compstr810_o = $unsigned(i_add_i_i_i_i_i126_i_28_c_compstr810_a) + $unsigned(i_add_i_i_i_i_i126_i_28_c_compstr810_b);
    assign i_add_i_i_i_i_i126_i_28_c_compstr810_q = i_add_i_i_i_i_i126_i_28_c_compstr810_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_28_c_compstr810_sel_x(BITSELECT,2093)@70
    assign bgTrunc_i_add_i_i_i_i_i126_i_28_c_compstr810_sel_x_b = i_add_i_i_i_i_i126_i_28_c_compstr810_q[15:0];

    // i_conv_i_i_i_i_i75_i277_29_c_compstr830_sel_x(BITSELECT,3634)@70
    assign i_conv_i_i_i_i_i75_i277_29_c_compstr830_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_28_c_compstr810_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_29_c_compstr830_vt_select_15(BITSELECT,7437)@70
    assign i_conv_i_i_i_i_i75_i277_29_c_compstr830_vt_select_15_b = i_conv_i_i_i_i_i75_i277_29_c_compstr830_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_29_c_compstr830_vt_join(BITJOIN,7436)@70
    assign i_conv_i_i_i_i_i75_i277_29_c_compstr830_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_29_c_compstr830_vt_select_15_b};

    // leftShiftStage0_uid23738_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x(MUX,23737)@70
    assign leftShiftStage0_uid23738_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23738_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_29_c_compstr830_vt_join_q or leftShiftStage0Idx1_uid23736_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23738_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23738_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_29_c_compstr830_vt_join_q;
            1'b1 : leftShiftStage0_uid23738_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23736_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23738_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23743_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x(MUX,23742)@70
    assign leftShiftStage1_uid23743_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23743_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_s or leftShiftStage0_uid23738_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23741_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23743_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23743_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q = leftShiftStage0_uid23738_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23743_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23741_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23743_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23748_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x(MUX,23747)@70
    assign leftShiftStage2_uid23748_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23748_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_s or leftShiftStage1_uid23743_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23746_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23748_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23748_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q = leftShiftStage1_uid23743_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23748_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23746_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23748_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_29_c_compstr831_vt_select_28(BITSELECT,9187)@70
    assign i_shl_i_i_i_i_i77_i_29_c_compstr831_vt_select_28_b = leftShiftStage2_uid23748_i_shl_i_i_i_i_i77_i_29_c_compstr0_shift_x_q[28:13];

    // redist461_i_shl_i_i_i_i_i77_i_29_c_compstr831_vt_select_28_b_1(DELAY,28689)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist461_i_shl_i_i_i_i_i77_i_29_c_compstr831_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_29_c_compstr831_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_29_c_compstr831_vt_join(BITJOIN,9186)@71
    assign i_shl_i_i_i_i_i77_i_29_c_compstr831_vt_join_q = {redist461_i_shl_i_i_i_i_i77_i_29_c_compstr831_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma(CHAINMULTADD,28147)@65 + 5
    // out q@71
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ah[0] <= redist829_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_59_tpl_57_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ah[1] <= redist828_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_58_tpl_57_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ch[0] <= redist575_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_59_tpl_57_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ch[1] <= redist574_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_58_tpl_57_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832(ADD,8443)@71
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compstr827_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compstr829_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compstr828_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_29_c_compstr831_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_29_c_compstr831_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_o[33:0];

    // rightShiftStage0_uid16736_dupName_115_i_unnamed_c_compstr0_shift_x(MUX,16735)@71
    assign rightShiftStage0_uid16736_dupName_115_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16736_dupName_115_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_q or rightShiftStage0Idx1_uid16734_dupName_115_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16736_dupName_115_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16736_dupName_115_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_q;
            1'b1 : rightShiftStage0_uid16736_dupName_115_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16734_dupName_115_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16736_dupName_115_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16741_dupName_115_i_unnamed_c_compstr0_shift_x(MUX,16740)@71
    assign rightShiftStage1_uid16741_dupName_115_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16741_dupName_115_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16736_dupName_115_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16739_dupName_115_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16741_dupName_115_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16741_dupName_115_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16736_dupName_115_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16741_dupName_115_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16739_dupName_115_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16741_dupName_115_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16746_dupName_115_i_unnamed_c_compstr0_shift_x(MUX,16745)@71
    assign rightShiftStage2_uid16746_dupName_115_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16746_dupName_115_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16741_dupName_115_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16744_dupName_115_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16746_dupName_115_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16746_dupName_115_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16741_dupName_115_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16746_dupName_115_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16744_dupName_115_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16746_dupName_115_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr833_vt_select_20(BITSELECT,12478)@71
    assign i_unnamed_c_compstr833_vt_select_20_b = rightShiftStage2_uid16746_dupName_115_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr833_vt_join(BITJOIN,12477)@71
    assign i_unnamed_c_compstr833_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr833_vt_select_20_b};

    // i_conv_i_i_i_i97_i_29_c_compstr834_sel_x(BITSELECT,3505)@71
    assign i_conv_i_i_i_i97_i_29_c_compstr834_sel_x_b = i_unnamed_c_compstr833_vt_join_q[15:0];

    // redist1231_i_conv_i_i_i_i97_i_29_c_compstr834_sel_x_b_1(DELAY,29459)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1231_i_conv_i_i_i_i97_i_29_c_compstr834_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_29_c_compstr834_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16755_dupName_116_i_unnamed_c_compstr0_shift_x(BITSELECT,16754)@71
    assign rightShiftStage1Idx1Rng8_uid16755_dupName_116_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16754_dupName_116_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16757_dupName_116_i_unnamed_c_compstr0_shift_x(BITJOIN,16756)@71
    assign rightShiftStage1Idx1_uid16757_dupName_116_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16755_dupName_116_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16750_dupName_116_i_unnamed_c_compstr0_shift_x(BITSELECT,16749)@71
    assign rightShiftStage0Idx1Rng4_uid16750_dupName_116_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_q[33:4];

    // rightShiftStage0Idx1_uid16752_dupName_116_i_unnamed_c_compstr0_shift_x(BITJOIN,16751)@71
    assign rightShiftStage0Idx1_uid16752_dupName_116_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16750_dupName_116_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16754_dupName_116_i_unnamed_c_compstr0_shift_x(MUX,16753)@71
    assign rightShiftStage0_uid16754_dupName_116_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16754_dupName_116_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_q or rightShiftStage0Idx1_uid16752_dupName_116_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16754_dupName_116_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16754_dupName_116_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compstr832_q;
            1'b1 : rightShiftStage0_uid16754_dupName_116_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16752_dupName_116_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16754_dupName_116_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16759_dupName_116_i_unnamed_c_compstr0_shift_x(MUX,16758)@71
    assign rightShiftStage1_uid16759_dupName_116_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16759_dupName_116_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16754_dupName_116_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16757_dupName_116_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16759_dupName_116_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16759_dupName_116_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16754_dupName_116_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16759_dupName_116_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16757_dupName_116_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16759_dupName_116_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr835_vt_select_21(BITSELECT,12481)@71
    assign i_unnamed_c_compstr835_vt_select_21_b = rightShiftStage1_uid16759_dupName_116_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr835_vt_join(BITJOIN,12480)@71
    assign i_unnamed_c_compstr835_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr835_vt_select_21_b};

    // i_unnamed_c_compstr836_sel_x(BITSELECT,6278)@71
    assign i_unnamed_c_compstr836_sel_x_b = i_unnamed_c_compstr835_vt_join_q[15:0];

    // i_unnamed_c_compstr837_BitSelect_for_a(BITSELECT,27945)@71
    assign i_unnamed_c_compstr837_BitSelect_for_a_b = i_unnamed_c_compstr836_sel_x_b[0:0];

    // i_unnamed_c_compstr837_join(BITJOIN,27946)@71
    assign i_unnamed_c_compstr837_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr837_BitSelect_for_a_b};

    // i_unnamed_c_compstr837_vt_select_0(BITSELECT,12486)@71
    assign i_unnamed_c_compstr837_vt_select_0_b = i_unnamed_c_compstr837_join_q[0:0];

    // redist14_i_unnamed_c_compstr837_vt_select_0_b_1(DELAY,28242)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist14_i_unnamed_c_compstr837_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr837_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr837_vt_join(BITJOIN,12485)@72
    assign i_unnamed_c_compstr837_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist14_i_unnamed_c_compstr837_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_29_c_compstr838(ADD,6900)@72
    assign i_add_i_i_i_i_i126_i_29_c_compstr838_a = {1'b0, i_unnamed_c_compstr837_vt_join_q};
    assign i_add_i_i_i_i_i126_i_29_c_compstr838_b = {1'b0, redist1231_i_conv_i_i_i_i97_i_29_c_compstr834_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_29_c_compstr838_o = $unsigned(i_add_i_i_i_i_i126_i_29_c_compstr838_a) + $unsigned(i_add_i_i_i_i_i126_i_29_c_compstr838_b);
    assign i_add_i_i_i_i_i126_i_29_c_compstr838_q = i_add_i_i_i_i_i126_i_29_c_compstr838_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_29_c_compstr838_sel_x(BITSELECT,2094)@72
    assign bgTrunc_i_add_i_i_i_i_i126_i_29_c_compstr838_sel_x_b = i_add_i_i_i_i_i126_i_29_c_compstr838_q[15:0];

    // i_conv_i_i_i_i_i75_i277_30_c_compstr858_sel_x(BITSELECT,3636)@72
    assign i_conv_i_i_i_i_i75_i277_30_c_compstr858_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_29_c_compstr838_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_30_c_compstr858_vt_select_15(BITSELECT,7445)@72
    assign i_conv_i_i_i_i_i75_i277_30_c_compstr858_vt_select_15_b = i_conv_i_i_i_i_i75_i277_30_c_compstr858_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_30_c_compstr858_vt_join(BITJOIN,7444)@72
    assign i_conv_i_i_i_i_i75_i277_30_c_compstr858_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_30_c_compstr858_vt_select_15_b};

    // leftShiftStage0_uid23774_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x(MUX,23773)@72
    assign leftShiftStage0_uid23774_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23774_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_30_c_compstr858_vt_join_q or leftShiftStage0Idx1_uid23772_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23774_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23774_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_30_c_compstr858_vt_join_q;
            1'b1 : leftShiftStage0_uid23774_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23772_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23774_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23779_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x(MUX,23778)@72
    assign leftShiftStage1_uid23779_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23779_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_s or leftShiftStage0_uid23774_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23777_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23779_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23779_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q = leftShiftStage0_uid23774_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23779_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23777_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23779_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23784_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x(MUX,23783)@72
    assign leftShiftStage2_uid23784_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23784_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_s or leftShiftStage1_uid23779_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23782_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23784_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23784_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q = leftShiftStage1_uid23779_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23784_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23782_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23784_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_30_c_compstr859_vt_select_28(BITSELECT,9193)@72
    assign i_shl_i_i_i_i_i77_i_30_c_compstr859_vt_select_28_b = leftShiftStage2_uid23784_i_shl_i_i_i_i_i77_i_30_c_compstr0_shift_x_q[28:13];

    // redist459_i_shl_i_i_i_i_i77_i_30_c_compstr859_vt_select_28_b_1(DELAY,28687)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist459_i_shl_i_i_i_i_i77_i_30_c_compstr859_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_30_c_compstr859_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_30_c_compstr859_vt_join(BITJOIN,9192)@73
    assign i_shl_i_i_i_i_i77_i_30_c_compstr859_vt_join_q = {redist459_i_shl_i_i_i_i_i77_i_30_c_compstr859_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma(CHAINMULTADD,28149)@67 + 5
    // out q@73
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ah[0] <= redist831_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_61_tpl_59_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ah[1] <= redist830_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_60_tpl_59_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ch[0] <= redist577_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_61_tpl_59_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ch[1] <= redist576_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_60_tpl_59_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860(ADD,8445)@73
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compstr855_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compstr857_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compstr856_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_30_c_compstr859_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_30_c_compstr859_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_o[33:0];

    // rightShiftStage0_uid16798_dupName_119_i_unnamed_c_compstr0_shift_x(MUX,16797)@73
    assign rightShiftStage0_uid16798_dupName_119_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16798_dupName_119_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_q or rightShiftStage0Idx1_uid16796_dupName_119_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16798_dupName_119_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16798_dupName_119_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_q;
            1'b1 : rightShiftStage0_uid16798_dupName_119_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16796_dupName_119_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16798_dupName_119_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16803_dupName_119_i_unnamed_c_compstr0_shift_x(MUX,16802)@73
    assign rightShiftStage1_uid16803_dupName_119_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16803_dupName_119_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16798_dupName_119_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16801_dupName_119_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16803_dupName_119_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16803_dupName_119_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16798_dupName_119_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16803_dupName_119_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16801_dupName_119_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16803_dupName_119_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16808_dupName_119_i_unnamed_c_compstr0_shift_x(MUX,16807)@73
    assign rightShiftStage2_uid16808_dupName_119_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16808_dupName_119_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16803_dupName_119_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16806_dupName_119_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16808_dupName_119_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16808_dupName_119_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16803_dupName_119_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16808_dupName_119_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16806_dupName_119_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16808_dupName_119_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr861_vt_select_20(BITSELECT,12500)@73
    assign i_unnamed_c_compstr861_vt_select_20_b = rightShiftStage2_uid16808_dupName_119_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr861_vt_join(BITJOIN,12499)@73
    assign i_unnamed_c_compstr861_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr861_vt_select_20_b};

    // i_conv_i_i_i_i97_i_30_c_compstr862_sel_x(BITSELECT,3507)@73
    assign i_conv_i_i_i_i97_i_30_c_compstr862_sel_x_b = i_unnamed_c_compstr861_vt_join_q[15:0];

    // redist1229_i_conv_i_i_i_i97_i_30_c_compstr862_sel_x_b_1(DELAY,29457)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1229_i_conv_i_i_i_i97_i_30_c_compstr862_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_30_c_compstr862_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16817_dupName_120_i_unnamed_c_compstr0_shift_x(BITSELECT,16816)@73
    assign rightShiftStage1Idx1Rng8_uid16817_dupName_120_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16816_dupName_120_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16819_dupName_120_i_unnamed_c_compstr0_shift_x(BITJOIN,16818)@73
    assign rightShiftStage1Idx1_uid16819_dupName_120_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16817_dupName_120_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16812_dupName_120_i_unnamed_c_compstr0_shift_x(BITSELECT,16811)@73
    assign rightShiftStage0Idx1Rng4_uid16812_dupName_120_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_q[33:4];

    // rightShiftStage0Idx1_uid16814_dupName_120_i_unnamed_c_compstr0_shift_x(BITJOIN,16813)@73
    assign rightShiftStage0Idx1_uid16814_dupName_120_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16812_dupName_120_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16816_dupName_120_i_unnamed_c_compstr0_shift_x(MUX,16815)@73
    assign rightShiftStage0_uid16816_dupName_120_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16816_dupName_120_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_q or rightShiftStage0Idx1_uid16814_dupName_120_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16816_dupName_120_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16816_dupName_120_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compstr860_q;
            1'b1 : rightShiftStage0_uid16816_dupName_120_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16814_dupName_120_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16816_dupName_120_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16821_dupName_120_i_unnamed_c_compstr0_shift_x(MUX,16820)@73
    assign rightShiftStage1_uid16821_dupName_120_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16821_dupName_120_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16816_dupName_120_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16819_dupName_120_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16821_dupName_120_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16821_dupName_120_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16816_dupName_120_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16821_dupName_120_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16819_dupName_120_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16821_dupName_120_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr863_vt_select_21(BITSELECT,12503)@73
    assign i_unnamed_c_compstr863_vt_select_21_b = rightShiftStage1_uid16821_dupName_120_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr863_vt_join(BITJOIN,12502)@73
    assign i_unnamed_c_compstr863_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr863_vt_select_21_b};

    // i_unnamed_c_compstr864_sel_x(BITSELECT,6280)@73
    assign i_unnamed_c_compstr864_sel_x_b = i_unnamed_c_compstr863_vt_join_q[15:0];

    // i_unnamed_c_compstr865_BitSelect_for_a(BITSELECT,27949)@73
    assign i_unnamed_c_compstr865_BitSelect_for_a_b = i_unnamed_c_compstr864_sel_x_b[0:0];

    // i_unnamed_c_compstr865_join(BITJOIN,27950)@73
    assign i_unnamed_c_compstr865_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr865_BitSelect_for_a_b};

    // i_unnamed_c_compstr865_vt_select_0(BITSELECT,12508)@73
    assign i_unnamed_c_compstr865_vt_select_0_b = i_unnamed_c_compstr865_join_q[0:0];

    // redist12_i_unnamed_c_compstr865_vt_select_0_b_1(DELAY,28240)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist12_i_unnamed_c_compstr865_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr865_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr865_vt_join(BITJOIN,12507)@74
    assign i_unnamed_c_compstr865_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist12_i_unnamed_c_compstr865_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_30_c_compstr866(ADD,6902)@74
    assign i_add_i_i_i_i_i126_i_30_c_compstr866_a = {1'b0, i_unnamed_c_compstr865_vt_join_q};
    assign i_add_i_i_i_i_i126_i_30_c_compstr866_b = {1'b0, redist1229_i_conv_i_i_i_i97_i_30_c_compstr862_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_30_c_compstr866_o = $unsigned(i_add_i_i_i_i_i126_i_30_c_compstr866_a) + $unsigned(i_add_i_i_i_i_i126_i_30_c_compstr866_b);
    assign i_add_i_i_i_i_i126_i_30_c_compstr866_q = i_add_i_i_i_i_i126_i_30_c_compstr866_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_30_c_compstr866_sel_x(BITSELECT,2096)@74
    assign bgTrunc_i_add_i_i_i_i_i126_i_30_c_compstr866_sel_x_b = i_add_i_i_i_i_i126_i_30_c_compstr866_q[15:0];

    // i_conv_i_i_i_i_i75_i277_31_c_compstr886_sel_x(BITSELECT,3637)@74
    assign i_conv_i_i_i_i_i75_i277_31_c_compstr886_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_30_c_compstr866_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_31_c_compstr886_vt_select_15(BITSELECT,7449)@74
    assign i_conv_i_i_i_i_i75_i277_31_c_compstr886_vt_select_15_b = i_conv_i_i_i_i_i75_i277_31_c_compstr886_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_31_c_compstr886_vt_join(BITJOIN,7448)@74
    assign i_conv_i_i_i_i_i75_i277_31_c_compstr886_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_31_c_compstr886_vt_select_15_b};

    // leftShiftStage0_uid23792_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x(MUX,23791)@74
    assign leftShiftStage0_uid23792_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23792_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_31_c_compstr886_vt_join_q or leftShiftStage0Idx1_uid23790_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23792_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23792_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_31_c_compstr886_vt_join_q;
            1'b1 : leftShiftStage0_uid23792_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23790_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23792_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23797_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x(MUX,23796)@74
    assign leftShiftStage1_uid23797_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23797_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_s or leftShiftStage0_uid23792_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23795_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23797_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23797_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q = leftShiftStage0_uid23792_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23797_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23795_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23797_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23802_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x(MUX,23801)@74
    assign leftShiftStage2_uid23802_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23802_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_s or leftShiftStage1_uid23797_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23800_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23802_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23802_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q = leftShiftStage1_uid23797_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23802_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23800_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23802_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_31_c_compstr887_vt_select_28(BITSELECT,9196)@74
    assign i_shl_i_i_i_i_i77_i_31_c_compstr887_vt_select_28_b = leftShiftStage2_uid23802_i_shl_i_i_i_i_i77_i_31_c_compstr0_shift_x_q[28:13];

    // redist458_i_shl_i_i_i_i_i77_i_31_c_compstr887_vt_select_28_b_1(DELAY,28686)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist458_i_shl_i_i_i_i_i77_i_31_c_compstr887_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_31_c_compstr887_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_31_c_compstr887_vt_join(BITJOIN,9195)@75
    assign i_shl_i_i_i_i_i77_i_31_c_compstr887_vt_join_q = {redist458_i_shl_i_i_i_i_i77_i_31_c_compstr887_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma(CHAINMULTADD,28150)@69 + 5
    // out q@75
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ah[0] <= redist833_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_63_tpl_61_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ah[1] <= redist832_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_62_tpl_61_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ch[0] <= redist579_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_63_tpl_61_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ch[1] <= redist578_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_62_tpl_61_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888(ADD,8446)@75
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compstr883_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compstr885_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compstr884_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_31_c_compstr887_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_31_c_compstr887_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_o[33:0];

    // rightShiftStage0_uid16860_dupName_123_i_unnamed_c_compstr0_shift_x(MUX,16859)@75
    assign rightShiftStage0_uid16860_dupName_123_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16860_dupName_123_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_q or rightShiftStage0Idx1_uid16858_dupName_123_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16860_dupName_123_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16860_dupName_123_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_q;
            1'b1 : rightShiftStage0_uid16860_dupName_123_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16858_dupName_123_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16860_dupName_123_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16865_dupName_123_i_unnamed_c_compstr0_shift_x(MUX,16864)@75
    assign rightShiftStage1_uid16865_dupName_123_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16865_dupName_123_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16860_dupName_123_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16863_dupName_123_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16865_dupName_123_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16865_dupName_123_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16860_dupName_123_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16865_dupName_123_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16863_dupName_123_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16865_dupName_123_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16870_dupName_123_i_unnamed_c_compstr0_shift_x(MUX,16869)@75
    assign rightShiftStage2_uid16870_dupName_123_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16870_dupName_123_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16865_dupName_123_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16868_dupName_123_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16870_dupName_123_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16870_dupName_123_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16865_dupName_123_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16870_dupName_123_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16868_dupName_123_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16870_dupName_123_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr889_vt_select_20(BITSELECT,12522)@75
    assign i_unnamed_c_compstr889_vt_select_20_b = rightShiftStage2_uid16870_dupName_123_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr889_vt_join(BITJOIN,12521)@75
    assign i_unnamed_c_compstr889_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr889_vt_select_20_b};

    // i_conv_i_i_i_i97_i_31_c_compstr890_sel_x(BITSELECT,3508)@75
    assign i_conv_i_i_i_i97_i_31_c_compstr890_sel_x_b = i_unnamed_c_compstr889_vt_join_q[15:0];

    // redist1228_i_conv_i_i_i_i97_i_31_c_compstr890_sel_x_b_1(DELAY,29456)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1228_i_conv_i_i_i_i97_i_31_c_compstr890_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_31_c_compstr890_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16879_dupName_124_i_unnamed_c_compstr0_shift_x(BITSELECT,16878)@75
    assign rightShiftStage1Idx1Rng8_uid16879_dupName_124_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16878_dupName_124_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16881_dupName_124_i_unnamed_c_compstr0_shift_x(BITJOIN,16880)@75
    assign rightShiftStage1Idx1_uid16881_dupName_124_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16879_dupName_124_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16874_dupName_124_i_unnamed_c_compstr0_shift_x(BITSELECT,16873)@75
    assign rightShiftStage0Idx1Rng4_uid16874_dupName_124_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_q[33:4];

    // rightShiftStage0Idx1_uid16876_dupName_124_i_unnamed_c_compstr0_shift_x(BITJOIN,16875)@75
    assign rightShiftStage0Idx1_uid16876_dupName_124_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16874_dupName_124_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16878_dupName_124_i_unnamed_c_compstr0_shift_x(MUX,16877)@75
    assign rightShiftStage0_uid16878_dupName_124_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16878_dupName_124_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_q or rightShiftStage0Idx1_uid16876_dupName_124_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16878_dupName_124_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16878_dupName_124_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compstr888_q;
            1'b1 : rightShiftStage0_uid16878_dupName_124_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16876_dupName_124_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16878_dupName_124_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16883_dupName_124_i_unnamed_c_compstr0_shift_x(MUX,16882)@75
    assign rightShiftStage1_uid16883_dupName_124_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16883_dupName_124_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16878_dupName_124_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16881_dupName_124_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16883_dupName_124_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16883_dupName_124_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16878_dupName_124_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16883_dupName_124_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16881_dupName_124_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16883_dupName_124_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr891_vt_select_21(BITSELECT,12525)@75
    assign i_unnamed_c_compstr891_vt_select_21_b = rightShiftStage1_uid16883_dupName_124_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr891_vt_join(BITJOIN,12524)@75
    assign i_unnamed_c_compstr891_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr891_vt_select_21_b};

    // i_unnamed_c_compstr892_sel_x(BITSELECT,6282)@75
    assign i_unnamed_c_compstr892_sel_x_b = i_unnamed_c_compstr891_vt_join_q[15:0];

    // i_unnamed_c_compstr893_BitSelect_for_a(BITSELECT,27953)@75
    assign i_unnamed_c_compstr893_BitSelect_for_a_b = i_unnamed_c_compstr892_sel_x_b[0:0];

    // i_unnamed_c_compstr893_join(BITJOIN,27954)@75
    assign i_unnamed_c_compstr893_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr893_BitSelect_for_a_b};

    // i_unnamed_c_compstr893_vt_select_0(BITSELECT,12530)@75
    assign i_unnamed_c_compstr893_vt_select_0_b = i_unnamed_c_compstr893_join_q[0:0];

    // redist10_i_unnamed_c_compstr893_vt_select_0_b_1(DELAY,28238)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist10_i_unnamed_c_compstr893_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr893_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr893_vt_join(BITJOIN,12529)@76
    assign i_unnamed_c_compstr893_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist10_i_unnamed_c_compstr893_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_31_c_compstr894(ADD,6903)@76
    assign i_add_i_i_i_i_i126_i_31_c_compstr894_a = {1'b0, i_unnamed_c_compstr893_vt_join_q};
    assign i_add_i_i_i_i_i126_i_31_c_compstr894_b = {1'b0, redist1228_i_conv_i_i_i_i97_i_31_c_compstr890_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_31_c_compstr894_o = $unsigned(i_add_i_i_i_i_i126_i_31_c_compstr894_a) + $unsigned(i_add_i_i_i_i_i126_i_31_c_compstr894_b);
    assign i_add_i_i_i_i_i126_i_31_c_compstr894_q = i_add_i_i_i_i_i126_i_31_c_compstr894_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_31_c_compstr894_sel_x(BITSELECT,2097)@76
    assign bgTrunc_i_add_i_i_i_i_i126_i_31_c_compstr894_sel_x_b = i_add_i_i_i_i_i126_i_31_c_compstr894_q[15:0];

    // i_conv_i_i_i_i_i75_i277_32_c_compstr914_sel_x(BITSELECT,3638)@76
    assign i_conv_i_i_i_i_i75_i277_32_c_compstr914_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_31_c_compstr894_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_32_c_compstr914_vt_select_15(BITSELECT,7453)@76
    assign i_conv_i_i_i_i_i75_i277_32_c_compstr914_vt_select_15_b = i_conv_i_i_i_i_i75_i277_32_c_compstr914_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_32_c_compstr914_vt_join(BITJOIN,7452)@76
    assign i_conv_i_i_i_i_i75_i277_32_c_compstr914_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_32_c_compstr914_vt_select_15_b};

    // leftShiftStage0_uid23810_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x(MUX,23809)@76
    assign leftShiftStage0_uid23810_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23810_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_32_c_compstr914_vt_join_q or leftShiftStage0Idx1_uid23808_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23810_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23810_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_32_c_compstr914_vt_join_q;
            1'b1 : leftShiftStage0_uid23810_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23808_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23810_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23815_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x(MUX,23814)@76
    assign leftShiftStage1_uid23815_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23815_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_s or leftShiftStage0_uid23810_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23813_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23815_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23815_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q = leftShiftStage0_uid23810_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23815_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23813_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23815_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23820_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x(MUX,23819)@76
    assign leftShiftStage2_uid23820_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23820_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_s or leftShiftStage1_uid23815_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23818_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23820_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23820_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q = leftShiftStage1_uid23815_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23820_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23818_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23820_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_32_c_compstr915_vt_select_28(BITSELECT,9199)@76
    assign i_shl_i_i_i_i_i77_i_32_c_compstr915_vt_select_28_b = leftShiftStage2_uid23820_i_shl_i_i_i_i_i77_i_32_c_compstr0_shift_x_q[28:13];

    // redist457_i_shl_i_i_i_i_i77_i_32_c_compstr915_vt_select_28_b_1(DELAY,28685)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist457_i_shl_i_i_i_i_i77_i_32_c_compstr915_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_32_c_compstr915_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_32_c_compstr915_vt_join(BITJOIN,9198)@77
    assign i_shl_i_i_i_i_i77_i_32_c_compstr915_vt_join_q = {redist457_i_shl_i_i_i_i_i77_i_32_c_compstr915_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma(CHAINMULTADD,28151)@71 + 5
    // out q@77
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ah[0] <= redist835_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_65_tpl_63_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ah[1] <= redist834_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_64_tpl_63_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ch[0] <= redist581_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_65_tpl_63_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ch[1] <= redist580_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_64_tpl_63_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916(ADD,8447)@77
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compstr911_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compstr913_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compstr912_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_32_c_compstr915_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_32_c_compstr915_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_o[33:0];

    // rightShiftStage0_uid16922_dupName_127_i_unnamed_c_compstr0_shift_x(MUX,16921)@77
    assign rightShiftStage0_uid16922_dupName_127_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16922_dupName_127_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_q or rightShiftStage0Idx1_uid16920_dupName_127_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16922_dupName_127_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16922_dupName_127_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_q;
            1'b1 : rightShiftStage0_uid16922_dupName_127_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16920_dupName_127_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16922_dupName_127_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16927_dupName_127_i_unnamed_c_compstr0_shift_x(MUX,16926)@77
    assign rightShiftStage1_uid16927_dupName_127_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16927_dupName_127_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16922_dupName_127_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16925_dupName_127_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16927_dupName_127_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16927_dupName_127_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16922_dupName_127_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16927_dupName_127_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16925_dupName_127_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16927_dupName_127_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16932_dupName_127_i_unnamed_c_compstr0_shift_x(MUX,16931)@77
    assign rightShiftStage2_uid16932_dupName_127_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16932_dupName_127_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16927_dupName_127_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16930_dupName_127_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16932_dupName_127_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16932_dupName_127_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16927_dupName_127_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16932_dupName_127_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16930_dupName_127_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16932_dupName_127_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr917_vt_select_20(BITSELECT,12544)@77
    assign i_unnamed_c_compstr917_vt_select_20_b = rightShiftStage2_uid16932_dupName_127_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr917_vt_join(BITJOIN,12543)@77
    assign i_unnamed_c_compstr917_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr917_vt_select_20_b};

    // i_conv_i_i_i_i97_i_32_c_compstr918_sel_x(BITSELECT,3509)@77
    assign i_conv_i_i_i_i97_i_32_c_compstr918_sel_x_b = i_unnamed_c_compstr917_vt_join_q[15:0];

    // redist1227_i_conv_i_i_i_i97_i_32_c_compstr918_sel_x_b_1(DELAY,29455)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1227_i_conv_i_i_i_i97_i_32_c_compstr918_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_32_c_compstr918_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16941_dupName_128_i_unnamed_c_compstr0_shift_x(BITSELECT,16940)@77
    assign rightShiftStage1Idx1Rng8_uid16941_dupName_128_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid16940_dupName_128_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16943_dupName_128_i_unnamed_c_compstr0_shift_x(BITJOIN,16942)@77
    assign rightShiftStage1Idx1_uid16943_dupName_128_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid16941_dupName_128_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16936_dupName_128_i_unnamed_c_compstr0_shift_x(BITSELECT,16935)@77
    assign rightShiftStage0Idx1Rng4_uid16936_dupName_128_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_q[33:4];

    // rightShiftStage0Idx1_uid16938_dupName_128_i_unnamed_c_compstr0_shift_x(BITJOIN,16937)@77
    assign rightShiftStage0Idx1_uid16938_dupName_128_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16936_dupName_128_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid16940_dupName_128_i_unnamed_c_compstr0_shift_x(MUX,16939)@77
    assign rightShiftStage0_uid16940_dupName_128_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16940_dupName_128_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_q or rightShiftStage0Idx1_uid16938_dupName_128_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16940_dupName_128_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16940_dupName_128_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compstr916_q;
            1'b1 : rightShiftStage0_uid16940_dupName_128_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16938_dupName_128_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16940_dupName_128_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16945_dupName_128_i_unnamed_c_compstr0_shift_x(MUX,16944)@77
    assign rightShiftStage1_uid16945_dupName_128_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16945_dupName_128_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16940_dupName_128_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16943_dupName_128_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16945_dupName_128_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16945_dupName_128_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16940_dupName_128_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16945_dupName_128_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16943_dupName_128_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16945_dupName_128_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr919_vt_select_21(BITSELECT,12547)@77
    assign i_unnamed_c_compstr919_vt_select_21_b = rightShiftStage1_uid16945_dupName_128_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr919_vt_join(BITJOIN,12546)@77
    assign i_unnamed_c_compstr919_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr919_vt_select_21_b};

    // i_unnamed_c_compstr920_sel_x(BITSELECT,6284)@77
    assign i_unnamed_c_compstr920_sel_x_b = i_unnamed_c_compstr919_vt_join_q[15:0];

    // i_unnamed_c_compstr921_BitSelect_for_a(BITSELECT,27957)@77
    assign i_unnamed_c_compstr921_BitSelect_for_a_b = i_unnamed_c_compstr920_sel_x_b[0:0];

    // i_unnamed_c_compstr921_join(BITJOIN,27958)@77
    assign i_unnamed_c_compstr921_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr921_BitSelect_for_a_b};

    // i_unnamed_c_compstr921_vt_select_0(BITSELECT,12552)@77
    assign i_unnamed_c_compstr921_vt_select_0_b = i_unnamed_c_compstr921_join_q[0:0];

    // redist8_i_unnamed_c_compstr921_vt_select_0_b_1(DELAY,28236)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist8_i_unnamed_c_compstr921_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr921_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr921_vt_join(BITJOIN,12551)@78
    assign i_unnamed_c_compstr921_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist8_i_unnamed_c_compstr921_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_32_c_compstr922(ADD,6904)@78
    assign i_add_i_i_i_i_i126_i_32_c_compstr922_a = {1'b0, i_unnamed_c_compstr921_vt_join_q};
    assign i_add_i_i_i_i_i126_i_32_c_compstr922_b = {1'b0, redist1227_i_conv_i_i_i_i97_i_32_c_compstr918_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_32_c_compstr922_o = $unsigned(i_add_i_i_i_i_i126_i_32_c_compstr922_a) + $unsigned(i_add_i_i_i_i_i126_i_32_c_compstr922_b);
    assign i_add_i_i_i_i_i126_i_32_c_compstr922_q = i_add_i_i_i_i_i126_i_32_c_compstr922_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_32_c_compstr922_sel_x(BITSELECT,2098)@78
    assign bgTrunc_i_add_i_i_i_i_i126_i_32_c_compstr922_sel_x_b = i_add_i_i_i_i_i126_i_32_c_compstr922_q[15:0];

    // i_conv_i_i_i_i_i75_i277_33_c_compstr942_sel_x(BITSELECT,3639)@78
    assign i_conv_i_i_i_i_i75_i277_33_c_compstr942_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_32_c_compstr922_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_33_c_compstr942_vt_select_15(BITSELECT,7457)@78
    assign i_conv_i_i_i_i_i75_i277_33_c_compstr942_vt_select_15_b = i_conv_i_i_i_i_i75_i277_33_c_compstr942_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_33_c_compstr942_vt_join(BITJOIN,7456)@78
    assign i_conv_i_i_i_i_i75_i277_33_c_compstr942_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_33_c_compstr942_vt_select_15_b};

    // leftShiftStage0_uid23828_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x(MUX,23827)@78
    assign leftShiftStage0_uid23828_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23828_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_33_c_compstr942_vt_join_q or leftShiftStage0Idx1_uid23826_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23828_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23828_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_33_c_compstr942_vt_join_q;
            1'b1 : leftShiftStage0_uid23828_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23826_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23828_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23833_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x(MUX,23832)@78
    assign leftShiftStage1_uid23833_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23833_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_s or leftShiftStage0_uid23828_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23831_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23833_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23833_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q = leftShiftStage0_uid23828_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23833_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23831_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23833_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23838_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x(MUX,23837)@78
    assign leftShiftStage2_uid23838_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23838_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_s or leftShiftStage1_uid23833_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23836_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23838_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23838_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q = leftShiftStage1_uid23833_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23838_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23836_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23838_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_33_c_compstr943_vt_select_28(BITSELECT,9202)@78
    assign i_shl_i_i_i_i_i77_i_33_c_compstr943_vt_select_28_b = leftShiftStage2_uid23838_i_shl_i_i_i_i_i77_i_33_c_compstr0_shift_x_q[28:13];

    // redist456_i_shl_i_i_i_i_i77_i_33_c_compstr943_vt_select_28_b_1(DELAY,28684)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist456_i_shl_i_i_i_i_i77_i_33_c_compstr943_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_33_c_compstr943_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_33_c_compstr943_vt_join(BITJOIN,9201)@79
    assign i_shl_i_i_i_i_i77_i_33_c_compstr943_vt_join_q = {redist456_i_shl_i_i_i_i_i77_i_33_c_compstr943_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma(CHAINMULTADD,28152)@73 + 5
    // out q@79
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ah[0] <= redist837_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_67_tpl_65_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ah[1] <= redist836_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_66_tpl_65_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ch[0] <= redist583_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_67_tpl_65_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ch[1] <= redist582_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_66_tpl_65_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944(ADD,8448)@79
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compstr939_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compstr941_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compstr940_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_33_c_compstr943_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_33_c_compstr943_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_o[33:0];

    // rightShiftStage0_uid16984_dupName_131_i_unnamed_c_compstr0_shift_x(MUX,16983)@79
    assign rightShiftStage0_uid16984_dupName_131_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16984_dupName_131_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_q or rightShiftStage0Idx1_uid16982_dupName_131_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16984_dupName_131_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid16984_dupName_131_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_q;
            1'b1 : rightShiftStage0_uid16984_dupName_131_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid16982_dupName_131_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid16984_dupName_131_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16989_dupName_131_i_unnamed_c_compstr0_shift_x(MUX,16988)@79
    assign rightShiftStage1_uid16989_dupName_131_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16989_dupName_131_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid16984_dupName_131_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid16987_dupName_131_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16989_dupName_131_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid16989_dupName_131_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid16984_dupName_131_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid16989_dupName_131_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid16987_dupName_131_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid16989_dupName_131_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16994_dupName_131_i_unnamed_c_compstr0_shift_x(MUX,16993)@79
    assign rightShiftStage2_uid16994_dupName_131_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16994_dupName_131_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid16989_dupName_131_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid16992_dupName_131_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16994_dupName_131_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid16994_dupName_131_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid16989_dupName_131_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid16994_dupName_131_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid16992_dupName_131_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid16994_dupName_131_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr945_vt_select_20(BITSELECT,12569)@79
    assign i_unnamed_c_compstr945_vt_select_20_b = rightShiftStage2_uid16994_dupName_131_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr945_vt_join(BITJOIN,12568)@79
    assign i_unnamed_c_compstr945_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr945_vt_select_20_b};

    // i_conv_i_i_i_i97_i_33_c_compstr946_sel_x(BITSELECT,3510)@79
    assign i_conv_i_i_i_i97_i_33_c_compstr946_sel_x_b = i_unnamed_c_compstr945_vt_join_q[15:0];

    // redist1226_i_conv_i_i_i_i97_i_33_c_compstr946_sel_x_b_1(DELAY,29454)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1226_i_conv_i_i_i_i97_i_33_c_compstr946_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_33_c_compstr946_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17003_dupName_132_i_unnamed_c_compstr0_shift_x(BITSELECT,17002)@79
    assign rightShiftStage1Idx1Rng8_uid17003_dupName_132_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17002_dupName_132_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17005_dupName_132_i_unnamed_c_compstr0_shift_x(BITJOIN,17004)@79
    assign rightShiftStage1Idx1_uid17005_dupName_132_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17003_dupName_132_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16998_dupName_132_i_unnamed_c_compstr0_shift_x(BITSELECT,16997)@79
    assign rightShiftStage0Idx1Rng4_uid16998_dupName_132_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_q[33:4];

    // rightShiftStage0Idx1_uid17000_dupName_132_i_unnamed_c_compstr0_shift_x(BITJOIN,16999)@79
    assign rightShiftStage0Idx1_uid17000_dupName_132_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid16998_dupName_132_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17002_dupName_132_i_unnamed_c_compstr0_shift_x(MUX,17001)@79
    assign rightShiftStage0_uid17002_dupName_132_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17002_dupName_132_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_q or rightShiftStage0Idx1_uid17000_dupName_132_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17002_dupName_132_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17002_dupName_132_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compstr944_q;
            1'b1 : rightShiftStage0_uid17002_dupName_132_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17000_dupName_132_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17002_dupName_132_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17007_dupName_132_i_unnamed_c_compstr0_shift_x(MUX,17006)@79
    assign rightShiftStage1_uid17007_dupName_132_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17007_dupName_132_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17002_dupName_132_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17005_dupName_132_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17007_dupName_132_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17007_dupName_132_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17002_dupName_132_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17007_dupName_132_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17005_dupName_132_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17007_dupName_132_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr947_vt_select_21(BITSELECT,12572)@79
    assign i_unnamed_c_compstr947_vt_select_21_b = rightShiftStage1_uid17007_dupName_132_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr947_vt_join(BITJOIN,12571)@79
    assign i_unnamed_c_compstr947_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr947_vt_select_21_b};

    // i_unnamed_c_compstr948_sel_x(BITSELECT,6286)@79
    assign i_unnamed_c_compstr948_sel_x_b = i_unnamed_c_compstr947_vt_join_q[15:0];

    // i_unnamed_c_compstr949_BitSelect_for_a(BITSELECT,27961)@79
    assign i_unnamed_c_compstr949_BitSelect_for_a_b = i_unnamed_c_compstr948_sel_x_b[0:0];

    // i_unnamed_c_compstr949_join(BITJOIN,27962)@79
    assign i_unnamed_c_compstr949_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr949_BitSelect_for_a_b};

    // i_unnamed_c_compstr949_vt_select_0(BITSELECT,12577)@79
    assign i_unnamed_c_compstr949_vt_select_0_b = i_unnamed_c_compstr949_join_q[0:0];

    // redist6_i_unnamed_c_compstr949_vt_select_0_b_1(DELAY,28234)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist6_i_unnamed_c_compstr949_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr949_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr949_vt_join(BITJOIN,12576)@80
    assign i_unnamed_c_compstr949_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist6_i_unnamed_c_compstr949_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_33_c_compstr950(ADD,6905)@80
    assign i_add_i_i_i_i_i126_i_33_c_compstr950_a = {1'b0, i_unnamed_c_compstr949_vt_join_q};
    assign i_add_i_i_i_i_i126_i_33_c_compstr950_b = {1'b0, redist1226_i_conv_i_i_i_i97_i_33_c_compstr946_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_33_c_compstr950_o = $unsigned(i_add_i_i_i_i_i126_i_33_c_compstr950_a) + $unsigned(i_add_i_i_i_i_i126_i_33_c_compstr950_b);
    assign i_add_i_i_i_i_i126_i_33_c_compstr950_q = i_add_i_i_i_i_i126_i_33_c_compstr950_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_33_c_compstr950_sel_x(BITSELECT,2099)@80
    assign bgTrunc_i_add_i_i_i_i_i126_i_33_c_compstr950_sel_x_b = i_add_i_i_i_i_i126_i_33_c_compstr950_q[15:0];

    // i_conv_i_i_i_i_i75_i277_34_c_compstr970_sel_x(BITSELECT,3640)@80
    assign i_conv_i_i_i_i_i75_i277_34_c_compstr970_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_33_c_compstr950_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_34_c_compstr970_vt_select_15(BITSELECT,7461)@80
    assign i_conv_i_i_i_i_i75_i277_34_c_compstr970_vt_select_15_b = i_conv_i_i_i_i_i75_i277_34_c_compstr970_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_34_c_compstr970_vt_join(BITJOIN,7460)@80
    assign i_conv_i_i_i_i_i75_i277_34_c_compstr970_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_34_c_compstr970_vt_select_15_b};

    // leftShiftStage0_uid23846_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x(MUX,23845)@80
    assign leftShiftStage0_uid23846_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23846_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_34_c_compstr970_vt_join_q or leftShiftStage0Idx1_uid23844_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23846_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23846_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_34_c_compstr970_vt_join_q;
            1'b1 : leftShiftStage0_uid23846_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23844_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23846_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23851_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x(MUX,23850)@80
    assign leftShiftStage1_uid23851_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23851_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_s or leftShiftStage0_uid23846_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23849_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23851_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23851_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q = leftShiftStage0_uid23846_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23851_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23849_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23851_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23856_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x(MUX,23855)@80
    assign leftShiftStage2_uid23856_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23856_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_s or leftShiftStage1_uid23851_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23854_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23856_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23856_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q = leftShiftStage1_uid23851_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23856_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23854_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23856_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_34_c_compstr971_vt_select_28(BITSELECT,9205)@80
    assign i_shl_i_i_i_i_i77_i_34_c_compstr971_vt_select_28_b = leftShiftStage2_uid23856_i_shl_i_i_i_i_i77_i_34_c_compstr0_shift_x_q[28:13];

    // redist455_i_shl_i_i_i_i_i77_i_34_c_compstr971_vt_select_28_b_1(DELAY,28683)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist455_i_shl_i_i_i_i_i77_i_34_c_compstr971_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_34_c_compstr971_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_34_c_compstr971_vt_join(BITJOIN,9204)@81
    assign i_shl_i_i_i_i_i77_i_34_c_compstr971_vt_join_q = {redist455_i_shl_i_i_i_i_i77_i_34_c_compstr971_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma(CHAINMULTADD,28153)@75 + 5
    // out q@81
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ah[0] <= redist839_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_69_tpl_67_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ah[1] <= redist838_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_68_tpl_67_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ch[0] <= redist585_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_69_tpl_67_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ch[1] <= redist584_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_68_tpl_67_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972(ADD,8449)@81
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compstr967_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compstr969_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compstr968_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_34_c_compstr971_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_34_c_compstr971_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_o[33:0];

    // rightShiftStage0_uid17046_dupName_135_i_unnamed_c_compstr0_shift_x(MUX,17045)@81
    assign rightShiftStage0_uid17046_dupName_135_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17046_dupName_135_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_q or rightShiftStage0Idx1_uid17044_dupName_135_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17046_dupName_135_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17046_dupName_135_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_q;
            1'b1 : rightShiftStage0_uid17046_dupName_135_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17044_dupName_135_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17046_dupName_135_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17051_dupName_135_i_unnamed_c_compstr0_shift_x(MUX,17050)@81
    assign rightShiftStage1_uid17051_dupName_135_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17051_dupName_135_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17046_dupName_135_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17049_dupName_135_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17051_dupName_135_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17051_dupName_135_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17046_dupName_135_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17051_dupName_135_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17049_dupName_135_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17051_dupName_135_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17056_dupName_135_i_unnamed_c_compstr0_shift_x(MUX,17055)@81
    assign rightShiftStage2_uid17056_dupName_135_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17056_dupName_135_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17051_dupName_135_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17054_dupName_135_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17056_dupName_135_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17056_dupName_135_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17051_dupName_135_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17056_dupName_135_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17054_dupName_135_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17056_dupName_135_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr973_vt_select_20(BITSELECT,12596)@81
    assign i_unnamed_c_compstr973_vt_select_20_b = rightShiftStage2_uid17056_dupName_135_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr973_vt_join(BITJOIN,12595)@81
    assign i_unnamed_c_compstr973_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr973_vt_select_20_b};

    // i_conv_i_i_i_i97_i_34_c_compstr974_sel_x(BITSELECT,3511)@81
    assign i_conv_i_i_i_i97_i_34_c_compstr974_sel_x_b = i_unnamed_c_compstr973_vt_join_q[15:0];

    // redist1225_i_conv_i_i_i_i97_i_34_c_compstr974_sel_x_b_1(DELAY,29453)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1225_i_conv_i_i_i_i97_i_34_c_compstr974_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_34_c_compstr974_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17065_dupName_136_i_unnamed_c_compstr0_shift_x(BITSELECT,17064)@81
    assign rightShiftStage1Idx1Rng8_uid17065_dupName_136_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17064_dupName_136_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17067_dupName_136_i_unnamed_c_compstr0_shift_x(BITJOIN,17066)@81
    assign rightShiftStage1Idx1_uid17067_dupName_136_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17065_dupName_136_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17060_dupName_136_i_unnamed_c_compstr0_shift_x(BITSELECT,17059)@81
    assign rightShiftStage0Idx1Rng4_uid17060_dupName_136_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_q[33:4];

    // rightShiftStage0Idx1_uid17062_dupName_136_i_unnamed_c_compstr0_shift_x(BITJOIN,17061)@81
    assign rightShiftStage0Idx1_uid17062_dupName_136_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17060_dupName_136_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17064_dupName_136_i_unnamed_c_compstr0_shift_x(MUX,17063)@81
    assign rightShiftStage0_uid17064_dupName_136_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17064_dupName_136_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_q or rightShiftStage0Idx1_uid17062_dupName_136_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17064_dupName_136_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17064_dupName_136_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compstr972_q;
            1'b1 : rightShiftStage0_uid17064_dupName_136_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17062_dupName_136_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17064_dupName_136_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17069_dupName_136_i_unnamed_c_compstr0_shift_x(MUX,17068)@81
    assign rightShiftStage1_uid17069_dupName_136_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17069_dupName_136_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17064_dupName_136_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17067_dupName_136_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17069_dupName_136_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17069_dupName_136_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17064_dupName_136_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17069_dupName_136_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17067_dupName_136_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17069_dupName_136_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr975_vt_select_21(BITSELECT,12599)@81
    assign i_unnamed_c_compstr975_vt_select_21_b = rightShiftStage1_uid17069_dupName_136_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr975_vt_join(BITJOIN,12598)@81
    assign i_unnamed_c_compstr975_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr975_vt_select_21_b};

    // i_unnamed_c_compstr976_sel_x(BITSELECT,6289)@81
    assign i_unnamed_c_compstr976_sel_x_b = i_unnamed_c_compstr975_vt_join_q[15:0];

    // i_unnamed_c_compstr977_BitSelect_for_a(BITSELECT,27967)@81
    assign i_unnamed_c_compstr977_BitSelect_for_a_b = i_unnamed_c_compstr976_sel_x_b[0:0];

    // i_unnamed_c_compstr977_join(BITJOIN,27968)@81
    assign i_unnamed_c_compstr977_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr977_BitSelect_for_a_b};

    // i_unnamed_c_compstr977_vt_select_0(BITSELECT,12604)@81
    assign i_unnamed_c_compstr977_vt_select_0_b = i_unnamed_c_compstr977_join_q[0:0];

    // redist4_i_unnamed_c_compstr977_vt_select_0_b_1(DELAY,28232)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist4_i_unnamed_c_compstr977_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr977_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr977_vt_join(BITJOIN,12603)@82
    assign i_unnamed_c_compstr977_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist4_i_unnamed_c_compstr977_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_34_c_compstr978(ADD,6906)@82
    assign i_add_i_i_i_i_i126_i_34_c_compstr978_a = {1'b0, i_unnamed_c_compstr977_vt_join_q};
    assign i_add_i_i_i_i_i126_i_34_c_compstr978_b = {1'b0, redist1225_i_conv_i_i_i_i97_i_34_c_compstr974_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_34_c_compstr978_o = $unsigned(i_add_i_i_i_i_i126_i_34_c_compstr978_a) + $unsigned(i_add_i_i_i_i_i126_i_34_c_compstr978_b);
    assign i_add_i_i_i_i_i126_i_34_c_compstr978_q = i_add_i_i_i_i_i126_i_34_c_compstr978_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_34_c_compstr978_sel_x(BITSELECT,2100)@82
    assign bgTrunc_i_add_i_i_i_i_i126_i_34_c_compstr978_sel_x_b = i_add_i_i_i_i_i126_i_34_c_compstr978_q[15:0];

    // i_conv_i_i_i_i_i75_i277_35_c_compstr998_sel_x(BITSELECT,3641)@82
    assign i_conv_i_i_i_i_i75_i277_35_c_compstr998_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_34_c_compstr978_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_35_c_compstr998_vt_select_15(BITSELECT,7465)@82
    assign i_conv_i_i_i_i_i75_i277_35_c_compstr998_vt_select_15_b = i_conv_i_i_i_i_i75_i277_35_c_compstr998_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_35_c_compstr998_vt_join(BITJOIN,7464)@82
    assign i_conv_i_i_i_i_i75_i277_35_c_compstr998_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_35_c_compstr998_vt_select_15_b};

    // leftShiftStage0_uid23864_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x(MUX,23863)@82
    assign leftShiftStage0_uid23864_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23864_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_35_c_compstr998_vt_join_q or leftShiftStage0Idx1_uid23862_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23864_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23864_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_35_c_compstr998_vt_join_q;
            1'b1 : leftShiftStage0_uid23864_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23862_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23864_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23869_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x(MUX,23868)@82
    assign leftShiftStage1_uid23869_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23869_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_s or leftShiftStage0_uid23864_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23867_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23869_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23869_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q = leftShiftStage0_uid23864_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23869_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23867_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23869_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23874_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x(MUX,23873)@82
    assign leftShiftStage2_uid23874_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23874_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_s or leftShiftStage1_uid23869_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23872_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23874_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23874_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q = leftShiftStage1_uid23869_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23874_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23872_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23874_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_35_c_compstr999_vt_select_28(BITSELECT,9208)@82
    assign i_shl_i_i_i_i_i77_i_35_c_compstr999_vt_select_28_b = leftShiftStage2_uid23874_i_shl_i_i_i_i_i77_i_35_c_compstr0_shift_x_q[28:13];

    // redist454_i_shl_i_i_i_i_i77_i_35_c_compstr999_vt_select_28_b_1(DELAY,28682)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist454_i_shl_i_i_i_i_i77_i_35_c_compstr999_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_35_c_compstr999_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_35_c_compstr999_vt_join(BITJOIN,9207)@83
    assign i_shl_i_i_i_i_i77_i_35_c_compstr999_vt_join_q = {redist454_i_shl_i_i_i_i_i77_i_35_c_compstr999_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma(CHAINMULTADD,28154)@77 + 5
    // out q@83
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ah[0] <= redist841_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_71_tpl_69_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ah[1] <= redist840_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_70_tpl_69_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ch[0] <= redist587_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_71_tpl_69_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ch[1] <= redist586_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_70_tpl_69_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000(ADD,8450)@83
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compstr995_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compstr997_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compstr996_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_35_c_compstr999_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_35_c_compstr999_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_o[33:0];

    // rightShiftStage0_uid17108_dupName_139_i_unnamed_c_compstr0_shift_x(MUX,17107)@83
    assign rightShiftStage0_uid17108_dupName_139_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17108_dupName_139_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_q or rightShiftStage0Idx1_uid17106_dupName_139_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17108_dupName_139_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17108_dupName_139_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_q;
            1'b1 : rightShiftStage0_uid17108_dupName_139_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17106_dupName_139_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17108_dupName_139_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17113_dupName_139_i_unnamed_c_compstr0_shift_x(MUX,17112)@83
    assign rightShiftStage1_uid17113_dupName_139_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17113_dupName_139_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17108_dupName_139_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17111_dupName_139_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17113_dupName_139_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17113_dupName_139_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17108_dupName_139_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17113_dupName_139_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17111_dupName_139_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17113_dupName_139_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17118_dupName_139_i_unnamed_c_compstr0_shift_x(MUX,17117)@83
    assign rightShiftStage2_uid17118_dupName_139_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17118_dupName_139_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17113_dupName_139_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17116_dupName_139_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17118_dupName_139_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17118_dupName_139_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17113_dupName_139_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17118_dupName_139_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17116_dupName_139_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17118_dupName_139_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1001_vt_select_20(BITSELECT,9805)@83
    assign i_unnamed_c_compstr1001_vt_select_20_b = rightShiftStage2_uid17118_dupName_139_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1001_vt_join(BITJOIN,9804)@83
    assign i_unnamed_c_compstr1001_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1001_vt_select_20_b};

    // i_conv_i_i_i_i97_i_35_c_compstr1002_sel_x(BITSELECT,3512)@83
    assign i_conv_i_i_i_i97_i_35_c_compstr1002_sel_x_b = i_unnamed_c_compstr1001_vt_join_q[15:0];

    // redist1224_i_conv_i_i_i_i97_i_35_c_compstr1002_sel_x_b_1(DELAY,29452)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1224_i_conv_i_i_i_i97_i_35_c_compstr1002_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_35_c_compstr1002_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17127_dupName_140_i_unnamed_c_compstr0_shift_x(BITSELECT,17126)@83
    assign rightShiftStage1Idx1Rng8_uid17127_dupName_140_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17126_dupName_140_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17129_dupName_140_i_unnamed_c_compstr0_shift_x(BITJOIN,17128)@83
    assign rightShiftStage1Idx1_uid17129_dupName_140_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17127_dupName_140_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17122_dupName_140_i_unnamed_c_compstr0_shift_x(BITSELECT,17121)@83
    assign rightShiftStage0Idx1Rng4_uid17122_dupName_140_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_q[33:4];

    // rightShiftStage0Idx1_uid17124_dupName_140_i_unnamed_c_compstr0_shift_x(BITJOIN,17123)@83
    assign rightShiftStage0Idx1_uid17124_dupName_140_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17122_dupName_140_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17126_dupName_140_i_unnamed_c_compstr0_shift_x(MUX,17125)@83
    assign rightShiftStage0_uid17126_dupName_140_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17126_dupName_140_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_q or rightShiftStage0Idx1_uid17124_dupName_140_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17126_dupName_140_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17126_dupName_140_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compstr1000_q;
            1'b1 : rightShiftStage0_uid17126_dupName_140_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17124_dupName_140_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17126_dupName_140_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17131_dupName_140_i_unnamed_c_compstr0_shift_x(MUX,17130)@83
    assign rightShiftStage1_uid17131_dupName_140_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17131_dupName_140_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17126_dupName_140_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17129_dupName_140_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17131_dupName_140_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17131_dupName_140_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17126_dupName_140_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17131_dupName_140_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17129_dupName_140_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17131_dupName_140_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1003_vt_select_21(BITSELECT,9808)@83
    assign i_unnamed_c_compstr1003_vt_select_21_b = rightShiftStage1_uid17131_dupName_140_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1003_vt_join(BITJOIN,9807)@83
    assign i_unnamed_c_compstr1003_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1003_vt_select_21_b};

    // i_unnamed_c_compstr1004_sel_x(BITSELECT,6035)@83
    assign i_unnamed_c_compstr1004_sel_x_b = i_unnamed_c_compstr1003_vt_join_q[15:0];

    // i_unnamed_c_compstr1005_BitSelect_for_a(BITSELECT,27459)@83
    assign i_unnamed_c_compstr1005_BitSelect_for_a_b = i_unnamed_c_compstr1004_sel_x_b[0:0];

    // i_unnamed_c_compstr1005_join(BITJOIN,27460)@83
    assign i_unnamed_c_compstr1005_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1005_BitSelect_for_a_b};

    // i_unnamed_c_compstr1005_vt_select_0(BITSELECT,9813)@83
    assign i_unnamed_c_compstr1005_vt_select_0_b = i_unnamed_c_compstr1005_join_q[0:0];

    // redist255_i_unnamed_c_compstr1005_vt_select_0_b_1(DELAY,28483)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist255_i_unnamed_c_compstr1005_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1005_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1005_vt_join(BITJOIN,9812)@84
    assign i_unnamed_c_compstr1005_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist255_i_unnamed_c_compstr1005_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_35_c_compstr1006(ADD,6907)@84
    assign i_add_i_i_i_i_i126_i_35_c_compstr1006_a = {1'b0, i_unnamed_c_compstr1005_vt_join_q};
    assign i_add_i_i_i_i_i126_i_35_c_compstr1006_b = {1'b0, redist1224_i_conv_i_i_i_i97_i_35_c_compstr1002_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_35_c_compstr1006_o = $unsigned(i_add_i_i_i_i_i126_i_35_c_compstr1006_a) + $unsigned(i_add_i_i_i_i_i126_i_35_c_compstr1006_b);
    assign i_add_i_i_i_i_i126_i_35_c_compstr1006_q = i_add_i_i_i_i_i126_i_35_c_compstr1006_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_35_c_compstr1006_sel_x(BITSELECT,2101)@84
    assign bgTrunc_i_add_i_i_i_i_i126_i_35_c_compstr1006_sel_x_b = i_add_i_i_i_i_i126_i_35_c_compstr1006_q[15:0];

    // i_conv_i_i_i_i_i75_i277_36_c_compstr1026_sel_x(BITSELECT,3642)@84
    assign i_conv_i_i_i_i_i75_i277_36_c_compstr1026_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_35_c_compstr1006_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_36_c_compstr1026_vt_select_15(BITSELECT,7469)@84
    assign i_conv_i_i_i_i_i75_i277_36_c_compstr1026_vt_select_15_b = i_conv_i_i_i_i_i75_i277_36_c_compstr1026_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_36_c_compstr1026_vt_join(BITJOIN,7468)@84
    assign i_conv_i_i_i_i_i75_i277_36_c_compstr1026_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_36_c_compstr1026_vt_select_15_b};

    // leftShiftStage0_uid23882_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x(MUX,23881)@84
    assign leftShiftStage0_uid23882_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23882_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_36_c_compstr1026_vt_join_q or leftShiftStage0Idx1_uid23880_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23882_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23882_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_36_c_compstr1026_vt_join_q;
            1'b1 : leftShiftStage0_uid23882_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23880_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23882_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23887_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x(MUX,23886)@84
    assign leftShiftStage1_uid23887_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23887_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_s or leftShiftStage0_uid23882_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23885_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23887_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23887_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q = leftShiftStage0_uid23882_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23887_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23885_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23887_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23892_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x(MUX,23891)@84
    assign leftShiftStage2_uid23892_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23892_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_s or leftShiftStage1_uid23887_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23890_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23892_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23892_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q = leftShiftStage1_uid23887_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23892_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23890_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23892_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_36_c_compstr1027_vt_select_28(BITSELECT,9211)@84
    assign i_shl_i_i_i_i_i77_i_36_c_compstr1027_vt_select_28_b = leftShiftStage2_uid23892_i_shl_i_i_i_i_i77_i_36_c_compstr0_shift_x_q[28:13];

    // redist453_i_shl_i_i_i_i_i77_i_36_c_compstr1027_vt_select_28_b_1(DELAY,28681)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist453_i_shl_i_i_i_i_i77_i_36_c_compstr1027_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_36_c_compstr1027_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_36_c_compstr1027_vt_join(BITJOIN,9210)@85
    assign i_shl_i_i_i_i_i77_i_36_c_compstr1027_vt_join_q = {redist453_i_shl_i_i_i_i_i77_i_36_c_compstr1027_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma(CHAINMULTADD,28155)@79 + 5
    // out q@85
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ah[0] <= redist843_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_73_tpl_71_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ah[1] <= redist842_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_72_tpl_71_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ch[0] <= redist589_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_73_tpl_71_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ch[1] <= redist588_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_72_tpl_71_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028(ADD,8451)@85
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compstr1023_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compstr1025_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compstr1024_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_36_c_compstr1027_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_36_c_compstr1027_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_o[33:0];

    // rightShiftStage0_uid17170_dupName_143_i_unnamed_c_compstr0_shift_x(MUX,17169)@85
    assign rightShiftStage0_uid17170_dupName_143_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17170_dupName_143_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_q or rightShiftStage0Idx1_uid17168_dupName_143_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17170_dupName_143_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17170_dupName_143_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_q;
            1'b1 : rightShiftStage0_uid17170_dupName_143_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17168_dupName_143_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17170_dupName_143_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17175_dupName_143_i_unnamed_c_compstr0_shift_x(MUX,17174)@85
    assign rightShiftStage1_uid17175_dupName_143_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17175_dupName_143_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17170_dupName_143_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17173_dupName_143_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17175_dupName_143_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17175_dupName_143_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17170_dupName_143_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17175_dupName_143_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17173_dupName_143_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17175_dupName_143_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17180_dupName_143_i_unnamed_c_compstr0_shift_x(MUX,17179)@85
    assign rightShiftStage2_uid17180_dupName_143_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17180_dupName_143_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17175_dupName_143_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17178_dupName_143_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17180_dupName_143_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17180_dupName_143_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17175_dupName_143_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17180_dupName_143_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17178_dupName_143_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17180_dupName_143_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1029_vt_select_20(BITSELECT,9827)@85
    assign i_unnamed_c_compstr1029_vt_select_20_b = rightShiftStage2_uid17180_dupName_143_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1029_vt_join(BITJOIN,9826)@85
    assign i_unnamed_c_compstr1029_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1029_vt_select_20_b};

    // i_conv_i_i_i_i97_i_36_c_compstr1030_sel_x(BITSELECT,3513)@85
    assign i_conv_i_i_i_i97_i_36_c_compstr1030_sel_x_b = i_unnamed_c_compstr1029_vt_join_q[15:0];

    // redist1223_i_conv_i_i_i_i97_i_36_c_compstr1030_sel_x_b_1(DELAY,29451)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1223_i_conv_i_i_i_i97_i_36_c_compstr1030_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_36_c_compstr1030_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17189_dupName_144_i_unnamed_c_compstr0_shift_x(BITSELECT,17188)@85
    assign rightShiftStage1Idx1Rng8_uid17189_dupName_144_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17188_dupName_144_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17191_dupName_144_i_unnamed_c_compstr0_shift_x(BITJOIN,17190)@85
    assign rightShiftStage1Idx1_uid17191_dupName_144_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17189_dupName_144_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17184_dupName_144_i_unnamed_c_compstr0_shift_x(BITSELECT,17183)@85
    assign rightShiftStage0Idx1Rng4_uid17184_dupName_144_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_q[33:4];

    // rightShiftStage0Idx1_uid17186_dupName_144_i_unnamed_c_compstr0_shift_x(BITJOIN,17185)@85
    assign rightShiftStage0Idx1_uid17186_dupName_144_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17184_dupName_144_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17188_dupName_144_i_unnamed_c_compstr0_shift_x(MUX,17187)@85
    assign rightShiftStage0_uid17188_dupName_144_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17188_dupName_144_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_q or rightShiftStage0Idx1_uid17186_dupName_144_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17188_dupName_144_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17188_dupName_144_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compstr1028_q;
            1'b1 : rightShiftStage0_uid17188_dupName_144_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17186_dupName_144_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17188_dupName_144_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17193_dupName_144_i_unnamed_c_compstr0_shift_x(MUX,17192)@85
    assign rightShiftStage1_uid17193_dupName_144_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17193_dupName_144_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17188_dupName_144_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17191_dupName_144_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17193_dupName_144_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17193_dupName_144_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17188_dupName_144_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17193_dupName_144_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17191_dupName_144_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17193_dupName_144_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1031_vt_select_21(BITSELECT,9830)@85
    assign i_unnamed_c_compstr1031_vt_select_21_b = rightShiftStage1_uid17193_dupName_144_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1031_vt_join(BITJOIN,9829)@85
    assign i_unnamed_c_compstr1031_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1031_vt_select_21_b};

    // i_unnamed_c_compstr1032_sel_x(BITSELECT,6037)@85
    assign i_unnamed_c_compstr1032_sel_x_b = i_unnamed_c_compstr1031_vt_join_q[15:0];

    // i_unnamed_c_compstr1033_BitSelect_for_a(BITSELECT,27463)@85
    assign i_unnamed_c_compstr1033_BitSelect_for_a_b = i_unnamed_c_compstr1032_sel_x_b[0:0];

    // i_unnamed_c_compstr1033_join(BITJOIN,27464)@85
    assign i_unnamed_c_compstr1033_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1033_BitSelect_for_a_b};

    // i_unnamed_c_compstr1033_vt_select_0(BITSELECT,9835)@85
    assign i_unnamed_c_compstr1033_vt_select_0_b = i_unnamed_c_compstr1033_join_q[0:0];

    // redist253_i_unnamed_c_compstr1033_vt_select_0_b_1(DELAY,28481)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist253_i_unnamed_c_compstr1033_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1033_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1033_vt_join(BITJOIN,9834)@86
    assign i_unnamed_c_compstr1033_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist253_i_unnamed_c_compstr1033_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_36_c_compstr1034(ADD,6908)@86
    assign i_add_i_i_i_i_i126_i_36_c_compstr1034_a = {1'b0, i_unnamed_c_compstr1033_vt_join_q};
    assign i_add_i_i_i_i_i126_i_36_c_compstr1034_b = {1'b0, redist1223_i_conv_i_i_i_i97_i_36_c_compstr1030_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_36_c_compstr1034_o = $unsigned(i_add_i_i_i_i_i126_i_36_c_compstr1034_a) + $unsigned(i_add_i_i_i_i_i126_i_36_c_compstr1034_b);
    assign i_add_i_i_i_i_i126_i_36_c_compstr1034_q = i_add_i_i_i_i_i126_i_36_c_compstr1034_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_36_c_compstr1034_sel_x(BITSELECT,2102)@86
    assign bgTrunc_i_add_i_i_i_i_i126_i_36_c_compstr1034_sel_x_b = i_add_i_i_i_i_i126_i_36_c_compstr1034_q[15:0];

    // i_conv_i_i_i_i_i75_i277_37_c_compstr1054_sel_x(BITSELECT,3643)@86
    assign i_conv_i_i_i_i_i75_i277_37_c_compstr1054_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_36_c_compstr1034_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_37_c_compstr1054_vt_select_15(BITSELECT,7473)@86
    assign i_conv_i_i_i_i_i75_i277_37_c_compstr1054_vt_select_15_b = i_conv_i_i_i_i_i75_i277_37_c_compstr1054_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_37_c_compstr1054_vt_join(BITJOIN,7472)@86
    assign i_conv_i_i_i_i_i75_i277_37_c_compstr1054_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_37_c_compstr1054_vt_select_15_b};

    // leftShiftStage0_uid23900_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x(MUX,23899)@86
    assign leftShiftStage0_uid23900_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23900_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_37_c_compstr1054_vt_join_q or leftShiftStage0Idx1_uid23898_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23900_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23900_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_37_c_compstr1054_vt_join_q;
            1'b1 : leftShiftStage0_uid23900_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23898_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23900_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23905_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x(MUX,23904)@86
    assign leftShiftStage1_uid23905_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23905_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_s or leftShiftStage0_uid23900_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23903_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23905_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23905_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q = leftShiftStage0_uid23900_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23905_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23903_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23905_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23910_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x(MUX,23909)@86
    assign leftShiftStage2_uid23910_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23910_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_s or leftShiftStage1_uid23905_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23908_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23910_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23910_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q = leftShiftStage1_uid23905_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23910_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23908_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23910_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_37_c_compstr1055_vt_select_28(BITSELECT,9214)@86
    assign i_shl_i_i_i_i_i77_i_37_c_compstr1055_vt_select_28_b = leftShiftStage2_uid23910_i_shl_i_i_i_i_i77_i_37_c_compstr0_shift_x_q[28:13];

    // redist452_i_shl_i_i_i_i_i77_i_37_c_compstr1055_vt_select_28_b_1(DELAY,28680)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist452_i_shl_i_i_i_i_i77_i_37_c_compstr1055_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_37_c_compstr1055_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_37_c_compstr1055_vt_join(BITJOIN,9213)@87
    assign i_shl_i_i_i_i_i77_i_37_c_compstr1055_vt_join_q = {redist452_i_shl_i_i_i_i_i77_i_37_c_compstr1055_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma(CHAINMULTADD,28156)@81 + 5
    // out q@87
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ah[0] <= redist845_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_75_tpl_73_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ah[1] <= redist844_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_74_tpl_73_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ch[0] <= redist591_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_75_tpl_73_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ch[1] <= redist590_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_74_tpl_73_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056(ADD,8452)@87
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compstr1051_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compstr1053_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compstr1052_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_37_c_compstr1055_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_37_c_compstr1055_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_o[33:0];

    // rightShiftStage0_uid17232_dupName_147_i_unnamed_c_compstr0_shift_x(MUX,17231)@87
    assign rightShiftStage0_uid17232_dupName_147_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17232_dupName_147_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_q or rightShiftStage0Idx1_uid17230_dupName_147_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17232_dupName_147_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17232_dupName_147_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_q;
            1'b1 : rightShiftStage0_uid17232_dupName_147_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17230_dupName_147_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17232_dupName_147_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17237_dupName_147_i_unnamed_c_compstr0_shift_x(MUX,17236)@87
    assign rightShiftStage1_uid17237_dupName_147_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17237_dupName_147_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17232_dupName_147_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17235_dupName_147_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17237_dupName_147_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17237_dupName_147_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17232_dupName_147_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17237_dupName_147_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17235_dupName_147_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17237_dupName_147_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17242_dupName_147_i_unnamed_c_compstr0_shift_x(MUX,17241)@87
    assign rightShiftStage2_uid17242_dupName_147_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17242_dupName_147_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17237_dupName_147_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17240_dupName_147_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17242_dupName_147_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17242_dupName_147_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17237_dupName_147_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17242_dupName_147_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17240_dupName_147_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17242_dupName_147_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1057_vt_select_20(BITSELECT,9849)@87
    assign i_unnamed_c_compstr1057_vt_select_20_b = rightShiftStage2_uid17242_dupName_147_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1057_vt_join(BITJOIN,9848)@87
    assign i_unnamed_c_compstr1057_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1057_vt_select_20_b};

    // i_conv_i_i_i_i97_i_37_c_compstr1058_sel_x(BITSELECT,3514)@87
    assign i_conv_i_i_i_i97_i_37_c_compstr1058_sel_x_b = i_unnamed_c_compstr1057_vt_join_q[15:0];

    // redist1222_i_conv_i_i_i_i97_i_37_c_compstr1058_sel_x_b_1(DELAY,29450)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1222_i_conv_i_i_i_i97_i_37_c_compstr1058_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_37_c_compstr1058_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17251_dupName_148_i_unnamed_c_compstr0_shift_x(BITSELECT,17250)@87
    assign rightShiftStage1Idx1Rng8_uid17251_dupName_148_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17250_dupName_148_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17253_dupName_148_i_unnamed_c_compstr0_shift_x(BITJOIN,17252)@87
    assign rightShiftStage1Idx1_uid17253_dupName_148_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17251_dupName_148_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17246_dupName_148_i_unnamed_c_compstr0_shift_x(BITSELECT,17245)@87
    assign rightShiftStage0Idx1Rng4_uid17246_dupName_148_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_q[33:4];

    // rightShiftStage0Idx1_uid17248_dupName_148_i_unnamed_c_compstr0_shift_x(BITJOIN,17247)@87
    assign rightShiftStage0Idx1_uid17248_dupName_148_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17246_dupName_148_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17250_dupName_148_i_unnamed_c_compstr0_shift_x(MUX,17249)@87
    assign rightShiftStage0_uid17250_dupName_148_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17250_dupName_148_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_q or rightShiftStage0Idx1_uid17248_dupName_148_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17250_dupName_148_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17250_dupName_148_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compstr1056_q;
            1'b1 : rightShiftStage0_uid17250_dupName_148_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17248_dupName_148_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17250_dupName_148_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17255_dupName_148_i_unnamed_c_compstr0_shift_x(MUX,17254)@87
    assign rightShiftStage1_uid17255_dupName_148_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17255_dupName_148_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17250_dupName_148_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17253_dupName_148_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17255_dupName_148_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17255_dupName_148_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17250_dupName_148_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17255_dupName_148_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17253_dupName_148_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17255_dupName_148_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1059_vt_select_21(BITSELECT,9852)@87
    assign i_unnamed_c_compstr1059_vt_select_21_b = rightShiftStage1_uid17255_dupName_148_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1059_vt_join(BITJOIN,9851)@87
    assign i_unnamed_c_compstr1059_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1059_vt_select_21_b};

    // i_unnamed_c_compstr1060_sel_x(BITSELECT,6039)@87
    assign i_unnamed_c_compstr1060_sel_x_b = i_unnamed_c_compstr1059_vt_join_q[15:0];

    // i_unnamed_c_compstr1061_BitSelect_for_a(BITSELECT,27467)@87
    assign i_unnamed_c_compstr1061_BitSelect_for_a_b = i_unnamed_c_compstr1060_sel_x_b[0:0];

    // i_unnamed_c_compstr1061_join(BITJOIN,27468)@87
    assign i_unnamed_c_compstr1061_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1061_BitSelect_for_a_b};

    // i_unnamed_c_compstr1061_vt_select_0(BITSELECT,9860)@87
    assign i_unnamed_c_compstr1061_vt_select_0_b = i_unnamed_c_compstr1061_join_q[0:0];

    // redist251_i_unnamed_c_compstr1061_vt_select_0_b_1(DELAY,28479)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist251_i_unnamed_c_compstr1061_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1061_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1061_vt_join(BITJOIN,9859)@88
    assign i_unnamed_c_compstr1061_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist251_i_unnamed_c_compstr1061_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_37_c_compstr1062(ADD,6909)@88
    assign i_add_i_i_i_i_i126_i_37_c_compstr1062_a = {1'b0, i_unnamed_c_compstr1061_vt_join_q};
    assign i_add_i_i_i_i_i126_i_37_c_compstr1062_b = {1'b0, redist1222_i_conv_i_i_i_i97_i_37_c_compstr1058_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_37_c_compstr1062_o = $unsigned(i_add_i_i_i_i_i126_i_37_c_compstr1062_a) + $unsigned(i_add_i_i_i_i_i126_i_37_c_compstr1062_b);
    assign i_add_i_i_i_i_i126_i_37_c_compstr1062_q = i_add_i_i_i_i_i126_i_37_c_compstr1062_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_37_c_compstr1062_sel_x(BITSELECT,2103)@88
    assign bgTrunc_i_add_i_i_i_i_i126_i_37_c_compstr1062_sel_x_b = i_add_i_i_i_i_i126_i_37_c_compstr1062_q[15:0];

    // i_conv_i_i_i_i_i75_i277_38_c_compstr1082_sel_x(BITSELECT,3644)@88
    assign i_conv_i_i_i_i_i75_i277_38_c_compstr1082_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_37_c_compstr1062_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_38_c_compstr1082_vt_select_15(BITSELECT,7477)@88
    assign i_conv_i_i_i_i_i75_i277_38_c_compstr1082_vt_select_15_b = i_conv_i_i_i_i_i75_i277_38_c_compstr1082_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_38_c_compstr1082_vt_join(BITJOIN,7476)@88
    assign i_conv_i_i_i_i_i75_i277_38_c_compstr1082_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_38_c_compstr1082_vt_select_15_b};

    // leftShiftStage0_uid23918_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x(MUX,23917)@88
    assign leftShiftStage0_uid23918_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23918_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_38_c_compstr1082_vt_join_q or leftShiftStage0Idx1_uid23916_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23918_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23918_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_38_c_compstr1082_vt_join_q;
            1'b1 : leftShiftStage0_uid23918_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23916_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23918_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23923_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x(MUX,23922)@88
    assign leftShiftStage1_uid23923_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23923_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_s or leftShiftStage0_uid23918_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23921_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23923_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23923_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q = leftShiftStage0_uid23918_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23923_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23921_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23923_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23928_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x(MUX,23927)@88
    assign leftShiftStage2_uid23928_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23928_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_s or leftShiftStage1_uid23923_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23926_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23928_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23928_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q = leftShiftStage1_uid23923_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23928_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23926_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23928_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_38_c_compstr1083_vt_select_28(BITSELECT,9217)@88
    assign i_shl_i_i_i_i_i77_i_38_c_compstr1083_vt_select_28_b = leftShiftStage2_uid23928_i_shl_i_i_i_i_i77_i_38_c_compstr0_shift_x_q[28:13];

    // redist451_i_shl_i_i_i_i_i77_i_38_c_compstr1083_vt_select_28_b_1(DELAY,28679)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist451_i_shl_i_i_i_i_i77_i_38_c_compstr1083_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_38_c_compstr1083_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_38_c_compstr1083_vt_join(BITJOIN,9216)@89
    assign i_shl_i_i_i_i_i77_i_38_c_compstr1083_vt_join_q = {redist451_i_shl_i_i_i_i_i77_i_38_c_compstr1083_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma(CHAINMULTADD,28157)@83 + 5
    // out q@89
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ah[0] <= redist847_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_77_tpl_75_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ah[1] <= redist846_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_76_tpl_75_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ch[0] <= redist593_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_77_tpl_75_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ch[1] <= redist592_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_76_tpl_75_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084(ADD,8453)@89
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compstr1079_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compstr1081_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compstr1080_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_38_c_compstr1083_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_38_c_compstr1083_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_o[33:0];

    // rightShiftStage0_uid17294_dupName_151_i_unnamed_c_compstr0_shift_x(MUX,17293)@89
    assign rightShiftStage0_uid17294_dupName_151_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17294_dupName_151_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_q or rightShiftStage0Idx1_uid17292_dupName_151_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17294_dupName_151_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17294_dupName_151_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_q;
            1'b1 : rightShiftStage0_uid17294_dupName_151_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17292_dupName_151_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17294_dupName_151_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17299_dupName_151_i_unnamed_c_compstr0_shift_x(MUX,17298)@89
    assign rightShiftStage1_uid17299_dupName_151_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17299_dupName_151_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17294_dupName_151_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17297_dupName_151_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17299_dupName_151_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17299_dupName_151_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17294_dupName_151_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17299_dupName_151_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17297_dupName_151_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17299_dupName_151_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17304_dupName_151_i_unnamed_c_compstr0_shift_x(MUX,17303)@89
    assign rightShiftStage2_uid17304_dupName_151_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17304_dupName_151_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17299_dupName_151_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17302_dupName_151_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17304_dupName_151_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17304_dupName_151_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17299_dupName_151_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17304_dupName_151_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17302_dupName_151_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17304_dupName_151_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1085_vt_select_20(BITSELECT,9877)@89
    assign i_unnamed_c_compstr1085_vt_select_20_b = rightShiftStage2_uid17304_dupName_151_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1085_vt_join(BITJOIN,9876)@89
    assign i_unnamed_c_compstr1085_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1085_vt_select_20_b};

    // i_conv_i_i_i_i97_i_38_c_compstr1086_sel_x(BITSELECT,3515)@89
    assign i_conv_i_i_i_i97_i_38_c_compstr1086_sel_x_b = i_unnamed_c_compstr1085_vt_join_q[15:0];

    // redist1221_i_conv_i_i_i_i97_i_38_c_compstr1086_sel_x_b_1(DELAY,29449)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1221_i_conv_i_i_i_i97_i_38_c_compstr1086_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_38_c_compstr1086_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17313_dupName_152_i_unnamed_c_compstr0_shift_x(BITSELECT,17312)@89
    assign rightShiftStage1Idx1Rng8_uid17313_dupName_152_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17312_dupName_152_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17315_dupName_152_i_unnamed_c_compstr0_shift_x(BITJOIN,17314)@89
    assign rightShiftStage1Idx1_uid17315_dupName_152_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17313_dupName_152_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17308_dupName_152_i_unnamed_c_compstr0_shift_x(BITSELECT,17307)@89
    assign rightShiftStage0Idx1Rng4_uid17308_dupName_152_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_q[33:4];

    // rightShiftStage0Idx1_uid17310_dupName_152_i_unnamed_c_compstr0_shift_x(BITJOIN,17309)@89
    assign rightShiftStage0Idx1_uid17310_dupName_152_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17308_dupName_152_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17312_dupName_152_i_unnamed_c_compstr0_shift_x(MUX,17311)@89
    assign rightShiftStage0_uid17312_dupName_152_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17312_dupName_152_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_q or rightShiftStage0Idx1_uid17310_dupName_152_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17312_dupName_152_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17312_dupName_152_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compstr1084_q;
            1'b1 : rightShiftStage0_uid17312_dupName_152_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17310_dupName_152_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17312_dupName_152_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17317_dupName_152_i_unnamed_c_compstr0_shift_x(MUX,17316)@89
    assign rightShiftStage1_uid17317_dupName_152_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17317_dupName_152_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17312_dupName_152_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17315_dupName_152_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17317_dupName_152_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17317_dupName_152_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17312_dupName_152_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17317_dupName_152_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17315_dupName_152_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17317_dupName_152_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1087_vt_select_21(BITSELECT,9880)@89
    assign i_unnamed_c_compstr1087_vt_select_21_b = rightShiftStage1_uid17317_dupName_152_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1087_vt_join(BITJOIN,9879)@89
    assign i_unnamed_c_compstr1087_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1087_vt_select_21_b};

    // i_unnamed_c_compstr1088_sel_x(BITSELECT,6042)@89
    assign i_unnamed_c_compstr1088_sel_x_b = i_unnamed_c_compstr1087_vt_join_q[15:0];

    // i_unnamed_c_compstr1089_BitSelect_for_a(BITSELECT,27471)@89
    assign i_unnamed_c_compstr1089_BitSelect_for_a_b = i_unnamed_c_compstr1088_sel_x_b[0:0];

    // i_unnamed_c_compstr1089_join(BITJOIN,27472)@89
    assign i_unnamed_c_compstr1089_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1089_BitSelect_for_a_b};

    // i_unnamed_c_compstr1089_vt_select_0(BITSELECT,9885)@89
    assign i_unnamed_c_compstr1089_vt_select_0_b = i_unnamed_c_compstr1089_join_q[0:0];

    // redist249_i_unnamed_c_compstr1089_vt_select_0_b_1(DELAY,28477)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist249_i_unnamed_c_compstr1089_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1089_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1089_vt_join(BITJOIN,9884)@90
    assign i_unnamed_c_compstr1089_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist249_i_unnamed_c_compstr1089_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_38_c_compstr1090(ADD,6910)@90
    assign i_add_i_i_i_i_i126_i_38_c_compstr1090_a = {1'b0, i_unnamed_c_compstr1089_vt_join_q};
    assign i_add_i_i_i_i_i126_i_38_c_compstr1090_b = {1'b0, redist1221_i_conv_i_i_i_i97_i_38_c_compstr1086_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_38_c_compstr1090_o = $unsigned(i_add_i_i_i_i_i126_i_38_c_compstr1090_a) + $unsigned(i_add_i_i_i_i_i126_i_38_c_compstr1090_b);
    assign i_add_i_i_i_i_i126_i_38_c_compstr1090_q = i_add_i_i_i_i_i126_i_38_c_compstr1090_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_38_c_compstr1090_sel_x(BITSELECT,2104)@90
    assign bgTrunc_i_add_i_i_i_i_i126_i_38_c_compstr1090_sel_x_b = i_add_i_i_i_i_i126_i_38_c_compstr1090_q[15:0];

    // i_conv_i_i_i_i_i75_i277_39_c_compstr1110_sel_x(BITSELECT,3645)@90
    assign i_conv_i_i_i_i_i75_i277_39_c_compstr1110_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_38_c_compstr1090_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_39_c_compstr1110_vt_select_15(BITSELECT,7481)@90
    assign i_conv_i_i_i_i_i75_i277_39_c_compstr1110_vt_select_15_b = i_conv_i_i_i_i_i75_i277_39_c_compstr1110_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_39_c_compstr1110_vt_join(BITJOIN,7480)@90
    assign i_conv_i_i_i_i_i75_i277_39_c_compstr1110_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_39_c_compstr1110_vt_select_15_b};

    // leftShiftStage0_uid23936_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x(MUX,23935)@90
    assign leftShiftStage0_uid23936_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23936_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_39_c_compstr1110_vt_join_q or leftShiftStage0Idx1_uid23934_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23936_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23936_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_39_c_compstr1110_vt_join_q;
            1'b1 : leftShiftStage0_uid23936_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23934_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23936_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23941_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x(MUX,23940)@90
    assign leftShiftStage1_uid23941_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23941_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_s or leftShiftStage0_uid23936_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23939_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23941_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23941_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q = leftShiftStage0_uid23936_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23941_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23939_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23941_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23946_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x(MUX,23945)@90
    assign leftShiftStage2_uid23946_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23946_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_s or leftShiftStage1_uid23941_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23944_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23946_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23946_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q = leftShiftStage1_uid23941_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23946_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23944_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23946_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_39_c_compstr1111_vt_select_28(BITSELECT,9220)@90
    assign i_shl_i_i_i_i_i77_i_39_c_compstr1111_vt_select_28_b = leftShiftStage2_uid23946_i_shl_i_i_i_i_i77_i_39_c_compstr0_shift_x_q[28:13];

    // redist450_i_shl_i_i_i_i_i77_i_39_c_compstr1111_vt_select_28_b_1(DELAY,28678)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist450_i_shl_i_i_i_i_i77_i_39_c_compstr1111_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_39_c_compstr1111_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_39_c_compstr1111_vt_join(BITJOIN,9219)@91
    assign i_shl_i_i_i_i_i77_i_39_c_compstr1111_vt_join_q = {redist450_i_shl_i_i_i_i_i77_i_39_c_compstr1111_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma(CHAINMULTADD,28158)@85 + 5
    // out q@91
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ah[0] <= redist849_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_79_tpl_77_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ah[1] <= redist848_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_78_tpl_77_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ch[0] <= redist595_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_79_tpl_77_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ch[1] <= redist594_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_78_tpl_77_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112(ADD,8454)@91
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compstr1107_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compstr1109_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compstr1108_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_39_c_compstr1111_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_39_c_compstr1111_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_o[33:0];

    // rightShiftStage0_uid17356_dupName_155_i_unnamed_c_compstr0_shift_x(MUX,17355)@91
    assign rightShiftStage0_uid17356_dupName_155_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17356_dupName_155_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_q or rightShiftStage0Idx1_uid17354_dupName_155_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17356_dupName_155_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17356_dupName_155_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_q;
            1'b1 : rightShiftStage0_uid17356_dupName_155_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17354_dupName_155_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17356_dupName_155_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17361_dupName_155_i_unnamed_c_compstr0_shift_x(MUX,17360)@91
    assign rightShiftStage1_uid17361_dupName_155_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17361_dupName_155_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17356_dupName_155_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17359_dupName_155_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17361_dupName_155_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17361_dupName_155_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17356_dupName_155_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17361_dupName_155_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17359_dupName_155_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17361_dupName_155_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17366_dupName_155_i_unnamed_c_compstr0_shift_x(MUX,17365)@91
    assign rightShiftStage2_uid17366_dupName_155_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17366_dupName_155_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17361_dupName_155_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17364_dupName_155_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17366_dupName_155_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17366_dupName_155_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17361_dupName_155_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17366_dupName_155_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17364_dupName_155_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17366_dupName_155_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1113_vt_select_20(BITSELECT,9904)@91
    assign i_unnamed_c_compstr1113_vt_select_20_b = rightShiftStage2_uid17366_dupName_155_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1113_vt_join(BITJOIN,9903)@91
    assign i_unnamed_c_compstr1113_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1113_vt_select_20_b};

    // i_conv_i_i_i_i97_i_39_c_compstr1114_sel_x(BITSELECT,3516)@91
    assign i_conv_i_i_i_i97_i_39_c_compstr1114_sel_x_b = i_unnamed_c_compstr1113_vt_join_q[15:0];

    // redist1220_i_conv_i_i_i_i97_i_39_c_compstr1114_sel_x_b_1(DELAY,29448)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1220_i_conv_i_i_i_i97_i_39_c_compstr1114_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_39_c_compstr1114_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17375_dupName_156_i_unnamed_c_compstr0_shift_x(BITSELECT,17374)@91
    assign rightShiftStage1Idx1Rng8_uid17375_dupName_156_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17374_dupName_156_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17377_dupName_156_i_unnamed_c_compstr0_shift_x(BITJOIN,17376)@91
    assign rightShiftStage1Idx1_uid17377_dupName_156_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17375_dupName_156_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17370_dupName_156_i_unnamed_c_compstr0_shift_x(BITSELECT,17369)@91
    assign rightShiftStage0Idx1Rng4_uid17370_dupName_156_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_q[33:4];

    // rightShiftStage0Idx1_uid17372_dupName_156_i_unnamed_c_compstr0_shift_x(BITJOIN,17371)@91
    assign rightShiftStage0Idx1_uid17372_dupName_156_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17370_dupName_156_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17374_dupName_156_i_unnamed_c_compstr0_shift_x(MUX,17373)@91
    assign rightShiftStage0_uid17374_dupName_156_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17374_dupName_156_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_q or rightShiftStage0Idx1_uid17372_dupName_156_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17374_dupName_156_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17374_dupName_156_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compstr1112_q;
            1'b1 : rightShiftStage0_uid17374_dupName_156_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17372_dupName_156_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17374_dupName_156_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17379_dupName_156_i_unnamed_c_compstr0_shift_x(MUX,17378)@91
    assign rightShiftStage1_uid17379_dupName_156_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17379_dupName_156_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17374_dupName_156_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17377_dupName_156_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17379_dupName_156_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17379_dupName_156_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17374_dupName_156_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17379_dupName_156_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17377_dupName_156_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17379_dupName_156_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1115_vt_select_21(BITSELECT,9907)@91
    assign i_unnamed_c_compstr1115_vt_select_21_b = rightShiftStage1_uid17379_dupName_156_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1115_vt_join(BITJOIN,9906)@91
    assign i_unnamed_c_compstr1115_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1115_vt_select_21_b};

    // i_unnamed_c_compstr1116_sel_x(BITSELECT,6044)@91
    assign i_unnamed_c_compstr1116_sel_x_b = i_unnamed_c_compstr1115_vt_join_q[15:0];

    // i_unnamed_c_compstr1117_BitSelect_for_a(BITSELECT,27477)@91
    assign i_unnamed_c_compstr1117_BitSelect_for_a_b = i_unnamed_c_compstr1116_sel_x_b[0:0];

    // i_unnamed_c_compstr1117_join(BITJOIN,27478)@91
    assign i_unnamed_c_compstr1117_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1117_BitSelect_for_a_b};

    // i_unnamed_c_compstr1117_vt_select_0(BITSELECT,9912)@91
    assign i_unnamed_c_compstr1117_vt_select_0_b = i_unnamed_c_compstr1117_join_q[0:0];

    // redist246_i_unnamed_c_compstr1117_vt_select_0_b_1(DELAY,28474)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist246_i_unnamed_c_compstr1117_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1117_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1117_vt_join(BITJOIN,9911)@92
    assign i_unnamed_c_compstr1117_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist246_i_unnamed_c_compstr1117_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_39_c_compstr1118(ADD,6911)@92
    assign i_add_i_i_i_i_i126_i_39_c_compstr1118_a = {1'b0, i_unnamed_c_compstr1117_vt_join_q};
    assign i_add_i_i_i_i_i126_i_39_c_compstr1118_b = {1'b0, redist1220_i_conv_i_i_i_i97_i_39_c_compstr1114_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_39_c_compstr1118_o = $unsigned(i_add_i_i_i_i_i126_i_39_c_compstr1118_a) + $unsigned(i_add_i_i_i_i_i126_i_39_c_compstr1118_b);
    assign i_add_i_i_i_i_i126_i_39_c_compstr1118_q = i_add_i_i_i_i_i126_i_39_c_compstr1118_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_39_c_compstr1118_sel_x(BITSELECT,2105)@92
    assign bgTrunc_i_add_i_i_i_i_i126_i_39_c_compstr1118_sel_x_b = i_add_i_i_i_i_i126_i_39_c_compstr1118_q[15:0];

    // i_conv_i_i_i_i_i75_i277_40_c_compstr1138_sel_x(BITSELECT,3647)@92
    assign i_conv_i_i_i_i_i75_i277_40_c_compstr1138_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_39_c_compstr1118_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_40_c_compstr1138_vt_select_15(BITSELECT,7489)@92
    assign i_conv_i_i_i_i_i75_i277_40_c_compstr1138_vt_select_15_b = i_conv_i_i_i_i_i75_i277_40_c_compstr1138_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_40_c_compstr1138_vt_join(BITJOIN,7488)@92
    assign i_conv_i_i_i_i_i75_i277_40_c_compstr1138_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_40_c_compstr1138_vt_select_15_b};

    // leftShiftStage0_uid23972_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x(MUX,23971)@92
    assign leftShiftStage0_uid23972_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23972_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_40_c_compstr1138_vt_join_q or leftShiftStage0Idx1_uid23970_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23972_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23972_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_40_c_compstr1138_vt_join_q;
            1'b1 : leftShiftStage0_uid23972_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23970_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23972_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23977_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x(MUX,23976)@92
    assign leftShiftStage1_uid23977_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23977_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_s or leftShiftStage0_uid23972_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23975_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23977_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23977_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q = leftShiftStage0_uid23972_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23977_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23975_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23977_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23982_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x(MUX,23981)@92
    assign leftShiftStage2_uid23982_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23982_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_s or leftShiftStage1_uid23977_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23980_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23982_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23982_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q = leftShiftStage1_uid23977_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23982_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23980_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23982_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_40_c_compstr1139_vt_select_28(BITSELECT,9226)@92
    assign i_shl_i_i_i_i_i77_i_40_c_compstr1139_vt_select_28_b = leftShiftStage2_uid23982_i_shl_i_i_i_i_i77_i_40_c_compstr0_shift_x_q[28:13];

    // redist448_i_shl_i_i_i_i_i77_i_40_c_compstr1139_vt_select_28_b_1(DELAY,28676)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist448_i_shl_i_i_i_i_i77_i_40_c_compstr1139_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_40_c_compstr1139_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_40_c_compstr1139_vt_join(BITJOIN,9225)@93
    assign i_shl_i_i_i_i_i77_i_40_c_compstr1139_vt_join_q = {redist448_i_shl_i_i_i_i_i77_i_40_c_compstr1139_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma(CHAINMULTADD,28160)@87 + 5
    // out q@93
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ah[0] <= redist851_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_81_tpl_79_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ah[1] <= redist850_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_80_tpl_79_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ch[0] <= redist597_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_81_tpl_79_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ch[1] <= redist596_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_80_tpl_79_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140(ADD,8456)@93
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compstr1135_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compstr1137_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compstr1136_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_40_c_compstr1139_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_40_c_compstr1139_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_o[33:0];

    // rightShiftStage0_uid17418_dupName_159_i_unnamed_c_compstr0_shift_x(MUX,17417)@93
    assign rightShiftStage0_uid17418_dupName_159_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17418_dupName_159_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_q or rightShiftStage0Idx1_uid17416_dupName_159_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17418_dupName_159_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17418_dupName_159_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_q;
            1'b1 : rightShiftStage0_uid17418_dupName_159_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17416_dupName_159_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17418_dupName_159_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17423_dupName_159_i_unnamed_c_compstr0_shift_x(MUX,17422)@93
    assign rightShiftStage1_uid17423_dupName_159_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17423_dupName_159_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17418_dupName_159_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17421_dupName_159_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17423_dupName_159_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17423_dupName_159_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17418_dupName_159_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17423_dupName_159_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17421_dupName_159_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17423_dupName_159_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17428_dupName_159_i_unnamed_c_compstr0_shift_x(MUX,17427)@93
    assign rightShiftStage2_uid17428_dupName_159_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17428_dupName_159_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17423_dupName_159_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17426_dupName_159_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17428_dupName_159_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17428_dupName_159_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17423_dupName_159_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17428_dupName_159_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17426_dupName_159_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17428_dupName_159_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1141_vt_select_20(BITSELECT,9926)@93
    assign i_unnamed_c_compstr1141_vt_select_20_b = rightShiftStage2_uid17428_dupName_159_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1141_vt_join(BITJOIN,9925)@93
    assign i_unnamed_c_compstr1141_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1141_vt_select_20_b};

    // i_conv_i_i_i_i97_i_40_c_compstr1142_sel_x(BITSELECT,3518)@93
    assign i_conv_i_i_i_i97_i_40_c_compstr1142_sel_x_b = i_unnamed_c_compstr1141_vt_join_q[15:0];

    // redist1218_i_conv_i_i_i_i97_i_40_c_compstr1142_sel_x_b_1(DELAY,29446)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1218_i_conv_i_i_i_i97_i_40_c_compstr1142_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_40_c_compstr1142_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17437_dupName_160_i_unnamed_c_compstr0_shift_x(BITSELECT,17436)@93
    assign rightShiftStage1Idx1Rng8_uid17437_dupName_160_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17436_dupName_160_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17439_dupName_160_i_unnamed_c_compstr0_shift_x(BITJOIN,17438)@93
    assign rightShiftStage1Idx1_uid17439_dupName_160_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17437_dupName_160_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17432_dupName_160_i_unnamed_c_compstr0_shift_x(BITSELECT,17431)@93
    assign rightShiftStage0Idx1Rng4_uid17432_dupName_160_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_q[33:4];

    // rightShiftStage0Idx1_uid17434_dupName_160_i_unnamed_c_compstr0_shift_x(BITJOIN,17433)@93
    assign rightShiftStage0Idx1_uid17434_dupName_160_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17432_dupName_160_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17436_dupName_160_i_unnamed_c_compstr0_shift_x(MUX,17435)@93
    assign rightShiftStage0_uid17436_dupName_160_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17436_dupName_160_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_q or rightShiftStage0Idx1_uid17434_dupName_160_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17436_dupName_160_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17436_dupName_160_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compstr1140_q;
            1'b1 : rightShiftStage0_uid17436_dupName_160_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17434_dupName_160_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17436_dupName_160_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17441_dupName_160_i_unnamed_c_compstr0_shift_x(MUX,17440)@93
    assign rightShiftStage1_uid17441_dupName_160_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17441_dupName_160_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17436_dupName_160_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17439_dupName_160_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17441_dupName_160_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17441_dupName_160_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17436_dupName_160_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17441_dupName_160_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17439_dupName_160_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17441_dupName_160_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1143_vt_select_21(BITSELECT,9929)@93
    assign i_unnamed_c_compstr1143_vt_select_21_b = rightShiftStage1_uid17441_dupName_160_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1143_vt_join(BITJOIN,9928)@93
    assign i_unnamed_c_compstr1143_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1143_vt_select_21_b};

    // i_unnamed_c_compstr1144_sel_x(BITSELECT,6046)@93
    assign i_unnamed_c_compstr1144_sel_x_b = i_unnamed_c_compstr1143_vt_join_q[15:0];

    // i_unnamed_c_compstr1145_BitSelect_for_a(BITSELECT,27481)@93
    assign i_unnamed_c_compstr1145_BitSelect_for_a_b = i_unnamed_c_compstr1144_sel_x_b[0:0];

    // i_unnamed_c_compstr1145_join(BITJOIN,27482)@93
    assign i_unnamed_c_compstr1145_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1145_BitSelect_for_a_b};

    // i_unnamed_c_compstr1145_vt_select_0(BITSELECT,9934)@93
    assign i_unnamed_c_compstr1145_vt_select_0_b = i_unnamed_c_compstr1145_join_q[0:0];

    // redist244_i_unnamed_c_compstr1145_vt_select_0_b_1(DELAY,28472)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist244_i_unnamed_c_compstr1145_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1145_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1145_vt_join(BITJOIN,9933)@94
    assign i_unnamed_c_compstr1145_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist244_i_unnamed_c_compstr1145_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_40_c_compstr1146(ADD,6913)@94
    assign i_add_i_i_i_i_i126_i_40_c_compstr1146_a = {1'b0, i_unnamed_c_compstr1145_vt_join_q};
    assign i_add_i_i_i_i_i126_i_40_c_compstr1146_b = {1'b0, redist1218_i_conv_i_i_i_i97_i_40_c_compstr1142_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_40_c_compstr1146_o = $unsigned(i_add_i_i_i_i_i126_i_40_c_compstr1146_a) + $unsigned(i_add_i_i_i_i_i126_i_40_c_compstr1146_b);
    assign i_add_i_i_i_i_i126_i_40_c_compstr1146_q = i_add_i_i_i_i_i126_i_40_c_compstr1146_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_40_c_compstr1146_sel_x(BITSELECT,2107)@94
    assign bgTrunc_i_add_i_i_i_i_i126_i_40_c_compstr1146_sel_x_b = i_add_i_i_i_i_i126_i_40_c_compstr1146_q[15:0];

    // i_conv_i_i_i_i_i75_i277_41_c_compstr1166_sel_x(BITSELECT,3648)@94
    assign i_conv_i_i_i_i_i75_i277_41_c_compstr1166_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_40_c_compstr1146_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_41_c_compstr1166_vt_select_15(BITSELECT,7493)@94
    assign i_conv_i_i_i_i_i75_i277_41_c_compstr1166_vt_select_15_b = i_conv_i_i_i_i_i75_i277_41_c_compstr1166_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_41_c_compstr1166_vt_join(BITJOIN,7492)@94
    assign i_conv_i_i_i_i_i75_i277_41_c_compstr1166_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_41_c_compstr1166_vt_select_15_b};

    // leftShiftStage0_uid23990_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x(MUX,23989)@94
    assign leftShiftStage0_uid23990_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23990_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_41_c_compstr1166_vt_join_q or leftShiftStage0Idx1_uid23988_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23990_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23990_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_41_c_compstr1166_vt_join_q;
            1'b1 : leftShiftStage0_uid23990_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23988_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23990_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23995_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x(MUX,23994)@94
    assign leftShiftStage1_uid23995_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23995_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_s or leftShiftStage0_uid23990_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23993_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23995_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23995_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q = leftShiftStage0_uid23990_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23995_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23993_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23995_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24000_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x(MUX,23999)@94
    assign leftShiftStage2_uid24000_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24000_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_s or leftShiftStage1_uid23995_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23998_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24000_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24000_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q = leftShiftStage1_uid23995_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24000_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23998_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24000_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_41_c_compstr1167_vt_select_28(BITSELECT,9229)@94
    assign i_shl_i_i_i_i_i77_i_41_c_compstr1167_vt_select_28_b = leftShiftStage2_uid24000_i_shl_i_i_i_i_i77_i_41_c_compstr0_shift_x_q[28:13];

    // redist447_i_shl_i_i_i_i_i77_i_41_c_compstr1167_vt_select_28_b_1(DELAY,28675)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist447_i_shl_i_i_i_i_i77_i_41_c_compstr1167_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_41_c_compstr1167_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_41_c_compstr1167_vt_join(BITJOIN,9228)@95
    assign i_shl_i_i_i_i_i77_i_41_c_compstr1167_vt_join_q = {redist447_i_shl_i_i_i_i_i77_i_41_c_compstr1167_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma(CHAINMULTADD,28161)@89 + 5
    // out q@95
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ah[0] <= redist853_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_83_tpl_81_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ah[1] <= redist852_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_82_tpl_81_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ch[0] <= redist599_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_83_tpl_81_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ch[1] <= redist598_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_82_tpl_81_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168(ADD,8457)@95
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compstr1163_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compstr1165_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compstr1164_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_41_c_compstr1167_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_41_c_compstr1167_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_o[33:0];

    // rightShiftStage0_uid17480_dupName_163_i_unnamed_c_compstr0_shift_x(MUX,17479)@95
    assign rightShiftStage0_uid17480_dupName_163_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17480_dupName_163_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_q or rightShiftStage0Idx1_uid17478_dupName_163_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17480_dupName_163_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17480_dupName_163_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_q;
            1'b1 : rightShiftStage0_uid17480_dupName_163_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17478_dupName_163_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17480_dupName_163_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17485_dupName_163_i_unnamed_c_compstr0_shift_x(MUX,17484)@95
    assign rightShiftStage1_uid17485_dupName_163_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17485_dupName_163_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17480_dupName_163_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17483_dupName_163_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17485_dupName_163_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17485_dupName_163_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17480_dupName_163_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17485_dupName_163_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17483_dupName_163_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17485_dupName_163_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17490_dupName_163_i_unnamed_c_compstr0_shift_x(MUX,17489)@95
    assign rightShiftStage2_uid17490_dupName_163_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17490_dupName_163_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17485_dupName_163_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17488_dupName_163_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17490_dupName_163_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17490_dupName_163_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17485_dupName_163_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17490_dupName_163_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17488_dupName_163_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17490_dupName_163_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1169_vt_select_20(BITSELECT,9948)@95
    assign i_unnamed_c_compstr1169_vt_select_20_b = rightShiftStage2_uid17490_dupName_163_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1169_vt_join(BITJOIN,9947)@95
    assign i_unnamed_c_compstr1169_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1169_vt_select_20_b};

    // i_conv_i_i_i_i97_i_41_c_compstr1170_sel_x(BITSELECT,3519)@95
    assign i_conv_i_i_i_i97_i_41_c_compstr1170_sel_x_b = i_unnamed_c_compstr1169_vt_join_q[15:0];

    // redist1217_i_conv_i_i_i_i97_i_41_c_compstr1170_sel_x_b_1(DELAY,29445)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1217_i_conv_i_i_i_i97_i_41_c_compstr1170_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_41_c_compstr1170_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17499_dupName_164_i_unnamed_c_compstr0_shift_x(BITSELECT,17498)@95
    assign rightShiftStage1Idx1Rng8_uid17499_dupName_164_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17498_dupName_164_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17501_dupName_164_i_unnamed_c_compstr0_shift_x(BITJOIN,17500)@95
    assign rightShiftStage1Idx1_uid17501_dupName_164_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17499_dupName_164_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17494_dupName_164_i_unnamed_c_compstr0_shift_x(BITSELECT,17493)@95
    assign rightShiftStage0Idx1Rng4_uid17494_dupName_164_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_q[33:4];

    // rightShiftStage0Idx1_uid17496_dupName_164_i_unnamed_c_compstr0_shift_x(BITJOIN,17495)@95
    assign rightShiftStage0Idx1_uid17496_dupName_164_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17494_dupName_164_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17498_dupName_164_i_unnamed_c_compstr0_shift_x(MUX,17497)@95
    assign rightShiftStage0_uid17498_dupName_164_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17498_dupName_164_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_q or rightShiftStage0Idx1_uid17496_dupName_164_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17498_dupName_164_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17498_dupName_164_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compstr1168_q;
            1'b1 : rightShiftStage0_uid17498_dupName_164_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17496_dupName_164_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17498_dupName_164_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17503_dupName_164_i_unnamed_c_compstr0_shift_x(MUX,17502)@95
    assign rightShiftStage1_uid17503_dupName_164_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17503_dupName_164_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17498_dupName_164_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17501_dupName_164_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17503_dupName_164_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17503_dupName_164_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17498_dupName_164_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17503_dupName_164_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17501_dupName_164_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17503_dupName_164_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1171_vt_select_21(BITSELECT,9951)@95
    assign i_unnamed_c_compstr1171_vt_select_21_b = rightShiftStage1_uid17503_dupName_164_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1171_vt_join(BITJOIN,9950)@95
    assign i_unnamed_c_compstr1171_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1171_vt_select_21_b};

    // i_unnamed_c_compstr1172_sel_x(BITSELECT,6048)@95
    assign i_unnamed_c_compstr1172_sel_x_b = i_unnamed_c_compstr1171_vt_join_q[15:0];

    // i_unnamed_c_compstr1173_BitSelect_for_a(BITSELECT,27485)@95
    assign i_unnamed_c_compstr1173_BitSelect_for_a_b = i_unnamed_c_compstr1172_sel_x_b[0:0];

    // i_unnamed_c_compstr1173_join(BITJOIN,27486)@95
    assign i_unnamed_c_compstr1173_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1173_BitSelect_for_a_b};

    // i_unnamed_c_compstr1173_vt_select_0(BITSELECT,9956)@95
    assign i_unnamed_c_compstr1173_vt_select_0_b = i_unnamed_c_compstr1173_join_q[0:0];

    // redist242_i_unnamed_c_compstr1173_vt_select_0_b_1(DELAY,28470)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist242_i_unnamed_c_compstr1173_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1173_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1173_vt_join(BITJOIN,9955)@96
    assign i_unnamed_c_compstr1173_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist242_i_unnamed_c_compstr1173_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_41_c_compstr1174(ADD,6914)@96
    assign i_add_i_i_i_i_i126_i_41_c_compstr1174_a = {1'b0, i_unnamed_c_compstr1173_vt_join_q};
    assign i_add_i_i_i_i_i126_i_41_c_compstr1174_b = {1'b0, redist1217_i_conv_i_i_i_i97_i_41_c_compstr1170_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_41_c_compstr1174_o = $unsigned(i_add_i_i_i_i_i126_i_41_c_compstr1174_a) + $unsigned(i_add_i_i_i_i_i126_i_41_c_compstr1174_b);
    assign i_add_i_i_i_i_i126_i_41_c_compstr1174_q = i_add_i_i_i_i_i126_i_41_c_compstr1174_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_41_c_compstr1174_sel_x(BITSELECT,2108)@96
    assign bgTrunc_i_add_i_i_i_i_i126_i_41_c_compstr1174_sel_x_b = i_add_i_i_i_i_i126_i_41_c_compstr1174_q[15:0];

    // i_conv_i_i_i_i_i75_i277_42_c_compstr1194_sel_x(BITSELECT,3649)@96
    assign i_conv_i_i_i_i_i75_i277_42_c_compstr1194_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_41_c_compstr1174_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_42_c_compstr1194_vt_select_15(BITSELECT,7497)@96
    assign i_conv_i_i_i_i_i75_i277_42_c_compstr1194_vt_select_15_b = i_conv_i_i_i_i_i75_i277_42_c_compstr1194_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_42_c_compstr1194_vt_join(BITJOIN,7496)@96
    assign i_conv_i_i_i_i_i75_i277_42_c_compstr1194_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_42_c_compstr1194_vt_select_15_b};

    // leftShiftStage0_uid24008_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x(MUX,24007)@96
    assign leftShiftStage0_uid24008_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24008_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_42_c_compstr1194_vt_join_q or leftShiftStage0Idx1_uid24006_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24008_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24008_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_42_c_compstr1194_vt_join_q;
            1'b1 : leftShiftStage0_uid24008_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24006_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24008_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24013_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x(MUX,24012)@96
    assign leftShiftStage1_uid24013_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24013_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_s or leftShiftStage0_uid24008_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24011_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24013_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24013_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q = leftShiftStage0_uid24008_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24013_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24011_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24013_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24018_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x(MUX,24017)@96
    assign leftShiftStage2_uid24018_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24018_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_s or leftShiftStage1_uid24013_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24016_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24018_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24018_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q = leftShiftStage1_uid24013_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24018_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24016_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24018_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_42_c_compstr1195_vt_select_28(BITSELECT,9232)@96
    assign i_shl_i_i_i_i_i77_i_42_c_compstr1195_vt_select_28_b = leftShiftStage2_uid24018_i_shl_i_i_i_i_i77_i_42_c_compstr0_shift_x_q[28:13];

    // redist446_i_shl_i_i_i_i_i77_i_42_c_compstr1195_vt_select_28_b_1(DELAY,28674)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist446_i_shl_i_i_i_i_i77_i_42_c_compstr1195_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_42_c_compstr1195_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_42_c_compstr1195_vt_join(BITJOIN,9231)@97
    assign i_shl_i_i_i_i_i77_i_42_c_compstr1195_vt_join_q = {redist446_i_shl_i_i_i_i_i77_i_42_c_compstr1195_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma(CHAINMULTADD,28162)@91 + 5
    // out q@97
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ah[0] <= redist855_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_85_tpl_83_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ah[1] <= redist854_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_84_tpl_83_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ch[0] <= redist601_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_85_tpl_83_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ch[1] <= redist600_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_84_tpl_83_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196(ADD,8458)@97
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compstr1191_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compstr1193_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compstr1192_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_42_c_compstr1195_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_42_c_compstr1195_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_o[33:0];

    // rightShiftStage0_uid17542_dupName_167_i_unnamed_c_compstr0_shift_x(MUX,17541)@97
    assign rightShiftStage0_uid17542_dupName_167_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17542_dupName_167_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_q or rightShiftStage0Idx1_uid17540_dupName_167_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17542_dupName_167_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17542_dupName_167_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_q;
            1'b1 : rightShiftStage0_uid17542_dupName_167_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17540_dupName_167_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17542_dupName_167_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17547_dupName_167_i_unnamed_c_compstr0_shift_x(MUX,17546)@97
    assign rightShiftStage1_uid17547_dupName_167_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17547_dupName_167_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17542_dupName_167_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17545_dupName_167_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17547_dupName_167_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17547_dupName_167_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17542_dupName_167_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17547_dupName_167_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17545_dupName_167_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17547_dupName_167_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17552_dupName_167_i_unnamed_c_compstr0_shift_x(MUX,17551)@97
    assign rightShiftStage2_uid17552_dupName_167_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17552_dupName_167_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17547_dupName_167_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17550_dupName_167_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17552_dupName_167_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17552_dupName_167_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17547_dupName_167_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17552_dupName_167_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17550_dupName_167_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17552_dupName_167_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1197_vt_select_20(BITSELECT,9970)@97
    assign i_unnamed_c_compstr1197_vt_select_20_b = rightShiftStage2_uid17552_dupName_167_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1197_vt_join(BITJOIN,9969)@97
    assign i_unnamed_c_compstr1197_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1197_vt_select_20_b};

    // i_conv_i_i_i_i97_i_42_c_compstr1198_sel_x(BITSELECT,3520)@97
    assign i_conv_i_i_i_i97_i_42_c_compstr1198_sel_x_b = i_unnamed_c_compstr1197_vt_join_q[15:0];

    // redist1216_i_conv_i_i_i_i97_i_42_c_compstr1198_sel_x_b_1(DELAY,29444)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1216_i_conv_i_i_i_i97_i_42_c_compstr1198_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_42_c_compstr1198_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17561_dupName_168_i_unnamed_c_compstr0_shift_x(BITSELECT,17560)@97
    assign rightShiftStage1Idx1Rng8_uid17561_dupName_168_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17560_dupName_168_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17563_dupName_168_i_unnamed_c_compstr0_shift_x(BITJOIN,17562)@97
    assign rightShiftStage1Idx1_uid17563_dupName_168_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17561_dupName_168_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17556_dupName_168_i_unnamed_c_compstr0_shift_x(BITSELECT,17555)@97
    assign rightShiftStage0Idx1Rng4_uid17556_dupName_168_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_q[33:4];

    // rightShiftStage0Idx1_uid17558_dupName_168_i_unnamed_c_compstr0_shift_x(BITJOIN,17557)@97
    assign rightShiftStage0Idx1_uid17558_dupName_168_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17556_dupName_168_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17560_dupName_168_i_unnamed_c_compstr0_shift_x(MUX,17559)@97
    assign rightShiftStage0_uid17560_dupName_168_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17560_dupName_168_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_q or rightShiftStage0Idx1_uid17558_dupName_168_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17560_dupName_168_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17560_dupName_168_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compstr1196_q;
            1'b1 : rightShiftStage0_uid17560_dupName_168_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17558_dupName_168_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17560_dupName_168_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17565_dupName_168_i_unnamed_c_compstr0_shift_x(MUX,17564)@97
    assign rightShiftStage1_uid17565_dupName_168_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17565_dupName_168_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17560_dupName_168_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17563_dupName_168_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17565_dupName_168_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17565_dupName_168_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17560_dupName_168_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17565_dupName_168_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17563_dupName_168_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17565_dupName_168_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1199_vt_select_21(BITSELECT,9973)@97
    assign i_unnamed_c_compstr1199_vt_select_21_b = rightShiftStage1_uid17565_dupName_168_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1199_vt_join(BITJOIN,9972)@97
    assign i_unnamed_c_compstr1199_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1199_vt_select_21_b};

    // i_unnamed_c_compstr1200_sel_x(BITSELECT,6050)@97
    assign i_unnamed_c_compstr1200_sel_x_b = i_unnamed_c_compstr1199_vt_join_q[15:0];

    // i_unnamed_c_compstr1201_BitSelect_for_a(BITSELECT,27489)@97
    assign i_unnamed_c_compstr1201_BitSelect_for_a_b = i_unnamed_c_compstr1200_sel_x_b[0:0];

    // i_unnamed_c_compstr1201_join(BITJOIN,27490)@97
    assign i_unnamed_c_compstr1201_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1201_BitSelect_for_a_b};

    // i_unnamed_c_compstr1201_vt_select_0(BITSELECT,9978)@97
    assign i_unnamed_c_compstr1201_vt_select_0_b = i_unnamed_c_compstr1201_join_q[0:0];

    // redist240_i_unnamed_c_compstr1201_vt_select_0_b_1(DELAY,28468)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist240_i_unnamed_c_compstr1201_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1201_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1201_vt_join(BITJOIN,9977)@98
    assign i_unnamed_c_compstr1201_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist240_i_unnamed_c_compstr1201_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_42_c_compstr1202(ADD,6915)@98
    assign i_add_i_i_i_i_i126_i_42_c_compstr1202_a = {1'b0, i_unnamed_c_compstr1201_vt_join_q};
    assign i_add_i_i_i_i_i126_i_42_c_compstr1202_b = {1'b0, redist1216_i_conv_i_i_i_i97_i_42_c_compstr1198_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_42_c_compstr1202_o = $unsigned(i_add_i_i_i_i_i126_i_42_c_compstr1202_a) + $unsigned(i_add_i_i_i_i_i126_i_42_c_compstr1202_b);
    assign i_add_i_i_i_i_i126_i_42_c_compstr1202_q = i_add_i_i_i_i_i126_i_42_c_compstr1202_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_42_c_compstr1202_sel_x(BITSELECT,2109)@98
    assign bgTrunc_i_add_i_i_i_i_i126_i_42_c_compstr1202_sel_x_b = i_add_i_i_i_i_i126_i_42_c_compstr1202_q[15:0];

    // i_conv_i_i_i_i_i75_i277_43_c_compstr1222_sel_x(BITSELECT,3650)@98
    assign i_conv_i_i_i_i_i75_i277_43_c_compstr1222_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_42_c_compstr1202_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_43_c_compstr1222_vt_select_15(BITSELECT,7501)@98
    assign i_conv_i_i_i_i_i75_i277_43_c_compstr1222_vt_select_15_b = i_conv_i_i_i_i_i75_i277_43_c_compstr1222_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_43_c_compstr1222_vt_join(BITJOIN,7500)@98
    assign i_conv_i_i_i_i_i75_i277_43_c_compstr1222_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_43_c_compstr1222_vt_select_15_b};

    // leftShiftStage0_uid24026_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x(MUX,24025)@98
    assign leftShiftStage0_uid24026_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24026_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_43_c_compstr1222_vt_join_q or leftShiftStage0Idx1_uid24024_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24026_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24026_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_43_c_compstr1222_vt_join_q;
            1'b1 : leftShiftStage0_uid24026_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24024_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24026_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24031_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x(MUX,24030)@98
    assign leftShiftStage1_uid24031_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24031_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_s or leftShiftStage0_uid24026_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24029_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24031_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24031_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q = leftShiftStage0_uid24026_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24031_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24029_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24031_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24036_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x(MUX,24035)@98
    assign leftShiftStage2_uid24036_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24036_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_s or leftShiftStage1_uid24031_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24034_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24036_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24036_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q = leftShiftStage1_uid24031_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24036_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24034_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24036_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_43_c_compstr1223_vt_select_28(BITSELECT,9235)@98
    assign i_shl_i_i_i_i_i77_i_43_c_compstr1223_vt_select_28_b = leftShiftStage2_uid24036_i_shl_i_i_i_i_i77_i_43_c_compstr0_shift_x_q[28:13];

    // redist445_i_shl_i_i_i_i_i77_i_43_c_compstr1223_vt_select_28_b_1(DELAY,28673)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist445_i_shl_i_i_i_i_i77_i_43_c_compstr1223_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_43_c_compstr1223_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_43_c_compstr1223_vt_join(BITJOIN,9234)@99
    assign i_shl_i_i_i_i_i77_i_43_c_compstr1223_vt_join_q = {redist445_i_shl_i_i_i_i_i77_i_43_c_compstr1223_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma(CHAINMULTADD,28163)@93 + 5
    // out q@99
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ah[0] <= redist857_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_87_tpl_85_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ah[1] <= redist856_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_86_tpl_85_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ch[0] <= redist603_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_87_tpl_85_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ch[1] <= redist602_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_86_tpl_85_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224(ADD,8459)@99
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compstr1219_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compstr1221_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compstr1220_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_43_c_compstr1223_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_43_c_compstr1223_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_o[33:0];

    // rightShiftStage0_uid17604_dupName_171_i_unnamed_c_compstr0_shift_x(MUX,17603)@99
    assign rightShiftStage0_uid17604_dupName_171_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17604_dupName_171_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_q or rightShiftStage0Idx1_uid17602_dupName_171_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17604_dupName_171_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17604_dupName_171_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_q;
            1'b1 : rightShiftStage0_uid17604_dupName_171_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17602_dupName_171_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17604_dupName_171_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17609_dupName_171_i_unnamed_c_compstr0_shift_x(MUX,17608)@99
    assign rightShiftStage1_uid17609_dupName_171_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17609_dupName_171_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17604_dupName_171_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17607_dupName_171_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17609_dupName_171_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17609_dupName_171_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17604_dupName_171_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17609_dupName_171_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17607_dupName_171_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17609_dupName_171_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17614_dupName_171_i_unnamed_c_compstr0_shift_x(MUX,17613)@99
    assign rightShiftStage2_uid17614_dupName_171_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17614_dupName_171_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17609_dupName_171_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17612_dupName_171_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17614_dupName_171_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17614_dupName_171_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17609_dupName_171_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17614_dupName_171_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17612_dupName_171_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17614_dupName_171_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1225_vt_select_20(BITSELECT,9995)@99
    assign i_unnamed_c_compstr1225_vt_select_20_b = rightShiftStage2_uid17614_dupName_171_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1225_vt_join(BITJOIN,9994)@99
    assign i_unnamed_c_compstr1225_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1225_vt_select_20_b};

    // i_conv_i_i_i_i97_i_43_c_compstr1226_sel_x(BITSELECT,3521)@99
    assign i_conv_i_i_i_i97_i_43_c_compstr1226_sel_x_b = i_unnamed_c_compstr1225_vt_join_q[15:0];

    // redist1215_i_conv_i_i_i_i97_i_43_c_compstr1226_sel_x_b_1(DELAY,29443)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1215_i_conv_i_i_i_i97_i_43_c_compstr1226_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_43_c_compstr1226_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17623_dupName_172_i_unnamed_c_compstr0_shift_x(BITSELECT,17622)@99
    assign rightShiftStage1Idx1Rng8_uid17623_dupName_172_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17622_dupName_172_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17625_dupName_172_i_unnamed_c_compstr0_shift_x(BITJOIN,17624)@99
    assign rightShiftStage1Idx1_uid17625_dupName_172_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17623_dupName_172_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17618_dupName_172_i_unnamed_c_compstr0_shift_x(BITSELECT,17617)@99
    assign rightShiftStage0Idx1Rng4_uid17618_dupName_172_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_q[33:4];

    // rightShiftStage0Idx1_uid17620_dupName_172_i_unnamed_c_compstr0_shift_x(BITJOIN,17619)@99
    assign rightShiftStage0Idx1_uid17620_dupName_172_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17618_dupName_172_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17622_dupName_172_i_unnamed_c_compstr0_shift_x(MUX,17621)@99
    assign rightShiftStage0_uid17622_dupName_172_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17622_dupName_172_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_q or rightShiftStage0Idx1_uid17620_dupName_172_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17622_dupName_172_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17622_dupName_172_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compstr1224_q;
            1'b1 : rightShiftStage0_uid17622_dupName_172_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17620_dupName_172_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17622_dupName_172_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17627_dupName_172_i_unnamed_c_compstr0_shift_x(MUX,17626)@99
    assign rightShiftStage1_uid17627_dupName_172_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17627_dupName_172_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17622_dupName_172_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17625_dupName_172_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17627_dupName_172_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17627_dupName_172_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17622_dupName_172_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17627_dupName_172_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17625_dupName_172_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17627_dupName_172_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1227_vt_select_21(BITSELECT,9998)@99
    assign i_unnamed_c_compstr1227_vt_select_21_b = rightShiftStage1_uid17627_dupName_172_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1227_vt_join(BITJOIN,9997)@99
    assign i_unnamed_c_compstr1227_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1227_vt_select_21_b};

    // i_unnamed_c_compstr1228_sel_x(BITSELECT,6052)@99
    assign i_unnamed_c_compstr1228_sel_x_b = i_unnamed_c_compstr1227_vt_join_q[15:0];

    // i_unnamed_c_compstr1229_BitSelect_for_a(BITSELECT,27493)@99
    assign i_unnamed_c_compstr1229_BitSelect_for_a_b = i_unnamed_c_compstr1228_sel_x_b[0:0];

    // i_unnamed_c_compstr1229_join(BITJOIN,27494)@99
    assign i_unnamed_c_compstr1229_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1229_BitSelect_for_a_b};

    // i_unnamed_c_compstr1229_vt_select_0(BITSELECT,10003)@99
    assign i_unnamed_c_compstr1229_vt_select_0_b = i_unnamed_c_compstr1229_join_q[0:0];

    // redist238_i_unnamed_c_compstr1229_vt_select_0_b_1(DELAY,28466)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist238_i_unnamed_c_compstr1229_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1229_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1229_vt_join(BITJOIN,10002)@100
    assign i_unnamed_c_compstr1229_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist238_i_unnamed_c_compstr1229_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_43_c_compstr1230(ADD,6916)@100
    assign i_add_i_i_i_i_i126_i_43_c_compstr1230_a = {1'b0, i_unnamed_c_compstr1229_vt_join_q};
    assign i_add_i_i_i_i_i126_i_43_c_compstr1230_b = {1'b0, redist1215_i_conv_i_i_i_i97_i_43_c_compstr1226_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_43_c_compstr1230_o = $unsigned(i_add_i_i_i_i_i126_i_43_c_compstr1230_a) + $unsigned(i_add_i_i_i_i_i126_i_43_c_compstr1230_b);
    assign i_add_i_i_i_i_i126_i_43_c_compstr1230_q = i_add_i_i_i_i_i126_i_43_c_compstr1230_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_43_c_compstr1230_sel_x(BITSELECT,2110)@100
    assign bgTrunc_i_add_i_i_i_i_i126_i_43_c_compstr1230_sel_x_b = i_add_i_i_i_i_i126_i_43_c_compstr1230_q[15:0];

    // i_conv_i_i_i_i_i75_i277_44_c_compstr1250_sel_x(BITSELECT,3651)@100
    assign i_conv_i_i_i_i_i75_i277_44_c_compstr1250_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_43_c_compstr1230_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_44_c_compstr1250_vt_select_15(BITSELECT,7505)@100
    assign i_conv_i_i_i_i_i75_i277_44_c_compstr1250_vt_select_15_b = i_conv_i_i_i_i_i75_i277_44_c_compstr1250_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_44_c_compstr1250_vt_join(BITJOIN,7504)@100
    assign i_conv_i_i_i_i_i75_i277_44_c_compstr1250_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_44_c_compstr1250_vt_select_15_b};

    // leftShiftStage0_uid24044_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x(MUX,24043)@100
    assign leftShiftStage0_uid24044_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24044_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_44_c_compstr1250_vt_join_q or leftShiftStage0Idx1_uid24042_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24044_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24044_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_44_c_compstr1250_vt_join_q;
            1'b1 : leftShiftStage0_uid24044_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24042_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24044_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24049_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x(MUX,24048)@100
    assign leftShiftStage1_uid24049_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24049_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_s or leftShiftStage0_uid24044_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24047_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24049_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24049_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q = leftShiftStage0_uid24044_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24049_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24047_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24049_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24054_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x(MUX,24053)@100
    assign leftShiftStage2_uid24054_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24054_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_s or leftShiftStage1_uid24049_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24052_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24054_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24054_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q = leftShiftStage1_uid24049_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24054_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24052_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24054_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_44_c_compstr1251_vt_select_28(BITSELECT,9238)@100
    assign i_shl_i_i_i_i_i77_i_44_c_compstr1251_vt_select_28_b = leftShiftStage2_uid24054_i_shl_i_i_i_i_i77_i_44_c_compstr0_shift_x_q[28:13];

    // redist444_i_shl_i_i_i_i_i77_i_44_c_compstr1251_vt_select_28_b_1(DELAY,28672)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist444_i_shl_i_i_i_i_i77_i_44_c_compstr1251_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_44_c_compstr1251_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_44_c_compstr1251_vt_join(BITJOIN,9237)@101
    assign i_shl_i_i_i_i_i77_i_44_c_compstr1251_vt_join_q = {redist444_i_shl_i_i_i_i_i77_i_44_c_compstr1251_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma(CHAINMULTADD,28164)@95 + 5
    // out q@101
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ah[0] <= redist859_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_89_tpl_87_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ah[1] <= redist858_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_88_tpl_87_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ch[0] <= redist605_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_89_tpl_87_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ch[1] <= redist604_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_88_tpl_87_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252(ADD,8460)@101
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compstr1247_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compstr1249_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compstr1248_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_44_c_compstr1251_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_44_c_compstr1251_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_o[33:0];

    // rightShiftStage0_uid17666_dupName_175_i_unnamed_c_compstr0_shift_x(MUX,17665)@101
    assign rightShiftStage0_uid17666_dupName_175_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17666_dupName_175_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_q or rightShiftStage0Idx1_uid17664_dupName_175_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17666_dupName_175_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17666_dupName_175_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_q;
            1'b1 : rightShiftStage0_uid17666_dupName_175_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17664_dupName_175_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17666_dupName_175_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17671_dupName_175_i_unnamed_c_compstr0_shift_x(MUX,17670)@101
    assign rightShiftStage1_uid17671_dupName_175_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17671_dupName_175_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17666_dupName_175_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17669_dupName_175_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17671_dupName_175_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17671_dupName_175_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17666_dupName_175_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17671_dupName_175_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17669_dupName_175_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17671_dupName_175_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17676_dupName_175_i_unnamed_c_compstr0_shift_x(MUX,17675)@101
    assign rightShiftStage2_uid17676_dupName_175_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17676_dupName_175_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17671_dupName_175_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17674_dupName_175_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17676_dupName_175_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17676_dupName_175_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17671_dupName_175_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17676_dupName_175_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17674_dupName_175_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17676_dupName_175_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1253_vt_select_20(BITSELECT,10022)@101
    assign i_unnamed_c_compstr1253_vt_select_20_b = rightShiftStage2_uid17676_dupName_175_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1253_vt_join(BITJOIN,10021)@101
    assign i_unnamed_c_compstr1253_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1253_vt_select_20_b};

    // i_conv_i_i_i_i97_i_44_c_compstr1254_sel_x(BITSELECT,3522)@101
    assign i_conv_i_i_i_i97_i_44_c_compstr1254_sel_x_b = i_unnamed_c_compstr1253_vt_join_q[15:0];

    // redist1214_i_conv_i_i_i_i97_i_44_c_compstr1254_sel_x_b_1(DELAY,29442)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1214_i_conv_i_i_i_i97_i_44_c_compstr1254_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_44_c_compstr1254_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17685_dupName_176_i_unnamed_c_compstr0_shift_x(BITSELECT,17684)@101
    assign rightShiftStage1Idx1Rng8_uid17685_dupName_176_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17684_dupName_176_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17687_dupName_176_i_unnamed_c_compstr0_shift_x(BITJOIN,17686)@101
    assign rightShiftStage1Idx1_uid17687_dupName_176_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17685_dupName_176_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17680_dupName_176_i_unnamed_c_compstr0_shift_x(BITSELECT,17679)@101
    assign rightShiftStage0Idx1Rng4_uid17680_dupName_176_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_q[33:4];

    // rightShiftStage0Idx1_uid17682_dupName_176_i_unnamed_c_compstr0_shift_x(BITJOIN,17681)@101
    assign rightShiftStage0Idx1_uid17682_dupName_176_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17680_dupName_176_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17684_dupName_176_i_unnamed_c_compstr0_shift_x(MUX,17683)@101
    assign rightShiftStage0_uid17684_dupName_176_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17684_dupName_176_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_q or rightShiftStage0Idx1_uid17682_dupName_176_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17684_dupName_176_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17684_dupName_176_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compstr1252_q;
            1'b1 : rightShiftStage0_uid17684_dupName_176_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17682_dupName_176_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17684_dupName_176_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17689_dupName_176_i_unnamed_c_compstr0_shift_x(MUX,17688)@101
    assign rightShiftStage1_uid17689_dupName_176_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17689_dupName_176_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17684_dupName_176_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17687_dupName_176_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17689_dupName_176_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17689_dupName_176_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17684_dupName_176_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17689_dupName_176_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17687_dupName_176_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17689_dupName_176_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1255_vt_select_21(BITSELECT,10025)@101
    assign i_unnamed_c_compstr1255_vt_select_21_b = rightShiftStage1_uid17689_dupName_176_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1255_vt_join(BITJOIN,10024)@101
    assign i_unnamed_c_compstr1255_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1255_vt_select_21_b};

    // i_unnamed_c_compstr1256_sel_x(BITSELECT,6055)@101
    assign i_unnamed_c_compstr1256_sel_x_b = i_unnamed_c_compstr1255_vt_join_q[15:0];

    // i_unnamed_c_compstr1257_BitSelect_for_a(BITSELECT,27499)@101
    assign i_unnamed_c_compstr1257_BitSelect_for_a_b = i_unnamed_c_compstr1256_sel_x_b[0:0];

    // i_unnamed_c_compstr1257_join(BITJOIN,27500)@101
    assign i_unnamed_c_compstr1257_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1257_BitSelect_for_a_b};

    // i_unnamed_c_compstr1257_vt_select_0(BITSELECT,10030)@101
    assign i_unnamed_c_compstr1257_vt_select_0_b = i_unnamed_c_compstr1257_join_q[0:0];

    // redist236_i_unnamed_c_compstr1257_vt_select_0_b_1(DELAY,28464)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist236_i_unnamed_c_compstr1257_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1257_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1257_vt_join(BITJOIN,10029)@102
    assign i_unnamed_c_compstr1257_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist236_i_unnamed_c_compstr1257_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_44_c_compstr1258(ADD,6917)@102
    assign i_add_i_i_i_i_i126_i_44_c_compstr1258_a = {1'b0, i_unnamed_c_compstr1257_vt_join_q};
    assign i_add_i_i_i_i_i126_i_44_c_compstr1258_b = {1'b0, redist1214_i_conv_i_i_i_i97_i_44_c_compstr1254_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_44_c_compstr1258_o = $unsigned(i_add_i_i_i_i_i126_i_44_c_compstr1258_a) + $unsigned(i_add_i_i_i_i_i126_i_44_c_compstr1258_b);
    assign i_add_i_i_i_i_i126_i_44_c_compstr1258_q = i_add_i_i_i_i_i126_i_44_c_compstr1258_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_44_c_compstr1258_sel_x(BITSELECT,2111)@102
    assign bgTrunc_i_add_i_i_i_i_i126_i_44_c_compstr1258_sel_x_b = i_add_i_i_i_i_i126_i_44_c_compstr1258_q[15:0];

    // i_conv_i_i_i_i_i75_i277_45_c_compstr1278_sel_x(BITSELECT,3652)@102
    assign i_conv_i_i_i_i_i75_i277_45_c_compstr1278_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_44_c_compstr1258_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_45_c_compstr1278_vt_select_15(BITSELECT,7509)@102
    assign i_conv_i_i_i_i_i75_i277_45_c_compstr1278_vt_select_15_b = i_conv_i_i_i_i_i75_i277_45_c_compstr1278_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_45_c_compstr1278_vt_join(BITJOIN,7508)@102
    assign i_conv_i_i_i_i_i75_i277_45_c_compstr1278_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_45_c_compstr1278_vt_select_15_b};

    // leftShiftStage0_uid24062_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x(MUX,24061)@102
    assign leftShiftStage0_uid24062_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24062_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_45_c_compstr1278_vt_join_q or leftShiftStage0Idx1_uid24060_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24062_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24062_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_45_c_compstr1278_vt_join_q;
            1'b1 : leftShiftStage0_uid24062_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24060_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24062_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24067_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x(MUX,24066)@102
    assign leftShiftStage1_uid24067_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24067_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_s or leftShiftStage0_uid24062_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24065_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24067_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24067_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q = leftShiftStage0_uid24062_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24067_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24065_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24067_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24072_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x(MUX,24071)@102
    assign leftShiftStage2_uid24072_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24072_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_s or leftShiftStage1_uid24067_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24070_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24072_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24072_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q = leftShiftStage1_uid24067_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24072_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24070_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24072_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_45_c_compstr1279_vt_select_28(BITSELECT,9241)@102
    assign i_shl_i_i_i_i_i77_i_45_c_compstr1279_vt_select_28_b = leftShiftStage2_uid24072_i_shl_i_i_i_i_i77_i_45_c_compstr0_shift_x_q[28:13];

    // redist443_i_shl_i_i_i_i_i77_i_45_c_compstr1279_vt_select_28_b_1(DELAY,28671)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist443_i_shl_i_i_i_i_i77_i_45_c_compstr1279_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_45_c_compstr1279_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_45_c_compstr1279_vt_join(BITJOIN,9240)@103
    assign i_shl_i_i_i_i_i77_i_45_c_compstr1279_vt_join_q = {redist443_i_shl_i_i_i_i_i77_i_45_c_compstr1279_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma(CHAINMULTADD,28165)@97 + 5
    // out q@103
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ah[0] <= redist861_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_91_tpl_89_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ah[1] <= redist860_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_90_tpl_89_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ch[0] <= redist607_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_91_tpl_89_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ch[1] <= redist606_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_90_tpl_89_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280(ADD,8461)@103
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compstr1275_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compstr1277_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compstr1276_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_45_c_compstr1279_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_45_c_compstr1279_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_o[33:0];

    // rightShiftStage0_uid17728_dupName_179_i_unnamed_c_compstr0_shift_x(MUX,17727)@103
    assign rightShiftStage0_uid17728_dupName_179_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17728_dupName_179_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_q or rightShiftStage0Idx1_uid17726_dupName_179_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17728_dupName_179_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17728_dupName_179_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_q;
            1'b1 : rightShiftStage0_uid17728_dupName_179_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17726_dupName_179_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17728_dupName_179_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17733_dupName_179_i_unnamed_c_compstr0_shift_x(MUX,17732)@103
    assign rightShiftStage1_uid17733_dupName_179_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17733_dupName_179_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17728_dupName_179_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17731_dupName_179_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17733_dupName_179_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17733_dupName_179_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17728_dupName_179_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17733_dupName_179_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17731_dupName_179_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17733_dupName_179_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17738_dupName_179_i_unnamed_c_compstr0_shift_x(MUX,17737)@103
    assign rightShiftStage2_uid17738_dupName_179_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17738_dupName_179_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17733_dupName_179_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17736_dupName_179_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17738_dupName_179_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17738_dupName_179_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17733_dupName_179_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17738_dupName_179_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17736_dupName_179_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17738_dupName_179_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1281_vt_select_20(BITSELECT,10047)@103
    assign i_unnamed_c_compstr1281_vt_select_20_b = rightShiftStage2_uid17738_dupName_179_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1281_vt_join(BITJOIN,10046)@103
    assign i_unnamed_c_compstr1281_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1281_vt_select_20_b};

    // i_conv_i_i_i_i97_i_45_c_compstr1282_sel_x(BITSELECT,3523)@103
    assign i_conv_i_i_i_i97_i_45_c_compstr1282_sel_x_b = i_unnamed_c_compstr1281_vt_join_q[15:0];

    // redist1213_i_conv_i_i_i_i97_i_45_c_compstr1282_sel_x_b_1(DELAY,29441)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1213_i_conv_i_i_i_i97_i_45_c_compstr1282_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_45_c_compstr1282_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17747_dupName_180_i_unnamed_c_compstr0_shift_x(BITSELECT,17746)@103
    assign rightShiftStage1Idx1Rng8_uid17747_dupName_180_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17746_dupName_180_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17749_dupName_180_i_unnamed_c_compstr0_shift_x(BITJOIN,17748)@103
    assign rightShiftStage1Idx1_uid17749_dupName_180_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17747_dupName_180_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17742_dupName_180_i_unnamed_c_compstr0_shift_x(BITSELECT,17741)@103
    assign rightShiftStage0Idx1Rng4_uid17742_dupName_180_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_q[33:4];

    // rightShiftStage0Idx1_uid17744_dupName_180_i_unnamed_c_compstr0_shift_x(BITJOIN,17743)@103
    assign rightShiftStage0Idx1_uid17744_dupName_180_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17742_dupName_180_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17746_dupName_180_i_unnamed_c_compstr0_shift_x(MUX,17745)@103
    assign rightShiftStage0_uid17746_dupName_180_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17746_dupName_180_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_q or rightShiftStage0Idx1_uid17744_dupName_180_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17746_dupName_180_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17746_dupName_180_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compstr1280_q;
            1'b1 : rightShiftStage0_uid17746_dupName_180_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17744_dupName_180_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17746_dupName_180_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17751_dupName_180_i_unnamed_c_compstr0_shift_x(MUX,17750)@103
    assign rightShiftStage1_uid17751_dupName_180_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17751_dupName_180_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17746_dupName_180_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17749_dupName_180_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17751_dupName_180_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17751_dupName_180_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17746_dupName_180_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17751_dupName_180_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17749_dupName_180_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17751_dupName_180_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1283_vt_select_21(BITSELECT,10050)@103
    assign i_unnamed_c_compstr1283_vt_select_21_b = rightShiftStage1_uid17751_dupName_180_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1283_vt_join(BITJOIN,10049)@103
    assign i_unnamed_c_compstr1283_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1283_vt_select_21_b};

    // i_unnamed_c_compstr1284_sel_x(BITSELECT,6057)@103
    assign i_unnamed_c_compstr1284_sel_x_b = i_unnamed_c_compstr1283_vt_join_q[15:0];

    // i_unnamed_c_compstr1285_BitSelect_for_a(BITSELECT,27503)@103
    assign i_unnamed_c_compstr1285_BitSelect_for_a_b = i_unnamed_c_compstr1284_sel_x_b[0:0];

    // i_unnamed_c_compstr1285_join(BITJOIN,27504)@103
    assign i_unnamed_c_compstr1285_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1285_BitSelect_for_a_b};

    // i_unnamed_c_compstr1285_vt_select_0(BITSELECT,10055)@103
    assign i_unnamed_c_compstr1285_vt_select_0_b = i_unnamed_c_compstr1285_join_q[0:0];

    // redist233_i_unnamed_c_compstr1285_vt_select_0_b_1(DELAY,28461)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist233_i_unnamed_c_compstr1285_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1285_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1285_vt_join(BITJOIN,10054)@104
    assign i_unnamed_c_compstr1285_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist233_i_unnamed_c_compstr1285_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_45_c_compstr1286(ADD,6918)@104
    assign i_add_i_i_i_i_i126_i_45_c_compstr1286_a = {1'b0, i_unnamed_c_compstr1285_vt_join_q};
    assign i_add_i_i_i_i_i126_i_45_c_compstr1286_b = {1'b0, redist1213_i_conv_i_i_i_i97_i_45_c_compstr1282_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_45_c_compstr1286_o = $unsigned(i_add_i_i_i_i_i126_i_45_c_compstr1286_a) + $unsigned(i_add_i_i_i_i_i126_i_45_c_compstr1286_b);
    assign i_add_i_i_i_i_i126_i_45_c_compstr1286_q = i_add_i_i_i_i_i126_i_45_c_compstr1286_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_45_c_compstr1286_sel_x(BITSELECT,2112)@104
    assign bgTrunc_i_add_i_i_i_i_i126_i_45_c_compstr1286_sel_x_b = i_add_i_i_i_i_i126_i_45_c_compstr1286_q[15:0];

    // i_conv_i_i_i_i_i75_i277_46_c_compstr1306_sel_x(BITSELECT,3653)@104
    assign i_conv_i_i_i_i_i75_i277_46_c_compstr1306_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_45_c_compstr1286_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_46_c_compstr1306_vt_select_15(BITSELECT,7513)@104
    assign i_conv_i_i_i_i_i75_i277_46_c_compstr1306_vt_select_15_b = i_conv_i_i_i_i_i75_i277_46_c_compstr1306_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_46_c_compstr1306_vt_join(BITJOIN,7512)@104
    assign i_conv_i_i_i_i_i75_i277_46_c_compstr1306_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_46_c_compstr1306_vt_select_15_b};

    // leftShiftStage0_uid24080_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x(MUX,24079)@104
    assign leftShiftStage0_uid24080_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24080_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_46_c_compstr1306_vt_join_q or leftShiftStage0Idx1_uid24078_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24080_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24080_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_46_c_compstr1306_vt_join_q;
            1'b1 : leftShiftStage0_uid24080_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24078_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24080_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24085_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x(MUX,24084)@104
    assign leftShiftStage1_uid24085_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24085_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_s or leftShiftStage0_uid24080_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24083_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24085_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24085_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q = leftShiftStage0_uid24080_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24085_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24083_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24085_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24090_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x(MUX,24089)@104
    assign leftShiftStage2_uid24090_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24090_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_s or leftShiftStage1_uid24085_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24088_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24090_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24090_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q = leftShiftStage1_uid24085_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24090_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24088_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24090_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_46_c_compstr1307_vt_select_28(BITSELECT,9244)@104
    assign i_shl_i_i_i_i_i77_i_46_c_compstr1307_vt_select_28_b = leftShiftStage2_uid24090_i_shl_i_i_i_i_i77_i_46_c_compstr0_shift_x_q[28:13];

    // redist442_i_shl_i_i_i_i_i77_i_46_c_compstr1307_vt_select_28_b_1(DELAY,28670)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist442_i_shl_i_i_i_i_i77_i_46_c_compstr1307_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_46_c_compstr1307_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_46_c_compstr1307_vt_join(BITJOIN,9243)@105
    assign i_shl_i_i_i_i_i77_i_46_c_compstr1307_vt_join_q = {redist442_i_shl_i_i_i_i_i77_i_46_c_compstr1307_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma(CHAINMULTADD,28166)@99 + 5
    // out q@105
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ah[0] <= redist863_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_93_tpl_91_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ah[1] <= redist862_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_92_tpl_91_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ch[0] <= redist609_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_93_tpl_91_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ch[1] <= redist608_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_92_tpl_91_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308(ADD,8462)@105
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compstr1303_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compstr1305_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compstr1304_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_46_c_compstr1307_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_46_c_compstr1307_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_o[33:0];

    // rightShiftStage0_uid17790_dupName_183_i_unnamed_c_compstr0_shift_x(MUX,17789)@105
    assign rightShiftStage0_uid17790_dupName_183_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17790_dupName_183_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_q or rightShiftStage0Idx1_uid17788_dupName_183_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17790_dupName_183_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17790_dupName_183_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_q;
            1'b1 : rightShiftStage0_uid17790_dupName_183_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17788_dupName_183_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17790_dupName_183_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17795_dupName_183_i_unnamed_c_compstr0_shift_x(MUX,17794)@105
    assign rightShiftStage1_uid17795_dupName_183_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17795_dupName_183_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17790_dupName_183_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17793_dupName_183_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17795_dupName_183_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17795_dupName_183_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17790_dupName_183_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17795_dupName_183_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17793_dupName_183_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17795_dupName_183_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17800_dupName_183_i_unnamed_c_compstr0_shift_x(MUX,17799)@105
    assign rightShiftStage2_uid17800_dupName_183_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17800_dupName_183_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17795_dupName_183_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17798_dupName_183_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17800_dupName_183_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17800_dupName_183_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17795_dupName_183_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17800_dupName_183_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17798_dupName_183_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17800_dupName_183_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1309_vt_select_20(BITSELECT,10069)@105
    assign i_unnamed_c_compstr1309_vt_select_20_b = rightShiftStage2_uid17800_dupName_183_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1309_vt_join(BITJOIN,10068)@105
    assign i_unnamed_c_compstr1309_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1309_vt_select_20_b};

    // i_conv_i_i_i_i97_i_46_c_compstr1310_sel_x(BITSELECT,3524)@105
    assign i_conv_i_i_i_i97_i_46_c_compstr1310_sel_x_b = i_unnamed_c_compstr1309_vt_join_q[15:0];

    // redist1212_i_conv_i_i_i_i97_i_46_c_compstr1310_sel_x_b_1(DELAY,29440)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1212_i_conv_i_i_i_i97_i_46_c_compstr1310_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_46_c_compstr1310_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17809_dupName_184_i_unnamed_c_compstr0_shift_x(BITSELECT,17808)@105
    assign rightShiftStage1Idx1Rng8_uid17809_dupName_184_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17808_dupName_184_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17811_dupName_184_i_unnamed_c_compstr0_shift_x(BITJOIN,17810)@105
    assign rightShiftStage1Idx1_uid17811_dupName_184_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17809_dupName_184_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17804_dupName_184_i_unnamed_c_compstr0_shift_x(BITSELECT,17803)@105
    assign rightShiftStage0Idx1Rng4_uid17804_dupName_184_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_q[33:4];

    // rightShiftStage0Idx1_uid17806_dupName_184_i_unnamed_c_compstr0_shift_x(BITJOIN,17805)@105
    assign rightShiftStage0Idx1_uid17806_dupName_184_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17804_dupName_184_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17808_dupName_184_i_unnamed_c_compstr0_shift_x(MUX,17807)@105
    assign rightShiftStage0_uid17808_dupName_184_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17808_dupName_184_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_q or rightShiftStage0Idx1_uid17806_dupName_184_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17808_dupName_184_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17808_dupName_184_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compstr1308_q;
            1'b1 : rightShiftStage0_uid17808_dupName_184_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17806_dupName_184_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17808_dupName_184_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17813_dupName_184_i_unnamed_c_compstr0_shift_x(MUX,17812)@105
    assign rightShiftStage1_uid17813_dupName_184_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17813_dupName_184_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17808_dupName_184_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17811_dupName_184_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17813_dupName_184_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17813_dupName_184_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17808_dupName_184_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17813_dupName_184_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17811_dupName_184_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17813_dupName_184_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1311_vt_select_21(BITSELECT,10072)@105
    assign i_unnamed_c_compstr1311_vt_select_21_b = rightShiftStage1_uid17813_dupName_184_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1311_vt_join(BITJOIN,10071)@105
    assign i_unnamed_c_compstr1311_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1311_vt_select_21_b};

    // i_unnamed_c_compstr1312_sel_x(BITSELECT,6059)@105
    assign i_unnamed_c_compstr1312_sel_x_b = i_unnamed_c_compstr1311_vt_join_q[15:0];

    // i_unnamed_c_compstr1313_BitSelect_for_a(BITSELECT,27507)@105
    assign i_unnamed_c_compstr1313_BitSelect_for_a_b = i_unnamed_c_compstr1312_sel_x_b[0:0];

    // i_unnamed_c_compstr1313_join(BITJOIN,27508)@105
    assign i_unnamed_c_compstr1313_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1313_BitSelect_for_a_b};

    // i_unnamed_c_compstr1313_vt_select_0(BITSELECT,10077)@105
    assign i_unnamed_c_compstr1313_vt_select_0_b = i_unnamed_c_compstr1313_join_q[0:0];

    // redist231_i_unnamed_c_compstr1313_vt_select_0_b_1(DELAY,28459)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist231_i_unnamed_c_compstr1313_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1313_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1313_vt_join(BITJOIN,10076)@106
    assign i_unnamed_c_compstr1313_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist231_i_unnamed_c_compstr1313_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_46_c_compstr1314(ADD,6919)@106
    assign i_add_i_i_i_i_i126_i_46_c_compstr1314_a = {1'b0, i_unnamed_c_compstr1313_vt_join_q};
    assign i_add_i_i_i_i_i126_i_46_c_compstr1314_b = {1'b0, redist1212_i_conv_i_i_i_i97_i_46_c_compstr1310_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_46_c_compstr1314_o = $unsigned(i_add_i_i_i_i_i126_i_46_c_compstr1314_a) + $unsigned(i_add_i_i_i_i_i126_i_46_c_compstr1314_b);
    assign i_add_i_i_i_i_i126_i_46_c_compstr1314_q = i_add_i_i_i_i_i126_i_46_c_compstr1314_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_46_c_compstr1314_sel_x(BITSELECT,2113)@106
    assign bgTrunc_i_add_i_i_i_i_i126_i_46_c_compstr1314_sel_x_b = i_add_i_i_i_i_i126_i_46_c_compstr1314_q[15:0];

    // i_conv_i_i_i_i_i75_i277_47_c_compstr1334_sel_x(BITSELECT,3654)@106
    assign i_conv_i_i_i_i_i75_i277_47_c_compstr1334_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_46_c_compstr1314_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_47_c_compstr1334_vt_select_15(BITSELECT,7517)@106
    assign i_conv_i_i_i_i_i75_i277_47_c_compstr1334_vt_select_15_b = i_conv_i_i_i_i_i75_i277_47_c_compstr1334_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_47_c_compstr1334_vt_join(BITJOIN,7516)@106
    assign i_conv_i_i_i_i_i75_i277_47_c_compstr1334_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_47_c_compstr1334_vt_select_15_b};

    // leftShiftStage0_uid24098_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x(MUX,24097)@106
    assign leftShiftStage0_uid24098_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24098_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_47_c_compstr1334_vt_join_q or leftShiftStage0Idx1_uid24096_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24098_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24098_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_47_c_compstr1334_vt_join_q;
            1'b1 : leftShiftStage0_uid24098_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24096_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24098_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24103_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x(MUX,24102)@106
    assign leftShiftStage1_uid24103_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24103_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_s or leftShiftStage0_uid24098_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24101_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24103_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24103_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q = leftShiftStage0_uid24098_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24103_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24101_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24103_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24108_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x(MUX,24107)@106
    assign leftShiftStage2_uid24108_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24108_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_s or leftShiftStage1_uid24103_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24106_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24108_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24108_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q = leftShiftStage1_uid24103_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24108_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24106_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24108_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_47_c_compstr1335_vt_select_28(BITSELECT,9247)@106
    assign i_shl_i_i_i_i_i77_i_47_c_compstr1335_vt_select_28_b = leftShiftStage2_uid24108_i_shl_i_i_i_i_i77_i_47_c_compstr0_shift_x_q[28:13];

    // redist441_i_shl_i_i_i_i_i77_i_47_c_compstr1335_vt_select_28_b_1(DELAY,28669)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist441_i_shl_i_i_i_i_i77_i_47_c_compstr1335_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_47_c_compstr1335_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_47_c_compstr1335_vt_join(BITJOIN,9246)@107
    assign i_shl_i_i_i_i_i77_i_47_c_compstr1335_vt_join_q = {redist441_i_shl_i_i_i_i_i77_i_47_c_compstr1335_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma(CHAINMULTADD,28167)@101 + 5
    // out q@107
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ah[0] <= redist865_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_95_tpl_93_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ah[1] <= redist864_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_94_tpl_93_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ch[0] <= redist611_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_95_tpl_93_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ch[1] <= redist610_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_94_tpl_93_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336(ADD,8463)@107
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compstr1331_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compstr1333_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compstr1332_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_47_c_compstr1335_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_47_c_compstr1335_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_o[33:0];

    // rightShiftStage0_uid17852_dupName_187_i_unnamed_c_compstr0_shift_x(MUX,17851)@107
    assign rightShiftStage0_uid17852_dupName_187_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17852_dupName_187_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_q or rightShiftStage0Idx1_uid17850_dupName_187_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17852_dupName_187_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17852_dupName_187_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_q;
            1'b1 : rightShiftStage0_uid17852_dupName_187_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17850_dupName_187_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17852_dupName_187_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17857_dupName_187_i_unnamed_c_compstr0_shift_x(MUX,17856)@107
    assign rightShiftStage1_uid17857_dupName_187_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17857_dupName_187_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17852_dupName_187_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17855_dupName_187_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17857_dupName_187_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17857_dupName_187_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17852_dupName_187_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17857_dupName_187_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17855_dupName_187_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17857_dupName_187_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17862_dupName_187_i_unnamed_c_compstr0_shift_x(MUX,17861)@107
    assign rightShiftStage2_uid17862_dupName_187_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17862_dupName_187_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17857_dupName_187_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17860_dupName_187_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17862_dupName_187_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17862_dupName_187_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17857_dupName_187_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17862_dupName_187_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17860_dupName_187_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17862_dupName_187_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1337_vt_select_20(BITSELECT,10091)@107
    assign i_unnamed_c_compstr1337_vt_select_20_b = rightShiftStage2_uid17862_dupName_187_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1337_vt_join(BITJOIN,10090)@107
    assign i_unnamed_c_compstr1337_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1337_vt_select_20_b};

    // i_conv_i_i_i_i97_i_47_c_compstr1338_sel_x(BITSELECT,3525)@107
    assign i_conv_i_i_i_i97_i_47_c_compstr1338_sel_x_b = i_unnamed_c_compstr1337_vt_join_q[15:0];

    // redist1211_i_conv_i_i_i_i97_i_47_c_compstr1338_sel_x_b_1(DELAY,29439)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1211_i_conv_i_i_i_i97_i_47_c_compstr1338_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_47_c_compstr1338_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17871_dupName_188_i_unnamed_c_compstr0_shift_x(BITSELECT,17870)@107
    assign rightShiftStage1Idx1Rng8_uid17871_dupName_188_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17870_dupName_188_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17873_dupName_188_i_unnamed_c_compstr0_shift_x(BITJOIN,17872)@107
    assign rightShiftStage1Idx1_uid17873_dupName_188_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17871_dupName_188_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17866_dupName_188_i_unnamed_c_compstr0_shift_x(BITSELECT,17865)@107
    assign rightShiftStage0Idx1Rng4_uid17866_dupName_188_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_q[33:4];

    // rightShiftStage0Idx1_uid17868_dupName_188_i_unnamed_c_compstr0_shift_x(BITJOIN,17867)@107
    assign rightShiftStage0Idx1_uid17868_dupName_188_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17866_dupName_188_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17870_dupName_188_i_unnamed_c_compstr0_shift_x(MUX,17869)@107
    assign rightShiftStage0_uid17870_dupName_188_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17870_dupName_188_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_q or rightShiftStage0Idx1_uid17868_dupName_188_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17870_dupName_188_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17870_dupName_188_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compstr1336_q;
            1'b1 : rightShiftStage0_uid17870_dupName_188_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17868_dupName_188_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17870_dupName_188_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17875_dupName_188_i_unnamed_c_compstr0_shift_x(MUX,17874)@107
    assign rightShiftStage1_uid17875_dupName_188_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17875_dupName_188_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17870_dupName_188_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17873_dupName_188_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17875_dupName_188_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17875_dupName_188_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17870_dupName_188_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17875_dupName_188_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17873_dupName_188_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17875_dupName_188_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1339_vt_select_21(BITSELECT,10094)@107
    assign i_unnamed_c_compstr1339_vt_select_21_b = rightShiftStage1_uid17875_dupName_188_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1339_vt_join(BITJOIN,10093)@107
    assign i_unnamed_c_compstr1339_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1339_vt_select_21_b};

    // i_unnamed_c_compstr1340_sel_x(BITSELECT,6061)@107
    assign i_unnamed_c_compstr1340_sel_x_b = i_unnamed_c_compstr1339_vt_join_q[15:0];

    // i_unnamed_c_compstr1341_BitSelect_for_a(BITSELECT,27511)@107
    assign i_unnamed_c_compstr1341_BitSelect_for_a_b = i_unnamed_c_compstr1340_sel_x_b[0:0];

    // i_unnamed_c_compstr1341_join(BITJOIN,27512)@107
    assign i_unnamed_c_compstr1341_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1341_BitSelect_for_a_b};

    // i_unnamed_c_compstr1341_vt_select_0(BITSELECT,10102)@107
    assign i_unnamed_c_compstr1341_vt_select_0_b = i_unnamed_c_compstr1341_join_q[0:0];

    // redist229_i_unnamed_c_compstr1341_vt_select_0_b_1(DELAY,28457)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist229_i_unnamed_c_compstr1341_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1341_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1341_vt_join(BITJOIN,10101)@108
    assign i_unnamed_c_compstr1341_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist229_i_unnamed_c_compstr1341_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_47_c_compstr1342(ADD,6920)@108
    assign i_add_i_i_i_i_i126_i_47_c_compstr1342_a = {1'b0, i_unnamed_c_compstr1341_vt_join_q};
    assign i_add_i_i_i_i_i126_i_47_c_compstr1342_b = {1'b0, redist1211_i_conv_i_i_i_i97_i_47_c_compstr1338_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_47_c_compstr1342_o = $unsigned(i_add_i_i_i_i_i126_i_47_c_compstr1342_a) + $unsigned(i_add_i_i_i_i_i126_i_47_c_compstr1342_b);
    assign i_add_i_i_i_i_i126_i_47_c_compstr1342_q = i_add_i_i_i_i_i126_i_47_c_compstr1342_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_47_c_compstr1342_sel_x(BITSELECT,2114)@108
    assign bgTrunc_i_add_i_i_i_i_i126_i_47_c_compstr1342_sel_x_b = i_add_i_i_i_i_i126_i_47_c_compstr1342_q[15:0];

    // i_conv_i_i_i_i_i75_i277_48_c_compstr1362_sel_x(BITSELECT,3655)@108
    assign i_conv_i_i_i_i_i75_i277_48_c_compstr1362_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_47_c_compstr1342_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_48_c_compstr1362_vt_select_15(BITSELECT,7521)@108
    assign i_conv_i_i_i_i_i75_i277_48_c_compstr1362_vt_select_15_b = i_conv_i_i_i_i_i75_i277_48_c_compstr1362_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_48_c_compstr1362_vt_join(BITJOIN,7520)@108
    assign i_conv_i_i_i_i_i75_i277_48_c_compstr1362_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_48_c_compstr1362_vt_select_15_b};

    // leftShiftStage0_uid24116_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x(MUX,24115)@108
    assign leftShiftStage0_uid24116_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24116_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_48_c_compstr1362_vt_join_q or leftShiftStage0Idx1_uid24114_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24116_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24116_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_48_c_compstr1362_vt_join_q;
            1'b1 : leftShiftStage0_uid24116_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24114_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24116_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24121_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x(MUX,24120)@108
    assign leftShiftStage1_uid24121_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24121_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_s or leftShiftStage0_uid24116_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24119_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24121_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24121_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q = leftShiftStage0_uid24116_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24121_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24119_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24121_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24126_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x(MUX,24125)@108
    assign leftShiftStage2_uid24126_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24126_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_s or leftShiftStage1_uid24121_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24124_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24126_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24126_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q = leftShiftStage1_uid24121_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24126_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24124_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24126_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_48_c_compstr1363_vt_select_28(BITSELECT,9250)@108
    assign i_shl_i_i_i_i_i77_i_48_c_compstr1363_vt_select_28_b = leftShiftStage2_uid24126_i_shl_i_i_i_i_i77_i_48_c_compstr0_shift_x_q[28:13];

    // redist440_i_shl_i_i_i_i_i77_i_48_c_compstr1363_vt_select_28_b_1(DELAY,28668)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist440_i_shl_i_i_i_i_i77_i_48_c_compstr1363_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_48_c_compstr1363_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_48_c_compstr1363_vt_join(BITJOIN,9249)@109
    assign i_shl_i_i_i_i_i77_i_48_c_compstr1363_vt_join_q = {redist440_i_shl_i_i_i_i_i77_i_48_c_compstr1363_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma(CHAINMULTADD,28168)@103 + 5
    // out q@109
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ah[0] <= redist867_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_97_tpl_95_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ah[1] <= redist866_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_96_tpl_95_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ch[0] <= redist613_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_97_tpl_95_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ch[1] <= redist612_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_96_tpl_95_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364(ADD,8464)@109
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compstr1359_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compstr1361_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compstr1360_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_48_c_compstr1363_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_48_c_compstr1363_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_o[33:0];

    // rightShiftStage0_uid17914_dupName_191_i_unnamed_c_compstr0_shift_x(MUX,17913)@109
    assign rightShiftStage0_uid17914_dupName_191_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17914_dupName_191_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_q or rightShiftStage0Idx1_uid17912_dupName_191_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17914_dupName_191_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17914_dupName_191_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_q;
            1'b1 : rightShiftStage0_uid17914_dupName_191_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17912_dupName_191_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17914_dupName_191_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17919_dupName_191_i_unnamed_c_compstr0_shift_x(MUX,17918)@109
    assign rightShiftStage1_uid17919_dupName_191_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17919_dupName_191_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17914_dupName_191_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17917_dupName_191_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17919_dupName_191_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17919_dupName_191_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17914_dupName_191_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17919_dupName_191_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17917_dupName_191_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17919_dupName_191_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17924_dupName_191_i_unnamed_c_compstr0_shift_x(MUX,17923)@109
    assign rightShiftStage2_uid17924_dupName_191_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17924_dupName_191_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17919_dupName_191_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17922_dupName_191_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17924_dupName_191_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17924_dupName_191_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17919_dupName_191_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17924_dupName_191_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17922_dupName_191_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17924_dupName_191_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1365_vt_select_20(BITSELECT,10119)@109
    assign i_unnamed_c_compstr1365_vt_select_20_b = rightShiftStage2_uid17924_dupName_191_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1365_vt_join(BITJOIN,10118)@109
    assign i_unnamed_c_compstr1365_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1365_vt_select_20_b};

    // i_conv_i_i_i_i97_i_48_c_compstr1366_sel_x(BITSELECT,3526)@109
    assign i_conv_i_i_i_i97_i_48_c_compstr1366_sel_x_b = i_unnamed_c_compstr1365_vt_join_q[15:0];

    // redist1210_i_conv_i_i_i_i97_i_48_c_compstr1366_sel_x_b_1(DELAY,29438)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1210_i_conv_i_i_i_i97_i_48_c_compstr1366_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_48_c_compstr1366_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17933_dupName_192_i_unnamed_c_compstr0_shift_x(BITSELECT,17932)@109
    assign rightShiftStage1Idx1Rng8_uid17933_dupName_192_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17932_dupName_192_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17935_dupName_192_i_unnamed_c_compstr0_shift_x(BITJOIN,17934)@109
    assign rightShiftStage1Idx1_uid17935_dupName_192_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17933_dupName_192_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17928_dupName_192_i_unnamed_c_compstr0_shift_x(BITSELECT,17927)@109
    assign rightShiftStage0Idx1Rng4_uid17928_dupName_192_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_q[33:4];

    // rightShiftStage0Idx1_uid17930_dupName_192_i_unnamed_c_compstr0_shift_x(BITJOIN,17929)@109
    assign rightShiftStage0Idx1_uid17930_dupName_192_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17928_dupName_192_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17932_dupName_192_i_unnamed_c_compstr0_shift_x(MUX,17931)@109
    assign rightShiftStage0_uid17932_dupName_192_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17932_dupName_192_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_q or rightShiftStage0Idx1_uid17930_dupName_192_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17932_dupName_192_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17932_dupName_192_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compstr1364_q;
            1'b1 : rightShiftStage0_uid17932_dupName_192_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17930_dupName_192_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17932_dupName_192_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17937_dupName_192_i_unnamed_c_compstr0_shift_x(MUX,17936)@109
    assign rightShiftStage1_uid17937_dupName_192_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17937_dupName_192_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17932_dupName_192_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17935_dupName_192_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17937_dupName_192_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17937_dupName_192_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17932_dupName_192_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17937_dupName_192_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17935_dupName_192_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17937_dupName_192_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1367_vt_select_21(BITSELECT,10122)@109
    assign i_unnamed_c_compstr1367_vt_select_21_b = rightShiftStage1_uid17937_dupName_192_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1367_vt_join(BITJOIN,10121)@109
    assign i_unnamed_c_compstr1367_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1367_vt_select_21_b};

    // i_unnamed_c_compstr1368_sel_x(BITSELECT,6064)@109
    assign i_unnamed_c_compstr1368_sel_x_b = i_unnamed_c_compstr1367_vt_join_q[15:0];

    // i_unnamed_c_compstr1369_BitSelect_for_a(BITSELECT,27515)@109
    assign i_unnamed_c_compstr1369_BitSelect_for_a_b = i_unnamed_c_compstr1368_sel_x_b[0:0];

    // i_unnamed_c_compstr1369_join(BITJOIN,27516)@109
    assign i_unnamed_c_compstr1369_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1369_BitSelect_for_a_b};

    // i_unnamed_c_compstr1369_vt_select_0(BITSELECT,10127)@109
    assign i_unnamed_c_compstr1369_vt_select_0_b = i_unnamed_c_compstr1369_join_q[0:0];

    // redist227_i_unnamed_c_compstr1369_vt_select_0_b_1(DELAY,28455)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist227_i_unnamed_c_compstr1369_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1369_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1369_vt_join(BITJOIN,10126)@110
    assign i_unnamed_c_compstr1369_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist227_i_unnamed_c_compstr1369_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_48_c_compstr1370(ADD,6921)@110
    assign i_add_i_i_i_i_i126_i_48_c_compstr1370_a = {1'b0, i_unnamed_c_compstr1369_vt_join_q};
    assign i_add_i_i_i_i_i126_i_48_c_compstr1370_b = {1'b0, redist1210_i_conv_i_i_i_i97_i_48_c_compstr1366_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_48_c_compstr1370_o = $unsigned(i_add_i_i_i_i_i126_i_48_c_compstr1370_a) + $unsigned(i_add_i_i_i_i_i126_i_48_c_compstr1370_b);
    assign i_add_i_i_i_i_i126_i_48_c_compstr1370_q = i_add_i_i_i_i_i126_i_48_c_compstr1370_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_48_c_compstr1370_sel_x(BITSELECT,2115)@110
    assign bgTrunc_i_add_i_i_i_i_i126_i_48_c_compstr1370_sel_x_b = i_add_i_i_i_i_i126_i_48_c_compstr1370_q[15:0];

    // i_conv_i_i_i_i_i75_i277_49_c_compstr1390_sel_x(BITSELECT,3656)@110
    assign i_conv_i_i_i_i_i75_i277_49_c_compstr1390_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_48_c_compstr1370_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_49_c_compstr1390_vt_select_15(BITSELECT,7525)@110
    assign i_conv_i_i_i_i_i75_i277_49_c_compstr1390_vt_select_15_b = i_conv_i_i_i_i_i75_i277_49_c_compstr1390_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_49_c_compstr1390_vt_join(BITJOIN,7524)@110
    assign i_conv_i_i_i_i_i75_i277_49_c_compstr1390_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_49_c_compstr1390_vt_select_15_b};

    // leftShiftStage0_uid24134_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x(MUX,24133)@110
    assign leftShiftStage0_uid24134_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24134_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_49_c_compstr1390_vt_join_q or leftShiftStage0Idx1_uid24132_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24134_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24134_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_49_c_compstr1390_vt_join_q;
            1'b1 : leftShiftStage0_uid24134_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24132_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24134_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24139_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x(MUX,24138)@110
    assign leftShiftStage1_uid24139_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24139_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_s or leftShiftStage0_uid24134_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24137_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24139_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24139_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q = leftShiftStage0_uid24134_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24139_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24137_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24139_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24144_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x(MUX,24143)@110
    assign leftShiftStage2_uid24144_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24144_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_s or leftShiftStage1_uid24139_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24142_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24144_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24144_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q = leftShiftStage1_uid24139_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24144_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24142_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24144_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_49_c_compstr1391_vt_select_28(BITSELECT,9253)@110
    assign i_shl_i_i_i_i_i77_i_49_c_compstr1391_vt_select_28_b = leftShiftStage2_uid24144_i_shl_i_i_i_i_i77_i_49_c_compstr0_shift_x_q[28:13];

    // redist439_i_shl_i_i_i_i_i77_i_49_c_compstr1391_vt_select_28_b_1(DELAY,28667)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist439_i_shl_i_i_i_i_i77_i_49_c_compstr1391_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_49_c_compstr1391_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_49_c_compstr1391_vt_join(BITJOIN,9252)@111
    assign i_shl_i_i_i_i_i77_i_49_c_compstr1391_vt_join_q = {redist439_i_shl_i_i_i_i_i77_i_49_c_compstr1391_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma(CHAINMULTADD,28169)@105 + 5
    // out q@111
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ah[0] <= redist869_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_99_tpl_97_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ah[1] <= redist868_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_98_tpl_97_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ch[0] <= redist615_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_99_tpl_97_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ch[1] <= redist614_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_98_tpl_97_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392(ADD,8465)@111
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compstr1387_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compstr1389_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compstr1388_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_49_c_compstr1391_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_49_c_compstr1391_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_o[33:0];

    // rightShiftStage0_uid17976_dupName_195_i_unnamed_c_compstr0_shift_x(MUX,17975)@111
    assign rightShiftStage0_uid17976_dupName_195_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17976_dupName_195_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_q or rightShiftStage0Idx1_uid17974_dupName_195_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17976_dupName_195_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17976_dupName_195_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_q;
            1'b1 : rightShiftStage0_uid17976_dupName_195_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17974_dupName_195_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17976_dupName_195_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17981_dupName_195_i_unnamed_c_compstr0_shift_x(MUX,17980)@111
    assign rightShiftStage1_uid17981_dupName_195_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17981_dupName_195_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17976_dupName_195_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17979_dupName_195_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17981_dupName_195_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17981_dupName_195_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17976_dupName_195_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17981_dupName_195_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17979_dupName_195_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17981_dupName_195_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17986_dupName_195_i_unnamed_c_compstr0_shift_x(MUX,17985)@111
    assign rightShiftStage2_uid17986_dupName_195_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17986_dupName_195_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid17981_dupName_195_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid17984_dupName_195_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17986_dupName_195_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid17986_dupName_195_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid17981_dupName_195_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid17986_dupName_195_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid17984_dupName_195_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid17986_dupName_195_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1393_vt_select_20(BITSELECT,10146)@111
    assign i_unnamed_c_compstr1393_vt_select_20_b = rightShiftStage2_uid17986_dupName_195_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1393_vt_join(BITJOIN,10145)@111
    assign i_unnamed_c_compstr1393_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1393_vt_select_20_b};

    // i_conv_i_i_i_i97_i_49_c_compstr1394_sel_x(BITSELECT,3527)@111
    assign i_conv_i_i_i_i97_i_49_c_compstr1394_sel_x_b = i_unnamed_c_compstr1393_vt_join_q[15:0];

    // redist1209_i_conv_i_i_i_i97_i_49_c_compstr1394_sel_x_b_1(DELAY,29437)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1209_i_conv_i_i_i_i97_i_49_c_compstr1394_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_49_c_compstr1394_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17995_dupName_196_i_unnamed_c_compstr0_shift_x(BITSELECT,17994)@111
    assign rightShiftStage1Idx1Rng8_uid17995_dupName_196_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid17994_dupName_196_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17997_dupName_196_i_unnamed_c_compstr0_shift_x(BITJOIN,17996)@111
    assign rightShiftStage1Idx1_uid17997_dupName_196_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid17995_dupName_196_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17990_dupName_196_i_unnamed_c_compstr0_shift_x(BITSELECT,17989)@111
    assign rightShiftStage0Idx1Rng4_uid17990_dupName_196_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_q[33:4];

    // rightShiftStage0Idx1_uid17992_dupName_196_i_unnamed_c_compstr0_shift_x(BITJOIN,17991)@111
    assign rightShiftStage0Idx1_uid17992_dupName_196_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid17990_dupName_196_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid17994_dupName_196_i_unnamed_c_compstr0_shift_x(MUX,17993)@111
    assign rightShiftStage0_uid17994_dupName_196_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17994_dupName_196_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_q or rightShiftStage0Idx1_uid17992_dupName_196_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17994_dupName_196_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid17994_dupName_196_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compstr1392_q;
            1'b1 : rightShiftStage0_uid17994_dupName_196_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid17992_dupName_196_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid17994_dupName_196_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17999_dupName_196_i_unnamed_c_compstr0_shift_x(MUX,17998)@111
    assign rightShiftStage1_uid17999_dupName_196_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17999_dupName_196_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid17994_dupName_196_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid17997_dupName_196_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17999_dupName_196_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid17999_dupName_196_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid17994_dupName_196_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid17999_dupName_196_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid17997_dupName_196_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid17999_dupName_196_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1395_vt_select_21(BITSELECT,10149)@111
    assign i_unnamed_c_compstr1395_vt_select_21_b = rightShiftStage1_uid17999_dupName_196_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1395_vt_join(BITJOIN,10148)@111
    assign i_unnamed_c_compstr1395_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1395_vt_select_21_b};

    // i_unnamed_c_compstr1396_sel_x(BITSELECT,6066)@111
    assign i_unnamed_c_compstr1396_sel_x_b = i_unnamed_c_compstr1395_vt_join_q[15:0];

    // i_unnamed_c_compstr1397_BitSelect_for_a(BITSELECT,27521)@111
    assign i_unnamed_c_compstr1397_BitSelect_for_a_b = i_unnamed_c_compstr1396_sel_x_b[0:0];

    // i_unnamed_c_compstr1397_join(BITJOIN,27522)@111
    assign i_unnamed_c_compstr1397_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1397_BitSelect_for_a_b};

    // i_unnamed_c_compstr1397_vt_select_0(BITSELECT,10154)@111
    assign i_unnamed_c_compstr1397_vt_select_0_b = i_unnamed_c_compstr1397_join_q[0:0];

    // redist224_i_unnamed_c_compstr1397_vt_select_0_b_1(DELAY,28452)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist224_i_unnamed_c_compstr1397_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1397_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1397_vt_join(BITJOIN,10153)@112
    assign i_unnamed_c_compstr1397_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist224_i_unnamed_c_compstr1397_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_49_c_compstr1398(ADD,6922)@112
    assign i_add_i_i_i_i_i126_i_49_c_compstr1398_a = {1'b0, i_unnamed_c_compstr1397_vt_join_q};
    assign i_add_i_i_i_i_i126_i_49_c_compstr1398_b = {1'b0, redist1209_i_conv_i_i_i_i97_i_49_c_compstr1394_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_49_c_compstr1398_o = $unsigned(i_add_i_i_i_i_i126_i_49_c_compstr1398_a) + $unsigned(i_add_i_i_i_i_i126_i_49_c_compstr1398_b);
    assign i_add_i_i_i_i_i126_i_49_c_compstr1398_q = i_add_i_i_i_i_i126_i_49_c_compstr1398_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_49_c_compstr1398_sel_x(BITSELECT,2116)@112
    assign bgTrunc_i_add_i_i_i_i_i126_i_49_c_compstr1398_sel_x_b = i_add_i_i_i_i_i126_i_49_c_compstr1398_q[15:0];

    // i_conv_i_i_i_i_i75_i277_50_c_compstr1418_sel_x(BITSELECT,3658)@112
    assign i_conv_i_i_i_i_i75_i277_50_c_compstr1418_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_49_c_compstr1398_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_50_c_compstr1418_vt_select_15(BITSELECT,7533)@112
    assign i_conv_i_i_i_i_i75_i277_50_c_compstr1418_vt_select_15_b = i_conv_i_i_i_i_i75_i277_50_c_compstr1418_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_50_c_compstr1418_vt_join(BITJOIN,7532)@112
    assign i_conv_i_i_i_i_i75_i277_50_c_compstr1418_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_50_c_compstr1418_vt_select_15_b};

    // leftShiftStage0_uid24170_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x(MUX,24169)@112
    assign leftShiftStage0_uid24170_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24170_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_50_c_compstr1418_vt_join_q or leftShiftStage0Idx1_uid24168_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24170_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24170_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_50_c_compstr1418_vt_join_q;
            1'b1 : leftShiftStage0_uid24170_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24168_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24170_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24175_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x(MUX,24174)@112
    assign leftShiftStage1_uid24175_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24175_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_s or leftShiftStage0_uid24170_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24173_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24175_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24175_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q = leftShiftStage0_uid24170_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24175_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24173_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24175_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24180_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x(MUX,24179)@112
    assign leftShiftStage2_uid24180_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24180_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_s or leftShiftStage1_uid24175_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24178_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24180_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24180_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q = leftShiftStage1_uid24175_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24180_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24178_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24180_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_50_c_compstr1419_vt_select_28(BITSELECT,9259)@112
    assign i_shl_i_i_i_i_i77_i_50_c_compstr1419_vt_select_28_b = leftShiftStage2_uid24180_i_shl_i_i_i_i_i77_i_50_c_compstr0_shift_x_q[28:13];

    // redist437_i_shl_i_i_i_i_i77_i_50_c_compstr1419_vt_select_28_b_1(DELAY,28665)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist437_i_shl_i_i_i_i_i77_i_50_c_compstr1419_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_50_c_compstr1419_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_50_c_compstr1419_vt_join(BITJOIN,9258)@113
    assign i_shl_i_i_i_i_i77_i_50_c_compstr1419_vt_join_q = {redist437_i_shl_i_i_i_i_i77_i_50_c_compstr1419_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma(CHAINMULTADD,28171)@107 + 5
    // out q@113
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ah[0] <= redist871_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_101_tpl_99_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ah[1] <= redist870_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_100_tpl_99_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ch[0] <= redist617_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_101_tpl_99_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ch[1] <= redist616_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_100_tpl_99_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420(ADD,8467)@113
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compstr1415_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compstr1417_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compstr1416_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_50_c_compstr1419_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_50_c_compstr1419_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_o[33:0];

    // rightShiftStage0_uid18038_dupName_199_i_unnamed_c_compstr0_shift_x(MUX,18037)@113
    assign rightShiftStage0_uid18038_dupName_199_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18038_dupName_199_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_q or rightShiftStage0Idx1_uid18036_dupName_199_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18038_dupName_199_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18038_dupName_199_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_q;
            1'b1 : rightShiftStage0_uid18038_dupName_199_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18036_dupName_199_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18038_dupName_199_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18043_dupName_199_i_unnamed_c_compstr0_shift_x(MUX,18042)@113
    assign rightShiftStage1_uid18043_dupName_199_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18043_dupName_199_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18038_dupName_199_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18041_dupName_199_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18043_dupName_199_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18043_dupName_199_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18038_dupName_199_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18043_dupName_199_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18041_dupName_199_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18043_dupName_199_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18048_dupName_199_i_unnamed_c_compstr0_shift_x(MUX,18047)@113
    assign rightShiftStage2_uid18048_dupName_199_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18048_dupName_199_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18043_dupName_199_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18046_dupName_199_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18048_dupName_199_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18048_dupName_199_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18043_dupName_199_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18048_dupName_199_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18046_dupName_199_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18048_dupName_199_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1421_vt_select_20(BITSELECT,10168)@113
    assign i_unnamed_c_compstr1421_vt_select_20_b = rightShiftStage2_uid18048_dupName_199_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1421_vt_join(BITJOIN,10167)@113
    assign i_unnamed_c_compstr1421_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1421_vt_select_20_b};

    // i_conv_i_i_i_i97_i_50_c_compstr1422_sel_x(BITSELECT,3529)@113
    assign i_conv_i_i_i_i97_i_50_c_compstr1422_sel_x_b = i_unnamed_c_compstr1421_vt_join_q[15:0];

    // redist1207_i_conv_i_i_i_i97_i_50_c_compstr1422_sel_x_b_1(DELAY,29435)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1207_i_conv_i_i_i_i97_i_50_c_compstr1422_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_50_c_compstr1422_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18057_dupName_200_i_unnamed_c_compstr0_shift_x(BITSELECT,18056)@113
    assign rightShiftStage1Idx1Rng8_uid18057_dupName_200_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18056_dupName_200_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18059_dupName_200_i_unnamed_c_compstr0_shift_x(BITJOIN,18058)@113
    assign rightShiftStage1Idx1_uid18059_dupName_200_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18057_dupName_200_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18052_dupName_200_i_unnamed_c_compstr0_shift_x(BITSELECT,18051)@113
    assign rightShiftStage0Idx1Rng4_uid18052_dupName_200_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_q[33:4];

    // rightShiftStage0Idx1_uid18054_dupName_200_i_unnamed_c_compstr0_shift_x(BITJOIN,18053)@113
    assign rightShiftStage0Idx1_uid18054_dupName_200_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18052_dupName_200_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18056_dupName_200_i_unnamed_c_compstr0_shift_x(MUX,18055)@113
    assign rightShiftStage0_uid18056_dupName_200_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18056_dupName_200_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_q or rightShiftStage0Idx1_uid18054_dupName_200_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18056_dupName_200_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18056_dupName_200_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compstr1420_q;
            1'b1 : rightShiftStage0_uid18056_dupName_200_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18054_dupName_200_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18056_dupName_200_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18061_dupName_200_i_unnamed_c_compstr0_shift_x(MUX,18060)@113
    assign rightShiftStage1_uid18061_dupName_200_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18061_dupName_200_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18056_dupName_200_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18059_dupName_200_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18061_dupName_200_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18061_dupName_200_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18056_dupName_200_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18061_dupName_200_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18059_dupName_200_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18061_dupName_200_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1423_vt_select_21(BITSELECT,10171)@113
    assign i_unnamed_c_compstr1423_vt_select_21_b = rightShiftStage1_uid18061_dupName_200_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1423_vt_join(BITJOIN,10170)@113
    assign i_unnamed_c_compstr1423_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1423_vt_select_21_b};

    // i_unnamed_c_compstr1424_sel_x(BITSELECT,6068)@113
    assign i_unnamed_c_compstr1424_sel_x_b = i_unnamed_c_compstr1423_vt_join_q[15:0];

    // i_unnamed_c_compstr1425_BitSelect_for_a(BITSELECT,27525)@113
    assign i_unnamed_c_compstr1425_BitSelect_for_a_b = i_unnamed_c_compstr1424_sel_x_b[0:0];

    // i_unnamed_c_compstr1425_join(BITJOIN,27526)@113
    assign i_unnamed_c_compstr1425_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1425_BitSelect_for_a_b};

    // i_unnamed_c_compstr1425_vt_select_0(BITSELECT,10176)@113
    assign i_unnamed_c_compstr1425_vt_select_0_b = i_unnamed_c_compstr1425_join_q[0:0];

    // redist222_i_unnamed_c_compstr1425_vt_select_0_b_1(DELAY,28450)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist222_i_unnamed_c_compstr1425_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1425_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1425_vt_join(BITJOIN,10175)@114
    assign i_unnamed_c_compstr1425_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist222_i_unnamed_c_compstr1425_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_50_c_compstr1426(ADD,6924)@114
    assign i_add_i_i_i_i_i126_i_50_c_compstr1426_a = {1'b0, i_unnamed_c_compstr1425_vt_join_q};
    assign i_add_i_i_i_i_i126_i_50_c_compstr1426_b = {1'b0, redist1207_i_conv_i_i_i_i97_i_50_c_compstr1422_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_50_c_compstr1426_o = $unsigned(i_add_i_i_i_i_i126_i_50_c_compstr1426_a) + $unsigned(i_add_i_i_i_i_i126_i_50_c_compstr1426_b);
    assign i_add_i_i_i_i_i126_i_50_c_compstr1426_q = i_add_i_i_i_i_i126_i_50_c_compstr1426_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_50_c_compstr1426_sel_x(BITSELECT,2118)@114
    assign bgTrunc_i_add_i_i_i_i_i126_i_50_c_compstr1426_sel_x_b = i_add_i_i_i_i_i126_i_50_c_compstr1426_q[15:0];

    // i_conv_i_i_i_i_i75_i277_51_c_compstr1446_sel_x(BITSELECT,3659)@114
    assign i_conv_i_i_i_i_i75_i277_51_c_compstr1446_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_50_c_compstr1426_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_51_c_compstr1446_vt_select_15(BITSELECT,7537)@114
    assign i_conv_i_i_i_i_i75_i277_51_c_compstr1446_vt_select_15_b = i_conv_i_i_i_i_i75_i277_51_c_compstr1446_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_51_c_compstr1446_vt_join(BITJOIN,7536)@114
    assign i_conv_i_i_i_i_i75_i277_51_c_compstr1446_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_51_c_compstr1446_vt_select_15_b};

    // leftShiftStage0_uid24188_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x(MUX,24187)@114
    assign leftShiftStage0_uid24188_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24188_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_51_c_compstr1446_vt_join_q or leftShiftStage0Idx1_uid24186_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24188_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24188_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_51_c_compstr1446_vt_join_q;
            1'b1 : leftShiftStage0_uid24188_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24186_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24188_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24193_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x(MUX,24192)@114
    assign leftShiftStage1_uid24193_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24193_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_s or leftShiftStage0_uid24188_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24191_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24193_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24193_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q = leftShiftStage0_uid24188_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24193_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24191_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24193_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24198_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x(MUX,24197)@114
    assign leftShiftStage2_uid24198_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24198_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_s or leftShiftStage1_uid24193_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24196_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24198_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24198_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q = leftShiftStage1_uid24193_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24198_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24196_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24198_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_51_c_compstr1447_vt_select_28(BITSELECT,9262)@114
    assign i_shl_i_i_i_i_i77_i_51_c_compstr1447_vt_select_28_b = leftShiftStage2_uid24198_i_shl_i_i_i_i_i77_i_51_c_compstr0_shift_x_q[28:13];

    // redist436_i_shl_i_i_i_i_i77_i_51_c_compstr1447_vt_select_28_b_1(DELAY,28664)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist436_i_shl_i_i_i_i_i77_i_51_c_compstr1447_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_51_c_compstr1447_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_51_c_compstr1447_vt_join(BITJOIN,9261)@115
    assign i_shl_i_i_i_i_i77_i_51_c_compstr1447_vt_join_q = {redist436_i_shl_i_i_i_i_i77_i_51_c_compstr1447_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma(CHAINMULTADD,28172)@109 + 5
    // out q@115
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ah[0] <= redist873_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_103_tpl_101_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ah[1] <= redist872_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_102_tpl_101_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ch[0] <= redist619_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_103_tpl_101_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ch[1] <= redist618_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_102_tpl_101_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448(ADD,8468)@115
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compstr1443_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compstr1445_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compstr1444_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_51_c_compstr1447_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_51_c_compstr1447_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_o[33:0];

    // rightShiftStage0_uid18100_dupName_203_i_unnamed_c_compstr0_shift_x(MUX,18099)@115
    assign rightShiftStage0_uid18100_dupName_203_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18100_dupName_203_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_q or rightShiftStage0Idx1_uid18098_dupName_203_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18100_dupName_203_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18100_dupName_203_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_q;
            1'b1 : rightShiftStage0_uid18100_dupName_203_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18098_dupName_203_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18100_dupName_203_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18105_dupName_203_i_unnamed_c_compstr0_shift_x(MUX,18104)@115
    assign rightShiftStage1_uid18105_dupName_203_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18105_dupName_203_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18100_dupName_203_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18103_dupName_203_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18105_dupName_203_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18105_dupName_203_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18100_dupName_203_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18105_dupName_203_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18103_dupName_203_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18105_dupName_203_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18110_dupName_203_i_unnamed_c_compstr0_shift_x(MUX,18109)@115
    assign rightShiftStage2_uid18110_dupName_203_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18110_dupName_203_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18105_dupName_203_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18108_dupName_203_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18110_dupName_203_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18110_dupName_203_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18105_dupName_203_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18110_dupName_203_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18108_dupName_203_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18110_dupName_203_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1449_vt_select_20(BITSELECT,10190)@115
    assign i_unnamed_c_compstr1449_vt_select_20_b = rightShiftStage2_uid18110_dupName_203_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1449_vt_join(BITJOIN,10189)@115
    assign i_unnamed_c_compstr1449_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1449_vt_select_20_b};

    // i_conv_i_i_i_i97_i_51_c_compstr1450_sel_x(BITSELECT,3530)@115
    assign i_conv_i_i_i_i97_i_51_c_compstr1450_sel_x_b = i_unnamed_c_compstr1449_vt_join_q[15:0];

    // redist1206_i_conv_i_i_i_i97_i_51_c_compstr1450_sel_x_b_1(DELAY,29434)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1206_i_conv_i_i_i_i97_i_51_c_compstr1450_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_51_c_compstr1450_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18119_dupName_204_i_unnamed_c_compstr0_shift_x(BITSELECT,18118)@115
    assign rightShiftStage1Idx1Rng8_uid18119_dupName_204_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18118_dupName_204_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18121_dupName_204_i_unnamed_c_compstr0_shift_x(BITJOIN,18120)@115
    assign rightShiftStage1Idx1_uid18121_dupName_204_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18119_dupName_204_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18114_dupName_204_i_unnamed_c_compstr0_shift_x(BITSELECT,18113)@115
    assign rightShiftStage0Idx1Rng4_uid18114_dupName_204_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_q[33:4];

    // rightShiftStage0Idx1_uid18116_dupName_204_i_unnamed_c_compstr0_shift_x(BITJOIN,18115)@115
    assign rightShiftStage0Idx1_uid18116_dupName_204_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18114_dupName_204_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18118_dupName_204_i_unnamed_c_compstr0_shift_x(MUX,18117)@115
    assign rightShiftStage0_uid18118_dupName_204_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18118_dupName_204_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_q or rightShiftStage0Idx1_uid18116_dupName_204_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18118_dupName_204_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18118_dupName_204_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compstr1448_q;
            1'b1 : rightShiftStage0_uid18118_dupName_204_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18116_dupName_204_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18118_dupName_204_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18123_dupName_204_i_unnamed_c_compstr0_shift_x(MUX,18122)@115
    assign rightShiftStage1_uid18123_dupName_204_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18123_dupName_204_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18118_dupName_204_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18121_dupName_204_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18123_dupName_204_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18123_dupName_204_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18118_dupName_204_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18123_dupName_204_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18121_dupName_204_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18123_dupName_204_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1451_vt_select_21(BITSELECT,10193)@115
    assign i_unnamed_c_compstr1451_vt_select_21_b = rightShiftStage1_uid18123_dupName_204_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1451_vt_join(BITJOIN,10192)@115
    assign i_unnamed_c_compstr1451_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1451_vt_select_21_b};

    // i_unnamed_c_compstr1452_sel_x(BITSELECT,6070)@115
    assign i_unnamed_c_compstr1452_sel_x_b = i_unnamed_c_compstr1451_vt_join_q[15:0];

    // i_unnamed_c_compstr1453_BitSelect_for_a(BITSELECT,27529)@115
    assign i_unnamed_c_compstr1453_BitSelect_for_a_b = i_unnamed_c_compstr1452_sel_x_b[0:0];

    // i_unnamed_c_compstr1453_join(BITJOIN,27530)@115
    assign i_unnamed_c_compstr1453_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1453_BitSelect_for_a_b};

    // i_unnamed_c_compstr1453_vt_select_0(BITSELECT,10198)@115
    assign i_unnamed_c_compstr1453_vt_select_0_b = i_unnamed_c_compstr1453_join_q[0:0];

    // redist220_i_unnamed_c_compstr1453_vt_select_0_b_1(DELAY,28448)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist220_i_unnamed_c_compstr1453_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1453_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1453_vt_join(BITJOIN,10197)@116
    assign i_unnamed_c_compstr1453_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist220_i_unnamed_c_compstr1453_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_51_c_compstr1454(ADD,6925)@116
    assign i_add_i_i_i_i_i126_i_51_c_compstr1454_a = {1'b0, i_unnamed_c_compstr1453_vt_join_q};
    assign i_add_i_i_i_i_i126_i_51_c_compstr1454_b = {1'b0, redist1206_i_conv_i_i_i_i97_i_51_c_compstr1450_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_51_c_compstr1454_o = $unsigned(i_add_i_i_i_i_i126_i_51_c_compstr1454_a) + $unsigned(i_add_i_i_i_i_i126_i_51_c_compstr1454_b);
    assign i_add_i_i_i_i_i126_i_51_c_compstr1454_q = i_add_i_i_i_i_i126_i_51_c_compstr1454_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_51_c_compstr1454_sel_x(BITSELECT,2119)@116
    assign bgTrunc_i_add_i_i_i_i_i126_i_51_c_compstr1454_sel_x_b = i_add_i_i_i_i_i126_i_51_c_compstr1454_q[15:0];

    // i_conv_i_i_i_i_i75_i277_52_c_compstr1474_sel_x(BITSELECT,3660)@116
    assign i_conv_i_i_i_i_i75_i277_52_c_compstr1474_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_51_c_compstr1454_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_52_c_compstr1474_vt_select_15(BITSELECT,7541)@116
    assign i_conv_i_i_i_i_i75_i277_52_c_compstr1474_vt_select_15_b = i_conv_i_i_i_i_i75_i277_52_c_compstr1474_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_52_c_compstr1474_vt_join(BITJOIN,7540)@116
    assign i_conv_i_i_i_i_i75_i277_52_c_compstr1474_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_52_c_compstr1474_vt_select_15_b};

    // leftShiftStage0_uid24206_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x(MUX,24205)@116
    assign leftShiftStage0_uid24206_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24206_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_52_c_compstr1474_vt_join_q or leftShiftStage0Idx1_uid24204_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24206_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24206_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_52_c_compstr1474_vt_join_q;
            1'b1 : leftShiftStage0_uid24206_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24204_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24206_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24211_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x(MUX,24210)@116
    assign leftShiftStage1_uid24211_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24211_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_s or leftShiftStage0_uid24206_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24209_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24211_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24211_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q = leftShiftStage0_uid24206_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24211_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24209_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24211_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24216_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x(MUX,24215)@116
    assign leftShiftStage2_uid24216_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24216_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_s or leftShiftStage1_uid24211_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24214_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24216_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24216_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q = leftShiftStage1_uid24211_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24216_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24214_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24216_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_52_c_compstr1475_vt_select_28(BITSELECT,9265)@116
    assign i_shl_i_i_i_i_i77_i_52_c_compstr1475_vt_select_28_b = leftShiftStage2_uid24216_i_shl_i_i_i_i_i77_i_52_c_compstr0_shift_x_q[28:13];

    // redist435_i_shl_i_i_i_i_i77_i_52_c_compstr1475_vt_select_28_b_1(DELAY,28663)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist435_i_shl_i_i_i_i_i77_i_52_c_compstr1475_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_52_c_compstr1475_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_52_c_compstr1475_vt_join(BITJOIN,9264)@117
    assign i_shl_i_i_i_i_i77_i_52_c_compstr1475_vt_join_q = {redist435_i_shl_i_i_i_i_i77_i_52_c_compstr1475_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma(CHAINMULTADD,28173)@111 + 5
    // out q@117
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ah[0] <= redist875_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_105_tpl_103_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ah[1] <= redist874_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_104_tpl_103_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ch[0] <= redist621_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_105_tpl_103_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ch[1] <= redist620_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_104_tpl_103_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476(ADD,8469)@117
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compstr1471_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compstr1473_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compstr1472_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_52_c_compstr1475_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_52_c_compstr1475_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_o[33:0];

    // rightShiftStage0_uid18162_dupName_207_i_unnamed_c_compstr0_shift_x(MUX,18161)@117
    assign rightShiftStage0_uid18162_dupName_207_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18162_dupName_207_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_q or rightShiftStage0Idx1_uid18160_dupName_207_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18162_dupName_207_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18162_dupName_207_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_q;
            1'b1 : rightShiftStage0_uid18162_dupName_207_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18160_dupName_207_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18162_dupName_207_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18167_dupName_207_i_unnamed_c_compstr0_shift_x(MUX,18166)@117
    assign rightShiftStage1_uid18167_dupName_207_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18167_dupName_207_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18162_dupName_207_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18165_dupName_207_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18167_dupName_207_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18167_dupName_207_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18162_dupName_207_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18167_dupName_207_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18165_dupName_207_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18167_dupName_207_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18172_dupName_207_i_unnamed_c_compstr0_shift_x(MUX,18171)@117
    assign rightShiftStage2_uid18172_dupName_207_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18172_dupName_207_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18167_dupName_207_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18170_dupName_207_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18172_dupName_207_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18172_dupName_207_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18167_dupName_207_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18172_dupName_207_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18170_dupName_207_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18172_dupName_207_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1477_vt_select_20(BITSELECT,10212)@117
    assign i_unnamed_c_compstr1477_vt_select_20_b = rightShiftStage2_uid18172_dupName_207_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1477_vt_join(BITJOIN,10211)@117
    assign i_unnamed_c_compstr1477_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1477_vt_select_20_b};

    // i_conv_i_i_i_i97_i_52_c_compstr1478_sel_x(BITSELECT,3531)@117
    assign i_conv_i_i_i_i97_i_52_c_compstr1478_sel_x_b = i_unnamed_c_compstr1477_vt_join_q[15:0];

    // redist1205_i_conv_i_i_i_i97_i_52_c_compstr1478_sel_x_b_1(DELAY,29433)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1205_i_conv_i_i_i_i97_i_52_c_compstr1478_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_52_c_compstr1478_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18181_dupName_208_i_unnamed_c_compstr0_shift_x(BITSELECT,18180)@117
    assign rightShiftStage1Idx1Rng8_uid18181_dupName_208_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18180_dupName_208_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18183_dupName_208_i_unnamed_c_compstr0_shift_x(BITJOIN,18182)@117
    assign rightShiftStage1Idx1_uid18183_dupName_208_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18181_dupName_208_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18176_dupName_208_i_unnamed_c_compstr0_shift_x(BITSELECT,18175)@117
    assign rightShiftStage0Idx1Rng4_uid18176_dupName_208_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_q[33:4];

    // rightShiftStage0Idx1_uid18178_dupName_208_i_unnamed_c_compstr0_shift_x(BITJOIN,18177)@117
    assign rightShiftStage0Idx1_uid18178_dupName_208_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18176_dupName_208_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18180_dupName_208_i_unnamed_c_compstr0_shift_x(MUX,18179)@117
    assign rightShiftStage0_uid18180_dupName_208_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18180_dupName_208_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_q or rightShiftStage0Idx1_uid18178_dupName_208_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18180_dupName_208_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18180_dupName_208_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compstr1476_q;
            1'b1 : rightShiftStage0_uid18180_dupName_208_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18178_dupName_208_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18180_dupName_208_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18185_dupName_208_i_unnamed_c_compstr0_shift_x(MUX,18184)@117
    assign rightShiftStage1_uid18185_dupName_208_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18185_dupName_208_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18180_dupName_208_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18183_dupName_208_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18185_dupName_208_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18185_dupName_208_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18180_dupName_208_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18185_dupName_208_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18183_dupName_208_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18185_dupName_208_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1479_vt_select_21(BITSELECT,10215)@117
    assign i_unnamed_c_compstr1479_vt_select_21_b = rightShiftStage1_uid18185_dupName_208_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1479_vt_join(BITJOIN,10214)@117
    assign i_unnamed_c_compstr1479_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1479_vt_select_21_b};

    // i_unnamed_c_compstr1480_sel_x(BITSELECT,6072)@117
    assign i_unnamed_c_compstr1480_sel_x_b = i_unnamed_c_compstr1479_vt_join_q[15:0];

    // i_unnamed_c_compstr1481_BitSelect_for_a(BITSELECT,27533)@117
    assign i_unnamed_c_compstr1481_BitSelect_for_a_b = i_unnamed_c_compstr1480_sel_x_b[0:0];

    // i_unnamed_c_compstr1481_join(BITJOIN,27534)@117
    assign i_unnamed_c_compstr1481_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1481_BitSelect_for_a_b};

    // i_unnamed_c_compstr1481_vt_select_0(BITSELECT,10220)@117
    assign i_unnamed_c_compstr1481_vt_select_0_b = i_unnamed_c_compstr1481_join_q[0:0];

    // redist218_i_unnamed_c_compstr1481_vt_select_0_b_1(DELAY,28446)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist218_i_unnamed_c_compstr1481_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1481_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1481_vt_join(BITJOIN,10219)@118
    assign i_unnamed_c_compstr1481_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist218_i_unnamed_c_compstr1481_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_52_c_compstr1482(ADD,6926)@118
    assign i_add_i_i_i_i_i126_i_52_c_compstr1482_a = {1'b0, i_unnamed_c_compstr1481_vt_join_q};
    assign i_add_i_i_i_i_i126_i_52_c_compstr1482_b = {1'b0, redist1205_i_conv_i_i_i_i97_i_52_c_compstr1478_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_52_c_compstr1482_o = $unsigned(i_add_i_i_i_i_i126_i_52_c_compstr1482_a) + $unsigned(i_add_i_i_i_i_i126_i_52_c_compstr1482_b);
    assign i_add_i_i_i_i_i126_i_52_c_compstr1482_q = i_add_i_i_i_i_i126_i_52_c_compstr1482_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_52_c_compstr1482_sel_x(BITSELECT,2120)@118
    assign bgTrunc_i_add_i_i_i_i_i126_i_52_c_compstr1482_sel_x_b = i_add_i_i_i_i_i126_i_52_c_compstr1482_q[15:0];

    // i_conv_i_i_i_i_i75_i277_53_c_compstr1502_sel_x(BITSELECT,3661)@118
    assign i_conv_i_i_i_i_i75_i277_53_c_compstr1502_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_52_c_compstr1482_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_53_c_compstr1502_vt_select_15(BITSELECT,7545)@118
    assign i_conv_i_i_i_i_i75_i277_53_c_compstr1502_vt_select_15_b = i_conv_i_i_i_i_i75_i277_53_c_compstr1502_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_53_c_compstr1502_vt_join(BITJOIN,7544)@118
    assign i_conv_i_i_i_i_i75_i277_53_c_compstr1502_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_53_c_compstr1502_vt_select_15_b};

    // leftShiftStage0_uid24224_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x(MUX,24223)@118
    assign leftShiftStage0_uid24224_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24224_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_53_c_compstr1502_vt_join_q or leftShiftStage0Idx1_uid24222_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24224_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24224_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_53_c_compstr1502_vt_join_q;
            1'b1 : leftShiftStage0_uid24224_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24222_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24224_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24229_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x(MUX,24228)@118
    assign leftShiftStage1_uid24229_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24229_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_s or leftShiftStage0_uid24224_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24227_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24229_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24229_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q = leftShiftStage0_uid24224_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24229_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24227_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24229_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24234_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x(MUX,24233)@118
    assign leftShiftStage2_uid24234_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24234_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_s or leftShiftStage1_uid24229_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24232_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24234_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24234_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q = leftShiftStage1_uid24229_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24234_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24232_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24234_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_53_c_compstr1503_vt_select_28(BITSELECT,9268)@118
    assign i_shl_i_i_i_i_i77_i_53_c_compstr1503_vt_select_28_b = leftShiftStage2_uid24234_i_shl_i_i_i_i_i77_i_53_c_compstr0_shift_x_q[28:13];

    // redist434_i_shl_i_i_i_i_i77_i_53_c_compstr1503_vt_select_28_b_1(DELAY,28662)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist434_i_shl_i_i_i_i_i77_i_53_c_compstr1503_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_53_c_compstr1503_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_53_c_compstr1503_vt_join(BITJOIN,9267)@119
    assign i_shl_i_i_i_i_i77_i_53_c_compstr1503_vt_join_q = {redist434_i_shl_i_i_i_i_i77_i_53_c_compstr1503_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma(CHAINMULTADD,28174)@113 + 5
    // out q@119
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ah[0] <= redist877_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_107_tpl_105_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ah[1] <= redist876_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_106_tpl_105_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ch[0] <= redist623_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_107_tpl_105_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ch[1] <= redist622_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_106_tpl_105_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504(ADD,8470)@119
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compstr1499_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compstr1501_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compstr1500_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_53_c_compstr1503_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_53_c_compstr1503_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_o[33:0];

    // rightShiftStage0_uid18224_dupName_211_i_unnamed_c_compstr0_shift_x(MUX,18223)@119
    assign rightShiftStage0_uid18224_dupName_211_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18224_dupName_211_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_q or rightShiftStage0Idx1_uid18222_dupName_211_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18224_dupName_211_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18224_dupName_211_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_q;
            1'b1 : rightShiftStage0_uid18224_dupName_211_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18222_dupName_211_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18224_dupName_211_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18229_dupName_211_i_unnamed_c_compstr0_shift_x(MUX,18228)@119
    assign rightShiftStage1_uid18229_dupName_211_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18229_dupName_211_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18224_dupName_211_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18227_dupName_211_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18229_dupName_211_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18229_dupName_211_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18224_dupName_211_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18229_dupName_211_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18227_dupName_211_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18229_dupName_211_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18234_dupName_211_i_unnamed_c_compstr0_shift_x(MUX,18233)@119
    assign rightShiftStage2_uid18234_dupName_211_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18234_dupName_211_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18229_dupName_211_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18232_dupName_211_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18234_dupName_211_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18234_dupName_211_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18229_dupName_211_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18234_dupName_211_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18232_dupName_211_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18234_dupName_211_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1505_vt_select_20(BITSELECT,10237)@119
    assign i_unnamed_c_compstr1505_vt_select_20_b = rightShiftStage2_uid18234_dupName_211_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1505_vt_join(BITJOIN,10236)@119
    assign i_unnamed_c_compstr1505_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1505_vt_select_20_b};

    // i_conv_i_i_i_i97_i_53_c_compstr1506_sel_x(BITSELECT,3532)@119
    assign i_conv_i_i_i_i97_i_53_c_compstr1506_sel_x_b = i_unnamed_c_compstr1505_vt_join_q[15:0];

    // redist1204_i_conv_i_i_i_i97_i_53_c_compstr1506_sel_x_b_1(DELAY,29432)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1204_i_conv_i_i_i_i97_i_53_c_compstr1506_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_53_c_compstr1506_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18243_dupName_212_i_unnamed_c_compstr0_shift_x(BITSELECT,18242)@119
    assign rightShiftStage1Idx1Rng8_uid18243_dupName_212_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18242_dupName_212_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18245_dupName_212_i_unnamed_c_compstr0_shift_x(BITJOIN,18244)@119
    assign rightShiftStage1Idx1_uid18245_dupName_212_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18243_dupName_212_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18238_dupName_212_i_unnamed_c_compstr0_shift_x(BITSELECT,18237)@119
    assign rightShiftStage0Idx1Rng4_uid18238_dupName_212_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_q[33:4];

    // rightShiftStage0Idx1_uid18240_dupName_212_i_unnamed_c_compstr0_shift_x(BITJOIN,18239)@119
    assign rightShiftStage0Idx1_uid18240_dupName_212_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18238_dupName_212_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18242_dupName_212_i_unnamed_c_compstr0_shift_x(MUX,18241)@119
    assign rightShiftStage0_uid18242_dupName_212_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18242_dupName_212_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_q or rightShiftStage0Idx1_uid18240_dupName_212_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18242_dupName_212_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18242_dupName_212_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compstr1504_q;
            1'b1 : rightShiftStage0_uid18242_dupName_212_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18240_dupName_212_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18242_dupName_212_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18247_dupName_212_i_unnamed_c_compstr0_shift_x(MUX,18246)@119
    assign rightShiftStage1_uid18247_dupName_212_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18247_dupName_212_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18242_dupName_212_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18245_dupName_212_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18247_dupName_212_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18247_dupName_212_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18242_dupName_212_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18247_dupName_212_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18245_dupName_212_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18247_dupName_212_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1507_vt_select_21(BITSELECT,10240)@119
    assign i_unnamed_c_compstr1507_vt_select_21_b = rightShiftStage1_uid18247_dupName_212_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1507_vt_join(BITJOIN,10239)@119
    assign i_unnamed_c_compstr1507_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1507_vt_select_21_b};

    // i_unnamed_c_compstr1508_sel_x(BITSELECT,6074)@119
    assign i_unnamed_c_compstr1508_sel_x_b = i_unnamed_c_compstr1507_vt_join_q[15:0];

    // i_unnamed_c_compstr1509_BitSelect_for_a(BITSELECT,27537)@119
    assign i_unnamed_c_compstr1509_BitSelect_for_a_b = i_unnamed_c_compstr1508_sel_x_b[0:0];

    // i_unnamed_c_compstr1509_join(BITJOIN,27538)@119
    assign i_unnamed_c_compstr1509_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1509_BitSelect_for_a_b};

    // i_unnamed_c_compstr1509_vt_select_0(BITSELECT,10245)@119
    assign i_unnamed_c_compstr1509_vt_select_0_b = i_unnamed_c_compstr1509_join_q[0:0];

    // redist216_i_unnamed_c_compstr1509_vt_select_0_b_1(DELAY,28444)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist216_i_unnamed_c_compstr1509_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1509_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1509_vt_join(BITJOIN,10244)@120
    assign i_unnamed_c_compstr1509_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist216_i_unnamed_c_compstr1509_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_53_c_compstr1510(ADD,6927)@120
    assign i_add_i_i_i_i_i126_i_53_c_compstr1510_a = {1'b0, i_unnamed_c_compstr1509_vt_join_q};
    assign i_add_i_i_i_i_i126_i_53_c_compstr1510_b = {1'b0, redist1204_i_conv_i_i_i_i97_i_53_c_compstr1506_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_53_c_compstr1510_o = $unsigned(i_add_i_i_i_i_i126_i_53_c_compstr1510_a) + $unsigned(i_add_i_i_i_i_i126_i_53_c_compstr1510_b);
    assign i_add_i_i_i_i_i126_i_53_c_compstr1510_q = i_add_i_i_i_i_i126_i_53_c_compstr1510_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_53_c_compstr1510_sel_x(BITSELECT,2121)@120
    assign bgTrunc_i_add_i_i_i_i_i126_i_53_c_compstr1510_sel_x_b = i_add_i_i_i_i_i126_i_53_c_compstr1510_q[15:0];

    // i_conv_i_i_i_i_i75_i277_54_c_compstr1530_sel_x(BITSELECT,3662)@120
    assign i_conv_i_i_i_i_i75_i277_54_c_compstr1530_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_53_c_compstr1510_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_54_c_compstr1530_vt_select_15(BITSELECT,7549)@120
    assign i_conv_i_i_i_i_i75_i277_54_c_compstr1530_vt_select_15_b = i_conv_i_i_i_i_i75_i277_54_c_compstr1530_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_54_c_compstr1530_vt_join(BITJOIN,7548)@120
    assign i_conv_i_i_i_i_i75_i277_54_c_compstr1530_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_54_c_compstr1530_vt_select_15_b};

    // leftShiftStage0_uid24242_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x(MUX,24241)@120
    assign leftShiftStage0_uid24242_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24242_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_54_c_compstr1530_vt_join_q or leftShiftStage0Idx1_uid24240_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24242_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24242_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_54_c_compstr1530_vt_join_q;
            1'b1 : leftShiftStage0_uid24242_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24240_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24242_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24247_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x(MUX,24246)@120
    assign leftShiftStage1_uid24247_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24247_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_s or leftShiftStage0_uid24242_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24245_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24247_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24247_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q = leftShiftStage0_uid24242_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24247_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24245_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24247_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24252_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x(MUX,24251)@120
    assign leftShiftStage2_uid24252_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24252_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_s or leftShiftStage1_uid24247_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24250_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24252_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24252_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q = leftShiftStage1_uid24247_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24252_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24250_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24252_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_54_c_compstr1531_vt_select_28(BITSELECT,9271)@120
    assign i_shl_i_i_i_i_i77_i_54_c_compstr1531_vt_select_28_b = leftShiftStage2_uid24252_i_shl_i_i_i_i_i77_i_54_c_compstr0_shift_x_q[28:13];

    // redist433_i_shl_i_i_i_i_i77_i_54_c_compstr1531_vt_select_28_b_1(DELAY,28661)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist433_i_shl_i_i_i_i_i77_i_54_c_compstr1531_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_54_c_compstr1531_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_54_c_compstr1531_vt_join(BITJOIN,9270)@121
    assign i_shl_i_i_i_i_i77_i_54_c_compstr1531_vt_join_q = {redist433_i_shl_i_i_i_i_i77_i_54_c_compstr1531_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma(CHAINMULTADD,28175)@115 + 5
    // out q@121
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ah[0] <= redist879_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_109_tpl_107_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ah[1] <= redist878_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_108_tpl_107_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ch[0] <= redist625_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_109_tpl_107_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ch[1] <= redist624_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_108_tpl_107_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532(ADD,8471)@121
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compstr1527_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compstr1529_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compstr1528_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_54_c_compstr1531_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_54_c_compstr1531_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_o[33:0];

    // rightShiftStage0_uid18286_dupName_215_i_unnamed_c_compstr0_shift_x(MUX,18285)@121
    assign rightShiftStage0_uid18286_dupName_215_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18286_dupName_215_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_q or rightShiftStage0Idx1_uid18284_dupName_215_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18286_dupName_215_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18286_dupName_215_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_q;
            1'b1 : rightShiftStage0_uid18286_dupName_215_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18284_dupName_215_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18286_dupName_215_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18291_dupName_215_i_unnamed_c_compstr0_shift_x(MUX,18290)@121
    assign rightShiftStage1_uid18291_dupName_215_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18291_dupName_215_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18286_dupName_215_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18289_dupName_215_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18291_dupName_215_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18291_dupName_215_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18286_dupName_215_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18291_dupName_215_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18289_dupName_215_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18291_dupName_215_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18296_dupName_215_i_unnamed_c_compstr0_shift_x(MUX,18295)@121
    assign rightShiftStage2_uid18296_dupName_215_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18296_dupName_215_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18291_dupName_215_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18294_dupName_215_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18296_dupName_215_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18296_dupName_215_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18291_dupName_215_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18296_dupName_215_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18294_dupName_215_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18296_dupName_215_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1533_vt_select_20(BITSELECT,10264)@121
    assign i_unnamed_c_compstr1533_vt_select_20_b = rightShiftStage2_uid18296_dupName_215_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1533_vt_join(BITJOIN,10263)@121
    assign i_unnamed_c_compstr1533_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1533_vt_select_20_b};

    // i_conv_i_i_i_i97_i_54_c_compstr1534_sel_x(BITSELECT,3533)@121
    assign i_conv_i_i_i_i97_i_54_c_compstr1534_sel_x_b = i_unnamed_c_compstr1533_vt_join_q[15:0];

    // redist1203_i_conv_i_i_i_i97_i_54_c_compstr1534_sel_x_b_1(DELAY,29431)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1203_i_conv_i_i_i_i97_i_54_c_compstr1534_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_54_c_compstr1534_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18305_dupName_216_i_unnamed_c_compstr0_shift_x(BITSELECT,18304)@121
    assign rightShiftStage1Idx1Rng8_uid18305_dupName_216_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18304_dupName_216_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18307_dupName_216_i_unnamed_c_compstr0_shift_x(BITJOIN,18306)@121
    assign rightShiftStage1Idx1_uid18307_dupName_216_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18305_dupName_216_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18300_dupName_216_i_unnamed_c_compstr0_shift_x(BITSELECT,18299)@121
    assign rightShiftStage0Idx1Rng4_uid18300_dupName_216_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_q[33:4];

    // rightShiftStage0Idx1_uid18302_dupName_216_i_unnamed_c_compstr0_shift_x(BITJOIN,18301)@121
    assign rightShiftStage0Idx1_uid18302_dupName_216_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18300_dupName_216_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18304_dupName_216_i_unnamed_c_compstr0_shift_x(MUX,18303)@121
    assign rightShiftStage0_uid18304_dupName_216_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18304_dupName_216_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_q or rightShiftStage0Idx1_uid18302_dupName_216_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18304_dupName_216_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18304_dupName_216_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compstr1532_q;
            1'b1 : rightShiftStage0_uid18304_dupName_216_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18302_dupName_216_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18304_dupName_216_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18309_dupName_216_i_unnamed_c_compstr0_shift_x(MUX,18308)@121
    assign rightShiftStage1_uid18309_dupName_216_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18309_dupName_216_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18304_dupName_216_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18307_dupName_216_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18309_dupName_216_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18309_dupName_216_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18304_dupName_216_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18309_dupName_216_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18307_dupName_216_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18309_dupName_216_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1535_vt_select_21(BITSELECT,10267)@121
    assign i_unnamed_c_compstr1535_vt_select_21_b = rightShiftStage1_uid18309_dupName_216_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1535_vt_join(BITJOIN,10266)@121
    assign i_unnamed_c_compstr1535_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1535_vt_select_21_b};

    // i_unnamed_c_compstr1536_sel_x(BITSELECT,6077)@121
    assign i_unnamed_c_compstr1536_sel_x_b = i_unnamed_c_compstr1535_vt_join_q[15:0];

    // i_unnamed_c_compstr1537_BitSelect_for_a(BITSELECT,27543)@121
    assign i_unnamed_c_compstr1537_BitSelect_for_a_b = i_unnamed_c_compstr1536_sel_x_b[0:0];

    // i_unnamed_c_compstr1537_join(BITJOIN,27544)@121
    assign i_unnamed_c_compstr1537_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1537_BitSelect_for_a_b};

    // i_unnamed_c_compstr1537_vt_select_0(BITSELECT,10272)@121
    assign i_unnamed_c_compstr1537_vt_select_0_b = i_unnamed_c_compstr1537_join_q[0:0];

    // redist214_i_unnamed_c_compstr1537_vt_select_0_b_1(DELAY,28442)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist214_i_unnamed_c_compstr1537_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1537_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1537_vt_join(BITJOIN,10271)@122
    assign i_unnamed_c_compstr1537_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist214_i_unnamed_c_compstr1537_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_54_c_compstr1538(ADD,6928)@122
    assign i_add_i_i_i_i_i126_i_54_c_compstr1538_a = {1'b0, i_unnamed_c_compstr1537_vt_join_q};
    assign i_add_i_i_i_i_i126_i_54_c_compstr1538_b = {1'b0, redist1203_i_conv_i_i_i_i97_i_54_c_compstr1534_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_54_c_compstr1538_o = $unsigned(i_add_i_i_i_i_i126_i_54_c_compstr1538_a) + $unsigned(i_add_i_i_i_i_i126_i_54_c_compstr1538_b);
    assign i_add_i_i_i_i_i126_i_54_c_compstr1538_q = i_add_i_i_i_i_i126_i_54_c_compstr1538_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_54_c_compstr1538_sel_x(BITSELECT,2122)@122
    assign bgTrunc_i_add_i_i_i_i_i126_i_54_c_compstr1538_sel_x_b = i_add_i_i_i_i_i126_i_54_c_compstr1538_q[15:0];

    // i_conv_i_i_i_i_i75_i277_55_c_compstr1558_sel_x(BITSELECT,3663)@122
    assign i_conv_i_i_i_i_i75_i277_55_c_compstr1558_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_54_c_compstr1538_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_55_c_compstr1558_vt_select_15(BITSELECT,7553)@122
    assign i_conv_i_i_i_i_i75_i277_55_c_compstr1558_vt_select_15_b = i_conv_i_i_i_i_i75_i277_55_c_compstr1558_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_55_c_compstr1558_vt_join(BITJOIN,7552)@122
    assign i_conv_i_i_i_i_i75_i277_55_c_compstr1558_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_55_c_compstr1558_vt_select_15_b};

    // leftShiftStage0_uid24260_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x(MUX,24259)@122
    assign leftShiftStage0_uid24260_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24260_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_55_c_compstr1558_vt_join_q or leftShiftStage0Idx1_uid24258_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24260_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24260_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_55_c_compstr1558_vt_join_q;
            1'b1 : leftShiftStage0_uid24260_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24258_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24260_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24265_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x(MUX,24264)@122
    assign leftShiftStage1_uid24265_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24265_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_s or leftShiftStage0_uid24260_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24263_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24265_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24265_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q = leftShiftStage0_uid24260_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24265_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24263_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24265_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24270_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x(MUX,24269)@122
    assign leftShiftStage2_uid24270_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24270_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_s or leftShiftStage1_uid24265_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24268_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24270_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24270_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q = leftShiftStage1_uid24265_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24270_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24268_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24270_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_55_c_compstr1559_vt_select_28(BITSELECT,9274)@122
    assign i_shl_i_i_i_i_i77_i_55_c_compstr1559_vt_select_28_b = leftShiftStage2_uid24270_i_shl_i_i_i_i_i77_i_55_c_compstr0_shift_x_q[28:13];

    // redist432_i_shl_i_i_i_i_i77_i_55_c_compstr1559_vt_select_28_b_1(DELAY,28660)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist432_i_shl_i_i_i_i_i77_i_55_c_compstr1559_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_55_c_compstr1559_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_55_c_compstr1559_vt_join(BITJOIN,9273)@123
    assign i_shl_i_i_i_i_i77_i_55_c_compstr1559_vt_join_q = {redist432_i_shl_i_i_i_i_i77_i_55_c_compstr1559_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma(CHAINMULTADD,28176)@117 + 5
    // out q@123
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ah[0] <= redist881_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_111_tpl_109_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ah[1] <= redist880_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_110_tpl_109_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ch[0] <= redist627_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_111_tpl_109_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ch[1] <= redist626_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_110_tpl_109_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560(ADD,8472)@123
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compstr1555_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compstr1557_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compstr1556_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_55_c_compstr1559_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_55_c_compstr1559_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_o[33:0];

    // rightShiftStage0_uid18348_dupName_219_i_unnamed_c_compstr0_shift_x(MUX,18347)@123
    assign rightShiftStage0_uid18348_dupName_219_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18348_dupName_219_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_q or rightShiftStage0Idx1_uid18346_dupName_219_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18348_dupName_219_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18348_dupName_219_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_q;
            1'b1 : rightShiftStage0_uid18348_dupName_219_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18346_dupName_219_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18348_dupName_219_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18353_dupName_219_i_unnamed_c_compstr0_shift_x(MUX,18352)@123
    assign rightShiftStage1_uid18353_dupName_219_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18353_dupName_219_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18348_dupName_219_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18351_dupName_219_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18353_dupName_219_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18353_dupName_219_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18348_dupName_219_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18353_dupName_219_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18351_dupName_219_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18353_dupName_219_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18358_dupName_219_i_unnamed_c_compstr0_shift_x(MUX,18357)@123
    assign rightShiftStage2_uid18358_dupName_219_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18358_dupName_219_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18353_dupName_219_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18356_dupName_219_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18358_dupName_219_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18358_dupName_219_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18353_dupName_219_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18358_dupName_219_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18356_dupName_219_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18358_dupName_219_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1561_vt_select_20(BITSELECT,10289)@123
    assign i_unnamed_c_compstr1561_vt_select_20_b = rightShiftStage2_uid18358_dupName_219_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1561_vt_join(BITJOIN,10288)@123
    assign i_unnamed_c_compstr1561_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1561_vt_select_20_b};

    // i_conv_i_i_i_i97_i_55_c_compstr1562_sel_x(BITSELECT,3534)@123
    assign i_conv_i_i_i_i97_i_55_c_compstr1562_sel_x_b = i_unnamed_c_compstr1561_vt_join_q[15:0];

    // redist1202_i_conv_i_i_i_i97_i_55_c_compstr1562_sel_x_b_1(DELAY,29430)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1202_i_conv_i_i_i_i97_i_55_c_compstr1562_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_55_c_compstr1562_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18367_dupName_220_i_unnamed_c_compstr0_shift_x(BITSELECT,18366)@123
    assign rightShiftStage1Idx1Rng8_uid18367_dupName_220_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18366_dupName_220_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18369_dupName_220_i_unnamed_c_compstr0_shift_x(BITJOIN,18368)@123
    assign rightShiftStage1Idx1_uid18369_dupName_220_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18367_dupName_220_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18362_dupName_220_i_unnamed_c_compstr0_shift_x(BITSELECT,18361)@123
    assign rightShiftStage0Idx1Rng4_uid18362_dupName_220_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_q[33:4];

    // rightShiftStage0Idx1_uid18364_dupName_220_i_unnamed_c_compstr0_shift_x(BITJOIN,18363)@123
    assign rightShiftStage0Idx1_uid18364_dupName_220_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18362_dupName_220_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18366_dupName_220_i_unnamed_c_compstr0_shift_x(MUX,18365)@123
    assign rightShiftStage0_uid18366_dupName_220_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18366_dupName_220_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_q or rightShiftStage0Idx1_uid18364_dupName_220_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18366_dupName_220_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18366_dupName_220_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compstr1560_q;
            1'b1 : rightShiftStage0_uid18366_dupName_220_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18364_dupName_220_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18366_dupName_220_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18371_dupName_220_i_unnamed_c_compstr0_shift_x(MUX,18370)@123
    assign rightShiftStage1_uid18371_dupName_220_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18371_dupName_220_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18366_dupName_220_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18369_dupName_220_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18371_dupName_220_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18371_dupName_220_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18366_dupName_220_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18371_dupName_220_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18369_dupName_220_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18371_dupName_220_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1563_vt_select_21(BITSELECT,10292)@123
    assign i_unnamed_c_compstr1563_vt_select_21_b = rightShiftStage1_uid18371_dupName_220_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1563_vt_join(BITJOIN,10291)@123
    assign i_unnamed_c_compstr1563_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1563_vt_select_21_b};

    // i_unnamed_c_compstr1564_sel_x(BITSELECT,6079)@123
    assign i_unnamed_c_compstr1564_sel_x_b = i_unnamed_c_compstr1563_vt_join_q[15:0];

    // i_unnamed_c_compstr1565_BitSelect_for_a(BITSELECT,27547)@123
    assign i_unnamed_c_compstr1565_BitSelect_for_a_b = i_unnamed_c_compstr1564_sel_x_b[0:0];

    // i_unnamed_c_compstr1565_join(BITJOIN,27548)@123
    assign i_unnamed_c_compstr1565_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1565_BitSelect_for_a_b};

    // i_unnamed_c_compstr1565_vt_select_0(BITSELECT,10297)@123
    assign i_unnamed_c_compstr1565_vt_select_0_b = i_unnamed_c_compstr1565_join_q[0:0];

    // redist211_i_unnamed_c_compstr1565_vt_select_0_b_1(DELAY,28439)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist211_i_unnamed_c_compstr1565_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1565_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1565_vt_join(BITJOIN,10296)@124
    assign i_unnamed_c_compstr1565_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist211_i_unnamed_c_compstr1565_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_55_c_compstr1566(ADD,6929)@124
    assign i_add_i_i_i_i_i126_i_55_c_compstr1566_a = {1'b0, i_unnamed_c_compstr1565_vt_join_q};
    assign i_add_i_i_i_i_i126_i_55_c_compstr1566_b = {1'b0, redist1202_i_conv_i_i_i_i97_i_55_c_compstr1562_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_55_c_compstr1566_o = $unsigned(i_add_i_i_i_i_i126_i_55_c_compstr1566_a) + $unsigned(i_add_i_i_i_i_i126_i_55_c_compstr1566_b);
    assign i_add_i_i_i_i_i126_i_55_c_compstr1566_q = i_add_i_i_i_i_i126_i_55_c_compstr1566_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_55_c_compstr1566_sel_x(BITSELECT,2123)@124
    assign bgTrunc_i_add_i_i_i_i_i126_i_55_c_compstr1566_sel_x_b = i_add_i_i_i_i_i126_i_55_c_compstr1566_q[15:0];

    // i_conv_i_i_i_i_i75_i277_56_c_compstr1586_sel_x(BITSELECT,3664)@124
    assign i_conv_i_i_i_i_i75_i277_56_c_compstr1586_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_55_c_compstr1566_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_56_c_compstr1586_vt_select_15(BITSELECT,7557)@124
    assign i_conv_i_i_i_i_i75_i277_56_c_compstr1586_vt_select_15_b = i_conv_i_i_i_i_i75_i277_56_c_compstr1586_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_56_c_compstr1586_vt_join(BITJOIN,7556)@124
    assign i_conv_i_i_i_i_i75_i277_56_c_compstr1586_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_56_c_compstr1586_vt_select_15_b};

    // leftShiftStage0_uid24278_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x(MUX,24277)@124
    assign leftShiftStage0_uid24278_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24278_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_56_c_compstr1586_vt_join_q or leftShiftStage0Idx1_uid24276_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24278_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24278_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_56_c_compstr1586_vt_join_q;
            1'b1 : leftShiftStage0_uid24278_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24276_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24278_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24283_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x(MUX,24282)@124
    assign leftShiftStage1_uid24283_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24283_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_s or leftShiftStage0_uid24278_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24281_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24283_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24283_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q = leftShiftStage0_uid24278_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24283_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24281_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24283_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24288_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x(MUX,24287)@124
    assign leftShiftStage2_uid24288_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24288_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_s or leftShiftStage1_uid24283_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24286_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24288_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24288_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q = leftShiftStage1_uid24283_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24288_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24286_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24288_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_56_c_compstr1587_vt_select_28(BITSELECT,9277)@124
    assign i_shl_i_i_i_i_i77_i_56_c_compstr1587_vt_select_28_b = leftShiftStage2_uid24288_i_shl_i_i_i_i_i77_i_56_c_compstr0_shift_x_q[28:13];

    // redist431_i_shl_i_i_i_i_i77_i_56_c_compstr1587_vt_select_28_b_1(DELAY,28659)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist431_i_shl_i_i_i_i_i77_i_56_c_compstr1587_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_56_c_compstr1587_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_56_c_compstr1587_vt_join(BITJOIN,9276)@125
    assign i_shl_i_i_i_i_i77_i_56_c_compstr1587_vt_join_q = {redist431_i_shl_i_i_i_i_i77_i_56_c_compstr1587_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma(CHAINMULTADD,28177)@119 + 5
    // out q@125
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ah[0] <= redist883_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_113_tpl_111_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ah[1] <= redist882_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_112_tpl_111_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ch[0] <= redist629_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_113_tpl_111_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ch[1] <= redist628_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_112_tpl_111_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588(ADD,8473)@125
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compstr1583_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compstr1585_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compstr1584_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_56_c_compstr1587_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_56_c_compstr1587_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_o[33:0];

    // rightShiftStage0_uid18410_dupName_223_i_unnamed_c_compstr0_shift_x(MUX,18409)@125
    assign rightShiftStage0_uid18410_dupName_223_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18410_dupName_223_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_q or rightShiftStage0Idx1_uid18408_dupName_223_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18410_dupName_223_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18410_dupName_223_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_q;
            1'b1 : rightShiftStage0_uid18410_dupName_223_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18408_dupName_223_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18410_dupName_223_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18415_dupName_223_i_unnamed_c_compstr0_shift_x(MUX,18414)@125
    assign rightShiftStage1_uid18415_dupName_223_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18415_dupName_223_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18410_dupName_223_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18413_dupName_223_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18415_dupName_223_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18415_dupName_223_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18410_dupName_223_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18415_dupName_223_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18413_dupName_223_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18415_dupName_223_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18420_dupName_223_i_unnamed_c_compstr0_shift_x(MUX,18419)@125
    assign rightShiftStage2_uid18420_dupName_223_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18420_dupName_223_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18415_dupName_223_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18418_dupName_223_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18420_dupName_223_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18420_dupName_223_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18415_dupName_223_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18420_dupName_223_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18418_dupName_223_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18420_dupName_223_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1589_vt_select_20(BITSELECT,10311)@125
    assign i_unnamed_c_compstr1589_vt_select_20_b = rightShiftStage2_uid18420_dupName_223_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1589_vt_join(BITJOIN,10310)@125
    assign i_unnamed_c_compstr1589_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1589_vt_select_20_b};

    // i_conv_i_i_i_i97_i_56_c_compstr1590_sel_x(BITSELECT,3535)@125
    assign i_conv_i_i_i_i97_i_56_c_compstr1590_sel_x_b = i_unnamed_c_compstr1589_vt_join_q[15:0];

    // redist1201_i_conv_i_i_i_i97_i_56_c_compstr1590_sel_x_b_1(DELAY,29429)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1201_i_conv_i_i_i_i97_i_56_c_compstr1590_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_56_c_compstr1590_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18429_dupName_224_i_unnamed_c_compstr0_shift_x(BITSELECT,18428)@125
    assign rightShiftStage1Idx1Rng8_uid18429_dupName_224_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18428_dupName_224_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18431_dupName_224_i_unnamed_c_compstr0_shift_x(BITJOIN,18430)@125
    assign rightShiftStage1Idx1_uid18431_dupName_224_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18429_dupName_224_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18424_dupName_224_i_unnamed_c_compstr0_shift_x(BITSELECT,18423)@125
    assign rightShiftStage0Idx1Rng4_uid18424_dupName_224_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_q[33:4];

    // rightShiftStage0Idx1_uid18426_dupName_224_i_unnamed_c_compstr0_shift_x(BITJOIN,18425)@125
    assign rightShiftStage0Idx1_uid18426_dupName_224_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18424_dupName_224_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18428_dupName_224_i_unnamed_c_compstr0_shift_x(MUX,18427)@125
    assign rightShiftStage0_uid18428_dupName_224_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18428_dupName_224_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_q or rightShiftStage0Idx1_uid18426_dupName_224_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18428_dupName_224_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18428_dupName_224_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compstr1588_q;
            1'b1 : rightShiftStage0_uid18428_dupName_224_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18426_dupName_224_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18428_dupName_224_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18433_dupName_224_i_unnamed_c_compstr0_shift_x(MUX,18432)@125
    assign rightShiftStage1_uid18433_dupName_224_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18433_dupName_224_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18428_dupName_224_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18431_dupName_224_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18433_dupName_224_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18433_dupName_224_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18428_dupName_224_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18433_dupName_224_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18431_dupName_224_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18433_dupName_224_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1591_vt_select_21(BITSELECT,10314)@125
    assign i_unnamed_c_compstr1591_vt_select_21_b = rightShiftStage1_uid18433_dupName_224_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1591_vt_join(BITJOIN,10313)@125
    assign i_unnamed_c_compstr1591_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1591_vt_select_21_b};

    // i_unnamed_c_compstr1592_sel_x(BITSELECT,6081)@125
    assign i_unnamed_c_compstr1592_sel_x_b = i_unnamed_c_compstr1591_vt_join_q[15:0];

    // i_unnamed_c_compstr1593_BitSelect_for_a(BITSELECT,27551)@125
    assign i_unnamed_c_compstr1593_BitSelect_for_a_b = i_unnamed_c_compstr1592_sel_x_b[0:0];

    // i_unnamed_c_compstr1593_join(BITJOIN,27552)@125
    assign i_unnamed_c_compstr1593_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1593_BitSelect_for_a_b};

    // i_unnamed_c_compstr1593_vt_select_0(BITSELECT,10319)@125
    assign i_unnamed_c_compstr1593_vt_select_0_b = i_unnamed_c_compstr1593_join_q[0:0];

    // redist209_i_unnamed_c_compstr1593_vt_select_0_b_1(DELAY,28437)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist209_i_unnamed_c_compstr1593_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1593_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1593_vt_join(BITJOIN,10318)@126
    assign i_unnamed_c_compstr1593_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist209_i_unnamed_c_compstr1593_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_56_c_compstr1594(ADD,6930)@126
    assign i_add_i_i_i_i_i126_i_56_c_compstr1594_a = {1'b0, i_unnamed_c_compstr1593_vt_join_q};
    assign i_add_i_i_i_i_i126_i_56_c_compstr1594_b = {1'b0, redist1201_i_conv_i_i_i_i97_i_56_c_compstr1590_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_56_c_compstr1594_o = $unsigned(i_add_i_i_i_i_i126_i_56_c_compstr1594_a) + $unsigned(i_add_i_i_i_i_i126_i_56_c_compstr1594_b);
    assign i_add_i_i_i_i_i126_i_56_c_compstr1594_q = i_add_i_i_i_i_i126_i_56_c_compstr1594_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_56_c_compstr1594_sel_x(BITSELECT,2124)@126
    assign bgTrunc_i_add_i_i_i_i_i126_i_56_c_compstr1594_sel_x_b = i_add_i_i_i_i_i126_i_56_c_compstr1594_q[15:0];

    // i_conv_i_i_i_i_i75_i277_57_c_compstr1614_sel_x(BITSELECT,3665)@126
    assign i_conv_i_i_i_i_i75_i277_57_c_compstr1614_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_56_c_compstr1594_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_57_c_compstr1614_vt_select_15(BITSELECT,7561)@126
    assign i_conv_i_i_i_i_i75_i277_57_c_compstr1614_vt_select_15_b = i_conv_i_i_i_i_i75_i277_57_c_compstr1614_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_57_c_compstr1614_vt_join(BITJOIN,7560)@126
    assign i_conv_i_i_i_i_i75_i277_57_c_compstr1614_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_57_c_compstr1614_vt_select_15_b};

    // leftShiftStage0_uid24296_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x(MUX,24295)@126
    assign leftShiftStage0_uid24296_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24296_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_57_c_compstr1614_vt_join_q or leftShiftStage0Idx1_uid24294_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24296_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24296_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_57_c_compstr1614_vt_join_q;
            1'b1 : leftShiftStage0_uid24296_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24294_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24296_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24301_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x(MUX,24300)@126
    assign leftShiftStage1_uid24301_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24301_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_s or leftShiftStage0_uid24296_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24299_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24301_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24301_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q = leftShiftStage0_uid24296_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24301_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24299_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24301_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24306_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x(MUX,24305)@126
    assign leftShiftStage2_uid24306_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24306_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_s or leftShiftStage1_uid24301_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24304_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24306_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24306_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q = leftShiftStage1_uid24301_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24306_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24304_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24306_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_57_c_compstr1615_vt_select_28(BITSELECT,9280)@126
    assign i_shl_i_i_i_i_i77_i_57_c_compstr1615_vt_select_28_b = leftShiftStage2_uid24306_i_shl_i_i_i_i_i77_i_57_c_compstr0_shift_x_q[28:13];

    // redist430_i_shl_i_i_i_i_i77_i_57_c_compstr1615_vt_select_28_b_1(DELAY,28658)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist430_i_shl_i_i_i_i_i77_i_57_c_compstr1615_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_57_c_compstr1615_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_57_c_compstr1615_vt_join(BITJOIN,9279)@127
    assign i_shl_i_i_i_i_i77_i_57_c_compstr1615_vt_join_q = {redist430_i_shl_i_i_i_i_i77_i_57_c_compstr1615_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma(CHAINMULTADD,28178)@121 + 5
    // out q@127
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ah[0] <= redist885_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_115_tpl_113_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ah[1] <= redist884_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_114_tpl_113_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ch[0] <= redist631_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_115_tpl_113_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ch[1] <= redist630_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_114_tpl_113_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616(ADD,8474)@127
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compstr1611_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compstr1613_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compstr1612_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_57_c_compstr1615_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_57_c_compstr1615_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_o[33:0];

    // rightShiftStage0_uid18472_dupName_227_i_unnamed_c_compstr0_shift_x(MUX,18471)@127
    assign rightShiftStage0_uid18472_dupName_227_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18472_dupName_227_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_q or rightShiftStage0Idx1_uid18470_dupName_227_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18472_dupName_227_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18472_dupName_227_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_q;
            1'b1 : rightShiftStage0_uid18472_dupName_227_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18470_dupName_227_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18472_dupName_227_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18477_dupName_227_i_unnamed_c_compstr0_shift_x(MUX,18476)@127
    assign rightShiftStage1_uid18477_dupName_227_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18477_dupName_227_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18472_dupName_227_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18475_dupName_227_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18477_dupName_227_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18477_dupName_227_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18472_dupName_227_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18477_dupName_227_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18475_dupName_227_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18477_dupName_227_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18482_dupName_227_i_unnamed_c_compstr0_shift_x(MUX,18481)@127
    assign rightShiftStage2_uid18482_dupName_227_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18482_dupName_227_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18477_dupName_227_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18480_dupName_227_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18482_dupName_227_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18482_dupName_227_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18477_dupName_227_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18482_dupName_227_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18480_dupName_227_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18482_dupName_227_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1617_vt_select_20(BITSELECT,10333)@127
    assign i_unnamed_c_compstr1617_vt_select_20_b = rightShiftStage2_uid18482_dupName_227_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1617_vt_join(BITJOIN,10332)@127
    assign i_unnamed_c_compstr1617_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1617_vt_select_20_b};

    // i_conv_i_i_i_i97_i_57_c_compstr1618_sel_x(BITSELECT,3536)@127
    assign i_conv_i_i_i_i97_i_57_c_compstr1618_sel_x_b = i_unnamed_c_compstr1617_vt_join_q[15:0];

    // redist1200_i_conv_i_i_i_i97_i_57_c_compstr1618_sel_x_b_1(DELAY,29428)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1200_i_conv_i_i_i_i97_i_57_c_compstr1618_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_57_c_compstr1618_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18491_dupName_228_i_unnamed_c_compstr0_shift_x(BITSELECT,18490)@127
    assign rightShiftStage1Idx1Rng8_uid18491_dupName_228_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18490_dupName_228_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18493_dupName_228_i_unnamed_c_compstr0_shift_x(BITJOIN,18492)@127
    assign rightShiftStage1Idx1_uid18493_dupName_228_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18491_dupName_228_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18486_dupName_228_i_unnamed_c_compstr0_shift_x(BITSELECT,18485)@127
    assign rightShiftStage0Idx1Rng4_uid18486_dupName_228_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_q[33:4];

    // rightShiftStage0Idx1_uid18488_dupName_228_i_unnamed_c_compstr0_shift_x(BITJOIN,18487)@127
    assign rightShiftStage0Idx1_uid18488_dupName_228_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18486_dupName_228_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18490_dupName_228_i_unnamed_c_compstr0_shift_x(MUX,18489)@127
    assign rightShiftStage0_uid18490_dupName_228_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18490_dupName_228_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_q or rightShiftStage0Idx1_uid18488_dupName_228_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18490_dupName_228_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18490_dupName_228_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compstr1616_q;
            1'b1 : rightShiftStage0_uid18490_dupName_228_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18488_dupName_228_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18490_dupName_228_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18495_dupName_228_i_unnamed_c_compstr0_shift_x(MUX,18494)@127
    assign rightShiftStage1_uid18495_dupName_228_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18495_dupName_228_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18490_dupName_228_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18493_dupName_228_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18495_dupName_228_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18495_dupName_228_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18490_dupName_228_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18495_dupName_228_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18493_dupName_228_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18495_dupName_228_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1619_vt_select_21(BITSELECT,10336)@127
    assign i_unnamed_c_compstr1619_vt_select_21_b = rightShiftStage1_uid18495_dupName_228_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1619_vt_join(BITJOIN,10335)@127
    assign i_unnamed_c_compstr1619_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1619_vt_select_21_b};

    // i_unnamed_c_compstr1620_sel_x(BITSELECT,6083)@127
    assign i_unnamed_c_compstr1620_sel_x_b = i_unnamed_c_compstr1619_vt_join_q[15:0];

    // i_unnamed_c_compstr1621_BitSelect_for_a(BITSELECT,27555)@127
    assign i_unnamed_c_compstr1621_BitSelect_for_a_b = i_unnamed_c_compstr1620_sel_x_b[0:0];

    // i_unnamed_c_compstr1621_join(BITJOIN,27556)@127
    assign i_unnamed_c_compstr1621_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1621_BitSelect_for_a_b};

    // i_unnamed_c_compstr1621_vt_select_0(BITSELECT,10344)@127
    assign i_unnamed_c_compstr1621_vt_select_0_b = i_unnamed_c_compstr1621_join_q[0:0];

    // redist207_i_unnamed_c_compstr1621_vt_select_0_b_1(DELAY,28435)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist207_i_unnamed_c_compstr1621_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1621_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1621_vt_join(BITJOIN,10343)@128
    assign i_unnamed_c_compstr1621_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist207_i_unnamed_c_compstr1621_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_57_c_compstr1622(ADD,6931)@128
    assign i_add_i_i_i_i_i126_i_57_c_compstr1622_a = {1'b0, i_unnamed_c_compstr1621_vt_join_q};
    assign i_add_i_i_i_i_i126_i_57_c_compstr1622_b = {1'b0, redist1200_i_conv_i_i_i_i97_i_57_c_compstr1618_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_57_c_compstr1622_o = $unsigned(i_add_i_i_i_i_i126_i_57_c_compstr1622_a) + $unsigned(i_add_i_i_i_i_i126_i_57_c_compstr1622_b);
    assign i_add_i_i_i_i_i126_i_57_c_compstr1622_q = i_add_i_i_i_i_i126_i_57_c_compstr1622_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_57_c_compstr1622_sel_x(BITSELECT,2125)@128
    assign bgTrunc_i_add_i_i_i_i_i126_i_57_c_compstr1622_sel_x_b = i_add_i_i_i_i_i126_i_57_c_compstr1622_q[15:0];

    // i_conv_i_i_i_i_i75_i277_58_c_compstr1642_sel_x(BITSELECT,3666)@128
    assign i_conv_i_i_i_i_i75_i277_58_c_compstr1642_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_57_c_compstr1622_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_58_c_compstr1642_vt_select_15(BITSELECT,7565)@128
    assign i_conv_i_i_i_i_i75_i277_58_c_compstr1642_vt_select_15_b = i_conv_i_i_i_i_i75_i277_58_c_compstr1642_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_58_c_compstr1642_vt_join(BITJOIN,7564)@128
    assign i_conv_i_i_i_i_i75_i277_58_c_compstr1642_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_58_c_compstr1642_vt_select_15_b};

    // leftShiftStage0_uid24314_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x(MUX,24313)@128
    assign leftShiftStage0_uid24314_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24314_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_58_c_compstr1642_vt_join_q or leftShiftStage0Idx1_uid24312_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24314_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24314_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_58_c_compstr1642_vt_join_q;
            1'b1 : leftShiftStage0_uid24314_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24312_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24314_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24319_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x(MUX,24318)@128
    assign leftShiftStage1_uid24319_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24319_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_s or leftShiftStage0_uid24314_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24317_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24319_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24319_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q = leftShiftStage0_uid24314_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24319_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24317_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24319_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24324_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x(MUX,24323)@128
    assign leftShiftStage2_uid24324_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24324_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_s or leftShiftStage1_uid24319_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24322_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24324_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24324_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q = leftShiftStage1_uid24319_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24324_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24322_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24324_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_58_c_compstr1643_vt_select_28(BITSELECT,9283)@128
    assign i_shl_i_i_i_i_i77_i_58_c_compstr1643_vt_select_28_b = leftShiftStage2_uid24324_i_shl_i_i_i_i_i77_i_58_c_compstr0_shift_x_q[28:13];

    // redist429_i_shl_i_i_i_i_i77_i_58_c_compstr1643_vt_select_28_b_1(DELAY,28657)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist429_i_shl_i_i_i_i_i77_i_58_c_compstr1643_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_58_c_compstr1643_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_58_c_compstr1643_vt_join(BITJOIN,9282)@129
    assign i_shl_i_i_i_i_i77_i_58_c_compstr1643_vt_join_q = {redist429_i_shl_i_i_i_i_i77_i_58_c_compstr1643_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma(CHAINMULTADD,28179)@123 + 5
    // out q@129
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ah[0] <= redist887_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_117_tpl_115_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ah[1] <= redist886_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_116_tpl_115_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ch[0] <= redist633_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_117_tpl_115_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ch[1] <= redist632_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_116_tpl_115_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644(ADD,8475)@129
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compstr1639_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compstr1641_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compstr1640_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_58_c_compstr1643_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_58_c_compstr1643_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_o[33:0];

    // rightShiftStage0_uid18534_dupName_231_i_unnamed_c_compstr0_shift_x(MUX,18533)@129
    assign rightShiftStage0_uid18534_dupName_231_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18534_dupName_231_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_q or rightShiftStage0Idx1_uid18532_dupName_231_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18534_dupName_231_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18534_dupName_231_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_q;
            1'b1 : rightShiftStage0_uid18534_dupName_231_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18532_dupName_231_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18534_dupName_231_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18539_dupName_231_i_unnamed_c_compstr0_shift_x(MUX,18538)@129
    assign rightShiftStage1_uid18539_dupName_231_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18539_dupName_231_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18534_dupName_231_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18537_dupName_231_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18539_dupName_231_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18539_dupName_231_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18534_dupName_231_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18539_dupName_231_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18537_dupName_231_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18539_dupName_231_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18544_dupName_231_i_unnamed_c_compstr0_shift_x(MUX,18543)@129
    assign rightShiftStage2_uid18544_dupName_231_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18544_dupName_231_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18539_dupName_231_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18542_dupName_231_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18544_dupName_231_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18544_dupName_231_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18539_dupName_231_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18544_dupName_231_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18542_dupName_231_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18544_dupName_231_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1645_vt_select_20(BITSELECT,10361)@129
    assign i_unnamed_c_compstr1645_vt_select_20_b = rightShiftStage2_uid18544_dupName_231_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1645_vt_join(BITJOIN,10360)@129
    assign i_unnamed_c_compstr1645_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1645_vt_select_20_b};

    // i_conv_i_i_i_i97_i_58_c_compstr1646_sel_x(BITSELECT,3537)@129
    assign i_conv_i_i_i_i97_i_58_c_compstr1646_sel_x_b = i_unnamed_c_compstr1645_vt_join_q[15:0];

    // redist1199_i_conv_i_i_i_i97_i_58_c_compstr1646_sel_x_b_1(DELAY,29427)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1199_i_conv_i_i_i_i97_i_58_c_compstr1646_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_58_c_compstr1646_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18553_dupName_232_i_unnamed_c_compstr0_shift_x(BITSELECT,18552)@129
    assign rightShiftStage1Idx1Rng8_uid18553_dupName_232_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18552_dupName_232_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18555_dupName_232_i_unnamed_c_compstr0_shift_x(BITJOIN,18554)@129
    assign rightShiftStage1Idx1_uid18555_dupName_232_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18553_dupName_232_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18548_dupName_232_i_unnamed_c_compstr0_shift_x(BITSELECT,18547)@129
    assign rightShiftStage0Idx1Rng4_uid18548_dupName_232_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_q[33:4];

    // rightShiftStage0Idx1_uid18550_dupName_232_i_unnamed_c_compstr0_shift_x(BITJOIN,18549)@129
    assign rightShiftStage0Idx1_uid18550_dupName_232_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18548_dupName_232_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18552_dupName_232_i_unnamed_c_compstr0_shift_x(MUX,18551)@129
    assign rightShiftStage0_uid18552_dupName_232_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18552_dupName_232_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_q or rightShiftStage0Idx1_uid18550_dupName_232_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18552_dupName_232_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18552_dupName_232_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compstr1644_q;
            1'b1 : rightShiftStage0_uid18552_dupName_232_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18550_dupName_232_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18552_dupName_232_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18557_dupName_232_i_unnamed_c_compstr0_shift_x(MUX,18556)@129
    assign rightShiftStage1_uid18557_dupName_232_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18557_dupName_232_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18552_dupName_232_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18555_dupName_232_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18557_dupName_232_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18557_dupName_232_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18552_dupName_232_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18557_dupName_232_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18555_dupName_232_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18557_dupName_232_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1647_vt_select_21(BITSELECT,10364)@129
    assign i_unnamed_c_compstr1647_vt_select_21_b = rightShiftStage1_uid18557_dupName_232_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1647_vt_join(BITJOIN,10363)@129
    assign i_unnamed_c_compstr1647_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1647_vt_select_21_b};

    // i_unnamed_c_compstr1648_sel_x(BITSELECT,6086)@129
    assign i_unnamed_c_compstr1648_sel_x_b = i_unnamed_c_compstr1647_vt_join_q[15:0];

    // i_unnamed_c_compstr1649_BitSelect_for_a(BITSELECT,27559)@129
    assign i_unnamed_c_compstr1649_BitSelect_for_a_b = i_unnamed_c_compstr1648_sel_x_b[0:0];

    // i_unnamed_c_compstr1649_join(BITJOIN,27560)@129
    assign i_unnamed_c_compstr1649_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1649_BitSelect_for_a_b};

    // i_unnamed_c_compstr1649_vt_select_0(BITSELECT,10369)@129
    assign i_unnamed_c_compstr1649_vt_select_0_b = i_unnamed_c_compstr1649_join_q[0:0];

    // redist205_i_unnamed_c_compstr1649_vt_select_0_b_1(DELAY,28433)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist205_i_unnamed_c_compstr1649_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1649_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1649_vt_join(BITJOIN,10368)@130
    assign i_unnamed_c_compstr1649_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist205_i_unnamed_c_compstr1649_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_58_c_compstr1650(ADD,6932)@130
    assign i_add_i_i_i_i_i126_i_58_c_compstr1650_a = {1'b0, i_unnamed_c_compstr1649_vt_join_q};
    assign i_add_i_i_i_i_i126_i_58_c_compstr1650_b = {1'b0, redist1199_i_conv_i_i_i_i97_i_58_c_compstr1646_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_58_c_compstr1650_o = $unsigned(i_add_i_i_i_i_i126_i_58_c_compstr1650_a) + $unsigned(i_add_i_i_i_i_i126_i_58_c_compstr1650_b);
    assign i_add_i_i_i_i_i126_i_58_c_compstr1650_q = i_add_i_i_i_i_i126_i_58_c_compstr1650_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_58_c_compstr1650_sel_x(BITSELECT,2126)@130
    assign bgTrunc_i_add_i_i_i_i_i126_i_58_c_compstr1650_sel_x_b = i_add_i_i_i_i_i126_i_58_c_compstr1650_q[15:0];

    // i_conv_i_i_i_i_i75_i277_59_c_compstr1670_sel_x(BITSELECT,3667)@130
    assign i_conv_i_i_i_i_i75_i277_59_c_compstr1670_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_58_c_compstr1650_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_59_c_compstr1670_vt_select_15(BITSELECT,7569)@130
    assign i_conv_i_i_i_i_i75_i277_59_c_compstr1670_vt_select_15_b = i_conv_i_i_i_i_i75_i277_59_c_compstr1670_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_59_c_compstr1670_vt_join(BITJOIN,7568)@130
    assign i_conv_i_i_i_i_i75_i277_59_c_compstr1670_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_59_c_compstr1670_vt_select_15_b};

    // leftShiftStage0_uid24332_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x(MUX,24331)@130
    assign leftShiftStage0_uid24332_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24332_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_59_c_compstr1670_vt_join_q or leftShiftStage0Idx1_uid24330_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24332_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24332_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_59_c_compstr1670_vt_join_q;
            1'b1 : leftShiftStage0_uid24332_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24330_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24332_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24337_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x(MUX,24336)@130
    assign leftShiftStage1_uid24337_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24337_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_s or leftShiftStage0_uid24332_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24335_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24337_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24337_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q = leftShiftStage0_uid24332_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24337_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24335_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24337_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24342_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x(MUX,24341)@130
    assign leftShiftStage2_uid24342_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24342_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_s or leftShiftStage1_uid24337_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24340_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24342_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24342_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q = leftShiftStage1_uid24337_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24342_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24340_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24342_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_59_c_compstr1671_vt_select_28(BITSELECT,9286)@130
    assign i_shl_i_i_i_i_i77_i_59_c_compstr1671_vt_select_28_b = leftShiftStage2_uid24342_i_shl_i_i_i_i_i77_i_59_c_compstr0_shift_x_q[28:13];

    // redist428_i_shl_i_i_i_i_i77_i_59_c_compstr1671_vt_select_28_b_1(DELAY,28656)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist428_i_shl_i_i_i_i_i77_i_59_c_compstr1671_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_59_c_compstr1671_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_59_c_compstr1671_vt_join(BITJOIN,9285)@131
    assign i_shl_i_i_i_i_i77_i_59_c_compstr1671_vt_join_q = {redist428_i_shl_i_i_i_i_i77_i_59_c_compstr1671_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma(CHAINMULTADD,28180)@125 + 5
    // out q@131
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ah[0] <= redist889_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_119_tpl_117_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ah[1] <= redist888_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_118_tpl_117_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ch[0] <= redist635_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_119_tpl_117_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ch[1] <= redist634_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_118_tpl_117_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672(ADD,8476)@131
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compstr1667_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compstr1669_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compstr1668_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_59_c_compstr1671_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_59_c_compstr1671_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_o[33:0];

    // rightShiftStage0_uid18596_dupName_235_i_unnamed_c_compstr0_shift_x(MUX,18595)@131
    assign rightShiftStage0_uid18596_dupName_235_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18596_dupName_235_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_q or rightShiftStage0Idx1_uid18594_dupName_235_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18596_dupName_235_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18596_dupName_235_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_q;
            1'b1 : rightShiftStage0_uid18596_dupName_235_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18594_dupName_235_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18596_dupName_235_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18601_dupName_235_i_unnamed_c_compstr0_shift_x(MUX,18600)@131
    assign rightShiftStage1_uid18601_dupName_235_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18601_dupName_235_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18596_dupName_235_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18599_dupName_235_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18601_dupName_235_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18601_dupName_235_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18596_dupName_235_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18601_dupName_235_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18599_dupName_235_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18601_dupName_235_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18606_dupName_235_i_unnamed_c_compstr0_shift_x(MUX,18605)@131
    assign rightShiftStage2_uid18606_dupName_235_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18606_dupName_235_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18601_dupName_235_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18604_dupName_235_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18606_dupName_235_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18606_dupName_235_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18601_dupName_235_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18606_dupName_235_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18604_dupName_235_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18606_dupName_235_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1673_vt_select_20(BITSELECT,10388)@131
    assign i_unnamed_c_compstr1673_vt_select_20_b = rightShiftStage2_uid18606_dupName_235_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1673_vt_join(BITJOIN,10387)@131
    assign i_unnamed_c_compstr1673_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1673_vt_select_20_b};

    // i_conv_i_i_i_i97_i_59_c_compstr1674_sel_x(BITSELECT,3538)@131
    assign i_conv_i_i_i_i97_i_59_c_compstr1674_sel_x_b = i_unnamed_c_compstr1673_vt_join_q[15:0];

    // redist1198_i_conv_i_i_i_i97_i_59_c_compstr1674_sel_x_b_1(DELAY,29426)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1198_i_conv_i_i_i_i97_i_59_c_compstr1674_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_59_c_compstr1674_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18615_dupName_236_i_unnamed_c_compstr0_shift_x(BITSELECT,18614)@131
    assign rightShiftStage1Idx1Rng8_uid18615_dupName_236_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18614_dupName_236_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18617_dupName_236_i_unnamed_c_compstr0_shift_x(BITJOIN,18616)@131
    assign rightShiftStage1Idx1_uid18617_dupName_236_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18615_dupName_236_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18610_dupName_236_i_unnamed_c_compstr0_shift_x(BITSELECT,18609)@131
    assign rightShiftStage0Idx1Rng4_uid18610_dupName_236_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_q[33:4];

    // rightShiftStage0Idx1_uid18612_dupName_236_i_unnamed_c_compstr0_shift_x(BITJOIN,18611)@131
    assign rightShiftStage0Idx1_uid18612_dupName_236_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18610_dupName_236_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18614_dupName_236_i_unnamed_c_compstr0_shift_x(MUX,18613)@131
    assign rightShiftStage0_uid18614_dupName_236_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18614_dupName_236_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_q or rightShiftStage0Idx1_uid18612_dupName_236_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18614_dupName_236_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18614_dupName_236_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compstr1672_q;
            1'b1 : rightShiftStage0_uid18614_dupName_236_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18612_dupName_236_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18614_dupName_236_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18619_dupName_236_i_unnamed_c_compstr0_shift_x(MUX,18618)@131
    assign rightShiftStage1_uid18619_dupName_236_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18619_dupName_236_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18614_dupName_236_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18617_dupName_236_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18619_dupName_236_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18619_dupName_236_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18614_dupName_236_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18619_dupName_236_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18617_dupName_236_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18619_dupName_236_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1675_vt_select_21(BITSELECT,10391)@131
    assign i_unnamed_c_compstr1675_vt_select_21_b = rightShiftStage1_uid18619_dupName_236_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1675_vt_join(BITJOIN,10390)@131
    assign i_unnamed_c_compstr1675_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1675_vt_select_21_b};

    // i_unnamed_c_compstr1676_sel_x(BITSELECT,6088)@131
    assign i_unnamed_c_compstr1676_sel_x_b = i_unnamed_c_compstr1675_vt_join_q[15:0];

    // i_unnamed_c_compstr1677_BitSelect_for_a(BITSELECT,27565)@131
    assign i_unnamed_c_compstr1677_BitSelect_for_a_b = i_unnamed_c_compstr1676_sel_x_b[0:0];

    // i_unnamed_c_compstr1677_join(BITJOIN,27566)@131
    assign i_unnamed_c_compstr1677_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1677_BitSelect_for_a_b};

    // i_unnamed_c_compstr1677_vt_select_0(BITSELECT,10396)@131
    assign i_unnamed_c_compstr1677_vt_select_0_b = i_unnamed_c_compstr1677_join_q[0:0];

    // redist202_i_unnamed_c_compstr1677_vt_select_0_b_1(DELAY,28430)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist202_i_unnamed_c_compstr1677_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1677_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1677_vt_join(BITJOIN,10395)@132
    assign i_unnamed_c_compstr1677_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist202_i_unnamed_c_compstr1677_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_59_c_compstr1678(ADD,6933)@132
    assign i_add_i_i_i_i_i126_i_59_c_compstr1678_a = {1'b0, i_unnamed_c_compstr1677_vt_join_q};
    assign i_add_i_i_i_i_i126_i_59_c_compstr1678_b = {1'b0, redist1198_i_conv_i_i_i_i97_i_59_c_compstr1674_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_59_c_compstr1678_o = $unsigned(i_add_i_i_i_i_i126_i_59_c_compstr1678_a) + $unsigned(i_add_i_i_i_i_i126_i_59_c_compstr1678_b);
    assign i_add_i_i_i_i_i126_i_59_c_compstr1678_q = i_add_i_i_i_i_i126_i_59_c_compstr1678_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_59_c_compstr1678_sel_x(BITSELECT,2127)@132
    assign bgTrunc_i_add_i_i_i_i_i126_i_59_c_compstr1678_sel_x_b = i_add_i_i_i_i_i126_i_59_c_compstr1678_q[15:0];

    // i_conv_i_i_i_i_i75_i277_60_c_compstr1698_sel_x(BITSELECT,3669)@132
    assign i_conv_i_i_i_i_i75_i277_60_c_compstr1698_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_59_c_compstr1678_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_60_c_compstr1698_vt_select_15(BITSELECT,7577)@132
    assign i_conv_i_i_i_i_i75_i277_60_c_compstr1698_vt_select_15_b = i_conv_i_i_i_i_i75_i277_60_c_compstr1698_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_60_c_compstr1698_vt_join(BITJOIN,7576)@132
    assign i_conv_i_i_i_i_i75_i277_60_c_compstr1698_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_60_c_compstr1698_vt_select_15_b};

    // leftShiftStage0_uid24368_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x(MUX,24367)@132
    assign leftShiftStage0_uid24368_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24368_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_60_c_compstr1698_vt_join_q or leftShiftStage0Idx1_uid24366_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24368_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24368_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_60_c_compstr1698_vt_join_q;
            1'b1 : leftShiftStage0_uid24368_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24366_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24368_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24373_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x(MUX,24372)@132
    assign leftShiftStage1_uid24373_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24373_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_s or leftShiftStage0_uid24368_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24371_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24373_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24373_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q = leftShiftStage0_uid24368_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24373_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24371_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24373_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24378_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x(MUX,24377)@132
    assign leftShiftStage2_uid24378_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24378_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_s or leftShiftStage1_uid24373_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24376_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24378_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24378_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q = leftShiftStage1_uid24373_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24378_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24376_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24378_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_60_c_compstr1699_vt_select_28(BITSELECT,9292)@132
    assign i_shl_i_i_i_i_i77_i_60_c_compstr1699_vt_select_28_b = leftShiftStage2_uid24378_i_shl_i_i_i_i_i77_i_60_c_compstr0_shift_x_q[28:13];

    // redist426_i_shl_i_i_i_i_i77_i_60_c_compstr1699_vt_select_28_b_1(DELAY,28654)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist426_i_shl_i_i_i_i_i77_i_60_c_compstr1699_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_60_c_compstr1699_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_60_c_compstr1699_vt_join(BITJOIN,9291)@133
    assign i_shl_i_i_i_i_i77_i_60_c_compstr1699_vt_join_q = {redist426_i_shl_i_i_i_i_i77_i_60_c_compstr1699_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma(CHAINMULTADD,28182)@127 + 5
    // out q@133
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ah[0] <= redist891_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_121_tpl_119_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ah[1] <= redist890_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_120_tpl_119_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ch[0] <= redist637_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_121_tpl_119_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ch[1] <= redist636_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_120_tpl_119_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700(ADD,8478)@133
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compstr1695_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compstr1697_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compstr1696_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_60_c_compstr1699_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_60_c_compstr1699_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_o[33:0];

    // rightShiftStage0_uid18658_dupName_239_i_unnamed_c_compstr0_shift_x(MUX,18657)@133
    assign rightShiftStage0_uid18658_dupName_239_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18658_dupName_239_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_q or rightShiftStage0Idx1_uid18656_dupName_239_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18658_dupName_239_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18658_dupName_239_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_q;
            1'b1 : rightShiftStage0_uid18658_dupName_239_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18656_dupName_239_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18658_dupName_239_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18663_dupName_239_i_unnamed_c_compstr0_shift_x(MUX,18662)@133
    assign rightShiftStage1_uid18663_dupName_239_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18663_dupName_239_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18658_dupName_239_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18661_dupName_239_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18663_dupName_239_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18663_dupName_239_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18658_dupName_239_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18663_dupName_239_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18661_dupName_239_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18663_dupName_239_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18668_dupName_239_i_unnamed_c_compstr0_shift_x(MUX,18667)@133
    assign rightShiftStage2_uid18668_dupName_239_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18668_dupName_239_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18663_dupName_239_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18666_dupName_239_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18668_dupName_239_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18668_dupName_239_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18663_dupName_239_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18668_dupName_239_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18666_dupName_239_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18668_dupName_239_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1701_vt_select_20(BITSELECT,10410)@133
    assign i_unnamed_c_compstr1701_vt_select_20_b = rightShiftStage2_uid18668_dupName_239_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1701_vt_join(BITJOIN,10409)@133
    assign i_unnamed_c_compstr1701_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1701_vt_select_20_b};

    // i_conv_i_i_i_i97_i_60_c_compstr1702_sel_x(BITSELECT,3540)@133
    assign i_conv_i_i_i_i97_i_60_c_compstr1702_sel_x_b = i_unnamed_c_compstr1701_vt_join_q[15:0];

    // redist1196_i_conv_i_i_i_i97_i_60_c_compstr1702_sel_x_b_1(DELAY,29424)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1196_i_conv_i_i_i_i97_i_60_c_compstr1702_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_60_c_compstr1702_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18677_dupName_240_i_unnamed_c_compstr0_shift_x(BITSELECT,18676)@133
    assign rightShiftStage1Idx1Rng8_uid18677_dupName_240_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18676_dupName_240_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18679_dupName_240_i_unnamed_c_compstr0_shift_x(BITJOIN,18678)@133
    assign rightShiftStage1Idx1_uid18679_dupName_240_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18677_dupName_240_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18672_dupName_240_i_unnamed_c_compstr0_shift_x(BITSELECT,18671)@133
    assign rightShiftStage0Idx1Rng4_uid18672_dupName_240_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_q[33:4];

    // rightShiftStage0Idx1_uid18674_dupName_240_i_unnamed_c_compstr0_shift_x(BITJOIN,18673)@133
    assign rightShiftStage0Idx1_uid18674_dupName_240_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18672_dupName_240_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18676_dupName_240_i_unnamed_c_compstr0_shift_x(MUX,18675)@133
    assign rightShiftStage0_uid18676_dupName_240_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18676_dupName_240_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_q or rightShiftStage0Idx1_uid18674_dupName_240_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18676_dupName_240_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18676_dupName_240_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compstr1700_q;
            1'b1 : rightShiftStage0_uid18676_dupName_240_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18674_dupName_240_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18676_dupName_240_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18681_dupName_240_i_unnamed_c_compstr0_shift_x(MUX,18680)@133
    assign rightShiftStage1_uid18681_dupName_240_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18681_dupName_240_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18676_dupName_240_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18679_dupName_240_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18681_dupName_240_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18681_dupName_240_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18676_dupName_240_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18681_dupName_240_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18679_dupName_240_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18681_dupName_240_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1703_vt_select_21(BITSELECT,10413)@133
    assign i_unnamed_c_compstr1703_vt_select_21_b = rightShiftStage1_uid18681_dupName_240_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1703_vt_join(BITJOIN,10412)@133
    assign i_unnamed_c_compstr1703_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1703_vt_select_21_b};

    // i_unnamed_c_compstr1704_sel_x(BITSELECT,6090)@133
    assign i_unnamed_c_compstr1704_sel_x_b = i_unnamed_c_compstr1703_vt_join_q[15:0];

    // i_unnamed_c_compstr1705_BitSelect_for_a(BITSELECT,27569)@133
    assign i_unnamed_c_compstr1705_BitSelect_for_a_b = i_unnamed_c_compstr1704_sel_x_b[0:0];

    // i_unnamed_c_compstr1705_join(BITJOIN,27570)@133
    assign i_unnamed_c_compstr1705_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1705_BitSelect_for_a_b};

    // i_unnamed_c_compstr1705_vt_select_0(BITSELECT,10418)@133
    assign i_unnamed_c_compstr1705_vt_select_0_b = i_unnamed_c_compstr1705_join_q[0:0];

    // redist200_i_unnamed_c_compstr1705_vt_select_0_b_1(DELAY,28428)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist200_i_unnamed_c_compstr1705_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1705_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1705_vt_join(BITJOIN,10417)@134
    assign i_unnamed_c_compstr1705_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist200_i_unnamed_c_compstr1705_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_60_c_compstr1706(ADD,6935)@134
    assign i_add_i_i_i_i_i126_i_60_c_compstr1706_a = {1'b0, i_unnamed_c_compstr1705_vt_join_q};
    assign i_add_i_i_i_i_i126_i_60_c_compstr1706_b = {1'b0, redist1196_i_conv_i_i_i_i97_i_60_c_compstr1702_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_60_c_compstr1706_o = $unsigned(i_add_i_i_i_i_i126_i_60_c_compstr1706_a) + $unsigned(i_add_i_i_i_i_i126_i_60_c_compstr1706_b);
    assign i_add_i_i_i_i_i126_i_60_c_compstr1706_q = i_add_i_i_i_i_i126_i_60_c_compstr1706_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_60_c_compstr1706_sel_x(BITSELECT,2129)@134
    assign bgTrunc_i_add_i_i_i_i_i126_i_60_c_compstr1706_sel_x_b = i_add_i_i_i_i_i126_i_60_c_compstr1706_q[15:0];

    // i_conv_i_i_i_i_i75_i277_61_c_compstr1726_sel_x(BITSELECT,3670)@134
    assign i_conv_i_i_i_i_i75_i277_61_c_compstr1726_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_60_c_compstr1706_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_61_c_compstr1726_vt_select_15(BITSELECT,7581)@134
    assign i_conv_i_i_i_i_i75_i277_61_c_compstr1726_vt_select_15_b = i_conv_i_i_i_i_i75_i277_61_c_compstr1726_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_61_c_compstr1726_vt_join(BITJOIN,7580)@134
    assign i_conv_i_i_i_i_i75_i277_61_c_compstr1726_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_61_c_compstr1726_vt_select_15_b};

    // leftShiftStage0_uid24386_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x(MUX,24385)@134
    assign leftShiftStage0_uid24386_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24386_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_61_c_compstr1726_vt_join_q or leftShiftStage0Idx1_uid24384_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24386_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24386_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_61_c_compstr1726_vt_join_q;
            1'b1 : leftShiftStage0_uid24386_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24384_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24386_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24391_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x(MUX,24390)@134
    assign leftShiftStage1_uid24391_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24391_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_s or leftShiftStage0_uid24386_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24389_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24391_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24391_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q = leftShiftStage0_uid24386_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24391_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24389_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24391_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24396_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x(MUX,24395)@134
    assign leftShiftStage2_uid24396_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24396_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_s or leftShiftStage1_uid24391_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24394_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24396_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24396_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q = leftShiftStage1_uid24391_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24396_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24394_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24396_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_61_c_compstr1727_vt_select_28(BITSELECT,9295)@134
    assign i_shl_i_i_i_i_i77_i_61_c_compstr1727_vt_select_28_b = leftShiftStage2_uid24396_i_shl_i_i_i_i_i77_i_61_c_compstr0_shift_x_q[28:13];

    // redist425_i_shl_i_i_i_i_i77_i_61_c_compstr1727_vt_select_28_b_1(DELAY,28653)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist425_i_shl_i_i_i_i_i77_i_61_c_compstr1727_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_61_c_compstr1727_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_61_c_compstr1727_vt_join(BITJOIN,9294)@135
    assign i_shl_i_i_i_i_i77_i_61_c_compstr1727_vt_join_q = {redist425_i_shl_i_i_i_i_i77_i_61_c_compstr1727_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma(CHAINMULTADD,28183)@129 + 5
    // out q@135
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ah[0] <= redist893_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_123_tpl_121_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ah[1] <= redist892_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_122_tpl_121_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ch[0] <= redist639_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_123_tpl_121_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ch[1] <= redist638_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_122_tpl_121_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728(ADD,8479)@135
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compstr1723_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compstr1725_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compstr1724_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_61_c_compstr1727_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_61_c_compstr1727_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_o[33:0];

    // rightShiftStage0_uid18720_dupName_243_i_unnamed_c_compstr0_shift_x(MUX,18719)@135
    assign rightShiftStage0_uid18720_dupName_243_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18720_dupName_243_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_q or rightShiftStage0Idx1_uid18718_dupName_243_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18720_dupName_243_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18720_dupName_243_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_q;
            1'b1 : rightShiftStage0_uid18720_dupName_243_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18718_dupName_243_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18720_dupName_243_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18725_dupName_243_i_unnamed_c_compstr0_shift_x(MUX,18724)@135
    assign rightShiftStage1_uid18725_dupName_243_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18725_dupName_243_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18720_dupName_243_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18723_dupName_243_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18725_dupName_243_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18725_dupName_243_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18720_dupName_243_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18725_dupName_243_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18723_dupName_243_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18725_dupName_243_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18730_dupName_243_i_unnamed_c_compstr0_shift_x(MUX,18729)@135
    assign rightShiftStage2_uid18730_dupName_243_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18730_dupName_243_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18725_dupName_243_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18728_dupName_243_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18730_dupName_243_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18730_dupName_243_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18725_dupName_243_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18730_dupName_243_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18728_dupName_243_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18730_dupName_243_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1729_vt_select_20(BITSELECT,10432)@135
    assign i_unnamed_c_compstr1729_vt_select_20_b = rightShiftStage2_uid18730_dupName_243_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1729_vt_join(BITJOIN,10431)@135
    assign i_unnamed_c_compstr1729_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1729_vt_select_20_b};

    // i_conv_i_i_i_i97_i_61_c_compstr1730_sel_x(BITSELECT,3541)@135
    assign i_conv_i_i_i_i97_i_61_c_compstr1730_sel_x_b = i_unnamed_c_compstr1729_vt_join_q[15:0];

    // redist1195_i_conv_i_i_i_i97_i_61_c_compstr1730_sel_x_b_1(DELAY,29423)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1195_i_conv_i_i_i_i97_i_61_c_compstr1730_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_61_c_compstr1730_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18739_dupName_244_i_unnamed_c_compstr0_shift_x(BITSELECT,18738)@135
    assign rightShiftStage1Idx1Rng8_uid18739_dupName_244_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18738_dupName_244_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18741_dupName_244_i_unnamed_c_compstr0_shift_x(BITJOIN,18740)@135
    assign rightShiftStage1Idx1_uid18741_dupName_244_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18739_dupName_244_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18734_dupName_244_i_unnamed_c_compstr0_shift_x(BITSELECT,18733)@135
    assign rightShiftStage0Idx1Rng4_uid18734_dupName_244_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_q[33:4];

    // rightShiftStage0Idx1_uid18736_dupName_244_i_unnamed_c_compstr0_shift_x(BITJOIN,18735)@135
    assign rightShiftStage0Idx1_uid18736_dupName_244_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18734_dupName_244_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18738_dupName_244_i_unnamed_c_compstr0_shift_x(MUX,18737)@135
    assign rightShiftStage0_uid18738_dupName_244_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18738_dupName_244_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_q or rightShiftStage0Idx1_uid18736_dupName_244_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18738_dupName_244_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18738_dupName_244_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compstr1728_q;
            1'b1 : rightShiftStage0_uid18738_dupName_244_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18736_dupName_244_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18738_dupName_244_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18743_dupName_244_i_unnamed_c_compstr0_shift_x(MUX,18742)@135
    assign rightShiftStage1_uid18743_dupName_244_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18743_dupName_244_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18738_dupName_244_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18741_dupName_244_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18743_dupName_244_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18743_dupName_244_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18738_dupName_244_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18743_dupName_244_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18741_dupName_244_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18743_dupName_244_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1731_vt_select_21(BITSELECT,10435)@135
    assign i_unnamed_c_compstr1731_vt_select_21_b = rightShiftStage1_uid18743_dupName_244_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1731_vt_join(BITJOIN,10434)@135
    assign i_unnamed_c_compstr1731_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1731_vt_select_21_b};

    // i_unnamed_c_compstr1732_sel_x(BITSELECT,6092)@135
    assign i_unnamed_c_compstr1732_sel_x_b = i_unnamed_c_compstr1731_vt_join_q[15:0];

    // i_unnamed_c_compstr1733_BitSelect_for_a(BITSELECT,27573)@135
    assign i_unnamed_c_compstr1733_BitSelect_for_a_b = i_unnamed_c_compstr1732_sel_x_b[0:0];

    // i_unnamed_c_compstr1733_join(BITJOIN,27574)@135
    assign i_unnamed_c_compstr1733_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1733_BitSelect_for_a_b};

    // i_unnamed_c_compstr1733_vt_select_0(BITSELECT,10440)@135
    assign i_unnamed_c_compstr1733_vt_select_0_b = i_unnamed_c_compstr1733_join_q[0:0];

    // redist198_i_unnamed_c_compstr1733_vt_select_0_b_1(DELAY,28426)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist198_i_unnamed_c_compstr1733_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1733_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1733_vt_join(BITJOIN,10439)@136
    assign i_unnamed_c_compstr1733_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist198_i_unnamed_c_compstr1733_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_61_c_compstr1734(ADD,6936)@136
    assign i_add_i_i_i_i_i126_i_61_c_compstr1734_a = {1'b0, i_unnamed_c_compstr1733_vt_join_q};
    assign i_add_i_i_i_i_i126_i_61_c_compstr1734_b = {1'b0, redist1195_i_conv_i_i_i_i97_i_61_c_compstr1730_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_61_c_compstr1734_o = $unsigned(i_add_i_i_i_i_i126_i_61_c_compstr1734_a) + $unsigned(i_add_i_i_i_i_i126_i_61_c_compstr1734_b);
    assign i_add_i_i_i_i_i126_i_61_c_compstr1734_q = i_add_i_i_i_i_i126_i_61_c_compstr1734_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_61_c_compstr1734_sel_x(BITSELECT,2130)@136
    assign bgTrunc_i_add_i_i_i_i_i126_i_61_c_compstr1734_sel_x_b = i_add_i_i_i_i_i126_i_61_c_compstr1734_q[15:0];

    // i_conv_i_i_i_i_i75_i277_62_c_compstr1754_sel_x(BITSELECT,3671)@136
    assign i_conv_i_i_i_i_i75_i277_62_c_compstr1754_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_61_c_compstr1734_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_62_c_compstr1754_vt_select_15(BITSELECT,7585)@136
    assign i_conv_i_i_i_i_i75_i277_62_c_compstr1754_vt_select_15_b = i_conv_i_i_i_i_i75_i277_62_c_compstr1754_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_62_c_compstr1754_vt_join(BITJOIN,7584)@136
    assign i_conv_i_i_i_i_i75_i277_62_c_compstr1754_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_62_c_compstr1754_vt_select_15_b};

    // leftShiftStage0_uid24404_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x(MUX,24403)@136
    assign leftShiftStage0_uid24404_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24404_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_62_c_compstr1754_vt_join_q or leftShiftStage0Idx1_uid24402_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24404_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24404_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_62_c_compstr1754_vt_join_q;
            1'b1 : leftShiftStage0_uid24404_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24402_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24404_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24409_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x(MUX,24408)@136
    assign leftShiftStage1_uid24409_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24409_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_s or leftShiftStage0_uid24404_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24407_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24409_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24409_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q = leftShiftStage0_uid24404_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24409_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24407_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24409_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24414_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x(MUX,24413)@136
    assign leftShiftStage2_uid24414_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24414_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_s or leftShiftStage1_uid24409_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24412_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24414_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24414_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q = leftShiftStage1_uid24409_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24414_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24412_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24414_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_62_c_compstr1755_vt_select_28(BITSELECT,9298)@136
    assign i_shl_i_i_i_i_i77_i_62_c_compstr1755_vt_select_28_b = leftShiftStage2_uid24414_i_shl_i_i_i_i_i77_i_62_c_compstr0_shift_x_q[28:13];

    // redist424_i_shl_i_i_i_i_i77_i_62_c_compstr1755_vt_select_28_b_1(DELAY,28652)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist424_i_shl_i_i_i_i_i77_i_62_c_compstr1755_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_62_c_compstr1755_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_62_c_compstr1755_vt_join(BITJOIN,9297)@137
    assign i_shl_i_i_i_i_i77_i_62_c_compstr1755_vt_join_q = {redist424_i_shl_i_i_i_i_i77_i_62_c_compstr1755_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma(CHAINMULTADD,28184)@131 + 5
    // out q@137
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ah[0] <= redist895_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_125_tpl_123_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ah[1] <= redist894_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_124_tpl_123_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ch[0] <= redist641_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_125_tpl_123_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ch[1] <= redist640_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_124_tpl_123_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756(ADD,8480)@137
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compstr1751_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compstr1753_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compstr1752_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_62_c_compstr1755_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_62_c_compstr1755_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_o[33:0];

    // rightShiftStage0_uid18782_dupName_247_i_unnamed_c_compstr0_shift_x(MUX,18781)@137
    assign rightShiftStage0_uid18782_dupName_247_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18782_dupName_247_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_q or rightShiftStage0Idx1_uid18780_dupName_247_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18782_dupName_247_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18782_dupName_247_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_q;
            1'b1 : rightShiftStage0_uid18782_dupName_247_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18780_dupName_247_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18782_dupName_247_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18787_dupName_247_i_unnamed_c_compstr0_shift_x(MUX,18786)@137
    assign rightShiftStage1_uid18787_dupName_247_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18787_dupName_247_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18782_dupName_247_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18785_dupName_247_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18787_dupName_247_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18787_dupName_247_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18782_dupName_247_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18787_dupName_247_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18785_dupName_247_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18787_dupName_247_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18792_dupName_247_i_unnamed_c_compstr0_shift_x(MUX,18791)@137
    assign rightShiftStage2_uid18792_dupName_247_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18792_dupName_247_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18787_dupName_247_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18790_dupName_247_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18792_dupName_247_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18792_dupName_247_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18787_dupName_247_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18792_dupName_247_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18790_dupName_247_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18792_dupName_247_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1757_vt_select_20(BITSELECT,10454)@137
    assign i_unnamed_c_compstr1757_vt_select_20_b = rightShiftStage2_uid18792_dupName_247_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1757_vt_join(BITJOIN,10453)@137
    assign i_unnamed_c_compstr1757_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1757_vt_select_20_b};

    // i_conv_i_i_i_i97_i_62_c_compstr1758_sel_x(BITSELECT,3542)@137
    assign i_conv_i_i_i_i97_i_62_c_compstr1758_sel_x_b = i_unnamed_c_compstr1757_vt_join_q[15:0];

    // redist1194_i_conv_i_i_i_i97_i_62_c_compstr1758_sel_x_b_1(DELAY,29422)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1194_i_conv_i_i_i_i97_i_62_c_compstr1758_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_62_c_compstr1758_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18801_dupName_248_i_unnamed_c_compstr0_shift_x(BITSELECT,18800)@137
    assign rightShiftStage1Idx1Rng8_uid18801_dupName_248_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18800_dupName_248_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18803_dupName_248_i_unnamed_c_compstr0_shift_x(BITJOIN,18802)@137
    assign rightShiftStage1Idx1_uid18803_dupName_248_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18801_dupName_248_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18796_dupName_248_i_unnamed_c_compstr0_shift_x(BITSELECT,18795)@137
    assign rightShiftStage0Idx1Rng4_uid18796_dupName_248_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_q[33:4];

    // rightShiftStage0Idx1_uid18798_dupName_248_i_unnamed_c_compstr0_shift_x(BITJOIN,18797)@137
    assign rightShiftStage0Idx1_uid18798_dupName_248_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18796_dupName_248_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18800_dupName_248_i_unnamed_c_compstr0_shift_x(MUX,18799)@137
    assign rightShiftStage0_uid18800_dupName_248_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18800_dupName_248_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_q or rightShiftStage0Idx1_uid18798_dupName_248_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18800_dupName_248_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18800_dupName_248_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compstr1756_q;
            1'b1 : rightShiftStage0_uid18800_dupName_248_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18798_dupName_248_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18800_dupName_248_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18805_dupName_248_i_unnamed_c_compstr0_shift_x(MUX,18804)@137
    assign rightShiftStage1_uid18805_dupName_248_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18805_dupName_248_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18800_dupName_248_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18803_dupName_248_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18805_dupName_248_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18805_dupName_248_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18800_dupName_248_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18805_dupName_248_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18803_dupName_248_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18805_dupName_248_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1759_vt_select_21(BITSELECT,10457)@137
    assign i_unnamed_c_compstr1759_vt_select_21_b = rightShiftStage1_uid18805_dupName_248_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1759_vt_join(BITJOIN,10456)@137
    assign i_unnamed_c_compstr1759_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1759_vt_select_21_b};

    // i_unnamed_c_compstr1760_sel_x(BITSELECT,6094)@137
    assign i_unnamed_c_compstr1760_sel_x_b = i_unnamed_c_compstr1759_vt_join_q[15:0];

    // i_unnamed_c_compstr1761_BitSelect_for_a(BITSELECT,27577)@137
    assign i_unnamed_c_compstr1761_BitSelect_for_a_b = i_unnamed_c_compstr1760_sel_x_b[0:0];

    // i_unnamed_c_compstr1761_join(BITJOIN,27578)@137
    assign i_unnamed_c_compstr1761_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1761_BitSelect_for_a_b};

    // i_unnamed_c_compstr1761_vt_select_0(BITSELECT,10462)@137
    assign i_unnamed_c_compstr1761_vt_select_0_b = i_unnamed_c_compstr1761_join_q[0:0];

    // redist196_i_unnamed_c_compstr1761_vt_select_0_b_1(DELAY,28424)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist196_i_unnamed_c_compstr1761_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1761_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1761_vt_join(BITJOIN,10461)@138
    assign i_unnamed_c_compstr1761_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist196_i_unnamed_c_compstr1761_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_62_c_compstr1762(ADD,6937)@138
    assign i_add_i_i_i_i_i126_i_62_c_compstr1762_a = {1'b0, i_unnamed_c_compstr1761_vt_join_q};
    assign i_add_i_i_i_i_i126_i_62_c_compstr1762_b = {1'b0, redist1194_i_conv_i_i_i_i97_i_62_c_compstr1758_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_62_c_compstr1762_o = $unsigned(i_add_i_i_i_i_i126_i_62_c_compstr1762_a) + $unsigned(i_add_i_i_i_i_i126_i_62_c_compstr1762_b);
    assign i_add_i_i_i_i_i126_i_62_c_compstr1762_q = i_add_i_i_i_i_i126_i_62_c_compstr1762_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_62_c_compstr1762_sel_x(BITSELECT,2131)@138
    assign bgTrunc_i_add_i_i_i_i_i126_i_62_c_compstr1762_sel_x_b = i_add_i_i_i_i_i126_i_62_c_compstr1762_q[15:0];

    // i_conv_i_i_i_i_i75_i277_63_c_compstr1782_sel_x(BITSELECT,3672)@138
    assign i_conv_i_i_i_i_i75_i277_63_c_compstr1782_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_62_c_compstr1762_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_63_c_compstr1782_vt_select_15(BITSELECT,7589)@138
    assign i_conv_i_i_i_i_i75_i277_63_c_compstr1782_vt_select_15_b = i_conv_i_i_i_i_i75_i277_63_c_compstr1782_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_63_c_compstr1782_vt_join(BITJOIN,7588)@138
    assign i_conv_i_i_i_i_i75_i277_63_c_compstr1782_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_63_c_compstr1782_vt_select_15_b};

    // leftShiftStage0_uid24422_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x(MUX,24421)@138
    assign leftShiftStage0_uid24422_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24422_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_63_c_compstr1782_vt_join_q or leftShiftStage0Idx1_uid24420_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24422_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24422_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_63_c_compstr1782_vt_join_q;
            1'b1 : leftShiftStage0_uid24422_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24420_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24422_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24427_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x(MUX,24426)@138
    assign leftShiftStage1_uid24427_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24427_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_s or leftShiftStage0_uid24422_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24425_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24427_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24427_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q = leftShiftStage0_uid24422_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24427_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24425_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24427_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24432_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x(MUX,24431)@138
    assign leftShiftStage2_uid24432_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24432_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_s or leftShiftStage1_uid24427_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24430_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24432_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24432_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q = leftShiftStage1_uid24427_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24432_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24430_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24432_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_63_c_compstr1783_vt_select_28(BITSELECT,9301)@138
    assign i_shl_i_i_i_i_i77_i_63_c_compstr1783_vt_select_28_b = leftShiftStage2_uid24432_i_shl_i_i_i_i_i77_i_63_c_compstr0_shift_x_q[28:13];

    // redist423_i_shl_i_i_i_i_i77_i_63_c_compstr1783_vt_select_28_b_1(DELAY,28651)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist423_i_shl_i_i_i_i_i77_i_63_c_compstr1783_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_63_c_compstr1783_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_63_c_compstr1783_vt_join(BITJOIN,9300)@139
    assign i_shl_i_i_i_i_i77_i_63_c_compstr1783_vt_join_q = {redist423_i_shl_i_i_i_i_i77_i_63_c_compstr1783_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma(CHAINMULTADD,28185)@133 + 5
    // out q@139
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ah[0] <= redist897_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_127_tpl_125_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ah[1] <= redist896_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_126_tpl_125_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ch[0] <= redist643_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_127_tpl_125_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ch[1] <= redist642_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_126_tpl_125_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784(ADD,8481)@139
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compstr1779_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compstr1781_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compstr1780_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_63_c_compstr1783_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_63_c_compstr1783_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_o[33:0];

    // rightShiftStage0_uid18844_dupName_251_i_unnamed_c_compstr0_shift_x(MUX,18843)@139
    assign rightShiftStage0_uid18844_dupName_251_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18844_dupName_251_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_q or rightShiftStage0Idx1_uid18842_dupName_251_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18844_dupName_251_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18844_dupName_251_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_q;
            1'b1 : rightShiftStage0_uid18844_dupName_251_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18842_dupName_251_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18844_dupName_251_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18849_dupName_251_i_unnamed_c_compstr0_shift_x(MUX,18848)@139
    assign rightShiftStage1_uid18849_dupName_251_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18849_dupName_251_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18844_dupName_251_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18847_dupName_251_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18849_dupName_251_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18849_dupName_251_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18844_dupName_251_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18849_dupName_251_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18847_dupName_251_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18849_dupName_251_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18854_dupName_251_i_unnamed_c_compstr0_shift_x(MUX,18853)@139
    assign rightShiftStage2_uid18854_dupName_251_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18854_dupName_251_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18849_dupName_251_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18852_dupName_251_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18854_dupName_251_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18854_dupName_251_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18849_dupName_251_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18854_dupName_251_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18852_dupName_251_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18854_dupName_251_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1785_vt_select_20(BITSELECT,10479)@139
    assign i_unnamed_c_compstr1785_vt_select_20_b = rightShiftStage2_uid18854_dupName_251_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1785_vt_join(BITJOIN,10478)@139
    assign i_unnamed_c_compstr1785_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1785_vt_select_20_b};

    // i_conv_i_i_i_i97_i_63_c_compstr1786_sel_x(BITSELECT,3543)@139
    assign i_conv_i_i_i_i97_i_63_c_compstr1786_sel_x_b = i_unnamed_c_compstr1785_vt_join_q[15:0];

    // redist1193_i_conv_i_i_i_i97_i_63_c_compstr1786_sel_x_b_1(DELAY,29421)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1193_i_conv_i_i_i_i97_i_63_c_compstr1786_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_63_c_compstr1786_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18863_dupName_252_i_unnamed_c_compstr0_shift_x(BITSELECT,18862)@139
    assign rightShiftStage1Idx1Rng8_uid18863_dupName_252_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18862_dupName_252_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18865_dupName_252_i_unnamed_c_compstr0_shift_x(BITJOIN,18864)@139
    assign rightShiftStage1Idx1_uid18865_dupName_252_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18863_dupName_252_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18858_dupName_252_i_unnamed_c_compstr0_shift_x(BITSELECT,18857)@139
    assign rightShiftStage0Idx1Rng4_uid18858_dupName_252_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_q[33:4];

    // rightShiftStage0Idx1_uid18860_dupName_252_i_unnamed_c_compstr0_shift_x(BITJOIN,18859)@139
    assign rightShiftStage0Idx1_uid18860_dupName_252_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18858_dupName_252_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18862_dupName_252_i_unnamed_c_compstr0_shift_x(MUX,18861)@139
    assign rightShiftStage0_uid18862_dupName_252_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18862_dupName_252_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_q or rightShiftStage0Idx1_uid18860_dupName_252_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18862_dupName_252_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18862_dupName_252_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compstr1784_q;
            1'b1 : rightShiftStage0_uid18862_dupName_252_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18860_dupName_252_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18862_dupName_252_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18867_dupName_252_i_unnamed_c_compstr0_shift_x(MUX,18866)@139
    assign rightShiftStage1_uid18867_dupName_252_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18867_dupName_252_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18862_dupName_252_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18865_dupName_252_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18867_dupName_252_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18867_dupName_252_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18862_dupName_252_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18867_dupName_252_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18865_dupName_252_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18867_dupName_252_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1787_vt_select_21(BITSELECT,10482)@139
    assign i_unnamed_c_compstr1787_vt_select_21_b = rightShiftStage1_uid18867_dupName_252_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1787_vt_join(BITJOIN,10481)@139
    assign i_unnamed_c_compstr1787_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1787_vt_select_21_b};

    // i_unnamed_c_compstr1788_sel_x(BITSELECT,6096)@139
    assign i_unnamed_c_compstr1788_sel_x_b = i_unnamed_c_compstr1787_vt_join_q[15:0];

    // i_unnamed_c_compstr1789_BitSelect_for_a(BITSELECT,27581)@139
    assign i_unnamed_c_compstr1789_BitSelect_for_a_b = i_unnamed_c_compstr1788_sel_x_b[0:0];

    // i_unnamed_c_compstr1789_join(BITJOIN,27582)@139
    assign i_unnamed_c_compstr1789_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1789_BitSelect_for_a_b};

    // i_unnamed_c_compstr1789_vt_select_0(BITSELECT,10487)@139
    assign i_unnamed_c_compstr1789_vt_select_0_b = i_unnamed_c_compstr1789_join_q[0:0];

    // redist194_i_unnamed_c_compstr1789_vt_select_0_b_1(DELAY,28422)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist194_i_unnamed_c_compstr1789_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1789_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1789_vt_join(BITJOIN,10486)@140
    assign i_unnamed_c_compstr1789_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist194_i_unnamed_c_compstr1789_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_63_c_compstr1790(ADD,6938)@140
    assign i_add_i_i_i_i_i126_i_63_c_compstr1790_a = {1'b0, i_unnamed_c_compstr1789_vt_join_q};
    assign i_add_i_i_i_i_i126_i_63_c_compstr1790_b = {1'b0, redist1193_i_conv_i_i_i_i97_i_63_c_compstr1786_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_63_c_compstr1790_o = $unsigned(i_add_i_i_i_i_i126_i_63_c_compstr1790_a) + $unsigned(i_add_i_i_i_i_i126_i_63_c_compstr1790_b);
    assign i_add_i_i_i_i_i126_i_63_c_compstr1790_q = i_add_i_i_i_i_i126_i_63_c_compstr1790_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_63_c_compstr1790_sel_x(BITSELECT,2132)@140
    assign bgTrunc_i_add_i_i_i_i_i126_i_63_c_compstr1790_sel_x_b = i_add_i_i_i_i_i126_i_63_c_compstr1790_q[15:0];

    // i_conv_i_i_i_i_i75_i277_64_c_compstr1810_sel_x(BITSELECT,3673)@140
    assign i_conv_i_i_i_i_i75_i277_64_c_compstr1810_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_63_c_compstr1790_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_64_c_compstr1810_vt_select_15(BITSELECT,7593)@140
    assign i_conv_i_i_i_i_i75_i277_64_c_compstr1810_vt_select_15_b = i_conv_i_i_i_i_i75_i277_64_c_compstr1810_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_64_c_compstr1810_vt_join(BITJOIN,7592)@140
    assign i_conv_i_i_i_i_i75_i277_64_c_compstr1810_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_64_c_compstr1810_vt_select_15_b};

    // leftShiftStage0_uid24440_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x(MUX,24439)@140
    assign leftShiftStage0_uid24440_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24440_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_64_c_compstr1810_vt_join_q or leftShiftStage0Idx1_uid24438_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24440_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24440_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_64_c_compstr1810_vt_join_q;
            1'b1 : leftShiftStage0_uid24440_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24438_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24440_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24445_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x(MUX,24444)@140
    assign leftShiftStage1_uid24445_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24445_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_s or leftShiftStage0_uid24440_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24443_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24445_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24445_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q = leftShiftStage0_uid24440_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24445_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24443_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24445_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24450_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x(MUX,24449)@140
    assign leftShiftStage2_uid24450_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24450_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_s or leftShiftStage1_uid24445_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24448_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24450_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24450_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q = leftShiftStage1_uid24445_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24450_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24448_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24450_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_64_c_compstr1811_vt_select_28(BITSELECT,9304)@140
    assign i_shl_i_i_i_i_i77_i_64_c_compstr1811_vt_select_28_b = leftShiftStage2_uid24450_i_shl_i_i_i_i_i77_i_64_c_compstr0_shift_x_q[28:13];

    // redist422_i_shl_i_i_i_i_i77_i_64_c_compstr1811_vt_select_28_b_1(DELAY,28650)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist422_i_shl_i_i_i_i_i77_i_64_c_compstr1811_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_64_c_compstr1811_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_64_c_compstr1811_vt_join(BITJOIN,9303)@141
    assign i_shl_i_i_i_i_i77_i_64_c_compstr1811_vt_join_q = {redist422_i_shl_i_i_i_i_i77_i_64_c_compstr1811_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma(CHAINMULTADD,28186)@135 + 5
    // out q@141
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ah[0] <= redist899_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_129_tpl_127_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ah[1] <= redist898_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_128_tpl_127_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ch[0] <= redist645_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_129_tpl_127_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ch[1] <= redist644_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_128_tpl_127_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812(ADD,8482)@141
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compstr1807_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compstr1809_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compstr1808_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_64_c_compstr1811_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_64_c_compstr1811_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_o[33:0];

    // rightShiftStage0_uid18906_dupName_255_i_unnamed_c_compstr0_shift_x(MUX,18905)@141
    assign rightShiftStage0_uid18906_dupName_255_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18906_dupName_255_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_q or rightShiftStage0Idx1_uid18904_dupName_255_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18906_dupName_255_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18906_dupName_255_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_q;
            1'b1 : rightShiftStage0_uid18906_dupName_255_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18904_dupName_255_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18906_dupName_255_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18911_dupName_255_i_unnamed_c_compstr0_shift_x(MUX,18910)@141
    assign rightShiftStage1_uid18911_dupName_255_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18911_dupName_255_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18906_dupName_255_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18909_dupName_255_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18911_dupName_255_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18911_dupName_255_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18906_dupName_255_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18911_dupName_255_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18909_dupName_255_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18911_dupName_255_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18916_dupName_255_i_unnamed_c_compstr0_shift_x(MUX,18915)@141
    assign rightShiftStage2_uid18916_dupName_255_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18916_dupName_255_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18911_dupName_255_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18914_dupName_255_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18916_dupName_255_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18916_dupName_255_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18911_dupName_255_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18916_dupName_255_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18914_dupName_255_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18916_dupName_255_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1813_vt_select_20(BITSELECT,10506)@141
    assign i_unnamed_c_compstr1813_vt_select_20_b = rightShiftStage2_uid18916_dupName_255_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1813_vt_join(BITJOIN,10505)@141
    assign i_unnamed_c_compstr1813_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1813_vt_select_20_b};

    // i_conv_i_i_i_i97_i_64_c_compstr1814_sel_x(BITSELECT,3544)@141
    assign i_conv_i_i_i_i97_i_64_c_compstr1814_sel_x_b = i_unnamed_c_compstr1813_vt_join_q[15:0];

    // redist1192_i_conv_i_i_i_i97_i_64_c_compstr1814_sel_x_b_1(DELAY,29420)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1192_i_conv_i_i_i_i97_i_64_c_compstr1814_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_64_c_compstr1814_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18925_dupName_256_i_unnamed_c_compstr0_shift_x(BITSELECT,18924)@141
    assign rightShiftStage1Idx1Rng8_uid18925_dupName_256_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18924_dupName_256_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18927_dupName_256_i_unnamed_c_compstr0_shift_x(BITJOIN,18926)@141
    assign rightShiftStage1Idx1_uid18927_dupName_256_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18925_dupName_256_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18920_dupName_256_i_unnamed_c_compstr0_shift_x(BITSELECT,18919)@141
    assign rightShiftStage0Idx1Rng4_uid18920_dupName_256_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_q[33:4];

    // rightShiftStage0Idx1_uid18922_dupName_256_i_unnamed_c_compstr0_shift_x(BITJOIN,18921)@141
    assign rightShiftStage0Idx1_uid18922_dupName_256_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18920_dupName_256_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18924_dupName_256_i_unnamed_c_compstr0_shift_x(MUX,18923)@141
    assign rightShiftStage0_uid18924_dupName_256_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18924_dupName_256_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_q or rightShiftStage0Idx1_uid18922_dupName_256_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18924_dupName_256_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18924_dupName_256_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compstr1812_q;
            1'b1 : rightShiftStage0_uid18924_dupName_256_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18922_dupName_256_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18924_dupName_256_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18929_dupName_256_i_unnamed_c_compstr0_shift_x(MUX,18928)@141
    assign rightShiftStage1_uid18929_dupName_256_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18929_dupName_256_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18924_dupName_256_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18927_dupName_256_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18929_dupName_256_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18929_dupName_256_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18924_dupName_256_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18929_dupName_256_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18927_dupName_256_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18929_dupName_256_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1815_vt_select_21(BITSELECT,10509)@141
    assign i_unnamed_c_compstr1815_vt_select_21_b = rightShiftStage1_uid18929_dupName_256_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1815_vt_join(BITJOIN,10508)@141
    assign i_unnamed_c_compstr1815_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1815_vt_select_21_b};

    // i_unnamed_c_compstr1816_sel_x(BITSELECT,6099)@141
    assign i_unnamed_c_compstr1816_sel_x_b = i_unnamed_c_compstr1815_vt_join_q[15:0];

    // i_unnamed_c_compstr1817_BitSelect_for_a(BITSELECT,27587)@141
    assign i_unnamed_c_compstr1817_BitSelect_for_a_b = i_unnamed_c_compstr1816_sel_x_b[0:0];

    // i_unnamed_c_compstr1817_join(BITJOIN,27588)@141
    assign i_unnamed_c_compstr1817_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1817_BitSelect_for_a_b};

    // i_unnamed_c_compstr1817_vt_select_0(BITSELECT,10514)@141
    assign i_unnamed_c_compstr1817_vt_select_0_b = i_unnamed_c_compstr1817_join_q[0:0];

    // redist192_i_unnamed_c_compstr1817_vt_select_0_b_1(DELAY,28420)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist192_i_unnamed_c_compstr1817_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1817_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1817_vt_join(BITJOIN,10513)@142
    assign i_unnamed_c_compstr1817_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist192_i_unnamed_c_compstr1817_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_64_c_compstr1818(ADD,6939)@142
    assign i_add_i_i_i_i_i126_i_64_c_compstr1818_a = {1'b0, i_unnamed_c_compstr1817_vt_join_q};
    assign i_add_i_i_i_i_i126_i_64_c_compstr1818_b = {1'b0, redist1192_i_conv_i_i_i_i97_i_64_c_compstr1814_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_64_c_compstr1818_o = $unsigned(i_add_i_i_i_i_i126_i_64_c_compstr1818_a) + $unsigned(i_add_i_i_i_i_i126_i_64_c_compstr1818_b);
    assign i_add_i_i_i_i_i126_i_64_c_compstr1818_q = i_add_i_i_i_i_i126_i_64_c_compstr1818_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_64_c_compstr1818_sel_x(BITSELECT,2133)@142
    assign bgTrunc_i_add_i_i_i_i_i126_i_64_c_compstr1818_sel_x_b = i_add_i_i_i_i_i126_i_64_c_compstr1818_q[15:0];

    // i_conv_i_i_i_i_i75_i277_65_c_compstr1838_sel_x(BITSELECT,3674)@142
    assign i_conv_i_i_i_i_i75_i277_65_c_compstr1838_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_64_c_compstr1818_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_65_c_compstr1838_vt_select_15(BITSELECT,7597)@142
    assign i_conv_i_i_i_i_i75_i277_65_c_compstr1838_vt_select_15_b = i_conv_i_i_i_i_i75_i277_65_c_compstr1838_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_65_c_compstr1838_vt_join(BITJOIN,7596)@142
    assign i_conv_i_i_i_i_i75_i277_65_c_compstr1838_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_65_c_compstr1838_vt_select_15_b};

    // leftShiftStage0_uid24458_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x(MUX,24457)@142
    assign leftShiftStage0_uid24458_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24458_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_65_c_compstr1838_vt_join_q or leftShiftStage0Idx1_uid24456_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24458_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24458_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_65_c_compstr1838_vt_join_q;
            1'b1 : leftShiftStage0_uid24458_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24456_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24458_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24463_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x(MUX,24462)@142
    assign leftShiftStage1_uid24463_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24463_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_s or leftShiftStage0_uid24458_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24461_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24463_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24463_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q = leftShiftStage0_uid24458_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24463_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24461_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24463_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24468_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x(MUX,24467)@142
    assign leftShiftStage2_uid24468_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24468_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_s or leftShiftStage1_uid24463_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24466_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24468_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24468_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q = leftShiftStage1_uid24463_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24468_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24466_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24468_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_65_c_compstr1839_vt_select_28(BITSELECT,9307)@142
    assign i_shl_i_i_i_i_i77_i_65_c_compstr1839_vt_select_28_b = leftShiftStage2_uid24468_i_shl_i_i_i_i_i77_i_65_c_compstr0_shift_x_q[28:13];

    // redist421_i_shl_i_i_i_i_i77_i_65_c_compstr1839_vt_select_28_b_1(DELAY,28649)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist421_i_shl_i_i_i_i_i77_i_65_c_compstr1839_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_65_c_compstr1839_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_65_c_compstr1839_vt_join(BITJOIN,9306)@143
    assign i_shl_i_i_i_i_i77_i_65_c_compstr1839_vt_join_q = {redist421_i_shl_i_i_i_i_i77_i_65_c_compstr1839_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma(CHAINMULTADD,28187)@137 + 5
    // out q@143
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ah[0] <= redist901_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_131_tpl_129_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ah[1] <= redist900_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_130_tpl_129_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ch[0] <= redist647_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_131_tpl_129_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ch[1] <= redist646_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_130_tpl_129_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840(ADD,8483)@143
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compstr1835_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compstr1837_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compstr1836_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_65_c_compstr1839_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_65_c_compstr1839_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_o[33:0];

    // rightShiftStage0_uid18968_dupName_259_i_unnamed_c_compstr0_shift_x(MUX,18967)@143
    assign rightShiftStage0_uid18968_dupName_259_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18968_dupName_259_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_q or rightShiftStage0Idx1_uid18966_dupName_259_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18968_dupName_259_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18968_dupName_259_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_q;
            1'b1 : rightShiftStage0_uid18968_dupName_259_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18966_dupName_259_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18968_dupName_259_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18973_dupName_259_i_unnamed_c_compstr0_shift_x(MUX,18972)@143
    assign rightShiftStage1_uid18973_dupName_259_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18973_dupName_259_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18968_dupName_259_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18971_dupName_259_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18973_dupName_259_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18973_dupName_259_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18968_dupName_259_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18973_dupName_259_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18971_dupName_259_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18973_dupName_259_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18978_dupName_259_i_unnamed_c_compstr0_shift_x(MUX,18977)@143
    assign rightShiftStage2_uid18978_dupName_259_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18978_dupName_259_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid18973_dupName_259_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid18976_dupName_259_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18978_dupName_259_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid18978_dupName_259_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid18973_dupName_259_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid18978_dupName_259_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid18976_dupName_259_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid18978_dupName_259_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1841_vt_select_20(BITSELECT,10531)@143
    assign i_unnamed_c_compstr1841_vt_select_20_b = rightShiftStage2_uid18978_dupName_259_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1841_vt_join(BITJOIN,10530)@143
    assign i_unnamed_c_compstr1841_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1841_vt_select_20_b};

    // i_conv_i_i_i_i97_i_65_c_compstr1842_sel_x(BITSELECT,3545)@143
    assign i_conv_i_i_i_i97_i_65_c_compstr1842_sel_x_b = i_unnamed_c_compstr1841_vt_join_q[15:0];

    // redist1191_i_conv_i_i_i_i97_i_65_c_compstr1842_sel_x_b_1(DELAY,29419)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1191_i_conv_i_i_i_i97_i_65_c_compstr1842_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_65_c_compstr1842_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18987_dupName_260_i_unnamed_c_compstr0_shift_x(BITSELECT,18986)@143
    assign rightShiftStage1Idx1Rng8_uid18987_dupName_260_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid18986_dupName_260_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18989_dupName_260_i_unnamed_c_compstr0_shift_x(BITJOIN,18988)@143
    assign rightShiftStage1Idx1_uid18989_dupName_260_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid18987_dupName_260_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18982_dupName_260_i_unnamed_c_compstr0_shift_x(BITSELECT,18981)@143
    assign rightShiftStage0Idx1Rng4_uid18982_dupName_260_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_q[33:4];

    // rightShiftStage0Idx1_uid18984_dupName_260_i_unnamed_c_compstr0_shift_x(BITJOIN,18983)@143
    assign rightShiftStage0Idx1_uid18984_dupName_260_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid18982_dupName_260_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid18986_dupName_260_i_unnamed_c_compstr0_shift_x(MUX,18985)@143
    assign rightShiftStage0_uid18986_dupName_260_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18986_dupName_260_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_q or rightShiftStage0Idx1_uid18984_dupName_260_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18986_dupName_260_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid18986_dupName_260_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compstr1840_q;
            1'b1 : rightShiftStage0_uid18986_dupName_260_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid18984_dupName_260_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid18986_dupName_260_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18991_dupName_260_i_unnamed_c_compstr0_shift_x(MUX,18990)@143
    assign rightShiftStage1_uid18991_dupName_260_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18991_dupName_260_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid18986_dupName_260_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid18989_dupName_260_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18991_dupName_260_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid18991_dupName_260_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid18986_dupName_260_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid18991_dupName_260_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid18989_dupName_260_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid18991_dupName_260_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1843_vt_select_21(BITSELECT,10534)@143
    assign i_unnamed_c_compstr1843_vt_select_21_b = rightShiftStage1_uid18991_dupName_260_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1843_vt_join(BITJOIN,10533)@143
    assign i_unnamed_c_compstr1843_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1843_vt_select_21_b};

    // i_unnamed_c_compstr1844_sel_x(BITSELECT,6101)@143
    assign i_unnamed_c_compstr1844_sel_x_b = i_unnamed_c_compstr1843_vt_join_q[15:0];

    // i_unnamed_c_compstr1845_BitSelect_for_a(BITSELECT,27591)@143
    assign i_unnamed_c_compstr1845_BitSelect_for_a_b = i_unnamed_c_compstr1844_sel_x_b[0:0];

    // i_unnamed_c_compstr1845_join(BITJOIN,27592)@143
    assign i_unnamed_c_compstr1845_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1845_BitSelect_for_a_b};

    // i_unnamed_c_compstr1845_vt_select_0(BITSELECT,10539)@143
    assign i_unnamed_c_compstr1845_vt_select_0_b = i_unnamed_c_compstr1845_join_q[0:0];

    // redist189_i_unnamed_c_compstr1845_vt_select_0_b_1(DELAY,28417)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist189_i_unnamed_c_compstr1845_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1845_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1845_vt_join(BITJOIN,10538)@144
    assign i_unnamed_c_compstr1845_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist189_i_unnamed_c_compstr1845_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_65_c_compstr1846(ADD,6940)@144
    assign i_add_i_i_i_i_i126_i_65_c_compstr1846_a = {1'b0, i_unnamed_c_compstr1845_vt_join_q};
    assign i_add_i_i_i_i_i126_i_65_c_compstr1846_b = {1'b0, redist1191_i_conv_i_i_i_i97_i_65_c_compstr1842_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_65_c_compstr1846_o = $unsigned(i_add_i_i_i_i_i126_i_65_c_compstr1846_a) + $unsigned(i_add_i_i_i_i_i126_i_65_c_compstr1846_b);
    assign i_add_i_i_i_i_i126_i_65_c_compstr1846_q = i_add_i_i_i_i_i126_i_65_c_compstr1846_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_65_c_compstr1846_sel_x(BITSELECT,2134)@144
    assign bgTrunc_i_add_i_i_i_i_i126_i_65_c_compstr1846_sel_x_b = i_add_i_i_i_i_i126_i_65_c_compstr1846_q[15:0];

    // i_conv_i_i_i_i_i75_i277_66_c_compstr1866_sel_x(BITSELECT,3675)@144
    assign i_conv_i_i_i_i_i75_i277_66_c_compstr1866_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_65_c_compstr1846_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_66_c_compstr1866_vt_select_15(BITSELECT,7601)@144
    assign i_conv_i_i_i_i_i75_i277_66_c_compstr1866_vt_select_15_b = i_conv_i_i_i_i_i75_i277_66_c_compstr1866_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_66_c_compstr1866_vt_join(BITJOIN,7600)@144
    assign i_conv_i_i_i_i_i75_i277_66_c_compstr1866_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_66_c_compstr1866_vt_select_15_b};

    // leftShiftStage0_uid24476_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x(MUX,24475)@144
    assign leftShiftStage0_uid24476_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24476_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_66_c_compstr1866_vt_join_q or leftShiftStage0Idx1_uid24474_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24476_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24476_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_66_c_compstr1866_vt_join_q;
            1'b1 : leftShiftStage0_uid24476_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24474_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24476_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24481_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x(MUX,24480)@144
    assign leftShiftStage1_uid24481_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24481_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_s or leftShiftStage0_uid24476_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24479_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24481_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24481_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q = leftShiftStage0_uid24476_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24481_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24479_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24481_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24486_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x(MUX,24485)@144
    assign leftShiftStage2_uid24486_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24486_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_s or leftShiftStage1_uid24481_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24484_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24486_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24486_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q = leftShiftStage1_uid24481_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24486_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24484_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24486_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_66_c_compstr1867_vt_select_28(BITSELECT,9310)@144
    assign i_shl_i_i_i_i_i77_i_66_c_compstr1867_vt_select_28_b = leftShiftStage2_uid24486_i_shl_i_i_i_i_i77_i_66_c_compstr0_shift_x_q[28:13];

    // redist420_i_shl_i_i_i_i_i77_i_66_c_compstr1867_vt_select_28_b_1(DELAY,28648)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist420_i_shl_i_i_i_i_i77_i_66_c_compstr1867_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_66_c_compstr1867_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_66_c_compstr1867_vt_join(BITJOIN,9309)@145
    assign i_shl_i_i_i_i_i77_i_66_c_compstr1867_vt_join_q = {redist420_i_shl_i_i_i_i_i77_i_66_c_compstr1867_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma(CHAINMULTADD,28188)@139 + 5
    // out q@145
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ah[0] <= redist903_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_133_tpl_131_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ah[1] <= redist902_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_132_tpl_131_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ch[0] <= redist649_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_133_tpl_131_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ch[1] <= redist648_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_132_tpl_131_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868(ADD,8484)@145
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compstr1863_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compstr1865_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compstr1864_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_66_c_compstr1867_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_66_c_compstr1867_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_o[33:0];

    // rightShiftStage0_uid19030_dupName_263_i_unnamed_c_compstr0_shift_x(MUX,19029)@145
    assign rightShiftStage0_uid19030_dupName_263_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19030_dupName_263_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_q or rightShiftStage0Idx1_uid19028_dupName_263_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19030_dupName_263_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19030_dupName_263_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_q;
            1'b1 : rightShiftStage0_uid19030_dupName_263_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19028_dupName_263_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19030_dupName_263_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19035_dupName_263_i_unnamed_c_compstr0_shift_x(MUX,19034)@145
    assign rightShiftStage1_uid19035_dupName_263_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19035_dupName_263_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19030_dupName_263_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19033_dupName_263_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19035_dupName_263_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19035_dupName_263_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19030_dupName_263_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19035_dupName_263_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19033_dupName_263_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19035_dupName_263_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19040_dupName_263_i_unnamed_c_compstr0_shift_x(MUX,19039)@145
    assign rightShiftStage2_uid19040_dupName_263_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19040_dupName_263_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19035_dupName_263_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19038_dupName_263_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19040_dupName_263_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19040_dupName_263_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19035_dupName_263_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19040_dupName_263_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19038_dupName_263_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19040_dupName_263_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1869_vt_select_20(BITSELECT,10553)@145
    assign i_unnamed_c_compstr1869_vt_select_20_b = rightShiftStage2_uid19040_dupName_263_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1869_vt_join(BITJOIN,10552)@145
    assign i_unnamed_c_compstr1869_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1869_vt_select_20_b};

    // i_conv_i_i_i_i97_i_66_c_compstr1870_sel_x(BITSELECT,3546)@145
    assign i_conv_i_i_i_i97_i_66_c_compstr1870_sel_x_b = i_unnamed_c_compstr1869_vt_join_q[15:0];

    // redist1190_i_conv_i_i_i_i97_i_66_c_compstr1870_sel_x_b_1(DELAY,29418)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1190_i_conv_i_i_i_i97_i_66_c_compstr1870_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_66_c_compstr1870_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19049_dupName_264_i_unnamed_c_compstr0_shift_x(BITSELECT,19048)@145
    assign rightShiftStage1Idx1Rng8_uid19049_dupName_264_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19048_dupName_264_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19051_dupName_264_i_unnamed_c_compstr0_shift_x(BITJOIN,19050)@145
    assign rightShiftStage1Idx1_uid19051_dupName_264_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19049_dupName_264_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19044_dupName_264_i_unnamed_c_compstr0_shift_x(BITSELECT,19043)@145
    assign rightShiftStage0Idx1Rng4_uid19044_dupName_264_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_q[33:4];

    // rightShiftStage0Idx1_uid19046_dupName_264_i_unnamed_c_compstr0_shift_x(BITJOIN,19045)@145
    assign rightShiftStage0Idx1_uid19046_dupName_264_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19044_dupName_264_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19048_dupName_264_i_unnamed_c_compstr0_shift_x(MUX,19047)@145
    assign rightShiftStage0_uid19048_dupName_264_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19048_dupName_264_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_q or rightShiftStage0Idx1_uid19046_dupName_264_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19048_dupName_264_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19048_dupName_264_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compstr1868_q;
            1'b1 : rightShiftStage0_uid19048_dupName_264_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19046_dupName_264_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19048_dupName_264_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19053_dupName_264_i_unnamed_c_compstr0_shift_x(MUX,19052)@145
    assign rightShiftStage1_uid19053_dupName_264_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19053_dupName_264_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19048_dupName_264_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19051_dupName_264_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19053_dupName_264_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19053_dupName_264_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19048_dupName_264_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19053_dupName_264_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19051_dupName_264_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19053_dupName_264_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1871_vt_select_21(BITSELECT,10556)@145
    assign i_unnamed_c_compstr1871_vt_select_21_b = rightShiftStage1_uid19053_dupName_264_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1871_vt_join(BITJOIN,10555)@145
    assign i_unnamed_c_compstr1871_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1871_vt_select_21_b};

    // i_unnamed_c_compstr1872_sel_x(BITSELECT,6103)@145
    assign i_unnamed_c_compstr1872_sel_x_b = i_unnamed_c_compstr1871_vt_join_q[15:0];

    // i_unnamed_c_compstr1873_BitSelect_for_a(BITSELECT,27595)@145
    assign i_unnamed_c_compstr1873_BitSelect_for_a_b = i_unnamed_c_compstr1872_sel_x_b[0:0];

    // i_unnamed_c_compstr1873_join(BITJOIN,27596)@145
    assign i_unnamed_c_compstr1873_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1873_BitSelect_for_a_b};

    // i_unnamed_c_compstr1873_vt_select_0(BITSELECT,10561)@145
    assign i_unnamed_c_compstr1873_vt_select_0_b = i_unnamed_c_compstr1873_join_q[0:0];

    // redist187_i_unnamed_c_compstr1873_vt_select_0_b_1(DELAY,28415)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist187_i_unnamed_c_compstr1873_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1873_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1873_vt_join(BITJOIN,10560)@146
    assign i_unnamed_c_compstr1873_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist187_i_unnamed_c_compstr1873_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_66_c_compstr1874(ADD,6941)@146
    assign i_add_i_i_i_i_i126_i_66_c_compstr1874_a = {1'b0, i_unnamed_c_compstr1873_vt_join_q};
    assign i_add_i_i_i_i_i126_i_66_c_compstr1874_b = {1'b0, redist1190_i_conv_i_i_i_i97_i_66_c_compstr1870_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_66_c_compstr1874_o = $unsigned(i_add_i_i_i_i_i126_i_66_c_compstr1874_a) + $unsigned(i_add_i_i_i_i_i126_i_66_c_compstr1874_b);
    assign i_add_i_i_i_i_i126_i_66_c_compstr1874_q = i_add_i_i_i_i_i126_i_66_c_compstr1874_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_66_c_compstr1874_sel_x(BITSELECT,2135)@146
    assign bgTrunc_i_add_i_i_i_i_i126_i_66_c_compstr1874_sel_x_b = i_add_i_i_i_i_i126_i_66_c_compstr1874_q[15:0];

    // i_conv_i_i_i_i_i75_i277_67_c_compstr1894_sel_x(BITSELECT,3676)@146
    assign i_conv_i_i_i_i_i75_i277_67_c_compstr1894_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_66_c_compstr1874_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_67_c_compstr1894_vt_select_15(BITSELECT,7605)@146
    assign i_conv_i_i_i_i_i75_i277_67_c_compstr1894_vt_select_15_b = i_conv_i_i_i_i_i75_i277_67_c_compstr1894_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_67_c_compstr1894_vt_join(BITJOIN,7604)@146
    assign i_conv_i_i_i_i_i75_i277_67_c_compstr1894_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_67_c_compstr1894_vt_select_15_b};

    // leftShiftStage0_uid24494_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x(MUX,24493)@146
    assign leftShiftStage0_uid24494_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24494_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_67_c_compstr1894_vt_join_q or leftShiftStage0Idx1_uid24492_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24494_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24494_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_67_c_compstr1894_vt_join_q;
            1'b1 : leftShiftStage0_uid24494_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24492_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24494_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24499_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x(MUX,24498)@146
    assign leftShiftStage1_uid24499_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24499_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_s or leftShiftStage0_uid24494_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24497_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24499_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24499_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q = leftShiftStage0_uid24494_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24499_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24497_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24499_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24504_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x(MUX,24503)@146
    assign leftShiftStage2_uid24504_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24504_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_s or leftShiftStage1_uid24499_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24502_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24504_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24504_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q = leftShiftStage1_uid24499_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24504_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24502_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24504_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_67_c_compstr1895_vt_select_28(BITSELECT,9313)@146
    assign i_shl_i_i_i_i_i77_i_67_c_compstr1895_vt_select_28_b = leftShiftStage2_uid24504_i_shl_i_i_i_i_i77_i_67_c_compstr0_shift_x_q[28:13];

    // redist419_i_shl_i_i_i_i_i77_i_67_c_compstr1895_vt_select_28_b_1(DELAY,28647)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist419_i_shl_i_i_i_i_i77_i_67_c_compstr1895_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_67_c_compstr1895_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_67_c_compstr1895_vt_join(BITJOIN,9312)@147
    assign i_shl_i_i_i_i_i77_i_67_c_compstr1895_vt_join_q = {redist419_i_shl_i_i_i_i_i77_i_67_c_compstr1895_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma(CHAINMULTADD,28189)@141 + 5
    // out q@147
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ah[0] <= redist905_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_135_tpl_133_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ah[1] <= redist904_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_134_tpl_133_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ch[0] <= redist651_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_135_tpl_133_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ch[1] <= redist650_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_134_tpl_133_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896(ADD,8485)@147
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compstr1891_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compstr1893_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compstr1892_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_67_c_compstr1895_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_67_c_compstr1895_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_o[33:0];

    // rightShiftStage0_uid19092_dupName_267_i_unnamed_c_compstr0_shift_x(MUX,19091)@147
    assign rightShiftStage0_uid19092_dupName_267_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19092_dupName_267_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_q or rightShiftStage0Idx1_uid19090_dupName_267_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19092_dupName_267_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19092_dupName_267_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_q;
            1'b1 : rightShiftStage0_uid19092_dupName_267_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19090_dupName_267_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19092_dupName_267_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19097_dupName_267_i_unnamed_c_compstr0_shift_x(MUX,19096)@147
    assign rightShiftStage1_uid19097_dupName_267_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19097_dupName_267_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19092_dupName_267_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19095_dupName_267_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19097_dupName_267_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19097_dupName_267_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19092_dupName_267_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19097_dupName_267_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19095_dupName_267_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19097_dupName_267_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19102_dupName_267_i_unnamed_c_compstr0_shift_x(MUX,19101)@147
    assign rightShiftStage2_uid19102_dupName_267_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19102_dupName_267_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19097_dupName_267_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19100_dupName_267_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19102_dupName_267_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19102_dupName_267_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19097_dupName_267_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19102_dupName_267_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19100_dupName_267_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19102_dupName_267_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1897_vt_select_20(BITSELECT,10575)@147
    assign i_unnamed_c_compstr1897_vt_select_20_b = rightShiftStage2_uid19102_dupName_267_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1897_vt_join(BITJOIN,10574)@147
    assign i_unnamed_c_compstr1897_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1897_vt_select_20_b};

    // i_conv_i_i_i_i97_i_67_c_compstr1898_sel_x(BITSELECT,3547)@147
    assign i_conv_i_i_i_i97_i_67_c_compstr1898_sel_x_b = i_unnamed_c_compstr1897_vt_join_q[15:0];

    // redist1189_i_conv_i_i_i_i97_i_67_c_compstr1898_sel_x_b_1(DELAY,29417)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1189_i_conv_i_i_i_i97_i_67_c_compstr1898_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_67_c_compstr1898_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19111_dupName_268_i_unnamed_c_compstr0_shift_x(BITSELECT,19110)@147
    assign rightShiftStage1Idx1Rng8_uid19111_dupName_268_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19110_dupName_268_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19113_dupName_268_i_unnamed_c_compstr0_shift_x(BITJOIN,19112)@147
    assign rightShiftStage1Idx1_uid19113_dupName_268_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19111_dupName_268_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19106_dupName_268_i_unnamed_c_compstr0_shift_x(BITSELECT,19105)@147
    assign rightShiftStage0Idx1Rng4_uid19106_dupName_268_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_q[33:4];

    // rightShiftStage0Idx1_uid19108_dupName_268_i_unnamed_c_compstr0_shift_x(BITJOIN,19107)@147
    assign rightShiftStage0Idx1_uid19108_dupName_268_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19106_dupName_268_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19110_dupName_268_i_unnamed_c_compstr0_shift_x(MUX,19109)@147
    assign rightShiftStage0_uid19110_dupName_268_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19110_dupName_268_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_q or rightShiftStage0Idx1_uid19108_dupName_268_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19110_dupName_268_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19110_dupName_268_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compstr1896_q;
            1'b1 : rightShiftStage0_uid19110_dupName_268_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19108_dupName_268_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19110_dupName_268_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19115_dupName_268_i_unnamed_c_compstr0_shift_x(MUX,19114)@147
    assign rightShiftStage1_uid19115_dupName_268_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19115_dupName_268_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19110_dupName_268_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19113_dupName_268_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19115_dupName_268_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19115_dupName_268_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19110_dupName_268_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19115_dupName_268_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19113_dupName_268_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19115_dupName_268_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1899_vt_select_21(BITSELECT,10578)@147
    assign i_unnamed_c_compstr1899_vt_select_21_b = rightShiftStage1_uid19115_dupName_268_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1899_vt_join(BITJOIN,10577)@147
    assign i_unnamed_c_compstr1899_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1899_vt_select_21_b};

    // i_unnamed_c_compstr1900_sel_x(BITSELECT,6105)@147
    assign i_unnamed_c_compstr1900_sel_x_b = i_unnamed_c_compstr1899_vt_join_q[15:0];

    // i_unnamed_c_compstr1901_BitSelect_for_a(BITSELECT,27599)@147
    assign i_unnamed_c_compstr1901_BitSelect_for_a_b = i_unnamed_c_compstr1900_sel_x_b[0:0];

    // i_unnamed_c_compstr1901_join(BITJOIN,27600)@147
    assign i_unnamed_c_compstr1901_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1901_BitSelect_for_a_b};

    // i_unnamed_c_compstr1901_vt_select_0(BITSELECT,10586)@147
    assign i_unnamed_c_compstr1901_vt_select_0_b = i_unnamed_c_compstr1901_join_q[0:0];

    // redist185_i_unnamed_c_compstr1901_vt_select_0_b_1(DELAY,28413)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist185_i_unnamed_c_compstr1901_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1901_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1901_vt_join(BITJOIN,10585)@148
    assign i_unnamed_c_compstr1901_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist185_i_unnamed_c_compstr1901_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_67_c_compstr1902(ADD,6942)@148
    assign i_add_i_i_i_i_i126_i_67_c_compstr1902_a = {1'b0, i_unnamed_c_compstr1901_vt_join_q};
    assign i_add_i_i_i_i_i126_i_67_c_compstr1902_b = {1'b0, redist1189_i_conv_i_i_i_i97_i_67_c_compstr1898_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_67_c_compstr1902_o = $unsigned(i_add_i_i_i_i_i126_i_67_c_compstr1902_a) + $unsigned(i_add_i_i_i_i_i126_i_67_c_compstr1902_b);
    assign i_add_i_i_i_i_i126_i_67_c_compstr1902_q = i_add_i_i_i_i_i126_i_67_c_compstr1902_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_67_c_compstr1902_sel_x(BITSELECT,2136)@148
    assign bgTrunc_i_add_i_i_i_i_i126_i_67_c_compstr1902_sel_x_b = i_add_i_i_i_i_i126_i_67_c_compstr1902_q[15:0];

    // i_conv_i_i_i_i_i75_i277_68_c_compstr1922_sel_x(BITSELECT,3677)@148
    assign i_conv_i_i_i_i_i75_i277_68_c_compstr1922_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_67_c_compstr1902_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_68_c_compstr1922_vt_select_15(BITSELECT,7609)@148
    assign i_conv_i_i_i_i_i75_i277_68_c_compstr1922_vt_select_15_b = i_conv_i_i_i_i_i75_i277_68_c_compstr1922_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_68_c_compstr1922_vt_join(BITJOIN,7608)@148
    assign i_conv_i_i_i_i_i75_i277_68_c_compstr1922_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_68_c_compstr1922_vt_select_15_b};

    // leftShiftStage0_uid24512_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x(MUX,24511)@148
    assign leftShiftStage0_uid24512_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24512_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_68_c_compstr1922_vt_join_q or leftShiftStage0Idx1_uid24510_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24512_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24512_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_68_c_compstr1922_vt_join_q;
            1'b1 : leftShiftStage0_uid24512_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24510_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24512_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24517_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x(MUX,24516)@148
    assign leftShiftStage1_uid24517_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24517_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_s or leftShiftStage0_uid24512_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24515_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24517_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24517_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q = leftShiftStage0_uid24512_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24517_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24515_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24517_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24522_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x(MUX,24521)@148
    assign leftShiftStage2_uid24522_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24522_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_s or leftShiftStage1_uid24517_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24520_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24522_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24522_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q = leftShiftStage1_uid24517_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24522_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24520_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24522_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_68_c_compstr1923_vt_select_28(BITSELECT,9316)@148
    assign i_shl_i_i_i_i_i77_i_68_c_compstr1923_vt_select_28_b = leftShiftStage2_uid24522_i_shl_i_i_i_i_i77_i_68_c_compstr0_shift_x_q[28:13];

    // redist418_i_shl_i_i_i_i_i77_i_68_c_compstr1923_vt_select_28_b_1(DELAY,28646)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist418_i_shl_i_i_i_i_i77_i_68_c_compstr1923_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_68_c_compstr1923_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_68_c_compstr1923_vt_join(BITJOIN,9315)@149
    assign i_shl_i_i_i_i_i77_i_68_c_compstr1923_vt_join_q = {redist418_i_shl_i_i_i_i_i77_i_68_c_compstr1923_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma(CHAINMULTADD,28190)@143 + 5
    // out q@149
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ah[0] <= redist907_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_137_tpl_135_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ah[1] <= redist906_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_136_tpl_135_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ch[0] <= redist653_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_137_tpl_135_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ch[1] <= redist652_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_136_tpl_135_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924(ADD,8486)@149
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compstr1919_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compstr1921_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compstr1920_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_68_c_compstr1923_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_68_c_compstr1923_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_o[33:0];

    // rightShiftStage0_uid19154_dupName_271_i_unnamed_c_compstr0_shift_x(MUX,19153)@149
    assign rightShiftStage0_uid19154_dupName_271_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19154_dupName_271_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_q or rightShiftStage0Idx1_uid19152_dupName_271_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19154_dupName_271_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19154_dupName_271_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_q;
            1'b1 : rightShiftStage0_uid19154_dupName_271_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19152_dupName_271_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19154_dupName_271_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19159_dupName_271_i_unnamed_c_compstr0_shift_x(MUX,19158)@149
    assign rightShiftStage1_uid19159_dupName_271_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19159_dupName_271_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19154_dupName_271_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19157_dupName_271_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19159_dupName_271_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19159_dupName_271_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19154_dupName_271_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19159_dupName_271_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19157_dupName_271_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19159_dupName_271_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19164_dupName_271_i_unnamed_c_compstr0_shift_x(MUX,19163)@149
    assign rightShiftStage2_uid19164_dupName_271_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19164_dupName_271_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19159_dupName_271_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19162_dupName_271_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19164_dupName_271_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19164_dupName_271_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19159_dupName_271_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19164_dupName_271_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19162_dupName_271_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19164_dupName_271_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1925_vt_select_20(BITSELECT,10603)@149
    assign i_unnamed_c_compstr1925_vt_select_20_b = rightShiftStage2_uid19164_dupName_271_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1925_vt_join(BITJOIN,10602)@149
    assign i_unnamed_c_compstr1925_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1925_vt_select_20_b};

    // i_conv_i_i_i_i97_i_68_c_compstr1926_sel_x(BITSELECT,3548)@149
    assign i_conv_i_i_i_i97_i_68_c_compstr1926_sel_x_b = i_unnamed_c_compstr1925_vt_join_q[15:0];

    // redist1188_i_conv_i_i_i_i97_i_68_c_compstr1926_sel_x_b_1(DELAY,29416)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1188_i_conv_i_i_i_i97_i_68_c_compstr1926_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_68_c_compstr1926_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19173_dupName_272_i_unnamed_c_compstr0_shift_x(BITSELECT,19172)@149
    assign rightShiftStage1Idx1Rng8_uid19173_dupName_272_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19172_dupName_272_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19175_dupName_272_i_unnamed_c_compstr0_shift_x(BITJOIN,19174)@149
    assign rightShiftStage1Idx1_uid19175_dupName_272_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19173_dupName_272_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19168_dupName_272_i_unnamed_c_compstr0_shift_x(BITSELECT,19167)@149
    assign rightShiftStage0Idx1Rng4_uid19168_dupName_272_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_q[33:4];

    // rightShiftStage0Idx1_uid19170_dupName_272_i_unnamed_c_compstr0_shift_x(BITJOIN,19169)@149
    assign rightShiftStage0Idx1_uid19170_dupName_272_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19168_dupName_272_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19172_dupName_272_i_unnamed_c_compstr0_shift_x(MUX,19171)@149
    assign rightShiftStage0_uid19172_dupName_272_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19172_dupName_272_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_q or rightShiftStage0Idx1_uid19170_dupName_272_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19172_dupName_272_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19172_dupName_272_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compstr1924_q;
            1'b1 : rightShiftStage0_uid19172_dupName_272_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19170_dupName_272_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19172_dupName_272_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19177_dupName_272_i_unnamed_c_compstr0_shift_x(MUX,19176)@149
    assign rightShiftStage1_uid19177_dupName_272_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19177_dupName_272_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19172_dupName_272_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19175_dupName_272_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19177_dupName_272_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19177_dupName_272_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19172_dupName_272_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19177_dupName_272_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19175_dupName_272_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19177_dupName_272_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1927_vt_select_21(BITSELECT,10606)@149
    assign i_unnamed_c_compstr1927_vt_select_21_b = rightShiftStage1_uid19177_dupName_272_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1927_vt_join(BITJOIN,10605)@149
    assign i_unnamed_c_compstr1927_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1927_vt_select_21_b};

    // i_unnamed_c_compstr1928_sel_x(BITSELECT,6108)@149
    assign i_unnamed_c_compstr1928_sel_x_b = i_unnamed_c_compstr1927_vt_join_q[15:0];

    // i_unnamed_c_compstr1929_BitSelect_for_a(BITSELECT,27603)@149
    assign i_unnamed_c_compstr1929_BitSelect_for_a_b = i_unnamed_c_compstr1928_sel_x_b[0:0];

    // i_unnamed_c_compstr1929_join(BITJOIN,27604)@149
    assign i_unnamed_c_compstr1929_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1929_BitSelect_for_a_b};

    // i_unnamed_c_compstr1929_vt_select_0(BITSELECT,10611)@149
    assign i_unnamed_c_compstr1929_vt_select_0_b = i_unnamed_c_compstr1929_join_q[0:0];

    // redist183_i_unnamed_c_compstr1929_vt_select_0_b_1(DELAY,28411)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist183_i_unnamed_c_compstr1929_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1929_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1929_vt_join(BITJOIN,10610)@150
    assign i_unnamed_c_compstr1929_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist183_i_unnamed_c_compstr1929_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_68_c_compstr1930(ADD,6943)@150
    assign i_add_i_i_i_i_i126_i_68_c_compstr1930_a = {1'b0, i_unnamed_c_compstr1929_vt_join_q};
    assign i_add_i_i_i_i_i126_i_68_c_compstr1930_b = {1'b0, redist1188_i_conv_i_i_i_i97_i_68_c_compstr1926_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_68_c_compstr1930_o = $unsigned(i_add_i_i_i_i_i126_i_68_c_compstr1930_a) + $unsigned(i_add_i_i_i_i_i126_i_68_c_compstr1930_b);
    assign i_add_i_i_i_i_i126_i_68_c_compstr1930_q = i_add_i_i_i_i_i126_i_68_c_compstr1930_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_68_c_compstr1930_sel_x(BITSELECT,2137)@150
    assign bgTrunc_i_add_i_i_i_i_i126_i_68_c_compstr1930_sel_x_b = i_add_i_i_i_i_i126_i_68_c_compstr1930_q[15:0];

    // i_conv_i_i_i_i_i75_i277_69_c_compstr1950_sel_x(BITSELECT,3678)@150
    assign i_conv_i_i_i_i_i75_i277_69_c_compstr1950_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_68_c_compstr1930_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_69_c_compstr1950_vt_select_15(BITSELECT,7613)@150
    assign i_conv_i_i_i_i_i75_i277_69_c_compstr1950_vt_select_15_b = i_conv_i_i_i_i_i75_i277_69_c_compstr1950_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_69_c_compstr1950_vt_join(BITJOIN,7612)@150
    assign i_conv_i_i_i_i_i75_i277_69_c_compstr1950_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_69_c_compstr1950_vt_select_15_b};

    // leftShiftStage0_uid24530_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x(MUX,24529)@150
    assign leftShiftStage0_uid24530_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24530_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_69_c_compstr1950_vt_join_q or leftShiftStage0Idx1_uid24528_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24530_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24530_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_69_c_compstr1950_vt_join_q;
            1'b1 : leftShiftStage0_uid24530_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24528_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24530_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24535_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x(MUX,24534)@150
    assign leftShiftStage1_uid24535_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24535_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_s or leftShiftStage0_uid24530_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24533_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24535_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24535_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q = leftShiftStage0_uid24530_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24535_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24533_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24535_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24540_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x(MUX,24539)@150
    assign leftShiftStage2_uid24540_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24540_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_s or leftShiftStage1_uid24535_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24538_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24540_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24540_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q = leftShiftStage1_uid24535_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24540_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24538_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24540_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_69_c_compstr1951_vt_select_28(BITSELECT,9319)@150
    assign i_shl_i_i_i_i_i77_i_69_c_compstr1951_vt_select_28_b = leftShiftStage2_uid24540_i_shl_i_i_i_i_i77_i_69_c_compstr0_shift_x_q[28:13];

    // redist417_i_shl_i_i_i_i_i77_i_69_c_compstr1951_vt_select_28_b_1(DELAY,28645)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist417_i_shl_i_i_i_i_i77_i_69_c_compstr1951_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_69_c_compstr1951_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_69_c_compstr1951_vt_join(BITJOIN,9318)@151
    assign i_shl_i_i_i_i_i77_i_69_c_compstr1951_vt_join_q = {redist417_i_shl_i_i_i_i_i77_i_69_c_compstr1951_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma(CHAINMULTADD,28191)@145 + 5
    // out q@151
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ah[0] <= redist909_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_139_tpl_137_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ah[1] <= redist908_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_138_tpl_137_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ch[0] <= redist655_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_139_tpl_137_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ch[1] <= redist654_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_138_tpl_137_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952(ADD,8487)@151
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compstr1947_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compstr1949_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compstr1948_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_69_c_compstr1951_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_69_c_compstr1951_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_o[33:0];

    // rightShiftStage0_uid19216_dupName_275_i_unnamed_c_compstr0_shift_x(MUX,19215)@151
    assign rightShiftStage0_uid19216_dupName_275_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19216_dupName_275_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_q or rightShiftStage0Idx1_uid19214_dupName_275_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19216_dupName_275_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19216_dupName_275_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_q;
            1'b1 : rightShiftStage0_uid19216_dupName_275_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19214_dupName_275_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19216_dupName_275_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19221_dupName_275_i_unnamed_c_compstr0_shift_x(MUX,19220)@151
    assign rightShiftStage1_uid19221_dupName_275_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19221_dupName_275_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19216_dupName_275_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19219_dupName_275_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19221_dupName_275_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19221_dupName_275_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19216_dupName_275_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19221_dupName_275_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19219_dupName_275_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19221_dupName_275_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19226_dupName_275_i_unnamed_c_compstr0_shift_x(MUX,19225)@151
    assign rightShiftStage2_uid19226_dupName_275_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19226_dupName_275_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19221_dupName_275_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19224_dupName_275_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19226_dupName_275_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19226_dupName_275_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19221_dupName_275_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19226_dupName_275_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19224_dupName_275_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19226_dupName_275_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1953_vt_select_20(BITSELECT,10630)@151
    assign i_unnamed_c_compstr1953_vt_select_20_b = rightShiftStage2_uid19226_dupName_275_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1953_vt_join(BITJOIN,10629)@151
    assign i_unnamed_c_compstr1953_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1953_vt_select_20_b};

    // i_conv_i_i_i_i97_i_69_c_compstr1954_sel_x(BITSELECT,3549)@151
    assign i_conv_i_i_i_i97_i_69_c_compstr1954_sel_x_b = i_unnamed_c_compstr1953_vt_join_q[15:0];

    // redist1187_i_conv_i_i_i_i97_i_69_c_compstr1954_sel_x_b_1(DELAY,29415)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1187_i_conv_i_i_i_i97_i_69_c_compstr1954_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_69_c_compstr1954_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19235_dupName_276_i_unnamed_c_compstr0_shift_x(BITSELECT,19234)@151
    assign rightShiftStage1Idx1Rng8_uid19235_dupName_276_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19234_dupName_276_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19237_dupName_276_i_unnamed_c_compstr0_shift_x(BITJOIN,19236)@151
    assign rightShiftStage1Idx1_uid19237_dupName_276_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19235_dupName_276_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19230_dupName_276_i_unnamed_c_compstr0_shift_x(BITSELECT,19229)@151
    assign rightShiftStage0Idx1Rng4_uid19230_dupName_276_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_q[33:4];

    // rightShiftStage0Idx1_uid19232_dupName_276_i_unnamed_c_compstr0_shift_x(BITJOIN,19231)@151
    assign rightShiftStage0Idx1_uid19232_dupName_276_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19230_dupName_276_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19234_dupName_276_i_unnamed_c_compstr0_shift_x(MUX,19233)@151
    assign rightShiftStage0_uid19234_dupName_276_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19234_dupName_276_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_q or rightShiftStage0Idx1_uid19232_dupName_276_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19234_dupName_276_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19234_dupName_276_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compstr1952_q;
            1'b1 : rightShiftStage0_uid19234_dupName_276_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19232_dupName_276_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19234_dupName_276_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19239_dupName_276_i_unnamed_c_compstr0_shift_x(MUX,19238)@151
    assign rightShiftStage1_uid19239_dupName_276_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19239_dupName_276_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19234_dupName_276_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19237_dupName_276_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19239_dupName_276_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19239_dupName_276_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19234_dupName_276_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19239_dupName_276_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19237_dupName_276_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19239_dupName_276_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1955_vt_select_21(BITSELECT,10633)@151
    assign i_unnamed_c_compstr1955_vt_select_21_b = rightShiftStage1_uid19239_dupName_276_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1955_vt_join(BITJOIN,10632)@151
    assign i_unnamed_c_compstr1955_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1955_vt_select_21_b};

    // i_unnamed_c_compstr1956_sel_x(BITSELECT,6110)@151
    assign i_unnamed_c_compstr1956_sel_x_b = i_unnamed_c_compstr1955_vt_join_q[15:0];

    // i_unnamed_c_compstr1957_BitSelect_for_a(BITSELECT,27609)@151
    assign i_unnamed_c_compstr1957_BitSelect_for_a_b = i_unnamed_c_compstr1956_sel_x_b[0:0];

    // i_unnamed_c_compstr1957_join(BITJOIN,27610)@151
    assign i_unnamed_c_compstr1957_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1957_BitSelect_for_a_b};

    // i_unnamed_c_compstr1957_vt_select_0(BITSELECT,10638)@151
    assign i_unnamed_c_compstr1957_vt_select_0_b = i_unnamed_c_compstr1957_join_q[0:0];

    // redist180_i_unnamed_c_compstr1957_vt_select_0_b_1(DELAY,28408)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist180_i_unnamed_c_compstr1957_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1957_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1957_vt_join(BITJOIN,10637)@152
    assign i_unnamed_c_compstr1957_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist180_i_unnamed_c_compstr1957_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_69_c_compstr1958(ADD,6944)@152
    assign i_add_i_i_i_i_i126_i_69_c_compstr1958_a = {1'b0, i_unnamed_c_compstr1957_vt_join_q};
    assign i_add_i_i_i_i_i126_i_69_c_compstr1958_b = {1'b0, redist1187_i_conv_i_i_i_i97_i_69_c_compstr1954_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_69_c_compstr1958_o = $unsigned(i_add_i_i_i_i_i126_i_69_c_compstr1958_a) + $unsigned(i_add_i_i_i_i_i126_i_69_c_compstr1958_b);
    assign i_add_i_i_i_i_i126_i_69_c_compstr1958_q = i_add_i_i_i_i_i126_i_69_c_compstr1958_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_69_c_compstr1958_sel_x(BITSELECT,2138)@152
    assign bgTrunc_i_add_i_i_i_i_i126_i_69_c_compstr1958_sel_x_b = i_add_i_i_i_i_i126_i_69_c_compstr1958_q[15:0];

    // i_conv_i_i_i_i_i75_i277_70_c_compstr1978_sel_x(BITSELECT,3680)@152
    assign i_conv_i_i_i_i_i75_i277_70_c_compstr1978_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_69_c_compstr1958_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_70_c_compstr1978_vt_select_15(BITSELECT,7621)@152
    assign i_conv_i_i_i_i_i75_i277_70_c_compstr1978_vt_select_15_b = i_conv_i_i_i_i_i75_i277_70_c_compstr1978_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_70_c_compstr1978_vt_join(BITJOIN,7620)@152
    assign i_conv_i_i_i_i_i75_i277_70_c_compstr1978_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_70_c_compstr1978_vt_select_15_b};

    // leftShiftStage0_uid24566_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x(MUX,24565)@152
    assign leftShiftStage0_uid24566_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24566_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_70_c_compstr1978_vt_join_q or leftShiftStage0Idx1_uid24564_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24566_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24566_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_70_c_compstr1978_vt_join_q;
            1'b1 : leftShiftStage0_uid24566_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24564_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24566_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24571_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x(MUX,24570)@152
    assign leftShiftStage1_uid24571_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24571_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_s or leftShiftStage0_uid24566_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24569_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24571_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24571_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q = leftShiftStage0_uid24566_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24571_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24569_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24571_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24576_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x(MUX,24575)@152
    assign leftShiftStage2_uid24576_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24576_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_s or leftShiftStage1_uid24571_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24574_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24576_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24576_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q = leftShiftStage1_uid24571_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24576_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24574_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24576_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_70_c_compstr1979_vt_select_28(BITSELECT,9325)@152
    assign i_shl_i_i_i_i_i77_i_70_c_compstr1979_vt_select_28_b = leftShiftStage2_uid24576_i_shl_i_i_i_i_i77_i_70_c_compstr0_shift_x_q[28:13];

    // redist415_i_shl_i_i_i_i_i77_i_70_c_compstr1979_vt_select_28_b_1(DELAY,28643)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist415_i_shl_i_i_i_i_i77_i_70_c_compstr1979_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_70_c_compstr1979_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_70_c_compstr1979_vt_join(BITJOIN,9324)@153
    assign i_shl_i_i_i_i_i77_i_70_c_compstr1979_vt_join_q = {redist415_i_shl_i_i_i_i_i77_i_70_c_compstr1979_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma(CHAINMULTADD,28193)@147 + 5
    // out q@153
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ah[0] <= redist911_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_141_tpl_139_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ah[1] <= redist910_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_140_tpl_139_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ch[0] <= redist657_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_141_tpl_139_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ch[1] <= redist656_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_140_tpl_139_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980(ADD,8489)@153
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compstr1975_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compstr1977_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compstr1976_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_70_c_compstr1979_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_70_c_compstr1979_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_o[33:0];

    // rightShiftStage0_uid19278_dupName_279_i_unnamed_c_compstr0_shift_x(MUX,19277)@153
    assign rightShiftStage0_uid19278_dupName_279_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19278_dupName_279_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_q or rightShiftStage0Idx1_uid19276_dupName_279_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19278_dupName_279_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19278_dupName_279_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_q;
            1'b1 : rightShiftStage0_uid19278_dupName_279_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19276_dupName_279_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19278_dupName_279_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19283_dupName_279_i_unnamed_c_compstr0_shift_x(MUX,19282)@153
    assign rightShiftStage1_uid19283_dupName_279_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19283_dupName_279_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19278_dupName_279_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19281_dupName_279_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19283_dupName_279_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19283_dupName_279_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19278_dupName_279_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19283_dupName_279_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19281_dupName_279_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19283_dupName_279_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19288_dupName_279_i_unnamed_c_compstr0_shift_x(MUX,19287)@153
    assign rightShiftStage2_uid19288_dupName_279_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19288_dupName_279_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19283_dupName_279_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19286_dupName_279_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19288_dupName_279_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19288_dupName_279_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19283_dupName_279_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19288_dupName_279_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19286_dupName_279_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19288_dupName_279_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1981_vt_select_20(BITSELECT,10652)@153
    assign i_unnamed_c_compstr1981_vt_select_20_b = rightShiftStage2_uid19288_dupName_279_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr1981_vt_join(BITJOIN,10651)@153
    assign i_unnamed_c_compstr1981_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr1981_vt_select_20_b};

    // i_conv_i_i_i_i97_i_70_c_compstr1982_sel_x(BITSELECT,3551)@153
    assign i_conv_i_i_i_i97_i_70_c_compstr1982_sel_x_b = i_unnamed_c_compstr1981_vt_join_q[15:0];

    // redist1185_i_conv_i_i_i_i97_i_70_c_compstr1982_sel_x_b_1(DELAY,29413)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1185_i_conv_i_i_i_i97_i_70_c_compstr1982_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_70_c_compstr1982_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19297_dupName_280_i_unnamed_c_compstr0_shift_x(BITSELECT,19296)@153
    assign rightShiftStage1Idx1Rng8_uid19297_dupName_280_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19296_dupName_280_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19299_dupName_280_i_unnamed_c_compstr0_shift_x(BITJOIN,19298)@153
    assign rightShiftStage1Idx1_uid19299_dupName_280_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19297_dupName_280_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19292_dupName_280_i_unnamed_c_compstr0_shift_x(BITSELECT,19291)@153
    assign rightShiftStage0Idx1Rng4_uid19292_dupName_280_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_q[33:4];

    // rightShiftStage0Idx1_uid19294_dupName_280_i_unnamed_c_compstr0_shift_x(BITJOIN,19293)@153
    assign rightShiftStage0Idx1_uid19294_dupName_280_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19292_dupName_280_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19296_dupName_280_i_unnamed_c_compstr0_shift_x(MUX,19295)@153
    assign rightShiftStage0_uid19296_dupName_280_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19296_dupName_280_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_q or rightShiftStage0Idx1_uid19294_dupName_280_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19296_dupName_280_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19296_dupName_280_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compstr1980_q;
            1'b1 : rightShiftStage0_uid19296_dupName_280_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19294_dupName_280_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19296_dupName_280_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19301_dupName_280_i_unnamed_c_compstr0_shift_x(MUX,19300)@153
    assign rightShiftStage1_uid19301_dupName_280_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19301_dupName_280_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19296_dupName_280_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19299_dupName_280_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19301_dupName_280_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19301_dupName_280_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19296_dupName_280_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19301_dupName_280_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19299_dupName_280_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19301_dupName_280_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr1983_vt_select_21(BITSELECT,10655)@153
    assign i_unnamed_c_compstr1983_vt_select_21_b = rightShiftStage1_uid19301_dupName_280_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr1983_vt_join(BITJOIN,10654)@153
    assign i_unnamed_c_compstr1983_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr1983_vt_select_21_b};

    // i_unnamed_c_compstr1984_sel_x(BITSELECT,6112)@153
    assign i_unnamed_c_compstr1984_sel_x_b = i_unnamed_c_compstr1983_vt_join_q[15:0];

    // i_unnamed_c_compstr1985_BitSelect_for_a(BITSELECT,27613)@153
    assign i_unnamed_c_compstr1985_BitSelect_for_a_b = i_unnamed_c_compstr1984_sel_x_b[0:0];

    // i_unnamed_c_compstr1985_join(BITJOIN,27614)@153
    assign i_unnamed_c_compstr1985_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr1985_BitSelect_for_a_b};

    // i_unnamed_c_compstr1985_vt_select_0(BITSELECT,10660)@153
    assign i_unnamed_c_compstr1985_vt_select_0_b = i_unnamed_c_compstr1985_join_q[0:0];

    // redist178_i_unnamed_c_compstr1985_vt_select_0_b_1(DELAY,28406)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist178_i_unnamed_c_compstr1985_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr1985_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr1985_vt_join(BITJOIN,10659)@154
    assign i_unnamed_c_compstr1985_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist178_i_unnamed_c_compstr1985_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_70_c_compstr1986(ADD,6946)@154
    assign i_add_i_i_i_i_i126_i_70_c_compstr1986_a = {1'b0, i_unnamed_c_compstr1985_vt_join_q};
    assign i_add_i_i_i_i_i126_i_70_c_compstr1986_b = {1'b0, redist1185_i_conv_i_i_i_i97_i_70_c_compstr1982_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_70_c_compstr1986_o = $unsigned(i_add_i_i_i_i_i126_i_70_c_compstr1986_a) + $unsigned(i_add_i_i_i_i_i126_i_70_c_compstr1986_b);
    assign i_add_i_i_i_i_i126_i_70_c_compstr1986_q = i_add_i_i_i_i_i126_i_70_c_compstr1986_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_70_c_compstr1986_sel_x(BITSELECT,2140)@154
    assign bgTrunc_i_add_i_i_i_i_i126_i_70_c_compstr1986_sel_x_b = i_add_i_i_i_i_i126_i_70_c_compstr1986_q[15:0];

    // i_conv_i_i_i_i_i75_i277_71_c_compstr2006_sel_x(BITSELECT,3681)@154
    assign i_conv_i_i_i_i_i75_i277_71_c_compstr2006_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_70_c_compstr1986_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_71_c_compstr2006_vt_select_15(BITSELECT,7625)@154
    assign i_conv_i_i_i_i_i75_i277_71_c_compstr2006_vt_select_15_b = i_conv_i_i_i_i_i75_i277_71_c_compstr2006_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_71_c_compstr2006_vt_join(BITJOIN,7624)@154
    assign i_conv_i_i_i_i_i75_i277_71_c_compstr2006_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_71_c_compstr2006_vt_select_15_b};

    // leftShiftStage0_uid24584_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x(MUX,24583)@154
    assign leftShiftStage0_uid24584_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24584_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_71_c_compstr2006_vt_join_q or leftShiftStage0Idx1_uid24582_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24584_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24584_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_71_c_compstr2006_vt_join_q;
            1'b1 : leftShiftStage0_uid24584_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24582_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24584_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24589_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x(MUX,24588)@154
    assign leftShiftStage1_uid24589_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24589_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_s or leftShiftStage0_uid24584_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24587_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24589_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24589_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q = leftShiftStage0_uid24584_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24589_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24587_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24589_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24594_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x(MUX,24593)@154
    assign leftShiftStage2_uid24594_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24594_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_s or leftShiftStage1_uid24589_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24592_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24594_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24594_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q = leftShiftStage1_uid24589_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24594_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24592_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24594_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_71_c_compstr2007_vt_select_28(BITSELECT,9328)@154
    assign i_shl_i_i_i_i_i77_i_71_c_compstr2007_vt_select_28_b = leftShiftStage2_uid24594_i_shl_i_i_i_i_i77_i_71_c_compstr0_shift_x_q[28:13];

    // redist414_i_shl_i_i_i_i_i77_i_71_c_compstr2007_vt_select_28_b_1(DELAY,28642)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist414_i_shl_i_i_i_i_i77_i_71_c_compstr2007_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_71_c_compstr2007_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_71_c_compstr2007_vt_join(BITJOIN,9327)@155
    assign i_shl_i_i_i_i_i77_i_71_c_compstr2007_vt_join_q = {redist414_i_shl_i_i_i_i_i77_i_71_c_compstr2007_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma(CHAINMULTADD,28194)@149 + 5
    // out q@155
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ah[0] <= redist913_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_143_tpl_141_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ah[1] <= redist912_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_142_tpl_141_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ch[0] <= redist659_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_143_tpl_141_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ch[1] <= redist658_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_142_tpl_141_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008(ADD,8490)@155
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compstr2003_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compstr2005_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compstr2004_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_71_c_compstr2007_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_71_c_compstr2007_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_o[33:0];

    // rightShiftStage0_uid19340_dupName_283_i_unnamed_c_compstr0_shift_x(MUX,19339)@155
    assign rightShiftStage0_uid19340_dupName_283_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19340_dupName_283_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_q or rightShiftStage0Idx1_uid19338_dupName_283_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19340_dupName_283_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19340_dupName_283_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_q;
            1'b1 : rightShiftStage0_uid19340_dupName_283_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19338_dupName_283_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19340_dupName_283_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19345_dupName_283_i_unnamed_c_compstr0_shift_x(MUX,19344)@155
    assign rightShiftStage1_uid19345_dupName_283_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19345_dupName_283_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19340_dupName_283_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19343_dupName_283_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19345_dupName_283_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19345_dupName_283_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19340_dupName_283_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19345_dupName_283_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19343_dupName_283_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19345_dupName_283_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19350_dupName_283_i_unnamed_c_compstr0_shift_x(MUX,19349)@155
    assign rightShiftStage2_uid19350_dupName_283_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19350_dupName_283_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19345_dupName_283_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19348_dupName_283_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19350_dupName_283_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19350_dupName_283_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19345_dupName_283_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19350_dupName_283_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19348_dupName_283_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19350_dupName_283_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2009_vt_select_20(BITSELECT,10674)@155
    assign i_unnamed_c_compstr2009_vt_select_20_b = rightShiftStage2_uid19350_dupName_283_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2009_vt_join(BITJOIN,10673)@155
    assign i_unnamed_c_compstr2009_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2009_vt_select_20_b};

    // i_conv_i_i_i_i97_i_71_c_compstr2010_sel_x(BITSELECT,3552)@155
    assign i_conv_i_i_i_i97_i_71_c_compstr2010_sel_x_b = i_unnamed_c_compstr2009_vt_join_q[15:0];

    // redist1184_i_conv_i_i_i_i97_i_71_c_compstr2010_sel_x_b_1(DELAY,29412)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1184_i_conv_i_i_i_i97_i_71_c_compstr2010_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_71_c_compstr2010_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19359_dupName_284_i_unnamed_c_compstr0_shift_x(BITSELECT,19358)@155
    assign rightShiftStage1Idx1Rng8_uid19359_dupName_284_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19358_dupName_284_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19361_dupName_284_i_unnamed_c_compstr0_shift_x(BITJOIN,19360)@155
    assign rightShiftStage1Idx1_uid19361_dupName_284_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19359_dupName_284_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19354_dupName_284_i_unnamed_c_compstr0_shift_x(BITSELECT,19353)@155
    assign rightShiftStage0Idx1Rng4_uid19354_dupName_284_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_q[33:4];

    // rightShiftStage0Idx1_uid19356_dupName_284_i_unnamed_c_compstr0_shift_x(BITJOIN,19355)@155
    assign rightShiftStage0Idx1_uid19356_dupName_284_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19354_dupName_284_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19358_dupName_284_i_unnamed_c_compstr0_shift_x(MUX,19357)@155
    assign rightShiftStage0_uid19358_dupName_284_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19358_dupName_284_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_q or rightShiftStage0Idx1_uid19356_dupName_284_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19358_dupName_284_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19358_dupName_284_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compstr2008_q;
            1'b1 : rightShiftStage0_uid19358_dupName_284_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19356_dupName_284_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19358_dupName_284_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19363_dupName_284_i_unnamed_c_compstr0_shift_x(MUX,19362)@155
    assign rightShiftStage1_uid19363_dupName_284_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19363_dupName_284_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19358_dupName_284_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19361_dupName_284_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19363_dupName_284_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19363_dupName_284_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19358_dupName_284_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19363_dupName_284_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19361_dupName_284_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19363_dupName_284_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2011_vt_select_21(BITSELECT,10677)@155
    assign i_unnamed_c_compstr2011_vt_select_21_b = rightShiftStage1_uid19363_dupName_284_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2011_vt_join(BITJOIN,10676)@155
    assign i_unnamed_c_compstr2011_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2011_vt_select_21_b};

    // i_unnamed_c_compstr2012_sel_x(BITSELECT,6114)@155
    assign i_unnamed_c_compstr2012_sel_x_b = i_unnamed_c_compstr2011_vt_join_q[15:0];

    // i_unnamed_c_compstr2013_BitSelect_for_a(BITSELECT,27617)@155
    assign i_unnamed_c_compstr2013_BitSelect_for_a_b = i_unnamed_c_compstr2012_sel_x_b[0:0];

    // i_unnamed_c_compstr2013_join(BITJOIN,27618)@155
    assign i_unnamed_c_compstr2013_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2013_BitSelect_for_a_b};

    // i_unnamed_c_compstr2013_vt_select_0(BITSELECT,10682)@155
    assign i_unnamed_c_compstr2013_vt_select_0_b = i_unnamed_c_compstr2013_join_q[0:0];

    // redist176_i_unnamed_c_compstr2013_vt_select_0_b_1(DELAY,28404)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist176_i_unnamed_c_compstr2013_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2013_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2013_vt_join(BITJOIN,10681)@156
    assign i_unnamed_c_compstr2013_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist176_i_unnamed_c_compstr2013_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_71_c_compstr2014(ADD,6947)@156
    assign i_add_i_i_i_i_i126_i_71_c_compstr2014_a = {1'b0, i_unnamed_c_compstr2013_vt_join_q};
    assign i_add_i_i_i_i_i126_i_71_c_compstr2014_b = {1'b0, redist1184_i_conv_i_i_i_i97_i_71_c_compstr2010_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_71_c_compstr2014_o = $unsigned(i_add_i_i_i_i_i126_i_71_c_compstr2014_a) + $unsigned(i_add_i_i_i_i_i126_i_71_c_compstr2014_b);
    assign i_add_i_i_i_i_i126_i_71_c_compstr2014_q = i_add_i_i_i_i_i126_i_71_c_compstr2014_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_71_c_compstr2014_sel_x(BITSELECT,2141)@156
    assign bgTrunc_i_add_i_i_i_i_i126_i_71_c_compstr2014_sel_x_b = i_add_i_i_i_i_i126_i_71_c_compstr2014_q[15:0];

    // i_conv_i_i_i_i_i75_i277_72_c_compstr2034_sel_x(BITSELECT,3682)@156
    assign i_conv_i_i_i_i_i75_i277_72_c_compstr2034_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_71_c_compstr2014_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_72_c_compstr2034_vt_select_15(BITSELECT,7629)@156
    assign i_conv_i_i_i_i_i75_i277_72_c_compstr2034_vt_select_15_b = i_conv_i_i_i_i_i75_i277_72_c_compstr2034_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_72_c_compstr2034_vt_join(BITJOIN,7628)@156
    assign i_conv_i_i_i_i_i75_i277_72_c_compstr2034_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_72_c_compstr2034_vt_select_15_b};

    // leftShiftStage0_uid24602_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x(MUX,24601)@156
    assign leftShiftStage0_uid24602_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24602_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_72_c_compstr2034_vt_join_q or leftShiftStage0Idx1_uid24600_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24602_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24602_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_72_c_compstr2034_vt_join_q;
            1'b1 : leftShiftStage0_uid24602_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24600_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24602_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24607_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x(MUX,24606)@156
    assign leftShiftStage1_uid24607_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24607_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_s or leftShiftStage0_uid24602_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24605_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24607_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24607_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q = leftShiftStage0_uid24602_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24607_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24605_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24607_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24612_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x(MUX,24611)@156
    assign leftShiftStage2_uid24612_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24612_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_s or leftShiftStage1_uid24607_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24610_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24612_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24612_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q = leftShiftStage1_uid24607_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24612_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24610_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24612_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_72_c_compstr2035_vt_select_28(BITSELECT,9331)@156
    assign i_shl_i_i_i_i_i77_i_72_c_compstr2035_vt_select_28_b = leftShiftStage2_uid24612_i_shl_i_i_i_i_i77_i_72_c_compstr0_shift_x_q[28:13];

    // redist413_i_shl_i_i_i_i_i77_i_72_c_compstr2035_vt_select_28_b_1(DELAY,28641)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist413_i_shl_i_i_i_i_i77_i_72_c_compstr2035_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_72_c_compstr2035_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_72_c_compstr2035_vt_join(BITJOIN,9330)@157
    assign i_shl_i_i_i_i_i77_i_72_c_compstr2035_vt_join_q = {redist413_i_shl_i_i_i_i_i77_i_72_c_compstr2035_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma(CHAINMULTADD,28195)@151 + 5
    // out q@157
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ah[0] <= redist915_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_145_tpl_143_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ah[1] <= redist914_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_144_tpl_143_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ch[0] <= redist661_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_145_tpl_143_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ch[1] <= redist660_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_144_tpl_143_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036(ADD,8491)@157
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compstr2031_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compstr2033_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compstr2032_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_72_c_compstr2035_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_72_c_compstr2035_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_o[33:0];

    // rightShiftStage0_uid19402_dupName_287_i_unnamed_c_compstr0_shift_x(MUX,19401)@157
    assign rightShiftStage0_uid19402_dupName_287_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19402_dupName_287_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_q or rightShiftStage0Idx1_uid19400_dupName_287_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19402_dupName_287_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19402_dupName_287_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_q;
            1'b1 : rightShiftStage0_uid19402_dupName_287_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19400_dupName_287_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19402_dupName_287_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19407_dupName_287_i_unnamed_c_compstr0_shift_x(MUX,19406)@157
    assign rightShiftStage1_uid19407_dupName_287_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19407_dupName_287_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19402_dupName_287_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19405_dupName_287_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19407_dupName_287_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19407_dupName_287_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19402_dupName_287_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19407_dupName_287_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19405_dupName_287_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19407_dupName_287_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19412_dupName_287_i_unnamed_c_compstr0_shift_x(MUX,19411)@157
    assign rightShiftStage2_uid19412_dupName_287_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19412_dupName_287_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19407_dupName_287_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19410_dupName_287_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19412_dupName_287_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19412_dupName_287_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19407_dupName_287_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19412_dupName_287_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19410_dupName_287_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19412_dupName_287_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2037_vt_select_20(BITSELECT,10696)@157
    assign i_unnamed_c_compstr2037_vt_select_20_b = rightShiftStage2_uid19412_dupName_287_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2037_vt_join(BITJOIN,10695)@157
    assign i_unnamed_c_compstr2037_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2037_vt_select_20_b};

    // i_conv_i_i_i_i97_i_72_c_compstr2038_sel_x(BITSELECT,3553)@157
    assign i_conv_i_i_i_i97_i_72_c_compstr2038_sel_x_b = i_unnamed_c_compstr2037_vt_join_q[15:0];

    // redist1183_i_conv_i_i_i_i97_i_72_c_compstr2038_sel_x_b_1(DELAY,29411)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1183_i_conv_i_i_i_i97_i_72_c_compstr2038_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_72_c_compstr2038_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19421_dupName_288_i_unnamed_c_compstr0_shift_x(BITSELECT,19420)@157
    assign rightShiftStage1Idx1Rng8_uid19421_dupName_288_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19420_dupName_288_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19423_dupName_288_i_unnamed_c_compstr0_shift_x(BITJOIN,19422)@157
    assign rightShiftStage1Idx1_uid19423_dupName_288_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19421_dupName_288_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19416_dupName_288_i_unnamed_c_compstr0_shift_x(BITSELECT,19415)@157
    assign rightShiftStage0Idx1Rng4_uid19416_dupName_288_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_q[33:4];

    // rightShiftStage0Idx1_uid19418_dupName_288_i_unnamed_c_compstr0_shift_x(BITJOIN,19417)@157
    assign rightShiftStage0Idx1_uid19418_dupName_288_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19416_dupName_288_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19420_dupName_288_i_unnamed_c_compstr0_shift_x(MUX,19419)@157
    assign rightShiftStage0_uid19420_dupName_288_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19420_dupName_288_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_q or rightShiftStage0Idx1_uid19418_dupName_288_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19420_dupName_288_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19420_dupName_288_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compstr2036_q;
            1'b1 : rightShiftStage0_uid19420_dupName_288_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19418_dupName_288_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19420_dupName_288_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19425_dupName_288_i_unnamed_c_compstr0_shift_x(MUX,19424)@157
    assign rightShiftStage1_uid19425_dupName_288_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19425_dupName_288_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19420_dupName_288_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19423_dupName_288_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19425_dupName_288_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19425_dupName_288_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19420_dupName_288_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19425_dupName_288_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19423_dupName_288_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19425_dupName_288_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2039_vt_select_21(BITSELECT,10699)@157
    assign i_unnamed_c_compstr2039_vt_select_21_b = rightShiftStage1_uid19425_dupName_288_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2039_vt_join(BITJOIN,10698)@157
    assign i_unnamed_c_compstr2039_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2039_vt_select_21_b};

    // i_unnamed_c_compstr2040_sel_x(BITSELECT,6116)@157
    assign i_unnamed_c_compstr2040_sel_x_b = i_unnamed_c_compstr2039_vt_join_q[15:0];

    // i_unnamed_c_compstr2041_BitSelect_for_a(BITSELECT,27621)@157
    assign i_unnamed_c_compstr2041_BitSelect_for_a_b = i_unnamed_c_compstr2040_sel_x_b[0:0];

    // i_unnamed_c_compstr2041_join(BITJOIN,27622)@157
    assign i_unnamed_c_compstr2041_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2041_BitSelect_for_a_b};

    // i_unnamed_c_compstr2041_vt_select_0(BITSELECT,10704)@157
    assign i_unnamed_c_compstr2041_vt_select_0_b = i_unnamed_c_compstr2041_join_q[0:0];

    // redist174_i_unnamed_c_compstr2041_vt_select_0_b_1(DELAY,28402)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist174_i_unnamed_c_compstr2041_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2041_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2041_vt_join(BITJOIN,10703)@158
    assign i_unnamed_c_compstr2041_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist174_i_unnamed_c_compstr2041_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_72_c_compstr2042(ADD,6948)@158
    assign i_add_i_i_i_i_i126_i_72_c_compstr2042_a = {1'b0, i_unnamed_c_compstr2041_vt_join_q};
    assign i_add_i_i_i_i_i126_i_72_c_compstr2042_b = {1'b0, redist1183_i_conv_i_i_i_i97_i_72_c_compstr2038_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_72_c_compstr2042_o = $unsigned(i_add_i_i_i_i_i126_i_72_c_compstr2042_a) + $unsigned(i_add_i_i_i_i_i126_i_72_c_compstr2042_b);
    assign i_add_i_i_i_i_i126_i_72_c_compstr2042_q = i_add_i_i_i_i_i126_i_72_c_compstr2042_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_72_c_compstr2042_sel_x(BITSELECT,2142)@158
    assign bgTrunc_i_add_i_i_i_i_i126_i_72_c_compstr2042_sel_x_b = i_add_i_i_i_i_i126_i_72_c_compstr2042_q[15:0];

    // i_conv_i_i_i_i_i75_i277_73_c_compstr2062_sel_x(BITSELECT,3683)@158
    assign i_conv_i_i_i_i_i75_i277_73_c_compstr2062_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_72_c_compstr2042_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_73_c_compstr2062_vt_select_15(BITSELECT,7633)@158
    assign i_conv_i_i_i_i_i75_i277_73_c_compstr2062_vt_select_15_b = i_conv_i_i_i_i_i75_i277_73_c_compstr2062_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_73_c_compstr2062_vt_join(BITJOIN,7632)@158
    assign i_conv_i_i_i_i_i75_i277_73_c_compstr2062_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_73_c_compstr2062_vt_select_15_b};

    // leftShiftStage0_uid24620_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x(MUX,24619)@158
    assign leftShiftStage0_uid24620_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24620_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_73_c_compstr2062_vt_join_q or leftShiftStage0Idx1_uid24618_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24620_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24620_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_73_c_compstr2062_vt_join_q;
            1'b1 : leftShiftStage0_uid24620_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24618_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24620_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24625_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x(MUX,24624)@158
    assign leftShiftStage1_uid24625_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24625_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_s or leftShiftStage0_uid24620_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24623_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24625_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24625_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q = leftShiftStage0_uid24620_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24625_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24623_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24625_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24630_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x(MUX,24629)@158
    assign leftShiftStage2_uid24630_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24630_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_s or leftShiftStage1_uid24625_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24628_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24630_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24630_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q = leftShiftStage1_uid24625_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24630_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24628_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24630_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_73_c_compstr2063_vt_select_28(BITSELECT,9334)@158
    assign i_shl_i_i_i_i_i77_i_73_c_compstr2063_vt_select_28_b = leftShiftStage2_uid24630_i_shl_i_i_i_i_i77_i_73_c_compstr0_shift_x_q[28:13];

    // redist412_i_shl_i_i_i_i_i77_i_73_c_compstr2063_vt_select_28_b_1(DELAY,28640)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist412_i_shl_i_i_i_i_i77_i_73_c_compstr2063_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_73_c_compstr2063_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_73_c_compstr2063_vt_join(BITJOIN,9333)@159
    assign i_shl_i_i_i_i_i77_i_73_c_compstr2063_vt_join_q = {redist412_i_shl_i_i_i_i_i77_i_73_c_compstr2063_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma(CHAINMULTADD,28196)@153 + 5
    // out q@159
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ah[0] <= redist917_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_147_tpl_145_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ah[1] <= redist916_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_146_tpl_145_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ch[0] <= redist663_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_147_tpl_145_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ch[1] <= redist662_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_146_tpl_145_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064(ADD,8492)@159
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compstr2059_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compstr2061_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compstr2060_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_73_c_compstr2063_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_73_c_compstr2063_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_o[33:0];

    // rightShiftStage0_uid19464_dupName_291_i_unnamed_c_compstr0_shift_x(MUX,19463)@159
    assign rightShiftStage0_uid19464_dupName_291_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19464_dupName_291_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_q or rightShiftStage0Idx1_uid19462_dupName_291_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19464_dupName_291_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19464_dupName_291_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_q;
            1'b1 : rightShiftStage0_uid19464_dupName_291_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19462_dupName_291_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19464_dupName_291_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19469_dupName_291_i_unnamed_c_compstr0_shift_x(MUX,19468)@159
    assign rightShiftStage1_uid19469_dupName_291_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19469_dupName_291_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19464_dupName_291_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19467_dupName_291_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19469_dupName_291_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19469_dupName_291_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19464_dupName_291_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19469_dupName_291_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19467_dupName_291_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19469_dupName_291_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19474_dupName_291_i_unnamed_c_compstr0_shift_x(MUX,19473)@159
    assign rightShiftStage2_uid19474_dupName_291_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19474_dupName_291_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19469_dupName_291_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19472_dupName_291_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19474_dupName_291_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19474_dupName_291_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19469_dupName_291_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19474_dupName_291_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19472_dupName_291_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19474_dupName_291_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2065_vt_select_20(BITSELECT,10721)@159
    assign i_unnamed_c_compstr2065_vt_select_20_b = rightShiftStage2_uid19474_dupName_291_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2065_vt_join(BITJOIN,10720)@159
    assign i_unnamed_c_compstr2065_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2065_vt_select_20_b};

    // i_conv_i_i_i_i97_i_73_c_compstr2066_sel_x(BITSELECT,3554)@159
    assign i_conv_i_i_i_i97_i_73_c_compstr2066_sel_x_b = i_unnamed_c_compstr2065_vt_join_q[15:0];

    // redist1182_i_conv_i_i_i_i97_i_73_c_compstr2066_sel_x_b_1(DELAY,29410)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1182_i_conv_i_i_i_i97_i_73_c_compstr2066_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_73_c_compstr2066_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19483_dupName_292_i_unnamed_c_compstr0_shift_x(BITSELECT,19482)@159
    assign rightShiftStage1Idx1Rng8_uid19483_dupName_292_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19482_dupName_292_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19485_dupName_292_i_unnamed_c_compstr0_shift_x(BITJOIN,19484)@159
    assign rightShiftStage1Idx1_uid19485_dupName_292_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19483_dupName_292_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19478_dupName_292_i_unnamed_c_compstr0_shift_x(BITSELECT,19477)@159
    assign rightShiftStage0Idx1Rng4_uid19478_dupName_292_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_q[33:4];

    // rightShiftStage0Idx1_uid19480_dupName_292_i_unnamed_c_compstr0_shift_x(BITJOIN,19479)@159
    assign rightShiftStage0Idx1_uid19480_dupName_292_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19478_dupName_292_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19482_dupName_292_i_unnamed_c_compstr0_shift_x(MUX,19481)@159
    assign rightShiftStage0_uid19482_dupName_292_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19482_dupName_292_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_q or rightShiftStage0Idx1_uid19480_dupName_292_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19482_dupName_292_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19482_dupName_292_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compstr2064_q;
            1'b1 : rightShiftStage0_uid19482_dupName_292_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19480_dupName_292_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19482_dupName_292_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19487_dupName_292_i_unnamed_c_compstr0_shift_x(MUX,19486)@159
    assign rightShiftStage1_uid19487_dupName_292_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19487_dupName_292_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19482_dupName_292_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19485_dupName_292_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19487_dupName_292_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19487_dupName_292_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19482_dupName_292_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19487_dupName_292_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19485_dupName_292_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19487_dupName_292_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2067_vt_select_21(BITSELECT,10724)@159
    assign i_unnamed_c_compstr2067_vt_select_21_b = rightShiftStage1_uid19487_dupName_292_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2067_vt_join(BITJOIN,10723)@159
    assign i_unnamed_c_compstr2067_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2067_vt_select_21_b};

    // i_unnamed_c_compstr2068_sel_x(BITSELECT,6118)@159
    assign i_unnamed_c_compstr2068_sel_x_b = i_unnamed_c_compstr2067_vt_join_q[15:0];

    // i_unnamed_c_compstr2069_BitSelect_for_a(BITSELECT,27625)@159
    assign i_unnamed_c_compstr2069_BitSelect_for_a_b = i_unnamed_c_compstr2068_sel_x_b[0:0];

    // i_unnamed_c_compstr2069_join(BITJOIN,27626)@159
    assign i_unnamed_c_compstr2069_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2069_BitSelect_for_a_b};

    // i_unnamed_c_compstr2069_vt_select_0(BITSELECT,10729)@159
    assign i_unnamed_c_compstr2069_vt_select_0_b = i_unnamed_c_compstr2069_join_q[0:0];

    // redist172_i_unnamed_c_compstr2069_vt_select_0_b_1(DELAY,28400)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist172_i_unnamed_c_compstr2069_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2069_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2069_vt_join(BITJOIN,10728)@160
    assign i_unnamed_c_compstr2069_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist172_i_unnamed_c_compstr2069_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_73_c_compstr2070(ADD,6949)@160
    assign i_add_i_i_i_i_i126_i_73_c_compstr2070_a = {1'b0, i_unnamed_c_compstr2069_vt_join_q};
    assign i_add_i_i_i_i_i126_i_73_c_compstr2070_b = {1'b0, redist1182_i_conv_i_i_i_i97_i_73_c_compstr2066_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_73_c_compstr2070_o = $unsigned(i_add_i_i_i_i_i126_i_73_c_compstr2070_a) + $unsigned(i_add_i_i_i_i_i126_i_73_c_compstr2070_b);
    assign i_add_i_i_i_i_i126_i_73_c_compstr2070_q = i_add_i_i_i_i_i126_i_73_c_compstr2070_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_73_c_compstr2070_sel_x(BITSELECT,2143)@160
    assign bgTrunc_i_add_i_i_i_i_i126_i_73_c_compstr2070_sel_x_b = i_add_i_i_i_i_i126_i_73_c_compstr2070_q[15:0];

    // i_conv_i_i_i_i_i75_i277_74_c_compstr2090_sel_x(BITSELECT,3684)@160
    assign i_conv_i_i_i_i_i75_i277_74_c_compstr2090_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_73_c_compstr2070_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_74_c_compstr2090_vt_select_15(BITSELECT,7637)@160
    assign i_conv_i_i_i_i_i75_i277_74_c_compstr2090_vt_select_15_b = i_conv_i_i_i_i_i75_i277_74_c_compstr2090_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_74_c_compstr2090_vt_join(BITJOIN,7636)@160
    assign i_conv_i_i_i_i_i75_i277_74_c_compstr2090_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_74_c_compstr2090_vt_select_15_b};

    // leftShiftStage0_uid24638_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x(MUX,24637)@160
    assign leftShiftStage0_uid24638_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24638_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_74_c_compstr2090_vt_join_q or leftShiftStage0Idx1_uid24636_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24638_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24638_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_74_c_compstr2090_vt_join_q;
            1'b1 : leftShiftStage0_uid24638_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24636_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24638_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24643_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x(MUX,24642)@160
    assign leftShiftStage1_uid24643_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24643_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_s or leftShiftStage0_uid24638_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24641_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24643_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24643_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q = leftShiftStage0_uid24638_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24643_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24641_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24643_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24648_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x(MUX,24647)@160
    assign leftShiftStage2_uid24648_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24648_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_s or leftShiftStage1_uid24643_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24646_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24648_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24648_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q = leftShiftStage1_uid24643_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24648_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24646_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24648_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_74_c_compstr2091_vt_select_28(BITSELECT,9337)@160
    assign i_shl_i_i_i_i_i77_i_74_c_compstr2091_vt_select_28_b = leftShiftStage2_uid24648_i_shl_i_i_i_i_i77_i_74_c_compstr0_shift_x_q[28:13];

    // redist411_i_shl_i_i_i_i_i77_i_74_c_compstr2091_vt_select_28_b_1(DELAY,28639)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist411_i_shl_i_i_i_i_i77_i_74_c_compstr2091_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_74_c_compstr2091_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_74_c_compstr2091_vt_join(BITJOIN,9336)@161
    assign i_shl_i_i_i_i_i77_i_74_c_compstr2091_vt_join_q = {redist411_i_shl_i_i_i_i_i77_i_74_c_compstr2091_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma(CHAINMULTADD,28197)@155 + 5
    // out q@161
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ah[0] <= redist919_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_149_tpl_147_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ah[1] <= redist918_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_148_tpl_147_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ch[0] <= redist665_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_149_tpl_147_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ch[1] <= redist664_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_148_tpl_147_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092(ADD,8493)@161
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compstr2087_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compstr2089_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compstr2088_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_74_c_compstr2091_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_74_c_compstr2091_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_o[33:0];

    // rightShiftStage0_uid19526_dupName_295_i_unnamed_c_compstr0_shift_x(MUX,19525)@161
    assign rightShiftStage0_uid19526_dupName_295_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19526_dupName_295_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_q or rightShiftStage0Idx1_uid19524_dupName_295_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19526_dupName_295_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19526_dupName_295_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_q;
            1'b1 : rightShiftStage0_uid19526_dupName_295_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19524_dupName_295_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19526_dupName_295_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19531_dupName_295_i_unnamed_c_compstr0_shift_x(MUX,19530)@161
    assign rightShiftStage1_uid19531_dupName_295_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19531_dupName_295_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19526_dupName_295_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19529_dupName_295_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19531_dupName_295_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19531_dupName_295_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19526_dupName_295_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19531_dupName_295_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19529_dupName_295_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19531_dupName_295_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19536_dupName_295_i_unnamed_c_compstr0_shift_x(MUX,19535)@161
    assign rightShiftStage2_uid19536_dupName_295_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19536_dupName_295_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19531_dupName_295_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19534_dupName_295_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19536_dupName_295_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19536_dupName_295_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19531_dupName_295_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19536_dupName_295_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19534_dupName_295_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19536_dupName_295_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2093_vt_select_20(BITSELECT,10748)@161
    assign i_unnamed_c_compstr2093_vt_select_20_b = rightShiftStage2_uid19536_dupName_295_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2093_vt_join(BITJOIN,10747)@161
    assign i_unnamed_c_compstr2093_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2093_vt_select_20_b};

    // i_conv_i_i_i_i97_i_74_c_compstr2094_sel_x(BITSELECT,3555)@161
    assign i_conv_i_i_i_i97_i_74_c_compstr2094_sel_x_b = i_unnamed_c_compstr2093_vt_join_q[15:0];

    // redist1181_i_conv_i_i_i_i97_i_74_c_compstr2094_sel_x_b_1(DELAY,29409)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1181_i_conv_i_i_i_i97_i_74_c_compstr2094_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_74_c_compstr2094_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19545_dupName_296_i_unnamed_c_compstr0_shift_x(BITSELECT,19544)@161
    assign rightShiftStage1Idx1Rng8_uid19545_dupName_296_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19544_dupName_296_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19547_dupName_296_i_unnamed_c_compstr0_shift_x(BITJOIN,19546)@161
    assign rightShiftStage1Idx1_uid19547_dupName_296_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19545_dupName_296_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19540_dupName_296_i_unnamed_c_compstr0_shift_x(BITSELECT,19539)@161
    assign rightShiftStage0Idx1Rng4_uid19540_dupName_296_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_q[33:4];

    // rightShiftStage0Idx1_uid19542_dupName_296_i_unnamed_c_compstr0_shift_x(BITJOIN,19541)@161
    assign rightShiftStage0Idx1_uid19542_dupName_296_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19540_dupName_296_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19544_dupName_296_i_unnamed_c_compstr0_shift_x(MUX,19543)@161
    assign rightShiftStage0_uid19544_dupName_296_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19544_dupName_296_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_q or rightShiftStage0Idx1_uid19542_dupName_296_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19544_dupName_296_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19544_dupName_296_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compstr2092_q;
            1'b1 : rightShiftStage0_uid19544_dupName_296_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19542_dupName_296_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19544_dupName_296_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19549_dupName_296_i_unnamed_c_compstr0_shift_x(MUX,19548)@161
    assign rightShiftStage1_uid19549_dupName_296_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19549_dupName_296_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19544_dupName_296_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19547_dupName_296_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19549_dupName_296_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19549_dupName_296_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19544_dupName_296_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19549_dupName_296_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19547_dupName_296_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19549_dupName_296_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2095_vt_select_21(BITSELECT,10751)@161
    assign i_unnamed_c_compstr2095_vt_select_21_b = rightShiftStage1_uid19549_dupName_296_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2095_vt_join(BITJOIN,10750)@161
    assign i_unnamed_c_compstr2095_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2095_vt_select_21_b};

    // i_unnamed_c_compstr2096_sel_x(BITSELECT,6121)@161
    assign i_unnamed_c_compstr2096_sel_x_b = i_unnamed_c_compstr2095_vt_join_q[15:0];

    // i_unnamed_c_compstr2097_BitSelect_for_a(BITSELECT,27631)@161
    assign i_unnamed_c_compstr2097_BitSelect_for_a_b = i_unnamed_c_compstr2096_sel_x_b[0:0];

    // i_unnamed_c_compstr2097_join(BITJOIN,27632)@161
    assign i_unnamed_c_compstr2097_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2097_BitSelect_for_a_b};

    // i_unnamed_c_compstr2097_vt_select_0(BITSELECT,10756)@161
    assign i_unnamed_c_compstr2097_vt_select_0_b = i_unnamed_c_compstr2097_join_q[0:0];

    // redist170_i_unnamed_c_compstr2097_vt_select_0_b_1(DELAY,28398)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist170_i_unnamed_c_compstr2097_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2097_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2097_vt_join(BITJOIN,10755)@162
    assign i_unnamed_c_compstr2097_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist170_i_unnamed_c_compstr2097_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_74_c_compstr2098(ADD,6950)@162
    assign i_add_i_i_i_i_i126_i_74_c_compstr2098_a = {1'b0, i_unnamed_c_compstr2097_vt_join_q};
    assign i_add_i_i_i_i_i126_i_74_c_compstr2098_b = {1'b0, redist1181_i_conv_i_i_i_i97_i_74_c_compstr2094_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_74_c_compstr2098_o = $unsigned(i_add_i_i_i_i_i126_i_74_c_compstr2098_a) + $unsigned(i_add_i_i_i_i_i126_i_74_c_compstr2098_b);
    assign i_add_i_i_i_i_i126_i_74_c_compstr2098_q = i_add_i_i_i_i_i126_i_74_c_compstr2098_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_74_c_compstr2098_sel_x(BITSELECT,2144)@162
    assign bgTrunc_i_add_i_i_i_i_i126_i_74_c_compstr2098_sel_x_b = i_add_i_i_i_i_i126_i_74_c_compstr2098_q[15:0];

    // i_conv_i_i_i_i_i75_i277_75_c_compstr2118_sel_x(BITSELECT,3685)@162
    assign i_conv_i_i_i_i_i75_i277_75_c_compstr2118_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_74_c_compstr2098_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_75_c_compstr2118_vt_select_15(BITSELECT,7641)@162
    assign i_conv_i_i_i_i_i75_i277_75_c_compstr2118_vt_select_15_b = i_conv_i_i_i_i_i75_i277_75_c_compstr2118_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_75_c_compstr2118_vt_join(BITJOIN,7640)@162
    assign i_conv_i_i_i_i_i75_i277_75_c_compstr2118_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_75_c_compstr2118_vt_select_15_b};

    // leftShiftStage0_uid24656_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x(MUX,24655)@162
    assign leftShiftStage0_uid24656_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24656_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_75_c_compstr2118_vt_join_q or leftShiftStage0Idx1_uid24654_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24656_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24656_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_75_c_compstr2118_vt_join_q;
            1'b1 : leftShiftStage0_uid24656_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24654_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24656_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24661_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x(MUX,24660)@162
    assign leftShiftStage1_uid24661_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24661_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_s or leftShiftStage0_uid24656_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24659_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24661_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24661_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q = leftShiftStage0_uid24656_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24661_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24659_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24661_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24666_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x(MUX,24665)@162
    assign leftShiftStage2_uid24666_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24666_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_s or leftShiftStage1_uid24661_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24664_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24666_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24666_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q = leftShiftStage1_uid24661_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24666_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24664_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24666_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_75_c_compstr2119_vt_select_28(BITSELECT,9340)@162
    assign i_shl_i_i_i_i_i77_i_75_c_compstr2119_vt_select_28_b = leftShiftStage2_uid24666_i_shl_i_i_i_i_i77_i_75_c_compstr0_shift_x_q[28:13];

    // redist410_i_shl_i_i_i_i_i77_i_75_c_compstr2119_vt_select_28_b_1(DELAY,28638)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist410_i_shl_i_i_i_i_i77_i_75_c_compstr2119_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_75_c_compstr2119_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_75_c_compstr2119_vt_join(BITJOIN,9339)@163
    assign i_shl_i_i_i_i_i77_i_75_c_compstr2119_vt_join_q = {redist410_i_shl_i_i_i_i_i77_i_75_c_compstr2119_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma(CHAINMULTADD,28198)@157 + 5
    // out q@163
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ah[0] <= redist921_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_151_tpl_149_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ah[1] <= redist920_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_150_tpl_149_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ch[0] <= redist667_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_151_tpl_149_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ch[1] <= redist666_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_150_tpl_149_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120(ADD,8494)@163
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compstr2115_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compstr2117_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compstr2116_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_75_c_compstr2119_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_75_c_compstr2119_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_o[33:0];

    // rightShiftStage0_uid19588_dupName_299_i_unnamed_c_compstr0_shift_x(MUX,19587)@163
    assign rightShiftStage0_uid19588_dupName_299_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19588_dupName_299_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_q or rightShiftStage0Idx1_uid19586_dupName_299_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19588_dupName_299_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19588_dupName_299_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_q;
            1'b1 : rightShiftStage0_uid19588_dupName_299_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19586_dupName_299_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19588_dupName_299_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19593_dupName_299_i_unnamed_c_compstr0_shift_x(MUX,19592)@163
    assign rightShiftStage1_uid19593_dupName_299_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19593_dupName_299_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19588_dupName_299_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19591_dupName_299_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19593_dupName_299_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19593_dupName_299_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19588_dupName_299_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19593_dupName_299_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19591_dupName_299_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19593_dupName_299_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19598_dupName_299_i_unnamed_c_compstr0_shift_x(MUX,19597)@163
    assign rightShiftStage2_uid19598_dupName_299_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19598_dupName_299_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19593_dupName_299_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19596_dupName_299_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19598_dupName_299_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19598_dupName_299_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19593_dupName_299_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19598_dupName_299_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19596_dupName_299_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19598_dupName_299_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2121_vt_select_20(BITSELECT,10773)@163
    assign i_unnamed_c_compstr2121_vt_select_20_b = rightShiftStage2_uid19598_dupName_299_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2121_vt_join(BITJOIN,10772)@163
    assign i_unnamed_c_compstr2121_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2121_vt_select_20_b};

    // i_conv_i_i_i_i97_i_75_c_compstr2122_sel_x(BITSELECT,3556)@163
    assign i_conv_i_i_i_i97_i_75_c_compstr2122_sel_x_b = i_unnamed_c_compstr2121_vt_join_q[15:0];

    // redist1180_i_conv_i_i_i_i97_i_75_c_compstr2122_sel_x_b_1(DELAY,29408)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1180_i_conv_i_i_i_i97_i_75_c_compstr2122_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_75_c_compstr2122_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19607_dupName_300_i_unnamed_c_compstr0_shift_x(BITSELECT,19606)@163
    assign rightShiftStage1Idx1Rng8_uid19607_dupName_300_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19606_dupName_300_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19609_dupName_300_i_unnamed_c_compstr0_shift_x(BITJOIN,19608)@163
    assign rightShiftStage1Idx1_uid19609_dupName_300_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19607_dupName_300_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19602_dupName_300_i_unnamed_c_compstr0_shift_x(BITSELECT,19601)@163
    assign rightShiftStage0Idx1Rng4_uid19602_dupName_300_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_q[33:4];

    // rightShiftStage0Idx1_uid19604_dupName_300_i_unnamed_c_compstr0_shift_x(BITJOIN,19603)@163
    assign rightShiftStage0Idx1_uid19604_dupName_300_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19602_dupName_300_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19606_dupName_300_i_unnamed_c_compstr0_shift_x(MUX,19605)@163
    assign rightShiftStage0_uid19606_dupName_300_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19606_dupName_300_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_q or rightShiftStage0Idx1_uid19604_dupName_300_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19606_dupName_300_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19606_dupName_300_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compstr2120_q;
            1'b1 : rightShiftStage0_uid19606_dupName_300_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19604_dupName_300_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19606_dupName_300_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19611_dupName_300_i_unnamed_c_compstr0_shift_x(MUX,19610)@163
    assign rightShiftStage1_uid19611_dupName_300_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19611_dupName_300_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19606_dupName_300_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19609_dupName_300_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19611_dupName_300_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19611_dupName_300_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19606_dupName_300_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19611_dupName_300_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19609_dupName_300_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19611_dupName_300_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2123_vt_select_21(BITSELECT,10776)@163
    assign i_unnamed_c_compstr2123_vt_select_21_b = rightShiftStage1_uid19611_dupName_300_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2123_vt_join(BITJOIN,10775)@163
    assign i_unnamed_c_compstr2123_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2123_vt_select_21_b};

    // i_unnamed_c_compstr2124_sel_x(BITSELECT,6123)@163
    assign i_unnamed_c_compstr2124_sel_x_b = i_unnamed_c_compstr2123_vt_join_q[15:0];

    // i_unnamed_c_compstr2125_BitSelect_for_a(BITSELECT,27635)@163
    assign i_unnamed_c_compstr2125_BitSelect_for_a_b = i_unnamed_c_compstr2124_sel_x_b[0:0];

    // i_unnamed_c_compstr2125_join(BITJOIN,27636)@163
    assign i_unnamed_c_compstr2125_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2125_BitSelect_for_a_b};

    // i_unnamed_c_compstr2125_vt_select_0(BITSELECT,10781)@163
    assign i_unnamed_c_compstr2125_vt_select_0_b = i_unnamed_c_compstr2125_join_q[0:0];

    // redist167_i_unnamed_c_compstr2125_vt_select_0_b_1(DELAY,28395)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist167_i_unnamed_c_compstr2125_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2125_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2125_vt_join(BITJOIN,10780)@164
    assign i_unnamed_c_compstr2125_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist167_i_unnamed_c_compstr2125_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_75_c_compstr2126(ADD,6951)@164
    assign i_add_i_i_i_i_i126_i_75_c_compstr2126_a = {1'b0, i_unnamed_c_compstr2125_vt_join_q};
    assign i_add_i_i_i_i_i126_i_75_c_compstr2126_b = {1'b0, redist1180_i_conv_i_i_i_i97_i_75_c_compstr2122_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_75_c_compstr2126_o = $unsigned(i_add_i_i_i_i_i126_i_75_c_compstr2126_a) + $unsigned(i_add_i_i_i_i_i126_i_75_c_compstr2126_b);
    assign i_add_i_i_i_i_i126_i_75_c_compstr2126_q = i_add_i_i_i_i_i126_i_75_c_compstr2126_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_75_c_compstr2126_sel_x(BITSELECT,2145)@164
    assign bgTrunc_i_add_i_i_i_i_i126_i_75_c_compstr2126_sel_x_b = i_add_i_i_i_i_i126_i_75_c_compstr2126_q[15:0];

    // i_conv_i_i_i_i_i75_i277_76_c_compstr2146_sel_x(BITSELECT,3686)@164
    assign i_conv_i_i_i_i_i75_i277_76_c_compstr2146_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_75_c_compstr2126_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_76_c_compstr2146_vt_select_15(BITSELECT,7645)@164
    assign i_conv_i_i_i_i_i75_i277_76_c_compstr2146_vt_select_15_b = i_conv_i_i_i_i_i75_i277_76_c_compstr2146_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_76_c_compstr2146_vt_join(BITJOIN,7644)@164
    assign i_conv_i_i_i_i_i75_i277_76_c_compstr2146_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_76_c_compstr2146_vt_select_15_b};

    // leftShiftStage0_uid24674_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x(MUX,24673)@164
    assign leftShiftStage0_uid24674_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24674_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_76_c_compstr2146_vt_join_q or leftShiftStage0Idx1_uid24672_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24674_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24674_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_76_c_compstr2146_vt_join_q;
            1'b1 : leftShiftStage0_uid24674_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24672_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24674_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24679_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x(MUX,24678)@164
    assign leftShiftStage1_uid24679_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24679_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_s or leftShiftStage0_uid24674_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24677_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24679_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24679_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q = leftShiftStage0_uid24674_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24679_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24677_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24679_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24684_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x(MUX,24683)@164
    assign leftShiftStage2_uid24684_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24684_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_s or leftShiftStage1_uid24679_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24682_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24684_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24684_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q = leftShiftStage1_uid24679_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24684_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24682_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24684_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_76_c_compstr2147_vt_select_28(BITSELECT,9343)@164
    assign i_shl_i_i_i_i_i77_i_76_c_compstr2147_vt_select_28_b = leftShiftStage2_uid24684_i_shl_i_i_i_i_i77_i_76_c_compstr0_shift_x_q[28:13];

    // redist409_i_shl_i_i_i_i_i77_i_76_c_compstr2147_vt_select_28_b_1(DELAY,28637)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist409_i_shl_i_i_i_i_i77_i_76_c_compstr2147_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_76_c_compstr2147_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_76_c_compstr2147_vt_join(BITJOIN,9342)@165
    assign i_shl_i_i_i_i_i77_i_76_c_compstr2147_vt_join_q = {redist409_i_shl_i_i_i_i_i77_i_76_c_compstr2147_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma(CHAINMULTADD,28199)@159 + 5
    // out q@165
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ah[0] <= redist923_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_153_tpl_151_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ah[1] <= redist922_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_152_tpl_151_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ch[0] <= redist669_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_153_tpl_151_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ch[1] <= redist668_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_152_tpl_151_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148(ADD,8495)@165
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compstr2143_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compstr2145_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compstr2144_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_76_c_compstr2147_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_76_c_compstr2147_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_o[33:0];

    // rightShiftStage0_uid19650_dupName_303_i_unnamed_c_compstr0_shift_x(MUX,19649)@165
    assign rightShiftStage0_uid19650_dupName_303_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19650_dupName_303_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_q or rightShiftStage0Idx1_uid19648_dupName_303_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19650_dupName_303_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19650_dupName_303_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_q;
            1'b1 : rightShiftStage0_uid19650_dupName_303_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19648_dupName_303_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19650_dupName_303_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19655_dupName_303_i_unnamed_c_compstr0_shift_x(MUX,19654)@165
    assign rightShiftStage1_uid19655_dupName_303_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19655_dupName_303_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19650_dupName_303_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19653_dupName_303_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19655_dupName_303_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19655_dupName_303_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19650_dupName_303_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19655_dupName_303_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19653_dupName_303_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19655_dupName_303_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19660_dupName_303_i_unnamed_c_compstr0_shift_x(MUX,19659)@165
    assign rightShiftStage2_uid19660_dupName_303_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19660_dupName_303_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19655_dupName_303_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19658_dupName_303_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19660_dupName_303_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19660_dupName_303_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19655_dupName_303_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19660_dupName_303_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19658_dupName_303_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19660_dupName_303_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2149_vt_select_20(BITSELECT,10795)@165
    assign i_unnamed_c_compstr2149_vt_select_20_b = rightShiftStage2_uid19660_dupName_303_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2149_vt_join(BITJOIN,10794)@165
    assign i_unnamed_c_compstr2149_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2149_vt_select_20_b};

    // i_conv_i_i_i_i97_i_76_c_compstr2150_sel_x(BITSELECT,3557)@165
    assign i_conv_i_i_i_i97_i_76_c_compstr2150_sel_x_b = i_unnamed_c_compstr2149_vt_join_q[15:0];

    // redist1179_i_conv_i_i_i_i97_i_76_c_compstr2150_sel_x_b_1(DELAY,29407)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1179_i_conv_i_i_i_i97_i_76_c_compstr2150_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_76_c_compstr2150_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19669_dupName_304_i_unnamed_c_compstr0_shift_x(BITSELECT,19668)@165
    assign rightShiftStage1Idx1Rng8_uid19669_dupName_304_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19668_dupName_304_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19671_dupName_304_i_unnamed_c_compstr0_shift_x(BITJOIN,19670)@165
    assign rightShiftStage1Idx1_uid19671_dupName_304_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19669_dupName_304_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19664_dupName_304_i_unnamed_c_compstr0_shift_x(BITSELECT,19663)@165
    assign rightShiftStage0Idx1Rng4_uid19664_dupName_304_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_q[33:4];

    // rightShiftStage0Idx1_uid19666_dupName_304_i_unnamed_c_compstr0_shift_x(BITJOIN,19665)@165
    assign rightShiftStage0Idx1_uid19666_dupName_304_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19664_dupName_304_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19668_dupName_304_i_unnamed_c_compstr0_shift_x(MUX,19667)@165
    assign rightShiftStage0_uid19668_dupName_304_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19668_dupName_304_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_q or rightShiftStage0Idx1_uid19666_dupName_304_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19668_dupName_304_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19668_dupName_304_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compstr2148_q;
            1'b1 : rightShiftStage0_uid19668_dupName_304_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19666_dupName_304_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19668_dupName_304_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19673_dupName_304_i_unnamed_c_compstr0_shift_x(MUX,19672)@165
    assign rightShiftStage1_uid19673_dupName_304_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19673_dupName_304_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19668_dupName_304_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19671_dupName_304_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19673_dupName_304_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19673_dupName_304_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19668_dupName_304_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19673_dupName_304_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19671_dupName_304_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19673_dupName_304_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2151_vt_select_21(BITSELECT,10798)@165
    assign i_unnamed_c_compstr2151_vt_select_21_b = rightShiftStage1_uid19673_dupName_304_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2151_vt_join(BITJOIN,10797)@165
    assign i_unnamed_c_compstr2151_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2151_vt_select_21_b};

    // i_unnamed_c_compstr2152_sel_x(BITSELECT,6125)@165
    assign i_unnamed_c_compstr2152_sel_x_b = i_unnamed_c_compstr2151_vt_join_q[15:0];

    // i_unnamed_c_compstr2153_BitSelect_for_a(BITSELECT,27639)@165
    assign i_unnamed_c_compstr2153_BitSelect_for_a_b = i_unnamed_c_compstr2152_sel_x_b[0:0];

    // i_unnamed_c_compstr2153_join(BITJOIN,27640)@165
    assign i_unnamed_c_compstr2153_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2153_BitSelect_for_a_b};

    // i_unnamed_c_compstr2153_vt_select_0(BITSELECT,10803)@165
    assign i_unnamed_c_compstr2153_vt_select_0_b = i_unnamed_c_compstr2153_join_q[0:0];

    // redist165_i_unnamed_c_compstr2153_vt_select_0_b_1(DELAY,28393)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist165_i_unnamed_c_compstr2153_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2153_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2153_vt_join(BITJOIN,10802)@166
    assign i_unnamed_c_compstr2153_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist165_i_unnamed_c_compstr2153_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_76_c_compstr2154(ADD,6952)@166
    assign i_add_i_i_i_i_i126_i_76_c_compstr2154_a = {1'b0, i_unnamed_c_compstr2153_vt_join_q};
    assign i_add_i_i_i_i_i126_i_76_c_compstr2154_b = {1'b0, redist1179_i_conv_i_i_i_i97_i_76_c_compstr2150_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_76_c_compstr2154_o = $unsigned(i_add_i_i_i_i_i126_i_76_c_compstr2154_a) + $unsigned(i_add_i_i_i_i_i126_i_76_c_compstr2154_b);
    assign i_add_i_i_i_i_i126_i_76_c_compstr2154_q = i_add_i_i_i_i_i126_i_76_c_compstr2154_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_76_c_compstr2154_sel_x(BITSELECT,2146)@166
    assign bgTrunc_i_add_i_i_i_i_i126_i_76_c_compstr2154_sel_x_b = i_add_i_i_i_i_i126_i_76_c_compstr2154_q[15:0];

    // i_conv_i_i_i_i_i75_i277_77_c_compstr2174_sel_x(BITSELECT,3687)@166
    assign i_conv_i_i_i_i_i75_i277_77_c_compstr2174_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_76_c_compstr2154_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_77_c_compstr2174_vt_select_15(BITSELECT,7649)@166
    assign i_conv_i_i_i_i_i75_i277_77_c_compstr2174_vt_select_15_b = i_conv_i_i_i_i_i75_i277_77_c_compstr2174_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_77_c_compstr2174_vt_join(BITJOIN,7648)@166
    assign i_conv_i_i_i_i_i75_i277_77_c_compstr2174_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_77_c_compstr2174_vt_select_15_b};

    // leftShiftStage0_uid24692_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x(MUX,24691)@166
    assign leftShiftStage0_uid24692_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24692_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_77_c_compstr2174_vt_join_q or leftShiftStage0Idx1_uid24690_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24692_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24692_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_77_c_compstr2174_vt_join_q;
            1'b1 : leftShiftStage0_uid24692_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24690_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24692_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24697_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x(MUX,24696)@166
    assign leftShiftStage1_uid24697_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24697_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_s or leftShiftStage0_uid24692_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24695_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24697_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24697_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q = leftShiftStage0_uid24692_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24697_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24695_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24697_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24702_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x(MUX,24701)@166
    assign leftShiftStage2_uid24702_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24702_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_s or leftShiftStage1_uid24697_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24700_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24702_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24702_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q = leftShiftStage1_uid24697_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24702_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24700_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24702_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_77_c_compstr2175_vt_select_28(BITSELECT,9346)@166
    assign i_shl_i_i_i_i_i77_i_77_c_compstr2175_vt_select_28_b = leftShiftStage2_uid24702_i_shl_i_i_i_i_i77_i_77_c_compstr0_shift_x_q[28:13];

    // redist408_i_shl_i_i_i_i_i77_i_77_c_compstr2175_vt_select_28_b_1(DELAY,28636)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist408_i_shl_i_i_i_i_i77_i_77_c_compstr2175_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_77_c_compstr2175_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_77_c_compstr2175_vt_join(BITJOIN,9345)@167
    assign i_shl_i_i_i_i_i77_i_77_c_compstr2175_vt_join_q = {redist408_i_shl_i_i_i_i_i77_i_77_c_compstr2175_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma(CHAINMULTADD,28200)@161 + 5
    // out q@167
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ah[0] <= redist925_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_155_tpl_153_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ah[1] <= redist924_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_154_tpl_153_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ch[0] <= redist671_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_155_tpl_153_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ch[1] <= redist670_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_154_tpl_153_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176(ADD,8496)@167
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compstr2171_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compstr2173_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compstr2172_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_77_c_compstr2175_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_77_c_compstr2175_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_o[33:0];

    // rightShiftStage0_uid19712_dupName_307_i_unnamed_c_compstr0_shift_x(MUX,19711)@167
    assign rightShiftStage0_uid19712_dupName_307_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19712_dupName_307_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_q or rightShiftStage0Idx1_uid19710_dupName_307_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19712_dupName_307_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19712_dupName_307_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_q;
            1'b1 : rightShiftStage0_uid19712_dupName_307_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19710_dupName_307_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19712_dupName_307_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19717_dupName_307_i_unnamed_c_compstr0_shift_x(MUX,19716)@167
    assign rightShiftStage1_uid19717_dupName_307_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19717_dupName_307_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19712_dupName_307_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19715_dupName_307_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19717_dupName_307_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19717_dupName_307_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19712_dupName_307_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19717_dupName_307_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19715_dupName_307_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19717_dupName_307_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19722_dupName_307_i_unnamed_c_compstr0_shift_x(MUX,19721)@167
    assign rightShiftStage2_uid19722_dupName_307_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19722_dupName_307_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19717_dupName_307_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19720_dupName_307_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19722_dupName_307_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19722_dupName_307_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19717_dupName_307_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19722_dupName_307_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19720_dupName_307_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19722_dupName_307_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2177_vt_select_20(BITSELECT,10817)@167
    assign i_unnamed_c_compstr2177_vt_select_20_b = rightShiftStage2_uid19722_dupName_307_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2177_vt_join(BITJOIN,10816)@167
    assign i_unnamed_c_compstr2177_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2177_vt_select_20_b};

    // i_conv_i_i_i_i97_i_77_c_compstr2178_sel_x(BITSELECT,3558)@167
    assign i_conv_i_i_i_i97_i_77_c_compstr2178_sel_x_b = i_unnamed_c_compstr2177_vt_join_q[15:0];

    // redist1178_i_conv_i_i_i_i97_i_77_c_compstr2178_sel_x_b_1(DELAY,29406)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1178_i_conv_i_i_i_i97_i_77_c_compstr2178_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_77_c_compstr2178_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19731_dupName_308_i_unnamed_c_compstr0_shift_x(BITSELECT,19730)@167
    assign rightShiftStage1Idx1Rng8_uid19731_dupName_308_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19730_dupName_308_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19733_dupName_308_i_unnamed_c_compstr0_shift_x(BITJOIN,19732)@167
    assign rightShiftStage1Idx1_uid19733_dupName_308_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19731_dupName_308_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19726_dupName_308_i_unnamed_c_compstr0_shift_x(BITSELECT,19725)@167
    assign rightShiftStage0Idx1Rng4_uid19726_dupName_308_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_q[33:4];

    // rightShiftStage0Idx1_uid19728_dupName_308_i_unnamed_c_compstr0_shift_x(BITJOIN,19727)@167
    assign rightShiftStage0Idx1_uid19728_dupName_308_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19726_dupName_308_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19730_dupName_308_i_unnamed_c_compstr0_shift_x(MUX,19729)@167
    assign rightShiftStage0_uid19730_dupName_308_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19730_dupName_308_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_q or rightShiftStage0Idx1_uid19728_dupName_308_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19730_dupName_308_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19730_dupName_308_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compstr2176_q;
            1'b1 : rightShiftStage0_uid19730_dupName_308_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19728_dupName_308_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19730_dupName_308_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19735_dupName_308_i_unnamed_c_compstr0_shift_x(MUX,19734)@167
    assign rightShiftStage1_uid19735_dupName_308_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19735_dupName_308_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19730_dupName_308_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19733_dupName_308_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19735_dupName_308_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19735_dupName_308_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19730_dupName_308_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19735_dupName_308_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19733_dupName_308_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19735_dupName_308_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2179_vt_select_21(BITSELECT,10820)@167
    assign i_unnamed_c_compstr2179_vt_select_21_b = rightShiftStage1_uid19735_dupName_308_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2179_vt_join(BITJOIN,10819)@167
    assign i_unnamed_c_compstr2179_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2179_vt_select_21_b};

    // i_unnamed_c_compstr2180_sel_x(BITSELECT,6127)@167
    assign i_unnamed_c_compstr2180_sel_x_b = i_unnamed_c_compstr2179_vt_join_q[15:0];

    // i_unnamed_c_compstr2181_BitSelect_for_a(BITSELECT,27643)@167
    assign i_unnamed_c_compstr2181_BitSelect_for_a_b = i_unnamed_c_compstr2180_sel_x_b[0:0];

    // i_unnamed_c_compstr2181_join(BITJOIN,27644)@167
    assign i_unnamed_c_compstr2181_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2181_BitSelect_for_a_b};

    // i_unnamed_c_compstr2181_vt_select_0(BITSELECT,10828)@167
    assign i_unnamed_c_compstr2181_vt_select_0_b = i_unnamed_c_compstr2181_join_q[0:0];

    // redist163_i_unnamed_c_compstr2181_vt_select_0_b_1(DELAY,28391)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist163_i_unnamed_c_compstr2181_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2181_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2181_vt_join(BITJOIN,10827)@168
    assign i_unnamed_c_compstr2181_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist163_i_unnamed_c_compstr2181_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_77_c_compstr2182(ADD,6953)@168
    assign i_add_i_i_i_i_i126_i_77_c_compstr2182_a = {1'b0, i_unnamed_c_compstr2181_vt_join_q};
    assign i_add_i_i_i_i_i126_i_77_c_compstr2182_b = {1'b0, redist1178_i_conv_i_i_i_i97_i_77_c_compstr2178_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_77_c_compstr2182_o = $unsigned(i_add_i_i_i_i_i126_i_77_c_compstr2182_a) + $unsigned(i_add_i_i_i_i_i126_i_77_c_compstr2182_b);
    assign i_add_i_i_i_i_i126_i_77_c_compstr2182_q = i_add_i_i_i_i_i126_i_77_c_compstr2182_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_77_c_compstr2182_sel_x(BITSELECT,2147)@168
    assign bgTrunc_i_add_i_i_i_i_i126_i_77_c_compstr2182_sel_x_b = i_add_i_i_i_i_i126_i_77_c_compstr2182_q[15:0];

    // i_conv_i_i_i_i_i75_i277_78_c_compstr2202_sel_x(BITSELECT,3688)@168
    assign i_conv_i_i_i_i_i75_i277_78_c_compstr2202_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_77_c_compstr2182_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_78_c_compstr2202_vt_select_15(BITSELECT,7653)@168
    assign i_conv_i_i_i_i_i75_i277_78_c_compstr2202_vt_select_15_b = i_conv_i_i_i_i_i75_i277_78_c_compstr2202_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_78_c_compstr2202_vt_join(BITJOIN,7652)@168
    assign i_conv_i_i_i_i_i75_i277_78_c_compstr2202_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_78_c_compstr2202_vt_select_15_b};

    // leftShiftStage0_uid24710_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x(MUX,24709)@168
    assign leftShiftStage0_uid24710_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24710_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_78_c_compstr2202_vt_join_q or leftShiftStage0Idx1_uid24708_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24710_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24710_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_78_c_compstr2202_vt_join_q;
            1'b1 : leftShiftStage0_uid24710_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24708_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24710_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24715_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x(MUX,24714)@168
    assign leftShiftStage1_uid24715_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24715_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_s or leftShiftStage0_uid24710_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24713_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24715_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24715_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q = leftShiftStage0_uid24710_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24715_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24713_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24715_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24720_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x(MUX,24719)@168
    assign leftShiftStage2_uid24720_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24720_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_s or leftShiftStage1_uid24715_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24718_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24720_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24720_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q = leftShiftStage1_uid24715_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24720_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24718_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24720_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_78_c_compstr2203_vt_select_28(BITSELECT,9349)@168
    assign i_shl_i_i_i_i_i77_i_78_c_compstr2203_vt_select_28_b = leftShiftStage2_uid24720_i_shl_i_i_i_i_i77_i_78_c_compstr0_shift_x_q[28:13];

    // redist407_i_shl_i_i_i_i_i77_i_78_c_compstr2203_vt_select_28_b_1(DELAY,28635)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist407_i_shl_i_i_i_i_i77_i_78_c_compstr2203_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_78_c_compstr2203_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_78_c_compstr2203_vt_join(BITJOIN,9348)@169
    assign i_shl_i_i_i_i_i77_i_78_c_compstr2203_vt_join_q = {redist407_i_shl_i_i_i_i_i77_i_78_c_compstr2203_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma(CHAINMULTADD,28201)@163 + 5
    // out q@169
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ah[0] <= redist927_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_157_tpl_155_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ah[1] <= redist926_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_156_tpl_155_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ch[0] <= redist673_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_157_tpl_155_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ch[1] <= redist672_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_156_tpl_155_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204(ADD,8497)@169
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compstr2199_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compstr2201_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compstr2200_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_78_c_compstr2203_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_78_c_compstr2203_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_o[33:0];

    // rightShiftStage0_uid19774_dupName_311_i_unnamed_c_compstr0_shift_x(MUX,19773)@169
    assign rightShiftStage0_uid19774_dupName_311_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19774_dupName_311_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_q or rightShiftStage0Idx1_uid19772_dupName_311_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19774_dupName_311_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19774_dupName_311_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_q;
            1'b1 : rightShiftStage0_uid19774_dupName_311_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19772_dupName_311_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19774_dupName_311_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19779_dupName_311_i_unnamed_c_compstr0_shift_x(MUX,19778)@169
    assign rightShiftStage1_uid19779_dupName_311_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19779_dupName_311_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19774_dupName_311_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19777_dupName_311_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19779_dupName_311_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19779_dupName_311_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19774_dupName_311_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19779_dupName_311_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19777_dupName_311_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19779_dupName_311_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19784_dupName_311_i_unnamed_c_compstr0_shift_x(MUX,19783)@169
    assign rightShiftStage2_uid19784_dupName_311_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19784_dupName_311_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19779_dupName_311_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19782_dupName_311_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19784_dupName_311_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19784_dupName_311_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19779_dupName_311_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19784_dupName_311_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19782_dupName_311_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19784_dupName_311_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2205_vt_select_20(BITSELECT,10845)@169
    assign i_unnamed_c_compstr2205_vt_select_20_b = rightShiftStage2_uid19784_dupName_311_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2205_vt_join(BITJOIN,10844)@169
    assign i_unnamed_c_compstr2205_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2205_vt_select_20_b};

    // i_conv_i_i_i_i97_i_78_c_compstr2206_sel_x(BITSELECT,3559)@169
    assign i_conv_i_i_i_i97_i_78_c_compstr2206_sel_x_b = i_unnamed_c_compstr2205_vt_join_q[15:0];

    // redist1177_i_conv_i_i_i_i97_i_78_c_compstr2206_sel_x_b_1(DELAY,29405)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1177_i_conv_i_i_i_i97_i_78_c_compstr2206_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_78_c_compstr2206_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19793_dupName_312_i_unnamed_c_compstr0_shift_x(BITSELECT,19792)@169
    assign rightShiftStage1Idx1Rng8_uid19793_dupName_312_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19792_dupName_312_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19795_dupName_312_i_unnamed_c_compstr0_shift_x(BITJOIN,19794)@169
    assign rightShiftStage1Idx1_uid19795_dupName_312_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19793_dupName_312_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19788_dupName_312_i_unnamed_c_compstr0_shift_x(BITSELECT,19787)@169
    assign rightShiftStage0Idx1Rng4_uid19788_dupName_312_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_q[33:4];

    // rightShiftStage0Idx1_uid19790_dupName_312_i_unnamed_c_compstr0_shift_x(BITJOIN,19789)@169
    assign rightShiftStage0Idx1_uid19790_dupName_312_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19788_dupName_312_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19792_dupName_312_i_unnamed_c_compstr0_shift_x(MUX,19791)@169
    assign rightShiftStage0_uid19792_dupName_312_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19792_dupName_312_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_q or rightShiftStage0Idx1_uid19790_dupName_312_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19792_dupName_312_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19792_dupName_312_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compstr2204_q;
            1'b1 : rightShiftStage0_uid19792_dupName_312_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19790_dupName_312_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19792_dupName_312_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19797_dupName_312_i_unnamed_c_compstr0_shift_x(MUX,19796)@169
    assign rightShiftStage1_uid19797_dupName_312_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19797_dupName_312_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19792_dupName_312_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19795_dupName_312_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19797_dupName_312_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19797_dupName_312_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19792_dupName_312_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19797_dupName_312_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19795_dupName_312_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19797_dupName_312_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2207_vt_select_21(BITSELECT,10848)@169
    assign i_unnamed_c_compstr2207_vt_select_21_b = rightShiftStage1_uid19797_dupName_312_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2207_vt_join(BITJOIN,10847)@169
    assign i_unnamed_c_compstr2207_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2207_vt_select_21_b};

    // i_unnamed_c_compstr2208_sel_x(BITSELECT,6130)@169
    assign i_unnamed_c_compstr2208_sel_x_b = i_unnamed_c_compstr2207_vt_join_q[15:0];

    // i_unnamed_c_compstr2209_BitSelect_for_a(BITSELECT,27647)@169
    assign i_unnamed_c_compstr2209_BitSelect_for_a_b = i_unnamed_c_compstr2208_sel_x_b[0:0];

    // i_unnamed_c_compstr2209_join(BITJOIN,27648)@169
    assign i_unnamed_c_compstr2209_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2209_BitSelect_for_a_b};

    // i_unnamed_c_compstr2209_vt_select_0(BITSELECT,10853)@169
    assign i_unnamed_c_compstr2209_vt_select_0_b = i_unnamed_c_compstr2209_join_q[0:0];

    // redist161_i_unnamed_c_compstr2209_vt_select_0_b_1(DELAY,28389)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist161_i_unnamed_c_compstr2209_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2209_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2209_vt_join(BITJOIN,10852)@170
    assign i_unnamed_c_compstr2209_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist161_i_unnamed_c_compstr2209_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_78_c_compstr2210(ADD,6954)@170
    assign i_add_i_i_i_i_i126_i_78_c_compstr2210_a = {1'b0, i_unnamed_c_compstr2209_vt_join_q};
    assign i_add_i_i_i_i_i126_i_78_c_compstr2210_b = {1'b0, redist1177_i_conv_i_i_i_i97_i_78_c_compstr2206_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_78_c_compstr2210_o = $unsigned(i_add_i_i_i_i_i126_i_78_c_compstr2210_a) + $unsigned(i_add_i_i_i_i_i126_i_78_c_compstr2210_b);
    assign i_add_i_i_i_i_i126_i_78_c_compstr2210_q = i_add_i_i_i_i_i126_i_78_c_compstr2210_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_78_c_compstr2210_sel_x(BITSELECT,2148)@170
    assign bgTrunc_i_add_i_i_i_i_i126_i_78_c_compstr2210_sel_x_b = i_add_i_i_i_i_i126_i_78_c_compstr2210_q[15:0];

    // i_conv_i_i_i_i_i75_i277_79_c_compstr2230_sel_x(BITSELECT,3689)@170
    assign i_conv_i_i_i_i_i75_i277_79_c_compstr2230_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_78_c_compstr2210_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_79_c_compstr2230_vt_select_15(BITSELECT,7657)@170
    assign i_conv_i_i_i_i_i75_i277_79_c_compstr2230_vt_select_15_b = i_conv_i_i_i_i_i75_i277_79_c_compstr2230_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_79_c_compstr2230_vt_join(BITJOIN,7656)@170
    assign i_conv_i_i_i_i_i75_i277_79_c_compstr2230_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_79_c_compstr2230_vt_select_15_b};

    // leftShiftStage0_uid24728_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x(MUX,24727)@170
    assign leftShiftStage0_uid24728_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24728_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_79_c_compstr2230_vt_join_q or leftShiftStage0Idx1_uid24726_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24728_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24728_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_79_c_compstr2230_vt_join_q;
            1'b1 : leftShiftStage0_uid24728_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24726_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24728_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24733_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x(MUX,24732)@170
    assign leftShiftStage1_uid24733_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24733_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_s or leftShiftStage0_uid24728_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24731_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24733_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24733_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q = leftShiftStage0_uid24728_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24733_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24731_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24733_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24738_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x(MUX,24737)@170
    assign leftShiftStage2_uid24738_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24738_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_s or leftShiftStage1_uid24733_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24736_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24738_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24738_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q = leftShiftStage1_uid24733_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24738_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24736_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24738_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_79_c_compstr2231_vt_select_28(BITSELECT,9352)@170
    assign i_shl_i_i_i_i_i77_i_79_c_compstr2231_vt_select_28_b = leftShiftStage2_uid24738_i_shl_i_i_i_i_i77_i_79_c_compstr0_shift_x_q[28:13];

    // redist406_i_shl_i_i_i_i_i77_i_79_c_compstr2231_vt_select_28_b_1(DELAY,28634)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist406_i_shl_i_i_i_i_i77_i_79_c_compstr2231_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_79_c_compstr2231_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_79_c_compstr2231_vt_join(BITJOIN,9351)@171
    assign i_shl_i_i_i_i_i77_i_79_c_compstr2231_vt_join_q = {redist406_i_shl_i_i_i_i_i77_i_79_c_compstr2231_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma(CHAINMULTADD,28202)@165 + 5
    // out q@171
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ah[0] <= redist929_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_159_tpl_157_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ah[1] <= redist928_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_158_tpl_157_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ch[0] <= redist675_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_159_tpl_157_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ch[1] <= redist674_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_158_tpl_157_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232(ADD,8498)@171
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compstr2227_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compstr2229_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compstr2228_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_79_c_compstr2231_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_79_c_compstr2231_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_o[33:0];

    // rightShiftStage0_uid19836_dupName_315_i_unnamed_c_compstr0_shift_x(MUX,19835)@171
    assign rightShiftStage0_uid19836_dupName_315_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19836_dupName_315_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_q or rightShiftStage0Idx1_uid19834_dupName_315_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19836_dupName_315_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19836_dupName_315_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_q;
            1'b1 : rightShiftStage0_uid19836_dupName_315_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19834_dupName_315_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19836_dupName_315_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19841_dupName_315_i_unnamed_c_compstr0_shift_x(MUX,19840)@171
    assign rightShiftStage1_uid19841_dupName_315_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19841_dupName_315_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19836_dupName_315_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19839_dupName_315_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19841_dupName_315_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19841_dupName_315_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19836_dupName_315_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19841_dupName_315_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19839_dupName_315_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19841_dupName_315_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19846_dupName_315_i_unnamed_c_compstr0_shift_x(MUX,19845)@171
    assign rightShiftStage2_uid19846_dupName_315_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19846_dupName_315_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19841_dupName_315_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19844_dupName_315_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19846_dupName_315_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19846_dupName_315_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19841_dupName_315_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19846_dupName_315_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19844_dupName_315_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19846_dupName_315_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2233_vt_select_20(BITSELECT,10872)@171
    assign i_unnamed_c_compstr2233_vt_select_20_b = rightShiftStage2_uid19846_dupName_315_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2233_vt_join(BITJOIN,10871)@171
    assign i_unnamed_c_compstr2233_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2233_vt_select_20_b};

    // i_conv_i_i_i_i97_i_79_c_compstr2234_sel_x(BITSELECT,3560)@171
    assign i_conv_i_i_i_i97_i_79_c_compstr2234_sel_x_b = i_unnamed_c_compstr2233_vt_join_q[15:0];

    // redist1176_i_conv_i_i_i_i97_i_79_c_compstr2234_sel_x_b_1(DELAY,29404)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1176_i_conv_i_i_i_i97_i_79_c_compstr2234_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_79_c_compstr2234_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19855_dupName_316_i_unnamed_c_compstr0_shift_x(BITSELECT,19854)@171
    assign rightShiftStage1Idx1Rng8_uid19855_dupName_316_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19854_dupName_316_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19857_dupName_316_i_unnamed_c_compstr0_shift_x(BITJOIN,19856)@171
    assign rightShiftStage1Idx1_uid19857_dupName_316_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19855_dupName_316_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19850_dupName_316_i_unnamed_c_compstr0_shift_x(BITSELECT,19849)@171
    assign rightShiftStage0Idx1Rng4_uid19850_dupName_316_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_q[33:4];

    // rightShiftStage0Idx1_uid19852_dupName_316_i_unnamed_c_compstr0_shift_x(BITJOIN,19851)@171
    assign rightShiftStage0Idx1_uid19852_dupName_316_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19850_dupName_316_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19854_dupName_316_i_unnamed_c_compstr0_shift_x(MUX,19853)@171
    assign rightShiftStage0_uid19854_dupName_316_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19854_dupName_316_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_q or rightShiftStage0Idx1_uid19852_dupName_316_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19854_dupName_316_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19854_dupName_316_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compstr2232_q;
            1'b1 : rightShiftStage0_uid19854_dupName_316_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19852_dupName_316_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19854_dupName_316_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19859_dupName_316_i_unnamed_c_compstr0_shift_x(MUX,19858)@171
    assign rightShiftStage1_uid19859_dupName_316_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19859_dupName_316_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19854_dupName_316_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19857_dupName_316_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19859_dupName_316_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19859_dupName_316_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19854_dupName_316_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19859_dupName_316_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19857_dupName_316_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19859_dupName_316_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2235_vt_select_21(BITSELECT,10875)@171
    assign i_unnamed_c_compstr2235_vt_select_21_b = rightShiftStage1_uid19859_dupName_316_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2235_vt_join(BITJOIN,10874)@171
    assign i_unnamed_c_compstr2235_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2235_vt_select_21_b};

    // i_unnamed_c_compstr2236_sel_x(BITSELECT,6132)@171
    assign i_unnamed_c_compstr2236_sel_x_b = i_unnamed_c_compstr2235_vt_join_q[15:0];

    // i_unnamed_c_compstr2237_BitSelect_for_a(BITSELECT,27653)@171
    assign i_unnamed_c_compstr2237_BitSelect_for_a_b = i_unnamed_c_compstr2236_sel_x_b[0:0];

    // i_unnamed_c_compstr2237_join(BITJOIN,27654)@171
    assign i_unnamed_c_compstr2237_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2237_BitSelect_for_a_b};

    // i_unnamed_c_compstr2237_vt_select_0(BITSELECT,10880)@171
    assign i_unnamed_c_compstr2237_vt_select_0_b = i_unnamed_c_compstr2237_join_q[0:0];

    // redist158_i_unnamed_c_compstr2237_vt_select_0_b_1(DELAY,28386)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist158_i_unnamed_c_compstr2237_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2237_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2237_vt_join(BITJOIN,10879)@172
    assign i_unnamed_c_compstr2237_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist158_i_unnamed_c_compstr2237_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_79_c_compstr2238(ADD,6955)@172
    assign i_add_i_i_i_i_i126_i_79_c_compstr2238_a = {1'b0, i_unnamed_c_compstr2237_vt_join_q};
    assign i_add_i_i_i_i_i126_i_79_c_compstr2238_b = {1'b0, redist1176_i_conv_i_i_i_i97_i_79_c_compstr2234_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_79_c_compstr2238_o = $unsigned(i_add_i_i_i_i_i126_i_79_c_compstr2238_a) + $unsigned(i_add_i_i_i_i_i126_i_79_c_compstr2238_b);
    assign i_add_i_i_i_i_i126_i_79_c_compstr2238_q = i_add_i_i_i_i_i126_i_79_c_compstr2238_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_79_c_compstr2238_sel_x(BITSELECT,2149)@172
    assign bgTrunc_i_add_i_i_i_i_i126_i_79_c_compstr2238_sel_x_b = i_add_i_i_i_i_i126_i_79_c_compstr2238_q[15:0];

    // i_conv_i_i_i_i_i75_i277_80_c_compstr2258_sel_x(BITSELECT,3691)@172
    assign i_conv_i_i_i_i_i75_i277_80_c_compstr2258_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_79_c_compstr2238_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_80_c_compstr2258_vt_select_15(BITSELECT,7665)@172
    assign i_conv_i_i_i_i_i75_i277_80_c_compstr2258_vt_select_15_b = i_conv_i_i_i_i_i75_i277_80_c_compstr2258_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_80_c_compstr2258_vt_join(BITJOIN,7664)@172
    assign i_conv_i_i_i_i_i75_i277_80_c_compstr2258_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_80_c_compstr2258_vt_select_15_b};

    // leftShiftStage0_uid24764_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x(MUX,24763)@172
    assign leftShiftStage0_uid24764_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24764_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_80_c_compstr2258_vt_join_q or leftShiftStage0Idx1_uid24762_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24764_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24764_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_80_c_compstr2258_vt_join_q;
            1'b1 : leftShiftStage0_uid24764_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24762_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24764_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24769_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x(MUX,24768)@172
    assign leftShiftStage1_uid24769_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24769_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_s or leftShiftStage0_uid24764_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24767_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24769_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24769_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q = leftShiftStage0_uid24764_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24769_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24767_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24769_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24774_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x(MUX,24773)@172
    assign leftShiftStage2_uid24774_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24774_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_s or leftShiftStage1_uid24769_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24772_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24774_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24774_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q = leftShiftStage1_uid24769_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24774_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24772_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24774_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_80_c_compstr2259_vt_select_28(BITSELECT,9358)@172
    assign i_shl_i_i_i_i_i77_i_80_c_compstr2259_vt_select_28_b = leftShiftStage2_uid24774_i_shl_i_i_i_i_i77_i_80_c_compstr0_shift_x_q[28:13];

    // redist404_i_shl_i_i_i_i_i77_i_80_c_compstr2259_vt_select_28_b_1(DELAY,28632)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist404_i_shl_i_i_i_i_i77_i_80_c_compstr2259_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_80_c_compstr2259_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_80_c_compstr2259_vt_join(BITJOIN,9357)@173
    assign i_shl_i_i_i_i_i77_i_80_c_compstr2259_vt_join_q = {redist404_i_shl_i_i_i_i_i77_i_80_c_compstr2259_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma(CHAINMULTADD,28204)@167 + 5
    // out q@173
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ah[0] <= redist931_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_161_tpl_159_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ah[1] <= redist930_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_160_tpl_159_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ch[0] <= redist677_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_161_tpl_159_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ch[1] <= redist676_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_160_tpl_159_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260(ADD,8500)@173
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compstr2255_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compstr2257_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compstr2256_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_80_c_compstr2259_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_80_c_compstr2259_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_o[33:0];

    // rightShiftStage0_uid19898_dupName_319_i_unnamed_c_compstr0_shift_x(MUX,19897)@173
    assign rightShiftStage0_uid19898_dupName_319_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19898_dupName_319_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_q or rightShiftStage0Idx1_uid19896_dupName_319_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19898_dupName_319_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19898_dupName_319_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_q;
            1'b1 : rightShiftStage0_uid19898_dupName_319_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19896_dupName_319_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19898_dupName_319_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19903_dupName_319_i_unnamed_c_compstr0_shift_x(MUX,19902)@173
    assign rightShiftStage1_uid19903_dupName_319_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19903_dupName_319_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19898_dupName_319_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19901_dupName_319_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19903_dupName_319_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19903_dupName_319_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19898_dupName_319_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19903_dupName_319_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19901_dupName_319_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19903_dupName_319_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19908_dupName_319_i_unnamed_c_compstr0_shift_x(MUX,19907)@173
    assign rightShiftStage2_uid19908_dupName_319_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19908_dupName_319_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19903_dupName_319_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19906_dupName_319_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19908_dupName_319_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19908_dupName_319_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19903_dupName_319_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19908_dupName_319_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19906_dupName_319_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19908_dupName_319_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2261_vt_select_20(BITSELECT,10894)@173
    assign i_unnamed_c_compstr2261_vt_select_20_b = rightShiftStage2_uid19908_dupName_319_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2261_vt_join(BITJOIN,10893)@173
    assign i_unnamed_c_compstr2261_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2261_vt_select_20_b};

    // i_conv_i_i_i_i97_i_80_c_compstr2262_sel_x(BITSELECT,3562)@173
    assign i_conv_i_i_i_i97_i_80_c_compstr2262_sel_x_b = i_unnamed_c_compstr2261_vt_join_q[15:0];

    // redist1174_i_conv_i_i_i_i97_i_80_c_compstr2262_sel_x_b_1(DELAY,29402)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1174_i_conv_i_i_i_i97_i_80_c_compstr2262_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_80_c_compstr2262_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19917_dupName_320_i_unnamed_c_compstr0_shift_x(BITSELECT,19916)@173
    assign rightShiftStage1Idx1Rng8_uid19917_dupName_320_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19916_dupName_320_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19919_dupName_320_i_unnamed_c_compstr0_shift_x(BITJOIN,19918)@173
    assign rightShiftStage1Idx1_uid19919_dupName_320_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19917_dupName_320_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19912_dupName_320_i_unnamed_c_compstr0_shift_x(BITSELECT,19911)@173
    assign rightShiftStage0Idx1Rng4_uid19912_dupName_320_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_q[33:4];

    // rightShiftStage0Idx1_uid19914_dupName_320_i_unnamed_c_compstr0_shift_x(BITJOIN,19913)@173
    assign rightShiftStage0Idx1_uid19914_dupName_320_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19912_dupName_320_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19916_dupName_320_i_unnamed_c_compstr0_shift_x(MUX,19915)@173
    assign rightShiftStage0_uid19916_dupName_320_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19916_dupName_320_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_q or rightShiftStage0Idx1_uid19914_dupName_320_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19916_dupName_320_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19916_dupName_320_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compstr2260_q;
            1'b1 : rightShiftStage0_uid19916_dupName_320_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19914_dupName_320_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19916_dupName_320_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19921_dupName_320_i_unnamed_c_compstr0_shift_x(MUX,19920)@173
    assign rightShiftStage1_uid19921_dupName_320_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19921_dupName_320_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19916_dupName_320_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19919_dupName_320_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19921_dupName_320_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19921_dupName_320_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19916_dupName_320_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19921_dupName_320_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19919_dupName_320_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19921_dupName_320_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2263_vt_select_21(BITSELECT,10897)@173
    assign i_unnamed_c_compstr2263_vt_select_21_b = rightShiftStage1_uid19921_dupName_320_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2263_vt_join(BITJOIN,10896)@173
    assign i_unnamed_c_compstr2263_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2263_vt_select_21_b};

    // i_unnamed_c_compstr2264_sel_x(BITSELECT,6134)@173
    assign i_unnamed_c_compstr2264_sel_x_b = i_unnamed_c_compstr2263_vt_join_q[15:0];

    // i_unnamed_c_compstr2265_BitSelect_for_a(BITSELECT,27657)@173
    assign i_unnamed_c_compstr2265_BitSelect_for_a_b = i_unnamed_c_compstr2264_sel_x_b[0:0];

    // i_unnamed_c_compstr2265_join(BITJOIN,27658)@173
    assign i_unnamed_c_compstr2265_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2265_BitSelect_for_a_b};

    // i_unnamed_c_compstr2265_vt_select_0(BITSELECT,10902)@173
    assign i_unnamed_c_compstr2265_vt_select_0_b = i_unnamed_c_compstr2265_join_q[0:0];

    // redist156_i_unnamed_c_compstr2265_vt_select_0_b_1(DELAY,28384)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist156_i_unnamed_c_compstr2265_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2265_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2265_vt_join(BITJOIN,10901)@174
    assign i_unnamed_c_compstr2265_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist156_i_unnamed_c_compstr2265_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_80_c_compstr2266(ADD,6957)@174
    assign i_add_i_i_i_i_i126_i_80_c_compstr2266_a = {1'b0, i_unnamed_c_compstr2265_vt_join_q};
    assign i_add_i_i_i_i_i126_i_80_c_compstr2266_b = {1'b0, redist1174_i_conv_i_i_i_i97_i_80_c_compstr2262_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_80_c_compstr2266_o = $unsigned(i_add_i_i_i_i_i126_i_80_c_compstr2266_a) + $unsigned(i_add_i_i_i_i_i126_i_80_c_compstr2266_b);
    assign i_add_i_i_i_i_i126_i_80_c_compstr2266_q = i_add_i_i_i_i_i126_i_80_c_compstr2266_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_80_c_compstr2266_sel_x(BITSELECT,2151)@174
    assign bgTrunc_i_add_i_i_i_i_i126_i_80_c_compstr2266_sel_x_b = i_add_i_i_i_i_i126_i_80_c_compstr2266_q[15:0];

    // i_conv_i_i_i_i_i75_i277_81_c_compstr2286_sel_x(BITSELECT,3692)@174
    assign i_conv_i_i_i_i_i75_i277_81_c_compstr2286_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_80_c_compstr2266_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_81_c_compstr2286_vt_select_15(BITSELECT,7669)@174
    assign i_conv_i_i_i_i_i75_i277_81_c_compstr2286_vt_select_15_b = i_conv_i_i_i_i_i75_i277_81_c_compstr2286_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_81_c_compstr2286_vt_join(BITJOIN,7668)@174
    assign i_conv_i_i_i_i_i75_i277_81_c_compstr2286_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_81_c_compstr2286_vt_select_15_b};

    // leftShiftStage0_uid24782_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x(MUX,24781)@174
    assign leftShiftStage0_uid24782_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24782_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_81_c_compstr2286_vt_join_q or leftShiftStage0Idx1_uid24780_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24782_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24782_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_81_c_compstr2286_vt_join_q;
            1'b1 : leftShiftStage0_uid24782_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24780_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24782_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24787_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x(MUX,24786)@174
    assign leftShiftStage1_uid24787_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24787_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_s or leftShiftStage0_uid24782_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24785_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24787_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24787_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q = leftShiftStage0_uid24782_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24787_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24785_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24787_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24792_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x(MUX,24791)@174
    assign leftShiftStage2_uid24792_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24792_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_s or leftShiftStage1_uid24787_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24790_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24792_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24792_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q = leftShiftStage1_uid24787_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24792_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24790_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24792_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_81_c_compstr2287_vt_select_28(BITSELECT,9361)@174
    assign i_shl_i_i_i_i_i77_i_81_c_compstr2287_vt_select_28_b = leftShiftStage2_uid24792_i_shl_i_i_i_i_i77_i_81_c_compstr0_shift_x_q[28:13];

    // redist403_i_shl_i_i_i_i_i77_i_81_c_compstr2287_vt_select_28_b_1(DELAY,28631)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist403_i_shl_i_i_i_i_i77_i_81_c_compstr2287_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_81_c_compstr2287_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_81_c_compstr2287_vt_join(BITJOIN,9360)@175
    assign i_shl_i_i_i_i_i77_i_81_c_compstr2287_vt_join_q = {redist403_i_shl_i_i_i_i_i77_i_81_c_compstr2287_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma(CHAINMULTADD,28205)@169 + 5
    // out q@175
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ah[0] <= redist933_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_163_tpl_161_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ah[1] <= redist932_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_162_tpl_161_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ch[0] <= redist679_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_163_tpl_161_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ch[1] <= redist678_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_162_tpl_161_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288(ADD,8501)@175
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compstr2283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compstr2285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compstr2284_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_81_c_compstr2287_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_81_c_compstr2287_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_o[33:0];

    // rightShiftStage0_uid19960_dupName_323_i_unnamed_c_compstr0_shift_x(MUX,19959)@175
    assign rightShiftStage0_uid19960_dupName_323_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19960_dupName_323_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_q or rightShiftStage0Idx1_uid19958_dupName_323_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19960_dupName_323_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19960_dupName_323_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_q;
            1'b1 : rightShiftStage0_uid19960_dupName_323_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19958_dupName_323_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19960_dupName_323_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19965_dupName_323_i_unnamed_c_compstr0_shift_x(MUX,19964)@175
    assign rightShiftStage1_uid19965_dupName_323_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19965_dupName_323_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19960_dupName_323_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19963_dupName_323_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19965_dupName_323_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19965_dupName_323_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19960_dupName_323_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19965_dupName_323_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19963_dupName_323_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19965_dupName_323_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19970_dupName_323_i_unnamed_c_compstr0_shift_x(MUX,19969)@175
    assign rightShiftStage2_uid19970_dupName_323_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19970_dupName_323_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid19965_dupName_323_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid19968_dupName_323_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19970_dupName_323_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid19970_dupName_323_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid19965_dupName_323_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid19970_dupName_323_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid19968_dupName_323_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid19970_dupName_323_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2289_vt_select_20(BITSELECT,10916)@175
    assign i_unnamed_c_compstr2289_vt_select_20_b = rightShiftStage2_uid19970_dupName_323_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2289_vt_join(BITJOIN,10915)@175
    assign i_unnamed_c_compstr2289_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2289_vt_select_20_b};

    // i_conv_i_i_i_i97_i_81_c_compstr2290_sel_x(BITSELECT,3563)@175
    assign i_conv_i_i_i_i97_i_81_c_compstr2290_sel_x_b = i_unnamed_c_compstr2289_vt_join_q[15:0];

    // redist1173_i_conv_i_i_i_i97_i_81_c_compstr2290_sel_x_b_1(DELAY,29401)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1173_i_conv_i_i_i_i97_i_81_c_compstr2290_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_81_c_compstr2290_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19979_dupName_324_i_unnamed_c_compstr0_shift_x(BITSELECT,19978)@175
    assign rightShiftStage1Idx1Rng8_uid19979_dupName_324_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid19978_dupName_324_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19981_dupName_324_i_unnamed_c_compstr0_shift_x(BITJOIN,19980)@175
    assign rightShiftStage1Idx1_uid19981_dupName_324_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid19979_dupName_324_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19974_dupName_324_i_unnamed_c_compstr0_shift_x(BITSELECT,19973)@175
    assign rightShiftStage0Idx1Rng4_uid19974_dupName_324_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_q[33:4];

    // rightShiftStage0Idx1_uid19976_dupName_324_i_unnamed_c_compstr0_shift_x(BITJOIN,19975)@175
    assign rightShiftStage0Idx1_uid19976_dupName_324_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid19974_dupName_324_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid19978_dupName_324_i_unnamed_c_compstr0_shift_x(MUX,19977)@175
    assign rightShiftStage0_uid19978_dupName_324_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19978_dupName_324_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_q or rightShiftStage0Idx1_uid19976_dupName_324_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19978_dupName_324_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid19978_dupName_324_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compstr2288_q;
            1'b1 : rightShiftStage0_uid19978_dupName_324_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid19976_dupName_324_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid19978_dupName_324_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19983_dupName_324_i_unnamed_c_compstr0_shift_x(MUX,19982)@175
    assign rightShiftStage1_uid19983_dupName_324_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19983_dupName_324_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid19978_dupName_324_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid19981_dupName_324_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19983_dupName_324_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid19983_dupName_324_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid19978_dupName_324_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid19983_dupName_324_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid19981_dupName_324_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid19983_dupName_324_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2291_vt_select_21(BITSELECT,10919)@175
    assign i_unnamed_c_compstr2291_vt_select_21_b = rightShiftStage1_uid19983_dupName_324_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2291_vt_join(BITJOIN,10918)@175
    assign i_unnamed_c_compstr2291_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2291_vt_select_21_b};

    // i_unnamed_c_compstr2292_sel_x(BITSELECT,6136)@175
    assign i_unnamed_c_compstr2292_sel_x_b = i_unnamed_c_compstr2291_vt_join_q[15:0];

    // i_unnamed_c_compstr2293_BitSelect_for_a(BITSELECT,27661)@175
    assign i_unnamed_c_compstr2293_BitSelect_for_a_b = i_unnamed_c_compstr2292_sel_x_b[0:0];

    // i_unnamed_c_compstr2293_join(BITJOIN,27662)@175
    assign i_unnamed_c_compstr2293_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2293_BitSelect_for_a_b};

    // i_unnamed_c_compstr2293_vt_select_0(BITSELECT,10924)@175
    assign i_unnamed_c_compstr2293_vt_select_0_b = i_unnamed_c_compstr2293_join_q[0:0];

    // redist154_i_unnamed_c_compstr2293_vt_select_0_b_1(DELAY,28382)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist154_i_unnamed_c_compstr2293_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2293_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2293_vt_join(BITJOIN,10923)@176
    assign i_unnamed_c_compstr2293_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist154_i_unnamed_c_compstr2293_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_81_c_compstr2294(ADD,6958)@176
    assign i_add_i_i_i_i_i126_i_81_c_compstr2294_a = {1'b0, i_unnamed_c_compstr2293_vt_join_q};
    assign i_add_i_i_i_i_i126_i_81_c_compstr2294_b = {1'b0, redist1173_i_conv_i_i_i_i97_i_81_c_compstr2290_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_81_c_compstr2294_o = $unsigned(i_add_i_i_i_i_i126_i_81_c_compstr2294_a) + $unsigned(i_add_i_i_i_i_i126_i_81_c_compstr2294_b);
    assign i_add_i_i_i_i_i126_i_81_c_compstr2294_q = i_add_i_i_i_i_i126_i_81_c_compstr2294_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_81_c_compstr2294_sel_x(BITSELECT,2152)@176
    assign bgTrunc_i_add_i_i_i_i_i126_i_81_c_compstr2294_sel_x_b = i_add_i_i_i_i_i126_i_81_c_compstr2294_q[15:0];

    // i_conv_i_i_i_i_i75_i277_82_c_compstr2314_sel_x(BITSELECT,3693)@176
    assign i_conv_i_i_i_i_i75_i277_82_c_compstr2314_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_81_c_compstr2294_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_82_c_compstr2314_vt_select_15(BITSELECT,7673)@176
    assign i_conv_i_i_i_i_i75_i277_82_c_compstr2314_vt_select_15_b = i_conv_i_i_i_i_i75_i277_82_c_compstr2314_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_82_c_compstr2314_vt_join(BITJOIN,7672)@176
    assign i_conv_i_i_i_i_i75_i277_82_c_compstr2314_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_82_c_compstr2314_vt_select_15_b};

    // leftShiftStage0_uid24800_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x(MUX,24799)@176
    assign leftShiftStage0_uid24800_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24800_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_82_c_compstr2314_vt_join_q or leftShiftStage0Idx1_uid24798_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24800_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24800_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_82_c_compstr2314_vt_join_q;
            1'b1 : leftShiftStage0_uid24800_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24798_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24800_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24805_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x(MUX,24804)@176
    assign leftShiftStage1_uid24805_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24805_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_s or leftShiftStage0_uid24800_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24803_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24805_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24805_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q = leftShiftStage0_uid24800_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24805_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24803_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24805_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24810_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x(MUX,24809)@176
    assign leftShiftStage2_uid24810_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24810_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_s or leftShiftStage1_uid24805_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24808_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24810_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24810_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q = leftShiftStage1_uid24805_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24810_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24808_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24810_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_82_c_compstr2315_vt_select_28(BITSELECT,9364)@176
    assign i_shl_i_i_i_i_i77_i_82_c_compstr2315_vt_select_28_b = leftShiftStage2_uid24810_i_shl_i_i_i_i_i77_i_82_c_compstr0_shift_x_q[28:13];

    // redist402_i_shl_i_i_i_i_i77_i_82_c_compstr2315_vt_select_28_b_1(DELAY,28630)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist402_i_shl_i_i_i_i_i77_i_82_c_compstr2315_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_82_c_compstr2315_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_82_c_compstr2315_vt_join(BITJOIN,9363)@177
    assign i_shl_i_i_i_i_i77_i_82_c_compstr2315_vt_join_q = {redist402_i_shl_i_i_i_i_i77_i_82_c_compstr2315_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma(CHAINMULTADD,28206)@171 + 5
    // out q@177
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ah[0] <= redist935_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_165_tpl_163_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ah[1] <= redist934_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_164_tpl_163_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ch[0] <= redist681_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_165_tpl_163_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ch[1] <= redist680_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_164_tpl_163_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316(ADD,8502)@177
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compstr2311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compstr2313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compstr2312_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_82_c_compstr2315_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_82_c_compstr2315_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_o[33:0];

    // rightShiftStage0_uid20022_dupName_327_i_unnamed_c_compstr0_shift_x(MUX,20021)@177
    assign rightShiftStage0_uid20022_dupName_327_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20022_dupName_327_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_q or rightShiftStage0Idx1_uid20020_dupName_327_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20022_dupName_327_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20022_dupName_327_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_q;
            1'b1 : rightShiftStage0_uid20022_dupName_327_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20020_dupName_327_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20022_dupName_327_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20027_dupName_327_i_unnamed_c_compstr0_shift_x(MUX,20026)@177
    assign rightShiftStage1_uid20027_dupName_327_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20027_dupName_327_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20022_dupName_327_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20025_dupName_327_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20027_dupName_327_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20027_dupName_327_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20022_dupName_327_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20027_dupName_327_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20025_dupName_327_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20027_dupName_327_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20032_dupName_327_i_unnamed_c_compstr0_shift_x(MUX,20031)@177
    assign rightShiftStage2_uid20032_dupName_327_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20032_dupName_327_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20027_dupName_327_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20030_dupName_327_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20032_dupName_327_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20032_dupName_327_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20027_dupName_327_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20032_dupName_327_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20030_dupName_327_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20032_dupName_327_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2317_vt_select_20(BITSELECT,10938)@177
    assign i_unnamed_c_compstr2317_vt_select_20_b = rightShiftStage2_uid20032_dupName_327_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2317_vt_join(BITJOIN,10937)@177
    assign i_unnamed_c_compstr2317_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2317_vt_select_20_b};

    // i_conv_i_i_i_i97_i_82_c_compstr2318_sel_x(BITSELECT,3564)@177
    assign i_conv_i_i_i_i97_i_82_c_compstr2318_sel_x_b = i_unnamed_c_compstr2317_vt_join_q[15:0];

    // redist1172_i_conv_i_i_i_i97_i_82_c_compstr2318_sel_x_b_1(DELAY,29400)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1172_i_conv_i_i_i_i97_i_82_c_compstr2318_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_82_c_compstr2318_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20041_dupName_328_i_unnamed_c_compstr0_shift_x(BITSELECT,20040)@177
    assign rightShiftStage1Idx1Rng8_uid20041_dupName_328_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20040_dupName_328_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20043_dupName_328_i_unnamed_c_compstr0_shift_x(BITJOIN,20042)@177
    assign rightShiftStage1Idx1_uid20043_dupName_328_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20041_dupName_328_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20036_dupName_328_i_unnamed_c_compstr0_shift_x(BITSELECT,20035)@177
    assign rightShiftStage0Idx1Rng4_uid20036_dupName_328_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_q[33:4];

    // rightShiftStage0Idx1_uid20038_dupName_328_i_unnamed_c_compstr0_shift_x(BITJOIN,20037)@177
    assign rightShiftStage0Idx1_uid20038_dupName_328_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20036_dupName_328_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20040_dupName_328_i_unnamed_c_compstr0_shift_x(MUX,20039)@177
    assign rightShiftStage0_uid20040_dupName_328_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20040_dupName_328_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_q or rightShiftStage0Idx1_uid20038_dupName_328_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20040_dupName_328_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20040_dupName_328_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compstr2316_q;
            1'b1 : rightShiftStage0_uid20040_dupName_328_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20038_dupName_328_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20040_dupName_328_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20045_dupName_328_i_unnamed_c_compstr0_shift_x(MUX,20044)@177
    assign rightShiftStage1_uid20045_dupName_328_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20045_dupName_328_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20040_dupName_328_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20043_dupName_328_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20045_dupName_328_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20045_dupName_328_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20040_dupName_328_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20045_dupName_328_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20043_dupName_328_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20045_dupName_328_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2319_vt_select_21(BITSELECT,10941)@177
    assign i_unnamed_c_compstr2319_vt_select_21_b = rightShiftStage1_uid20045_dupName_328_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2319_vt_join(BITJOIN,10940)@177
    assign i_unnamed_c_compstr2319_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2319_vt_select_21_b};

    // i_unnamed_c_compstr2320_sel_x(BITSELECT,6138)@177
    assign i_unnamed_c_compstr2320_sel_x_b = i_unnamed_c_compstr2319_vt_join_q[15:0];

    // i_unnamed_c_compstr2321_BitSelect_for_a(BITSELECT,27665)@177
    assign i_unnamed_c_compstr2321_BitSelect_for_a_b = i_unnamed_c_compstr2320_sel_x_b[0:0];

    // i_unnamed_c_compstr2321_join(BITJOIN,27666)@177
    assign i_unnamed_c_compstr2321_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2321_BitSelect_for_a_b};

    // i_unnamed_c_compstr2321_vt_select_0(BITSELECT,10946)@177
    assign i_unnamed_c_compstr2321_vt_select_0_b = i_unnamed_c_compstr2321_join_q[0:0];

    // redist152_i_unnamed_c_compstr2321_vt_select_0_b_1(DELAY,28380)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist152_i_unnamed_c_compstr2321_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2321_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2321_vt_join(BITJOIN,10945)@178
    assign i_unnamed_c_compstr2321_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist152_i_unnamed_c_compstr2321_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_82_c_compstr2322(ADD,6959)@178
    assign i_add_i_i_i_i_i126_i_82_c_compstr2322_a = {1'b0, i_unnamed_c_compstr2321_vt_join_q};
    assign i_add_i_i_i_i_i126_i_82_c_compstr2322_b = {1'b0, redist1172_i_conv_i_i_i_i97_i_82_c_compstr2318_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_82_c_compstr2322_o = $unsigned(i_add_i_i_i_i_i126_i_82_c_compstr2322_a) + $unsigned(i_add_i_i_i_i_i126_i_82_c_compstr2322_b);
    assign i_add_i_i_i_i_i126_i_82_c_compstr2322_q = i_add_i_i_i_i_i126_i_82_c_compstr2322_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_82_c_compstr2322_sel_x(BITSELECT,2153)@178
    assign bgTrunc_i_add_i_i_i_i_i126_i_82_c_compstr2322_sel_x_b = i_add_i_i_i_i_i126_i_82_c_compstr2322_q[15:0];

    // i_conv_i_i_i_i_i75_i277_83_c_compstr2342_sel_x(BITSELECT,3694)@178
    assign i_conv_i_i_i_i_i75_i277_83_c_compstr2342_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_82_c_compstr2322_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_83_c_compstr2342_vt_select_15(BITSELECT,7677)@178
    assign i_conv_i_i_i_i_i75_i277_83_c_compstr2342_vt_select_15_b = i_conv_i_i_i_i_i75_i277_83_c_compstr2342_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_83_c_compstr2342_vt_join(BITJOIN,7676)@178
    assign i_conv_i_i_i_i_i75_i277_83_c_compstr2342_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_83_c_compstr2342_vt_select_15_b};

    // leftShiftStage0_uid24818_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x(MUX,24817)@178
    assign leftShiftStage0_uid24818_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24818_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_83_c_compstr2342_vt_join_q or leftShiftStage0Idx1_uid24816_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24818_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24818_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_83_c_compstr2342_vt_join_q;
            1'b1 : leftShiftStage0_uid24818_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24816_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24818_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24823_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x(MUX,24822)@178
    assign leftShiftStage1_uid24823_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24823_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_s or leftShiftStage0_uid24818_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24821_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24823_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24823_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q = leftShiftStage0_uid24818_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24823_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24821_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24823_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24828_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x(MUX,24827)@178
    assign leftShiftStage2_uid24828_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24828_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_s or leftShiftStage1_uid24823_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24826_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24828_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24828_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q = leftShiftStage1_uid24823_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24828_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24826_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24828_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_83_c_compstr2343_vt_select_28(BITSELECT,9367)@178
    assign i_shl_i_i_i_i_i77_i_83_c_compstr2343_vt_select_28_b = leftShiftStage2_uid24828_i_shl_i_i_i_i_i77_i_83_c_compstr0_shift_x_q[28:13];

    // redist401_i_shl_i_i_i_i_i77_i_83_c_compstr2343_vt_select_28_b_1(DELAY,28629)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist401_i_shl_i_i_i_i_i77_i_83_c_compstr2343_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_83_c_compstr2343_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_83_c_compstr2343_vt_join(BITJOIN,9366)@179
    assign i_shl_i_i_i_i_i77_i_83_c_compstr2343_vt_join_q = {redist401_i_shl_i_i_i_i_i77_i_83_c_compstr2343_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma(CHAINMULTADD,28207)@173 + 5
    // out q@179
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ah[0] <= redist937_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_167_tpl_165_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ah[1] <= redist936_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_166_tpl_165_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ch[0] <= redist683_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_167_tpl_165_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ch[1] <= redist682_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_166_tpl_165_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344(ADD,8503)@179
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compstr2339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compstr2341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compstr2340_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_83_c_compstr2343_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_83_c_compstr2343_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_o[33:0];

    // rightShiftStage0_uid20084_dupName_331_i_unnamed_c_compstr0_shift_x(MUX,20083)@179
    assign rightShiftStage0_uid20084_dupName_331_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20084_dupName_331_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_q or rightShiftStage0Idx1_uid20082_dupName_331_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20084_dupName_331_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20084_dupName_331_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_q;
            1'b1 : rightShiftStage0_uid20084_dupName_331_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20082_dupName_331_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20084_dupName_331_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20089_dupName_331_i_unnamed_c_compstr0_shift_x(MUX,20088)@179
    assign rightShiftStage1_uid20089_dupName_331_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20089_dupName_331_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20084_dupName_331_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20087_dupName_331_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20089_dupName_331_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20089_dupName_331_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20084_dupName_331_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20089_dupName_331_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20087_dupName_331_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20089_dupName_331_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20094_dupName_331_i_unnamed_c_compstr0_shift_x(MUX,20093)@179
    assign rightShiftStage2_uid20094_dupName_331_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20094_dupName_331_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20089_dupName_331_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20092_dupName_331_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20094_dupName_331_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20094_dupName_331_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20089_dupName_331_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20094_dupName_331_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20092_dupName_331_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20094_dupName_331_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2345_vt_select_20(BITSELECT,10963)@179
    assign i_unnamed_c_compstr2345_vt_select_20_b = rightShiftStage2_uid20094_dupName_331_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2345_vt_join(BITJOIN,10962)@179
    assign i_unnamed_c_compstr2345_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2345_vt_select_20_b};

    // i_conv_i_i_i_i97_i_83_c_compstr2346_sel_x(BITSELECT,3565)@179
    assign i_conv_i_i_i_i97_i_83_c_compstr2346_sel_x_b = i_unnamed_c_compstr2345_vt_join_q[15:0];

    // redist1171_i_conv_i_i_i_i97_i_83_c_compstr2346_sel_x_b_1(DELAY,29399)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1171_i_conv_i_i_i_i97_i_83_c_compstr2346_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_83_c_compstr2346_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20103_dupName_332_i_unnamed_c_compstr0_shift_x(BITSELECT,20102)@179
    assign rightShiftStage1Idx1Rng8_uid20103_dupName_332_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20102_dupName_332_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20105_dupName_332_i_unnamed_c_compstr0_shift_x(BITJOIN,20104)@179
    assign rightShiftStage1Idx1_uid20105_dupName_332_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20103_dupName_332_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20098_dupName_332_i_unnamed_c_compstr0_shift_x(BITSELECT,20097)@179
    assign rightShiftStage0Idx1Rng4_uid20098_dupName_332_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_q[33:4];

    // rightShiftStage0Idx1_uid20100_dupName_332_i_unnamed_c_compstr0_shift_x(BITJOIN,20099)@179
    assign rightShiftStage0Idx1_uid20100_dupName_332_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20098_dupName_332_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20102_dupName_332_i_unnamed_c_compstr0_shift_x(MUX,20101)@179
    assign rightShiftStage0_uid20102_dupName_332_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20102_dupName_332_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_q or rightShiftStage0Idx1_uid20100_dupName_332_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20102_dupName_332_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20102_dupName_332_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compstr2344_q;
            1'b1 : rightShiftStage0_uid20102_dupName_332_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20100_dupName_332_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20102_dupName_332_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20107_dupName_332_i_unnamed_c_compstr0_shift_x(MUX,20106)@179
    assign rightShiftStage1_uid20107_dupName_332_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20107_dupName_332_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20102_dupName_332_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20105_dupName_332_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20107_dupName_332_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20107_dupName_332_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20102_dupName_332_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20107_dupName_332_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20105_dupName_332_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20107_dupName_332_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2347_vt_select_21(BITSELECT,10966)@179
    assign i_unnamed_c_compstr2347_vt_select_21_b = rightShiftStage1_uid20107_dupName_332_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2347_vt_join(BITJOIN,10965)@179
    assign i_unnamed_c_compstr2347_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2347_vt_select_21_b};

    // i_unnamed_c_compstr2348_sel_x(BITSELECT,6140)@179
    assign i_unnamed_c_compstr2348_sel_x_b = i_unnamed_c_compstr2347_vt_join_q[15:0];

    // i_unnamed_c_compstr2349_BitSelect_for_a(BITSELECT,27669)@179
    assign i_unnamed_c_compstr2349_BitSelect_for_a_b = i_unnamed_c_compstr2348_sel_x_b[0:0];

    // i_unnamed_c_compstr2349_join(BITJOIN,27670)@179
    assign i_unnamed_c_compstr2349_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2349_BitSelect_for_a_b};

    // i_unnamed_c_compstr2349_vt_select_0(BITSELECT,10971)@179
    assign i_unnamed_c_compstr2349_vt_select_0_b = i_unnamed_c_compstr2349_join_q[0:0];

    // redist150_i_unnamed_c_compstr2349_vt_select_0_b_1(DELAY,28378)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist150_i_unnamed_c_compstr2349_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2349_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2349_vt_join(BITJOIN,10970)@180
    assign i_unnamed_c_compstr2349_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist150_i_unnamed_c_compstr2349_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_83_c_compstr2350(ADD,6960)@180
    assign i_add_i_i_i_i_i126_i_83_c_compstr2350_a = {1'b0, i_unnamed_c_compstr2349_vt_join_q};
    assign i_add_i_i_i_i_i126_i_83_c_compstr2350_b = {1'b0, redist1171_i_conv_i_i_i_i97_i_83_c_compstr2346_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_83_c_compstr2350_o = $unsigned(i_add_i_i_i_i_i126_i_83_c_compstr2350_a) + $unsigned(i_add_i_i_i_i_i126_i_83_c_compstr2350_b);
    assign i_add_i_i_i_i_i126_i_83_c_compstr2350_q = i_add_i_i_i_i_i126_i_83_c_compstr2350_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_83_c_compstr2350_sel_x(BITSELECT,2154)@180
    assign bgTrunc_i_add_i_i_i_i_i126_i_83_c_compstr2350_sel_x_b = i_add_i_i_i_i_i126_i_83_c_compstr2350_q[15:0];

    // i_conv_i_i_i_i_i75_i277_84_c_compstr2370_sel_x(BITSELECT,3695)@180
    assign i_conv_i_i_i_i_i75_i277_84_c_compstr2370_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_83_c_compstr2350_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_84_c_compstr2370_vt_select_15(BITSELECT,7681)@180
    assign i_conv_i_i_i_i_i75_i277_84_c_compstr2370_vt_select_15_b = i_conv_i_i_i_i_i75_i277_84_c_compstr2370_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_84_c_compstr2370_vt_join(BITJOIN,7680)@180
    assign i_conv_i_i_i_i_i75_i277_84_c_compstr2370_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_84_c_compstr2370_vt_select_15_b};

    // leftShiftStage0_uid24836_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x(MUX,24835)@180
    assign leftShiftStage0_uid24836_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24836_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_84_c_compstr2370_vt_join_q or leftShiftStage0Idx1_uid24834_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24836_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24836_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_84_c_compstr2370_vt_join_q;
            1'b1 : leftShiftStage0_uid24836_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24834_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24836_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24841_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x(MUX,24840)@180
    assign leftShiftStage1_uid24841_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24841_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_s or leftShiftStage0_uid24836_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24839_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24841_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24841_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q = leftShiftStage0_uid24836_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24841_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24839_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24841_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24846_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x(MUX,24845)@180
    assign leftShiftStage2_uid24846_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24846_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_s or leftShiftStage1_uid24841_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24844_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24846_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24846_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q = leftShiftStage1_uid24841_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24846_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24844_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24846_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_84_c_compstr2371_vt_select_28(BITSELECT,9370)@180
    assign i_shl_i_i_i_i_i77_i_84_c_compstr2371_vt_select_28_b = leftShiftStage2_uid24846_i_shl_i_i_i_i_i77_i_84_c_compstr0_shift_x_q[28:13];

    // redist400_i_shl_i_i_i_i_i77_i_84_c_compstr2371_vt_select_28_b_1(DELAY,28628)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist400_i_shl_i_i_i_i_i77_i_84_c_compstr2371_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_84_c_compstr2371_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_84_c_compstr2371_vt_join(BITJOIN,9369)@181
    assign i_shl_i_i_i_i_i77_i_84_c_compstr2371_vt_join_q = {redist400_i_shl_i_i_i_i_i77_i_84_c_compstr2371_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma(CHAINMULTADD,28208)@175 + 5
    // out q@181
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ah[0] <= redist939_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_169_tpl_167_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ah[1] <= redist938_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_168_tpl_167_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ch[0] <= redist685_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_169_tpl_167_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ch[1] <= redist684_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_168_tpl_167_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372(ADD,8504)@181
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compstr2367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compstr2369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compstr2368_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_84_c_compstr2371_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_84_c_compstr2371_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_o[33:0];

    // rightShiftStage0_uid20146_dupName_335_i_unnamed_c_compstr0_shift_x(MUX,20145)@181
    assign rightShiftStage0_uid20146_dupName_335_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20146_dupName_335_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_q or rightShiftStage0Idx1_uid20144_dupName_335_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20146_dupName_335_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20146_dupName_335_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_q;
            1'b1 : rightShiftStage0_uid20146_dupName_335_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20144_dupName_335_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20146_dupName_335_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20151_dupName_335_i_unnamed_c_compstr0_shift_x(MUX,20150)@181
    assign rightShiftStage1_uid20151_dupName_335_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20151_dupName_335_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20146_dupName_335_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20149_dupName_335_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20151_dupName_335_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20151_dupName_335_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20146_dupName_335_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20151_dupName_335_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20149_dupName_335_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20151_dupName_335_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20156_dupName_335_i_unnamed_c_compstr0_shift_x(MUX,20155)@181
    assign rightShiftStage2_uid20156_dupName_335_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20156_dupName_335_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20151_dupName_335_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20154_dupName_335_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20156_dupName_335_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20156_dupName_335_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20151_dupName_335_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20156_dupName_335_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20154_dupName_335_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20156_dupName_335_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2373_vt_select_20(BITSELECT,10990)@181
    assign i_unnamed_c_compstr2373_vt_select_20_b = rightShiftStage2_uid20156_dupName_335_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2373_vt_join(BITJOIN,10989)@181
    assign i_unnamed_c_compstr2373_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2373_vt_select_20_b};

    // i_conv_i_i_i_i97_i_84_c_compstr2374_sel_x(BITSELECT,3566)@181
    assign i_conv_i_i_i_i97_i_84_c_compstr2374_sel_x_b = i_unnamed_c_compstr2373_vt_join_q[15:0];

    // redist1170_i_conv_i_i_i_i97_i_84_c_compstr2374_sel_x_b_1(DELAY,29398)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1170_i_conv_i_i_i_i97_i_84_c_compstr2374_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_84_c_compstr2374_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20165_dupName_336_i_unnamed_c_compstr0_shift_x(BITSELECT,20164)@181
    assign rightShiftStage1Idx1Rng8_uid20165_dupName_336_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20164_dupName_336_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20167_dupName_336_i_unnamed_c_compstr0_shift_x(BITJOIN,20166)@181
    assign rightShiftStage1Idx1_uid20167_dupName_336_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20165_dupName_336_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20160_dupName_336_i_unnamed_c_compstr0_shift_x(BITSELECT,20159)@181
    assign rightShiftStage0Idx1Rng4_uid20160_dupName_336_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_q[33:4];

    // rightShiftStage0Idx1_uid20162_dupName_336_i_unnamed_c_compstr0_shift_x(BITJOIN,20161)@181
    assign rightShiftStage0Idx1_uid20162_dupName_336_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20160_dupName_336_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20164_dupName_336_i_unnamed_c_compstr0_shift_x(MUX,20163)@181
    assign rightShiftStage0_uid20164_dupName_336_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20164_dupName_336_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_q or rightShiftStage0Idx1_uid20162_dupName_336_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20164_dupName_336_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20164_dupName_336_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compstr2372_q;
            1'b1 : rightShiftStage0_uid20164_dupName_336_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20162_dupName_336_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20164_dupName_336_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20169_dupName_336_i_unnamed_c_compstr0_shift_x(MUX,20168)@181
    assign rightShiftStage1_uid20169_dupName_336_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20169_dupName_336_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20164_dupName_336_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20167_dupName_336_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20169_dupName_336_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20169_dupName_336_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20164_dupName_336_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20169_dupName_336_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20167_dupName_336_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20169_dupName_336_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2375_vt_select_21(BITSELECT,10993)@181
    assign i_unnamed_c_compstr2375_vt_select_21_b = rightShiftStage1_uid20169_dupName_336_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2375_vt_join(BITJOIN,10992)@181
    assign i_unnamed_c_compstr2375_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2375_vt_select_21_b};

    // i_unnamed_c_compstr2376_sel_x(BITSELECT,6143)@181
    assign i_unnamed_c_compstr2376_sel_x_b = i_unnamed_c_compstr2375_vt_join_q[15:0];

    // i_unnamed_c_compstr2377_BitSelect_for_a(BITSELECT,27675)@181
    assign i_unnamed_c_compstr2377_BitSelect_for_a_b = i_unnamed_c_compstr2376_sel_x_b[0:0];

    // i_unnamed_c_compstr2377_join(BITJOIN,27676)@181
    assign i_unnamed_c_compstr2377_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2377_BitSelect_for_a_b};

    // i_unnamed_c_compstr2377_vt_select_0(BITSELECT,10998)@181
    assign i_unnamed_c_compstr2377_vt_select_0_b = i_unnamed_c_compstr2377_join_q[0:0];

    // redist148_i_unnamed_c_compstr2377_vt_select_0_b_1(DELAY,28376)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist148_i_unnamed_c_compstr2377_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2377_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2377_vt_join(BITJOIN,10997)@182
    assign i_unnamed_c_compstr2377_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist148_i_unnamed_c_compstr2377_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_84_c_compstr2378(ADD,6961)@182
    assign i_add_i_i_i_i_i126_i_84_c_compstr2378_a = {1'b0, i_unnamed_c_compstr2377_vt_join_q};
    assign i_add_i_i_i_i_i126_i_84_c_compstr2378_b = {1'b0, redist1170_i_conv_i_i_i_i97_i_84_c_compstr2374_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_84_c_compstr2378_o = $unsigned(i_add_i_i_i_i_i126_i_84_c_compstr2378_a) + $unsigned(i_add_i_i_i_i_i126_i_84_c_compstr2378_b);
    assign i_add_i_i_i_i_i126_i_84_c_compstr2378_q = i_add_i_i_i_i_i126_i_84_c_compstr2378_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_84_c_compstr2378_sel_x(BITSELECT,2155)@182
    assign bgTrunc_i_add_i_i_i_i_i126_i_84_c_compstr2378_sel_x_b = i_add_i_i_i_i_i126_i_84_c_compstr2378_q[15:0];

    // i_conv_i_i_i_i_i75_i277_85_c_compstr2398_sel_x(BITSELECT,3696)@182
    assign i_conv_i_i_i_i_i75_i277_85_c_compstr2398_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_84_c_compstr2378_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_85_c_compstr2398_vt_select_15(BITSELECT,7685)@182
    assign i_conv_i_i_i_i_i75_i277_85_c_compstr2398_vt_select_15_b = i_conv_i_i_i_i_i75_i277_85_c_compstr2398_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_85_c_compstr2398_vt_join(BITJOIN,7684)@182
    assign i_conv_i_i_i_i_i75_i277_85_c_compstr2398_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_85_c_compstr2398_vt_select_15_b};

    // leftShiftStage0_uid24854_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x(MUX,24853)@182
    assign leftShiftStage0_uid24854_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24854_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_85_c_compstr2398_vt_join_q or leftShiftStage0Idx1_uid24852_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24854_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24854_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_85_c_compstr2398_vt_join_q;
            1'b1 : leftShiftStage0_uid24854_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24852_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24854_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24859_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x(MUX,24858)@182
    assign leftShiftStage1_uid24859_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24859_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_s or leftShiftStage0_uid24854_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24857_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24859_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24859_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q = leftShiftStage0_uid24854_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24859_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24857_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24859_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24864_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x(MUX,24863)@182
    assign leftShiftStage2_uid24864_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24864_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_s or leftShiftStage1_uid24859_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24862_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24864_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24864_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q = leftShiftStage1_uid24859_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24864_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24862_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24864_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_85_c_compstr2399_vt_select_28(BITSELECT,9373)@182
    assign i_shl_i_i_i_i_i77_i_85_c_compstr2399_vt_select_28_b = leftShiftStage2_uid24864_i_shl_i_i_i_i_i77_i_85_c_compstr0_shift_x_q[28:13];

    // redist399_i_shl_i_i_i_i_i77_i_85_c_compstr2399_vt_select_28_b_1(DELAY,28627)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist399_i_shl_i_i_i_i_i77_i_85_c_compstr2399_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_85_c_compstr2399_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_85_c_compstr2399_vt_join(BITJOIN,9372)@183
    assign i_shl_i_i_i_i_i77_i_85_c_compstr2399_vt_join_q = {redist399_i_shl_i_i_i_i_i77_i_85_c_compstr2399_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma(CHAINMULTADD,28209)@177 + 5
    // out q@183
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ah[0] <= redist941_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_171_tpl_169_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ah[1] <= redist940_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_170_tpl_169_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ch[0] <= redist687_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_171_tpl_169_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ch[1] <= redist686_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_170_tpl_169_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400(ADD,8505)@183
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compstr2395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compstr2397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compstr2396_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_85_c_compstr2399_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_85_c_compstr2399_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_o[33:0];

    // rightShiftStage0_uid20208_dupName_339_i_unnamed_c_compstr0_shift_x(MUX,20207)@183
    assign rightShiftStage0_uid20208_dupName_339_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20208_dupName_339_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_q or rightShiftStage0Idx1_uid20206_dupName_339_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20208_dupName_339_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20208_dupName_339_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_q;
            1'b1 : rightShiftStage0_uid20208_dupName_339_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20206_dupName_339_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20208_dupName_339_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20213_dupName_339_i_unnamed_c_compstr0_shift_x(MUX,20212)@183
    assign rightShiftStage1_uid20213_dupName_339_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20213_dupName_339_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20208_dupName_339_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20211_dupName_339_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20213_dupName_339_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20213_dupName_339_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20208_dupName_339_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20213_dupName_339_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20211_dupName_339_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20213_dupName_339_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20218_dupName_339_i_unnamed_c_compstr0_shift_x(MUX,20217)@183
    assign rightShiftStage2_uid20218_dupName_339_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20218_dupName_339_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20213_dupName_339_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20216_dupName_339_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20218_dupName_339_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20218_dupName_339_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20213_dupName_339_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20218_dupName_339_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20216_dupName_339_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20218_dupName_339_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2401_vt_select_20(BITSELECT,11018)@183
    assign i_unnamed_c_compstr2401_vt_select_20_b = rightShiftStage2_uid20218_dupName_339_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2401_vt_join(BITJOIN,11017)@183
    assign i_unnamed_c_compstr2401_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2401_vt_select_20_b};

    // i_conv_i_i_i_i97_i_85_c_compstr2402_sel_x(BITSELECT,3567)@183
    assign i_conv_i_i_i_i97_i_85_c_compstr2402_sel_x_b = i_unnamed_c_compstr2401_vt_join_q[15:0];

    // redist1169_i_conv_i_i_i_i97_i_85_c_compstr2402_sel_x_b_1(DELAY,29397)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1169_i_conv_i_i_i_i97_i_85_c_compstr2402_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_85_c_compstr2402_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20227_dupName_340_i_unnamed_c_compstr0_shift_x(BITSELECT,20226)@183
    assign rightShiftStage1Idx1Rng8_uid20227_dupName_340_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20226_dupName_340_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20229_dupName_340_i_unnamed_c_compstr0_shift_x(BITJOIN,20228)@183
    assign rightShiftStage1Idx1_uid20229_dupName_340_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20227_dupName_340_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20222_dupName_340_i_unnamed_c_compstr0_shift_x(BITSELECT,20221)@183
    assign rightShiftStage0Idx1Rng4_uid20222_dupName_340_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_q[33:4];

    // rightShiftStage0Idx1_uid20224_dupName_340_i_unnamed_c_compstr0_shift_x(BITJOIN,20223)@183
    assign rightShiftStage0Idx1_uid20224_dupName_340_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20222_dupName_340_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20226_dupName_340_i_unnamed_c_compstr0_shift_x(MUX,20225)@183
    assign rightShiftStage0_uid20226_dupName_340_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20226_dupName_340_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_q or rightShiftStage0Idx1_uid20224_dupName_340_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20226_dupName_340_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20226_dupName_340_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compstr2400_q;
            1'b1 : rightShiftStage0_uid20226_dupName_340_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20224_dupName_340_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20226_dupName_340_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20231_dupName_340_i_unnamed_c_compstr0_shift_x(MUX,20230)@183
    assign rightShiftStage1_uid20231_dupName_340_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20231_dupName_340_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20226_dupName_340_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20229_dupName_340_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20231_dupName_340_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20231_dupName_340_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20226_dupName_340_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20231_dupName_340_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20229_dupName_340_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20231_dupName_340_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2403_vt_select_21(BITSELECT,11021)@183
    assign i_unnamed_c_compstr2403_vt_select_21_b = rightShiftStage1_uid20231_dupName_340_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2403_vt_join(BITJOIN,11020)@183
    assign i_unnamed_c_compstr2403_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2403_vt_select_21_b};

    // i_unnamed_c_compstr2404_sel_x(BITSELECT,6145)@183
    assign i_unnamed_c_compstr2404_sel_x_b = i_unnamed_c_compstr2403_vt_join_q[15:0];

    // i_unnamed_c_compstr2405_BitSelect_for_a(BITSELECT,27679)@183
    assign i_unnamed_c_compstr2405_BitSelect_for_a_b = i_unnamed_c_compstr2404_sel_x_b[0:0];

    // i_unnamed_c_compstr2405_join(BITJOIN,27680)@183
    assign i_unnamed_c_compstr2405_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2405_BitSelect_for_a_b};

    // i_unnamed_c_compstr2405_vt_select_0(BITSELECT,11026)@183
    assign i_unnamed_c_compstr2405_vt_select_0_b = i_unnamed_c_compstr2405_join_q[0:0];

    // redist145_i_unnamed_c_compstr2405_vt_select_0_b_1(DELAY,28373)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist145_i_unnamed_c_compstr2405_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2405_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2405_vt_join(BITJOIN,11025)@184
    assign i_unnamed_c_compstr2405_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist145_i_unnamed_c_compstr2405_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_85_c_compstr2406(ADD,6962)@184
    assign i_add_i_i_i_i_i126_i_85_c_compstr2406_a = {1'b0, i_unnamed_c_compstr2405_vt_join_q};
    assign i_add_i_i_i_i_i126_i_85_c_compstr2406_b = {1'b0, redist1169_i_conv_i_i_i_i97_i_85_c_compstr2402_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_85_c_compstr2406_o = $unsigned(i_add_i_i_i_i_i126_i_85_c_compstr2406_a) + $unsigned(i_add_i_i_i_i_i126_i_85_c_compstr2406_b);
    assign i_add_i_i_i_i_i126_i_85_c_compstr2406_q = i_add_i_i_i_i_i126_i_85_c_compstr2406_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_85_c_compstr2406_sel_x(BITSELECT,2156)@184
    assign bgTrunc_i_add_i_i_i_i_i126_i_85_c_compstr2406_sel_x_b = i_add_i_i_i_i_i126_i_85_c_compstr2406_q[15:0];

    // i_conv_i_i_i_i_i75_i277_86_c_compstr2426_sel_x(BITSELECT,3697)@184
    assign i_conv_i_i_i_i_i75_i277_86_c_compstr2426_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_85_c_compstr2406_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_86_c_compstr2426_vt_select_15(BITSELECT,7689)@184
    assign i_conv_i_i_i_i_i75_i277_86_c_compstr2426_vt_select_15_b = i_conv_i_i_i_i_i75_i277_86_c_compstr2426_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_86_c_compstr2426_vt_join(BITJOIN,7688)@184
    assign i_conv_i_i_i_i_i75_i277_86_c_compstr2426_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_86_c_compstr2426_vt_select_15_b};

    // leftShiftStage0_uid24872_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x(MUX,24871)@184
    assign leftShiftStage0_uid24872_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24872_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_86_c_compstr2426_vt_join_q or leftShiftStage0Idx1_uid24870_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24872_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24872_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_86_c_compstr2426_vt_join_q;
            1'b1 : leftShiftStage0_uid24872_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24870_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24872_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24877_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x(MUX,24876)@184
    assign leftShiftStage1_uid24877_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24877_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_s or leftShiftStage0_uid24872_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24875_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24877_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24877_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q = leftShiftStage0_uid24872_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24877_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24875_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24877_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24882_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x(MUX,24881)@184
    assign leftShiftStage2_uid24882_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24882_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_s or leftShiftStage1_uid24877_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24880_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24882_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24882_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q = leftShiftStage1_uid24877_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24882_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24880_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24882_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_86_c_compstr2427_vt_select_28(BITSELECT,9376)@184
    assign i_shl_i_i_i_i_i77_i_86_c_compstr2427_vt_select_28_b = leftShiftStage2_uid24882_i_shl_i_i_i_i_i77_i_86_c_compstr0_shift_x_q[28:13];

    // redist398_i_shl_i_i_i_i_i77_i_86_c_compstr2427_vt_select_28_b_1(DELAY,28626)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist398_i_shl_i_i_i_i_i77_i_86_c_compstr2427_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_86_c_compstr2427_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_86_c_compstr2427_vt_join(BITJOIN,9375)@185
    assign i_shl_i_i_i_i_i77_i_86_c_compstr2427_vt_join_q = {redist398_i_shl_i_i_i_i_i77_i_86_c_compstr2427_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma(CHAINMULTADD,28210)@179 + 5
    // out q@185
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ah[0] <= redist943_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_173_tpl_171_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ah[1] <= redist942_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_172_tpl_171_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ch[0] <= redist689_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_173_tpl_171_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ch[1] <= redist688_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_172_tpl_171_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428(ADD,8506)@185
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compstr2423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compstr2425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compstr2424_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_86_c_compstr2427_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_86_c_compstr2427_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_o[33:0];

    // rightShiftStage0_uid20270_dupName_343_i_unnamed_c_compstr0_shift_x(MUX,20269)@185
    assign rightShiftStage0_uid20270_dupName_343_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20270_dupName_343_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_q or rightShiftStage0Idx1_uid20268_dupName_343_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20270_dupName_343_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20270_dupName_343_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_q;
            1'b1 : rightShiftStage0_uid20270_dupName_343_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20268_dupName_343_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20270_dupName_343_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20275_dupName_343_i_unnamed_c_compstr0_shift_x(MUX,20274)@185
    assign rightShiftStage1_uid20275_dupName_343_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20275_dupName_343_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20270_dupName_343_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20273_dupName_343_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20275_dupName_343_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20275_dupName_343_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20270_dupName_343_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20275_dupName_343_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20273_dupName_343_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20275_dupName_343_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20280_dupName_343_i_unnamed_c_compstr0_shift_x(MUX,20279)@185
    assign rightShiftStage2_uid20280_dupName_343_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20280_dupName_343_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20275_dupName_343_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20278_dupName_343_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20280_dupName_343_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20280_dupName_343_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20275_dupName_343_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20280_dupName_343_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20278_dupName_343_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20280_dupName_343_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2429_vt_select_20(BITSELECT,11040)@185
    assign i_unnamed_c_compstr2429_vt_select_20_b = rightShiftStage2_uid20280_dupName_343_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2429_vt_join(BITJOIN,11039)@185
    assign i_unnamed_c_compstr2429_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2429_vt_select_20_b};

    // i_conv_i_i_i_i97_i_86_c_compstr2430_sel_x(BITSELECT,3568)@185
    assign i_conv_i_i_i_i97_i_86_c_compstr2430_sel_x_b = i_unnamed_c_compstr2429_vt_join_q[15:0];

    // redist1168_i_conv_i_i_i_i97_i_86_c_compstr2430_sel_x_b_1(DELAY,29396)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1168_i_conv_i_i_i_i97_i_86_c_compstr2430_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_86_c_compstr2430_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20289_dupName_344_i_unnamed_c_compstr0_shift_x(BITSELECT,20288)@185
    assign rightShiftStage1Idx1Rng8_uid20289_dupName_344_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20288_dupName_344_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20291_dupName_344_i_unnamed_c_compstr0_shift_x(BITJOIN,20290)@185
    assign rightShiftStage1Idx1_uid20291_dupName_344_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20289_dupName_344_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20284_dupName_344_i_unnamed_c_compstr0_shift_x(BITSELECT,20283)@185
    assign rightShiftStage0Idx1Rng4_uid20284_dupName_344_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_q[33:4];

    // rightShiftStage0Idx1_uid20286_dupName_344_i_unnamed_c_compstr0_shift_x(BITJOIN,20285)@185
    assign rightShiftStage0Idx1_uid20286_dupName_344_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20284_dupName_344_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20288_dupName_344_i_unnamed_c_compstr0_shift_x(MUX,20287)@185
    assign rightShiftStage0_uid20288_dupName_344_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20288_dupName_344_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_q or rightShiftStage0Idx1_uid20286_dupName_344_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20288_dupName_344_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20288_dupName_344_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compstr2428_q;
            1'b1 : rightShiftStage0_uid20288_dupName_344_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20286_dupName_344_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20288_dupName_344_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20293_dupName_344_i_unnamed_c_compstr0_shift_x(MUX,20292)@185
    assign rightShiftStage1_uid20293_dupName_344_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20293_dupName_344_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20288_dupName_344_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20291_dupName_344_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20293_dupName_344_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20293_dupName_344_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20288_dupName_344_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20293_dupName_344_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20291_dupName_344_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20293_dupName_344_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2431_vt_select_21(BITSELECT,11043)@185
    assign i_unnamed_c_compstr2431_vt_select_21_b = rightShiftStage1_uid20293_dupName_344_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2431_vt_join(BITJOIN,11042)@185
    assign i_unnamed_c_compstr2431_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2431_vt_select_21_b};

    // i_unnamed_c_compstr2432_sel_x(BITSELECT,6147)@185
    assign i_unnamed_c_compstr2432_sel_x_b = i_unnamed_c_compstr2431_vt_join_q[15:0];

    // i_unnamed_c_compstr2433_BitSelect_for_a(BITSELECT,27683)@185
    assign i_unnamed_c_compstr2433_BitSelect_for_a_b = i_unnamed_c_compstr2432_sel_x_b[0:0];

    // i_unnamed_c_compstr2433_join(BITJOIN,27684)@185
    assign i_unnamed_c_compstr2433_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2433_BitSelect_for_a_b};

    // i_unnamed_c_compstr2433_vt_select_0(BITSELECT,11048)@185
    assign i_unnamed_c_compstr2433_vt_select_0_b = i_unnamed_c_compstr2433_join_q[0:0];

    // redist143_i_unnamed_c_compstr2433_vt_select_0_b_1(DELAY,28371)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist143_i_unnamed_c_compstr2433_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2433_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2433_vt_join(BITJOIN,11047)@186
    assign i_unnamed_c_compstr2433_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist143_i_unnamed_c_compstr2433_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_86_c_compstr2434(ADD,6963)@186
    assign i_add_i_i_i_i_i126_i_86_c_compstr2434_a = {1'b0, i_unnamed_c_compstr2433_vt_join_q};
    assign i_add_i_i_i_i_i126_i_86_c_compstr2434_b = {1'b0, redist1168_i_conv_i_i_i_i97_i_86_c_compstr2430_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_86_c_compstr2434_o = $unsigned(i_add_i_i_i_i_i126_i_86_c_compstr2434_a) + $unsigned(i_add_i_i_i_i_i126_i_86_c_compstr2434_b);
    assign i_add_i_i_i_i_i126_i_86_c_compstr2434_q = i_add_i_i_i_i_i126_i_86_c_compstr2434_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_86_c_compstr2434_sel_x(BITSELECT,2157)@186
    assign bgTrunc_i_add_i_i_i_i_i126_i_86_c_compstr2434_sel_x_b = i_add_i_i_i_i_i126_i_86_c_compstr2434_q[15:0];

    // i_conv_i_i_i_i_i75_i277_87_c_compstr2454_sel_x(BITSELECT,3698)@186
    assign i_conv_i_i_i_i_i75_i277_87_c_compstr2454_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_86_c_compstr2434_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_87_c_compstr2454_vt_select_15(BITSELECT,7693)@186
    assign i_conv_i_i_i_i_i75_i277_87_c_compstr2454_vt_select_15_b = i_conv_i_i_i_i_i75_i277_87_c_compstr2454_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_87_c_compstr2454_vt_join(BITJOIN,7692)@186
    assign i_conv_i_i_i_i_i75_i277_87_c_compstr2454_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_87_c_compstr2454_vt_select_15_b};

    // leftShiftStage0_uid24890_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x(MUX,24889)@186
    assign leftShiftStage0_uid24890_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24890_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_87_c_compstr2454_vt_join_q or leftShiftStage0Idx1_uid24888_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24890_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24890_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_87_c_compstr2454_vt_join_q;
            1'b1 : leftShiftStage0_uid24890_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24888_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24890_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24895_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x(MUX,24894)@186
    assign leftShiftStage1_uid24895_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24895_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_s or leftShiftStage0_uid24890_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24893_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24895_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24895_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q = leftShiftStage0_uid24890_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24895_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24893_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24895_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24900_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x(MUX,24899)@186
    assign leftShiftStage2_uid24900_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24900_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_s or leftShiftStage1_uid24895_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24898_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24900_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24900_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q = leftShiftStage1_uid24895_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24900_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24898_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24900_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_87_c_compstr2455_vt_select_28(BITSELECT,9379)@186
    assign i_shl_i_i_i_i_i77_i_87_c_compstr2455_vt_select_28_b = leftShiftStage2_uid24900_i_shl_i_i_i_i_i77_i_87_c_compstr0_shift_x_q[28:13];

    // redist397_i_shl_i_i_i_i_i77_i_87_c_compstr2455_vt_select_28_b_1(DELAY,28625)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist397_i_shl_i_i_i_i_i77_i_87_c_compstr2455_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_87_c_compstr2455_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_87_c_compstr2455_vt_join(BITJOIN,9378)@187
    assign i_shl_i_i_i_i_i77_i_87_c_compstr2455_vt_join_q = {redist397_i_shl_i_i_i_i_i77_i_87_c_compstr2455_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma(CHAINMULTADD,28211)@181 + 5
    // out q@187
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ah[0] <= redist945_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_175_tpl_173_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ah[1] <= redist944_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_174_tpl_173_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ch[0] <= redist691_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_175_tpl_173_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ch[1] <= redist690_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_174_tpl_173_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456(ADD,8507)@187
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compstr2451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compstr2453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compstr2452_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_87_c_compstr2455_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_87_c_compstr2455_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_o[33:0];

    // rightShiftStage0_uid20332_dupName_347_i_unnamed_c_compstr0_shift_x(MUX,20331)@187
    assign rightShiftStage0_uid20332_dupName_347_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20332_dupName_347_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_q or rightShiftStage0Idx1_uid20330_dupName_347_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20332_dupName_347_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20332_dupName_347_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_q;
            1'b1 : rightShiftStage0_uid20332_dupName_347_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20330_dupName_347_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20332_dupName_347_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20337_dupName_347_i_unnamed_c_compstr0_shift_x(MUX,20336)@187
    assign rightShiftStage1_uid20337_dupName_347_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20337_dupName_347_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20332_dupName_347_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20335_dupName_347_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20337_dupName_347_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20337_dupName_347_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20332_dupName_347_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20337_dupName_347_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20335_dupName_347_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20337_dupName_347_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20342_dupName_347_i_unnamed_c_compstr0_shift_x(MUX,20341)@187
    assign rightShiftStage2_uid20342_dupName_347_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20342_dupName_347_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20337_dupName_347_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20340_dupName_347_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20342_dupName_347_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20342_dupName_347_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20337_dupName_347_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20342_dupName_347_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20340_dupName_347_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20342_dupName_347_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2457_vt_select_20(BITSELECT,11062)@187
    assign i_unnamed_c_compstr2457_vt_select_20_b = rightShiftStage2_uid20342_dupName_347_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2457_vt_join(BITJOIN,11061)@187
    assign i_unnamed_c_compstr2457_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2457_vt_select_20_b};

    // i_conv_i_i_i_i97_i_87_c_compstr2458_sel_x(BITSELECT,3569)@187
    assign i_conv_i_i_i_i97_i_87_c_compstr2458_sel_x_b = i_unnamed_c_compstr2457_vt_join_q[15:0];

    // redist1167_i_conv_i_i_i_i97_i_87_c_compstr2458_sel_x_b_1(DELAY,29395)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1167_i_conv_i_i_i_i97_i_87_c_compstr2458_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_87_c_compstr2458_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20351_dupName_348_i_unnamed_c_compstr0_shift_x(BITSELECT,20350)@187
    assign rightShiftStage1Idx1Rng8_uid20351_dupName_348_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20350_dupName_348_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20353_dupName_348_i_unnamed_c_compstr0_shift_x(BITJOIN,20352)@187
    assign rightShiftStage1Idx1_uid20353_dupName_348_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20351_dupName_348_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20346_dupName_348_i_unnamed_c_compstr0_shift_x(BITSELECT,20345)@187
    assign rightShiftStage0Idx1Rng4_uid20346_dupName_348_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_q[33:4];

    // rightShiftStage0Idx1_uid20348_dupName_348_i_unnamed_c_compstr0_shift_x(BITJOIN,20347)@187
    assign rightShiftStage0Idx1_uid20348_dupName_348_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20346_dupName_348_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20350_dupName_348_i_unnamed_c_compstr0_shift_x(MUX,20349)@187
    assign rightShiftStage0_uid20350_dupName_348_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20350_dupName_348_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_q or rightShiftStage0Idx1_uid20348_dupName_348_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20350_dupName_348_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20350_dupName_348_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compstr2456_q;
            1'b1 : rightShiftStage0_uid20350_dupName_348_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20348_dupName_348_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20350_dupName_348_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20355_dupName_348_i_unnamed_c_compstr0_shift_x(MUX,20354)@187
    assign rightShiftStage1_uid20355_dupName_348_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20355_dupName_348_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20350_dupName_348_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20353_dupName_348_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20355_dupName_348_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20355_dupName_348_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20350_dupName_348_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20355_dupName_348_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20353_dupName_348_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20355_dupName_348_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2459_vt_select_21(BITSELECT,11065)@187
    assign i_unnamed_c_compstr2459_vt_select_21_b = rightShiftStage1_uid20355_dupName_348_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2459_vt_join(BITJOIN,11064)@187
    assign i_unnamed_c_compstr2459_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2459_vt_select_21_b};

    // i_unnamed_c_compstr2460_sel_x(BITSELECT,6149)@187
    assign i_unnamed_c_compstr2460_sel_x_b = i_unnamed_c_compstr2459_vt_join_q[15:0];

    // i_unnamed_c_compstr2461_BitSelect_for_a(BITSELECT,27687)@187
    assign i_unnamed_c_compstr2461_BitSelect_for_a_b = i_unnamed_c_compstr2460_sel_x_b[0:0];

    // i_unnamed_c_compstr2461_join(BITJOIN,27688)@187
    assign i_unnamed_c_compstr2461_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2461_BitSelect_for_a_b};

    // i_unnamed_c_compstr2461_vt_select_0(BITSELECT,11073)@187
    assign i_unnamed_c_compstr2461_vt_select_0_b = i_unnamed_c_compstr2461_join_q[0:0];

    // redist141_i_unnamed_c_compstr2461_vt_select_0_b_1(DELAY,28369)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist141_i_unnamed_c_compstr2461_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2461_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2461_vt_join(BITJOIN,11072)@188
    assign i_unnamed_c_compstr2461_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist141_i_unnamed_c_compstr2461_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_87_c_compstr2462(ADD,6964)@188
    assign i_add_i_i_i_i_i126_i_87_c_compstr2462_a = {1'b0, i_unnamed_c_compstr2461_vt_join_q};
    assign i_add_i_i_i_i_i126_i_87_c_compstr2462_b = {1'b0, redist1167_i_conv_i_i_i_i97_i_87_c_compstr2458_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_87_c_compstr2462_o = $unsigned(i_add_i_i_i_i_i126_i_87_c_compstr2462_a) + $unsigned(i_add_i_i_i_i_i126_i_87_c_compstr2462_b);
    assign i_add_i_i_i_i_i126_i_87_c_compstr2462_q = i_add_i_i_i_i_i126_i_87_c_compstr2462_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_87_c_compstr2462_sel_x(BITSELECT,2158)@188
    assign bgTrunc_i_add_i_i_i_i_i126_i_87_c_compstr2462_sel_x_b = i_add_i_i_i_i_i126_i_87_c_compstr2462_q[15:0];

    // i_conv_i_i_i_i_i75_i277_88_c_compstr2482_sel_x(BITSELECT,3699)@188
    assign i_conv_i_i_i_i_i75_i277_88_c_compstr2482_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_87_c_compstr2462_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_88_c_compstr2482_vt_select_15(BITSELECT,7697)@188
    assign i_conv_i_i_i_i_i75_i277_88_c_compstr2482_vt_select_15_b = i_conv_i_i_i_i_i75_i277_88_c_compstr2482_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_88_c_compstr2482_vt_join(BITJOIN,7696)@188
    assign i_conv_i_i_i_i_i75_i277_88_c_compstr2482_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_88_c_compstr2482_vt_select_15_b};

    // leftShiftStage0_uid24908_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x(MUX,24907)@188
    assign leftShiftStage0_uid24908_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24908_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_88_c_compstr2482_vt_join_q or leftShiftStage0Idx1_uid24906_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24908_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24908_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_88_c_compstr2482_vt_join_q;
            1'b1 : leftShiftStage0_uid24908_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24906_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24908_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24913_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x(MUX,24912)@188
    assign leftShiftStage1_uid24913_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24913_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_s or leftShiftStage0_uid24908_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24911_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24913_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24913_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q = leftShiftStage0_uid24908_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24913_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24911_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24913_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24918_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x(MUX,24917)@188
    assign leftShiftStage2_uid24918_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24918_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_s or leftShiftStage1_uid24913_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24916_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24918_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24918_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q = leftShiftStage1_uid24913_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24918_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24916_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24918_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_88_c_compstr2483_vt_select_28(BITSELECT,9382)@188
    assign i_shl_i_i_i_i_i77_i_88_c_compstr2483_vt_select_28_b = leftShiftStage2_uid24918_i_shl_i_i_i_i_i77_i_88_c_compstr0_shift_x_q[28:13];

    // redist396_i_shl_i_i_i_i_i77_i_88_c_compstr2483_vt_select_28_b_1(DELAY,28624)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist396_i_shl_i_i_i_i_i77_i_88_c_compstr2483_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_88_c_compstr2483_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_88_c_compstr2483_vt_join(BITJOIN,9381)@189
    assign i_shl_i_i_i_i_i77_i_88_c_compstr2483_vt_join_q = {redist396_i_shl_i_i_i_i_i77_i_88_c_compstr2483_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma(CHAINMULTADD,28212)@183 + 5
    // out q@189
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ah[0] <= redist947_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_177_tpl_175_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ah[1] <= redist946_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_176_tpl_175_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ch[0] <= redist693_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_177_tpl_175_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ch[1] <= redist692_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_176_tpl_175_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484(ADD,8508)@189
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compstr2479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compstr2481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compstr2480_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_88_c_compstr2483_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_88_c_compstr2483_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_o[33:0];

    // rightShiftStage0_uid20394_dupName_351_i_unnamed_c_compstr0_shift_x(MUX,20393)@189
    assign rightShiftStage0_uid20394_dupName_351_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20394_dupName_351_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_q or rightShiftStage0Idx1_uid20392_dupName_351_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20394_dupName_351_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20394_dupName_351_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_q;
            1'b1 : rightShiftStage0_uid20394_dupName_351_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20392_dupName_351_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20394_dupName_351_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20399_dupName_351_i_unnamed_c_compstr0_shift_x(MUX,20398)@189
    assign rightShiftStage1_uid20399_dupName_351_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20399_dupName_351_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20394_dupName_351_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20397_dupName_351_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20399_dupName_351_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20399_dupName_351_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20394_dupName_351_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20399_dupName_351_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20397_dupName_351_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20399_dupName_351_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20404_dupName_351_i_unnamed_c_compstr0_shift_x(MUX,20403)@189
    assign rightShiftStage2_uid20404_dupName_351_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20404_dupName_351_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20399_dupName_351_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20402_dupName_351_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20404_dupName_351_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20404_dupName_351_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20399_dupName_351_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20404_dupName_351_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20402_dupName_351_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20404_dupName_351_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2485_vt_select_20(BITSELECT,11090)@189
    assign i_unnamed_c_compstr2485_vt_select_20_b = rightShiftStage2_uid20404_dupName_351_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2485_vt_join(BITJOIN,11089)@189
    assign i_unnamed_c_compstr2485_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2485_vt_select_20_b};

    // i_conv_i_i_i_i97_i_88_c_compstr2486_sel_x(BITSELECT,3570)@189
    assign i_conv_i_i_i_i97_i_88_c_compstr2486_sel_x_b = i_unnamed_c_compstr2485_vt_join_q[15:0];

    // redist1166_i_conv_i_i_i_i97_i_88_c_compstr2486_sel_x_b_1(DELAY,29394)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1166_i_conv_i_i_i_i97_i_88_c_compstr2486_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_88_c_compstr2486_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20413_dupName_352_i_unnamed_c_compstr0_shift_x(BITSELECT,20412)@189
    assign rightShiftStage1Idx1Rng8_uid20413_dupName_352_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20412_dupName_352_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20415_dupName_352_i_unnamed_c_compstr0_shift_x(BITJOIN,20414)@189
    assign rightShiftStage1Idx1_uid20415_dupName_352_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20413_dupName_352_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20408_dupName_352_i_unnamed_c_compstr0_shift_x(BITSELECT,20407)@189
    assign rightShiftStage0Idx1Rng4_uid20408_dupName_352_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_q[33:4];

    // rightShiftStage0Idx1_uid20410_dupName_352_i_unnamed_c_compstr0_shift_x(BITJOIN,20409)@189
    assign rightShiftStage0Idx1_uid20410_dupName_352_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20408_dupName_352_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20412_dupName_352_i_unnamed_c_compstr0_shift_x(MUX,20411)@189
    assign rightShiftStage0_uid20412_dupName_352_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20412_dupName_352_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_q or rightShiftStage0Idx1_uid20410_dupName_352_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20412_dupName_352_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20412_dupName_352_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compstr2484_q;
            1'b1 : rightShiftStage0_uid20412_dupName_352_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20410_dupName_352_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20412_dupName_352_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20417_dupName_352_i_unnamed_c_compstr0_shift_x(MUX,20416)@189
    assign rightShiftStage1_uid20417_dupName_352_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20417_dupName_352_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20412_dupName_352_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20415_dupName_352_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20417_dupName_352_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20417_dupName_352_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20412_dupName_352_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20417_dupName_352_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20415_dupName_352_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20417_dupName_352_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2487_vt_select_21(BITSELECT,11093)@189
    assign i_unnamed_c_compstr2487_vt_select_21_b = rightShiftStage1_uid20417_dupName_352_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2487_vt_join(BITJOIN,11092)@189
    assign i_unnamed_c_compstr2487_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2487_vt_select_21_b};

    // i_unnamed_c_compstr2488_sel_x(BITSELECT,6152)@189
    assign i_unnamed_c_compstr2488_sel_x_b = i_unnamed_c_compstr2487_vt_join_q[15:0];

    // i_unnamed_c_compstr2489_BitSelect_for_a(BITSELECT,27691)@189
    assign i_unnamed_c_compstr2489_BitSelect_for_a_b = i_unnamed_c_compstr2488_sel_x_b[0:0];

    // i_unnamed_c_compstr2489_join(BITJOIN,27692)@189
    assign i_unnamed_c_compstr2489_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2489_BitSelect_for_a_b};

    // i_unnamed_c_compstr2489_vt_select_0(BITSELECT,11098)@189
    assign i_unnamed_c_compstr2489_vt_select_0_b = i_unnamed_c_compstr2489_join_q[0:0];

    // redist139_i_unnamed_c_compstr2489_vt_select_0_b_1(DELAY,28367)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist139_i_unnamed_c_compstr2489_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2489_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2489_vt_join(BITJOIN,11097)@190
    assign i_unnamed_c_compstr2489_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist139_i_unnamed_c_compstr2489_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_88_c_compstr2490(ADD,6965)@190
    assign i_add_i_i_i_i_i126_i_88_c_compstr2490_a = {1'b0, i_unnamed_c_compstr2489_vt_join_q};
    assign i_add_i_i_i_i_i126_i_88_c_compstr2490_b = {1'b0, redist1166_i_conv_i_i_i_i97_i_88_c_compstr2486_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_88_c_compstr2490_o = $unsigned(i_add_i_i_i_i_i126_i_88_c_compstr2490_a) + $unsigned(i_add_i_i_i_i_i126_i_88_c_compstr2490_b);
    assign i_add_i_i_i_i_i126_i_88_c_compstr2490_q = i_add_i_i_i_i_i126_i_88_c_compstr2490_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_88_c_compstr2490_sel_x(BITSELECT,2159)@190
    assign bgTrunc_i_add_i_i_i_i_i126_i_88_c_compstr2490_sel_x_b = i_add_i_i_i_i_i126_i_88_c_compstr2490_q[15:0];

    // i_conv_i_i_i_i_i75_i277_89_c_compstr2510_sel_x(BITSELECT,3700)@190
    assign i_conv_i_i_i_i_i75_i277_89_c_compstr2510_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_88_c_compstr2490_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_89_c_compstr2510_vt_select_15(BITSELECT,7701)@190
    assign i_conv_i_i_i_i_i75_i277_89_c_compstr2510_vt_select_15_b = i_conv_i_i_i_i_i75_i277_89_c_compstr2510_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_89_c_compstr2510_vt_join(BITJOIN,7700)@190
    assign i_conv_i_i_i_i_i75_i277_89_c_compstr2510_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_89_c_compstr2510_vt_select_15_b};

    // leftShiftStage0_uid24926_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x(MUX,24925)@190
    assign leftShiftStage0_uid24926_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24926_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_89_c_compstr2510_vt_join_q or leftShiftStage0Idx1_uid24924_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24926_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24926_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_89_c_compstr2510_vt_join_q;
            1'b1 : leftShiftStage0_uid24926_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24924_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24926_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24931_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x(MUX,24930)@190
    assign leftShiftStage1_uid24931_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24931_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_s or leftShiftStage0_uid24926_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24929_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24931_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24931_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q = leftShiftStage0_uid24926_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24931_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24929_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24931_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24936_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x(MUX,24935)@190
    assign leftShiftStage2_uid24936_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24936_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_s or leftShiftStage1_uid24931_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24934_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24936_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24936_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q = leftShiftStage1_uid24931_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24936_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24934_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24936_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_89_c_compstr2511_vt_select_28(BITSELECT,9385)@190
    assign i_shl_i_i_i_i_i77_i_89_c_compstr2511_vt_select_28_b = leftShiftStage2_uid24936_i_shl_i_i_i_i_i77_i_89_c_compstr0_shift_x_q[28:13];

    // redist395_i_shl_i_i_i_i_i77_i_89_c_compstr2511_vt_select_28_b_1(DELAY,28623)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist395_i_shl_i_i_i_i_i77_i_89_c_compstr2511_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_89_c_compstr2511_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_89_c_compstr2511_vt_join(BITJOIN,9384)@191
    assign i_shl_i_i_i_i_i77_i_89_c_compstr2511_vt_join_q = {redist395_i_shl_i_i_i_i_i77_i_89_c_compstr2511_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma(CHAINMULTADD,28213)@185 + 5
    // out q@191
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ah[0] <= redist949_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_179_tpl_177_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ah[1] <= redist948_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_178_tpl_177_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ch[0] <= redist695_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_179_tpl_177_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ch[1] <= redist694_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_178_tpl_177_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512(ADD,8509)@191
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compstr2507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compstr2509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compstr2508_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_89_c_compstr2511_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_89_c_compstr2511_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_o[33:0];

    // rightShiftStage0_uid20456_dupName_355_i_unnamed_c_compstr0_shift_x(MUX,20455)@191
    assign rightShiftStage0_uid20456_dupName_355_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20456_dupName_355_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_q or rightShiftStage0Idx1_uid20454_dupName_355_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20456_dupName_355_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20456_dupName_355_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_q;
            1'b1 : rightShiftStage0_uid20456_dupName_355_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20454_dupName_355_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20456_dupName_355_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20461_dupName_355_i_unnamed_c_compstr0_shift_x(MUX,20460)@191
    assign rightShiftStage1_uid20461_dupName_355_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20461_dupName_355_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20456_dupName_355_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20459_dupName_355_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20461_dupName_355_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20461_dupName_355_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20456_dupName_355_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20461_dupName_355_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20459_dupName_355_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20461_dupName_355_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20466_dupName_355_i_unnamed_c_compstr0_shift_x(MUX,20465)@191
    assign rightShiftStage2_uid20466_dupName_355_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20466_dupName_355_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20461_dupName_355_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20464_dupName_355_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20466_dupName_355_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20466_dupName_355_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20461_dupName_355_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20466_dupName_355_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20464_dupName_355_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20466_dupName_355_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2513_vt_select_20(BITSELECT,11117)@191
    assign i_unnamed_c_compstr2513_vt_select_20_b = rightShiftStage2_uid20466_dupName_355_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2513_vt_join(BITJOIN,11116)@191
    assign i_unnamed_c_compstr2513_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2513_vt_select_20_b};

    // i_conv_i_i_i_i97_i_89_c_compstr2514_sel_x(BITSELECT,3571)@191
    assign i_conv_i_i_i_i97_i_89_c_compstr2514_sel_x_b = i_unnamed_c_compstr2513_vt_join_q[15:0];

    // redist1165_i_conv_i_i_i_i97_i_89_c_compstr2514_sel_x_b_1(DELAY,29393)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1165_i_conv_i_i_i_i97_i_89_c_compstr2514_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_89_c_compstr2514_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20475_dupName_356_i_unnamed_c_compstr0_shift_x(BITSELECT,20474)@191
    assign rightShiftStage1Idx1Rng8_uid20475_dupName_356_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20474_dupName_356_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20477_dupName_356_i_unnamed_c_compstr0_shift_x(BITJOIN,20476)@191
    assign rightShiftStage1Idx1_uid20477_dupName_356_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20475_dupName_356_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20470_dupName_356_i_unnamed_c_compstr0_shift_x(BITSELECT,20469)@191
    assign rightShiftStage0Idx1Rng4_uid20470_dupName_356_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_q[33:4];

    // rightShiftStage0Idx1_uid20472_dupName_356_i_unnamed_c_compstr0_shift_x(BITJOIN,20471)@191
    assign rightShiftStage0Idx1_uid20472_dupName_356_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20470_dupName_356_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20474_dupName_356_i_unnamed_c_compstr0_shift_x(MUX,20473)@191
    assign rightShiftStage0_uid20474_dupName_356_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20474_dupName_356_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_q or rightShiftStage0Idx1_uid20472_dupName_356_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20474_dupName_356_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20474_dupName_356_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compstr2512_q;
            1'b1 : rightShiftStage0_uid20474_dupName_356_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20472_dupName_356_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20474_dupName_356_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20479_dupName_356_i_unnamed_c_compstr0_shift_x(MUX,20478)@191
    assign rightShiftStage1_uid20479_dupName_356_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20479_dupName_356_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20474_dupName_356_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20477_dupName_356_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20479_dupName_356_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20479_dupName_356_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20474_dupName_356_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20479_dupName_356_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20477_dupName_356_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20479_dupName_356_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2515_vt_select_21(BITSELECT,11120)@191
    assign i_unnamed_c_compstr2515_vt_select_21_b = rightShiftStage1_uid20479_dupName_356_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2515_vt_join(BITJOIN,11119)@191
    assign i_unnamed_c_compstr2515_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2515_vt_select_21_b};

    // i_unnamed_c_compstr2516_sel_x(BITSELECT,6154)@191
    assign i_unnamed_c_compstr2516_sel_x_b = i_unnamed_c_compstr2515_vt_join_q[15:0];

    // i_unnamed_c_compstr2517_BitSelect_for_a(BITSELECT,27697)@191
    assign i_unnamed_c_compstr2517_BitSelect_for_a_b = i_unnamed_c_compstr2516_sel_x_b[0:0];

    // i_unnamed_c_compstr2517_join(BITJOIN,27698)@191
    assign i_unnamed_c_compstr2517_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2517_BitSelect_for_a_b};

    // i_unnamed_c_compstr2517_vt_select_0(BITSELECT,11125)@191
    assign i_unnamed_c_compstr2517_vt_select_0_b = i_unnamed_c_compstr2517_join_q[0:0];

    // redist136_i_unnamed_c_compstr2517_vt_select_0_b_1(DELAY,28364)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist136_i_unnamed_c_compstr2517_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2517_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2517_vt_join(BITJOIN,11124)@192
    assign i_unnamed_c_compstr2517_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist136_i_unnamed_c_compstr2517_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_89_c_compstr2518(ADD,6966)@192
    assign i_add_i_i_i_i_i126_i_89_c_compstr2518_a = {1'b0, i_unnamed_c_compstr2517_vt_join_q};
    assign i_add_i_i_i_i_i126_i_89_c_compstr2518_b = {1'b0, redist1165_i_conv_i_i_i_i97_i_89_c_compstr2514_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_89_c_compstr2518_o = $unsigned(i_add_i_i_i_i_i126_i_89_c_compstr2518_a) + $unsigned(i_add_i_i_i_i_i126_i_89_c_compstr2518_b);
    assign i_add_i_i_i_i_i126_i_89_c_compstr2518_q = i_add_i_i_i_i_i126_i_89_c_compstr2518_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_89_c_compstr2518_sel_x(BITSELECT,2160)@192
    assign bgTrunc_i_add_i_i_i_i_i126_i_89_c_compstr2518_sel_x_b = i_add_i_i_i_i_i126_i_89_c_compstr2518_q[15:0];

    // i_conv_i_i_i_i_i75_i277_90_c_compstr2538_sel_x(BITSELECT,3702)@192
    assign i_conv_i_i_i_i_i75_i277_90_c_compstr2538_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_89_c_compstr2518_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_90_c_compstr2538_vt_select_15(BITSELECT,7709)@192
    assign i_conv_i_i_i_i_i75_i277_90_c_compstr2538_vt_select_15_b = i_conv_i_i_i_i_i75_i277_90_c_compstr2538_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_90_c_compstr2538_vt_join(BITJOIN,7708)@192
    assign i_conv_i_i_i_i_i75_i277_90_c_compstr2538_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_90_c_compstr2538_vt_select_15_b};

    // leftShiftStage0_uid24962_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x(MUX,24961)@192
    assign leftShiftStage0_uid24962_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24962_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_90_c_compstr2538_vt_join_q or leftShiftStage0Idx1_uid24960_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24962_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24962_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_90_c_compstr2538_vt_join_q;
            1'b1 : leftShiftStage0_uid24962_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24960_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24962_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24967_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x(MUX,24966)@192
    assign leftShiftStage1_uid24967_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24967_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_s or leftShiftStage0_uid24962_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24965_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24967_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24967_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q = leftShiftStage0_uid24962_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24967_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24965_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24967_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24972_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x(MUX,24971)@192
    assign leftShiftStage2_uid24972_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24972_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_s or leftShiftStage1_uid24967_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24970_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24972_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24972_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q = leftShiftStage1_uid24967_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24972_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24970_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24972_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_90_c_compstr2539_vt_select_28(BITSELECT,9391)@192
    assign i_shl_i_i_i_i_i77_i_90_c_compstr2539_vt_select_28_b = leftShiftStage2_uid24972_i_shl_i_i_i_i_i77_i_90_c_compstr0_shift_x_q[28:13];

    // redist393_i_shl_i_i_i_i_i77_i_90_c_compstr2539_vt_select_28_b_1(DELAY,28621)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist393_i_shl_i_i_i_i_i77_i_90_c_compstr2539_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_90_c_compstr2539_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_90_c_compstr2539_vt_join(BITJOIN,9390)@193
    assign i_shl_i_i_i_i_i77_i_90_c_compstr2539_vt_join_q = {redist393_i_shl_i_i_i_i_i77_i_90_c_compstr2539_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma(CHAINMULTADD,28215)@187 + 5
    // out q@193
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ah[0] <= redist951_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_181_tpl_179_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ah[1] <= redist950_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_180_tpl_179_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ch[0] <= redist697_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_181_tpl_179_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ch[1] <= redist696_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_180_tpl_179_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540(ADD,8511)@193
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compstr2535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compstr2537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compstr2536_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_90_c_compstr2539_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_90_c_compstr2539_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_o[33:0];

    // rightShiftStage0_uid20518_dupName_359_i_unnamed_c_compstr0_shift_x(MUX,20517)@193
    assign rightShiftStage0_uid20518_dupName_359_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20518_dupName_359_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_q or rightShiftStage0Idx1_uid20516_dupName_359_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20518_dupName_359_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20518_dupName_359_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_q;
            1'b1 : rightShiftStage0_uid20518_dupName_359_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20516_dupName_359_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20518_dupName_359_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20523_dupName_359_i_unnamed_c_compstr0_shift_x(MUX,20522)@193
    assign rightShiftStage1_uid20523_dupName_359_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20523_dupName_359_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20518_dupName_359_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20521_dupName_359_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20523_dupName_359_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20523_dupName_359_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20518_dupName_359_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20523_dupName_359_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20521_dupName_359_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20523_dupName_359_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20528_dupName_359_i_unnamed_c_compstr0_shift_x(MUX,20527)@193
    assign rightShiftStage2_uid20528_dupName_359_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20528_dupName_359_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20523_dupName_359_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20526_dupName_359_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20528_dupName_359_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20528_dupName_359_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20523_dupName_359_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20528_dupName_359_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20526_dupName_359_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20528_dupName_359_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2541_vt_select_20(BITSELECT,11139)@193
    assign i_unnamed_c_compstr2541_vt_select_20_b = rightShiftStage2_uid20528_dupName_359_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2541_vt_join(BITJOIN,11138)@193
    assign i_unnamed_c_compstr2541_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2541_vt_select_20_b};

    // i_conv_i_i_i_i97_i_90_c_compstr2542_sel_x(BITSELECT,3573)@193
    assign i_conv_i_i_i_i97_i_90_c_compstr2542_sel_x_b = i_unnamed_c_compstr2541_vt_join_q[15:0];

    // redist1163_i_conv_i_i_i_i97_i_90_c_compstr2542_sel_x_b_1(DELAY,29391)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1163_i_conv_i_i_i_i97_i_90_c_compstr2542_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_90_c_compstr2542_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20537_dupName_360_i_unnamed_c_compstr0_shift_x(BITSELECT,20536)@193
    assign rightShiftStage1Idx1Rng8_uid20537_dupName_360_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20536_dupName_360_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20539_dupName_360_i_unnamed_c_compstr0_shift_x(BITJOIN,20538)@193
    assign rightShiftStage1Idx1_uid20539_dupName_360_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20537_dupName_360_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20532_dupName_360_i_unnamed_c_compstr0_shift_x(BITSELECT,20531)@193
    assign rightShiftStage0Idx1Rng4_uid20532_dupName_360_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_q[33:4];

    // rightShiftStage0Idx1_uid20534_dupName_360_i_unnamed_c_compstr0_shift_x(BITJOIN,20533)@193
    assign rightShiftStage0Idx1_uid20534_dupName_360_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20532_dupName_360_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20536_dupName_360_i_unnamed_c_compstr0_shift_x(MUX,20535)@193
    assign rightShiftStage0_uid20536_dupName_360_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20536_dupName_360_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_q or rightShiftStage0Idx1_uid20534_dupName_360_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20536_dupName_360_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20536_dupName_360_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compstr2540_q;
            1'b1 : rightShiftStage0_uid20536_dupName_360_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20534_dupName_360_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20536_dupName_360_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20541_dupName_360_i_unnamed_c_compstr0_shift_x(MUX,20540)@193
    assign rightShiftStage1_uid20541_dupName_360_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20541_dupName_360_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20536_dupName_360_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20539_dupName_360_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20541_dupName_360_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20541_dupName_360_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20536_dupName_360_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20541_dupName_360_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20539_dupName_360_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20541_dupName_360_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2543_vt_select_21(BITSELECT,11142)@193
    assign i_unnamed_c_compstr2543_vt_select_21_b = rightShiftStage1_uid20541_dupName_360_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2543_vt_join(BITJOIN,11141)@193
    assign i_unnamed_c_compstr2543_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2543_vt_select_21_b};

    // i_unnamed_c_compstr2544_sel_x(BITSELECT,6156)@193
    assign i_unnamed_c_compstr2544_sel_x_b = i_unnamed_c_compstr2543_vt_join_q[15:0];

    // i_unnamed_c_compstr2545_BitSelect_for_a(BITSELECT,27701)@193
    assign i_unnamed_c_compstr2545_BitSelect_for_a_b = i_unnamed_c_compstr2544_sel_x_b[0:0];

    // i_unnamed_c_compstr2545_join(BITJOIN,27702)@193
    assign i_unnamed_c_compstr2545_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2545_BitSelect_for_a_b};

    // i_unnamed_c_compstr2545_vt_select_0(BITSELECT,11147)@193
    assign i_unnamed_c_compstr2545_vt_select_0_b = i_unnamed_c_compstr2545_join_q[0:0];

    // redist134_i_unnamed_c_compstr2545_vt_select_0_b_1(DELAY,28362)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist134_i_unnamed_c_compstr2545_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2545_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2545_vt_join(BITJOIN,11146)@194
    assign i_unnamed_c_compstr2545_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist134_i_unnamed_c_compstr2545_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_90_c_compstr2546(ADD,6968)@194
    assign i_add_i_i_i_i_i126_i_90_c_compstr2546_a = {1'b0, i_unnamed_c_compstr2545_vt_join_q};
    assign i_add_i_i_i_i_i126_i_90_c_compstr2546_b = {1'b0, redist1163_i_conv_i_i_i_i97_i_90_c_compstr2542_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_90_c_compstr2546_o = $unsigned(i_add_i_i_i_i_i126_i_90_c_compstr2546_a) + $unsigned(i_add_i_i_i_i_i126_i_90_c_compstr2546_b);
    assign i_add_i_i_i_i_i126_i_90_c_compstr2546_q = i_add_i_i_i_i_i126_i_90_c_compstr2546_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_90_c_compstr2546_sel_x(BITSELECT,2162)@194
    assign bgTrunc_i_add_i_i_i_i_i126_i_90_c_compstr2546_sel_x_b = i_add_i_i_i_i_i126_i_90_c_compstr2546_q[15:0];

    // i_conv_i_i_i_i_i75_i277_91_c_compstr2566_sel_x(BITSELECT,3703)@194
    assign i_conv_i_i_i_i_i75_i277_91_c_compstr2566_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_90_c_compstr2546_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_91_c_compstr2566_vt_select_15(BITSELECT,7713)@194
    assign i_conv_i_i_i_i_i75_i277_91_c_compstr2566_vt_select_15_b = i_conv_i_i_i_i_i75_i277_91_c_compstr2566_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_91_c_compstr2566_vt_join(BITJOIN,7712)@194
    assign i_conv_i_i_i_i_i75_i277_91_c_compstr2566_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_91_c_compstr2566_vt_select_15_b};

    // leftShiftStage0_uid24980_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x(MUX,24979)@194
    assign leftShiftStage0_uid24980_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24980_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_91_c_compstr2566_vt_join_q or leftShiftStage0Idx1_uid24978_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24980_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24980_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_91_c_compstr2566_vt_join_q;
            1'b1 : leftShiftStage0_uid24980_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24978_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24980_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24985_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x(MUX,24984)@194
    assign leftShiftStage1_uid24985_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24985_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_s or leftShiftStage0_uid24980_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid24983_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24985_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid24985_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q = leftShiftStage0_uid24980_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid24985_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid24983_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid24985_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24990_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x(MUX,24989)@194
    assign leftShiftStage2_uid24990_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24990_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_s or leftShiftStage1_uid24985_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid24988_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24990_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid24990_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q = leftShiftStage1_uid24985_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid24990_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid24988_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid24990_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_91_c_compstr2567_vt_select_28(BITSELECT,9394)@194
    assign i_shl_i_i_i_i_i77_i_91_c_compstr2567_vt_select_28_b = leftShiftStage2_uid24990_i_shl_i_i_i_i_i77_i_91_c_compstr0_shift_x_q[28:13];

    // redist392_i_shl_i_i_i_i_i77_i_91_c_compstr2567_vt_select_28_b_1(DELAY,28620)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist392_i_shl_i_i_i_i_i77_i_91_c_compstr2567_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_91_c_compstr2567_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_91_c_compstr2567_vt_join(BITJOIN,9393)@195
    assign i_shl_i_i_i_i_i77_i_91_c_compstr2567_vt_join_q = {redist392_i_shl_i_i_i_i_i77_i_91_c_compstr2567_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma(CHAINMULTADD,28216)@189 + 5
    // out q@195
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ah[0] <= redist953_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_183_tpl_181_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ah[1] <= redist952_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_182_tpl_181_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ch[0] <= redist699_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_183_tpl_181_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ch[1] <= redist698_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_182_tpl_181_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568(ADD,8512)@195
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compstr2563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compstr2565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compstr2564_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_91_c_compstr2567_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_91_c_compstr2567_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_o[33:0];

    // rightShiftStage0_uid20580_dupName_363_i_unnamed_c_compstr0_shift_x(MUX,20579)@195
    assign rightShiftStage0_uid20580_dupName_363_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20580_dupName_363_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_q or rightShiftStage0Idx1_uid20578_dupName_363_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20580_dupName_363_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20580_dupName_363_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_q;
            1'b1 : rightShiftStage0_uid20580_dupName_363_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20578_dupName_363_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20580_dupName_363_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20585_dupName_363_i_unnamed_c_compstr0_shift_x(MUX,20584)@195
    assign rightShiftStage1_uid20585_dupName_363_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20585_dupName_363_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20580_dupName_363_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20583_dupName_363_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20585_dupName_363_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20585_dupName_363_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20580_dupName_363_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20585_dupName_363_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20583_dupName_363_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20585_dupName_363_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20590_dupName_363_i_unnamed_c_compstr0_shift_x(MUX,20589)@195
    assign rightShiftStage2_uid20590_dupName_363_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20590_dupName_363_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20585_dupName_363_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20588_dupName_363_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20590_dupName_363_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20590_dupName_363_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20585_dupName_363_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20590_dupName_363_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20588_dupName_363_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20590_dupName_363_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2569_vt_select_20(BITSELECT,11161)@195
    assign i_unnamed_c_compstr2569_vt_select_20_b = rightShiftStage2_uid20590_dupName_363_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2569_vt_join(BITJOIN,11160)@195
    assign i_unnamed_c_compstr2569_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2569_vt_select_20_b};

    // i_conv_i_i_i_i97_i_91_c_compstr2570_sel_x(BITSELECT,3574)@195
    assign i_conv_i_i_i_i97_i_91_c_compstr2570_sel_x_b = i_unnamed_c_compstr2569_vt_join_q[15:0];

    // redist1162_i_conv_i_i_i_i97_i_91_c_compstr2570_sel_x_b_1(DELAY,29390)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1162_i_conv_i_i_i_i97_i_91_c_compstr2570_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_91_c_compstr2570_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20599_dupName_364_i_unnamed_c_compstr0_shift_x(BITSELECT,20598)@195
    assign rightShiftStage1Idx1Rng8_uid20599_dupName_364_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20598_dupName_364_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20601_dupName_364_i_unnamed_c_compstr0_shift_x(BITJOIN,20600)@195
    assign rightShiftStage1Idx1_uid20601_dupName_364_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20599_dupName_364_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20594_dupName_364_i_unnamed_c_compstr0_shift_x(BITSELECT,20593)@195
    assign rightShiftStage0Idx1Rng4_uid20594_dupName_364_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_q[33:4];

    // rightShiftStage0Idx1_uid20596_dupName_364_i_unnamed_c_compstr0_shift_x(BITJOIN,20595)@195
    assign rightShiftStage0Idx1_uid20596_dupName_364_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20594_dupName_364_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20598_dupName_364_i_unnamed_c_compstr0_shift_x(MUX,20597)@195
    assign rightShiftStage0_uid20598_dupName_364_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20598_dupName_364_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_q or rightShiftStage0Idx1_uid20596_dupName_364_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20598_dupName_364_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20598_dupName_364_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compstr2568_q;
            1'b1 : rightShiftStage0_uid20598_dupName_364_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20596_dupName_364_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20598_dupName_364_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20603_dupName_364_i_unnamed_c_compstr0_shift_x(MUX,20602)@195
    assign rightShiftStage1_uid20603_dupName_364_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20603_dupName_364_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20598_dupName_364_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20601_dupName_364_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20603_dupName_364_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20603_dupName_364_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20598_dupName_364_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20603_dupName_364_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20601_dupName_364_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20603_dupName_364_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2571_vt_select_21(BITSELECT,11164)@195
    assign i_unnamed_c_compstr2571_vt_select_21_b = rightShiftStage1_uid20603_dupName_364_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2571_vt_join(BITJOIN,11163)@195
    assign i_unnamed_c_compstr2571_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2571_vt_select_21_b};

    // i_unnamed_c_compstr2572_sel_x(BITSELECT,6158)@195
    assign i_unnamed_c_compstr2572_sel_x_b = i_unnamed_c_compstr2571_vt_join_q[15:0];

    // i_unnamed_c_compstr2573_BitSelect_for_a(BITSELECT,27705)@195
    assign i_unnamed_c_compstr2573_BitSelect_for_a_b = i_unnamed_c_compstr2572_sel_x_b[0:0];

    // i_unnamed_c_compstr2573_join(BITJOIN,27706)@195
    assign i_unnamed_c_compstr2573_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2573_BitSelect_for_a_b};

    // i_unnamed_c_compstr2573_vt_select_0(BITSELECT,11169)@195
    assign i_unnamed_c_compstr2573_vt_select_0_b = i_unnamed_c_compstr2573_join_q[0:0];

    // redist132_i_unnamed_c_compstr2573_vt_select_0_b_1(DELAY,28360)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist132_i_unnamed_c_compstr2573_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2573_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2573_vt_join(BITJOIN,11168)@196
    assign i_unnamed_c_compstr2573_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist132_i_unnamed_c_compstr2573_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_91_c_compstr2574(ADD,6969)@196
    assign i_add_i_i_i_i_i126_i_91_c_compstr2574_a = {1'b0, i_unnamed_c_compstr2573_vt_join_q};
    assign i_add_i_i_i_i_i126_i_91_c_compstr2574_b = {1'b0, redist1162_i_conv_i_i_i_i97_i_91_c_compstr2570_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_91_c_compstr2574_o = $unsigned(i_add_i_i_i_i_i126_i_91_c_compstr2574_a) + $unsigned(i_add_i_i_i_i_i126_i_91_c_compstr2574_b);
    assign i_add_i_i_i_i_i126_i_91_c_compstr2574_q = i_add_i_i_i_i_i126_i_91_c_compstr2574_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_91_c_compstr2574_sel_x(BITSELECT,2163)@196
    assign bgTrunc_i_add_i_i_i_i_i126_i_91_c_compstr2574_sel_x_b = i_add_i_i_i_i_i126_i_91_c_compstr2574_q[15:0];

    // i_conv_i_i_i_i_i75_i277_92_c_compstr2594_sel_x(BITSELECT,3704)@196
    assign i_conv_i_i_i_i_i75_i277_92_c_compstr2594_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_91_c_compstr2574_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_92_c_compstr2594_vt_select_15(BITSELECT,7717)@196
    assign i_conv_i_i_i_i_i75_i277_92_c_compstr2594_vt_select_15_b = i_conv_i_i_i_i_i75_i277_92_c_compstr2594_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_92_c_compstr2594_vt_join(BITJOIN,7716)@196
    assign i_conv_i_i_i_i_i75_i277_92_c_compstr2594_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_92_c_compstr2594_vt_select_15_b};

    // leftShiftStage0_uid24998_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x(MUX,24997)@196
    assign leftShiftStage0_uid24998_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24998_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_92_c_compstr2594_vt_join_q or leftShiftStage0Idx1_uid24996_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24998_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid24998_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_92_c_compstr2594_vt_join_q;
            1'b1 : leftShiftStage0_uid24998_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid24996_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid24998_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25003_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x(MUX,25002)@196
    assign leftShiftStage1_uid25003_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25003_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_s or leftShiftStage0_uid24998_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25001_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25003_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25003_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q = leftShiftStage0_uid24998_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25003_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25001_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25003_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25008_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x(MUX,25007)@196
    assign leftShiftStage2_uid25008_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25008_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_s or leftShiftStage1_uid25003_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25006_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25008_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25008_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q = leftShiftStage1_uid25003_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25008_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25006_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25008_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_92_c_compstr2595_vt_select_28(BITSELECT,9397)@196
    assign i_shl_i_i_i_i_i77_i_92_c_compstr2595_vt_select_28_b = leftShiftStage2_uid25008_i_shl_i_i_i_i_i77_i_92_c_compstr0_shift_x_q[28:13];

    // redist391_i_shl_i_i_i_i_i77_i_92_c_compstr2595_vt_select_28_b_1(DELAY,28619)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist391_i_shl_i_i_i_i_i77_i_92_c_compstr2595_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_92_c_compstr2595_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_92_c_compstr2595_vt_join(BITJOIN,9396)@197
    assign i_shl_i_i_i_i_i77_i_92_c_compstr2595_vt_join_q = {redist391_i_shl_i_i_i_i_i77_i_92_c_compstr2595_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma(CHAINMULTADD,28217)@191 + 5
    // out q@197
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ah[0] <= redist955_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_185_tpl_183_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ah[1] <= redist954_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_184_tpl_183_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ch[0] <= redist701_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_185_tpl_183_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ch[1] <= redist700_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_184_tpl_183_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596(ADD,8513)@197
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compstr2591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compstr2593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compstr2592_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_92_c_compstr2595_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_92_c_compstr2595_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_o[33:0];

    // rightShiftStage0_uid20642_dupName_367_i_unnamed_c_compstr0_shift_x(MUX,20641)@197
    assign rightShiftStage0_uid20642_dupName_367_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20642_dupName_367_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_q or rightShiftStage0Idx1_uid20640_dupName_367_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20642_dupName_367_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20642_dupName_367_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_q;
            1'b1 : rightShiftStage0_uid20642_dupName_367_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20640_dupName_367_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20642_dupName_367_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20647_dupName_367_i_unnamed_c_compstr0_shift_x(MUX,20646)@197
    assign rightShiftStage1_uid20647_dupName_367_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20647_dupName_367_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20642_dupName_367_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20645_dupName_367_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20647_dupName_367_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20647_dupName_367_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20642_dupName_367_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20647_dupName_367_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20645_dupName_367_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20647_dupName_367_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20652_dupName_367_i_unnamed_c_compstr0_shift_x(MUX,20651)@197
    assign rightShiftStage2_uid20652_dupName_367_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20652_dupName_367_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20647_dupName_367_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20650_dupName_367_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20652_dupName_367_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20652_dupName_367_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20647_dupName_367_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20652_dupName_367_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20650_dupName_367_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20652_dupName_367_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2597_vt_select_20(BITSELECT,11183)@197
    assign i_unnamed_c_compstr2597_vt_select_20_b = rightShiftStage2_uid20652_dupName_367_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2597_vt_join(BITJOIN,11182)@197
    assign i_unnamed_c_compstr2597_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2597_vt_select_20_b};

    // i_conv_i_i_i_i97_i_92_c_compstr2598_sel_x(BITSELECT,3575)@197
    assign i_conv_i_i_i_i97_i_92_c_compstr2598_sel_x_b = i_unnamed_c_compstr2597_vt_join_q[15:0];

    // redist1161_i_conv_i_i_i_i97_i_92_c_compstr2598_sel_x_b_1(DELAY,29389)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1161_i_conv_i_i_i_i97_i_92_c_compstr2598_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_92_c_compstr2598_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20661_dupName_368_i_unnamed_c_compstr0_shift_x(BITSELECT,20660)@197
    assign rightShiftStage1Idx1Rng8_uid20661_dupName_368_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20660_dupName_368_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20663_dupName_368_i_unnamed_c_compstr0_shift_x(BITJOIN,20662)@197
    assign rightShiftStage1Idx1_uid20663_dupName_368_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20661_dupName_368_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20656_dupName_368_i_unnamed_c_compstr0_shift_x(BITSELECT,20655)@197
    assign rightShiftStage0Idx1Rng4_uid20656_dupName_368_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_q[33:4];

    // rightShiftStage0Idx1_uid20658_dupName_368_i_unnamed_c_compstr0_shift_x(BITJOIN,20657)@197
    assign rightShiftStage0Idx1_uid20658_dupName_368_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20656_dupName_368_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20660_dupName_368_i_unnamed_c_compstr0_shift_x(MUX,20659)@197
    assign rightShiftStage0_uid20660_dupName_368_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20660_dupName_368_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_q or rightShiftStage0Idx1_uid20658_dupName_368_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20660_dupName_368_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20660_dupName_368_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compstr2596_q;
            1'b1 : rightShiftStage0_uid20660_dupName_368_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20658_dupName_368_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20660_dupName_368_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20665_dupName_368_i_unnamed_c_compstr0_shift_x(MUX,20664)@197
    assign rightShiftStage1_uid20665_dupName_368_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20665_dupName_368_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20660_dupName_368_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20663_dupName_368_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20665_dupName_368_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20665_dupName_368_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20660_dupName_368_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20665_dupName_368_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20663_dupName_368_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20665_dupName_368_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2599_vt_select_21(BITSELECT,11186)@197
    assign i_unnamed_c_compstr2599_vt_select_21_b = rightShiftStage1_uid20665_dupName_368_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2599_vt_join(BITJOIN,11185)@197
    assign i_unnamed_c_compstr2599_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2599_vt_select_21_b};

    // i_unnamed_c_compstr2600_sel_x(BITSELECT,6161)@197
    assign i_unnamed_c_compstr2600_sel_x_b = i_unnamed_c_compstr2599_vt_join_q[15:0];

    // i_unnamed_c_compstr2601_BitSelect_for_a(BITSELECT,27709)@197
    assign i_unnamed_c_compstr2601_BitSelect_for_a_b = i_unnamed_c_compstr2600_sel_x_b[0:0];

    // i_unnamed_c_compstr2601_join(BITJOIN,27710)@197
    assign i_unnamed_c_compstr2601_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2601_BitSelect_for_a_b};

    // i_unnamed_c_compstr2601_vt_select_0(BITSELECT,11194)@197
    assign i_unnamed_c_compstr2601_vt_select_0_b = i_unnamed_c_compstr2601_join_q[0:0];

    // redist130_i_unnamed_c_compstr2601_vt_select_0_b_1(DELAY,28358)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist130_i_unnamed_c_compstr2601_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2601_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2601_vt_join(BITJOIN,11193)@198
    assign i_unnamed_c_compstr2601_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist130_i_unnamed_c_compstr2601_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_92_c_compstr2602(ADD,6970)@198
    assign i_add_i_i_i_i_i126_i_92_c_compstr2602_a = {1'b0, i_unnamed_c_compstr2601_vt_join_q};
    assign i_add_i_i_i_i_i126_i_92_c_compstr2602_b = {1'b0, redist1161_i_conv_i_i_i_i97_i_92_c_compstr2598_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_92_c_compstr2602_o = $unsigned(i_add_i_i_i_i_i126_i_92_c_compstr2602_a) + $unsigned(i_add_i_i_i_i_i126_i_92_c_compstr2602_b);
    assign i_add_i_i_i_i_i126_i_92_c_compstr2602_q = i_add_i_i_i_i_i126_i_92_c_compstr2602_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_92_c_compstr2602_sel_x(BITSELECT,2164)@198
    assign bgTrunc_i_add_i_i_i_i_i126_i_92_c_compstr2602_sel_x_b = i_add_i_i_i_i_i126_i_92_c_compstr2602_q[15:0];

    // i_conv_i_i_i_i_i75_i277_93_c_compstr2622_sel_x(BITSELECT,3705)@198
    assign i_conv_i_i_i_i_i75_i277_93_c_compstr2622_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_92_c_compstr2602_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_93_c_compstr2622_vt_select_15(BITSELECT,7721)@198
    assign i_conv_i_i_i_i_i75_i277_93_c_compstr2622_vt_select_15_b = i_conv_i_i_i_i_i75_i277_93_c_compstr2622_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_93_c_compstr2622_vt_join(BITJOIN,7720)@198
    assign i_conv_i_i_i_i_i75_i277_93_c_compstr2622_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_93_c_compstr2622_vt_select_15_b};

    // leftShiftStage0_uid25016_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x(MUX,25015)@198
    assign leftShiftStage0_uid25016_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25016_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_93_c_compstr2622_vt_join_q or leftShiftStage0Idx1_uid25014_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25016_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25016_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_93_c_compstr2622_vt_join_q;
            1'b1 : leftShiftStage0_uid25016_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25014_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25016_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25021_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x(MUX,25020)@198
    assign leftShiftStage1_uid25021_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25021_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_s or leftShiftStage0_uid25016_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25019_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25021_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25021_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q = leftShiftStage0_uid25016_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25021_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25019_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25021_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25026_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x(MUX,25025)@198
    assign leftShiftStage2_uid25026_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25026_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_s or leftShiftStage1_uid25021_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25024_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25026_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25026_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q = leftShiftStage1_uid25021_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25026_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25024_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25026_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_93_c_compstr2623_vt_select_28(BITSELECT,9400)@198
    assign i_shl_i_i_i_i_i77_i_93_c_compstr2623_vt_select_28_b = leftShiftStage2_uid25026_i_shl_i_i_i_i_i77_i_93_c_compstr0_shift_x_q[28:13];

    // redist390_i_shl_i_i_i_i_i77_i_93_c_compstr2623_vt_select_28_b_1(DELAY,28618)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist390_i_shl_i_i_i_i_i77_i_93_c_compstr2623_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_93_c_compstr2623_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_93_c_compstr2623_vt_join(BITJOIN,9399)@199
    assign i_shl_i_i_i_i_i77_i_93_c_compstr2623_vt_join_q = {redist390_i_shl_i_i_i_i_i77_i_93_c_compstr2623_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma(CHAINMULTADD,28218)@193 + 5
    // out q@199
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ah[0] <= redist957_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_187_tpl_185_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ah[1] <= redist956_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_186_tpl_185_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ch[0] <= redist703_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_187_tpl_185_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ch[1] <= redist702_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_186_tpl_185_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624(ADD,8514)@199
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compstr2619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compstr2621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compstr2620_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_93_c_compstr2623_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_93_c_compstr2623_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_o[33:0];

    // rightShiftStage0_uid20704_dupName_371_i_unnamed_c_compstr0_shift_x(MUX,20703)@199
    assign rightShiftStage0_uid20704_dupName_371_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20704_dupName_371_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_q or rightShiftStage0Idx1_uid20702_dupName_371_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20704_dupName_371_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20704_dupName_371_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_q;
            1'b1 : rightShiftStage0_uid20704_dupName_371_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20702_dupName_371_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20704_dupName_371_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20709_dupName_371_i_unnamed_c_compstr0_shift_x(MUX,20708)@199
    assign rightShiftStage1_uid20709_dupName_371_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20709_dupName_371_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20704_dupName_371_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20707_dupName_371_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20709_dupName_371_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20709_dupName_371_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20704_dupName_371_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20709_dupName_371_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20707_dupName_371_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20709_dupName_371_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20714_dupName_371_i_unnamed_c_compstr0_shift_x(MUX,20713)@199
    assign rightShiftStage2_uid20714_dupName_371_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20714_dupName_371_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20709_dupName_371_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20712_dupName_371_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20714_dupName_371_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20714_dupName_371_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20709_dupName_371_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20714_dupName_371_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20712_dupName_371_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20714_dupName_371_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2625_vt_select_20(BITSELECT,11211)@199
    assign i_unnamed_c_compstr2625_vt_select_20_b = rightShiftStage2_uid20714_dupName_371_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2625_vt_join(BITJOIN,11210)@199
    assign i_unnamed_c_compstr2625_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2625_vt_select_20_b};

    // i_conv_i_i_i_i97_i_93_c_compstr2626_sel_x(BITSELECT,3576)@199
    assign i_conv_i_i_i_i97_i_93_c_compstr2626_sel_x_b = i_unnamed_c_compstr2625_vt_join_q[15:0];

    // redist1160_i_conv_i_i_i_i97_i_93_c_compstr2626_sel_x_b_1(DELAY,29388)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1160_i_conv_i_i_i_i97_i_93_c_compstr2626_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_93_c_compstr2626_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20723_dupName_372_i_unnamed_c_compstr0_shift_x(BITSELECT,20722)@199
    assign rightShiftStage1Idx1Rng8_uid20723_dupName_372_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20722_dupName_372_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20725_dupName_372_i_unnamed_c_compstr0_shift_x(BITJOIN,20724)@199
    assign rightShiftStage1Idx1_uid20725_dupName_372_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20723_dupName_372_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20718_dupName_372_i_unnamed_c_compstr0_shift_x(BITSELECT,20717)@199
    assign rightShiftStage0Idx1Rng4_uid20718_dupName_372_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_q[33:4];

    // rightShiftStage0Idx1_uid20720_dupName_372_i_unnamed_c_compstr0_shift_x(BITJOIN,20719)@199
    assign rightShiftStage0Idx1_uid20720_dupName_372_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20718_dupName_372_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20722_dupName_372_i_unnamed_c_compstr0_shift_x(MUX,20721)@199
    assign rightShiftStage0_uid20722_dupName_372_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20722_dupName_372_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_q or rightShiftStage0Idx1_uid20720_dupName_372_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20722_dupName_372_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20722_dupName_372_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compstr2624_q;
            1'b1 : rightShiftStage0_uid20722_dupName_372_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20720_dupName_372_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20722_dupName_372_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20727_dupName_372_i_unnamed_c_compstr0_shift_x(MUX,20726)@199
    assign rightShiftStage1_uid20727_dupName_372_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20727_dupName_372_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20722_dupName_372_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20725_dupName_372_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20727_dupName_372_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20727_dupName_372_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20722_dupName_372_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20727_dupName_372_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20725_dupName_372_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20727_dupName_372_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2627_vt_select_21(BITSELECT,11214)@199
    assign i_unnamed_c_compstr2627_vt_select_21_b = rightShiftStage1_uid20727_dupName_372_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2627_vt_join(BITJOIN,11213)@199
    assign i_unnamed_c_compstr2627_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2627_vt_select_21_b};

    // i_unnamed_c_compstr2628_sel_x(BITSELECT,6163)@199
    assign i_unnamed_c_compstr2628_sel_x_b = i_unnamed_c_compstr2627_vt_join_q[15:0];

    // i_unnamed_c_compstr2629_BitSelect_for_a(BITSELECT,27713)@199
    assign i_unnamed_c_compstr2629_BitSelect_for_a_b = i_unnamed_c_compstr2628_sel_x_b[0:0];

    // i_unnamed_c_compstr2629_join(BITJOIN,27714)@199
    assign i_unnamed_c_compstr2629_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2629_BitSelect_for_a_b};

    // i_unnamed_c_compstr2629_vt_select_0(BITSELECT,11219)@199
    assign i_unnamed_c_compstr2629_vt_select_0_b = i_unnamed_c_compstr2629_join_q[0:0];

    // redist128_i_unnamed_c_compstr2629_vt_select_0_b_1(DELAY,28356)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist128_i_unnamed_c_compstr2629_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2629_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2629_vt_join(BITJOIN,11218)@200
    assign i_unnamed_c_compstr2629_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist128_i_unnamed_c_compstr2629_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_93_c_compstr2630(ADD,6971)@200
    assign i_add_i_i_i_i_i126_i_93_c_compstr2630_a = {1'b0, i_unnamed_c_compstr2629_vt_join_q};
    assign i_add_i_i_i_i_i126_i_93_c_compstr2630_b = {1'b0, redist1160_i_conv_i_i_i_i97_i_93_c_compstr2626_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_93_c_compstr2630_o = $unsigned(i_add_i_i_i_i_i126_i_93_c_compstr2630_a) + $unsigned(i_add_i_i_i_i_i126_i_93_c_compstr2630_b);
    assign i_add_i_i_i_i_i126_i_93_c_compstr2630_q = i_add_i_i_i_i_i126_i_93_c_compstr2630_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_93_c_compstr2630_sel_x(BITSELECT,2165)@200
    assign bgTrunc_i_add_i_i_i_i_i126_i_93_c_compstr2630_sel_x_b = i_add_i_i_i_i_i126_i_93_c_compstr2630_q[15:0];

    // i_conv_i_i_i_i_i75_i277_94_c_compstr2650_sel_x(BITSELECT,3706)@200
    assign i_conv_i_i_i_i_i75_i277_94_c_compstr2650_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_93_c_compstr2630_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_94_c_compstr2650_vt_select_15(BITSELECT,7725)@200
    assign i_conv_i_i_i_i_i75_i277_94_c_compstr2650_vt_select_15_b = i_conv_i_i_i_i_i75_i277_94_c_compstr2650_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_94_c_compstr2650_vt_join(BITJOIN,7724)@200
    assign i_conv_i_i_i_i_i75_i277_94_c_compstr2650_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_94_c_compstr2650_vt_select_15_b};

    // leftShiftStage0_uid25034_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x(MUX,25033)@200
    assign leftShiftStage0_uid25034_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25034_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_94_c_compstr2650_vt_join_q or leftShiftStage0Idx1_uid25032_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25034_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25034_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_94_c_compstr2650_vt_join_q;
            1'b1 : leftShiftStage0_uid25034_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25032_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25034_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25039_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x(MUX,25038)@200
    assign leftShiftStage1_uid25039_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25039_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_s or leftShiftStage0_uid25034_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25037_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25039_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25039_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q = leftShiftStage0_uid25034_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25039_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25037_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25039_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25044_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x(MUX,25043)@200
    assign leftShiftStage2_uid25044_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25044_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_s or leftShiftStage1_uid25039_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25042_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25044_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25044_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q = leftShiftStage1_uid25039_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25044_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25042_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25044_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_94_c_compstr2651_vt_select_28(BITSELECT,9403)@200
    assign i_shl_i_i_i_i_i77_i_94_c_compstr2651_vt_select_28_b = leftShiftStage2_uid25044_i_shl_i_i_i_i_i77_i_94_c_compstr0_shift_x_q[28:13];

    // redist389_i_shl_i_i_i_i_i77_i_94_c_compstr2651_vt_select_28_b_1(DELAY,28617)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist389_i_shl_i_i_i_i_i77_i_94_c_compstr2651_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_94_c_compstr2651_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_94_c_compstr2651_vt_join(BITJOIN,9402)@201
    assign i_shl_i_i_i_i_i77_i_94_c_compstr2651_vt_join_q = {redist389_i_shl_i_i_i_i_i77_i_94_c_compstr2651_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma(CHAINMULTADD,28219)@195 + 5
    // out q@201
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ah[0] <= redist959_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_189_tpl_187_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ah[1] <= redist958_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_188_tpl_187_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ch[0] <= redist705_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_189_tpl_187_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ch[1] <= redist704_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_188_tpl_187_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652(ADD,8515)@201
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compstr2647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compstr2649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compstr2648_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_94_c_compstr2651_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_94_c_compstr2651_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_o[33:0];

    // rightShiftStage0_uid20766_dupName_375_i_unnamed_c_compstr0_shift_x(MUX,20765)@201
    assign rightShiftStage0_uid20766_dupName_375_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20766_dupName_375_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_q or rightShiftStage0Idx1_uid20764_dupName_375_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20766_dupName_375_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20766_dupName_375_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_q;
            1'b1 : rightShiftStage0_uid20766_dupName_375_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20764_dupName_375_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20766_dupName_375_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20771_dupName_375_i_unnamed_c_compstr0_shift_x(MUX,20770)@201
    assign rightShiftStage1_uid20771_dupName_375_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20771_dupName_375_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20766_dupName_375_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20769_dupName_375_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20771_dupName_375_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20771_dupName_375_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20766_dupName_375_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20771_dupName_375_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20769_dupName_375_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20771_dupName_375_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20776_dupName_375_i_unnamed_c_compstr0_shift_x(MUX,20775)@201
    assign rightShiftStage2_uid20776_dupName_375_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20776_dupName_375_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20771_dupName_375_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20774_dupName_375_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20776_dupName_375_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20776_dupName_375_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20771_dupName_375_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20776_dupName_375_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20774_dupName_375_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20776_dupName_375_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2653_vt_select_20(BITSELECT,11238)@201
    assign i_unnamed_c_compstr2653_vt_select_20_b = rightShiftStage2_uid20776_dupName_375_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2653_vt_join(BITJOIN,11237)@201
    assign i_unnamed_c_compstr2653_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2653_vt_select_20_b};

    // i_conv_i_i_i_i97_i_94_c_compstr2654_sel_x(BITSELECT,3577)@201
    assign i_conv_i_i_i_i97_i_94_c_compstr2654_sel_x_b = i_unnamed_c_compstr2653_vt_join_q[15:0];

    // redist1159_i_conv_i_i_i_i97_i_94_c_compstr2654_sel_x_b_1(DELAY,29387)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1159_i_conv_i_i_i_i97_i_94_c_compstr2654_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_94_c_compstr2654_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20785_dupName_376_i_unnamed_c_compstr0_shift_x(BITSELECT,20784)@201
    assign rightShiftStage1Idx1Rng8_uid20785_dupName_376_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20784_dupName_376_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20787_dupName_376_i_unnamed_c_compstr0_shift_x(BITJOIN,20786)@201
    assign rightShiftStage1Idx1_uid20787_dupName_376_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20785_dupName_376_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20780_dupName_376_i_unnamed_c_compstr0_shift_x(BITSELECT,20779)@201
    assign rightShiftStage0Idx1Rng4_uid20780_dupName_376_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_q[33:4];

    // rightShiftStage0Idx1_uid20782_dupName_376_i_unnamed_c_compstr0_shift_x(BITJOIN,20781)@201
    assign rightShiftStage0Idx1_uid20782_dupName_376_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20780_dupName_376_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20784_dupName_376_i_unnamed_c_compstr0_shift_x(MUX,20783)@201
    assign rightShiftStage0_uid20784_dupName_376_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20784_dupName_376_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_q or rightShiftStage0Idx1_uid20782_dupName_376_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20784_dupName_376_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20784_dupName_376_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compstr2652_q;
            1'b1 : rightShiftStage0_uid20784_dupName_376_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20782_dupName_376_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20784_dupName_376_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20789_dupName_376_i_unnamed_c_compstr0_shift_x(MUX,20788)@201
    assign rightShiftStage1_uid20789_dupName_376_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20789_dupName_376_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20784_dupName_376_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20787_dupName_376_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20789_dupName_376_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20789_dupName_376_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20784_dupName_376_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20789_dupName_376_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20787_dupName_376_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20789_dupName_376_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2655_vt_select_21(BITSELECT,11241)@201
    assign i_unnamed_c_compstr2655_vt_select_21_b = rightShiftStage1_uid20789_dupName_376_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2655_vt_join(BITJOIN,11240)@201
    assign i_unnamed_c_compstr2655_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2655_vt_select_21_b};

    // i_unnamed_c_compstr2656_sel_x(BITSELECT,6166)@201
    assign i_unnamed_c_compstr2656_sel_x_b = i_unnamed_c_compstr2655_vt_join_q[15:0];

    // i_unnamed_c_compstr2657_BitSelect_for_a(BITSELECT,27719)@201
    assign i_unnamed_c_compstr2657_BitSelect_for_a_b = i_unnamed_c_compstr2656_sel_x_b[0:0];

    // i_unnamed_c_compstr2657_join(BITJOIN,27720)@201
    assign i_unnamed_c_compstr2657_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2657_BitSelect_for_a_b};

    // i_unnamed_c_compstr2657_vt_select_0(BITSELECT,11246)@201
    assign i_unnamed_c_compstr2657_vt_select_0_b = i_unnamed_c_compstr2657_join_q[0:0];

    // redist126_i_unnamed_c_compstr2657_vt_select_0_b_1(DELAY,28354)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist126_i_unnamed_c_compstr2657_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2657_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2657_vt_join(BITJOIN,11245)@202
    assign i_unnamed_c_compstr2657_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist126_i_unnamed_c_compstr2657_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_94_c_compstr2658(ADD,6972)@202
    assign i_add_i_i_i_i_i126_i_94_c_compstr2658_a = {1'b0, i_unnamed_c_compstr2657_vt_join_q};
    assign i_add_i_i_i_i_i126_i_94_c_compstr2658_b = {1'b0, redist1159_i_conv_i_i_i_i97_i_94_c_compstr2654_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_94_c_compstr2658_o = $unsigned(i_add_i_i_i_i_i126_i_94_c_compstr2658_a) + $unsigned(i_add_i_i_i_i_i126_i_94_c_compstr2658_b);
    assign i_add_i_i_i_i_i126_i_94_c_compstr2658_q = i_add_i_i_i_i_i126_i_94_c_compstr2658_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_94_c_compstr2658_sel_x(BITSELECT,2166)@202
    assign bgTrunc_i_add_i_i_i_i_i126_i_94_c_compstr2658_sel_x_b = i_add_i_i_i_i_i126_i_94_c_compstr2658_q[15:0];

    // i_conv_i_i_i_i_i75_i277_95_c_compstr2678_sel_x(BITSELECT,3707)@202
    assign i_conv_i_i_i_i_i75_i277_95_c_compstr2678_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_94_c_compstr2658_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_95_c_compstr2678_vt_select_15(BITSELECT,7729)@202
    assign i_conv_i_i_i_i_i75_i277_95_c_compstr2678_vt_select_15_b = i_conv_i_i_i_i_i75_i277_95_c_compstr2678_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_95_c_compstr2678_vt_join(BITJOIN,7728)@202
    assign i_conv_i_i_i_i_i75_i277_95_c_compstr2678_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_95_c_compstr2678_vt_select_15_b};

    // leftShiftStage0_uid25052_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x(MUX,25051)@202
    assign leftShiftStage0_uid25052_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25052_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_95_c_compstr2678_vt_join_q or leftShiftStage0Idx1_uid25050_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25052_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25052_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_95_c_compstr2678_vt_join_q;
            1'b1 : leftShiftStage0_uid25052_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25050_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25052_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25057_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x(MUX,25056)@202
    assign leftShiftStage1_uid25057_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25057_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_s or leftShiftStage0_uid25052_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25055_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25057_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25057_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q = leftShiftStage0_uid25052_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25057_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25055_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25057_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25062_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x(MUX,25061)@202
    assign leftShiftStage2_uid25062_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25062_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_s or leftShiftStage1_uid25057_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25060_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25062_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25062_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q = leftShiftStage1_uid25057_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25062_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25060_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25062_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_95_c_compstr2679_vt_select_28(BITSELECT,9406)@202
    assign i_shl_i_i_i_i_i77_i_95_c_compstr2679_vt_select_28_b = leftShiftStage2_uid25062_i_shl_i_i_i_i_i77_i_95_c_compstr0_shift_x_q[28:13];

    // redist388_i_shl_i_i_i_i_i77_i_95_c_compstr2679_vt_select_28_b_1(DELAY,28616)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist388_i_shl_i_i_i_i_i77_i_95_c_compstr2679_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_95_c_compstr2679_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_95_c_compstr2679_vt_join(BITJOIN,9405)@203
    assign i_shl_i_i_i_i_i77_i_95_c_compstr2679_vt_join_q = {redist388_i_shl_i_i_i_i_i77_i_95_c_compstr2679_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma(CHAINMULTADD,28220)@197 + 5
    // out q@203
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ah[0] <= redist961_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_191_tpl_189_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ah[1] <= redist960_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_190_tpl_189_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ch[0] <= redist707_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_191_tpl_189_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ch[1] <= redist706_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_190_tpl_189_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680(ADD,8516)@203
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compstr2675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compstr2677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compstr2676_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_95_c_compstr2679_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_95_c_compstr2679_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_o[33:0];

    // rightShiftStage0_uid20828_dupName_379_i_unnamed_c_compstr0_shift_x(MUX,20827)@203
    assign rightShiftStage0_uid20828_dupName_379_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20828_dupName_379_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_q or rightShiftStage0Idx1_uid20826_dupName_379_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20828_dupName_379_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20828_dupName_379_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_q;
            1'b1 : rightShiftStage0_uid20828_dupName_379_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20826_dupName_379_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20828_dupName_379_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20833_dupName_379_i_unnamed_c_compstr0_shift_x(MUX,20832)@203
    assign rightShiftStage1_uid20833_dupName_379_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20833_dupName_379_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20828_dupName_379_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20831_dupName_379_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20833_dupName_379_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20833_dupName_379_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20828_dupName_379_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20833_dupName_379_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20831_dupName_379_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20833_dupName_379_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20838_dupName_379_i_unnamed_c_compstr0_shift_x(MUX,20837)@203
    assign rightShiftStage2_uid20838_dupName_379_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20838_dupName_379_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20833_dupName_379_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20836_dupName_379_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20838_dupName_379_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20838_dupName_379_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20833_dupName_379_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20838_dupName_379_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20836_dupName_379_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20838_dupName_379_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2681_vt_select_20(BITSELECT,11263)@203
    assign i_unnamed_c_compstr2681_vt_select_20_b = rightShiftStage2_uid20838_dupName_379_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2681_vt_join(BITJOIN,11262)@203
    assign i_unnamed_c_compstr2681_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2681_vt_select_20_b};

    // i_conv_i_i_i_i97_i_95_c_compstr2682_sel_x(BITSELECT,3578)@203
    assign i_conv_i_i_i_i97_i_95_c_compstr2682_sel_x_b = i_unnamed_c_compstr2681_vt_join_q[15:0];

    // redist1158_i_conv_i_i_i_i97_i_95_c_compstr2682_sel_x_b_1(DELAY,29386)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1158_i_conv_i_i_i_i97_i_95_c_compstr2682_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_95_c_compstr2682_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20847_dupName_380_i_unnamed_c_compstr0_shift_x(BITSELECT,20846)@203
    assign rightShiftStage1Idx1Rng8_uid20847_dupName_380_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20846_dupName_380_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20849_dupName_380_i_unnamed_c_compstr0_shift_x(BITJOIN,20848)@203
    assign rightShiftStage1Idx1_uid20849_dupName_380_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20847_dupName_380_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20842_dupName_380_i_unnamed_c_compstr0_shift_x(BITSELECT,20841)@203
    assign rightShiftStage0Idx1Rng4_uid20842_dupName_380_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_q[33:4];

    // rightShiftStage0Idx1_uid20844_dupName_380_i_unnamed_c_compstr0_shift_x(BITJOIN,20843)@203
    assign rightShiftStage0Idx1_uid20844_dupName_380_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20842_dupName_380_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20846_dupName_380_i_unnamed_c_compstr0_shift_x(MUX,20845)@203
    assign rightShiftStage0_uid20846_dupName_380_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20846_dupName_380_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_q or rightShiftStage0Idx1_uid20844_dupName_380_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20846_dupName_380_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20846_dupName_380_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compstr2680_q;
            1'b1 : rightShiftStage0_uid20846_dupName_380_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20844_dupName_380_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20846_dupName_380_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20851_dupName_380_i_unnamed_c_compstr0_shift_x(MUX,20850)@203
    assign rightShiftStage1_uid20851_dupName_380_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20851_dupName_380_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20846_dupName_380_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20849_dupName_380_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20851_dupName_380_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20851_dupName_380_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20846_dupName_380_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20851_dupName_380_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20849_dupName_380_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20851_dupName_380_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2683_vt_select_21(BITSELECT,11266)@203
    assign i_unnamed_c_compstr2683_vt_select_21_b = rightShiftStage1_uid20851_dupName_380_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2683_vt_join(BITJOIN,11265)@203
    assign i_unnamed_c_compstr2683_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2683_vt_select_21_b};

    // i_unnamed_c_compstr2684_sel_x(BITSELECT,6168)@203
    assign i_unnamed_c_compstr2684_sel_x_b = i_unnamed_c_compstr2683_vt_join_q[15:0];

    // i_unnamed_c_compstr2685_BitSelect_for_a(BITSELECT,27723)@203
    assign i_unnamed_c_compstr2685_BitSelect_for_a_b = i_unnamed_c_compstr2684_sel_x_b[0:0];

    // i_unnamed_c_compstr2685_join(BITJOIN,27724)@203
    assign i_unnamed_c_compstr2685_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2685_BitSelect_for_a_b};

    // i_unnamed_c_compstr2685_vt_select_0(BITSELECT,11271)@203
    assign i_unnamed_c_compstr2685_vt_select_0_b = i_unnamed_c_compstr2685_join_q[0:0];

    // redist123_i_unnamed_c_compstr2685_vt_select_0_b_1(DELAY,28351)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist123_i_unnamed_c_compstr2685_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2685_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2685_vt_join(BITJOIN,11270)@204
    assign i_unnamed_c_compstr2685_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist123_i_unnamed_c_compstr2685_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_95_c_compstr2686(ADD,6973)@204
    assign i_add_i_i_i_i_i126_i_95_c_compstr2686_a = {1'b0, i_unnamed_c_compstr2685_vt_join_q};
    assign i_add_i_i_i_i_i126_i_95_c_compstr2686_b = {1'b0, redist1158_i_conv_i_i_i_i97_i_95_c_compstr2682_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_95_c_compstr2686_o = $unsigned(i_add_i_i_i_i_i126_i_95_c_compstr2686_a) + $unsigned(i_add_i_i_i_i_i126_i_95_c_compstr2686_b);
    assign i_add_i_i_i_i_i126_i_95_c_compstr2686_q = i_add_i_i_i_i_i126_i_95_c_compstr2686_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_95_c_compstr2686_sel_x(BITSELECT,2167)@204
    assign bgTrunc_i_add_i_i_i_i_i126_i_95_c_compstr2686_sel_x_b = i_add_i_i_i_i_i126_i_95_c_compstr2686_q[15:0];

    // i_conv_i_i_i_i_i75_i277_96_c_compstr2706_sel_x(BITSELECT,3708)@204
    assign i_conv_i_i_i_i_i75_i277_96_c_compstr2706_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_95_c_compstr2686_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_96_c_compstr2706_vt_select_15(BITSELECT,7733)@204
    assign i_conv_i_i_i_i_i75_i277_96_c_compstr2706_vt_select_15_b = i_conv_i_i_i_i_i75_i277_96_c_compstr2706_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_96_c_compstr2706_vt_join(BITJOIN,7732)@204
    assign i_conv_i_i_i_i_i75_i277_96_c_compstr2706_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_96_c_compstr2706_vt_select_15_b};

    // leftShiftStage0_uid25070_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x(MUX,25069)@204
    assign leftShiftStage0_uid25070_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25070_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_96_c_compstr2706_vt_join_q or leftShiftStage0Idx1_uid25068_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25070_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25070_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_96_c_compstr2706_vt_join_q;
            1'b1 : leftShiftStage0_uid25070_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25068_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25070_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25075_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x(MUX,25074)@204
    assign leftShiftStage1_uid25075_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25075_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_s or leftShiftStage0_uid25070_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25073_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25075_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25075_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q = leftShiftStage0_uid25070_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25075_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25073_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25075_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25080_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x(MUX,25079)@204
    assign leftShiftStage2_uid25080_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25080_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_s or leftShiftStage1_uid25075_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25078_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25080_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25080_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q = leftShiftStage1_uid25075_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25080_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25078_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25080_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_96_c_compstr2707_vt_select_28(BITSELECT,9409)@204
    assign i_shl_i_i_i_i_i77_i_96_c_compstr2707_vt_select_28_b = leftShiftStage2_uid25080_i_shl_i_i_i_i_i77_i_96_c_compstr0_shift_x_q[28:13];

    // redist387_i_shl_i_i_i_i_i77_i_96_c_compstr2707_vt_select_28_b_1(DELAY,28615)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist387_i_shl_i_i_i_i_i77_i_96_c_compstr2707_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_96_c_compstr2707_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_96_c_compstr2707_vt_join(BITJOIN,9408)@205
    assign i_shl_i_i_i_i_i77_i_96_c_compstr2707_vt_join_q = {redist387_i_shl_i_i_i_i_i77_i_96_c_compstr2707_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma(CHAINMULTADD,28221)@199 + 5
    // out q@205
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ah[0] <= redist963_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_193_tpl_191_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ah[1] <= redist962_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_192_tpl_191_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ch[0] <= redist709_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_193_tpl_191_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ch[1] <= redist708_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_192_tpl_191_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708(ADD,8517)@205
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compstr2703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compstr2705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compstr2704_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_96_c_compstr2707_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_96_c_compstr2707_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_o[33:0];

    // rightShiftStage0_uid20890_dupName_383_i_unnamed_c_compstr0_shift_x(MUX,20889)@205
    assign rightShiftStage0_uid20890_dupName_383_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20890_dupName_383_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_q or rightShiftStage0Idx1_uid20888_dupName_383_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20890_dupName_383_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20890_dupName_383_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_q;
            1'b1 : rightShiftStage0_uid20890_dupName_383_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20888_dupName_383_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20890_dupName_383_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20895_dupName_383_i_unnamed_c_compstr0_shift_x(MUX,20894)@205
    assign rightShiftStage1_uid20895_dupName_383_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20895_dupName_383_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20890_dupName_383_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20893_dupName_383_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20895_dupName_383_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20895_dupName_383_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20890_dupName_383_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20895_dupName_383_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20893_dupName_383_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20895_dupName_383_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20900_dupName_383_i_unnamed_c_compstr0_shift_x(MUX,20899)@205
    assign rightShiftStage2_uid20900_dupName_383_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20900_dupName_383_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20895_dupName_383_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20898_dupName_383_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20900_dupName_383_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20900_dupName_383_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20895_dupName_383_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20900_dupName_383_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20898_dupName_383_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20900_dupName_383_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2709_vt_select_20(BITSELECT,11287)@205
    assign i_unnamed_c_compstr2709_vt_select_20_b = rightShiftStage2_uid20900_dupName_383_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2709_vt_join(BITJOIN,11286)@205
    assign i_unnamed_c_compstr2709_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2709_vt_select_20_b};

    // i_conv_i_i_i_i97_i_96_c_compstr2710_sel_x(BITSELECT,3579)@205
    assign i_conv_i_i_i_i97_i_96_c_compstr2710_sel_x_b = i_unnamed_c_compstr2709_vt_join_q[15:0];

    // redist1157_i_conv_i_i_i_i97_i_96_c_compstr2710_sel_x_b_1(DELAY,29385)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1157_i_conv_i_i_i_i97_i_96_c_compstr2710_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_96_c_compstr2710_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20909_dupName_384_i_unnamed_c_compstr0_shift_x(BITSELECT,20908)@205
    assign rightShiftStage1Idx1Rng8_uid20909_dupName_384_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20908_dupName_384_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20911_dupName_384_i_unnamed_c_compstr0_shift_x(BITJOIN,20910)@205
    assign rightShiftStage1Idx1_uid20911_dupName_384_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20909_dupName_384_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20904_dupName_384_i_unnamed_c_compstr0_shift_x(BITSELECT,20903)@205
    assign rightShiftStage0Idx1Rng4_uid20904_dupName_384_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_q[33:4];

    // rightShiftStage0Idx1_uid20906_dupName_384_i_unnamed_c_compstr0_shift_x(BITJOIN,20905)@205
    assign rightShiftStage0Idx1_uid20906_dupName_384_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20904_dupName_384_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20908_dupName_384_i_unnamed_c_compstr0_shift_x(MUX,20907)@205
    assign rightShiftStage0_uid20908_dupName_384_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20908_dupName_384_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_q or rightShiftStage0Idx1_uid20906_dupName_384_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20908_dupName_384_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20908_dupName_384_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compstr2708_q;
            1'b1 : rightShiftStage0_uid20908_dupName_384_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20906_dupName_384_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20908_dupName_384_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20913_dupName_384_i_unnamed_c_compstr0_shift_x(MUX,20912)@205
    assign rightShiftStage1_uid20913_dupName_384_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20913_dupName_384_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20908_dupName_384_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20911_dupName_384_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20913_dupName_384_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20913_dupName_384_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20908_dupName_384_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20913_dupName_384_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20911_dupName_384_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20913_dupName_384_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2711_vt_select_21(BITSELECT,11290)@205
    assign i_unnamed_c_compstr2711_vt_select_21_b = rightShiftStage1_uid20913_dupName_384_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2711_vt_join(BITJOIN,11289)@205
    assign i_unnamed_c_compstr2711_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2711_vt_select_21_b};

    // i_unnamed_c_compstr2712_sel_x(BITSELECT,6170)@205
    assign i_unnamed_c_compstr2712_sel_x_b = i_unnamed_c_compstr2711_vt_join_q[15:0];

    // i_unnamed_c_compstr2713_BitSelect_for_a(BITSELECT,27729)@205
    assign i_unnamed_c_compstr2713_BitSelect_for_a_b = i_unnamed_c_compstr2712_sel_x_b[0:0];

    // i_unnamed_c_compstr2713_join(BITJOIN,27730)@205
    assign i_unnamed_c_compstr2713_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2713_BitSelect_for_a_b};

    // i_unnamed_c_compstr2713_vt_select_0(BITSELECT,11295)@205
    assign i_unnamed_c_compstr2713_vt_select_0_b = i_unnamed_c_compstr2713_join_q[0:0];

    // redist121_i_unnamed_c_compstr2713_vt_select_0_b_1(DELAY,28349)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist121_i_unnamed_c_compstr2713_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2713_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2713_vt_join(BITJOIN,11294)@206
    assign i_unnamed_c_compstr2713_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist121_i_unnamed_c_compstr2713_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_96_c_compstr2714(ADD,6974)@206
    assign i_add_i_i_i_i_i126_i_96_c_compstr2714_a = {1'b0, i_unnamed_c_compstr2713_vt_join_q};
    assign i_add_i_i_i_i_i126_i_96_c_compstr2714_b = {1'b0, redist1157_i_conv_i_i_i_i97_i_96_c_compstr2710_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_96_c_compstr2714_o = $unsigned(i_add_i_i_i_i_i126_i_96_c_compstr2714_a) + $unsigned(i_add_i_i_i_i_i126_i_96_c_compstr2714_b);
    assign i_add_i_i_i_i_i126_i_96_c_compstr2714_q = i_add_i_i_i_i_i126_i_96_c_compstr2714_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_96_c_compstr2714_sel_x(BITSELECT,2168)@206
    assign bgTrunc_i_add_i_i_i_i_i126_i_96_c_compstr2714_sel_x_b = i_add_i_i_i_i_i126_i_96_c_compstr2714_q[15:0];

    // i_conv_i_i_i_i_i75_i277_97_c_compstr2734_sel_x(BITSELECT,3709)@206
    assign i_conv_i_i_i_i_i75_i277_97_c_compstr2734_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_96_c_compstr2714_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_97_c_compstr2734_vt_select_15(BITSELECT,7737)@206
    assign i_conv_i_i_i_i_i75_i277_97_c_compstr2734_vt_select_15_b = i_conv_i_i_i_i_i75_i277_97_c_compstr2734_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_97_c_compstr2734_vt_join(BITJOIN,7736)@206
    assign i_conv_i_i_i_i_i75_i277_97_c_compstr2734_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_97_c_compstr2734_vt_select_15_b};

    // leftShiftStage0_uid25088_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x(MUX,25087)@206
    assign leftShiftStage0_uid25088_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25088_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_97_c_compstr2734_vt_join_q or leftShiftStage0Idx1_uid25086_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25088_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25088_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_97_c_compstr2734_vt_join_q;
            1'b1 : leftShiftStage0_uid25088_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25086_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25088_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25093_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x(MUX,25092)@206
    assign leftShiftStage1_uid25093_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25093_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_s or leftShiftStage0_uid25088_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25091_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25093_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25093_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q = leftShiftStage0_uid25088_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25093_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25091_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25093_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25098_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x(MUX,25097)@206
    assign leftShiftStage2_uid25098_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25098_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_s or leftShiftStage1_uid25093_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25096_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25098_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25098_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q = leftShiftStage1_uid25093_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25098_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25096_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25098_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_97_c_compstr2735_vt_select_28(BITSELECT,9412)@206
    assign i_shl_i_i_i_i_i77_i_97_c_compstr2735_vt_select_28_b = leftShiftStage2_uid25098_i_shl_i_i_i_i_i77_i_97_c_compstr0_shift_x_q[28:13];

    // redist386_i_shl_i_i_i_i_i77_i_97_c_compstr2735_vt_select_28_b_1(DELAY,28614)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist386_i_shl_i_i_i_i_i77_i_97_c_compstr2735_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_97_c_compstr2735_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_97_c_compstr2735_vt_join(BITJOIN,9411)@207
    assign i_shl_i_i_i_i_i77_i_97_c_compstr2735_vt_join_q = {redist386_i_shl_i_i_i_i_i77_i_97_c_compstr2735_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma(CHAINMULTADD,28222)@201 + 5
    // out q@207
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ah[0] <= redist965_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_195_tpl_193_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ah[1] <= redist964_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_194_tpl_193_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ch[0] <= redist711_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_195_tpl_193_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ch[1] <= redist710_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_194_tpl_193_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736(ADD,8518)@207
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compstr2731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compstr2733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compstr2732_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_97_c_compstr2735_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_97_c_compstr2735_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_o[33:0];

    // rightShiftStage0_uid20952_dupName_387_i_unnamed_c_compstr0_shift_x(MUX,20951)@207
    assign rightShiftStage0_uid20952_dupName_387_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20952_dupName_387_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_q or rightShiftStage0Idx1_uid20950_dupName_387_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20952_dupName_387_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20952_dupName_387_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_q;
            1'b1 : rightShiftStage0_uid20952_dupName_387_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20950_dupName_387_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20952_dupName_387_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20957_dupName_387_i_unnamed_c_compstr0_shift_x(MUX,20956)@207
    assign rightShiftStage1_uid20957_dupName_387_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20957_dupName_387_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20952_dupName_387_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20955_dupName_387_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20957_dupName_387_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20957_dupName_387_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20952_dupName_387_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20957_dupName_387_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20955_dupName_387_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20957_dupName_387_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20962_dupName_387_i_unnamed_c_compstr0_shift_x(MUX,20961)@207
    assign rightShiftStage2_uid20962_dupName_387_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20962_dupName_387_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid20957_dupName_387_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid20960_dupName_387_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20962_dupName_387_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid20962_dupName_387_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid20957_dupName_387_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid20962_dupName_387_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid20960_dupName_387_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid20962_dupName_387_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2737_vt_select_20(BITSELECT,11309)@207
    assign i_unnamed_c_compstr2737_vt_select_20_b = rightShiftStage2_uid20962_dupName_387_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2737_vt_join(BITJOIN,11308)@207
    assign i_unnamed_c_compstr2737_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2737_vt_select_20_b};

    // i_conv_i_i_i_i97_i_97_c_compstr2738_sel_x(BITSELECT,3580)@207
    assign i_conv_i_i_i_i97_i_97_c_compstr2738_sel_x_b = i_unnamed_c_compstr2737_vt_join_q[15:0];

    // redist1156_i_conv_i_i_i_i97_i_97_c_compstr2738_sel_x_b_1(DELAY,29384)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1156_i_conv_i_i_i_i97_i_97_c_compstr2738_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_97_c_compstr2738_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20971_dupName_388_i_unnamed_c_compstr0_shift_x(BITSELECT,20970)@207
    assign rightShiftStage1Idx1Rng8_uid20971_dupName_388_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid20970_dupName_388_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20973_dupName_388_i_unnamed_c_compstr0_shift_x(BITJOIN,20972)@207
    assign rightShiftStage1Idx1_uid20973_dupName_388_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid20971_dupName_388_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20966_dupName_388_i_unnamed_c_compstr0_shift_x(BITSELECT,20965)@207
    assign rightShiftStage0Idx1Rng4_uid20966_dupName_388_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_q[33:4];

    // rightShiftStage0Idx1_uid20968_dupName_388_i_unnamed_c_compstr0_shift_x(BITJOIN,20967)@207
    assign rightShiftStage0Idx1_uid20968_dupName_388_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid20966_dupName_388_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid20970_dupName_388_i_unnamed_c_compstr0_shift_x(MUX,20969)@207
    assign rightShiftStage0_uid20970_dupName_388_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20970_dupName_388_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_q or rightShiftStage0Idx1_uid20968_dupName_388_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20970_dupName_388_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid20970_dupName_388_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compstr2736_q;
            1'b1 : rightShiftStage0_uid20970_dupName_388_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid20968_dupName_388_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid20970_dupName_388_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20975_dupName_388_i_unnamed_c_compstr0_shift_x(MUX,20974)@207
    assign rightShiftStage1_uid20975_dupName_388_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20975_dupName_388_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid20970_dupName_388_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid20973_dupName_388_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20975_dupName_388_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid20975_dupName_388_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid20970_dupName_388_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid20975_dupName_388_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid20973_dupName_388_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid20975_dupName_388_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2739_vt_select_21(BITSELECT,11312)@207
    assign i_unnamed_c_compstr2739_vt_select_21_b = rightShiftStage1_uid20975_dupName_388_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2739_vt_join(BITJOIN,11311)@207
    assign i_unnamed_c_compstr2739_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2739_vt_select_21_b};

    // i_unnamed_c_compstr2740_sel_x(BITSELECT,6172)@207
    assign i_unnamed_c_compstr2740_sel_x_b = i_unnamed_c_compstr2739_vt_join_q[15:0];

    // i_unnamed_c_compstr2741_BitSelect_for_a(BITSELECT,27733)@207
    assign i_unnamed_c_compstr2741_BitSelect_for_a_b = i_unnamed_c_compstr2740_sel_x_b[0:0];

    // i_unnamed_c_compstr2741_join(BITJOIN,27734)@207
    assign i_unnamed_c_compstr2741_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2741_BitSelect_for_a_b};

    // i_unnamed_c_compstr2741_vt_select_0(BITSELECT,11320)@207
    assign i_unnamed_c_compstr2741_vt_select_0_b = i_unnamed_c_compstr2741_join_q[0:0];

    // redist119_i_unnamed_c_compstr2741_vt_select_0_b_1(DELAY,28347)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist119_i_unnamed_c_compstr2741_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2741_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2741_vt_join(BITJOIN,11319)@208
    assign i_unnamed_c_compstr2741_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist119_i_unnamed_c_compstr2741_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_97_c_compstr2742(ADD,6975)@208
    assign i_add_i_i_i_i_i126_i_97_c_compstr2742_a = {1'b0, i_unnamed_c_compstr2741_vt_join_q};
    assign i_add_i_i_i_i_i126_i_97_c_compstr2742_b = {1'b0, redist1156_i_conv_i_i_i_i97_i_97_c_compstr2738_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_97_c_compstr2742_o = $unsigned(i_add_i_i_i_i_i126_i_97_c_compstr2742_a) + $unsigned(i_add_i_i_i_i_i126_i_97_c_compstr2742_b);
    assign i_add_i_i_i_i_i126_i_97_c_compstr2742_q = i_add_i_i_i_i_i126_i_97_c_compstr2742_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_97_c_compstr2742_sel_x(BITSELECT,2169)@208
    assign bgTrunc_i_add_i_i_i_i_i126_i_97_c_compstr2742_sel_x_b = i_add_i_i_i_i_i126_i_97_c_compstr2742_q[15:0];

    // i_conv_i_i_i_i_i75_i277_98_c_compstr2762_sel_x(BITSELECT,3710)@208
    assign i_conv_i_i_i_i_i75_i277_98_c_compstr2762_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_97_c_compstr2742_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_98_c_compstr2762_vt_select_15(BITSELECT,7741)@208
    assign i_conv_i_i_i_i_i75_i277_98_c_compstr2762_vt_select_15_b = i_conv_i_i_i_i_i75_i277_98_c_compstr2762_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_98_c_compstr2762_vt_join(BITJOIN,7740)@208
    assign i_conv_i_i_i_i_i75_i277_98_c_compstr2762_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_98_c_compstr2762_vt_select_15_b};

    // leftShiftStage0_uid25106_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x(MUX,25105)@208
    assign leftShiftStage0_uid25106_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25106_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_98_c_compstr2762_vt_join_q or leftShiftStage0Idx1_uid25104_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25106_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25106_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_98_c_compstr2762_vt_join_q;
            1'b1 : leftShiftStage0_uid25106_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25104_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25106_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25111_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x(MUX,25110)@208
    assign leftShiftStage1_uid25111_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25111_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_s or leftShiftStage0_uid25106_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25109_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25111_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25111_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q = leftShiftStage0_uid25106_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25111_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25109_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25111_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25116_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x(MUX,25115)@208
    assign leftShiftStage2_uid25116_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25116_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_s or leftShiftStage1_uid25111_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25114_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25116_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25116_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q = leftShiftStage1_uid25111_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25116_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25114_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25116_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_98_c_compstr2763_vt_select_28(BITSELECT,9415)@208
    assign i_shl_i_i_i_i_i77_i_98_c_compstr2763_vt_select_28_b = leftShiftStage2_uid25116_i_shl_i_i_i_i_i77_i_98_c_compstr0_shift_x_q[28:13];

    // redist385_i_shl_i_i_i_i_i77_i_98_c_compstr2763_vt_select_28_b_1(DELAY,28613)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist385_i_shl_i_i_i_i_i77_i_98_c_compstr2763_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_98_c_compstr2763_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_98_c_compstr2763_vt_join(BITJOIN,9414)@209
    assign i_shl_i_i_i_i_i77_i_98_c_compstr2763_vt_join_q = {redist385_i_shl_i_i_i_i_i77_i_98_c_compstr2763_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma(CHAINMULTADD,28223)@203 + 5
    // out q@209
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ah[0] <= redist967_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_197_tpl_195_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ah[1] <= redist966_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_196_tpl_195_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ch[0] <= redist713_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_197_tpl_195_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ch[1] <= redist712_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_196_tpl_195_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764(ADD,8519)@209
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compstr2759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compstr2761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compstr2760_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_98_c_compstr2763_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_98_c_compstr2763_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_o[33:0];

    // rightShiftStage0_uid21014_dupName_391_i_unnamed_c_compstr0_shift_x(MUX,21013)@209
    assign rightShiftStage0_uid21014_dupName_391_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21014_dupName_391_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_q or rightShiftStage0Idx1_uid21012_dupName_391_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21014_dupName_391_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21014_dupName_391_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_q;
            1'b1 : rightShiftStage0_uid21014_dupName_391_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21012_dupName_391_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21014_dupName_391_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21019_dupName_391_i_unnamed_c_compstr0_shift_x(MUX,21018)@209
    assign rightShiftStage1_uid21019_dupName_391_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21019_dupName_391_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21014_dupName_391_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21017_dupName_391_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21019_dupName_391_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21019_dupName_391_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21014_dupName_391_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21019_dupName_391_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21017_dupName_391_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21019_dupName_391_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21024_dupName_391_i_unnamed_c_compstr0_shift_x(MUX,21023)@209
    assign rightShiftStage2_uid21024_dupName_391_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21024_dupName_391_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21019_dupName_391_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21022_dupName_391_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21024_dupName_391_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21024_dupName_391_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21019_dupName_391_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21024_dupName_391_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21022_dupName_391_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21024_dupName_391_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2765_vt_select_20(BITSELECT,11337)@209
    assign i_unnamed_c_compstr2765_vt_select_20_b = rightShiftStage2_uid21024_dupName_391_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2765_vt_join(BITJOIN,11336)@209
    assign i_unnamed_c_compstr2765_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2765_vt_select_20_b};

    // i_conv_i_i_i_i97_i_98_c_compstr2766_sel_x(BITSELECT,3581)@209
    assign i_conv_i_i_i_i97_i_98_c_compstr2766_sel_x_b = i_unnamed_c_compstr2765_vt_join_q[15:0];

    // redist1155_i_conv_i_i_i_i97_i_98_c_compstr2766_sel_x_b_1(DELAY,29383)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1155_i_conv_i_i_i_i97_i_98_c_compstr2766_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_98_c_compstr2766_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21033_dupName_392_i_unnamed_c_compstr0_shift_x(BITSELECT,21032)@209
    assign rightShiftStage1Idx1Rng8_uid21033_dupName_392_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21032_dupName_392_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21035_dupName_392_i_unnamed_c_compstr0_shift_x(BITJOIN,21034)@209
    assign rightShiftStage1Idx1_uid21035_dupName_392_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21033_dupName_392_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21028_dupName_392_i_unnamed_c_compstr0_shift_x(BITSELECT,21027)@209
    assign rightShiftStage0Idx1Rng4_uid21028_dupName_392_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_q[33:4];

    // rightShiftStage0Idx1_uid21030_dupName_392_i_unnamed_c_compstr0_shift_x(BITJOIN,21029)@209
    assign rightShiftStage0Idx1_uid21030_dupName_392_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21028_dupName_392_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21032_dupName_392_i_unnamed_c_compstr0_shift_x(MUX,21031)@209
    assign rightShiftStage0_uid21032_dupName_392_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21032_dupName_392_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_q or rightShiftStage0Idx1_uid21030_dupName_392_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21032_dupName_392_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21032_dupName_392_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compstr2764_q;
            1'b1 : rightShiftStage0_uid21032_dupName_392_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21030_dupName_392_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21032_dupName_392_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21037_dupName_392_i_unnamed_c_compstr0_shift_x(MUX,21036)@209
    assign rightShiftStage1_uid21037_dupName_392_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21037_dupName_392_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21032_dupName_392_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21035_dupName_392_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21037_dupName_392_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21037_dupName_392_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21032_dupName_392_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21037_dupName_392_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21035_dupName_392_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21037_dupName_392_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2767_vt_select_21(BITSELECT,11340)@209
    assign i_unnamed_c_compstr2767_vt_select_21_b = rightShiftStage1_uid21037_dupName_392_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2767_vt_join(BITJOIN,11339)@209
    assign i_unnamed_c_compstr2767_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2767_vt_select_21_b};

    // i_unnamed_c_compstr2768_sel_x(BITSELECT,6175)@209
    assign i_unnamed_c_compstr2768_sel_x_b = i_unnamed_c_compstr2767_vt_join_q[15:0];

    // i_unnamed_c_compstr2769_BitSelect_for_a(BITSELECT,27737)@209
    assign i_unnamed_c_compstr2769_BitSelect_for_a_b = i_unnamed_c_compstr2768_sel_x_b[0:0];

    // i_unnamed_c_compstr2769_join(BITJOIN,27738)@209
    assign i_unnamed_c_compstr2769_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2769_BitSelect_for_a_b};

    // i_unnamed_c_compstr2769_vt_select_0(BITSELECT,11345)@209
    assign i_unnamed_c_compstr2769_vt_select_0_b = i_unnamed_c_compstr2769_join_q[0:0];

    // redist117_i_unnamed_c_compstr2769_vt_select_0_b_1(DELAY,28345)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist117_i_unnamed_c_compstr2769_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2769_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2769_vt_join(BITJOIN,11344)@210
    assign i_unnamed_c_compstr2769_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist117_i_unnamed_c_compstr2769_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_98_c_compstr2770(ADD,6976)@210
    assign i_add_i_i_i_i_i126_i_98_c_compstr2770_a = {1'b0, i_unnamed_c_compstr2769_vt_join_q};
    assign i_add_i_i_i_i_i126_i_98_c_compstr2770_b = {1'b0, redist1155_i_conv_i_i_i_i97_i_98_c_compstr2766_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_98_c_compstr2770_o = $unsigned(i_add_i_i_i_i_i126_i_98_c_compstr2770_a) + $unsigned(i_add_i_i_i_i_i126_i_98_c_compstr2770_b);
    assign i_add_i_i_i_i_i126_i_98_c_compstr2770_q = i_add_i_i_i_i_i126_i_98_c_compstr2770_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_98_c_compstr2770_sel_x(BITSELECT,2170)@210
    assign bgTrunc_i_add_i_i_i_i_i126_i_98_c_compstr2770_sel_x_b = i_add_i_i_i_i_i126_i_98_c_compstr2770_q[15:0];

    // i_conv_i_i_i_i_i75_i277_99_c_compstr2790_sel_x(BITSELECT,3711)@210
    assign i_conv_i_i_i_i_i75_i277_99_c_compstr2790_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_98_c_compstr2770_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_99_c_compstr2790_vt_select_15(BITSELECT,7745)@210
    assign i_conv_i_i_i_i_i75_i277_99_c_compstr2790_vt_select_15_b = i_conv_i_i_i_i_i75_i277_99_c_compstr2790_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_99_c_compstr2790_vt_join(BITJOIN,7744)@210
    assign i_conv_i_i_i_i_i75_i277_99_c_compstr2790_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_99_c_compstr2790_vt_select_15_b};

    // leftShiftStage0_uid25124_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x(MUX,25123)@210
    assign leftShiftStage0_uid25124_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25124_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_99_c_compstr2790_vt_join_q or leftShiftStage0Idx1_uid25122_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25124_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid25124_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_99_c_compstr2790_vt_join_q;
            1'b1 : leftShiftStage0_uid25124_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid25122_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid25124_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25129_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x(MUX,25128)@210
    assign leftShiftStage1_uid25129_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25129_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_s or leftShiftStage0_uid25124_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid25127_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25129_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid25129_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q = leftShiftStage0_uid25124_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid25129_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid25127_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid25129_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25134_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x(MUX,25133)@210
    assign leftShiftStage2_uid25134_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25134_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_s or leftShiftStage1_uid25129_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid25132_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25134_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid25134_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q = leftShiftStage1_uid25129_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid25134_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid25132_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid25134_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_99_c_compstr2791_vt_select_28(BITSELECT,9418)@210
    assign i_shl_i_i_i_i_i77_i_99_c_compstr2791_vt_select_28_b = leftShiftStage2_uid25134_i_shl_i_i_i_i_i77_i_99_c_compstr0_shift_x_q[28:13];

    // redist384_i_shl_i_i_i_i_i77_i_99_c_compstr2791_vt_select_28_b_1(DELAY,28612)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist384_i_shl_i_i_i_i_i77_i_99_c_compstr2791_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_99_c_compstr2791_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_99_c_compstr2791_vt_join(BITJOIN,9417)@211
    assign i_shl_i_i_i_i_i77_i_99_c_compstr2791_vt_join_q = {redist384_i_shl_i_i_i_i_i77_i_99_c_compstr2791_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma(CHAINMULTADD,28224)@205 + 5
    // out q@211
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ah[0] <= redist969_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_199_tpl_197_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ah[1] <= redist968_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_198_tpl_197_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ch[0] <= redist715_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_199_tpl_197_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ch[1] <= redist714_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_198_tpl_197_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792(ADD,8520)@211
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compstr2787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compstr2789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compstr2788_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_99_c_compstr2791_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_99_c_compstr2791_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_o[33:0];

    // rightShiftStage0_uid21076_dupName_395_i_unnamed_c_compstr0_shift_x(MUX,21075)@211
    assign rightShiftStage0_uid21076_dupName_395_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21076_dupName_395_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_q or rightShiftStage0Idx1_uid21074_dupName_395_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21076_dupName_395_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21076_dupName_395_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_q;
            1'b1 : rightShiftStage0_uid21076_dupName_395_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21074_dupName_395_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21076_dupName_395_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21081_dupName_395_i_unnamed_c_compstr0_shift_x(MUX,21080)@211
    assign rightShiftStage1_uid21081_dupName_395_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21081_dupName_395_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21076_dupName_395_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21079_dupName_395_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21081_dupName_395_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21081_dupName_395_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21076_dupName_395_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21081_dupName_395_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21079_dupName_395_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21081_dupName_395_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21086_dupName_395_i_unnamed_c_compstr0_shift_x(MUX,21085)@211
    assign rightShiftStage2_uid21086_dupName_395_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21086_dupName_395_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21081_dupName_395_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21084_dupName_395_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21086_dupName_395_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21086_dupName_395_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21081_dupName_395_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21086_dupName_395_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21084_dupName_395_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21086_dupName_395_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2793_vt_select_20(BITSELECT,11364)@211
    assign i_unnamed_c_compstr2793_vt_select_20_b = rightShiftStage2_uid21086_dupName_395_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2793_vt_join(BITJOIN,11363)@211
    assign i_unnamed_c_compstr2793_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2793_vt_select_20_b};

    // i_conv_i_i_i_i97_i_99_c_compstr2794_sel_x(BITSELECT,3582)@211
    assign i_conv_i_i_i_i97_i_99_c_compstr2794_sel_x_b = i_unnamed_c_compstr2793_vt_join_q[15:0];

    // redist1154_i_conv_i_i_i_i97_i_99_c_compstr2794_sel_x_b_1(DELAY,29382)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1154_i_conv_i_i_i_i97_i_99_c_compstr2794_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_99_c_compstr2794_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21095_dupName_396_i_unnamed_c_compstr0_shift_x(BITSELECT,21094)@211
    assign rightShiftStage1Idx1Rng8_uid21095_dupName_396_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21094_dupName_396_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21097_dupName_396_i_unnamed_c_compstr0_shift_x(BITJOIN,21096)@211
    assign rightShiftStage1Idx1_uid21097_dupName_396_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21095_dupName_396_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21090_dupName_396_i_unnamed_c_compstr0_shift_x(BITSELECT,21089)@211
    assign rightShiftStage0Idx1Rng4_uid21090_dupName_396_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_q[33:4];

    // rightShiftStage0Idx1_uid21092_dupName_396_i_unnamed_c_compstr0_shift_x(BITJOIN,21091)@211
    assign rightShiftStage0Idx1_uid21092_dupName_396_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21090_dupName_396_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21094_dupName_396_i_unnamed_c_compstr0_shift_x(MUX,21093)@211
    assign rightShiftStage0_uid21094_dupName_396_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21094_dupName_396_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_q or rightShiftStage0Idx1_uid21092_dupName_396_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21094_dupName_396_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21094_dupName_396_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compstr2792_q;
            1'b1 : rightShiftStage0_uid21094_dupName_396_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21092_dupName_396_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21094_dupName_396_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21099_dupName_396_i_unnamed_c_compstr0_shift_x(MUX,21098)@211
    assign rightShiftStage1_uid21099_dupName_396_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21099_dupName_396_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21094_dupName_396_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21097_dupName_396_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21099_dupName_396_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21099_dupName_396_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21094_dupName_396_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21099_dupName_396_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21097_dupName_396_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21099_dupName_396_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2795_vt_select_21(BITSELECT,11367)@211
    assign i_unnamed_c_compstr2795_vt_select_21_b = rightShiftStage1_uid21099_dupName_396_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2795_vt_join(BITJOIN,11366)@211
    assign i_unnamed_c_compstr2795_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2795_vt_select_21_b};

    // i_unnamed_c_compstr2796_sel_x(BITSELECT,6177)@211
    assign i_unnamed_c_compstr2796_sel_x_b = i_unnamed_c_compstr2795_vt_join_q[15:0];

    // i_unnamed_c_compstr2797_BitSelect_for_a(BITSELECT,27743)@211
    assign i_unnamed_c_compstr2797_BitSelect_for_a_b = i_unnamed_c_compstr2796_sel_x_b[0:0];

    // i_unnamed_c_compstr2797_join(BITJOIN,27744)@211
    assign i_unnamed_c_compstr2797_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2797_BitSelect_for_a_b};

    // i_unnamed_c_compstr2797_vt_select_0(BITSELECT,11372)@211
    assign i_unnamed_c_compstr2797_vt_select_0_b = i_unnamed_c_compstr2797_join_q[0:0];

    // redist114_i_unnamed_c_compstr2797_vt_select_0_b_1(DELAY,28342)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist114_i_unnamed_c_compstr2797_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2797_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2797_vt_join(BITJOIN,11371)@212
    assign i_unnamed_c_compstr2797_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist114_i_unnamed_c_compstr2797_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_99_c_compstr2798(ADD,6977)@212
    assign i_add_i_i_i_i_i126_i_99_c_compstr2798_a = {1'b0, i_unnamed_c_compstr2797_vt_join_q};
    assign i_add_i_i_i_i_i126_i_99_c_compstr2798_b = {1'b0, redist1154_i_conv_i_i_i_i97_i_99_c_compstr2794_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_99_c_compstr2798_o = $unsigned(i_add_i_i_i_i_i126_i_99_c_compstr2798_a) + $unsigned(i_add_i_i_i_i_i126_i_99_c_compstr2798_b);
    assign i_add_i_i_i_i_i126_i_99_c_compstr2798_q = i_add_i_i_i_i_i126_i_99_c_compstr2798_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_99_c_compstr2798_sel_x(BITSELECT,2171)@212
    assign bgTrunc_i_add_i_i_i_i_i126_i_99_c_compstr2798_sel_x_b = i_add_i_i_i_i_i126_i_99_c_compstr2798_q[15:0];

    // i_conv_i_i_i_i_i75_i277_100_c_compstr2818_sel_x(BITSELECT,3586)@212
    assign i_conv_i_i_i_i_i75_i277_100_c_compstr2818_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_99_c_compstr2798_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_select_15(BITSELECT,7245)@212
    assign i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_select_15_b = i_conv_i_i_i_i_i75_i277_100_c_compstr2818_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_join(BITJOIN,7244)@212
    assign i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_select_15_b};

    // leftShiftStage0_uid22874_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x(MUX,22873)@212
    assign leftShiftStage0_uid22874_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid22874_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_join_q or leftShiftStage0Idx1_uid22872_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid22874_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid22874_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_join_q;
            1'b1 : leftShiftStage0_uid22874_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid22872_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid22874_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid22879_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x(MUX,22878)@212
    assign leftShiftStage1_uid22879_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid22879_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_s or leftShiftStage0_uid22874_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid22877_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid22879_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid22879_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q = leftShiftStage0_uid22874_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid22879_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid22877_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid22879_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid22884_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x(MUX,22883)@212
    assign leftShiftStage2_uid22884_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid22884_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_s or leftShiftStage1_uid22879_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid22882_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid22884_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid22884_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q = leftShiftStage1_uid22879_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid22884_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid22882_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid22884_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_100_c_compstr2819_vt_select_28(BITSELECT,9043)@212
    assign i_shl_i_i_i_i_i77_i_100_c_compstr2819_vt_select_28_b = leftShiftStage2_uid22884_i_shl_i_i_i_i_i77_i_100_c_compstr0_shift_x_q[28:13];

    // redist509_i_shl_i_i_i_i_i77_i_100_c_compstr2819_vt_select_28_b_1(DELAY,28737)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist509_i_shl_i_i_i_i_i77_i_100_c_compstr2819_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_100_c_compstr2819_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_100_c_compstr2819_vt_join(BITJOIN,9042)@213
    assign i_shl_i_i_i_i_i77_i_100_c_compstr2819_vt_join_q = {redist509_i_shl_i_i_i_i_i77_i_100_c_compstr2819_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma(CHAINMULTADD,28099)@207 + 5
    // out q@213
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ah[0] <= redist971_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_201_tpl_199_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ah[1] <= redist970_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_200_tpl_199_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ch[0] <= redist717_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_201_tpl_199_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ch[1] <= redist716_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_200_tpl_199_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820(ADD,8395)@213
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compstr2815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compstr2817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compstr2816_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_100_c_compstr2819_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_100_c_compstr2819_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_o[33:0];

    // rightShiftStage0_uid21138_dupName_399_i_unnamed_c_compstr0_shift_x(MUX,21137)@213
    assign rightShiftStage0_uid21138_dupName_399_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21138_dupName_399_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_q or rightShiftStage0Idx1_uid21136_dupName_399_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21138_dupName_399_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21138_dupName_399_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_q;
            1'b1 : rightShiftStage0_uid21138_dupName_399_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21136_dupName_399_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21138_dupName_399_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21143_dupName_399_i_unnamed_c_compstr0_shift_x(MUX,21142)@213
    assign rightShiftStage1_uid21143_dupName_399_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21143_dupName_399_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21138_dupName_399_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21141_dupName_399_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21143_dupName_399_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21143_dupName_399_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21138_dupName_399_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21143_dupName_399_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21141_dupName_399_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21143_dupName_399_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21148_dupName_399_i_unnamed_c_compstr0_shift_x(MUX,21147)@213
    assign rightShiftStage2_uid21148_dupName_399_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21148_dupName_399_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21143_dupName_399_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21146_dupName_399_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21148_dupName_399_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21148_dupName_399_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21143_dupName_399_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21148_dupName_399_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21146_dupName_399_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21148_dupName_399_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2821_vt_select_20(BITSELECT,11389)@213
    assign i_unnamed_c_compstr2821_vt_select_20_b = rightShiftStage2_uid21148_dupName_399_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2821_vt_join(BITJOIN,11388)@213
    assign i_unnamed_c_compstr2821_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2821_vt_select_20_b};

    // i_conv_i_i_i_i97_i_100_c_compstr2822_sel_x(BITSELECT,3457)@213
    assign i_conv_i_i_i_i97_i_100_c_compstr2822_sel_x_b = i_unnamed_c_compstr2821_vt_join_q[15:0];

    // redist1279_i_conv_i_i_i_i97_i_100_c_compstr2822_sel_x_b_1(DELAY,29507)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1279_i_conv_i_i_i_i97_i_100_c_compstr2822_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_100_c_compstr2822_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21157_dupName_400_i_unnamed_c_compstr0_shift_x(BITSELECT,21156)@213
    assign rightShiftStage1Idx1Rng8_uid21157_dupName_400_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21156_dupName_400_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21159_dupName_400_i_unnamed_c_compstr0_shift_x(BITJOIN,21158)@213
    assign rightShiftStage1Idx1_uid21159_dupName_400_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21157_dupName_400_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21152_dupName_400_i_unnamed_c_compstr0_shift_x(BITSELECT,21151)@213
    assign rightShiftStage0Idx1Rng4_uid21152_dupName_400_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_q[33:4];

    // rightShiftStage0Idx1_uid21154_dupName_400_i_unnamed_c_compstr0_shift_x(BITJOIN,21153)@213
    assign rightShiftStage0Idx1_uid21154_dupName_400_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21152_dupName_400_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21156_dupName_400_i_unnamed_c_compstr0_shift_x(MUX,21155)@213
    assign rightShiftStage0_uid21156_dupName_400_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21156_dupName_400_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_q or rightShiftStage0Idx1_uid21154_dupName_400_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21156_dupName_400_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21156_dupName_400_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compstr2820_q;
            1'b1 : rightShiftStage0_uid21156_dupName_400_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21154_dupName_400_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21156_dupName_400_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21161_dupName_400_i_unnamed_c_compstr0_shift_x(MUX,21160)@213
    assign rightShiftStage1_uid21161_dupName_400_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21161_dupName_400_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21156_dupName_400_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21159_dupName_400_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21161_dupName_400_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21161_dupName_400_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21156_dupName_400_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21161_dupName_400_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21159_dupName_400_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21161_dupName_400_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2823_vt_select_21(BITSELECT,11392)@213
    assign i_unnamed_c_compstr2823_vt_select_21_b = rightShiftStage1_uid21161_dupName_400_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2823_vt_join(BITJOIN,11391)@213
    assign i_unnamed_c_compstr2823_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2823_vt_select_21_b};

    // i_unnamed_c_compstr2824_sel_x(BITSELECT,6179)@213
    assign i_unnamed_c_compstr2824_sel_x_b = i_unnamed_c_compstr2823_vt_join_q[15:0];

    // i_unnamed_c_compstr2825_BitSelect_for_a(BITSELECT,27747)@213
    assign i_unnamed_c_compstr2825_BitSelect_for_a_b = i_unnamed_c_compstr2824_sel_x_b[0:0];

    // i_unnamed_c_compstr2825_join(BITJOIN,27748)@213
    assign i_unnamed_c_compstr2825_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2825_BitSelect_for_a_b};

    // i_unnamed_c_compstr2825_vt_select_0(BITSELECT,11397)@213
    assign i_unnamed_c_compstr2825_vt_select_0_b = i_unnamed_c_compstr2825_join_q[0:0];

    // redist112_i_unnamed_c_compstr2825_vt_select_0_b_1(DELAY,28340)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist112_i_unnamed_c_compstr2825_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2825_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2825_vt_join(BITJOIN,11396)@214
    assign i_unnamed_c_compstr2825_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist112_i_unnamed_c_compstr2825_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_100_c_compstr2826(ADD,6852)@214
    assign i_add_i_i_i_i_i126_i_100_c_compstr2826_a = {1'b0, i_unnamed_c_compstr2825_vt_join_q};
    assign i_add_i_i_i_i_i126_i_100_c_compstr2826_b = {1'b0, redist1279_i_conv_i_i_i_i97_i_100_c_compstr2822_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_100_c_compstr2826_o = $unsigned(i_add_i_i_i_i_i126_i_100_c_compstr2826_a) + $unsigned(i_add_i_i_i_i_i126_i_100_c_compstr2826_b);
    assign i_add_i_i_i_i_i126_i_100_c_compstr2826_q = i_add_i_i_i_i_i126_i_100_c_compstr2826_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_100_c_compstr2826_sel_x(BITSELECT,2046)@214
    assign bgTrunc_i_add_i_i_i_i_i126_i_100_c_compstr2826_sel_x_b = i_add_i_i_i_i_i126_i_100_c_compstr2826_q[15:0];

    // i_conv_i_i_i_i_i75_i277_101_c_compstr2846_sel_x(BITSELECT,3587)@214
    assign i_conv_i_i_i_i_i75_i277_101_c_compstr2846_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_100_c_compstr2826_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_101_c_compstr2846_vt_select_15(BITSELECT,7249)@214
    assign i_conv_i_i_i_i_i75_i277_101_c_compstr2846_vt_select_15_b = i_conv_i_i_i_i_i75_i277_101_c_compstr2846_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_101_c_compstr2846_vt_join(BITJOIN,7248)@214
    assign i_conv_i_i_i_i_i75_i277_101_c_compstr2846_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_101_c_compstr2846_vt_select_15_b};

    // leftShiftStage0_uid22892_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x(MUX,22891)@214
    assign leftShiftStage0_uid22892_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid22892_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_101_c_compstr2846_vt_join_q or leftShiftStage0Idx1_uid22890_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid22892_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid22892_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_101_c_compstr2846_vt_join_q;
            1'b1 : leftShiftStage0_uid22892_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid22890_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid22892_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid22897_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x(MUX,22896)@214
    assign leftShiftStage1_uid22897_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid22897_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_s or leftShiftStage0_uid22892_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid22895_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid22897_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid22897_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q = leftShiftStage0_uid22892_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid22897_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid22895_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid22897_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid22902_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x(MUX,22901)@214
    assign leftShiftStage2_uid22902_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid22902_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_s or leftShiftStage1_uid22897_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid22900_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid22902_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid22902_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q = leftShiftStage1_uid22897_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid22902_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid22900_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid22902_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_101_c_compstr2847_vt_select_28(BITSELECT,9046)@214
    assign i_shl_i_i_i_i_i77_i_101_c_compstr2847_vt_select_28_b = leftShiftStage2_uid22902_i_shl_i_i_i_i_i77_i_101_c_compstr0_shift_x_q[28:13];

    // redist508_i_shl_i_i_i_i_i77_i_101_c_compstr2847_vt_select_28_b_1(DELAY,28736)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist508_i_shl_i_i_i_i_i77_i_101_c_compstr2847_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_101_c_compstr2847_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_101_c_compstr2847_vt_join(BITJOIN,9045)@215
    assign i_shl_i_i_i_i_i77_i_101_c_compstr2847_vt_join_q = {redist508_i_shl_i_i_i_i_i77_i_101_c_compstr2847_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma(CHAINMULTADD,28100)@209 + 5
    // out q@215
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ah[0] <= redist973_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_203_tpl_201_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ah[1] <= redist972_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_202_tpl_201_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ch[0] <= redist719_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_203_tpl_201_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ch[1] <= redist718_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_202_tpl_201_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848(ADD,8396)@215
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compstr2843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compstr2845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compstr2844_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_101_c_compstr2847_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_101_c_compstr2847_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_o[33:0];

    // rightShiftStage0_uid21200_dupName_403_i_unnamed_c_compstr0_shift_x(MUX,21199)@215
    assign rightShiftStage0_uid21200_dupName_403_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21200_dupName_403_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_q or rightShiftStage0Idx1_uid21198_dupName_403_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21200_dupName_403_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21200_dupName_403_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_q;
            1'b1 : rightShiftStage0_uid21200_dupName_403_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21198_dupName_403_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21200_dupName_403_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21205_dupName_403_i_unnamed_c_compstr0_shift_x(MUX,21204)@215
    assign rightShiftStage1_uid21205_dupName_403_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21205_dupName_403_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21200_dupName_403_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21203_dupName_403_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21205_dupName_403_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21205_dupName_403_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21200_dupName_403_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21205_dupName_403_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21203_dupName_403_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21205_dupName_403_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21210_dupName_403_i_unnamed_c_compstr0_shift_x(MUX,21209)@215
    assign rightShiftStage2_uid21210_dupName_403_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21210_dupName_403_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21205_dupName_403_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21208_dupName_403_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21210_dupName_403_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21210_dupName_403_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21205_dupName_403_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21210_dupName_403_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21208_dupName_403_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21210_dupName_403_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2849_vt_select_20(BITSELECT,11411)@215
    assign i_unnamed_c_compstr2849_vt_select_20_b = rightShiftStage2_uid21210_dupName_403_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2849_vt_join(BITJOIN,11410)@215
    assign i_unnamed_c_compstr2849_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2849_vt_select_20_b};

    // i_conv_i_i_i_i97_i_101_c_compstr2850_sel_x(BITSELECT,3458)@215
    assign i_conv_i_i_i_i97_i_101_c_compstr2850_sel_x_b = i_unnamed_c_compstr2849_vt_join_q[15:0];

    // redist1278_i_conv_i_i_i_i97_i_101_c_compstr2850_sel_x_b_1(DELAY,29506)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1278_i_conv_i_i_i_i97_i_101_c_compstr2850_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_101_c_compstr2850_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21219_dupName_404_i_unnamed_c_compstr0_shift_x(BITSELECT,21218)@215
    assign rightShiftStage1Idx1Rng8_uid21219_dupName_404_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21218_dupName_404_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21221_dupName_404_i_unnamed_c_compstr0_shift_x(BITJOIN,21220)@215
    assign rightShiftStage1Idx1_uid21221_dupName_404_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21219_dupName_404_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21214_dupName_404_i_unnamed_c_compstr0_shift_x(BITSELECT,21213)@215
    assign rightShiftStage0Idx1Rng4_uid21214_dupName_404_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_q[33:4];

    // rightShiftStage0Idx1_uid21216_dupName_404_i_unnamed_c_compstr0_shift_x(BITJOIN,21215)@215
    assign rightShiftStage0Idx1_uid21216_dupName_404_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21214_dupName_404_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21218_dupName_404_i_unnamed_c_compstr0_shift_x(MUX,21217)@215
    assign rightShiftStage0_uid21218_dupName_404_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21218_dupName_404_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_q or rightShiftStage0Idx1_uid21216_dupName_404_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21218_dupName_404_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21218_dupName_404_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compstr2848_q;
            1'b1 : rightShiftStage0_uid21218_dupName_404_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21216_dupName_404_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21218_dupName_404_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21223_dupName_404_i_unnamed_c_compstr0_shift_x(MUX,21222)@215
    assign rightShiftStage1_uid21223_dupName_404_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21223_dupName_404_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21218_dupName_404_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21221_dupName_404_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21223_dupName_404_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21223_dupName_404_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21218_dupName_404_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21223_dupName_404_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21221_dupName_404_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21223_dupName_404_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2851_vt_select_21(BITSELECT,11414)@215
    assign i_unnamed_c_compstr2851_vt_select_21_b = rightShiftStage1_uid21223_dupName_404_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2851_vt_join(BITJOIN,11413)@215
    assign i_unnamed_c_compstr2851_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2851_vt_select_21_b};

    // i_unnamed_c_compstr2852_sel_x(BITSELECT,6181)@215
    assign i_unnamed_c_compstr2852_sel_x_b = i_unnamed_c_compstr2851_vt_join_q[15:0];

    // i_unnamed_c_compstr2853_BitSelect_for_a(BITSELECT,27751)@215
    assign i_unnamed_c_compstr2853_BitSelect_for_a_b = i_unnamed_c_compstr2852_sel_x_b[0:0];

    // i_unnamed_c_compstr2853_join(BITJOIN,27752)@215
    assign i_unnamed_c_compstr2853_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2853_BitSelect_for_a_b};

    // i_unnamed_c_compstr2853_vt_select_0(BITSELECT,11419)@215
    assign i_unnamed_c_compstr2853_vt_select_0_b = i_unnamed_c_compstr2853_join_q[0:0];

    // redist110_i_unnamed_c_compstr2853_vt_select_0_b_1(DELAY,28338)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist110_i_unnamed_c_compstr2853_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2853_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2853_vt_join(BITJOIN,11418)@216
    assign i_unnamed_c_compstr2853_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist110_i_unnamed_c_compstr2853_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_101_c_compstr2854(ADD,6853)@216
    assign i_add_i_i_i_i_i126_i_101_c_compstr2854_a = {1'b0, i_unnamed_c_compstr2853_vt_join_q};
    assign i_add_i_i_i_i_i126_i_101_c_compstr2854_b = {1'b0, redist1278_i_conv_i_i_i_i97_i_101_c_compstr2850_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_101_c_compstr2854_o = $unsigned(i_add_i_i_i_i_i126_i_101_c_compstr2854_a) + $unsigned(i_add_i_i_i_i_i126_i_101_c_compstr2854_b);
    assign i_add_i_i_i_i_i126_i_101_c_compstr2854_q = i_add_i_i_i_i_i126_i_101_c_compstr2854_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_101_c_compstr2854_sel_x(BITSELECT,2047)@216
    assign bgTrunc_i_add_i_i_i_i_i126_i_101_c_compstr2854_sel_x_b = i_add_i_i_i_i_i126_i_101_c_compstr2854_q[15:0];

    // i_conv_i_i_i_i_i75_i277_102_c_compstr2874_sel_x(BITSELECT,3588)@216
    assign i_conv_i_i_i_i_i75_i277_102_c_compstr2874_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_101_c_compstr2854_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_102_c_compstr2874_vt_select_15(BITSELECT,7253)@216
    assign i_conv_i_i_i_i_i75_i277_102_c_compstr2874_vt_select_15_b = i_conv_i_i_i_i_i75_i277_102_c_compstr2874_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_102_c_compstr2874_vt_join(BITJOIN,7252)@216
    assign i_conv_i_i_i_i_i75_i277_102_c_compstr2874_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_102_c_compstr2874_vt_select_15_b};

    // leftShiftStage0_uid22910_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x(MUX,22909)@216
    assign leftShiftStage0_uid22910_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid22910_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_102_c_compstr2874_vt_join_q or leftShiftStage0Idx1_uid22908_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid22910_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid22910_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_102_c_compstr2874_vt_join_q;
            1'b1 : leftShiftStage0_uid22910_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid22908_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid22910_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid22915_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x(MUX,22914)@216
    assign leftShiftStage1_uid22915_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid22915_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_s or leftShiftStage0_uid22910_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid22913_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid22915_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid22915_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q = leftShiftStage0_uid22910_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid22915_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid22913_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid22915_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid22920_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x(MUX,22919)@216
    assign leftShiftStage2_uid22920_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid22920_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_s or leftShiftStage1_uid22915_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid22918_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid22920_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid22920_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q = leftShiftStage1_uid22915_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid22920_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid22918_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid22920_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_102_c_compstr2875_vt_select_28(BITSELECT,9049)@216
    assign i_shl_i_i_i_i_i77_i_102_c_compstr2875_vt_select_28_b = leftShiftStage2_uid22920_i_shl_i_i_i_i_i77_i_102_c_compstr0_shift_x_q[28:13];

    // redist507_i_shl_i_i_i_i_i77_i_102_c_compstr2875_vt_select_28_b_1(DELAY,28735)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist507_i_shl_i_i_i_i_i77_i_102_c_compstr2875_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_102_c_compstr2875_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_102_c_compstr2875_vt_join(BITJOIN,9048)@217
    assign i_shl_i_i_i_i_i77_i_102_c_compstr2875_vt_join_q = {redist507_i_shl_i_i_i_i_i77_i_102_c_compstr2875_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma(CHAINMULTADD,28101)@211 + 5
    // out q@217
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ah[0] <= redist975_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_205_tpl_203_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ah[1] <= redist974_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_204_tpl_203_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ch[0] <= redist721_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_205_tpl_203_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ch[1] <= redist720_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_204_tpl_203_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876(ADD,8397)@217
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compstr2871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compstr2873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compstr2872_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_102_c_compstr2875_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_102_c_compstr2875_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_o[33:0];

    // rightShiftStage0_uid21262_dupName_407_i_unnamed_c_compstr0_shift_x(MUX,21261)@217
    assign rightShiftStage0_uid21262_dupName_407_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21262_dupName_407_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_q or rightShiftStage0Idx1_uid21260_dupName_407_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21262_dupName_407_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21262_dupName_407_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_q;
            1'b1 : rightShiftStage0_uid21262_dupName_407_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21260_dupName_407_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21262_dupName_407_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21267_dupName_407_i_unnamed_c_compstr0_shift_x(MUX,21266)@217
    assign rightShiftStage1_uid21267_dupName_407_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21267_dupName_407_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21262_dupName_407_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21265_dupName_407_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21267_dupName_407_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21267_dupName_407_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21262_dupName_407_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21267_dupName_407_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21265_dupName_407_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21267_dupName_407_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21272_dupName_407_i_unnamed_c_compstr0_shift_x(MUX,21271)@217
    assign rightShiftStage2_uid21272_dupName_407_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21272_dupName_407_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21267_dupName_407_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21270_dupName_407_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21272_dupName_407_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21272_dupName_407_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21267_dupName_407_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21272_dupName_407_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21270_dupName_407_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21272_dupName_407_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2877_vt_select_20(BITSELECT,11433)@217
    assign i_unnamed_c_compstr2877_vt_select_20_b = rightShiftStage2_uid21272_dupName_407_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2877_vt_join(BITJOIN,11432)@217
    assign i_unnamed_c_compstr2877_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2877_vt_select_20_b};

    // i_conv_i_i_i_i97_i_102_c_compstr2878_sel_x(BITSELECT,3459)@217
    assign i_conv_i_i_i_i97_i_102_c_compstr2878_sel_x_b = i_unnamed_c_compstr2877_vt_join_q[15:0];

    // redist1277_i_conv_i_i_i_i97_i_102_c_compstr2878_sel_x_b_1(DELAY,29505)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1277_i_conv_i_i_i_i97_i_102_c_compstr2878_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_102_c_compstr2878_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21281_dupName_408_i_unnamed_c_compstr0_shift_x(BITSELECT,21280)@217
    assign rightShiftStage1Idx1Rng8_uid21281_dupName_408_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21280_dupName_408_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21283_dupName_408_i_unnamed_c_compstr0_shift_x(BITJOIN,21282)@217
    assign rightShiftStage1Idx1_uid21283_dupName_408_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21281_dupName_408_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21276_dupName_408_i_unnamed_c_compstr0_shift_x(BITSELECT,21275)@217
    assign rightShiftStage0Idx1Rng4_uid21276_dupName_408_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_q[33:4];

    // rightShiftStage0Idx1_uid21278_dupName_408_i_unnamed_c_compstr0_shift_x(BITJOIN,21277)@217
    assign rightShiftStage0Idx1_uid21278_dupName_408_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21276_dupName_408_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21280_dupName_408_i_unnamed_c_compstr0_shift_x(MUX,21279)@217
    assign rightShiftStage0_uid21280_dupName_408_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21280_dupName_408_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_q or rightShiftStage0Idx1_uid21278_dupName_408_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21280_dupName_408_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21280_dupName_408_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compstr2876_q;
            1'b1 : rightShiftStage0_uid21280_dupName_408_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21278_dupName_408_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21280_dupName_408_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21285_dupName_408_i_unnamed_c_compstr0_shift_x(MUX,21284)@217
    assign rightShiftStage1_uid21285_dupName_408_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21285_dupName_408_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21280_dupName_408_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21283_dupName_408_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21285_dupName_408_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21285_dupName_408_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21280_dupName_408_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21285_dupName_408_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21283_dupName_408_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21285_dupName_408_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2879_vt_select_21(BITSELECT,11436)@217
    assign i_unnamed_c_compstr2879_vt_select_21_b = rightShiftStage1_uid21285_dupName_408_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2879_vt_join(BITJOIN,11435)@217
    assign i_unnamed_c_compstr2879_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2879_vt_select_21_b};

    // i_unnamed_c_compstr2880_sel_x(BITSELECT,6183)@217
    assign i_unnamed_c_compstr2880_sel_x_b = i_unnamed_c_compstr2879_vt_join_q[15:0];

    // i_unnamed_c_compstr2881_BitSelect_for_a(BITSELECT,27755)@217
    assign i_unnamed_c_compstr2881_BitSelect_for_a_b = i_unnamed_c_compstr2880_sel_x_b[0:0];

    // i_unnamed_c_compstr2881_join(BITJOIN,27756)@217
    assign i_unnamed_c_compstr2881_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2881_BitSelect_for_a_b};

    // i_unnamed_c_compstr2881_vt_select_0(BITSELECT,11441)@217
    assign i_unnamed_c_compstr2881_vt_select_0_b = i_unnamed_c_compstr2881_join_q[0:0];

    // redist108_i_unnamed_c_compstr2881_vt_select_0_b_1(DELAY,28336)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist108_i_unnamed_c_compstr2881_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2881_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2881_vt_join(BITJOIN,11440)@218
    assign i_unnamed_c_compstr2881_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist108_i_unnamed_c_compstr2881_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_102_c_compstr2882(ADD,6854)@218
    assign i_add_i_i_i_i_i126_i_102_c_compstr2882_a = {1'b0, i_unnamed_c_compstr2881_vt_join_q};
    assign i_add_i_i_i_i_i126_i_102_c_compstr2882_b = {1'b0, redist1277_i_conv_i_i_i_i97_i_102_c_compstr2878_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_102_c_compstr2882_o = $unsigned(i_add_i_i_i_i_i126_i_102_c_compstr2882_a) + $unsigned(i_add_i_i_i_i_i126_i_102_c_compstr2882_b);
    assign i_add_i_i_i_i_i126_i_102_c_compstr2882_q = i_add_i_i_i_i_i126_i_102_c_compstr2882_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_102_c_compstr2882_sel_x(BITSELECT,2048)@218
    assign bgTrunc_i_add_i_i_i_i_i126_i_102_c_compstr2882_sel_x_b = i_add_i_i_i_i_i126_i_102_c_compstr2882_q[15:0];

    // i_conv_i_i_i_i_i75_i277_103_c_compstr2902_sel_x(BITSELECT,3589)@218
    assign i_conv_i_i_i_i_i75_i277_103_c_compstr2902_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_102_c_compstr2882_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_103_c_compstr2902_vt_select_15(BITSELECT,7257)@218
    assign i_conv_i_i_i_i_i75_i277_103_c_compstr2902_vt_select_15_b = i_conv_i_i_i_i_i75_i277_103_c_compstr2902_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_103_c_compstr2902_vt_join(BITJOIN,7256)@218
    assign i_conv_i_i_i_i_i75_i277_103_c_compstr2902_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_103_c_compstr2902_vt_select_15_b};

    // leftShiftStage0_uid22928_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x(MUX,22927)@218
    assign leftShiftStage0_uid22928_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid22928_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_103_c_compstr2902_vt_join_q or leftShiftStage0Idx1_uid22926_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid22928_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid22928_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_103_c_compstr2902_vt_join_q;
            1'b1 : leftShiftStage0_uid22928_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid22926_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid22928_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid22933_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x(MUX,22932)@218
    assign leftShiftStage1_uid22933_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid22933_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_s or leftShiftStage0_uid22928_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid22931_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid22933_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid22933_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q = leftShiftStage0_uid22928_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid22933_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid22931_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid22933_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid22938_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x(MUX,22937)@218
    assign leftShiftStage2_uid22938_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid22938_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_s or leftShiftStage1_uid22933_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid22936_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid22938_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid22938_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q = leftShiftStage1_uid22933_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid22938_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid22936_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid22938_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_103_c_compstr2903_vt_select_28(BITSELECT,9052)@218
    assign i_shl_i_i_i_i_i77_i_103_c_compstr2903_vt_select_28_b = leftShiftStage2_uid22938_i_shl_i_i_i_i_i77_i_103_c_compstr0_shift_x_q[28:13];

    // redist506_i_shl_i_i_i_i_i77_i_103_c_compstr2903_vt_select_28_b_1(DELAY,28734)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist506_i_shl_i_i_i_i_i77_i_103_c_compstr2903_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_103_c_compstr2903_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_103_c_compstr2903_vt_join(BITJOIN,9051)@219
    assign i_shl_i_i_i_i_i77_i_103_c_compstr2903_vt_join_q = {redist506_i_shl_i_i_i_i_i77_i_103_c_compstr2903_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma(CHAINMULTADD,28102)@213 + 5
    // out q@219
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ah[0] <= redist977_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_207_tpl_205_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ah[1] <= redist976_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_206_tpl_205_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ch[0] <= redist723_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_207_tpl_205_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ch[1] <= redist722_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_206_tpl_205_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904(ADD,8398)@219
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compstr2899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compstr2901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compstr2900_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_103_c_compstr2903_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_103_c_compstr2903_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_o[33:0];

    // rightShiftStage0_uid21324_dupName_411_i_unnamed_c_compstr0_shift_x(MUX,21323)@219
    assign rightShiftStage0_uid21324_dupName_411_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21324_dupName_411_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_q or rightShiftStage0Idx1_uid21322_dupName_411_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21324_dupName_411_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21324_dupName_411_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_q;
            1'b1 : rightShiftStage0_uid21324_dupName_411_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21322_dupName_411_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21324_dupName_411_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21329_dupName_411_i_unnamed_c_compstr0_shift_x(MUX,21328)@219
    assign rightShiftStage1_uid21329_dupName_411_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21329_dupName_411_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21324_dupName_411_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21327_dupName_411_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21329_dupName_411_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21329_dupName_411_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21324_dupName_411_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21329_dupName_411_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21327_dupName_411_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21329_dupName_411_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21334_dupName_411_i_unnamed_c_compstr0_shift_x(MUX,21333)@219
    assign rightShiftStage2_uid21334_dupName_411_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21334_dupName_411_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21329_dupName_411_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21332_dupName_411_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21334_dupName_411_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21334_dupName_411_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21329_dupName_411_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21334_dupName_411_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21332_dupName_411_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21334_dupName_411_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2905_vt_select_20(BITSELECT,11458)@219
    assign i_unnamed_c_compstr2905_vt_select_20_b = rightShiftStage2_uid21334_dupName_411_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2905_vt_join(BITJOIN,11457)@219
    assign i_unnamed_c_compstr2905_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2905_vt_select_20_b};

    // i_conv_i_i_i_i97_i_103_c_compstr2906_sel_x(BITSELECT,3460)@219
    assign i_conv_i_i_i_i97_i_103_c_compstr2906_sel_x_b = i_unnamed_c_compstr2905_vt_join_q[15:0];

    // redist1276_i_conv_i_i_i_i97_i_103_c_compstr2906_sel_x_b_1(DELAY,29504)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1276_i_conv_i_i_i_i97_i_103_c_compstr2906_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_103_c_compstr2906_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21343_dupName_412_i_unnamed_c_compstr0_shift_x(BITSELECT,21342)@219
    assign rightShiftStage1Idx1Rng8_uid21343_dupName_412_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21342_dupName_412_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21345_dupName_412_i_unnamed_c_compstr0_shift_x(BITJOIN,21344)@219
    assign rightShiftStage1Idx1_uid21345_dupName_412_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21343_dupName_412_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21338_dupName_412_i_unnamed_c_compstr0_shift_x(BITSELECT,21337)@219
    assign rightShiftStage0Idx1Rng4_uid21338_dupName_412_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_q[33:4];

    // rightShiftStage0Idx1_uid21340_dupName_412_i_unnamed_c_compstr0_shift_x(BITJOIN,21339)@219
    assign rightShiftStage0Idx1_uid21340_dupName_412_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21338_dupName_412_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21342_dupName_412_i_unnamed_c_compstr0_shift_x(MUX,21341)@219
    assign rightShiftStage0_uid21342_dupName_412_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21342_dupName_412_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_q or rightShiftStage0Idx1_uid21340_dupName_412_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21342_dupName_412_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21342_dupName_412_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compstr2904_q;
            1'b1 : rightShiftStage0_uid21342_dupName_412_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21340_dupName_412_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21342_dupName_412_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21347_dupName_412_i_unnamed_c_compstr0_shift_x(MUX,21346)@219
    assign rightShiftStage1_uid21347_dupName_412_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21347_dupName_412_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21342_dupName_412_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21345_dupName_412_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21347_dupName_412_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21347_dupName_412_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21342_dupName_412_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21347_dupName_412_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21345_dupName_412_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21347_dupName_412_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2907_vt_select_21(BITSELECT,11461)@219
    assign i_unnamed_c_compstr2907_vt_select_21_b = rightShiftStage1_uid21347_dupName_412_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2907_vt_join(BITJOIN,11460)@219
    assign i_unnamed_c_compstr2907_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2907_vt_select_21_b};

    // i_unnamed_c_compstr2908_sel_x(BITSELECT,6185)@219
    assign i_unnamed_c_compstr2908_sel_x_b = i_unnamed_c_compstr2907_vt_join_q[15:0];

    // i_unnamed_c_compstr2909_BitSelect_for_a(BITSELECT,27759)@219
    assign i_unnamed_c_compstr2909_BitSelect_for_a_b = i_unnamed_c_compstr2908_sel_x_b[0:0];

    // i_unnamed_c_compstr2909_join(BITJOIN,27760)@219
    assign i_unnamed_c_compstr2909_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2909_BitSelect_for_a_b};

    // i_unnamed_c_compstr2909_vt_select_0(BITSELECT,11466)@219
    assign i_unnamed_c_compstr2909_vt_select_0_b = i_unnamed_c_compstr2909_join_q[0:0];

    // redist106_i_unnamed_c_compstr2909_vt_select_0_b_1(DELAY,28334)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist106_i_unnamed_c_compstr2909_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2909_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2909_vt_join(BITJOIN,11465)@220
    assign i_unnamed_c_compstr2909_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist106_i_unnamed_c_compstr2909_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_103_c_compstr2910(ADD,6855)@220
    assign i_add_i_i_i_i_i126_i_103_c_compstr2910_a = {1'b0, i_unnamed_c_compstr2909_vt_join_q};
    assign i_add_i_i_i_i_i126_i_103_c_compstr2910_b = {1'b0, redist1276_i_conv_i_i_i_i97_i_103_c_compstr2906_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_103_c_compstr2910_o = $unsigned(i_add_i_i_i_i_i126_i_103_c_compstr2910_a) + $unsigned(i_add_i_i_i_i_i126_i_103_c_compstr2910_b);
    assign i_add_i_i_i_i_i126_i_103_c_compstr2910_q = i_add_i_i_i_i_i126_i_103_c_compstr2910_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_103_c_compstr2910_sel_x(BITSELECT,2049)@220
    assign bgTrunc_i_add_i_i_i_i_i126_i_103_c_compstr2910_sel_x_b = i_add_i_i_i_i_i126_i_103_c_compstr2910_q[15:0];

    // i_conv_i_i_i_i_i75_i277_104_c_compstr2930_sel_x(BITSELECT,3590)@220
    assign i_conv_i_i_i_i_i75_i277_104_c_compstr2930_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_103_c_compstr2910_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_104_c_compstr2930_vt_select_15(BITSELECT,7261)@220
    assign i_conv_i_i_i_i_i75_i277_104_c_compstr2930_vt_select_15_b = i_conv_i_i_i_i_i75_i277_104_c_compstr2930_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_104_c_compstr2930_vt_join(BITJOIN,7260)@220
    assign i_conv_i_i_i_i_i75_i277_104_c_compstr2930_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_104_c_compstr2930_vt_select_15_b};

    // leftShiftStage0_uid22946_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x(MUX,22945)@220
    assign leftShiftStage0_uid22946_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid22946_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_104_c_compstr2930_vt_join_q or leftShiftStage0Idx1_uid22944_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid22946_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid22946_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_104_c_compstr2930_vt_join_q;
            1'b1 : leftShiftStage0_uid22946_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid22944_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid22946_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid22951_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x(MUX,22950)@220
    assign leftShiftStage1_uid22951_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid22951_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_s or leftShiftStage0_uid22946_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid22949_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid22951_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid22951_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q = leftShiftStage0_uid22946_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid22951_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid22949_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid22951_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid22956_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x(MUX,22955)@220
    assign leftShiftStage2_uid22956_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid22956_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_s or leftShiftStage1_uid22951_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid22954_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid22956_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid22956_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q = leftShiftStage1_uid22951_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid22956_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid22954_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid22956_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_104_c_compstr2931_vt_select_28(BITSELECT,9055)@220
    assign i_shl_i_i_i_i_i77_i_104_c_compstr2931_vt_select_28_b = leftShiftStage2_uid22956_i_shl_i_i_i_i_i77_i_104_c_compstr0_shift_x_q[28:13];

    // redist505_i_shl_i_i_i_i_i77_i_104_c_compstr2931_vt_select_28_b_1(DELAY,28733)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist505_i_shl_i_i_i_i_i77_i_104_c_compstr2931_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_104_c_compstr2931_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_104_c_compstr2931_vt_join(BITJOIN,9054)@221
    assign i_shl_i_i_i_i_i77_i_104_c_compstr2931_vt_join_q = {redist505_i_shl_i_i_i_i_i77_i_104_c_compstr2931_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma(CHAINMULTADD,28103)@215 + 5
    // out q@221
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ah[0] <= redist979_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_209_tpl_207_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ah[1] <= redist978_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_208_tpl_207_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ch[0] <= redist725_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_209_tpl_207_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ch[1] <= redist724_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_208_tpl_207_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932(ADD,8399)@221
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compstr2927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compstr2929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compstr2928_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_104_c_compstr2931_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_104_c_compstr2931_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_o[33:0];

    // rightShiftStage0_uid21386_dupName_415_i_unnamed_c_compstr0_shift_x(MUX,21385)@221
    assign rightShiftStage0_uid21386_dupName_415_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21386_dupName_415_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_q or rightShiftStage0Idx1_uid21384_dupName_415_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21386_dupName_415_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21386_dupName_415_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_q;
            1'b1 : rightShiftStage0_uid21386_dupName_415_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21384_dupName_415_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21386_dupName_415_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21391_dupName_415_i_unnamed_c_compstr0_shift_x(MUX,21390)@221
    assign rightShiftStage1_uid21391_dupName_415_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21391_dupName_415_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21386_dupName_415_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21389_dupName_415_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21391_dupName_415_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21391_dupName_415_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21386_dupName_415_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21391_dupName_415_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21389_dupName_415_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21391_dupName_415_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21396_dupName_415_i_unnamed_c_compstr0_shift_x(MUX,21395)@221
    assign rightShiftStage2_uid21396_dupName_415_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21396_dupName_415_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21391_dupName_415_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21394_dupName_415_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21396_dupName_415_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21396_dupName_415_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21391_dupName_415_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21396_dupName_415_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21394_dupName_415_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21396_dupName_415_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2933_vt_select_20(BITSELECT,11485)@221
    assign i_unnamed_c_compstr2933_vt_select_20_b = rightShiftStage2_uid21396_dupName_415_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2933_vt_join(BITJOIN,11484)@221
    assign i_unnamed_c_compstr2933_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2933_vt_select_20_b};

    // i_conv_i_i_i_i97_i_104_c_compstr2934_sel_x(BITSELECT,3461)@221
    assign i_conv_i_i_i_i97_i_104_c_compstr2934_sel_x_b = i_unnamed_c_compstr2933_vt_join_q[15:0];

    // redist1275_i_conv_i_i_i_i97_i_104_c_compstr2934_sel_x_b_1(DELAY,29503)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1275_i_conv_i_i_i_i97_i_104_c_compstr2934_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_104_c_compstr2934_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21405_dupName_416_i_unnamed_c_compstr0_shift_x(BITSELECT,21404)@221
    assign rightShiftStage1Idx1Rng8_uid21405_dupName_416_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21404_dupName_416_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21407_dupName_416_i_unnamed_c_compstr0_shift_x(BITJOIN,21406)@221
    assign rightShiftStage1Idx1_uid21407_dupName_416_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21405_dupName_416_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21400_dupName_416_i_unnamed_c_compstr0_shift_x(BITSELECT,21399)@221
    assign rightShiftStage0Idx1Rng4_uid21400_dupName_416_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_q[33:4];

    // rightShiftStage0Idx1_uid21402_dupName_416_i_unnamed_c_compstr0_shift_x(BITJOIN,21401)@221
    assign rightShiftStage0Idx1_uid21402_dupName_416_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21400_dupName_416_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21404_dupName_416_i_unnamed_c_compstr0_shift_x(MUX,21403)@221
    assign rightShiftStage0_uid21404_dupName_416_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21404_dupName_416_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_q or rightShiftStage0Idx1_uid21402_dupName_416_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21404_dupName_416_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21404_dupName_416_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compstr2932_q;
            1'b1 : rightShiftStage0_uid21404_dupName_416_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21402_dupName_416_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21404_dupName_416_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21409_dupName_416_i_unnamed_c_compstr0_shift_x(MUX,21408)@221
    assign rightShiftStage1_uid21409_dupName_416_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21409_dupName_416_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21404_dupName_416_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21407_dupName_416_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21409_dupName_416_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21409_dupName_416_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21404_dupName_416_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21409_dupName_416_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21407_dupName_416_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21409_dupName_416_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2935_vt_select_21(BITSELECT,11488)@221
    assign i_unnamed_c_compstr2935_vt_select_21_b = rightShiftStage1_uid21409_dupName_416_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2935_vt_join(BITJOIN,11487)@221
    assign i_unnamed_c_compstr2935_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2935_vt_select_21_b};

    // i_unnamed_c_compstr2936_sel_x(BITSELECT,6188)@221
    assign i_unnamed_c_compstr2936_sel_x_b = i_unnamed_c_compstr2935_vt_join_q[15:0];

    // i_unnamed_c_compstr2937_BitSelect_for_a(BITSELECT,27765)@221
    assign i_unnamed_c_compstr2937_BitSelect_for_a_b = i_unnamed_c_compstr2936_sel_x_b[0:0];

    // i_unnamed_c_compstr2937_join(BITJOIN,27766)@221
    assign i_unnamed_c_compstr2937_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2937_BitSelect_for_a_b};

    // i_unnamed_c_compstr2937_vt_select_0(BITSELECT,11493)@221
    assign i_unnamed_c_compstr2937_vt_select_0_b = i_unnamed_c_compstr2937_join_q[0:0];

    // redist104_i_unnamed_c_compstr2937_vt_select_0_b_1(DELAY,28332)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist104_i_unnamed_c_compstr2937_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2937_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2937_vt_join(BITJOIN,11492)@222
    assign i_unnamed_c_compstr2937_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist104_i_unnamed_c_compstr2937_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_104_c_compstr2938(ADD,6856)@222
    assign i_add_i_i_i_i_i126_i_104_c_compstr2938_a = {1'b0, i_unnamed_c_compstr2937_vt_join_q};
    assign i_add_i_i_i_i_i126_i_104_c_compstr2938_b = {1'b0, redist1275_i_conv_i_i_i_i97_i_104_c_compstr2934_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_104_c_compstr2938_o = $unsigned(i_add_i_i_i_i_i126_i_104_c_compstr2938_a) + $unsigned(i_add_i_i_i_i_i126_i_104_c_compstr2938_b);
    assign i_add_i_i_i_i_i126_i_104_c_compstr2938_q = i_add_i_i_i_i_i126_i_104_c_compstr2938_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_104_c_compstr2938_sel_x(BITSELECT,2050)@222
    assign bgTrunc_i_add_i_i_i_i_i126_i_104_c_compstr2938_sel_x_b = i_add_i_i_i_i_i126_i_104_c_compstr2938_q[15:0];

    // i_conv_i_i_i_i_i75_i277_105_c_compstr2958_sel_x(BITSELECT,3591)@222
    assign i_conv_i_i_i_i_i75_i277_105_c_compstr2958_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_104_c_compstr2938_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_105_c_compstr2958_vt_select_15(BITSELECT,7265)@222
    assign i_conv_i_i_i_i_i75_i277_105_c_compstr2958_vt_select_15_b = i_conv_i_i_i_i_i75_i277_105_c_compstr2958_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_105_c_compstr2958_vt_join(BITJOIN,7264)@222
    assign i_conv_i_i_i_i_i75_i277_105_c_compstr2958_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_105_c_compstr2958_vt_select_15_b};

    // leftShiftStage0_uid22964_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x(MUX,22963)@222
    assign leftShiftStage0_uid22964_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid22964_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_105_c_compstr2958_vt_join_q or leftShiftStage0Idx1_uid22962_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid22964_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid22964_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_105_c_compstr2958_vt_join_q;
            1'b1 : leftShiftStage0_uid22964_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid22962_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid22964_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid22969_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x(MUX,22968)@222
    assign leftShiftStage1_uid22969_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid22969_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_s or leftShiftStage0_uid22964_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid22967_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid22969_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid22969_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q = leftShiftStage0_uid22964_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid22969_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid22967_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid22969_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid22974_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x(MUX,22973)@222
    assign leftShiftStage2_uid22974_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid22974_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_s or leftShiftStage1_uid22969_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid22972_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid22974_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid22974_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q = leftShiftStage1_uid22969_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid22974_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid22972_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid22974_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_105_c_compstr2959_vt_select_28(BITSELECT,9058)@222
    assign i_shl_i_i_i_i_i77_i_105_c_compstr2959_vt_select_28_b = leftShiftStage2_uid22974_i_shl_i_i_i_i_i77_i_105_c_compstr0_shift_x_q[28:13];

    // redist504_i_shl_i_i_i_i_i77_i_105_c_compstr2959_vt_select_28_b_1(DELAY,28732)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist504_i_shl_i_i_i_i_i77_i_105_c_compstr2959_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_105_c_compstr2959_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_105_c_compstr2959_vt_join(BITJOIN,9057)@223
    assign i_shl_i_i_i_i_i77_i_105_c_compstr2959_vt_join_q = {redist504_i_shl_i_i_i_i_i77_i_105_c_compstr2959_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma(CHAINMULTADD,28104)@217 + 5
    // out q@223
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ah[0] <= redist981_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_211_tpl_209_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ah[1] <= redist980_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_210_tpl_209_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ch[0] <= redist727_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_211_tpl_209_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ch[1] <= redist726_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_210_tpl_209_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960(ADD,8400)@223
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compstr2955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compstr2957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compstr2956_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_105_c_compstr2959_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_105_c_compstr2959_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_o[33:0];

    // rightShiftStage0_uid21448_dupName_419_i_unnamed_c_compstr0_shift_x(MUX,21447)@223
    assign rightShiftStage0_uid21448_dupName_419_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21448_dupName_419_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_q or rightShiftStage0Idx1_uid21446_dupName_419_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21448_dupName_419_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21448_dupName_419_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_q;
            1'b1 : rightShiftStage0_uid21448_dupName_419_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21446_dupName_419_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21448_dupName_419_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21453_dupName_419_i_unnamed_c_compstr0_shift_x(MUX,21452)@223
    assign rightShiftStage1_uid21453_dupName_419_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21453_dupName_419_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21448_dupName_419_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21451_dupName_419_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21453_dupName_419_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21453_dupName_419_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21448_dupName_419_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21453_dupName_419_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21451_dupName_419_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21453_dupName_419_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21458_dupName_419_i_unnamed_c_compstr0_shift_x(MUX,21457)@223
    assign rightShiftStage2_uid21458_dupName_419_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21458_dupName_419_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21453_dupName_419_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21456_dupName_419_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21458_dupName_419_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21458_dupName_419_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21453_dupName_419_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21458_dupName_419_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21456_dupName_419_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21458_dupName_419_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2961_vt_select_20(BITSELECT,11510)@223
    assign i_unnamed_c_compstr2961_vt_select_20_b = rightShiftStage2_uid21458_dupName_419_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2961_vt_join(BITJOIN,11509)@223
    assign i_unnamed_c_compstr2961_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2961_vt_select_20_b};

    // i_conv_i_i_i_i97_i_105_c_compstr2962_sel_x(BITSELECT,3462)@223
    assign i_conv_i_i_i_i97_i_105_c_compstr2962_sel_x_b = i_unnamed_c_compstr2961_vt_join_q[15:0];

    // redist1274_i_conv_i_i_i_i97_i_105_c_compstr2962_sel_x_b_1(DELAY,29502)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1274_i_conv_i_i_i_i97_i_105_c_compstr2962_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_105_c_compstr2962_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21467_dupName_420_i_unnamed_c_compstr0_shift_x(BITSELECT,21466)@223
    assign rightShiftStage1Idx1Rng8_uid21467_dupName_420_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21466_dupName_420_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21469_dupName_420_i_unnamed_c_compstr0_shift_x(BITJOIN,21468)@223
    assign rightShiftStage1Idx1_uid21469_dupName_420_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21467_dupName_420_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21462_dupName_420_i_unnamed_c_compstr0_shift_x(BITSELECT,21461)@223
    assign rightShiftStage0Idx1Rng4_uid21462_dupName_420_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_q[33:4];

    // rightShiftStage0Idx1_uid21464_dupName_420_i_unnamed_c_compstr0_shift_x(BITJOIN,21463)@223
    assign rightShiftStage0Idx1_uid21464_dupName_420_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21462_dupName_420_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21466_dupName_420_i_unnamed_c_compstr0_shift_x(MUX,21465)@223
    assign rightShiftStage0_uid21466_dupName_420_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21466_dupName_420_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_q or rightShiftStage0Idx1_uid21464_dupName_420_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21466_dupName_420_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21466_dupName_420_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compstr2960_q;
            1'b1 : rightShiftStage0_uid21466_dupName_420_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21464_dupName_420_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21466_dupName_420_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21471_dupName_420_i_unnamed_c_compstr0_shift_x(MUX,21470)@223
    assign rightShiftStage1_uid21471_dupName_420_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21471_dupName_420_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21466_dupName_420_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21469_dupName_420_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21471_dupName_420_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21471_dupName_420_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21466_dupName_420_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21471_dupName_420_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21469_dupName_420_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21471_dupName_420_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2963_vt_select_21(BITSELECT,11513)@223
    assign i_unnamed_c_compstr2963_vt_select_21_b = rightShiftStage1_uid21471_dupName_420_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2963_vt_join(BITJOIN,11512)@223
    assign i_unnamed_c_compstr2963_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2963_vt_select_21_b};

    // i_unnamed_c_compstr2964_sel_x(BITSELECT,6190)@223
    assign i_unnamed_c_compstr2964_sel_x_b = i_unnamed_c_compstr2963_vt_join_q[15:0];

    // i_unnamed_c_compstr2965_BitSelect_for_a(BITSELECT,27769)@223
    assign i_unnamed_c_compstr2965_BitSelect_for_a_b = i_unnamed_c_compstr2964_sel_x_b[0:0];

    // i_unnamed_c_compstr2965_join(BITJOIN,27770)@223
    assign i_unnamed_c_compstr2965_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2965_BitSelect_for_a_b};

    // i_unnamed_c_compstr2965_vt_select_0(BITSELECT,11518)@223
    assign i_unnamed_c_compstr2965_vt_select_0_b = i_unnamed_c_compstr2965_join_q[0:0];

    // redist101_i_unnamed_c_compstr2965_vt_select_0_b_1(DELAY,28329)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist101_i_unnamed_c_compstr2965_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2965_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2965_vt_join(BITJOIN,11517)@224
    assign i_unnamed_c_compstr2965_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist101_i_unnamed_c_compstr2965_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_105_c_compstr2966(ADD,6857)@224
    assign i_add_i_i_i_i_i126_i_105_c_compstr2966_a = {1'b0, i_unnamed_c_compstr2965_vt_join_q};
    assign i_add_i_i_i_i_i126_i_105_c_compstr2966_b = {1'b0, redist1274_i_conv_i_i_i_i97_i_105_c_compstr2962_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_105_c_compstr2966_o = $unsigned(i_add_i_i_i_i_i126_i_105_c_compstr2966_a) + $unsigned(i_add_i_i_i_i_i126_i_105_c_compstr2966_b);
    assign i_add_i_i_i_i_i126_i_105_c_compstr2966_q = i_add_i_i_i_i_i126_i_105_c_compstr2966_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_105_c_compstr2966_sel_x(BITSELECT,2051)@224
    assign bgTrunc_i_add_i_i_i_i_i126_i_105_c_compstr2966_sel_x_b = i_add_i_i_i_i_i126_i_105_c_compstr2966_q[15:0];

    // i_conv_i_i_i_i_i75_i277_106_c_compstr2986_sel_x(BITSELECT,3592)@224
    assign i_conv_i_i_i_i_i75_i277_106_c_compstr2986_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_105_c_compstr2966_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_106_c_compstr2986_vt_select_15(BITSELECT,7269)@224
    assign i_conv_i_i_i_i_i75_i277_106_c_compstr2986_vt_select_15_b = i_conv_i_i_i_i_i75_i277_106_c_compstr2986_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_106_c_compstr2986_vt_join(BITJOIN,7268)@224
    assign i_conv_i_i_i_i_i75_i277_106_c_compstr2986_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_106_c_compstr2986_vt_select_15_b};

    // leftShiftStage0_uid22982_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x(MUX,22981)@224
    assign leftShiftStage0_uid22982_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid22982_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_106_c_compstr2986_vt_join_q or leftShiftStage0Idx1_uid22980_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid22982_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid22982_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_106_c_compstr2986_vt_join_q;
            1'b1 : leftShiftStage0_uid22982_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid22980_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid22982_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid22987_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x(MUX,22986)@224
    assign leftShiftStage1_uid22987_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid22987_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_s or leftShiftStage0_uid22982_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid22985_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid22987_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid22987_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q = leftShiftStage0_uid22982_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid22987_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid22985_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid22987_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid22992_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x(MUX,22991)@224
    assign leftShiftStage2_uid22992_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid22992_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_s or leftShiftStage1_uid22987_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid22990_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid22992_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid22992_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q = leftShiftStage1_uid22987_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid22992_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid22990_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid22992_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_106_c_compstr2987_vt_select_28(BITSELECT,9061)@224
    assign i_shl_i_i_i_i_i77_i_106_c_compstr2987_vt_select_28_b = leftShiftStage2_uid22992_i_shl_i_i_i_i_i77_i_106_c_compstr0_shift_x_q[28:13];

    // redist503_i_shl_i_i_i_i_i77_i_106_c_compstr2987_vt_select_28_b_1(DELAY,28731)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist503_i_shl_i_i_i_i_i77_i_106_c_compstr2987_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_106_c_compstr2987_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_106_c_compstr2987_vt_join(BITJOIN,9060)@225
    assign i_shl_i_i_i_i_i77_i_106_c_compstr2987_vt_join_q = {redist503_i_shl_i_i_i_i_i77_i_106_c_compstr2987_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma(CHAINMULTADD,28105)@219 + 5
    // out q@225
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ah[0] <= redist983_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_213_tpl_211_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ah[1] <= redist982_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_212_tpl_211_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ch[0] <= redist729_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_213_tpl_211_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ch[1] <= redist728_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_212_tpl_211_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988(ADD,8401)@225
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compstr2983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compstr2985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compstr2984_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_106_c_compstr2987_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_106_c_compstr2987_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_o[33:0];

    // rightShiftStage0_uid21510_dupName_423_i_unnamed_c_compstr0_shift_x(MUX,21509)@225
    assign rightShiftStage0_uid21510_dupName_423_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21510_dupName_423_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_q or rightShiftStage0Idx1_uid21508_dupName_423_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21510_dupName_423_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21510_dupName_423_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_q;
            1'b1 : rightShiftStage0_uid21510_dupName_423_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21508_dupName_423_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21510_dupName_423_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21515_dupName_423_i_unnamed_c_compstr0_shift_x(MUX,21514)@225
    assign rightShiftStage1_uid21515_dupName_423_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21515_dupName_423_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21510_dupName_423_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21513_dupName_423_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21515_dupName_423_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21515_dupName_423_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21510_dupName_423_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21515_dupName_423_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21513_dupName_423_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21515_dupName_423_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21520_dupName_423_i_unnamed_c_compstr0_shift_x(MUX,21519)@225
    assign rightShiftStage2_uid21520_dupName_423_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21520_dupName_423_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21515_dupName_423_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21518_dupName_423_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21520_dupName_423_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21520_dupName_423_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21515_dupName_423_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21520_dupName_423_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21518_dupName_423_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21520_dupName_423_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2989_vt_select_20(BITSELECT,11532)@225
    assign i_unnamed_c_compstr2989_vt_select_20_b = rightShiftStage2_uid21520_dupName_423_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr2989_vt_join(BITJOIN,11531)@225
    assign i_unnamed_c_compstr2989_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr2989_vt_select_20_b};

    // i_conv_i_i_i_i97_i_106_c_compstr2990_sel_x(BITSELECT,3463)@225
    assign i_conv_i_i_i_i97_i_106_c_compstr2990_sel_x_b = i_unnamed_c_compstr2989_vt_join_q[15:0];

    // redist1273_i_conv_i_i_i_i97_i_106_c_compstr2990_sel_x_b_1(DELAY,29501)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1273_i_conv_i_i_i_i97_i_106_c_compstr2990_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_106_c_compstr2990_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21529_dupName_424_i_unnamed_c_compstr0_shift_x(BITSELECT,21528)@225
    assign rightShiftStage1Idx1Rng8_uid21529_dupName_424_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21528_dupName_424_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21531_dupName_424_i_unnamed_c_compstr0_shift_x(BITJOIN,21530)@225
    assign rightShiftStage1Idx1_uid21531_dupName_424_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21529_dupName_424_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21524_dupName_424_i_unnamed_c_compstr0_shift_x(BITSELECT,21523)@225
    assign rightShiftStage0Idx1Rng4_uid21524_dupName_424_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_q[33:4];

    // rightShiftStage0Idx1_uid21526_dupName_424_i_unnamed_c_compstr0_shift_x(BITJOIN,21525)@225
    assign rightShiftStage0Idx1_uid21526_dupName_424_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21524_dupName_424_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21528_dupName_424_i_unnamed_c_compstr0_shift_x(MUX,21527)@225
    assign rightShiftStage0_uid21528_dupName_424_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21528_dupName_424_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_q or rightShiftStage0Idx1_uid21526_dupName_424_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21528_dupName_424_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21528_dupName_424_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compstr2988_q;
            1'b1 : rightShiftStage0_uid21528_dupName_424_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21526_dupName_424_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21528_dupName_424_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21533_dupName_424_i_unnamed_c_compstr0_shift_x(MUX,21532)@225
    assign rightShiftStage1_uid21533_dupName_424_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21533_dupName_424_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21528_dupName_424_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21531_dupName_424_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21533_dupName_424_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21533_dupName_424_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21528_dupName_424_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21533_dupName_424_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21531_dupName_424_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21533_dupName_424_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr2991_vt_select_21(BITSELECT,11535)@225
    assign i_unnamed_c_compstr2991_vt_select_21_b = rightShiftStage1_uid21533_dupName_424_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr2991_vt_join(BITJOIN,11534)@225
    assign i_unnamed_c_compstr2991_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr2991_vt_select_21_b};

    // i_unnamed_c_compstr2992_sel_x(BITSELECT,6192)@225
    assign i_unnamed_c_compstr2992_sel_x_b = i_unnamed_c_compstr2991_vt_join_q[15:0];

    // i_unnamed_c_compstr2993_BitSelect_for_a(BITSELECT,27773)@225
    assign i_unnamed_c_compstr2993_BitSelect_for_a_b = i_unnamed_c_compstr2992_sel_x_b[0:0];

    // i_unnamed_c_compstr2993_join(BITJOIN,27774)@225
    assign i_unnamed_c_compstr2993_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr2993_BitSelect_for_a_b};

    // i_unnamed_c_compstr2993_vt_select_0(BITSELECT,11540)@225
    assign i_unnamed_c_compstr2993_vt_select_0_b = i_unnamed_c_compstr2993_join_q[0:0];

    // redist99_i_unnamed_c_compstr2993_vt_select_0_b_1(DELAY,28327)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist99_i_unnamed_c_compstr2993_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr2993_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr2993_vt_join(BITJOIN,11539)@226
    assign i_unnamed_c_compstr2993_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist99_i_unnamed_c_compstr2993_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_106_c_compstr2994(ADD,6858)@226
    assign i_add_i_i_i_i_i126_i_106_c_compstr2994_a = {1'b0, i_unnamed_c_compstr2993_vt_join_q};
    assign i_add_i_i_i_i_i126_i_106_c_compstr2994_b = {1'b0, redist1273_i_conv_i_i_i_i97_i_106_c_compstr2990_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_106_c_compstr2994_o = $unsigned(i_add_i_i_i_i_i126_i_106_c_compstr2994_a) + $unsigned(i_add_i_i_i_i_i126_i_106_c_compstr2994_b);
    assign i_add_i_i_i_i_i126_i_106_c_compstr2994_q = i_add_i_i_i_i_i126_i_106_c_compstr2994_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_106_c_compstr2994_sel_x(BITSELECT,2052)@226
    assign bgTrunc_i_add_i_i_i_i_i126_i_106_c_compstr2994_sel_x_b = i_add_i_i_i_i_i126_i_106_c_compstr2994_q[15:0];

    // i_conv_i_i_i_i_i75_i277_107_c_compstr3014_sel_x(BITSELECT,3593)@226
    assign i_conv_i_i_i_i_i75_i277_107_c_compstr3014_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_106_c_compstr2994_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_107_c_compstr3014_vt_select_15(BITSELECT,7273)@226
    assign i_conv_i_i_i_i_i75_i277_107_c_compstr3014_vt_select_15_b = i_conv_i_i_i_i_i75_i277_107_c_compstr3014_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_107_c_compstr3014_vt_join(BITJOIN,7272)@226
    assign i_conv_i_i_i_i_i75_i277_107_c_compstr3014_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_107_c_compstr3014_vt_select_15_b};

    // leftShiftStage0_uid23000_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x(MUX,22999)@226
    assign leftShiftStage0_uid23000_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23000_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_107_c_compstr3014_vt_join_q or leftShiftStage0Idx1_uid22998_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23000_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23000_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_107_c_compstr3014_vt_join_q;
            1'b1 : leftShiftStage0_uid23000_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid22998_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23000_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23005_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x(MUX,23004)@226
    assign leftShiftStage1_uid23005_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23005_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_s or leftShiftStage0_uid23000_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23003_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23005_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23005_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q = leftShiftStage0_uid23000_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23005_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23003_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23005_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23010_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x(MUX,23009)@226
    assign leftShiftStage2_uid23010_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23010_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_s or leftShiftStage1_uid23005_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23008_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23010_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23010_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q = leftShiftStage1_uid23005_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23010_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23008_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23010_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_107_c_compstr3015_vt_select_28(BITSELECT,9064)@226
    assign i_shl_i_i_i_i_i77_i_107_c_compstr3015_vt_select_28_b = leftShiftStage2_uid23010_i_shl_i_i_i_i_i77_i_107_c_compstr0_shift_x_q[28:13];

    // redist502_i_shl_i_i_i_i_i77_i_107_c_compstr3015_vt_select_28_b_1(DELAY,28730)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist502_i_shl_i_i_i_i_i77_i_107_c_compstr3015_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_107_c_compstr3015_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_107_c_compstr3015_vt_join(BITJOIN,9063)@227
    assign i_shl_i_i_i_i_i77_i_107_c_compstr3015_vt_join_q = {redist502_i_shl_i_i_i_i_i77_i_107_c_compstr3015_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma(CHAINMULTADD,28106)@221 + 5
    // out q@227
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ah[0] <= redist985_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_215_tpl_213_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ah[1] <= redist984_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_214_tpl_213_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ch[0] <= redist731_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_215_tpl_213_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ch[1] <= redist730_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_214_tpl_213_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016(ADD,8402)@227
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compstr3011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compstr3013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compstr3012_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_107_c_compstr3015_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_107_c_compstr3015_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_o[33:0];

    // rightShiftStage0_uid21572_dupName_427_i_unnamed_c_compstr0_shift_x(MUX,21571)@227
    assign rightShiftStage0_uid21572_dupName_427_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21572_dupName_427_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_q or rightShiftStage0Idx1_uid21570_dupName_427_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21572_dupName_427_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21572_dupName_427_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_q;
            1'b1 : rightShiftStage0_uid21572_dupName_427_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21570_dupName_427_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21572_dupName_427_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21577_dupName_427_i_unnamed_c_compstr0_shift_x(MUX,21576)@227
    assign rightShiftStage1_uid21577_dupName_427_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21577_dupName_427_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21572_dupName_427_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21575_dupName_427_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21577_dupName_427_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21577_dupName_427_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21572_dupName_427_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21577_dupName_427_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21575_dupName_427_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21577_dupName_427_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21582_dupName_427_i_unnamed_c_compstr0_shift_x(MUX,21581)@227
    assign rightShiftStage2_uid21582_dupName_427_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21582_dupName_427_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21577_dupName_427_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21580_dupName_427_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21582_dupName_427_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21582_dupName_427_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21577_dupName_427_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21582_dupName_427_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21580_dupName_427_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21582_dupName_427_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3017_vt_select_20(BITSELECT,11554)@227
    assign i_unnamed_c_compstr3017_vt_select_20_b = rightShiftStage2_uid21582_dupName_427_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3017_vt_join(BITJOIN,11553)@227
    assign i_unnamed_c_compstr3017_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3017_vt_select_20_b};

    // i_conv_i_i_i_i97_i_107_c_compstr3018_sel_x(BITSELECT,3464)@227
    assign i_conv_i_i_i_i97_i_107_c_compstr3018_sel_x_b = i_unnamed_c_compstr3017_vt_join_q[15:0];

    // redist1272_i_conv_i_i_i_i97_i_107_c_compstr3018_sel_x_b_1(DELAY,29500)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1272_i_conv_i_i_i_i97_i_107_c_compstr3018_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_107_c_compstr3018_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21591_dupName_428_i_unnamed_c_compstr0_shift_x(BITSELECT,21590)@227
    assign rightShiftStage1Idx1Rng8_uid21591_dupName_428_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21590_dupName_428_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21593_dupName_428_i_unnamed_c_compstr0_shift_x(BITJOIN,21592)@227
    assign rightShiftStage1Idx1_uid21593_dupName_428_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21591_dupName_428_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21586_dupName_428_i_unnamed_c_compstr0_shift_x(BITSELECT,21585)@227
    assign rightShiftStage0Idx1Rng4_uid21586_dupName_428_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_q[33:4];

    // rightShiftStage0Idx1_uid21588_dupName_428_i_unnamed_c_compstr0_shift_x(BITJOIN,21587)@227
    assign rightShiftStage0Idx1_uid21588_dupName_428_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21586_dupName_428_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21590_dupName_428_i_unnamed_c_compstr0_shift_x(MUX,21589)@227
    assign rightShiftStage0_uid21590_dupName_428_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21590_dupName_428_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_q or rightShiftStage0Idx1_uid21588_dupName_428_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21590_dupName_428_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21590_dupName_428_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compstr3016_q;
            1'b1 : rightShiftStage0_uid21590_dupName_428_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21588_dupName_428_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21590_dupName_428_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21595_dupName_428_i_unnamed_c_compstr0_shift_x(MUX,21594)@227
    assign rightShiftStage1_uid21595_dupName_428_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21595_dupName_428_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21590_dupName_428_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21593_dupName_428_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21595_dupName_428_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21595_dupName_428_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21590_dupName_428_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21595_dupName_428_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21593_dupName_428_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21595_dupName_428_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3019_vt_select_21(BITSELECT,11557)@227
    assign i_unnamed_c_compstr3019_vt_select_21_b = rightShiftStage1_uid21595_dupName_428_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3019_vt_join(BITJOIN,11556)@227
    assign i_unnamed_c_compstr3019_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3019_vt_select_21_b};

    // i_unnamed_c_compstr3020_sel_x(BITSELECT,6194)@227
    assign i_unnamed_c_compstr3020_sel_x_b = i_unnamed_c_compstr3019_vt_join_q[15:0];

    // i_unnamed_c_compstr3021_BitSelect_for_a(BITSELECT,27777)@227
    assign i_unnamed_c_compstr3021_BitSelect_for_a_b = i_unnamed_c_compstr3020_sel_x_b[0:0];

    // i_unnamed_c_compstr3021_join(BITJOIN,27778)@227
    assign i_unnamed_c_compstr3021_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3021_BitSelect_for_a_b};

    // i_unnamed_c_compstr3021_vt_select_0(BITSELECT,11565)@227
    assign i_unnamed_c_compstr3021_vt_select_0_b = i_unnamed_c_compstr3021_join_q[0:0];

    // redist97_i_unnamed_c_compstr3021_vt_select_0_b_1(DELAY,28325)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist97_i_unnamed_c_compstr3021_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3021_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3021_vt_join(BITJOIN,11564)@228
    assign i_unnamed_c_compstr3021_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist97_i_unnamed_c_compstr3021_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_107_c_compstr3022(ADD,6859)@228
    assign i_add_i_i_i_i_i126_i_107_c_compstr3022_a = {1'b0, i_unnamed_c_compstr3021_vt_join_q};
    assign i_add_i_i_i_i_i126_i_107_c_compstr3022_b = {1'b0, redist1272_i_conv_i_i_i_i97_i_107_c_compstr3018_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_107_c_compstr3022_o = $unsigned(i_add_i_i_i_i_i126_i_107_c_compstr3022_a) + $unsigned(i_add_i_i_i_i_i126_i_107_c_compstr3022_b);
    assign i_add_i_i_i_i_i126_i_107_c_compstr3022_q = i_add_i_i_i_i_i126_i_107_c_compstr3022_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_107_c_compstr3022_sel_x(BITSELECT,2053)@228
    assign bgTrunc_i_add_i_i_i_i_i126_i_107_c_compstr3022_sel_x_b = i_add_i_i_i_i_i126_i_107_c_compstr3022_q[15:0];

    // i_conv_i_i_i_i_i75_i277_108_c_compstr3042_sel_x(BITSELECT,3594)@228
    assign i_conv_i_i_i_i_i75_i277_108_c_compstr3042_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_107_c_compstr3022_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_108_c_compstr3042_vt_select_15(BITSELECT,7277)@228
    assign i_conv_i_i_i_i_i75_i277_108_c_compstr3042_vt_select_15_b = i_conv_i_i_i_i_i75_i277_108_c_compstr3042_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_108_c_compstr3042_vt_join(BITJOIN,7276)@228
    assign i_conv_i_i_i_i_i75_i277_108_c_compstr3042_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_108_c_compstr3042_vt_select_15_b};

    // leftShiftStage0_uid23018_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x(MUX,23017)@228
    assign leftShiftStage0_uid23018_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23018_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_108_c_compstr3042_vt_join_q or leftShiftStage0Idx1_uid23016_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23018_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23018_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_108_c_compstr3042_vt_join_q;
            1'b1 : leftShiftStage0_uid23018_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23016_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23018_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23023_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x(MUX,23022)@228
    assign leftShiftStage1_uid23023_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23023_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_s or leftShiftStage0_uid23018_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23021_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23023_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23023_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q = leftShiftStage0_uid23018_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23023_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23021_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23023_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23028_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x(MUX,23027)@228
    assign leftShiftStage2_uid23028_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23028_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_s or leftShiftStage1_uid23023_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23026_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23028_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23028_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q = leftShiftStage1_uid23023_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23028_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23026_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23028_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_108_c_compstr3043_vt_select_28(BITSELECT,9067)@228
    assign i_shl_i_i_i_i_i77_i_108_c_compstr3043_vt_select_28_b = leftShiftStage2_uid23028_i_shl_i_i_i_i_i77_i_108_c_compstr0_shift_x_q[28:13];

    // redist501_i_shl_i_i_i_i_i77_i_108_c_compstr3043_vt_select_28_b_1(DELAY,28729)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist501_i_shl_i_i_i_i_i77_i_108_c_compstr3043_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_108_c_compstr3043_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_108_c_compstr3043_vt_join(BITJOIN,9066)@229
    assign i_shl_i_i_i_i_i77_i_108_c_compstr3043_vt_join_q = {redist501_i_shl_i_i_i_i_i77_i_108_c_compstr3043_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma(CHAINMULTADD,28107)@223 + 5
    // out q@229
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ah[0] <= redist987_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_217_tpl_215_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ah[1] <= redist986_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_216_tpl_215_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ch[0] <= redist733_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_217_tpl_215_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ch[1] <= redist732_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_216_tpl_215_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044(ADD,8403)@229
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compstr3039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compstr3041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compstr3040_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_108_c_compstr3043_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_108_c_compstr3043_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_o[33:0];

    // rightShiftStage0_uid21634_dupName_431_i_unnamed_c_compstr0_shift_x(MUX,21633)@229
    assign rightShiftStage0_uid21634_dupName_431_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21634_dupName_431_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_q or rightShiftStage0Idx1_uid21632_dupName_431_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21634_dupName_431_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21634_dupName_431_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_q;
            1'b1 : rightShiftStage0_uid21634_dupName_431_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21632_dupName_431_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21634_dupName_431_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21639_dupName_431_i_unnamed_c_compstr0_shift_x(MUX,21638)@229
    assign rightShiftStage1_uid21639_dupName_431_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21639_dupName_431_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21634_dupName_431_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21637_dupName_431_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21639_dupName_431_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21639_dupName_431_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21634_dupName_431_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21639_dupName_431_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21637_dupName_431_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21639_dupName_431_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21644_dupName_431_i_unnamed_c_compstr0_shift_x(MUX,21643)@229
    assign rightShiftStage2_uid21644_dupName_431_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21644_dupName_431_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21639_dupName_431_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21642_dupName_431_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21644_dupName_431_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21644_dupName_431_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21639_dupName_431_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21644_dupName_431_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21642_dupName_431_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21644_dupName_431_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3045_vt_select_20(BITSELECT,11582)@229
    assign i_unnamed_c_compstr3045_vt_select_20_b = rightShiftStage2_uid21644_dupName_431_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3045_vt_join(BITJOIN,11581)@229
    assign i_unnamed_c_compstr3045_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3045_vt_select_20_b};

    // i_conv_i_i_i_i97_i_108_c_compstr3046_sel_x(BITSELECT,3465)@229
    assign i_conv_i_i_i_i97_i_108_c_compstr3046_sel_x_b = i_unnamed_c_compstr3045_vt_join_q[15:0];

    // redist1271_i_conv_i_i_i_i97_i_108_c_compstr3046_sel_x_b_1(DELAY,29499)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1271_i_conv_i_i_i_i97_i_108_c_compstr3046_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_108_c_compstr3046_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21653_dupName_432_i_unnamed_c_compstr0_shift_x(BITSELECT,21652)@229
    assign rightShiftStage1Idx1Rng8_uid21653_dupName_432_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21652_dupName_432_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21655_dupName_432_i_unnamed_c_compstr0_shift_x(BITJOIN,21654)@229
    assign rightShiftStage1Idx1_uid21655_dupName_432_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21653_dupName_432_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21648_dupName_432_i_unnamed_c_compstr0_shift_x(BITSELECT,21647)@229
    assign rightShiftStage0Idx1Rng4_uid21648_dupName_432_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_q[33:4];

    // rightShiftStage0Idx1_uid21650_dupName_432_i_unnamed_c_compstr0_shift_x(BITJOIN,21649)@229
    assign rightShiftStage0Idx1_uid21650_dupName_432_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21648_dupName_432_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21652_dupName_432_i_unnamed_c_compstr0_shift_x(MUX,21651)@229
    assign rightShiftStage0_uid21652_dupName_432_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21652_dupName_432_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_q or rightShiftStage0Idx1_uid21650_dupName_432_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21652_dupName_432_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21652_dupName_432_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compstr3044_q;
            1'b1 : rightShiftStage0_uid21652_dupName_432_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21650_dupName_432_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21652_dupName_432_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21657_dupName_432_i_unnamed_c_compstr0_shift_x(MUX,21656)@229
    assign rightShiftStage1_uid21657_dupName_432_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21657_dupName_432_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21652_dupName_432_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21655_dupName_432_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21657_dupName_432_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21657_dupName_432_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21652_dupName_432_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21657_dupName_432_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21655_dupName_432_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21657_dupName_432_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3047_vt_select_21(BITSELECT,11585)@229
    assign i_unnamed_c_compstr3047_vt_select_21_b = rightShiftStage1_uid21657_dupName_432_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3047_vt_join(BITJOIN,11584)@229
    assign i_unnamed_c_compstr3047_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3047_vt_select_21_b};

    // i_unnamed_c_compstr3048_sel_x(BITSELECT,6197)@229
    assign i_unnamed_c_compstr3048_sel_x_b = i_unnamed_c_compstr3047_vt_join_q[15:0];

    // i_unnamed_c_compstr3049_BitSelect_for_a(BITSELECT,27781)@229
    assign i_unnamed_c_compstr3049_BitSelect_for_a_b = i_unnamed_c_compstr3048_sel_x_b[0:0];

    // i_unnamed_c_compstr3049_join(BITJOIN,27782)@229
    assign i_unnamed_c_compstr3049_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3049_BitSelect_for_a_b};

    // i_unnamed_c_compstr3049_vt_select_0(BITSELECT,11590)@229
    assign i_unnamed_c_compstr3049_vt_select_0_b = i_unnamed_c_compstr3049_join_q[0:0];

    // redist95_i_unnamed_c_compstr3049_vt_select_0_b_1(DELAY,28323)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist95_i_unnamed_c_compstr3049_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3049_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3049_vt_join(BITJOIN,11589)@230
    assign i_unnamed_c_compstr3049_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist95_i_unnamed_c_compstr3049_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_108_c_compstr3050(ADD,6860)@230
    assign i_add_i_i_i_i_i126_i_108_c_compstr3050_a = {1'b0, i_unnamed_c_compstr3049_vt_join_q};
    assign i_add_i_i_i_i_i126_i_108_c_compstr3050_b = {1'b0, redist1271_i_conv_i_i_i_i97_i_108_c_compstr3046_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_108_c_compstr3050_o = $unsigned(i_add_i_i_i_i_i126_i_108_c_compstr3050_a) + $unsigned(i_add_i_i_i_i_i126_i_108_c_compstr3050_b);
    assign i_add_i_i_i_i_i126_i_108_c_compstr3050_q = i_add_i_i_i_i_i126_i_108_c_compstr3050_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_108_c_compstr3050_sel_x(BITSELECT,2054)@230
    assign bgTrunc_i_add_i_i_i_i_i126_i_108_c_compstr3050_sel_x_b = i_add_i_i_i_i_i126_i_108_c_compstr3050_q[15:0];

    // i_conv_i_i_i_i_i75_i277_109_c_compstr3070_sel_x(BITSELECT,3595)@230
    assign i_conv_i_i_i_i_i75_i277_109_c_compstr3070_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_108_c_compstr3050_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_109_c_compstr3070_vt_select_15(BITSELECT,7281)@230
    assign i_conv_i_i_i_i_i75_i277_109_c_compstr3070_vt_select_15_b = i_conv_i_i_i_i_i75_i277_109_c_compstr3070_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_109_c_compstr3070_vt_join(BITJOIN,7280)@230
    assign i_conv_i_i_i_i_i75_i277_109_c_compstr3070_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_109_c_compstr3070_vt_select_15_b};

    // leftShiftStage0_uid23036_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x(MUX,23035)@230
    assign leftShiftStage0_uid23036_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23036_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_109_c_compstr3070_vt_join_q or leftShiftStage0Idx1_uid23034_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23036_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23036_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_109_c_compstr3070_vt_join_q;
            1'b1 : leftShiftStage0_uid23036_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23034_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23036_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23041_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x(MUX,23040)@230
    assign leftShiftStage1_uid23041_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23041_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_s or leftShiftStage0_uid23036_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23039_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23041_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23041_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q = leftShiftStage0_uid23036_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23041_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23039_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23041_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23046_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x(MUX,23045)@230
    assign leftShiftStage2_uid23046_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23046_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_s or leftShiftStage1_uid23041_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23044_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23046_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23046_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q = leftShiftStage1_uid23041_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23046_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23044_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23046_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_109_c_compstr3071_vt_select_28(BITSELECT,9070)@230
    assign i_shl_i_i_i_i_i77_i_109_c_compstr3071_vt_select_28_b = leftShiftStage2_uid23046_i_shl_i_i_i_i_i77_i_109_c_compstr0_shift_x_q[28:13];

    // redist500_i_shl_i_i_i_i_i77_i_109_c_compstr3071_vt_select_28_b_1(DELAY,28728)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist500_i_shl_i_i_i_i_i77_i_109_c_compstr3071_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_109_c_compstr3071_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_109_c_compstr3071_vt_join(BITJOIN,9069)@231
    assign i_shl_i_i_i_i_i77_i_109_c_compstr3071_vt_join_q = {redist500_i_shl_i_i_i_i_i77_i_109_c_compstr3071_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma(CHAINMULTADD,28108)@225 + 5
    // out q@231
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ah[0] <= redist989_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_219_tpl_217_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ah[1] <= redist988_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_218_tpl_217_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ch[0] <= redist735_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_219_tpl_217_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ch[1] <= redist734_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_218_tpl_217_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072(ADD,8404)@231
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compstr3067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compstr3069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compstr3068_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_109_c_compstr3071_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_109_c_compstr3071_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_o[33:0];

    // rightShiftStage0_uid21696_dupName_435_i_unnamed_c_compstr0_shift_x(MUX,21695)@231
    assign rightShiftStage0_uid21696_dupName_435_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21696_dupName_435_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_q or rightShiftStage0Idx1_uid21694_dupName_435_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21696_dupName_435_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21696_dupName_435_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_q;
            1'b1 : rightShiftStage0_uid21696_dupName_435_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21694_dupName_435_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21696_dupName_435_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21701_dupName_435_i_unnamed_c_compstr0_shift_x(MUX,21700)@231
    assign rightShiftStage1_uid21701_dupName_435_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21701_dupName_435_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21696_dupName_435_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21699_dupName_435_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21701_dupName_435_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21701_dupName_435_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21696_dupName_435_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21701_dupName_435_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21699_dupName_435_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21701_dupName_435_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21706_dupName_435_i_unnamed_c_compstr0_shift_x(MUX,21705)@231
    assign rightShiftStage2_uid21706_dupName_435_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21706_dupName_435_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21701_dupName_435_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21704_dupName_435_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21706_dupName_435_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21706_dupName_435_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21701_dupName_435_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21706_dupName_435_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21704_dupName_435_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21706_dupName_435_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3073_vt_select_20(BITSELECT,11609)@231
    assign i_unnamed_c_compstr3073_vt_select_20_b = rightShiftStage2_uid21706_dupName_435_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3073_vt_join(BITJOIN,11608)@231
    assign i_unnamed_c_compstr3073_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3073_vt_select_20_b};

    // i_conv_i_i_i_i97_i_109_c_compstr3074_sel_x(BITSELECT,3466)@231
    assign i_conv_i_i_i_i97_i_109_c_compstr3074_sel_x_b = i_unnamed_c_compstr3073_vt_join_q[15:0];

    // redist1270_i_conv_i_i_i_i97_i_109_c_compstr3074_sel_x_b_1(DELAY,29498)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1270_i_conv_i_i_i_i97_i_109_c_compstr3074_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_109_c_compstr3074_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21715_dupName_436_i_unnamed_c_compstr0_shift_x(BITSELECT,21714)@231
    assign rightShiftStage1Idx1Rng8_uid21715_dupName_436_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21714_dupName_436_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21717_dupName_436_i_unnamed_c_compstr0_shift_x(BITJOIN,21716)@231
    assign rightShiftStage1Idx1_uid21717_dupName_436_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21715_dupName_436_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21710_dupName_436_i_unnamed_c_compstr0_shift_x(BITSELECT,21709)@231
    assign rightShiftStage0Idx1Rng4_uid21710_dupName_436_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_q[33:4];

    // rightShiftStage0Idx1_uid21712_dupName_436_i_unnamed_c_compstr0_shift_x(BITJOIN,21711)@231
    assign rightShiftStage0Idx1_uid21712_dupName_436_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21710_dupName_436_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21714_dupName_436_i_unnamed_c_compstr0_shift_x(MUX,21713)@231
    assign rightShiftStage0_uid21714_dupName_436_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21714_dupName_436_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_q or rightShiftStage0Idx1_uid21712_dupName_436_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21714_dupName_436_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21714_dupName_436_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compstr3072_q;
            1'b1 : rightShiftStage0_uid21714_dupName_436_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21712_dupName_436_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21714_dupName_436_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21719_dupName_436_i_unnamed_c_compstr0_shift_x(MUX,21718)@231
    assign rightShiftStage1_uid21719_dupName_436_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21719_dupName_436_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21714_dupName_436_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21717_dupName_436_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21719_dupName_436_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21719_dupName_436_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21714_dupName_436_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21719_dupName_436_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21717_dupName_436_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21719_dupName_436_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3075_vt_select_21(BITSELECT,11612)@231
    assign i_unnamed_c_compstr3075_vt_select_21_b = rightShiftStage1_uid21719_dupName_436_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3075_vt_join(BITJOIN,11611)@231
    assign i_unnamed_c_compstr3075_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3075_vt_select_21_b};

    // i_unnamed_c_compstr3076_sel_x(BITSELECT,6199)@231
    assign i_unnamed_c_compstr3076_sel_x_b = i_unnamed_c_compstr3075_vt_join_q[15:0];

    // i_unnamed_c_compstr3077_BitSelect_for_a(BITSELECT,27787)@231
    assign i_unnamed_c_compstr3077_BitSelect_for_a_b = i_unnamed_c_compstr3076_sel_x_b[0:0];

    // i_unnamed_c_compstr3077_join(BITJOIN,27788)@231
    assign i_unnamed_c_compstr3077_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3077_BitSelect_for_a_b};

    // i_unnamed_c_compstr3077_vt_select_0(BITSELECT,11617)@231
    assign i_unnamed_c_compstr3077_vt_select_0_b = i_unnamed_c_compstr3077_join_q[0:0];

    // redist92_i_unnamed_c_compstr3077_vt_select_0_b_1(DELAY,28320)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist92_i_unnamed_c_compstr3077_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3077_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3077_vt_join(BITJOIN,11616)@232
    assign i_unnamed_c_compstr3077_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist92_i_unnamed_c_compstr3077_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_109_c_compstr3078(ADD,6861)@232
    assign i_add_i_i_i_i_i126_i_109_c_compstr3078_a = {1'b0, i_unnamed_c_compstr3077_vt_join_q};
    assign i_add_i_i_i_i_i126_i_109_c_compstr3078_b = {1'b0, redist1270_i_conv_i_i_i_i97_i_109_c_compstr3074_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_109_c_compstr3078_o = $unsigned(i_add_i_i_i_i_i126_i_109_c_compstr3078_a) + $unsigned(i_add_i_i_i_i_i126_i_109_c_compstr3078_b);
    assign i_add_i_i_i_i_i126_i_109_c_compstr3078_q = i_add_i_i_i_i_i126_i_109_c_compstr3078_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_109_c_compstr3078_sel_x(BITSELECT,2055)@232
    assign bgTrunc_i_add_i_i_i_i_i126_i_109_c_compstr3078_sel_x_b = i_add_i_i_i_i_i126_i_109_c_compstr3078_q[15:0];

    // i_conv_i_i_i_i_i75_i277_110_c_compstr3098_sel_x(BITSELECT,3597)@232
    assign i_conv_i_i_i_i_i75_i277_110_c_compstr3098_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_109_c_compstr3078_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_110_c_compstr3098_vt_select_15(BITSELECT,7289)@232
    assign i_conv_i_i_i_i_i75_i277_110_c_compstr3098_vt_select_15_b = i_conv_i_i_i_i_i75_i277_110_c_compstr3098_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_110_c_compstr3098_vt_join(BITJOIN,7288)@232
    assign i_conv_i_i_i_i_i75_i277_110_c_compstr3098_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_110_c_compstr3098_vt_select_15_b};

    // leftShiftStage0_uid23072_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x(MUX,23071)@232
    assign leftShiftStage0_uid23072_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23072_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_110_c_compstr3098_vt_join_q or leftShiftStage0Idx1_uid23070_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23072_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23072_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_110_c_compstr3098_vt_join_q;
            1'b1 : leftShiftStage0_uid23072_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23070_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23072_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23077_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x(MUX,23076)@232
    assign leftShiftStage1_uid23077_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23077_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_s or leftShiftStage0_uid23072_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23075_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23077_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23077_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q = leftShiftStage0_uid23072_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23077_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23075_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23077_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23082_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x(MUX,23081)@232
    assign leftShiftStage2_uid23082_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23082_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_s or leftShiftStage1_uid23077_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23080_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23082_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23082_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q = leftShiftStage1_uid23077_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23082_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23080_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23082_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_110_c_compstr3099_vt_select_28(BITSELECT,9076)@232
    assign i_shl_i_i_i_i_i77_i_110_c_compstr3099_vt_select_28_b = leftShiftStage2_uid23082_i_shl_i_i_i_i_i77_i_110_c_compstr0_shift_x_q[28:13];

    // redist498_i_shl_i_i_i_i_i77_i_110_c_compstr3099_vt_select_28_b_1(DELAY,28726)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist498_i_shl_i_i_i_i_i77_i_110_c_compstr3099_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_110_c_compstr3099_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_110_c_compstr3099_vt_join(BITJOIN,9075)@233
    assign i_shl_i_i_i_i_i77_i_110_c_compstr3099_vt_join_q = {redist498_i_shl_i_i_i_i_i77_i_110_c_compstr3099_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma(CHAINMULTADD,28110)@227 + 5
    // out q@233
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ah[0] <= redist991_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_221_tpl_219_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ah[1] <= redist990_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_220_tpl_219_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ch[0] <= redist737_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_221_tpl_219_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ch[1] <= redist736_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_220_tpl_219_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100(ADD,8406)@233
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compstr3095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compstr3097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compstr3096_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_110_c_compstr3099_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_110_c_compstr3099_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_o[33:0];

    // rightShiftStage0_uid21758_dupName_439_i_unnamed_c_compstr0_shift_x(MUX,21757)@233
    assign rightShiftStage0_uid21758_dupName_439_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21758_dupName_439_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_q or rightShiftStage0Idx1_uid21756_dupName_439_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21758_dupName_439_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21758_dupName_439_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_q;
            1'b1 : rightShiftStage0_uid21758_dupName_439_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21756_dupName_439_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21758_dupName_439_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21763_dupName_439_i_unnamed_c_compstr0_shift_x(MUX,21762)@233
    assign rightShiftStage1_uid21763_dupName_439_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21763_dupName_439_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21758_dupName_439_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21761_dupName_439_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21763_dupName_439_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21763_dupName_439_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21758_dupName_439_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21763_dupName_439_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21761_dupName_439_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21763_dupName_439_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21768_dupName_439_i_unnamed_c_compstr0_shift_x(MUX,21767)@233
    assign rightShiftStage2_uid21768_dupName_439_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21768_dupName_439_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21763_dupName_439_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21766_dupName_439_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21768_dupName_439_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21768_dupName_439_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21763_dupName_439_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21768_dupName_439_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21766_dupName_439_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21768_dupName_439_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3101_vt_select_20(BITSELECT,11631)@233
    assign i_unnamed_c_compstr3101_vt_select_20_b = rightShiftStage2_uid21768_dupName_439_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3101_vt_join(BITJOIN,11630)@233
    assign i_unnamed_c_compstr3101_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3101_vt_select_20_b};

    // i_conv_i_i_i_i97_i_110_c_compstr3102_sel_x(BITSELECT,3468)@233
    assign i_conv_i_i_i_i97_i_110_c_compstr3102_sel_x_b = i_unnamed_c_compstr3101_vt_join_q[15:0];

    // redist1268_i_conv_i_i_i_i97_i_110_c_compstr3102_sel_x_b_1(DELAY,29496)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1268_i_conv_i_i_i_i97_i_110_c_compstr3102_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_110_c_compstr3102_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21777_dupName_440_i_unnamed_c_compstr0_shift_x(BITSELECT,21776)@233
    assign rightShiftStage1Idx1Rng8_uid21777_dupName_440_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21776_dupName_440_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21779_dupName_440_i_unnamed_c_compstr0_shift_x(BITJOIN,21778)@233
    assign rightShiftStage1Idx1_uid21779_dupName_440_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21777_dupName_440_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21772_dupName_440_i_unnamed_c_compstr0_shift_x(BITSELECT,21771)@233
    assign rightShiftStage0Idx1Rng4_uid21772_dupName_440_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_q[33:4];

    // rightShiftStage0Idx1_uid21774_dupName_440_i_unnamed_c_compstr0_shift_x(BITJOIN,21773)@233
    assign rightShiftStage0Idx1_uid21774_dupName_440_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21772_dupName_440_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21776_dupName_440_i_unnamed_c_compstr0_shift_x(MUX,21775)@233
    assign rightShiftStage0_uid21776_dupName_440_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21776_dupName_440_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_q or rightShiftStage0Idx1_uid21774_dupName_440_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21776_dupName_440_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21776_dupName_440_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compstr3100_q;
            1'b1 : rightShiftStage0_uid21776_dupName_440_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21774_dupName_440_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21776_dupName_440_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21781_dupName_440_i_unnamed_c_compstr0_shift_x(MUX,21780)@233
    assign rightShiftStage1_uid21781_dupName_440_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21781_dupName_440_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21776_dupName_440_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21779_dupName_440_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21781_dupName_440_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21781_dupName_440_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21776_dupName_440_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21781_dupName_440_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21779_dupName_440_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21781_dupName_440_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3103_vt_select_21(BITSELECT,11634)@233
    assign i_unnamed_c_compstr3103_vt_select_21_b = rightShiftStage1_uid21781_dupName_440_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3103_vt_join(BITJOIN,11633)@233
    assign i_unnamed_c_compstr3103_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3103_vt_select_21_b};

    // i_unnamed_c_compstr3104_sel_x(BITSELECT,6201)@233
    assign i_unnamed_c_compstr3104_sel_x_b = i_unnamed_c_compstr3103_vt_join_q[15:0];

    // i_unnamed_c_compstr3105_BitSelect_for_a(BITSELECT,27791)@233
    assign i_unnamed_c_compstr3105_BitSelect_for_a_b = i_unnamed_c_compstr3104_sel_x_b[0:0];

    // i_unnamed_c_compstr3105_join(BITJOIN,27792)@233
    assign i_unnamed_c_compstr3105_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3105_BitSelect_for_a_b};

    // i_unnamed_c_compstr3105_vt_select_0(BITSELECT,11639)@233
    assign i_unnamed_c_compstr3105_vt_select_0_b = i_unnamed_c_compstr3105_join_q[0:0];

    // redist90_i_unnamed_c_compstr3105_vt_select_0_b_1(DELAY,28318)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist90_i_unnamed_c_compstr3105_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3105_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3105_vt_join(BITJOIN,11638)@234
    assign i_unnamed_c_compstr3105_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist90_i_unnamed_c_compstr3105_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_110_c_compstr3106(ADD,6863)@234
    assign i_add_i_i_i_i_i126_i_110_c_compstr3106_a = {1'b0, i_unnamed_c_compstr3105_vt_join_q};
    assign i_add_i_i_i_i_i126_i_110_c_compstr3106_b = {1'b0, redist1268_i_conv_i_i_i_i97_i_110_c_compstr3102_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_110_c_compstr3106_o = $unsigned(i_add_i_i_i_i_i126_i_110_c_compstr3106_a) + $unsigned(i_add_i_i_i_i_i126_i_110_c_compstr3106_b);
    assign i_add_i_i_i_i_i126_i_110_c_compstr3106_q = i_add_i_i_i_i_i126_i_110_c_compstr3106_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_110_c_compstr3106_sel_x(BITSELECT,2057)@234
    assign bgTrunc_i_add_i_i_i_i_i126_i_110_c_compstr3106_sel_x_b = i_add_i_i_i_i_i126_i_110_c_compstr3106_q[15:0];

    // i_conv_i_i_i_i_i75_i277_111_c_compstr3126_sel_x(BITSELECT,3598)@234
    assign i_conv_i_i_i_i_i75_i277_111_c_compstr3126_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_110_c_compstr3106_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_111_c_compstr3126_vt_select_15(BITSELECT,7293)@234
    assign i_conv_i_i_i_i_i75_i277_111_c_compstr3126_vt_select_15_b = i_conv_i_i_i_i_i75_i277_111_c_compstr3126_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_111_c_compstr3126_vt_join(BITJOIN,7292)@234
    assign i_conv_i_i_i_i_i75_i277_111_c_compstr3126_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_111_c_compstr3126_vt_select_15_b};

    // leftShiftStage0_uid23090_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x(MUX,23089)@234
    assign leftShiftStage0_uid23090_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23090_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_111_c_compstr3126_vt_join_q or leftShiftStage0Idx1_uid23088_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23090_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23090_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_111_c_compstr3126_vt_join_q;
            1'b1 : leftShiftStage0_uid23090_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23088_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23090_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23095_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x(MUX,23094)@234
    assign leftShiftStage1_uid23095_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23095_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_s or leftShiftStage0_uid23090_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23093_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23095_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23095_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q = leftShiftStage0_uid23090_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23095_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23093_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23095_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23100_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x(MUX,23099)@234
    assign leftShiftStage2_uid23100_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23100_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_s or leftShiftStage1_uid23095_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23098_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23100_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23100_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q = leftShiftStage1_uid23095_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23100_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23098_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23100_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_111_c_compstr3127_vt_select_28(BITSELECT,9079)@234
    assign i_shl_i_i_i_i_i77_i_111_c_compstr3127_vt_select_28_b = leftShiftStage2_uid23100_i_shl_i_i_i_i_i77_i_111_c_compstr0_shift_x_q[28:13];

    // redist497_i_shl_i_i_i_i_i77_i_111_c_compstr3127_vt_select_28_b_1(DELAY,28725)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist497_i_shl_i_i_i_i_i77_i_111_c_compstr3127_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_111_c_compstr3127_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_111_c_compstr3127_vt_join(BITJOIN,9078)@235
    assign i_shl_i_i_i_i_i77_i_111_c_compstr3127_vt_join_q = {redist497_i_shl_i_i_i_i_i77_i_111_c_compstr3127_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma(CHAINMULTADD,28111)@229 + 5
    // out q@235
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ah[0] <= redist993_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_223_tpl_221_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ah[1] <= redist992_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_222_tpl_221_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ch[0] <= redist739_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_223_tpl_221_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ch[1] <= redist738_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_222_tpl_221_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128(ADD,8407)@235
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compstr3123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compstr3125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compstr3124_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_111_c_compstr3127_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_111_c_compstr3127_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_o[33:0];

    // rightShiftStage0_uid21820_dupName_443_i_unnamed_c_compstr0_shift_x(MUX,21819)@235
    assign rightShiftStage0_uid21820_dupName_443_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21820_dupName_443_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_q or rightShiftStage0Idx1_uid21818_dupName_443_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21820_dupName_443_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21820_dupName_443_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_q;
            1'b1 : rightShiftStage0_uid21820_dupName_443_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21818_dupName_443_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21820_dupName_443_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21825_dupName_443_i_unnamed_c_compstr0_shift_x(MUX,21824)@235
    assign rightShiftStage1_uid21825_dupName_443_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21825_dupName_443_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21820_dupName_443_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21823_dupName_443_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21825_dupName_443_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21825_dupName_443_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21820_dupName_443_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21825_dupName_443_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21823_dupName_443_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21825_dupName_443_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21830_dupName_443_i_unnamed_c_compstr0_shift_x(MUX,21829)@235
    assign rightShiftStage2_uid21830_dupName_443_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21830_dupName_443_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21825_dupName_443_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21828_dupName_443_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21830_dupName_443_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21830_dupName_443_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21825_dupName_443_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21830_dupName_443_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21828_dupName_443_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21830_dupName_443_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3129_vt_select_20(BITSELECT,11653)@235
    assign i_unnamed_c_compstr3129_vt_select_20_b = rightShiftStage2_uid21830_dupName_443_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3129_vt_join(BITJOIN,11652)@235
    assign i_unnamed_c_compstr3129_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3129_vt_select_20_b};

    // i_conv_i_i_i_i97_i_111_c_compstr3130_sel_x(BITSELECT,3469)@235
    assign i_conv_i_i_i_i97_i_111_c_compstr3130_sel_x_b = i_unnamed_c_compstr3129_vt_join_q[15:0];

    // redist1267_i_conv_i_i_i_i97_i_111_c_compstr3130_sel_x_b_1(DELAY,29495)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1267_i_conv_i_i_i_i97_i_111_c_compstr3130_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_111_c_compstr3130_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21839_dupName_444_i_unnamed_c_compstr0_shift_x(BITSELECT,21838)@235
    assign rightShiftStage1Idx1Rng8_uid21839_dupName_444_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21838_dupName_444_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21841_dupName_444_i_unnamed_c_compstr0_shift_x(BITJOIN,21840)@235
    assign rightShiftStage1Idx1_uid21841_dupName_444_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21839_dupName_444_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21834_dupName_444_i_unnamed_c_compstr0_shift_x(BITSELECT,21833)@235
    assign rightShiftStage0Idx1Rng4_uid21834_dupName_444_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_q[33:4];

    // rightShiftStage0Idx1_uid21836_dupName_444_i_unnamed_c_compstr0_shift_x(BITJOIN,21835)@235
    assign rightShiftStage0Idx1_uid21836_dupName_444_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21834_dupName_444_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21838_dupName_444_i_unnamed_c_compstr0_shift_x(MUX,21837)@235
    assign rightShiftStage0_uid21838_dupName_444_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21838_dupName_444_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_q or rightShiftStage0Idx1_uid21836_dupName_444_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21838_dupName_444_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21838_dupName_444_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compstr3128_q;
            1'b1 : rightShiftStage0_uid21838_dupName_444_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21836_dupName_444_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21838_dupName_444_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21843_dupName_444_i_unnamed_c_compstr0_shift_x(MUX,21842)@235
    assign rightShiftStage1_uid21843_dupName_444_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21843_dupName_444_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21838_dupName_444_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21841_dupName_444_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21843_dupName_444_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21843_dupName_444_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21838_dupName_444_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21843_dupName_444_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21841_dupName_444_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21843_dupName_444_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3131_vt_select_21(BITSELECT,11656)@235
    assign i_unnamed_c_compstr3131_vt_select_21_b = rightShiftStage1_uid21843_dupName_444_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3131_vt_join(BITJOIN,11655)@235
    assign i_unnamed_c_compstr3131_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3131_vt_select_21_b};

    // i_unnamed_c_compstr3132_sel_x(BITSELECT,6203)@235
    assign i_unnamed_c_compstr3132_sel_x_b = i_unnamed_c_compstr3131_vt_join_q[15:0];

    // i_unnamed_c_compstr3133_BitSelect_for_a(BITSELECT,27795)@235
    assign i_unnamed_c_compstr3133_BitSelect_for_a_b = i_unnamed_c_compstr3132_sel_x_b[0:0];

    // i_unnamed_c_compstr3133_join(BITJOIN,27796)@235
    assign i_unnamed_c_compstr3133_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3133_BitSelect_for_a_b};

    // i_unnamed_c_compstr3133_vt_select_0(BITSELECT,11661)@235
    assign i_unnamed_c_compstr3133_vt_select_0_b = i_unnamed_c_compstr3133_join_q[0:0];

    // redist88_i_unnamed_c_compstr3133_vt_select_0_b_1(DELAY,28316)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist88_i_unnamed_c_compstr3133_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3133_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3133_vt_join(BITJOIN,11660)@236
    assign i_unnamed_c_compstr3133_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist88_i_unnamed_c_compstr3133_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_111_c_compstr3134(ADD,6864)@236
    assign i_add_i_i_i_i_i126_i_111_c_compstr3134_a = {1'b0, i_unnamed_c_compstr3133_vt_join_q};
    assign i_add_i_i_i_i_i126_i_111_c_compstr3134_b = {1'b0, redist1267_i_conv_i_i_i_i97_i_111_c_compstr3130_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_111_c_compstr3134_o = $unsigned(i_add_i_i_i_i_i126_i_111_c_compstr3134_a) + $unsigned(i_add_i_i_i_i_i126_i_111_c_compstr3134_b);
    assign i_add_i_i_i_i_i126_i_111_c_compstr3134_q = i_add_i_i_i_i_i126_i_111_c_compstr3134_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_111_c_compstr3134_sel_x(BITSELECT,2058)@236
    assign bgTrunc_i_add_i_i_i_i_i126_i_111_c_compstr3134_sel_x_b = i_add_i_i_i_i_i126_i_111_c_compstr3134_q[15:0];

    // i_conv_i_i_i_i_i75_i277_112_c_compstr3154_sel_x(BITSELECT,3599)@236
    assign i_conv_i_i_i_i_i75_i277_112_c_compstr3154_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_111_c_compstr3134_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_112_c_compstr3154_vt_select_15(BITSELECT,7297)@236
    assign i_conv_i_i_i_i_i75_i277_112_c_compstr3154_vt_select_15_b = i_conv_i_i_i_i_i75_i277_112_c_compstr3154_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_112_c_compstr3154_vt_join(BITJOIN,7296)@236
    assign i_conv_i_i_i_i_i75_i277_112_c_compstr3154_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_112_c_compstr3154_vt_select_15_b};

    // leftShiftStage0_uid23108_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x(MUX,23107)@236
    assign leftShiftStage0_uid23108_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23108_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_112_c_compstr3154_vt_join_q or leftShiftStage0Idx1_uid23106_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23108_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23108_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_112_c_compstr3154_vt_join_q;
            1'b1 : leftShiftStage0_uid23108_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23106_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23108_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23113_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x(MUX,23112)@236
    assign leftShiftStage1_uid23113_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23113_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_s or leftShiftStage0_uid23108_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23111_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23113_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23113_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q = leftShiftStage0_uid23108_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23113_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23111_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23113_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23118_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x(MUX,23117)@236
    assign leftShiftStage2_uid23118_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23118_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_s or leftShiftStage1_uid23113_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23116_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23118_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23118_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q = leftShiftStage1_uid23113_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23118_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23116_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23118_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_112_c_compstr3155_vt_select_28(BITSELECT,9082)@236
    assign i_shl_i_i_i_i_i77_i_112_c_compstr3155_vt_select_28_b = leftShiftStage2_uid23118_i_shl_i_i_i_i_i77_i_112_c_compstr0_shift_x_q[28:13];

    // redist496_i_shl_i_i_i_i_i77_i_112_c_compstr3155_vt_select_28_b_1(DELAY,28724)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist496_i_shl_i_i_i_i_i77_i_112_c_compstr3155_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_112_c_compstr3155_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_112_c_compstr3155_vt_join(BITJOIN,9081)@237
    assign i_shl_i_i_i_i_i77_i_112_c_compstr3155_vt_join_q = {redist496_i_shl_i_i_i_i_i77_i_112_c_compstr3155_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma(CHAINMULTADD,28112)@231 + 5
    // out q@237
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ah[0] <= redist995_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_225_tpl_223_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ah[1] <= redist994_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_224_tpl_223_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ch[0] <= redist741_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_225_tpl_223_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ch[1] <= redist740_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_224_tpl_223_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156(ADD,8408)@237
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compstr3151_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compstr3153_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compstr3152_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_112_c_compstr3155_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_112_c_compstr3155_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_o[33:0];

    // rightShiftStage0_uid21882_dupName_447_i_unnamed_c_compstr0_shift_x(MUX,21881)@237
    assign rightShiftStage0_uid21882_dupName_447_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21882_dupName_447_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_q or rightShiftStage0Idx1_uid21880_dupName_447_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21882_dupName_447_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21882_dupName_447_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_q;
            1'b1 : rightShiftStage0_uid21882_dupName_447_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21880_dupName_447_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21882_dupName_447_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21887_dupName_447_i_unnamed_c_compstr0_shift_x(MUX,21886)@237
    assign rightShiftStage1_uid21887_dupName_447_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21887_dupName_447_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21882_dupName_447_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21885_dupName_447_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21887_dupName_447_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21887_dupName_447_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21882_dupName_447_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21887_dupName_447_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21885_dupName_447_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21887_dupName_447_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21892_dupName_447_i_unnamed_c_compstr0_shift_x(MUX,21891)@237
    assign rightShiftStage2_uid21892_dupName_447_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21892_dupName_447_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21887_dupName_447_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21890_dupName_447_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21892_dupName_447_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21892_dupName_447_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21887_dupName_447_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21892_dupName_447_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21890_dupName_447_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21892_dupName_447_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3157_vt_select_20(BITSELECT,11675)@237
    assign i_unnamed_c_compstr3157_vt_select_20_b = rightShiftStage2_uid21892_dupName_447_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3157_vt_join(BITJOIN,11674)@237
    assign i_unnamed_c_compstr3157_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3157_vt_select_20_b};

    // i_conv_i_i_i_i97_i_112_c_compstr3158_sel_x(BITSELECT,3470)@237
    assign i_conv_i_i_i_i97_i_112_c_compstr3158_sel_x_b = i_unnamed_c_compstr3157_vt_join_q[15:0];

    // redist1266_i_conv_i_i_i_i97_i_112_c_compstr3158_sel_x_b_1(DELAY,29494)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1266_i_conv_i_i_i_i97_i_112_c_compstr3158_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_112_c_compstr3158_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21901_dupName_448_i_unnamed_c_compstr0_shift_x(BITSELECT,21900)@237
    assign rightShiftStage1Idx1Rng8_uid21901_dupName_448_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21900_dupName_448_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21903_dupName_448_i_unnamed_c_compstr0_shift_x(BITJOIN,21902)@237
    assign rightShiftStage1Idx1_uid21903_dupName_448_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21901_dupName_448_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21896_dupName_448_i_unnamed_c_compstr0_shift_x(BITSELECT,21895)@237
    assign rightShiftStage0Idx1Rng4_uid21896_dupName_448_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_q[33:4];

    // rightShiftStage0Idx1_uid21898_dupName_448_i_unnamed_c_compstr0_shift_x(BITJOIN,21897)@237
    assign rightShiftStage0Idx1_uid21898_dupName_448_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21896_dupName_448_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21900_dupName_448_i_unnamed_c_compstr0_shift_x(MUX,21899)@237
    assign rightShiftStage0_uid21900_dupName_448_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21900_dupName_448_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_q or rightShiftStage0Idx1_uid21898_dupName_448_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21900_dupName_448_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21900_dupName_448_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compstr3156_q;
            1'b1 : rightShiftStage0_uid21900_dupName_448_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21898_dupName_448_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21900_dupName_448_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21905_dupName_448_i_unnamed_c_compstr0_shift_x(MUX,21904)@237
    assign rightShiftStage1_uid21905_dupName_448_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21905_dupName_448_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21900_dupName_448_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21903_dupName_448_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21905_dupName_448_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21905_dupName_448_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21900_dupName_448_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21905_dupName_448_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21903_dupName_448_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21905_dupName_448_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3159_vt_select_21(BITSELECT,11678)@237
    assign i_unnamed_c_compstr3159_vt_select_21_b = rightShiftStage1_uid21905_dupName_448_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3159_vt_join(BITJOIN,11677)@237
    assign i_unnamed_c_compstr3159_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3159_vt_select_21_b};

    // i_unnamed_c_compstr3160_sel_x(BITSELECT,6205)@237
    assign i_unnamed_c_compstr3160_sel_x_b = i_unnamed_c_compstr3159_vt_join_q[15:0];

    // i_unnamed_c_compstr3161_BitSelect_for_a(BITSELECT,27799)@237
    assign i_unnamed_c_compstr3161_BitSelect_for_a_b = i_unnamed_c_compstr3160_sel_x_b[0:0];

    // i_unnamed_c_compstr3161_join(BITJOIN,27800)@237
    assign i_unnamed_c_compstr3161_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3161_BitSelect_for_a_b};

    // i_unnamed_c_compstr3161_vt_select_0(BITSELECT,11683)@237
    assign i_unnamed_c_compstr3161_vt_select_0_b = i_unnamed_c_compstr3161_join_q[0:0];

    // redist86_i_unnamed_c_compstr3161_vt_select_0_b_1(DELAY,28314)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist86_i_unnamed_c_compstr3161_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3161_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3161_vt_join(BITJOIN,11682)@238
    assign i_unnamed_c_compstr3161_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist86_i_unnamed_c_compstr3161_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_112_c_compstr3162(ADD,6865)@238
    assign i_add_i_i_i_i_i126_i_112_c_compstr3162_a = {1'b0, i_unnamed_c_compstr3161_vt_join_q};
    assign i_add_i_i_i_i_i126_i_112_c_compstr3162_b = {1'b0, redist1266_i_conv_i_i_i_i97_i_112_c_compstr3158_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_112_c_compstr3162_o = $unsigned(i_add_i_i_i_i_i126_i_112_c_compstr3162_a) + $unsigned(i_add_i_i_i_i_i126_i_112_c_compstr3162_b);
    assign i_add_i_i_i_i_i126_i_112_c_compstr3162_q = i_add_i_i_i_i_i126_i_112_c_compstr3162_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_112_c_compstr3162_sel_x(BITSELECT,2059)@238
    assign bgTrunc_i_add_i_i_i_i_i126_i_112_c_compstr3162_sel_x_b = i_add_i_i_i_i_i126_i_112_c_compstr3162_q[15:0];

    // i_conv_i_i_i_i_i75_i277_113_c_compstr3182_sel_x(BITSELECT,3600)@238
    assign i_conv_i_i_i_i_i75_i277_113_c_compstr3182_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_112_c_compstr3162_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_113_c_compstr3182_vt_select_15(BITSELECT,7301)@238
    assign i_conv_i_i_i_i_i75_i277_113_c_compstr3182_vt_select_15_b = i_conv_i_i_i_i_i75_i277_113_c_compstr3182_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_113_c_compstr3182_vt_join(BITJOIN,7300)@238
    assign i_conv_i_i_i_i_i75_i277_113_c_compstr3182_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_113_c_compstr3182_vt_select_15_b};

    // leftShiftStage0_uid23126_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x(MUX,23125)@238
    assign leftShiftStage0_uid23126_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23126_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_113_c_compstr3182_vt_join_q or leftShiftStage0Idx1_uid23124_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23126_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23126_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_113_c_compstr3182_vt_join_q;
            1'b1 : leftShiftStage0_uid23126_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23124_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23126_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23131_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x(MUX,23130)@238
    assign leftShiftStage1_uid23131_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23131_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_s or leftShiftStage0_uid23126_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23129_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23131_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23131_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q = leftShiftStage0_uid23126_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23131_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23129_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23131_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23136_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x(MUX,23135)@238
    assign leftShiftStage2_uid23136_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23136_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_s or leftShiftStage1_uid23131_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23134_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23136_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23136_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q = leftShiftStage1_uid23131_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23136_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23134_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23136_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_113_c_compstr3183_vt_select_28(BITSELECT,9085)@238
    assign i_shl_i_i_i_i_i77_i_113_c_compstr3183_vt_select_28_b = leftShiftStage2_uid23136_i_shl_i_i_i_i_i77_i_113_c_compstr0_shift_x_q[28:13];

    // redist495_i_shl_i_i_i_i_i77_i_113_c_compstr3183_vt_select_28_b_1(DELAY,28723)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist495_i_shl_i_i_i_i_i77_i_113_c_compstr3183_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_113_c_compstr3183_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_113_c_compstr3183_vt_join(BITJOIN,9084)@239
    assign i_shl_i_i_i_i_i77_i_113_c_compstr3183_vt_join_q = {redist495_i_shl_i_i_i_i_i77_i_113_c_compstr3183_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma(CHAINMULTADD,28113)@233 + 5
    // out q@239
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ah[0] <= redist997_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_227_tpl_225_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ah[1] <= redist996_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_226_tpl_225_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ch[0] <= redist743_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_227_tpl_225_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ch[1] <= redist742_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_226_tpl_225_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184(ADD,8409)@239
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compstr3179_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compstr3181_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compstr3180_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_113_c_compstr3183_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_113_c_compstr3183_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_o[33:0];

    // rightShiftStage0_uid21944_dupName_451_i_unnamed_c_compstr0_shift_x(MUX,21943)@239
    assign rightShiftStage0_uid21944_dupName_451_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21944_dupName_451_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_q or rightShiftStage0Idx1_uid21942_dupName_451_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21944_dupName_451_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21944_dupName_451_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_q;
            1'b1 : rightShiftStage0_uid21944_dupName_451_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21942_dupName_451_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21944_dupName_451_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21949_dupName_451_i_unnamed_c_compstr0_shift_x(MUX,21948)@239
    assign rightShiftStage1_uid21949_dupName_451_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21949_dupName_451_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21944_dupName_451_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21947_dupName_451_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21949_dupName_451_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21949_dupName_451_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21944_dupName_451_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21949_dupName_451_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21947_dupName_451_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21949_dupName_451_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21954_dupName_451_i_unnamed_c_compstr0_shift_x(MUX,21953)@239
    assign rightShiftStage2_uid21954_dupName_451_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21954_dupName_451_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid21949_dupName_451_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid21952_dupName_451_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21954_dupName_451_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid21954_dupName_451_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid21949_dupName_451_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid21954_dupName_451_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid21952_dupName_451_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid21954_dupName_451_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3185_vt_select_20(BITSELECT,11700)@239
    assign i_unnamed_c_compstr3185_vt_select_20_b = rightShiftStage2_uid21954_dupName_451_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3185_vt_join(BITJOIN,11699)@239
    assign i_unnamed_c_compstr3185_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3185_vt_select_20_b};

    // i_conv_i_i_i_i97_i_113_c_compstr3186_sel_x(BITSELECT,3471)@239
    assign i_conv_i_i_i_i97_i_113_c_compstr3186_sel_x_b = i_unnamed_c_compstr3185_vt_join_q[15:0];

    // redist1265_i_conv_i_i_i_i97_i_113_c_compstr3186_sel_x_b_1(DELAY,29493)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1265_i_conv_i_i_i_i97_i_113_c_compstr3186_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_113_c_compstr3186_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21963_dupName_452_i_unnamed_c_compstr0_shift_x(BITSELECT,21962)@239
    assign rightShiftStage1Idx1Rng8_uid21963_dupName_452_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid21962_dupName_452_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21965_dupName_452_i_unnamed_c_compstr0_shift_x(BITJOIN,21964)@239
    assign rightShiftStage1Idx1_uid21965_dupName_452_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid21963_dupName_452_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21958_dupName_452_i_unnamed_c_compstr0_shift_x(BITSELECT,21957)@239
    assign rightShiftStage0Idx1Rng4_uid21958_dupName_452_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_q[33:4];

    // rightShiftStage0Idx1_uid21960_dupName_452_i_unnamed_c_compstr0_shift_x(BITJOIN,21959)@239
    assign rightShiftStage0Idx1_uid21960_dupName_452_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid21958_dupName_452_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid21962_dupName_452_i_unnamed_c_compstr0_shift_x(MUX,21961)@239
    assign rightShiftStage0_uid21962_dupName_452_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21962_dupName_452_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_q or rightShiftStage0Idx1_uid21960_dupName_452_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21962_dupName_452_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid21962_dupName_452_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compstr3184_q;
            1'b1 : rightShiftStage0_uid21962_dupName_452_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid21960_dupName_452_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid21962_dupName_452_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21967_dupName_452_i_unnamed_c_compstr0_shift_x(MUX,21966)@239
    assign rightShiftStage1_uid21967_dupName_452_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21967_dupName_452_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid21962_dupName_452_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid21965_dupName_452_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21967_dupName_452_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid21967_dupName_452_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid21962_dupName_452_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid21967_dupName_452_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid21965_dupName_452_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid21967_dupName_452_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3187_vt_select_21(BITSELECT,11703)@239
    assign i_unnamed_c_compstr3187_vt_select_21_b = rightShiftStage1_uid21967_dupName_452_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3187_vt_join(BITJOIN,11702)@239
    assign i_unnamed_c_compstr3187_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3187_vt_select_21_b};

    // i_unnamed_c_compstr3188_sel_x(BITSELECT,6207)@239
    assign i_unnamed_c_compstr3188_sel_x_b = i_unnamed_c_compstr3187_vt_join_q[15:0];

    // i_unnamed_c_compstr3189_BitSelect_for_a(BITSELECT,27803)@239
    assign i_unnamed_c_compstr3189_BitSelect_for_a_b = i_unnamed_c_compstr3188_sel_x_b[0:0];

    // i_unnamed_c_compstr3189_join(BITJOIN,27804)@239
    assign i_unnamed_c_compstr3189_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3189_BitSelect_for_a_b};

    // i_unnamed_c_compstr3189_vt_select_0(BITSELECT,11708)@239
    assign i_unnamed_c_compstr3189_vt_select_0_b = i_unnamed_c_compstr3189_join_q[0:0];

    // redist84_i_unnamed_c_compstr3189_vt_select_0_b_1(DELAY,28312)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist84_i_unnamed_c_compstr3189_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3189_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3189_vt_join(BITJOIN,11707)@240
    assign i_unnamed_c_compstr3189_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist84_i_unnamed_c_compstr3189_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_113_c_compstr3190(ADD,6866)@240
    assign i_add_i_i_i_i_i126_i_113_c_compstr3190_a = {1'b0, i_unnamed_c_compstr3189_vt_join_q};
    assign i_add_i_i_i_i_i126_i_113_c_compstr3190_b = {1'b0, redist1265_i_conv_i_i_i_i97_i_113_c_compstr3186_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_113_c_compstr3190_o = $unsigned(i_add_i_i_i_i_i126_i_113_c_compstr3190_a) + $unsigned(i_add_i_i_i_i_i126_i_113_c_compstr3190_b);
    assign i_add_i_i_i_i_i126_i_113_c_compstr3190_q = i_add_i_i_i_i_i126_i_113_c_compstr3190_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_113_c_compstr3190_sel_x(BITSELECT,2060)@240
    assign bgTrunc_i_add_i_i_i_i_i126_i_113_c_compstr3190_sel_x_b = i_add_i_i_i_i_i126_i_113_c_compstr3190_q[15:0];

    // i_conv_i_i_i_i_i75_i277_114_c_compstr3210_sel_x(BITSELECT,3601)@240
    assign i_conv_i_i_i_i_i75_i277_114_c_compstr3210_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_113_c_compstr3190_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_114_c_compstr3210_vt_select_15(BITSELECT,7305)@240
    assign i_conv_i_i_i_i_i75_i277_114_c_compstr3210_vt_select_15_b = i_conv_i_i_i_i_i75_i277_114_c_compstr3210_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_114_c_compstr3210_vt_join(BITJOIN,7304)@240
    assign i_conv_i_i_i_i_i75_i277_114_c_compstr3210_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_114_c_compstr3210_vt_select_15_b};

    // leftShiftStage0_uid23144_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x(MUX,23143)@240
    assign leftShiftStage0_uid23144_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23144_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_114_c_compstr3210_vt_join_q or leftShiftStage0Idx1_uid23142_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23144_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23144_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_114_c_compstr3210_vt_join_q;
            1'b1 : leftShiftStage0_uid23144_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23142_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23144_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23149_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x(MUX,23148)@240
    assign leftShiftStage1_uid23149_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23149_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_s or leftShiftStage0_uid23144_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23147_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23149_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23149_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q = leftShiftStage0_uid23144_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23149_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23147_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23149_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23154_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x(MUX,23153)@240
    assign leftShiftStage2_uid23154_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23154_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_s or leftShiftStage1_uid23149_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23152_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23154_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23154_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q = leftShiftStage1_uid23149_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23154_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23152_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23154_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_114_c_compstr3211_vt_select_28(BITSELECT,9088)@240
    assign i_shl_i_i_i_i_i77_i_114_c_compstr3211_vt_select_28_b = leftShiftStage2_uid23154_i_shl_i_i_i_i_i77_i_114_c_compstr0_shift_x_q[28:13];

    // redist494_i_shl_i_i_i_i_i77_i_114_c_compstr3211_vt_select_28_b_1(DELAY,28722)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist494_i_shl_i_i_i_i_i77_i_114_c_compstr3211_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_114_c_compstr3211_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_114_c_compstr3211_vt_join(BITJOIN,9087)@241
    assign i_shl_i_i_i_i_i77_i_114_c_compstr3211_vt_join_q = {redist494_i_shl_i_i_i_i_i77_i_114_c_compstr3211_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma(CHAINMULTADD,28114)@235 + 5
    // out q@241
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ah[0] <= redist999_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_229_tpl_227_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ah[1] <= redist998_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_228_tpl_227_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ch[0] <= redist745_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_229_tpl_227_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ch[1] <= redist744_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_228_tpl_227_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212(ADD,8410)@241
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compstr3207_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compstr3209_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compstr3208_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_114_c_compstr3211_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_114_c_compstr3211_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_o[33:0];

    // rightShiftStage0_uid22006_dupName_455_i_unnamed_c_compstr0_shift_x(MUX,22005)@241
    assign rightShiftStage0_uid22006_dupName_455_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22006_dupName_455_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_q or rightShiftStage0Idx1_uid22004_dupName_455_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22006_dupName_455_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22006_dupName_455_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_q;
            1'b1 : rightShiftStage0_uid22006_dupName_455_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22004_dupName_455_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22006_dupName_455_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22011_dupName_455_i_unnamed_c_compstr0_shift_x(MUX,22010)@241
    assign rightShiftStage1_uid22011_dupName_455_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22011_dupName_455_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22006_dupName_455_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22009_dupName_455_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22011_dupName_455_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22011_dupName_455_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22006_dupName_455_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22011_dupName_455_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22009_dupName_455_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22011_dupName_455_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22016_dupName_455_i_unnamed_c_compstr0_shift_x(MUX,22015)@241
    assign rightShiftStage2_uid22016_dupName_455_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22016_dupName_455_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22011_dupName_455_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22014_dupName_455_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22016_dupName_455_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22016_dupName_455_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22011_dupName_455_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22016_dupName_455_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22014_dupName_455_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22016_dupName_455_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3213_vt_select_20(BITSELECT,11727)@241
    assign i_unnamed_c_compstr3213_vt_select_20_b = rightShiftStage2_uid22016_dupName_455_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3213_vt_join(BITJOIN,11726)@241
    assign i_unnamed_c_compstr3213_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3213_vt_select_20_b};

    // i_conv_i_i_i_i97_i_114_c_compstr3214_sel_x(BITSELECT,3472)@241
    assign i_conv_i_i_i_i97_i_114_c_compstr3214_sel_x_b = i_unnamed_c_compstr3213_vt_join_q[15:0];

    // redist1264_i_conv_i_i_i_i97_i_114_c_compstr3214_sel_x_b_1(DELAY,29492)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1264_i_conv_i_i_i_i97_i_114_c_compstr3214_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_114_c_compstr3214_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22025_dupName_456_i_unnamed_c_compstr0_shift_x(BITSELECT,22024)@241
    assign rightShiftStage1Idx1Rng8_uid22025_dupName_456_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22024_dupName_456_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22027_dupName_456_i_unnamed_c_compstr0_shift_x(BITJOIN,22026)@241
    assign rightShiftStage1Idx1_uid22027_dupName_456_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22025_dupName_456_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22020_dupName_456_i_unnamed_c_compstr0_shift_x(BITSELECT,22019)@241
    assign rightShiftStage0Idx1Rng4_uid22020_dupName_456_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_q[33:4];

    // rightShiftStage0Idx1_uid22022_dupName_456_i_unnamed_c_compstr0_shift_x(BITJOIN,22021)@241
    assign rightShiftStage0Idx1_uid22022_dupName_456_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22020_dupName_456_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22024_dupName_456_i_unnamed_c_compstr0_shift_x(MUX,22023)@241
    assign rightShiftStage0_uid22024_dupName_456_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22024_dupName_456_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_q or rightShiftStage0Idx1_uid22022_dupName_456_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22024_dupName_456_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22024_dupName_456_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compstr3212_q;
            1'b1 : rightShiftStage0_uid22024_dupName_456_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22022_dupName_456_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22024_dupName_456_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22029_dupName_456_i_unnamed_c_compstr0_shift_x(MUX,22028)@241
    assign rightShiftStage1_uid22029_dupName_456_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22029_dupName_456_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22024_dupName_456_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22027_dupName_456_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22029_dupName_456_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22029_dupName_456_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22024_dupName_456_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22029_dupName_456_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22027_dupName_456_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22029_dupName_456_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3215_vt_select_21(BITSELECT,11730)@241
    assign i_unnamed_c_compstr3215_vt_select_21_b = rightShiftStage1_uid22029_dupName_456_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3215_vt_join(BITJOIN,11729)@241
    assign i_unnamed_c_compstr3215_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3215_vt_select_21_b};

    // i_unnamed_c_compstr3216_sel_x(BITSELECT,6210)@241
    assign i_unnamed_c_compstr3216_sel_x_b = i_unnamed_c_compstr3215_vt_join_q[15:0];

    // i_unnamed_c_compstr3217_BitSelect_for_a(BITSELECT,27809)@241
    assign i_unnamed_c_compstr3217_BitSelect_for_a_b = i_unnamed_c_compstr3216_sel_x_b[0:0];

    // i_unnamed_c_compstr3217_join(BITJOIN,27810)@241
    assign i_unnamed_c_compstr3217_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3217_BitSelect_for_a_b};

    // i_unnamed_c_compstr3217_vt_select_0(BITSELECT,11735)@241
    assign i_unnamed_c_compstr3217_vt_select_0_b = i_unnamed_c_compstr3217_join_q[0:0];

    // redist82_i_unnamed_c_compstr3217_vt_select_0_b_1(DELAY,28310)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist82_i_unnamed_c_compstr3217_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3217_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3217_vt_join(BITJOIN,11734)@242
    assign i_unnamed_c_compstr3217_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist82_i_unnamed_c_compstr3217_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_114_c_compstr3218(ADD,6867)@242
    assign i_add_i_i_i_i_i126_i_114_c_compstr3218_a = {1'b0, i_unnamed_c_compstr3217_vt_join_q};
    assign i_add_i_i_i_i_i126_i_114_c_compstr3218_b = {1'b0, redist1264_i_conv_i_i_i_i97_i_114_c_compstr3214_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_114_c_compstr3218_o = $unsigned(i_add_i_i_i_i_i126_i_114_c_compstr3218_a) + $unsigned(i_add_i_i_i_i_i126_i_114_c_compstr3218_b);
    assign i_add_i_i_i_i_i126_i_114_c_compstr3218_q = i_add_i_i_i_i_i126_i_114_c_compstr3218_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_114_c_compstr3218_sel_x(BITSELECT,2061)@242
    assign bgTrunc_i_add_i_i_i_i_i126_i_114_c_compstr3218_sel_x_b = i_add_i_i_i_i_i126_i_114_c_compstr3218_q[15:0];

    // i_conv_i_i_i_i_i75_i277_115_c_compstr3238_sel_x(BITSELECT,3602)@242
    assign i_conv_i_i_i_i_i75_i277_115_c_compstr3238_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_114_c_compstr3218_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_115_c_compstr3238_vt_select_15(BITSELECT,7309)@242
    assign i_conv_i_i_i_i_i75_i277_115_c_compstr3238_vt_select_15_b = i_conv_i_i_i_i_i75_i277_115_c_compstr3238_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_115_c_compstr3238_vt_join(BITJOIN,7308)@242
    assign i_conv_i_i_i_i_i75_i277_115_c_compstr3238_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_115_c_compstr3238_vt_select_15_b};

    // leftShiftStage0_uid23162_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x(MUX,23161)@242
    assign leftShiftStage0_uid23162_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23162_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_115_c_compstr3238_vt_join_q or leftShiftStage0Idx1_uid23160_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23162_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23162_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_115_c_compstr3238_vt_join_q;
            1'b1 : leftShiftStage0_uid23162_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23160_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23162_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23167_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x(MUX,23166)@242
    assign leftShiftStage1_uid23167_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23167_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_s or leftShiftStage0_uid23162_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23165_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23167_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23167_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q = leftShiftStage0_uid23162_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23167_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23165_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23167_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23172_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x(MUX,23171)@242
    assign leftShiftStage2_uid23172_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23172_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_s or leftShiftStage1_uid23167_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23170_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23172_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23172_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q = leftShiftStage1_uid23167_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23172_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23170_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23172_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_115_c_compstr3239_vt_select_28(BITSELECT,9091)@242
    assign i_shl_i_i_i_i_i77_i_115_c_compstr3239_vt_select_28_b = leftShiftStage2_uid23172_i_shl_i_i_i_i_i77_i_115_c_compstr0_shift_x_q[28:13];

    // redist493_i_shl_i_i_i_i_i77_i_115_c_compstr3239_vt_select_28_b_1(DELAY,28721)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist493_i_shl_i_i_i_i_i77_i_115_c_compstr3239_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_115_c_compstr3239_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_115_c_compstr3239_vt_join(BITJOIN,9090)@243
    assign i_shl_i_i_i_i_i77_i_115_c_compstr3239_vt_join_q = {redist493_i_shl_i_i_i_i_i77_i_115_c_compstr3239_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma(CHAINMULTADD,28115)@237 + 5
    // out q@243
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ah[0] <= redist1001_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_231_tpl_229_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ah[1] <= redist1000_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_230_tpl_229_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ch[0] <= redist747_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_231_tpl_229_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ch[1] <= redist746_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_230_tpl_229_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240(ADD,8411)@243
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compstr3235_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compstr3237_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compstr3236_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_115_c_compstr3239_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_115_c_compstr3239_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_o[33:0];

    // rightShiftStage0_uid22068_dupName_459_i_unnamed_c_compstr0_shift_x(MUX,22067)@243
    assign rightShiftStage0_uid22068_dupName_459_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22068_dupName_459_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_q or rightShiftStage0Idx1_uid22066_dupName_459_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22068_dupName_459_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22068_dupName_459_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_q;
            1'b1 : rightShiftStage0_uid22068_dupName_459_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22066_dupName_459_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22068_dupName_459_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22073_dupName_459_i_unnamed_c_compstr0_shift_x(MUX,22072)@243
    assign rightShiftStage1_uid22073_dupName_459_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22073_dupName_459_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22068_dupName_459_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22071_dupName_459_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22073_dupName_459_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22073_dupName_459_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22068_dupName_459_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22073_dupName_459_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22071_dupName_459_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22073_dupName_459_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22078_dupName_459_i_unnamed_c_compstr0_shift_x(MUX,22077)@243
    assign rightShiftStage2_uid22078_dupName_459_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22078_dupName_459_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22073_dupName_459_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22076_dupName_459_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22078_dupName_459_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22078_dupName_459_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22073_dupName_459_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22078_dupName_459_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22076_dupName_459_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22078_dupName_459_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3241_vt_select_20(BITSELECT,11752)@243
    assign i_unnamed_c_compstr3241_vt_select_20_b = rightShiftStage2_uid22078_dupName_459_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3241_vt_join(BITJOIN,11751)@243
    assign i_unnamed_c_compstr3241_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3241_vt_select_20_b};

    // i_conv_i_i_i_i97_i_115_c_compstr3242_sel_x(BITSELECT,3473)@243
    assign i_conv_i_i_i_i97_i_115_c_compstr3242_sel_x_b = i_unnamed_c_compstr3241_vt_join_q[15:0];

    // redist1263_i_conv_i_i_i_i97_i_115_c_compstr3242_sel_x_b_1(DELAY,29491)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1263_i_conv_i_i_i_i97_i_115_c_compstr3242_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_115_c_compstr3242_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22087_dupName_460_i_unnamed_c_compstr0_shift_x(BITSELECT,22086)@243
    assign rightShiftStage1Idx1Rng8_uid22087_dupName_460_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22086_dupName_460_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22089_dupName_460_i_unnamed_c_compstr0_shift_x(BITJOIN,22088)@243
    assign rightShiftStage1Idx1_uid22089_dupName_460_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22087_dupName_460_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22082_dupName_460_i_unnamed_c_compstr0_shift_x(BITSELECT,22081)@243
    assign rightShiftStage0Idx1Rng4_uid22082_dupName_460_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_q[33:4];

    // rightShiftStage0Idx1_uid22084_dupName_460_i_unnamed_c_compstr0_shift_x(BITJOIN,22083)@243
    assign rightShiftStage0Idx1_uid22084_dupName_460_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22082_dupName_460_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22086_dupName_460_i_unnamed_c_compstr0_shift_x(MUX,22085)@243
    assign rightShiftStage0_uid22086_dupName_460_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22086_dupName_460_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_q or rightShiftStage0Idx1_uid22084_dupName_460_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22086_dupName_460_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22086_dupName_460_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compstr3240_q;
            1'b1 : rightShiftStage0_uid22086_dupName_460_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22084_dupName_460_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22086_dupName_460_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22091_dupName_460_i_unnamed_c_compstr0_shift_x(MUX,22090)@243
    assign rightShiftStage1_uid22091_dupName_460_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22091_dupName_460_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22086_dupName_460_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22089_dupName_460_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22091_dupName_460_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22091_dupName_460_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22086_dupName_460_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22091_dupName_460_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22089_dupName_460_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22091_dupName_460_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3243_vt_select_21(BITSELECT,11755)@243
    assign i_unnamed_c_compstr3243_vt_select_21_b = rightShiftStage1_uid22091_dupName_460_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3243_vt_join(BITJOIN,11754)@243
    assign i_unnamed_c_compstr3243_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3243_vt_select_21_b};

    // i_unnamed_c_compstr3244_sel_x(BITSELECT,6212)@243
    assign i_unnamed_c_compstr3244_sel_x_b = i_unnamed_c_compstr3243_vt_join_q[15:0];

    // i_unnamed_c_compstr3245_BitSelect_for_a(BITSELECT,27813)@243
    assign i_unnamed_c_compstr3245_BitSelect_for_a_b = i_unnamed_c_compstr3244_sel_x_b[0:0];

    // i_unnamed_c_compstr3245_join(BITJOIN,27814)@243
    assign i_unnamed_c_compstr3245_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3245_BitSelect_for_a_b};

    // i_unnamed_c_compstr3245_vt_select_0(BITSELECT,11760)@243
    assign i_unnamed_c_compstr3245_vt_select_0_b = i_unnamed_c_compstr3245_join_q[0:0];

    // redist79_i_unnamed_c_compstr3245_vt_select_0_b_1(DELAY,28307)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist79_i_unnamed_c_compstr3245_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3245_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3245_vt_join(BITJOIN,11759)@244
    assign i_unnamed_c_compstr3245_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist79_i_unnamed_c_compstr3245_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_115_c_compstr3246(ADD,6868)@244
    assign i_add_i_i_i_i_i126_i_115_c_compstr3246_a = {1'b0, i_unnamed_c_compstr3245_vt_join_q};
    assign i_add_i_i_i_i_i126_i_115_c_compstr3246_b = {1'b0, redist1263_i_conv_i_i_i_i97_i_115_c_compstr3242_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_115_c_compstr3246_o = $unsigned(i_add_i_i_i_i_i126_i_115_c_compstr3246_a) + $unsigned(i_add_i_i_i_i_i126_i_115_c_compstr3246_b);
    assign i_add_i_i_i_i_i126_i_115_c_compstr3246_q = i_add_i_i_i_i_i126_i_115_c_compstr3246_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_115_c_compstr3246_sel_x(BITSELECT,2062)@244
    assign bgTrunc_i_add_i_i_i_i_i126_i_115_c_compstr3246_sel_x_b = i_add_i_i_i_i_i126_i_115_c_compstr3246_q[15:0];

    // i_conv_i_i_i_i_i75_i277_116_c_compstr3266_sel_x(BITSELECT,3603)@244
    assign i_conv_i_i_i_i_i75_i277_116_c_compstr3266_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_115_c_compstr3246_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_116_c_compstr3266_vt_select_15(BITSELECT,7313)@244
    assign i_conv_i_i_i_i_i75_i277_116_c_compstr3266_vt_select_15_b = i_conv_i_i_i_i_i75_i277_116_c_compstr3266_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_116_c_compstr3266_vt_join(BITJOIN,7312)@244
    assign i_conv_i_i_i_i_i75_i277_116_c_compstr3266_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_116_c_compstr3266_vt_select_15_b};

    // leftShiftStage0_uid23180_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x(MUX,23179)@244
    assign leftShiftStage0_uid23180_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23180_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_116_c_compstr3266_vt_join_q or leftShiftStage0Idx1_uid23178_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23180_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23180_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_116_c_compstr3266_vt_join_q;
            1'b1 : leftShiftStage0_uid23180_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23178_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23180_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23185_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x(MUX,23184)@244
    assign leftShiftStage1_uid23185_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23185_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_s or leftShiftStage0_uid23180_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23183_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23185_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23185_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q = leftShiftStage0_uid23180_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23185_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23183_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23185_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23190_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x(MUX,23189)@244
    assign leftShiftStage2_uid23190_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23190_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_s or leftShiftStage1_uid23185_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23188_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23190_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23190_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q = leftShiftStage1_uid23185_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23190_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23188_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23190_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_116_c_compstr3267_vt_select_28(BITSELECT,9094)@244
    assign i_shl_i_i_i_i_i77_i_116_c_compstr3267_vt_select_28_b = leftShiftStage2_uid23190_i_shl_i_i_i_i_i77_i_116_c_compstr0_shift_x_q[28:13];

    // redist492_i_shl_i_i_i_i_i77_i_116_c_compstr3267_vt_select_28_b_1(DELAY,28720)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist492_i_shl_i_i_i_i_i77_i_116_c_compstr3267_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_116_c_compstr3267_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_116_c_compstr3267_vt_join(BITJOIN,9093)@245
    assign i_shl_i_i_i_i_i77_i_116_c_compstr3267_vt_join_q = {redist492_i_shl_i_i_i_i_i77_i_116_c_compstr3267_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma(CHAINMULTADD,28116)@239 + 5
    // out q@245
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ah[0] <= redist1003_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_233_tpl_231_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ah[1] <= redist1002_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_232_tpl_231_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ch[0] <= redist749_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_233_tpl_231_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ch[1] <= redist748_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_232_tpl_231_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268(ADD,8412)@245
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compstr3263_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compstr3265_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compstr3264_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_116_c_compstr3267_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_116_c_compstr3267_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_o[33:0];

    // rightShiftStage0_uid22130_dupName_463_i_unnamed_c_compstr0_shift_x(MUX,22129)@245
    assign rightShiftStage0_uid22130_dupName_463_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22130_dupName_463_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_q or rightShiftStage0Idx1_uid22128_dupName_463_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22130_dupName_463_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22130_dupName_463_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_q;
            1'b1 : rightShiftStage0_uid22130_dupName_463_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22128_dupName_463_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22130_dupName_463_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22135_dupName_463_i_unnamed_c_compstr0_shift_x(MUX,22134)@245
    assign rightShiftStage1_uid22135_dupName_463_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22135_dupName_463_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22130_dupName_463_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22133_dupName_463_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22135_dupName_463_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22135_dupName_463_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22130_dupName_463_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22135_dupName_463_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22133_dupName_463_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22135_dupName_463_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22140_dupName_463_i_unnamed_c_compstr0_shift_x(MUX,22139)@245
    assign rightShiftStage2_uid22140_dupName_463_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22140_dupName_463_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22135_dupName_463_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22138_dupName_463_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22140_dupName_463_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22140_dupName_463_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22135_dupName_463_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22140_dupName_463_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22138_dupName_463_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22140_dupName_463_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3269_vt_select_20(BITSELECT,11774)@245
    assign i_unnamed_c_compstr3269_vt_select_20_b = rightShiftStage2_uid22140_dupName_463_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3269_vt_join(BITJOIN,11773)@245
    assign i_unnamed_c_compstr3269_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3269_vt_select_20_b};

    // i_conv_i_i_i_i97_i_116_c_compstr3270_sel_x(BITSELECT,3474)@245
    assign i_conv_i_i_i_i97_i_116_c_compstr3270_sel_x_b = i_unnamed_c_compstr3269_vt_join_q[15:0];

    // redist1262_i_conv_i_i_i_i97_i_116_c_compstr3270_sel_x_b_1(DELAY,29490)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1262_i_conv_i_i_i_i97_i_116_c_compstr3270_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_116_c_compstr3270_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22149_dupName_464_i_unnamed_c_compstr0_shift_x(BITSELECT,22148)@245
    assign rightShiftStage1Idx1Rng8_uid22149_dupName_464_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22148_dupName_464_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22151_dupName_464_i_unnamed_c_compstr0_shift_x(BITJOIN,22150)@245
    assign rightShiftStage1Idx1_uid22151_dupName_464_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22149_dupName_464_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22144_dupName_464_i_unnamed_c_compstr0_shift_x(BITSELECT,22143)@245
    assign rightShiftStage0Idx1Rng4_uid22144_dupName_464_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_q[33:4];

    // rightShiftStage0Idx1_uid22146_dupName_464_i_unnamed_c_compstr0_shift_x(BITJOIN,22145)@245
    assign rightShiftStage0Idx1_uid22146_dupName_464_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22144_dupName_464_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22148_dupName_464_i_unnamed_c_compstr0_shift_x(MUX,22147)@245
    assign rightShiftStage0_uid22148_dupName_464_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22148_dupName_464_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_q or rightShiftStage0Idx1_uid22146_dupName_464_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22148_dupName_464_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22148_dupName_464_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compstr3268_q;
            1'b1 : rightShiftStage0_uid22148_dupName_464_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22146_dupName_464_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22148_dupName_464_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22153_dupName_464_i_unnamed_c_compstr0_shift_x(MUX,22152)@245
    assign rightShiftStage1_uid22153_dupName_464_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22153_dupName_464_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22148_dupName_464_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22151_dupName_464_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22153_dupName_464_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22153_dupName_464_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22148_dupName_464_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22153_dupName_464_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22151_dupName_464_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22153_dupName_464_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3271_vt_select_21(BITSELECT,11777)@245
    assign i_unnamed_c_compstr3271_vt_select_21_b = rightShiftStage1_uid22153_dupName_464_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3271_vt_join(BITJOIN,11776)@245
    assign i_unnamed_c_compstr3271_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3271_vt_select_21_b};

    // i_unnamed_c_compstr3272_sel_x(BITSELECT,6214)@245
    assign i_unnamed_c_compstr3272_sel_x_b = i_unnamed_c_compstr3271_vt_join_q[15:0];

    // i_unnamed_c_compstr3273_BitSelect_for_a(BITSELECT,27817)@245
    assign i_unnamed_c_compstr3273_BitSelect_for_a_b = i_unnamed_c_compstr3272_sel_x_b[0:0];

    // i_unnamed_c_compstr3273_join(BITJOIN,27818)@245
    assign i_unnamed_c_compstr3273_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3273_BitSelect_for_a_b};

    // i_unnamed_c_compstr3273_vt_select_0(BITSELECT,11782)@245
    assign i_unnamed_c_compstr3273_vt_select_0_b = i_unnamed_c_compstr3273_join_q[0:0];

    // redist77_i_unnamed_c_compstr3273_vt_select_0_b_1(DELAY,28305)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist77_i_unnamed_c_compstr3273_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3273_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3273_vt_join(BITJOIN,11781)@246
    assign i_unnamed_c_compstr3273_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist77_i_unnamed_c_compstr3273_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_116_c_compstr3274(ADD,6869)@246
    assign i_add_i_i_i_i_i126_i_116_c_compstr3274_a = {1'b0, i_unnamed_c_compstr3273_vt_join_q};
    assign i_add_i_i_i_i_i126_i_116_c_compstr3274_b = {1'b0, redist1262_i_conv_i_i_i_i97_i_116_c_compstr3270_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_116_c_compstr3274_o = $unsigned(i_add_i_i_i_i_i126_i_116_c_compstr3274_a) + $unsigned(i_add_i_i_i_i_i126_i_116_c_compstr3274_b);
    assign i_add_i_i_i_i_i126_i_116_c_compstr3274_q = i_add_i_i_i_i_i126_i_116_c_compstr3274_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_116_c_compstr3274_sel_x(BITSELECT,2063)@246
    assign bgTrunc_i_add_i_i_i_i_i126_i_116_c_compstr3274_sel_x_b = i_add_i_i_i_i_i126_i_116_c_compstr3274_q[15:0];

    // i_conv_i_i_i_i_i75_i277_117_c_compstr3294_sel_x(BITSELECT,3604)@246
    assign i_conv_i_i_i_i_i75_i277_117_c_compstr3294_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_116_c_compstr3274_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_117_c_compstr3294_vt_select_15(BITSELECT,7317)@246
    assign i_conv_i_i_i_i_i75_i277_117_c_compstr3294_vt_select_15_b = i_conv_i_i_i_i_i75_i277_117_c_compstr3294_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_117_c_compstr3294_vt_join(BITJOIN,7316)@246
    assign i_conv_i_i_i_i_i75_i277_117_c_compstr3294_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_117_c_compstr3294_vt_select_15_b};

    // leftShiftStage0_uid23198_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x(MUX,23197)@246
    assign leftShiftStage0_uid23198_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23198_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_117_c_compstr3294_vt_join_q or leftShiftStage0Idx1_uid23196_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23198_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23198_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_117_c_compstr3294_vt_join_q;
            1'b1 : leftShiftStage0_uid23198_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23196_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23198_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23203_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x(MUX,23202)@246
    assign leftShiftStage1_uid23203_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23203_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_s or leftShiftStage0_uid23198_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23201_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23203_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23203_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q = leftShiftStage0_uid23198_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23203_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23201_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23203_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23208_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x(MUX,23207)@246
    assign leftShiftStage2_uid23208_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23208_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_s or leftShiftStage1_uid23203_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23206_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23208_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23208_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q = leftShiftStage1_uid23203_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23208_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23206_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23208_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_117_c_compstr3295_vt_select_28(BITSELECT,9097)@246
    assign i_shl_i_i_i_i_i77_i_117_c_compstr3295_vt_select_28_b = leftShiftStage2_uid23208_i_shl_i_i_i_i_i77_i_117_c_compstr0_shift_x_q[28:13];

    // redist491_i_shl_i_i_i_i_i77_i_117_c_compstr3295_vt_select_28_b_1(DELAY,28719)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist491_i_shl_i_i_i_i_i77_i_117_c_compstr3295_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_117_c_compstr3295_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_117_c_compstr3295_vt_join(BITJOIN,9096)@247
    assign i_shl_i_i_i_i_i77_i_117_c_compstr3295_vt_join_q = {redist491_i_shl_i_i_i_i_i77_i_117_c_compstr3295_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma(CHAINMULTADD,28117)@241 + 5
    // out q@247
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ah[0] <= redist1005_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_235_tpl_233_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ah[1] <= redist1004_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_234_tpl_233_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ch[0] <= redist751_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_235_tpl_233_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ch[1] <= redist750_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_234_tpl_233_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296(ADD,8413)@247
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compstr3291_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compstr3293_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compstr3292_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_117_c_compstr3295_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_117_c_compstr3295_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_o[33:0];

    // rightShiftStage0_uid22192_dupName_467_i_unnamed_c_compstr0_shift_x(MUX,22191)@247
    assign rightShiftStage0_uid22192_dupName_467_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22192_dupName_467_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_q or rightShiftStage0Idx1_uid22190_dupName_467_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22192_dupName_467_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22192_dupName_467_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_q;
            1'b1 : rightShiftStage0_uid22192_dupName_467_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22190_dupName_467_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22192_dupName_467_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22197_dupName_467_i_unnamed_c_compstr0_shift_x(MUX,22196)@247
    assign rightShiftStage1_uid22197_dupName_467_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22197_dupName_467_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22192_dupName_467_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22195_dupName_467_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22197_dupName_467_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22197_dupName_467_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22192_dupName_467_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22197_dupName_467_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22195_dupName_467_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22197_dupName_467_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22202_dupName_467_i_unnamed_c_compstr0_shift_x(MUX,22201)@247
    assign rightShiftStage2_uid22202_dupName_467_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22202_dupName_467_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22197_dupName_467_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22200_dupName_467_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22202_dupName_467_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22202_dupName_467_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22197_dupName_467_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22202_dupName_467_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22200_dupName_467_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22202_dupName_467_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3297_vt_select_20(BITSELECT,11796)@247
    assign i_unnamed_c_compstr3297_vt_select_20_b = rightShiftStage2_uid22202_dupName_467_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3297_vt_join(BITJOIN,11795)@247
    assign i_unnamed_c_compstr3297_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3297_vt_select_20_b};

    // i_conv_i_i_i_i97_i_117_c_compstr3298_sel_x(BITSELECT,3475)@247
    assign i_conv_i_i_i_i97_i_117_c_compstr3298_sel_x_b = i_unnamed_c_compstr3297_vt_join_q[15:0];

    // redist1261_i_conv_i_i_i_i97_i_117_c_compstr3298_sel_x_b_1(DELAY,29489)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1261_i_conv_i_i_i_i97_i_117_c_compstr3298_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_117_c_compstr3298_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22211_dupName_468_i_unnamed_c_compstr0_shift_x(BITSELECT,22210)@247
    assign rightShiftStage1Idx1Rng8_uid22211_dupName_468_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22210_dupName_468_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22213_dupName_468_i_unnamed_c_compstr0_shift_x(BITJOIN,22212)@247
    assign rightShiftStage1Idx1_uid22213_dupName_468_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22211_dupName_468_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22206_dupName_468_i_unnamed_c_compstr0_shift_x(BITSELECT,22205)@247
    assign rightShiftStage0Idx1Rng4_uid22206_dupName_468_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_q[33:4];

    // rightShiftStage0Idx1_uid22208_dupName_468_i_unnamed_c_compstr0_shift_x(BITJOIN,22207)@247
    assign rightShiftStage0Idx1_uid22208_dupName_468_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22206_dupName_468_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22210_dupName_468_i_unnamed_c_compstr0_shift_x(MUX,22209)@247
    assign rightShiftStage0_uid22210_dupName_468_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22210_dupName_468_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_q or rightShiftStage0Idx1_uid22208_dupName_468_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22210_dupName_468_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22210_dupName_468_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compstr3296_q;
            1'b1 : rightShiftStage0_uid22210_dupName_468_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22208_dupName_468_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22210_dupName_468_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22215_dupName_468_i_unnamed_c_compstr0_shift_x(MUX,22214)@247
    assign rightShiftStage1_uid22215_dupName_468_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22215_dupName_468_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22210_dupName_468_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22213_dupName_468_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22215_dupName_468_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22215_dupName_468_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22210_dupName_468_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22215_dupName_468_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22213_dupName_468_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22215_dupName_468_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3299_vt_select_21(BITSELECT,11799)@247
    assign i_unnamed_c_compstr3299_vt_select_21_b = rightShiftStage1_uid22215_dupName_468_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3299_vt_join(BITJOIN,11798)@247
    assign i_unnamed_c_compstr3299_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3299_vt_select_21_b};

    // i_unnamed_c_compstr3300_sel_x(BITSELECT,6216)@247
    assign i_unnamed_c_compstr3300_sel_x_b = i_unnamed_c_compstr3299_vt_join_q[15:0];

    // i_unnamed_c_compstr3301_BitSelect_for_a(BITSELECT,27821)@247
    assign i_unnamed_c_compstr3301_BitSelect_for_a_b = i_unnamed_c_compstr3300_sel_x_b[0:0];

    // i_unnamed_c_compstr3301_join(BITJOIN,27822)@247
    assign i_unnamed_c_compstr3301_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3301_BitSelect_for_a_b};

    // i_unnamed_c_compstr3301_vt_select_0(BITSELECT,11807)@247
    assign i_unnamed_c_compstr3301_vt_select_0_b = i_unnamed_c_compstr3301_join_q[0:0];

    // redist75_i_unnamed_c_compstr3301_vt_select_0_b_1(DELAY,28303)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist75_i_unnamed_c_compstr3301_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3301_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3301_vt_join(BITJOIN,11806)@248
    assign i_unnamed_c_compstr3301_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist75_i_unnamed_c_compstr3301_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_117_c_compstr3302(ADD,6870)@248
    assign i_add_i_i_i_i_i126_i_117_c_compstr3302_a = {1'b0, i_unnamed_c_compstr3301_vt_join_q};
    assign i_add_i_i_i_i_i126_i_117_c_compstr3302_b = {1'b0, redist1261_i_conv_i_i_i_i97_i_117_c_compstr3298_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_117_c_compstr3302_o = $unsigned(i_add_i_i_i_i_i126_i_117_c_compstr3302_a) + $unsigned(i_add_i_i_i_i_i126_i_117_c_compstr3302_b);
    assign i_add_i_i_i_i_i126_i_117_c_compstr3302_q = i_add_i_i_i_i_i126_i_117_c_compstr3302_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_117_c_compstr3302_sel_x(BITSELECT,2064)@248
    assign bgTrunc_i_add_i_i_i_i_i126_i_117_c_compstr3302_sel_x_b = i_add_i_i_i_i_i126_i_117_c_compstr3302_q[15:0];

    // i_conv_i_i_i_i_i75_i277_118_c_compstr3322_sel_x(BITSELECT,3605)@248
    assign i_conv_i_i_i_i_i75_i277_118_c_compstr3322_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_117_c_compstr3302_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_118_c_compstr3322_vt_select_15(BITSELECT,7321)@248
    assign i_conv_i_i_i_i_i75_i277_118_c_compstr3322_vt_select_15_b = i_conv_i_i_i_i_i75_i277_118_c_compstr3322_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_118_c_compstr3322_vt_join(BITJOIN,7320)@248
    assign i_conv_i_i_i_i_i75_i277_118_c_compstr3322_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_118_c_compstr3322_vt_select_15_b};

    // leftShiftStage0_uid23216_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x(MUX,23215)@248
    assign leftShiftStage0_uid23216_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23216_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_118_c_compstr3322_vt_join_q or leftShiftStage0Idx1_uid23214_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23216_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23216_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_118_c_compstr3322_vt_join_q;
            1'b1 : leftShiftStage0_uid23216_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23214_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23216_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23221_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x(MUX,23220)@248
    assign leftShiftStage1_uid23221_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23221_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_s or leftShiftStage0_uid23216_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23219_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23221_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23221_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q = leftShiftStage0_uid23216_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23221_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23219_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23221_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23226_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x(MUX,23225)@248
    assign leftShiftStage2_uid23226_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23226_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_s or leftShiftStage1_uid23221_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23224_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23226_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23226_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q = leftShiftStage1_uid23221_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23226_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23224_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23226_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_118_c_compstr3323_vt_select_28(BITSELECT,9100)@248
    assign i_shl_i_i_i_i_i77_i_118_c_compstr3323_vt_select_28_b = leftShiftStage2_uid23226_i_shl_i_i_i_i_i77_i_118_c_compstr0_shift_x_q[28:13];

    // redist490_i_shl_i_i_i_i_i77_i_118_c_compstr3323_vt_select_28_b_1(DELAY,28718)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist490_i_shl_i_i_i_i_i77_i_118_c_compstr3323_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_118_c_compstr3323_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_118_c_compstr3323_vt_join(BITJOIN,9099)@249
    assign i_shl_i_i_i_i_i77_i_118_c_compstr3323_vt_join_q = {redist490_i_shl_i_i_i_i_i77_i_118_c_compstr3323_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma(CHAINMULTADD,28118)@243 + 5
    // out q@249
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ah[0] <= redist1007_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_237_tpl_235_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ah[1] <= redist1006_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_236_tpl_235_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ch[0] <= redist753_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_237_tpl_235_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ch[1] <= redist752_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_236_tpl_235_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324(ADD,8414)@249
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compstr3319_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compstr3321_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compstr3320_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_118_c_compstr3323_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_118_c_compstr3323_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_o[33:0];

    // rightShiftStage0_uid22254_dupName_471_i_unnamed_c_compstr0_shift_x(MUX,22253)@249
    assign rightShiftStage0_uid22254_dupName_471_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22254_dupName_471_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_q or rightShiftStage0Idx1_uid22252_dupName_471_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22254_dupName_471_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22254_dupName_471_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_q;
            1'b1 : rightShiftStage0_uid22254_dupName_471_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22252_dupName_471_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22254_dupName_471_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22259_dupName_471_i_unnamed_c_compstr0_shift_x(MUX,22258)@249
    assign rightShiftStage1_uid22259_dupName_471_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22259_dupName_471_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22254_dupName_471_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22257_dupName_471_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22259_dupName_471_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22259_dupName_471_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22254_dupName_471_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22259_dupName_471_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22257_dupName_471_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22259_dupName_471_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22264_dupName_471_i_unnamed_c_compstr0_shift_x(MUX,22263)@249
    assign rightShiftStage2_uid22264_dupName_471_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22264_dupName_471_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22259_dupName_471_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22262_dupName_471_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22264_dupName_471_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22264_dupName_471_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22259_dupName_471_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22264_dupName_471_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22262_dupName_471_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22264_dupName_471_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3325_vt_select_20(BITSELECT,11824)@249
    assign i_unnamed_c_compstr3325_vt_select_20_b = rightShiftStage2_uid22264_dupName_471_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3325_vt_join(BITJOIN,11823)@249
    assign i_unnamed_c_compstr3325_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3325_vt_select_20_b};

    // i_conv_i_i_i_i97_i_118_c_compstr3326_sel_x(BITSELECT,3476)@249
    assign i_conv_i_i_i_i97_i_118_c_compstr3326_sel_x_b = i_unnamed_c_compstr3325_vt_join_q[15:0];

    // redist1260_i_conv_i_i_i_i97_i_118_c_compstr3326_sel_x_b_1(DELAY,29488)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1260_i_conv_i_i_i_i97_i_118_c_compstr3326_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_118_c_compstr3326_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22273_dupName_472_i_unnamed_c_compstr0_shift_x(BITSELECT,22272)@249
    assign rightShiftStage1Idx1Rng8_uid22273_dupName_472_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22272_dupName_472_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22275_dupName_472_i_unnamed_c_compstr0_shift_x(BITJOIN,22274)@249
    assign rightShiftStage1Idx1_uid22275_dupName_472_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22273_dupName_472_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22268_dupName_472_i_unnamed_c_compstr0_shift_x(BITSELECT,22267)@249
    assign rightShiftStage0Idx1Rng4_uid22268_dupName_472_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_q[33:4];

    // rightShiftStage0Idx1_uid22270_dupName_472_i_unnamed_c_compstr0_shift_x(BITJOIN,22269)@249
    assign rightShiftStage0Idx1_uid22270_dupName_472_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22268_dupName_472_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22272_dupName_472_i_unnamed_c_compstr0_shift_x(MUX,22271)@249
    assign rightShiftStage0_uid22272_dupName_472_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22272_dupName_472_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_q or rightShiftStage0Idx1_uid22270_dupName_472_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22272_dupName_472_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22272_dupName_472_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compstr3324_q;
            1'b1 : rightShiftStage0_uid22272_dupName_472_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22270_dupName_472_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22272_dupName_472_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22277_dupName_472_i_unnamed_c_compstr0_shift_x(MUX,22276)@249
    assign rightShiftStage1_uid22277_dupName_472_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22277_dupName_472_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22272_dupName_472_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22275_dupName_472_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22277_dupName_472_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22277_dupName_472_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22272_dupName_472_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22277_dupName_472_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22275_dupName_472_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22277_dupName_472_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3327_vt_select_21(BITSELECT,11827)@249
    assign i_unnamed_c_compstr3327_vt_select_21_b = rightShiftStage1_uid22277_dupName_472_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3327_vt_join(BITJOIN,11826)@249
    assign i_unnamed_c_compstr3327_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3327_vt_select_21_b};

    // i_unnamed_c_compstr3328_sel_x(BITSELECT,6219)@249
    assign i_unnamed_c_compstr3328_sel_x_b = i_unnamed_c_compstr3327_vt_join_q[15:0];

    // i_unnamed_c_compstr3329_BitSelect_for_a(BITSELECT,27825)@249
    assign i_unnamed_c_compstr3329_BitSelect_for_a_b = i_unnamed_c_compstr3328_sel_x_b[0:0];

    // i_unnamed_c_compstr3329_join(BITJOIN,27826)@249
    assign i_unnamed_c_compstr3329_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3329_BitSelect_for_a_b};

    // i_unnamed_c_compstr3329_vt_select_0(BITSELECT,11832)@249
    assign i_unnamed_c_compstr3329_vt_select_0_b = i_unnamed_c_compstr3329_join_q[0:0];

    // redist73_i_unnamed_c_compstr3329_vt_select_0_b_1(DELAY,28301)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist73_i_unnamed_c_compstr3329_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3329_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3329_vt_join(BITJOIN,11831)@250
    assign i_unnamed_c_compstr3329_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist73_i_unnamed_c_compstr3329_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_118_c_compstr3330(ADD,6871)@250
    assign i_add_i_i_i_i_i126_i_118_c_compstr3330_a = {1'b0, i_unnamed_c_compstr3329_vt_join_q};
    assign i_add_i_i_i_i_i126_i_118_c_compstr3330_b = {1'b0, redist1260_i_conv_i_i_i_i97_i_118_c_compstr3326_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_118_c_compstr3330_o = $unsigned(i_add_i_i_i_i_i126_i_118_c_compstr3330_a) + $unsigned(i_add_i_i_i_i_i126_i_118_c_compstr3330_b);
    assign i_add_i_i_i_i_i126_i_118_c_compstr3330_q = i_add_i_i_i_i_i126_i_118_c_compstr3330_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_118_c_compstr3330_sel_x(BITSELECT,2065)@250
    assign bgTrunc_i_add_i_i_i_i_i126_i_118_c_compstr3330_sel_x_b = i_add_i_i_i_i_i126_i_118_c_compstr3330_q[15:0];

    // i_conv_i_i_i_i_i75_i277_119_c_compstr3350_sel_x(BITSELECT,3606)@250
    assign i_conv_i_i_i_i_i75_i277_119_c_compstr3350_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_118_c_compstr3330_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_119_c_compstr3350_vt_select_15(BITSELECT,7325)@250
    assign i_conv_i_i_i_i_i75_i277_119_c_compstr3350_vt_select_15_b = i_conv_i_i_i_i_i75_i277_119_c_compstr3350_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_119_c_compstr3350_vt_join(BITJOIN,7324)@250
    assign i_conv_i_i_i_i_i75_i277_119_c_compstr3350_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_119_c_compstr3350_vt_select_15_b};

    // leftShiftStage0_uid23234_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x(MUX,23233)@250
    assign leftShiftStage0_uid23234_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23234_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_119_c_compstr3350_vt_join_q or leftShiftStage0Idx1_uid23232_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23234_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23234_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_119_c_compstr3350_vt_join_q;
            1'b1 : leftShiftStage0_uid23234_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23232_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23234_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23239_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x(MUX,23238)@250
    assign leftShiftStage1_uid23239_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23239_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_s or leftShiftStage0_uid23234_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23237_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23239_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23239_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q = leftShiftStage0_uid23234_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23239_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23237_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23239_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23244_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x(MUX,23243)@250
    assign leftShiftStage2_uid23244_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23244_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_s or leftShiftStage1_uid23239_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23242_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23244_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23244_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q = leftShiftStage1_uid23239_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23244_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23242_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23244_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_119_c_compstr3351_vt_select_28(BITSELECT,9103)@250
    assign i_shl_i_i_i_i_i77_i_119_c_compstr3351_vt_select_28_b = leftShiftStage2_uid23244_i_shl_i_i_i_i_i77_i_119_c_compstr0_shift_x_q[28:13];

    // redist489_i_shl_i_i_i_i_i77_i_119_c_compstr3351_vt_select_28_b_1(DELAY,28717)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist489_i_shl_i_i_i_i_i77_i_119_c_compstr3351_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_119_c_compstr3351_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_119_c_compstr3351_vt_join(BITJOIN,9102)@251
    assign i_shl_i_i_i_i_i77_i_119_c_compstr3351_vt_join_q = {redist489_i_shl_i_i_i_i_i77_i_119_c_compstr3351_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma(CHAINMULTADD,28119)@245 + 5
    // out q@251
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ah[0] <= redist1009_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_239_tpl_237_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ah[1] <= redist1008_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_238_tpl_237_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ch[0] <= redist755_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_239_tpl_237_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ch[1] <= redist754_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_238_tpl_237_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352(ADD,8415)@251
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compstr3347_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compstr3349_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compstr3348_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_119_c_compstr3351_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_119_c_compstr3351_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_o[33:0];

    // rightShiftStage0_uid22316_dupName_475_i_unnamed_c_compstr0_shift_x(MUX,22315)@251
    assign rightShiftStage0_uid22316_dupName_475_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22316_dupName_475_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_q or rightShiftStage0Idx1_uid22314_dupName_475_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22316_dupName_475_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22316_dupName_475_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_q;
            1'b1 : rightShiftStage0_uid22316_dupName_475_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22314_dupName_475_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22316_dupName_475_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22321_dupName_475_i_unnamed_c_compstr0_shift_x(MUX,22320)@251
    assign rightShiftStage1_uid22321_dupName_475_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22321_dupName_475_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22316_dupName_475_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22319_dupName_475_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22321_dupName_475_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22321_dupName_475_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22316_dupName_475_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22321_dupName_475_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22319_dupName_475_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22321_dupName_475_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22326_dupName_475_i_unnamed_c_compstr0_shift_x(MUX,22325)@251
    assign rightShiftStage2_uid22326_dupName_475_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22326_dupName_475_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22321_dupName_475_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22324_dupName_475_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22326_dupName_475_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22326_dupName_475_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22321_dupName_475_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22326_dupName_475_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22324_dupName_475_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22326_dupName_475_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3353_vt_select_20(BITSELECT,11851)@251
    assign i_unnamed_c_compstr3353_vt_select_20_b = rightShiftStage2_uid22326_dupName_475_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3353_vt_join(BITJOIN,11850)@251
    assign i_unnamed_c_compstr3353_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3353_vt_select_20_b};

    // i_conv_i_i_i_i97_i_119_c_compstr3354_sel_x(BITSELECT,3477)@251
    assign i_conv_i_i_i_i97_i_119_c_compstr3354_sel_x_b = i_unnamed_c_compstr3353_vt_join_q[15:0];

    // redist1259_i_conv_i_i_i_i97_i_119_c_compstr3354_sel_x_b_1(DELAY,29487)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1259_i_conv_i_i_i_i97_i_119_c_compstr3354_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_119_c_compstr3354_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22335_dupName_476_i_unnamed_c_compstr0_shift_x(BITSELECT,22334)@251
    assign rightShiftStage1Idx1Rng8_uid22335_dupName_476_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22334_dupName_476_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22337_dupName_476_i_unnamed_c_compstr0_shift_x(BITJOIN,22336)@251
    assign rightShiftStage1Idx1_uid22337_dupName_476_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22335_dupName_476_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22330_dupName_476_i_unnamed_c_compstr0_shift_x(BITSELECT,22329)@251
    assign rightShiftStage0Idx1Rng4_uid22330_dupName_476_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_q[33:4];

    // rightShiftStage0Idx1_uid22332_dupName_476_i_unnamed_c_compstr0_shift_x(BITJOIN,22331)@251
    assign rightShiftStage0Idx1_uid22332_dupName_476_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22330_dupName_476_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22334_dupName_476_i_unnamed_c_compstr0_shift_x(MUX,22333)@251
    assign rightShiftStage0_uid22334_dupName_476_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22334_dupName_476_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_q or rightShiftStage0Idx1_uid22332_dupName_476_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22334_dupName_476_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22334_dupName_476_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compstr3352_q;
            1'b1 : rightShiftStage0_uid22334_dupName_476_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22332_dupName_476_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22334_dupName_476_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22339_dupName_476_i_unnamed_c_compstr0_shift_x(MUX,22338)@251
    assign rightShiftStage1_uid22339_dupName_476_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22339_dupName_476_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22334_dupName_476_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22337_dupName_476_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22339_dupName_476_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22339_dupName_476_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22334_dupName_476_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22339_dupName_476_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22337_dupName_476_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22339_dupName_476_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3355_vt_select_21(BITSELECT,11854)@251
    assign i_unnamed_c_compstr3355_vt_select_21_b = rightShiftStage1_uid22339_dupName_476_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3355_vt_join(BITJOIN,11853)@251
    assign i_unnamed_c_compstr3355_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3355_vt_select_21_b};

    // i_unnamed_c_compstr3356_sel_x(BITSELECT,6221)@251
    assign i_unnamed_c_compstr3356_sel_x_b = i_unnamed_c_compstr3355_vt_join_q[15:0];

    // i_unnamed_c_compstr3357_BitSelect_for_a(BITSELECT,27831)@251
    assign i_unnamed_c_compstr3357_BitSelect_for_a_b = i_unnamed_c_compstr3356_sel_x_b[0:0];

    // i_unnamed_c_compstr3357_join(BITJOIN,27832)@251
    assign i_unnamed_c_compstr3357_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3357_BitSelect_for_a_b};

    // i_unnamed_c_compstr3357_vt_select_0(BITSELECT,11859)@251
    assign i_unnamed_c_compstr3357_vt_select_0_b = i_unnamed_c_compstr3357_join_q[0:0];

    // redist70_i_unnamed_c_compstr3357_vt_select_0_b_1(DELAY,28298)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist70_i_unnamed_c_compstr3357_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3357_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3357_vt_join(BITJOIN,11858)@252
    assign i_unnamed_c_compstr3357_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist70_i_unnamed_c_compstr3357_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_119_c_compstr3358(ADD,6872)@252
    assign i_add_i_i_i_i_i126_i_119_c_compstr3358_a = {1'b0, i_unnamed_c_compstr3357_vt_join_q};
    assign i_add_i_i_i_i_i126_i_119_c_compstr3358_b = {1'b0, redist1259_i_conv_i_i_i_i97_i_119_c_compstr3354_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_119_c_compstr3358_o = $unsigned(i_add_i_i_i_i_i126_i_119_c_compstr3358_a) + $unsigned(i_add_i_i_i_i_i126_i_119_c_compstr3358_b);
    assign i_add_i_i_i_i_i126_i_119_c_compstr3358_q = i_add_i_i_i_i_i126_i_119_c_compstr3358_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_119_c_compstr3358_sel_x(BITSELECT,2066)@252
    assign bgTrunc_i_add_i_i_i_i_i126_i_119_c_compstr3358_sel_x_b = i_add_i_i_i_i_i126_i_119_c_compstr3358_q[15:0];

    // i_conv_i_i_i_i_i75_i277_120_c_compstr3378_sel_x(BITSELECT,3608)@252
    assign i_conv_i_i_i_i_i75_i277_120_c_compstr3378_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_119_c_compstr3358_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_120_c_compstr3378_vt_select_15(BITSELECT,7333)@252
    assign i_conv_i_i_i_i_i75_i277_120_c_compstr3378_vt_select_15_b = i_conv_i_i_i_i_i75_i277_120_c_compstr3378_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_120_c_compstr3378_vt_join(BITJOIN,7332)@252
    assign i_conv_i_i_i_i_i75_i277_120_c_compstr3378_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_120_c_compstr3378_vt_select_15_b};

    // leftShiftStage0_uid23270_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x(MUX,23269)@252
    assign leftShiftStage0_uid23270_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23270_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_120_c_compstr3378_vt_join_q or leftShiftStage0Idx1_uid23268_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23270_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23270_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_120_c_compstr3378_vt_join_q;
            1'b1 : leftShiftStage0_uid23270_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23268_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23270_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23275_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x(MUX,23274)@252
    assign leftShiftStage1_uid23275_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23275_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_s or leftShiftStage0_uid23270_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23273_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23275_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23275_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q = leftShiftStage0_uid23270_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23275_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23273_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23275_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23280_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x(MUX,23279)@252
    assign leftShiftStage2_uid23280_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23280_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_s or leftShiftStage1_uid23275_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23278_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23280_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23280_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q = leftShiftStage1_uid23275_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23280_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23278_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23280_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_120_c_compstr3379_vt_select_28(BITSELECT,9109)@252
    assign i_shl_i_i_i_i_i77_i_120_c_compstr3379_vt_select_28_b = leftShiftStage2_uid23280_i_shl_i_i_i_i_i77_i_120_c_compstr0_shift_x_q[28:13];

    // redist487_i_shl_i_i_i_i_i77_i_120_c_compstr3379_vt_select_28_b_1(DELAY,28715)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist487_i_shl_i_i_i_i_i77_i_120_c_compstr3379_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_120_c_compstr3379_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_120_c_compstr3379_vt_join(BITJOIN,9108)@253
    assign i_shl_i_i_i_i_i77_i_120_c_compstr3379_vt_join_q = {redist487_i_shl_i_i_i_i_i77_i_120_c_compstr3379_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma(CHAINMULTADD,28121)@247 + 5
    // out q@253
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ah[0] <= redist1011_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_241_tpl_239_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ah[1] <= redist1010_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_240_tpl_239_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ch[0] <= redist757_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_241_tpl_239_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ch[1] <= redist756_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_240_tpl_239_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380(ADD,8417)@253
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compstr3375_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compstr3377_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compstr3376_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_120_c_compstr3379_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_120_c_compstr3379_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_o[33:0];

    // rightShiftStage0_uid22378_dupName_479_i_unnamed_c_compstr0_shift_x(MUX,22377)@253
    assign rightShiftStage0_uid22378_dupName_479_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22378_dupName_479_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_q or rightShiftStage0Idx1_uid22376_dupName_479_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22378_dupName_479_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22378_dupName_479_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_q;
            1'b1 : rightShiftStage0_uid22378_dupName_479_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22376_dupName_479_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22378_dupName_479_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22383_dupName_479_i_unnamed_c_compstr0_shift_x(MUX,22382)@253
    assign rightShiftStage1_uid22383_dupName_479_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22383_dupName_479_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22378_dupName_479_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22381_dupName_479_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22383_dupName_479_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22383_dupName_479_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22378_dupName_479_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22383_dupName_479_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22381_dupName_479_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22383_dupName_479_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22388_dupName_479_i_unnamed_c_compstr0_shift_x(MUX,22387)@253
    assign rightShiftStage2_uid22388_dupName_479_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22388_dupName_479_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22383_dupName_479_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22386_dupName_479_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22388_dupName_479_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22388_dupName_479_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22383_dupName_479_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22388_dupName_479_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22386_dupName_479_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22388_dupName_479_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3381_vt_select_20(BITSELECT,11873)@253
    assign i_unnamed_c_compstr3381_vt_select_20_b = rightShiftStage2_uid22388_dupName_479_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3381_vt_join(BITJOIN,11872)@253
    assign i_unnamed_c_compstr3381_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3381_vt_select_20_b};

    // i_conv_i_i_i_i97_i_120_c_compstr3382_sel_x(BITSELECT,3479)@253
    assign i_conv_i_i_i_i97_i_120_c_compstr3382_sel_x_b = i_unnamed_c_compstr3381_vt_join_q[15:0];

    // redist1257_i_conv_i_i_i_i97_i_120_c_compstr3382_sel_x_b_1(DELAY,29485)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1257_i_conv_i_i_i_i97_i_120_c_compstr3382_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_120_c_compstr3382_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22397_dupName_480_i_unnamed_c_compstr0_shift_x(BITSELECT,22396)@253
    assign rightShiftStage1Idx1Rng8_uid22397_dupName_480_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22396_dupName_480_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22399_dupName_480_i_unnamed_c_compstr0_shift_x(BITJOIN,22398)@253
    assign rightShiftStage1Idx1_uid22399_dupName_480_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22397_dupName_480_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22392_dupName_480_i_unnamed_c_compstr0_shift_x(BITSELECT,22391)@253
    assign rightShiftStage0Idx1Rng4_uid22392_dupName_480_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_q[33:4];

    // rightShiftStage0Idx1_uid22394_dupName_480_i_unnamed_c_compstr0_shift_x(BITJOIN,22393)@253
    assign rightShiftStage0Idx1_uid22394_dupName_480_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22392_dupName_480_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22396_dupName_480_i_unnamed_c_compstr0_shift_x(MUX,22395)@253
    assign rightShiftStage0_uid22396_dupName_480_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22396_dupName_480_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_q or rightShiftStage0Idx1_uid22394_dupName_480_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22396_dupName_480_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22396_dupName_480_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compstr3380_q;
            1'b1 : rightShiftStage0_uid22396_dupName_480_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22394_dupName_480_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22396_dupName_480_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22401_dupName_480_i_unnamed_c_compstr0_shift_x(MUX,22400)@253
    assign rightShiftStage1_uid22401_dupName_480_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22401_dupName_480_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22396_dupName_480_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22399_dupName_480_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22401_dupName_480_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22401_dupName_480_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22396_dupName_480_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22401_dupName_480_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22399_dupName_480_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22401_dupName_480_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3383_vt_select_21(BITSELECT,11876)@253
    assign i_unnamed_c_compstr3383_vt_select_21_b = rightShiftStage1_uid22401_dupName_480_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3383_vt_join(BITJOIN,11875)@253
    assign i_unnamed_c_compstr3383_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3383_vt_select_21_b};

    // i_unnamed_c_compstr3384_sel_x(BITSELECT,6223)@253
    assign i_unnamed_c_compstr3384_sel_x_b = i_unnamed_c_compstr3383_vt_join_q[15:0];

    // i_unnamed_c_compstr3385_BitSelect_for_a(BITSELECT,27835)@253
    assign i_unnamed_c_compstr3385_BitSelect_for_a_b = i_unnamed_c_compstr3384_sel_x_b[0:0];

    // i_unnamed_c_compstr3385_join(BITJOIN,27836)@253
    assign i_unnamed_c_compstr3385_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3385_BitSelect_for_a_b};

    // i_unnamed_c_compstr3385_vt_select_0(BITSELECT,11881)@253
    assign i_unnamed_c_compstr3385_vt_select_0_b = i_unnamed_c_compstr3385_join_q[0:0];

    // redist68_i_unnamed_c_compstr3385_vt_select_0_b_1(DELAY,28296)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist68_i_unnamed_c_compstr3385_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3385_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3385_vt_join(BITJOIN,11880)@254
    assign i_unnamed_c_compstr3385_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist68_i_unnamed_c_compstr3385_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_120_c_compstr3386(ADD,6874)@254
    assign i_add_i_i_i_i_i126_i_120_c_compstr3386_a = {1'b0, i_unnamed_c_compstr3385_vt_join_q};
    assign i_add_i_i_i_i_i126_i_120_c_compstr3386_b = {1'b0, redist1257_i_conv_i_i_i_i97_i_120_c_compstr3382_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_120_c_compstr3386_o = $unsigned(i_add_i_i_i_i_i126_i_120_c_compstr3386_a) + $unsigned(i_add_i_i_i_i_i126_i_120_c_compstr3386_b);
    assign i_add_i_i_i_i_i126_i_120_c_compstr3386_q = i_add_i_i_i_i_i126_i_120_c_compstr3386_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_120_c_compstr3386_sel_x(BITSELECT,2068)@254
    assign bgTrunc_i_add_i_i_i_i_i126_i_120_c_compstr3386_sel_x_b = i_add_i_i_i_i_i126_i_120_c_compstr3386_q[15:0];

    // i_conv_i_i_i_i_i75_i277_121_c_compstr3406_sel_x(BITSELECT,3609)@254
    assign i_conv_i_i_i_i_i75_i277_121_c_compstr3406_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_120_c_compstr3386_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_121_c_compstr3406_vt_select_15(BITSELECT,7337)@254
    assign i_conv_i_i_i_i_i75_i277_121_c_compstr3406_vt_select_15_b = i_conv_i_i_i_i_i75_i277_121_c_compstr3406_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_121_c_compstr3406_vt_join(BITJOIN,7336)@254
    assign i_conv_i_i_i_i_i75_i277_121_c_compstr3406_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_121_c_compstr3406_vt_select_15_b};

    // leftShiftStage0_uid23288_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x(MUX,23287)@254
    assign leftShiftStage0_uid23288_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23288_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_121_c_compstr3406_vt_join_q or leftShiftStage0Idx1_uid23286_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23288_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23288_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_121_c_compstr3406_vt_join_q;
            1'b1 : leftShiftStage0_uid23288_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23286_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23288_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23293_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x(MUX,23292)@254
    assign leftShiftStage1_uid23293_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23293_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_s or leftShiftStage0_uid23288_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23291_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23293_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23293_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q = leftShiftStage0_uid23288_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23293_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23291_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23293_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23298_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x(MUX,23297)@254
    assign leftShiftStage2_uid23298_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23298_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_s or leftShiftStage1_uid23293_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23296_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23298_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23298_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q = leftShiftStage1_uid23293_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23298_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23296_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23298_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_121_c_compstr3407_vt_select_28(BITSELECT,9112)@254
    assign i_shl_i_i_i_i_i77_i_121_c_compstr3407_vt_select_28_b = leftShiftStage2_uid23298_i_shl_i_i_i_i_i77_i_121_c_compstr0_shift_x_q[28:13];

    // redist486_i_shl_i_i_i_i_i77_i_121_c_compstr3407_vt_select_28_b_1(DELAY,28714)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist486_i_shl_i_i_i_i_i77_i_121_c_compstr3407_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_121_c_compstr3407_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_121_c_compstr3407_vt_join(BITJOIN,9111)@255
    assign i_shl_i_i_i_i_i77_i_121_c_compstr3407_vt_join_q = {redist486_i_shl_i_i_i_i_i77_i_121_c_compstr3407_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma(CHAINMULTADD,28122)@249 + 5
    // out q@255
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ah[0] <= redist1013_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_243_tpl_241_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ah[1] <= redist1012_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_242_tpl_241_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ch[0] <= redist759_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_243_tpl_241_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ch[1] <= redist758_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_242_tpl_241_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408(ADD,8418)@255
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compstr3403_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compstr3405_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compstr3404_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_121_c_compstr3407_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_121_c_compstr3407_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_o[33:0];

    // rightShiftStage0_uid22440_dupName_483_i_unnamed_c_compstr0_shift_x(MUX,22439)@255
    assign rightShiftStage0_uid22440_dupName_483_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22440_dupName_483_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_q or rightShiftStage0Idx1_uid22438_dupName_483_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22440_dupName_483_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22440_dupName_483_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_q;
            1'b1 : rightShiftStage0_uid22440_dupName_483_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22438_dupName_483_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22440_dupName_483_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22445_dupName_483_i_unnamed_c_compstr0_shift_x(MUX,22444)@255
    assign rightShiftStage1_uid22445_dupName_483_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22445_dupName_483_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22440_dupName_483_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22443_dupName_483_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22445_dupName_483_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22445_dupName_483_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22440_dupName_483_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22445_dupName_483_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22443_dupName_483_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22445_dupName_483_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22450_dupName_483_i_unnamed_c_compstr0_shift_x(MUX,22449)@255
    assign rightShiftStage2_uid22450_dupName_483_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22450_dupName_483_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22445_dupName_483_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22448_dupName_483_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22450_dupName_483_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22450_dupName_483_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22445_dupName_483_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22450_dupName_483_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22448_dupName_483_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22450_dupName_483_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3409_vt_select_20(BITSELECT,11895)@255
    assign i_unnamed_c_compstr3409_vt_select_20_b = rightShiftStage2_uid22450_dupName_483_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3409_vt_join(BITJOIN,11894)@255
    assign i_unnamed_c_compstr3409_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3409_vt_select_20_b};

    // i_conv_i_i_i_i97_i_121_c_compstr3410_sel_x(BITSELECT,3480)@255
    assign i_conv_i_i_i_i97_i_121_c_compstr3410_sel_x_b = i_unnamed_c_compstr3409_vt_join_q[15:0];

    // redist1256_i_conv_i_i_i_i97_i_121_c_compstr3410_sel_x_b_1(DELAY,29484)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1256_i_conv_i_i_i_i97_i_121_c_compstr3410_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_121_c_compstr3410_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22459_dupName_484_i_unnamed_c_compstr0_shift_x(BITSELECT,22458)@255
    assign rightShiftStage1Idx1Rng8_uid22459_dupName_484_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22458_dupName_484_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22461_dupName_484_i_unnamed_c_compstr0_shift_x(BITJOIN,22460)@255
    assign rightShiftStage1Idx1_uid22461_dupName_484_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22459_dupName_484_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22454_dupName_484_i_unnamed_c_compstr0_shift_x(BITSELECT,22453)@255
    assign rightShiftStage0Idx1Rng4_uid22454_dupName_484_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_q[33:4];

    // rightShiftStage0Idx1_uid22456_dupName_484_i_unnamed_c_compstr0_shift_x(BITJOIN,22455)@255
    assign rightShiftStage0Idx1_uid22456_dupName_484_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22454_dupName_484_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22458_dupName_484_i_unnamed_c_compstr0_shift_x(MUX,22457)@255
    assign rightShiftStage0_uid22458_dupName_484_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22458_dupName_484_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_q or rightShiftStage0Idx1_uid22456_dupName_484_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22458_dupName_484_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22458_dupName_484_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compstr3408_q;
            1'b1 : rightShiftStage0_uid22458_dupName_484_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22456_dupName_484_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22458_dupName_484_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22463_dupName_484_i_unnamed_c_compstr0_shift_x(MUX,22462)@255
    assign rightShiftStage1_uid22463_dupName_484_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22463_dupName_484_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22458_dupName_484_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22461_dupName_484_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22463_dupName_484_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22463_dupName_484_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22458_dupName_484_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22463_dupName_484_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22461_dupName_484_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22463_dupName_484_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3411_vt_select_21(BITSELECT,11898)@255
    assign i_unnamed_c_compstr3411_vt_select_21_b = rightShiftStage1_uid22463_dupName_484_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3411_vt_join(BITJOIN,11897)@255
    assign i_unnamed_c_compstr3411_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3411_vt_select_21_b};

    // i_unnamed_c_compstr3412_sel_x(BITSELECT,6225)@255
    assign i_unnamed_c_compstr3412_sel_x_b = i_unnamed_c_compstr3411_vt_join_q[15:0];

    // i_unnamed_c_compstr3413_BitSelect_for_a(BITSELECT,27839)@255
    assign i_unnamed_c_compstr3413_BitSelect_for_a_b = i_unnamed_c_compstr3412_sel_x_b[0:0];

    // i_unnamed_c_compstr3413_join(BITJOIN,27840)@255
    assign i_unnamed_c_compstr3413_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3413_BitSelect_for_a_b};

    // i_unnamed_c_compstr3413_vt_select_0(BITSELECT,11903)@255
    assign i_unnamed_c_compstr3413_vt_select_0_b = i_unnamed_c_compstr3413_join_q[0:0];

    // redist66_i_unnamed_c_compstr3413_vt_select_0_b_1(DELAY,28294)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist66_i_unnamed_c_compstr3413_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3413_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3413_vt_join(BITJOIN,11902)@256
    assign i_unnamed_c_compstr3413_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist66_i_unnamed_c_compstr3413_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_121_c_compstr3414(ADD,6875)@256
    assign i_add_i_i_i_i_i126_i_121_c_compstr3414_a = {1'b0, i_unnamed_c_compstr3413_vt_join_q};
    assign i_add_i_i_i_i_i126_i_121_c_compstr3414_b = {1'b0, redist1256_i_conv_i_i_i_i97_i_121_c_compstr3410_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_121_c_compstr3414_o = $unsigned(i_add_i_i_i_i_i126_i_121_c_compstr3414_a) + $unsigned(i_add_i_i_i_i_i126_i_121_c_compstr3414_b);
    assign i_add_i_i_i_i_i126_i_121_c_compstr3414_q = i_add_i_i_i_i_i126_i_121_c_compstr3414_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_121_c_compstr3414_sel_x(BITSELECT,2069)@256
    assign bgTrunc_i_add_i_i_i_i_i126_i_121_c_compstr3414_sel_x_b = i_add_i_i_i_i_i126_i_121_c_compstr3414_q[15:0];

    // i_conv_i_i_i_i_i75_i277_122_c_compstr3434_sel_x(BITSELECT,3610)@256
    assign i_conv_i_i_i_i_i75_i277_122_c_compstr3434_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_121_c_compstr3414_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_122_c_compstr3434_vt_select_15(BITSELECT,7341)@256
    assign i_conv_i_i_i_i_i75_i277_122_c_compstr3434_vt_select_15_b = i_conv_i_i_i_i_i75_i277_122_c_compstr3434_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_122_c_compstr3434_vt_join(BITJOIN,7340)@256
    assign i_conv_i_i_i_i_i75_i277_122_c_compstr3434_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_122_c_compstr3434_vt_select_15_b};

    // leftShiftStage0_uid23306_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x(MUX,23305)@256
    assign leftShiftStage0_uid23306_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23306_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_122_c_compstr3434_vt_join_q or leftShiftStage0Idx1_uid23304_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23306_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23306_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_122_c_compstr3434_vt_join_q;
            1'b1 : leftShiftStage0_uid23306_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23304_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23306_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23311_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x(MUX,23310)@256
    assign leftShiftStage1_uid23311_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23311_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_s or leftShiftStage0_uid23306_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23309_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23311_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23311_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q = leftShiftStage0_uid23306_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23311_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23309_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23311_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23316_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x(MUX,23315)@256
    assign leftShiftStage2_uid23316_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23316_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_s or leftShiftStage1_uid23311_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23314_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23316_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23316_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q = leftShiftStage1_uid23311_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23316_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23314_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23316_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_122_c_compstr3435_vt_select_28(BITSELECT,9115)@256
    assign i_shl_i_i_i_i_i77_i_122_c_compstr3435_vt_select_28_b = leftShiftStage2_uid23316_i_shl_i_i_i_i_i77_i_122_c_compstr0_shift_x_q[28:13];

    // redist485_i_shl_i_i_i_i_i77_i_122_c_compstr3435_vt_select_28_b_1(DELAY,28713)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist485_i_shl_i_i_i_i_i77_i_122_c_compstr3435_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_122_c_compstr3435_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_122_c_compstr3435_vt_join(BITJOIN,9114)@257
    assign i_shl_i_i_i_i_i77_i_122_c_compstr3435_vt_join_q = {redist485_i_shl_i_i_i_i_i77_i_122_c_compstr3435_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma(CHAINMULTADD,28123)@251 + 5
    // out q@257
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ah[0] <= redist1015_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_245_tpl_243_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ah[1] <= redist1014_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_244_tpl_243_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ch[0] <= redist761_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_245_tpl_243_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ch[1] <= redist760_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_244_tpl_243_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436(ADD,8419)@257
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compstr3431_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compstr3433_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compstr3432_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_122_c_compstr3435_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_122_c_compstr3435_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_o[33:0];

    // rightShiftStage0_uid22502_dupName_487_i_unnamed_c_compstr0_shift_x(MUX,22501)@257
    assign rightShiftStage0_uid22502_dupName_487_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22502_dupName_487_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_q or rightShiftStage0Idx1_uid22500_dupName_487_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22502_dupName_487_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22502_dupName_487_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_q;
            1'b1 : rightShiftStage0_uid22502_dupName_487_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22500_dupName_487_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22502_dupName_487_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22507_dupName_487_i_unnamed_c_compstr0_shift_x(MUX,22506)@257
    assign rightShiftStage1_uid22507_dupName_487_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22507_dupName_487_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22502_dupName_487_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22505_dupName_487_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22507_dupName_487_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22507_dupName_487_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22502_dupName_487_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22507_dupName_487_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22505_dupName_487_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22507_dupName_487_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22512_dupName_487_i_unnamed_c_compstr0_shift_x(MUX,22511)@257
    assign rightShiftStage2_uid22512_dupName_487_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22512_dupName_487_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22507_dupName_487_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22510_dupName_487_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22512_dupName_487_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22512_dupName_487_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22507_dupName_487_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22512_dupName_487_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22510_dupName_487_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22512_dupName_487_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3437_vt_select_20(BITSELECT,11917)@257
    assign i_unnamed_c_compstr3437_vt_select_20_b = rightShiftStage2_uid22512_dupName_487_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3437_vt_join(BITJOIN,11916)@257
    assign i_unnamed_c_compstr3437_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3437_vt_select_20_b};

    // i_conv_i_i_i_i97_i_122_c_compstr3438_sel_x(BITSELECT,3481)@257
    assign i_conv_i_i_i_i97_i_122_c_compstr3438_sel_x_b = i_unnamed_c_compstr3437_vt_join_q[15:0];

    // redist1255_i_conv_i_i_i_i97_i_122_c_compstr3438_sel_x_b_1(DELAY,29483)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1255_i_conv_i_i_i_i97_i_122_c_compstr3438_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_122_c_compstr3438_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22521_dupName_488_i_unnamed_c_compstr0_shift_x(BITSELECT,22520)@257
    assign rightShiftStage1Idx1Rng8_uid22521_dupName_488_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22520_dupName_488_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22523_dupName_488_i_unnamed_c_compstr0_shift_x(BITJOIN,22522)@257
    assign rightShiftStage1Idx1_uid22523_dupName_488_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22521_dupName_488_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22516_dupName_488_i_unnamed_c_compstr0_shift_x(BITSELECT,22515)@257
    assign rightShiftStage0Idx1Rng4_uid22516_dupName_488_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_q[33:4];

    // rightShiftStage0Idx1_uid22518_dupName_488_i_unnamed_c_compstr0_shift_x(BITJOIN,22517)@257
    assign rightShiftStage0Idx1_uid22518_dupName_488_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22516_dupName_488_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22520_dupName_488_i_unnamed_c_compstr0_shift_x(MUX,22519)@257
    assign rightShiftStage0_uid22520_dupName_488_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22520_dupName_488_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_q or rightShiftStage0Idx1_uid22518_dupName_488_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22520_dupName_488_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22520_dupName_488_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compstr3436_q;
            1'b1 : rightShiftStage0_uid22520_dupName_488_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22518_dupName_488_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22520_dupName_488_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22525_dupName_488_i_unnamed_c_compstr0_shift_x(MUX,22524)@257
    assign rightShiftStage1_uid22525_dupName_488_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22525_dupName_488_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22520_dupName_488_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22523_dupName_488_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22525_dupName_488_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22525_dupName_488_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22520_dupName_488_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22525_dupName_488_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22523_dupName_488_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22525_dupName_488_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3439_vt_select_21(BITSELECT,11920)@257
    assign i_unnamed_c_compstr3439_vt_select_21_b = rightShiftStage1_uid22525_dupName_488_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3439_vt_join(BITJOIN,11919)@257
    assign i_unnamed_c_compstr3439_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3439_vt_select_21_b};

    // i_unnamed_c_compstr3440_sel_x(BITSELECT,6227)@257
    assign i_unnamed_c_compstr3440_sel_x_b = i_unnamed_c_compstr3439_vt_join_q[15:0];

    // i_unnamed_c_compstr3441_BitSelect_for_a(BITSELECT,27843)@257
    assign i_unnamed_c_compstr3441_BitSelect_for_a_b = i_unnamed_c_compstr3440_sel_x_b[0:0];

    // i_unnamed_c_compstr3441_join(BITJOIN,27844)@257
    assign i_unnamed_c_compstr3441_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3441_BitSelect_for_a_b};

    // i_unnamed_c_compstr3441_vt_select_0(BITSELECT,11925)@257
    assign i_unnamed_c_compstr3441_vt_select_0_b = i_unnamed_c_compstr3441_join_q[0:0];

    // redist64_i_unnamed_c_compstr3441_vt_select_0_b_1(DELAY,28292)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist64_i_unnamed_c_compstr3441_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3441_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3441_vt_join(BITJOIN,11924)@258
    assign i_unnamed_c_compstr3441_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist64_i_unnamed_c_compstr3441_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_122_c_compstr3442(ADD,6876)@258
    assign i_add_i_i_i_i_i126_i_122_c_compstr3442_a = {1'b0, i_unnamed_c_compstr3441_vt_join_q};
    assign i_add_i_i_i_i_i126_i_122_c_compstr3442_b = {1'b0, redist1255_i_conv_i_i_i_i97_i_122_c_compstr3438_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_122_c_compstr3442_o = $unsigned(i_add_i_i_i_i_i126_i_122_c_compstr3442_a) + $unsigned(i_add_i_i_i_i_i126_i_122_c_compstr3442_b);
    assign i_add_i_i_i_i_i126_i_122_c_compstr3442_q = i_add_i_i_i_i_i126_i_122_c_compstr3442_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_122_c_compstr3442_sel_x(BITSELECT,2070)@258
    assign bgTrunc_i_add_i_i_i_i_i126_i_122_c_compstr3442_sel_x_b = i_add_i_i_i_i_i126_i_122_c_compstr3442_q[15:0];

    // i_conv_i_i_i_i_i75_i277_123_c_compstr3462_sel_x(BITSELECT,3611)@258
    assign i_conv_i_i_i_i_i75_i277_123_c_compstr3462_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_122_c_compstr3442_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_123_c_compstr3462_vt_select_15(BITSELECT,7345)@258
    assign i_conv_i_i_i_i_i75_i277_123_c_compstr3462_vt_select_15_b = i_conv_i_i_i_i_i75_i277_123_c_compstr3462_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_123_c_compstr3462_vt_join(BITJOIN,7344)@258
    assign i_conv_i_i_i_i_i75_i277_123_c_compstr3462_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_123_c_compstr3462_vt_select_15_b};

    // leftShiftStage0_uid23324_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x(MUX,23323)@258
    assign leftShiftStage0_uid23324_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23324_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_123_c_compstr3462_vt_join_q or leftShiftStage0Idx1_uid23322_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23324_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23324_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_123_c_compstr3462_vt_join_q;
            1'b1 : leftShiftStage0_uid23324_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23322_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23324_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23329_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x(MUX,23328)@258
    assign leftShiftStage1_uid23329_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23329_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_s or leftShiftStage0_uid23324_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23327_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23329_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23329_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q = leftShiftStage0_uid23324_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23329_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23327_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23329_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23334_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x(MUX,23333)@258
    assign leftShiftStage2_uid23334_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23334_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_s or leftShiftStage1_uid23329_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23332_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23334_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23334_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q = leftShiftStage1_uid23329_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23334_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23332_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23334_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_123_c_compstr3463_vt_select_28(BITSELECT,9118)@258
    assign i_shl_i_i_i_i_i77_i_123_c_compstr3463_vt_select_28_b = leftShiftStage2_uid23334_i_shl_i_i_i_i_i77_i_123_c_compstr0_shift_x_q[28:13];

    // redist484_i_shl_i_i_i_i_i77_i_123_c_compstr3463_vt_select_28_b_1(DELAY,28712)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist484_i_shl_i_i_i_i_i77_i_123_c_compstr3463_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_123_c_compstr3463_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_123_c_compstr3463_vt_join(BITJOIN,9117)@259
    assign i_shl_i_i_i_i_i77_i_123_c_compstr3463_vt_join_q = {redist484_i_shl_i_i_i_i_i77_i_123_c_compstr3463_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma(CHAINMULTADD,28124)@253 + 5
    // out q@259
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ah[0] <= redist1017_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_247_tpl_245_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ah[1] <= redist1016_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_246_tpl_245_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ch[0] <= redist763_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_247_tpl_245_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ch[1] <= redist762_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_246_tpl_245_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464(ADD,8420)@259
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compstr3459_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compstr3461_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compstr3460_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_123_c_compstr3463_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_123_c_compstr3463_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_o[33:0];

    // rightShiftStage0_uid22564_dupName_491_i_unnamed_c_compstr0_shift_x(MUX,22563)@259
    assign rightShiftStage0_uid22564_dupName_491_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22564_dupName_491_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_q or rightShiftStage0Idx1_uid22562_dupName_491_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22564_dupName_491_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22564_dupName_491_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_q;
            1'b1 : rightShiftStage0_uid22564_dupName_491_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22562_dupName_491_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22564_dupName_491_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22569_dupName_491_i_unnamed_c_compstr0_shift_x(MUX,22568)@259
    assign rightShiftStage1_uid22569_dupName_491_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22569_dupName_491_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22564_dupName_491_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22567_dupName_491_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22569_dupName_491_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22569_dupName_491_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22564_dupName_491_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22569_dupName_491_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22567_dupName_491_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22569_dupName_491_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22574_dupName_491_i_unnamed_c_compstr0_shift_x(MUX,22573)@259
    assign rightShiftStage2_uid22574_dupName_491_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22574_dupName_491_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22569_dupName_491_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22572_dupName_491_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22574_dupName_491_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22574_dupName_491_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22569_dupName_491_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22574_dupName_491_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22572_dupName_491_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22574_dupName_491_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3465_vt_select_20(BITSELECT,11942)@259
    assign i_unnamed_c_compstr3465_vt_select_20_b = rightShiftStage2_uid22574_dupName_491_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3465_vt_join(BITJOIN,11941)@259
    assign i_unnamed_c_compstr3465_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3465_vt_select_20_b};

    // i_conv_i_i_i_i97_i_123_c_compstr3466_sel_x(BITSELECT,3482)@259
    assign i_conv_i_i_i_i97_i_123_c_compstr3466_sel_x_b = i_unnamed_c_compstr3465_vt_join_q[15:0];

    // redist1254_i_conv_i_i_i_i97_i_123_c_compstr3466_sel_x_b_1(DELAY,29482)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1254_i_conv_i_i_i_i97_i_123_c_compstr3466_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_123_c_compstr3466_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22583_dupName_492_i_unnamed_c_compstr0_shift_x(BITSELECT,22582)@259
    assign rightShiftStage1Idx1Rng8_uid22583_dupName_492_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22582_dupName_492_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22585_dupName_492_i_unnamed_c_compstr0_shift_x(BITJOIN,22584)@259
    assign rightShiftStage1Idx1_uid22585_dupName_492_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22583_dupName_492_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22578_dupName_492_i_unnamed_c_compstr0_shift_x(BITSELECT,22577)@259
    assign rightShiftStage0Idx1Rng4_uid22578_dupName_492_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_q[33:4];

    // rightShiftStage0Idx1_uid22580_dupName_492_i_unnamed_c_compstr0_shift_x(BITJOIN,22579)@259
    assign rightShiftStage0Idx1_uid22580_dupName_492_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22578_dupName_492_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22582_dupName_492_i_unnamed_c_compstr0_shift_x(MUX,22581)@259
    assign rightShiftStage0_uid22582_dupName_492_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22582_dupName_492_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_q or rightShiftStage0Idx1_uid22580_dupName_492_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22582_dupName_492_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22582_dupName_492_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compstr3464_q;
            1'b1 : rightShiftStage0_uid22582_dupName_492_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22580_dupName_492_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22582_dupName_492_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22587_dupName_492_i_unnamed_c_compstr0_shift_x(MUX,22586)@259
    assign rightShiftStage1_uid22587_dupName_492_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22587_dupName_492_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22582_dupName_492_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22585_dupName_492_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22587_dupName_492_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22587_dupName_492_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22582_dupName_492_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22587_dupName_492_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22585_dupName_492_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22587_dupName_492_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3467_vt_select_21(BITSELECT,11945)@259
    assign i_unnamed_c_compstr3467_vt_select_21_b = rightShiftStage1_uid22587_dupName_492_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3467_vt_join(BITJOIN,11944)@259
    assign i_unnamed_c_compstr3467_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3467_vt_select_21_b};

    // i_unnamed_c_compstr3468_sel_x(BITSELECT,6229)@259
    assign i_unnamed_c_compstr3468_sel_x_b = i_unnamed_c_compstr3467_vt_join_q[15:0];

    // i_unnamed_c_compstr3469_BitSelect_for_a(BITSELECT,27847)@259
    assign i_unnamed_c_compstr3469_BitSelect_for_a_b = i_unnamed_c_compstr3468_sel_x_b[0:0];

    // i_unnamed_c_compstr3469_join(BITJOIN,27848)@259
    assign i_unnamed_c_compstr3469_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3469_BitSelect_for_a_b};

    // i_unnamed_c_compstr3469_vt_select_0(BITSELECT,11950)@259
    assign i_unnamed_c_compstr3469_vt_select_0_b = i_unnamed_c_compstr3469_join_q[0:0];

    // redist62_i_unnamed_c_compstr3469_vt_select_0_b_1(DELAY,28290)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist62_i_unnamed_c_compstr3469_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3469_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3469_vt_join(BITJOIN,11949)@260
    assign i_unnamed_c_compstr3469_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist62_i_unnamed_c_compstr3469_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_123_c_compstr3470(ADD,6877)@260
    assign i_add_i_i_i_i_i126_i_123_c_compstr3470_a = {1'b0, i_unnamed_c_compstr3469_vt_join_q};
    assign i_add_i_i_i_i_i126_i_123_c_compstr3470_b = {1'b0, redist1254_i_conv_i_i_i_i97_i_123_c_compstr3466_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_123_c_compstr3470_o = $unsigned(i_add_i_i_i_i_i126_i_123_c_compstr3470_a) + $unsigned(i_add_i_i_i_i_i126_i_123_c_compstr3470_b);
    assign i_add_i_i_i_i_i126_i_123_c_compstr3470_q = i_add_i_i_i_i_i126_i_123_c_compstr3470_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_123_c_compstr3470_sel_x(BITSELECT,2071)@260
    assign bgTrunc_i_add_i_i_i_i_i126_i_123_c_compstr3470_sel_x_b = i_add_i_i_i_i_i126_i_123_c_compstr3470_q[15:0];

    // i_conv_i_i_i_i_i75_i277_124_c_compstr3490_sel_x(BITSELECT,3612)@260
    assign i_conv_i_i_i_i_i75_i277_124_c_compstr3490_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_123_c_compstr3470_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_124_c_compstr3490_vt_select_15(BITSELECT,7349)@260
    assign i_conv_i_i_i_i_i75_i277_124_c_compstr3490_vt_select_15_b = i_conv_i_i_i_i_i75_i277_124_c_compstr3490_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_124_c_compstr3490_vt_join(BITJOIN,7348)@260
    assign i_conv_i_i_i_i_i75_i277_124_c_compstr3490_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_124_c_compstr3490_vt_select_15_b};

    // leftShiftStage0_uid23342_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x(MUX,23341)@260
    assign leftShiftStage0_uid23342_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23342_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_124_c_compstr3490_vt_join_q or leftShiftStage0Idx1_uid23340_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23342_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23342_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_124_c_compstr3490_vt_join_q;
            1'b1 : leftShiftStage0_uid23342_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23340_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23342_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23347_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x(MUX,23346)@260
    assign leftShiftStage1_uid23347_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23347_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_s or leftShiftStage0_uid23342_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23345_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23347_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23347_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q = leftShiftStage0_uid23342_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23347_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23345_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23347_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23352_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x(MUX,23351)@260
    assign leftShiftStage2_uid23352_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23352_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_s or leftShiftStage1_uid23347_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23350_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23352_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23352_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q = leftShiftStage1_uid23347_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23352_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23350_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23352_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_124_c_compstr3491_vt_select_28(BITSELECT,9121)@260
    assign i_shl_i_i_i_i_i77_i_124_c_compstr3491_vt_select_28_b = leftShiftStage2_uid23352_i_shl_i_i_i_i_i77_i_124_c_compstr0_shift_x_q[28:13];

    // redist483_i_shl_i_i_i_i_i77_i_124_c_compstr3491_vt_select_28_b_1(DELAY,28711)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist483_i_shl_i_i_i_i_i77_i_124_c_compstr3491_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_124_c_compstr3491_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_124_c_compstr3491_vt_join(BITJOIN,9120)@261
    assign i_shl_i_i_i_i_i77_i_124_c_compstr3491_vt_join_q = {redist483_i_shl_i_i_i_i_i77_i_124_c_compstr3491_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma(CHAINMULTADD,28125)@255 + 5
    // out q@261
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ah[0] <= redist1019_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_249_tpl_247_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ah[1] <= redist1018_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_248_tpl_247_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ch[0] <= redist765_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_249_tpl_247_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ch[1] <= redist764_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_248_tpl_247_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492(ADD,8421)@261
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compstr3487_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compstr3489_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compstr3488_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_124_c_compstr3491_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_124_c_compstr3491_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_o[33:0];

    // rightShiftStage0_uid22626_dupName_495_i_unnamed_c_compstr0_shift_x(MUX,22625)@261
    assign rightShiftStage0_uid22626_dupName_495_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22626_dupName_495_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_q or rightShiftStage0Idx1_uid22624_dupName_495_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22626_dupName_495_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22626_dupName_495_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_q;
            1'b1 : rightShiftStage0_uid22626_dupName_495_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22624_dupName_495_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22626_dupName_495_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22631_dupName_495_i_unnamed_c_compstr0_shift_x(MUX,22630)@261
    assign rightShiftStage1_uid22631_dupName_495_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22631_dupName_495_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22626_dupName_495_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22629_dupName_495_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22631_dupName_495_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22631_dupName_495_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22626_dupName_495_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22631_dupName_495_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22629_dupName_495_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22631_dupName_495_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22636_dupName_495_i_unnamed_c_compstr0_shift_x(MUX,22635)@261
    assign rightShiftStage2_uid22636_dupName_495_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22636_dupName_495_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22631_dupName_495_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22634_dupName_495_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22636_dupName_495_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22636_dupName_495_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22631_dupName_495_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22636_dupName_495_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22634_dupName_495_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22636_dupName_495_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3493_vt_select_20(BITSELECT,11969)@261
    assign i_unnamed_c_compstr3493_vt_select_20_b = rightShiftStage2_uid22636_dupName_495_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3493_vt_join(BITJOIN,11968)@261
    assign i_unnamed_c_compstr3493_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3493_vt_select_20_b};

    // i_conv_i_i_i_i97_i_124_c_compstr3494_sel_x(BITSELECT,3483)@261
    assign i_conv_i_i_i_i97_i_124_c_compstr3494_sel_x_b = i_unnamed_c_compstr3493_vt_join_q[15:0];

    // redist1253_i_conv_i_i_i_i97_i_124_c_compstr3494_sel_x_b_1(DELAY,29481)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1253_i_conv_i_i_i_i97_i_124_c_compstr3494_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_124_c_compstr3494_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22645_dupName_496_i_unnamed_c_compstr0_shift_x(BITSELECT,22644)@261
    assign rightShiftStage1Idx1Rng8_uid22645_dupName_496_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22644_dupName_496_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22647_dupName_496_i_unnamed_c_compstr0_shift_x(BITJOIN,22646)@261
    assign rightShiftStage1Idx1_uid22647_dupName_496_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22645_dupName_496_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22640_dupName_496_i_unnamed_c_compstr0_shift_x(BITSELECT,22639)@261
    assign rightShiftStage0Idx1Rng4_uid22640_dupName_496_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_q[33:4];

    // rightShiftStage0Idx1_uid22642_dupName_496_i_unnamed_c_compstr0_shift_x(BITJOIN,22641)@261
    assign rightShiftStage0Idx1_uid22642_dupName_496_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22640_dupName_496_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22644_dupName_496_i_unnamed_c_compstr0_shift_x(MUX,22643)@261
    assign rightShiftStage0_uid22644_dupName_496_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22644_dupName_496_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_q or rightShiftStage0Idx1_uid22642_dupName_496_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22644_dupName_496_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22644_dupName_496_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compstr3492_q;
            1'b1 : rightShiftStage0_uid22644_dupName_496_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22642_dupName_496_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22644_dupName_496_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22649_dupName_496_i_unnamed_c_compstr0_shift_x(MUX,22648)@261
    assign rightShiftStage1_uid22649_dupName_496_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22649_dupName_496_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22644_dupName_496_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22647_dupName_496_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22649_dupName_496_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22649_dupName_496_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22644_dupName_496_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22649_dupName_496_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22647_dupName_496_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22649_dupName_496_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3495_vt_select_21(BITSELECT,11972)@261
    assign i_unnamed_c_compstr3495_vt_select_21_b = rightShiftStage1_uid22649_dupName_496_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3495_vt_join(BITJOIN,11971)@261
    assign i_unnamed_c_compstr3495_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3495_vt_select_21_b};

    // i_unnamed_c_compstr3496_sel_x(BITSELECT,6232)@261
    assign i_unnamed_c_compstr3496_sel_x_b = i_unnamed_c_compstr3495_vt_join_q[15:0];

    // i_unnamed_c_compstr3497_BitSelect_for_a(BITSELECT,27853)@261
    assign i_unnamed_c_compstr3497_BitSelect_for_a_b = i_unnamed_c_compstr3496_sel_x_b[0:0];

    // i_unnamed_c_compstr3497_join(BITJOIN,27854)@261
    assign i_unnamed_c_compstr3497_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3497_BitSelect_for_a_b};

    // i_unnamed_c_compstr3497_vt_select_0(BITSELECT,11977)@261
    assign i_unnamed_c_compstr3497_vt_select_0_b = i_unnamed_c_compstr3497_join_q[0:0];

    // redist60_i_unnamed_c_compstr3497_vt_select_0_b_1(DELAY,28288)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist60_i_unnamed_c_compstr3497_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3497_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3497_vt_join(BITJOIN,11976)@262
    assign i_unnamed_c_compstr3497_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist60_i_unnamed_c_compstr3497_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_124_c_compstr3498(ADD,6878)@262
    assign i_add_i_i_i_i_i126_i_124_c_compstr3498_a = {1'b0, i_unnamed_c_compstr3497_vt_join_q};
    assign i_add_i_i_i_i_i126_i_124_c_compstr3498_b = {1'b0, redist1253_i_conv_i_i_i_i97_i_124_c_compstr3494_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_124_c_compstr3498_o = $unsigned(i_add_i_i_i_i_i126_i_124_c_compstr3498_a) + $unsigned(i_add_i_i_i_i_i126_i_124_c_compstr3498_b);
    assign i_add_i_i_i_i_i126_i_124_c_compstr3498_q = i_add_i_i_i_i_i126_i_124_c_compstr3498_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_124_c_compstr3498_sel_x(BITSELECT,2072)@262
    assign bgTrunc_i_add_i_i_i_i_i126_i_124_c_compstr3498_sel_x_b = i_add_i_i_i_i_i126_i_124_c_compstr3498_q[15:0];

    // i_conv_i_i_i_i_i75_i277_125_c_compstr3518_sel_x(BITSELECT,3613)@262
    assign i_conv_i_i_i_i_i75_i277_125_c_compstr3518_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_124_c_compstr3498_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_125_c_compstr3518_vt_select_15(BITSELECT,7353)@262
    assign i_conv_i_i_i_i_i75_i277_125_c_compstr3518_vt_select_15_b = i_conv_i_i_i_i_i75_i277_125_c_compstr3518_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_125_c_compstr3518_vt_join(BITJOIN,7352)@262
    assign i_conv_i_i_i_i_i75_i277_125_c_compstr3518_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_125_c_compstr3518_vt_select_15_b};

    // leftShiftStage0_uid23360_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x(MUX,23359)@262
    assign leftShiftStage0_uid23360_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23360_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_125_c_compstr3518_vt_join_q or leftShiftStage0Idx1_uid23358_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23360_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23360_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_125_c_compstr3518_vt_join_q;
            1'b1 : leftShiftStage0_uid23360_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23358_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23360_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23365_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x(MUX,23364)@262
    assign leftShiftStage1_uid23365_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23365_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_s or leftShiftStage0_uid23360_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23363_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23365_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23365_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q = leftShiftStage0_uid23360_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23365_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23363_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23365_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23370_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x(MUX,23369)@262
    assign leftShiftStage2_uid23370_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23370_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_s or leftShiftStage1_uid23365_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23368_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23370_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23370_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q = leftShiftStage1_uid23365_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23370_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23368_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23370_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_125_c_compstr3519_vt_select_28(BITSELECT,9124)@262
    assign i_shl_i_i_i_i_i77_i_125_c_compstr3519_vt_select_28_b = leftShiftStage2_uid23370_i_shl_i_i_i_i_i77_i_125_c_compstr0_shift_x_q[28:13];

    // redist482_i_shl_i_i_i_i_i77_i_125_c_compstr3519_vt_select_28_b_1(DELAY,28710)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist482_i_shl_i_i_i_i_i77_i_125_c_compstr3519_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_125_c_compstr3519_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_125_c_compstr3519_vt_join(BITJOIN,9123)@263
    assign i_shl_i_i_i_i_i77_i_125_c_compstr3519_vt_join_q = {redist482_i_shl_i_i_i_i_i77_i_125_c_compstr3519_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma(CHAINMULTADD,28126)@257 + 5
    // out q@263
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ah[0] <= redist1021_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_251_tpl_249_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ah[1] <= redist1020_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_250_tpl_249_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ch[0] <= redist767_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_251_tpl_249_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ch[1] <= redist766_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_250_tpl_249_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520(ADD,8422)@263
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compstr3515_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compstr3517_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compstr3516_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_125_c_compstr3519_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_125_c_compstr3519_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_o[33:0];

    // rightShiftStage0_uid22688_dupName_499_i_unnamed_c_compstr0_shift_x(MUX,22687)@263
    assign rightShiftStage0_uid22688_dupName_499_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22688_dupName_499_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_q or rightShiftStage0Idx1_uid22686_dupName_499_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22688_dupName_499_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22688_dupName_499_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_q;
            1'b1 : rightShiftStage0_uid22688_dupName_499_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22686_dupName_499_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22688_dupName_499_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22693_dupName_499_i_unnamed_c_compstr0_shift_x(MUX,22692)@263
    assign rightShiftStage1_uid22693_dupName_499_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22693_dupName_499_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22688_dupName_499_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22691_dupName_499_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22693_dupName_499_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22693_dupName_499_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22688_dupName_499_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22693_dupName_499_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22691_dupName_499_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22693_dupName_499_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22698_dupName_499_i_unnamed_c_compstr0_shift_x(MUX,22697)@263
    assign rightShiftStage2_uid22698_dupName_499_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22698_dupName_499_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22693_dupName_499_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22696_dupName_499_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22698_dupName_499_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22698_dupName_499_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22693_dupName_499_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22698_dupName_499_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22696_dupName_499_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22698_dupName_499_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3521_vt_select_20(BITSELECT,11994)@263
    assign i_unnamed_c_compstr3521_vt_select_20_b = rightShiftStage2_uid22698_dupName_499_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3521_vt_join(BITJOIN,11993)@263
    assign i_unnamed_c_compstr3521_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3521_vt_select_20_b};

    // i_conv_i_i_i_i97_i_125_c_compstr3522_sel_x(BITSELECT,3484)@263
    assign i_conv_i_i_i_i97_i_125_c_compstr3522_sel_x_b = i_unnamed_c_compstr3521_vt_join_q[15:0];

    // redist1252_i_conv_i_i_i_i97_i_125_c_compstr3522_sel_x_b_1(DELAY,29480)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1252_i_conv_i_i_i_i97_i_125_c_compstr3522_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_125_c_compstr3522_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22707_dupName_500_i_unnamed_c_compstr0_shift_x(BITSELECT,22706)@263
    assign rightShiftStage1Idx1Rng8_uid22707_dupName_500_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22706_dupName_500_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22709_dupName_500_i_unnamed_c_compstr0_shift_x(BITJOIN,22708)@263
    assign rightShiftStage1Idx1_uid22709_dupName_500_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22707_dupName_500_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22702_dupName_500_i_unnamed_c_compstr0_shift_x(BITSELECT,22701)@263
    assign rightShiftStage0Idx1Rng4_uid22702_dupName_500_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_q[33:4];

    // rightShiftStage0Idx1_uid22704_dupName_500_i_unnamed_c_compstr0_shift_x(BITJOIN,22703)@263
    assign rightShiftStage0Idx1_uid22704_dupName_500_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22702_dupName_500_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22706_dupName_500_i_unnamed_c_compstr0_shift_x(MUX,22705)@263
    assign rightShiftStage0_uid22706_dupName_500_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22706_dupName_500_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_q or rightShiftStage0Idx1_uid22704_dupName_500_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22706_dupName_500_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22706_dupName_500_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compstr3520_q;
            1'b1 : rightShiftStage0_uid22706_dupName_500_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22704_dupName_500_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22706_dupName_500_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22711_dupName_500_i_unnamed_c_compstr0_shift_x(MUX,22710)@263
    assign rightShiftStage1_uid22711_dupName_500_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22711_dupName_500_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22706_dupName_500_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22709_dupName_500_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22711_dupName_500_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22711_dupName_500_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22706_dupName_500_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22711_dupName_500_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22709_dupName_500_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22711_dupName_500_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3523_vt_select_21(BITSELECT,11997)@263
    assign i_unnamed_c_compstr3523_vt_select_21_b = rightShiftStage1_uid22711_dupName_500_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3523_vt_join(BITJOIN,11996)@263
    assign i_unnamed_c_compstr3523_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3523_vt_select_21_b};

    // i_unnamed_c_compstr3524_sel_x(BITSELECT,6234)@263
    assign i_unnamed_c_compstr3524_sel_x_b = i_unnamed_c_compstr3523_vt_join_q[15:0];

    // i_unnamed_c_compstr3525_BitSelect_for_a(BITSELECT,27857)@263
    assign i_unnamed_c_compstr3525_BitSelect_for_a_b = i_unnamed_c_compstr3524_sel_x_b[0:0];

    // i_unnamed_c_compstr3525_join(BITJOIN,27858)@263
    assign i_unnamed_c_compstr3525_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3525_BitSelect_for_a_b};

    // i_unnamed_c_compstr3525_vt_select_0(BITSELECT,12002)@263
    assign i_unnamed_c_compstr3525_vt_select_0_b = i_unnamed_c_compstr3525_join_q[0:0];

    // redist57_i_unnamed_c_compstr3525_vt_select_0_b_1(DELAY,28285)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist57_i_unnamed_c_compstr3525_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3525_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3525_vt_join(BITJOIN,12001)@264
    assign i_unnamed_c_compstr3525_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist57_i_unnamed_c_compstr3525_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_125_c_compstr3526(ADD,6879)@264
    assign i_add_i_i_i_i_i126_i_125_c_compstr3526_a = {1'b0, i_unnamed_c_compstr3525_vt_join_q};
    assign i_add_i_i_i_i_i126_i_125_c_compstr3526_b = {1'b0, redist1252_i_conv_i_i_i_i97_i_125_c_compstr3522_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_125_c_compstr3526_o = $unsigned(i_add_i_i_i_i_i126_i_125_c_compstr3526_a) + $unsigned(i_add_i_i_i_i_i126_i_125_c_compstr3526_b);
    assign i_add_i_i_i_i_i126_i_125_c_compstr3526_q = i_add_i_i_i_i_i126_i_125_c_compstr3526_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_125_c_compstr3526_sel_x(BITSELECT,2073)@264
    assign bgTrunc_i_add_i_i_i_i_i126_i_125_c_compstr3526_sel_x_b = i_add_i_i_i_i_i126_i_125_c_compstr3526_q[15:0];

    // i_conv_i_i_i_i_i75_i277_126_c_compstr3546_sel_x(BITSELECT,3614)@264
    assign i_conv_i_i_i_i_i75_i277_126_c_compstr3546_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_125_c_compstr3526_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_126_c_compstr3546_vt_select_15(BITSELECT,7357)@264
    assign i_conv_i_i_i_i_i75_i277_126_c_compstr3546_vt_select_15_b = i_conv_i_i_i_i_i75_i277_126_c_compstr3546_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_126_c_compstr3546_vt_join(BITJOIN,7356)@264
    assign i_conv_i_i_i_i_i75_i277_126_c_compstr3546_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_126_c_compstr3546_vt_select_15_b};

    // leftShiftStage0_uid23378_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x(MUX,23377)@264
    assign leftShiftStage0_uid23378_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23378_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_126_c_compstr3546_vt_join_q or leftShiftStage0Idx1_uid23376_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23378_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23378_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_126_c_compstr3546_vt_join_q;
            1'b1 : leftShiftStage0_uid23378_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23376_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23378_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23383_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x(MUX,23382)@264
    assign leftShiftStage1_uid23383_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23383_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_s or leftShiftStage0_uid23378_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23381_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23383_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23383_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q = leftShiftStage0_uid23378_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23383_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23381_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23383_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23388_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x(MUX,23387)@264
    assign leftShiftStage2_uid23388_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23388_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_s or leftShiftStage1_uid23383_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23386_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23388_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23388_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q = leftShiftStage1_uid23383_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23388_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23386_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23388_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_126_c_compstr3547_vt_select_28(BITSELECT,9127)@264
    assign i_shl_i_i_i_i_i77_i_126_c_compstr3547_vt_select_28_b = leftShiftStage2_uid23388_i_shl_i_i_i_i_i77_i_126_c_compstr0_shift_x_q[28:13];

    // redist481_i_shl_i_i_i_i_i77_i_126_c_compstr3547_vt_select_28_b_1(DELAY,28709)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist481_i_shl_i_i_i_i_i77_i_126_c_compstr3547_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_126_c_compstr3547_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_126_c_compstr3547_vt_join(BITJOIN,9126)@265
    assign i_shl_i_i_i_i_i77_i_126_c_compstr3547_vt_join_q = {redist481_i_shl_i_i_i_i_i77_i_126_c_compstr3547_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma(CHAINMULTADD,28127)@259 + 5
    // out q@265
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ah[0] <= redist1023_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_253_tpl_251_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ah[1] <= redist1022_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_252_tpl_251_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ch[0] <= redist769_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_253_tpl_251_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ch[1] <= redist768_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_252_tpl_251_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548(ADD,8423)@265
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compstr3543_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compstr3545_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compstr3544_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_126_c_compstr3547_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_126_c_compstr3547_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_o[33:0];

    // rightShiftStage0_uid22750_dupName_503_i_unnamed_c_compstr0_shift_x(MUX,22749)@265
    assign rightShiftStage0_uid22750_dupName_503_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22750_dupName_503_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_q or rightShiftStage0Idx1_uid22748_dupName_503_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22750_dupName_503_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22750_dupName_503_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_q;
            1'b1 : rightShiftStage0_uid22750_dupName_503_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22748_dupName_503_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22750_dupName_503_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22755_dupName_503_i_unnamed_c_compstr0_shift_x(MUX,22754)@265
    assign rightShiftStage1_uid22755_dupName_503_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22755_dupName_503_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22750_dupName_503_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22753_dupName_503_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22755_dupName_503_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22755_dupName_503_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22750_dupName_503_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22755_dupName_503_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22753_dupName_503_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22755_dupName_503_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22760_dupName_503_i_unnamed_c_compstr0_shift_x(MUX,22759)@265
    assign rightShiftStage2_uid22760_dupName_503_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22760_dupName_503_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22755_dupName_503_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22758_dupName_503_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22760_dupName_503_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22760_dupName_503_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22755_dupName_503_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22760_dupName_503_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22758_dupName_503_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22760_dupName_503_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3549_vt_select_20(BITSELECT,12016)@265
    assign i_unnamed_c_compstr3549_vt_select_20_b = rightShiftStage2_uid22760_dupName_503_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3549_vt_join(BITJOIN,12015)@265
    assign i_unnamed_c_compstr3549_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3549_vt_select_20_b};

    // i_conv_i_i_i_i97_i_126_c_compstr3550_sel_x(BITSELECT,3485)@265
    assign i_conv_i_i_i_i97_i_126_c_compstr3550_sel_x_b = i_unnamed_c_compstr3549_vt_join_q[15:0];

    // redist1251_i_conv_i_i_i_i97_i_126_c_compstr3550_sel_x_b_1(DELAY,29479)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1251_i_conv_i_i_i_i97_i_126_c_compstr3550_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_126_c_compstr3550_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22769_dupName_504_i_unnamed_c_compstr0_shift_x(BITSELECT,22768)@265
    assign rightShiftStage1Idx1Rng8_uid22769_dupName_504_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22768_dupName_504_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22771_dupName_504_i_unnamed_c_compstr0_shift_x(BITJOIN,22770)@265
    assign rightShiftStage1Idx1_uid22771_dupName_504_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22769_dupName_504_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22764_dupName_504_i_unnamed_c_compstr0_shift_x(BITSELECT,22763)@265
    assign rightShiftStage0Idx1Rng4_uid22764_dupName_504_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_q[33:4];

    // rightShiftStage0Idx1_uid22766_dupName_504_i_unnamed_c_compstr0_shift_x(BITJOIN,22765)@265
    assign rightShiftStage0Idx1_uid22766_dupName_504_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22764_dupName_504_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22768_dupName_504_i_unnamed_c_compstr0_shift_x(MUX,22767)@265
    assign rightShiftStage0_uid22768_dupName_504_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22768_dupName_504_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_q or rightShiftStage0Idx1_uid22766_dupName_504_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22768_dupName_504_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22768_dupName_504_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compstr3548_q;
            1'b1 : rightShiftStage0_uid22768_dupName_504_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22766_dupName_504_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22768_dupName_504_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22773_dupName_504_i_unnamed_c_compstr0_shift_x(MUX,22772)@265
    assign rightShiftStage1_uid22773_dupName_504_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22773_dupName_504_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22768_dupName_504_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22771_dupName_504_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22773_dupName_504_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22773_dupName_504_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22768_dupName_504_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22773_dupName_504_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22771_dupName_504_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22773_dupName_504_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3551_vt_select_21(BITSELECT,12019)@265
    assign i_unnamed_c_compstr3551_vt_select_21_b = rightShiftStage1_uid22773_dupName_504_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3551_vt_join(BITJOIN,12018)@265
    assign i_unnamed_c_compstr3551_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3551_vt_select_21_b};

    // i_unnamed_c_compstr3552_sel_x(BITSELECT,6236)@265
    assign i_unnamed_c_compstr3552_sel_x_b = i_unnamed_c_compstr3551_vt_join_q[15:0];

    // i_unnamed_c_compstr3553_BitSelect_for_a(BITSELECT,27861)@265
    assign i_unnamed_c_compstr3553_BitSelect_for_a_b = i_unnamed_c_compstr3552_sel_x_b[0:0];

    // i_unnamed_c_compstr3553_join(BITJOIN,27862)@265
    assign i_unnamed_c_compstr3553_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3553_BitSelect_for_a_b};

    // i_unnamed_c_compstr3553_vt_select_0(BITSELECT,12024)@265
    assign i_unnamed_c_compstr3553_vt_select_0_b = i_unnamed_c_compstr3553_join_q[0:0];

    // redist55_i_unnamed_c_compstr3553_vt_select_0_b_1(DELAY,28283)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist55_i_unnamed_c_compstr3553_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3553_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3553_vt_join(BITJOIN,12023)@266
    assign i_unnamed_c_compstr3553_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist55_i_unnamed_c_compstr3553_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_126_c_compstr3554(ADD,6880)@266
    assign i_add_i_i_i_i_i126_i_126_c_compstr3554_a = {1'b0, i_unnamed_c_compstr3553_vt_join_q};
    assign i_add_i_i_i_i_i126_i_126_c_compstr3554_b = {1'b0, redist1251_i_conv_i_i_i_i97_i_126_c_compstr3550_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_126_c_compstr3554_o = $unsigned(i_add_i_i_i_i_i126_i_126_c_compstr3554_a) + $unsigned(i_add_i_i_i_i_i126_i_126_c_compstr3554_b);
    assign i_add_i_i_i_i_i126_i_126_c_compstr3554_q = i_add_i_i_i_i_i126_i_126_c_compstr3554_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_126_c_compstr3554_sel_x(BITSELECT,2074)@266
    assign bgTrunc_i_add_i_i_i_i_i126_i_126_c_compstr3554_sel_x_b = i_add_i_i_i_i_i126_i_126_c_compstr3554_q[15:0];

    // i_conv_i_i_i_i_i75_i277_127_c_compstr3574_sel_x(BITSELECT,3615)@266
    assign i_conv_i_i_i_i_i75_i277_127_c_compstr3574_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_126_c_compstr3554_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i277_127_c_compstr3574_vt_select_15(BITSELECT,7361)@266
    assign i_conv_i_i_i_i_i75_i277_127_c_compstr3574_vt_select_15_b = i_conv_i_i_i_i_i75_i277_127_c_compstr3574_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i277_127_c_compstr3574_vt_join(BITJOIN,7360)@266
    assign i_conv_i_i_i_i_i75_i277_127_c_compstr3574_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_conv_i_i_i_i_i75_i277_127_c_compstr3574_vt_select_15_b};

    // leftShiftStage0_uid23396_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x(MUX,23395)@266
    assign leftShiftStage0_uid23396_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23396_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_s or i_conv_i_i_i_i_i75_i277_127_c_compstr3574_vt_join_q or leftShiftStage0Idx1_uid23394_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23396_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage0_uid23396_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q = i_conv_i_i_i_i_i75_i277_127_c_compstr3574_vt_join_q;
            1'b1 : leftShiftStage0_uid23396_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q = leftShiftStage0Idx1_uid23394_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q;
            default : leftShiftStage0_uid23396_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23401_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x(MUX,23400)@266
    assign leftShiftStage1_uid23401_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23401_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_s or leftShiftStage0_uid23396_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q or leftShiftStage1Idx1_uid23399_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23401_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage1_uid23401_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q = leftShiftStage0_uid23396_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage1_uid23401_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q = leftShiftStage1Idx1_uid23399_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q;
            default : leftShiftStage1_uid23401_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23406_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x(MUX,23405)@266
    assign leftShiftStage2_uid23406_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23406_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_s or leftShiftStage1_uid23401_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q or leftShiftStage2Idx1_uid23404_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23406_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_s)
            1'b0 : leftShiftStage2_uid23406_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q = leftShiftStage1_uid23401_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q;
            1'b1 : leftShiftStage2_uid23406_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q = leftShiftStage2Idx1_uid23404_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q;
            default : leftShiftStage2_uid23406_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_127_c_compstr3575_vt_select_28(BITSELECT,9130)@266
    assign i_shl_i_i_i_i_i77_i_127_c_compstr3575_vt_select_28_b = leftShiftStage2_uid23406_i_shl_i_i_i_i_i77_i_127_c_compstr0_shift_x_q[28:13];

    // redist480_i_shl_i_i_i_i_i77_i_127_c_compstr3575_vt_select_28_b_1(DELAY,28708)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist480_i_shl_i_i_i_i_i77_i_127_c_compstr3575_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_127_c_compstr3575_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_127_c_compstr3575_vt_join(BITJOIN,9129)@267
    assign i_shl_i_i_i_i_i77_i_127_c_compstr3575_vt_join_q = {redist480_i_shl_i_i_i_i_i77_i_127_c_compstr3575_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma(CHAINMULTADD,28128)@261 + 5
    // out q@267
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ah[0] <= redist1025_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_255_tpl_253_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ah[1] <= redist1024_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_254_tpl_253_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ch[0] <= redist771_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_255_tpl_253_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ch[1] <= redist770_i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_254_tpl_253_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576(ADD,8424)@267
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compstr3571_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compstr3573_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compstr3572_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_127_c_compstr3575_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_127_c_compstr3575_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_o[33:0];

    // rightShiftStage0_uid22812_dupName_507_i_unnamed_c_compstr0_shift_x(MUX,22811)@267
    assign rightShiftStage0_uid22812_dupName_507_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22812_dupName_507_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_q or rightShiftStage0Idx1_uid22810_dupName_507_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22812_dupName_507_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22812_dupName_507_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_q;
            1'b1 : rightShiftStage0_uid22812_dupName_507_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22810_dupName_507_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22812_dupName_507_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22817_dupName_507_i_unnamed_c_compstr0_shift_x(MUX,22816)@267
    assign rightShiftStage1_uid22817_dupName_507_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22817_dupName_507_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22812_dupName_507_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22815_dupName_507_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22817_dupName_507_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22817_dupName_507_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22812_dupName_507_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22817_dupName_507_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22815_dupName_507_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22817_dupName_507_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22822_dupName_507_i_unnamed_c_compstr0_shift_x(MUX,22821)@267
    assign rightShiftStage2_uid22822_dupName_507_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22822_dupName_507_i_unnamed_c_compstr0_shift_x_s or rightShiftStage1_uid22817_dupName_507_i_unnamed_c_compstr0_shift_x_q or rightShiftStage2Idx1_uid22820_dupName_507_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22822_dupName_507_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage2_uid22822_dupName_507_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1_uid22817_dupName_507_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage2_uid22822_dupName_507_i_unnamed_c_compstr0_shift_x_q = rightShiftStage2Idx1_uid22820_dupName_507_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage2_uid22822_dupName_507_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3577_vt_select_20(BITSELECT,12038)@267
    assign i_unnamed_c_compstr3577_vt_select_20_b = rightShiftStage2_uid22822_dupName_507_i_unnamed_c_compstr0_shift_x_q[20:0];

    // i_unnamed_c_compstr3577_vt_join(BITJOIN,12037)@267
    assign i_unnamed_c_compstr3577_vt_join_q = {i_conv_i_i_i_i_i75_i277_100_c_compstr2818_vt_const_28_q, i_unnamed_c_compstr3577_vt_select_20_b};

    // i_conv_i_i_i_i97_i_127_c_compstr3578_sel_x(BITSELECT,3486)@267
    assign i_conv_i_i_i_i97_i_127_c_compstr3578_sel_x_b = i_unnamed_c_compstr3577_vt_join_q[15:0];

    // redist1250_i_conv_i_i_i_i97_i_127_c_compstr3578_sel_x_b_1(DELAY,29478)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1250_i_conv_i_i_i_i97_i_127_c_compstr3578_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_127_c_compstr3578_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22831_dupName_508_i_unnamed_c_compstr0_shift_x(BITSELECT,22830)@267
    assign rightShiftStage1Idx1Rng8_uid22831_dupName_508_i_unnamed_c_compstr0_shift_x_b = rightShiftStage0_uid22830_dupName_508_i_unnamed_c_compstr0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22833_dupName_508_i_unnamed_c_compstr0_shift_x(BITJOIN,22832)@267
    assign rightShiftStage1Idx1_uid22833_dupName_508_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage1Idx1Pad8_uid14958_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage1Idx1Rng8_uid22831_dupName_508_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22826_dupName_508_i_unnamed_c_compstr0_shift_x(BITSELECT,22825)@267
    assign rightShiftStage0Idx1Rng4_uid22826_dupName_508_i_unnamed_c_compstr0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_q[33:4];

    // rightShiftStage0Idx1_uid22828_dupName_508_i_unnamed_c_compstr0_shift_x(BITJOIN,22827)@267
    assign rightShiftStage0Idx1_uid22828_dupName_508_i_unnamed_c_compstr0_shift_x_q = {rightShiftStage0Idx1Pad4_uid14953_dupName_0_i_unnamed_c_compstr0_shift_x_q, rightShiftStage0Idx1Rng4_uid22826_dupName_508_i_unnamed_c_compstr0_shift_x_b};

    // rightShiftStage0_uid22830_dupName_508_i_unnamed_c_compstr0_shift_x(MUX,22829)@267
    assign rightShiftStage0_uid22830_dupName_508_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22830_dupName_508_i_unnamed_c_compstr0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_q or rightShiftStage0Idx1_uid22828_dupName_508_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22830_dupName_508_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage0_uid22830_dupName_508_i_unnamed_c_compstr0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compstr3576_q;
            1'b1 : rightShiftStage0_uid22830_dupName_508_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0Idx1_uid22828_dupName_508_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage0_uid22830_dupName_508_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22835_dupName_508_i_unnamed_c_compstr0_shift_x(MUX,22834)@267
    assign rightShiftStage1_uid22835_dupName_508_i_unnamed_c_compstr0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22835_dupName_508_i_unnamed_c_compstr0_shift_x_s or rightShiftStage0_uid22830_dupName_508_i_unnamed_c_compstr0_shift_x_q or rightShiftStage1Idx1_uid22833_dupName_508_i_unnamed_c_compstr0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22835_dupName_508_i_unnamed_c_compstr0_shift_x_s)
            1'b0 : rightShiftStage1_uid22835_dupName_508_i_unnamed_c_compstr0_shift_x_q = rightShiftStage0_uid22830_dupName_508_i_unnamed_c_compstr0_shift_x_q;
            1'b1 : rightShiftStage1_uid22835_dupName_508_i_unnamed_c_compstr0_shift_x_q = rightShiftStage1Idx1_uid22833_dupName_508_i_unnamed_c_compstr0_shift_x_q;
            default : rightShiftStage1_uid22835_dupName_508_i_unnamed_c_compstr0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compstr3579_vt_select_21(BITSELECT,12041)@267
    assign i_unnamed_c_compstr3579_vt_select_21_b = rightShiftStage1_uid22835_dupName_508_i_unnamed_c_compstr0_shift_x_q[21:0];

    // i_unnamed_c_compstr3579_vt_join(BITJOIN,12040)@267
    assign i_unnamed_c_compstr3579_vt_join_q = {i_unnamed_c_compstr1003_vt_const_33_q, i_unnamed_c_compstr3579_vt_select_21_b};

    // i_unnamed_c_compstr3580_sel_x(BITSELECT,6238)@267
    assign i_unnamed_c_compstr3580_sel_x_b = i_unnamed_c_compstr3579_vt_join_q[15:0];

    // i_unnamed_c_compstr3581_BitSelect_for_a(BITSELECT,27865)@267
    assign i_unnamed_c_compstr3581_BitSelect_for_a_b = i_unnamed_c_compstr3580_sel_x_b[0:0];

    // i_unnamed_c_compstr3581_join(BITJOIN,27866)@267
    assign i_unnamed_c_compstr3581_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compstr3581_BitSelect_for_a_b};

    // i_unnamed_c_compstr3581_vt_select_0(BITSELECT,12049)@267
    assign i_unnamed_c_compstr3581_vt_select_0_b = i_unnamed_c_compstr3581_join_q[0:0];

    // redist53_i_unnamed_c_compstr3581_vt_select_0_b_1(DELAY,28281)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist53_i_unnamed_c_compstr3581_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compstr3581_vt_select_0_b);
        end
    end

    // i_unnamed_c_compstr3581_vt_join(BITJOIN,12048)@268
    assign i_unnamed_c_compstr3581_vt_join_q = {i_unnamed_c_compstr1005_vt_const_15_q, redist53_i_unnamed_c_compstr3581_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_127_c_compstr3582(ADD,6881)@268
    assign i_add_i_i_i_i_i126_i_127_c_compstr3582_a = {1'b0, i_unnamed_c_compstr3581_vt_join_q};
    assign i_add_i_i_i_i_i126_i_127_c_compstr3582_b = {1'b0, redist1250_i_conv_i_i_i_i97_i_127_c_compstr3578_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_127_c_compstr3582_o = $unsigned(i_add_i_i_i_i_i126_i_127_c_compstr3582_a) + $unsigned(i_add_i_i_i_i_i126_i_127_c_compstr3582_b);
    assign i_add_i_i_i_i_i126_i_127_c_compstr3582_q = i_add_i_i_i_i_i126_i_127_c_compstr3582_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_127_c_compstr3582_sel_x(BITSELECT,2075)@268
    assign bgTrunc_i_add_i_i_i_i_i126_i_127_c_compstr3582_sel_x_b = i_add_i_i_i_i_i126_i_127_c_compstr3582_q[15:0];

    // i_memcoalesce_load_c_compstr_fpgaunique_5138_toi1_intcast_c_compstr18_sel_x(BITSELECT,5014)@8
    assign i_memcoalesce_load_c_compstr_fpgaunique_5138_toi1_intcast_c_compstr18_sel_x_b = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5138_c_compstr16_aunroll_x_out_o_readdata_0_tpl[0:0];

    // redist515_i_memcoalesce_load_c_compstr_fpgaunique_5138_toi1_intcast_c_compstr18_sel_x_b_260(DELAY,28743)
    dspba_delay_ver #( .width(1), .depth(260), .reset_kind("NONE"), .phase(0), .modulus(2), .reset_high(1'b0) )
    redist515_i_memcoalesce_load_c_compstr_fpgaunique_5138_toi1_intcast_c_compstr18_sel_x_b_260 ( .xin(i_memcoalesce_load_c_compstr_fpgaunique_5138_toi1_intcast_c_compstr18_sel_x_b), .xout(redist515_i_memcoalesce_load_c_compstr_fpgaunique_5138_toi1_intcast_c_compstr18_sel_x_b_260_q), .clk(clock), .aclr(resetn), .ena(1'b1) );

    // i_memcoalesce_load_c_compstr_fpgaunique_5126_toi1_intcast_c_compstr13_sel_x(BITSELECT,5013)@8
    assign i_memcoalesce_load_c_compstr_fpgaunique_5126_toi1_intcast_c_compstr13_sel_x_b = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_o_readdata_0_tpl[0:0];

    // redist516_i_memcoalesce_load_c_compstr_fpgaunique_5126_toi1_intcast_c_compstr13_sel_x_b_260(DELAY,28744)
    dspba_delay_ver #( .width(1), .depth(260), .reset_kind("NONE"), .phase(0), .modulus(2), .reset_high(1'b0) )
    redist516_i_memcoalesce_load_c_compstr_fpgaunique_5126_toi1_intcast_c_compstr13_sel_x_b_260 ( .xin(i_memcoalesce_load_c_compstr_fpgaunique_5126_toi1_intcast_c_compstr13_sel_x_b), .xout(redist516_i_memcoalesce_load_c_compstr_fpgaunique_5126_toi1_intcast_c_compstr13_sel_x_b_260_q), .clk(clock), .aclr(resetn), .ena(1'b1) );

    // sync_out_aunroll_x(GPOUT,6303)@268
    assign out_c0_exi5730_0_tpl = GND_q;
    assign out_c0_exi5730_1_tpl = redist516_i_memcoalesce_load_c_compstr_fpgaunique_5126_toi1_intcast_c_compstr13_sel_x_b_260_q;
    assign out_c0_exi5730_2_tpl = redist515_i_memcoalesce_load_c_compstr_fpgaunique_5138_toi1_intcast_c_compstr18_sel_x_b_260_q;
    assign out_c0_exi5730_3_tpl = bgTrunc_i_add_i_i_i_i_i126_i_127_c_compstr3582_sel_x_b;
    assign out_c0_exi5730_4_tpl = bgTrunc_i_add_i_i_i_i_i_i_127_c_compstr3598_sel_x_b;
    assign out_c0_exi5730_5_tpl = redist0_i_exitcond15_c_compstr3606_cmp_nsign_q_264_q;
    assign out_c0_exi5730_6_tpl = i_notcmp_c_compstr3609_q;
    assign out_c_compSTR_B7_current_iter_isspec = redist512_i_c_compstr_b7_current_iter_isspec_c_compstr5_q_264_q;
    assign out_o_valid = redist1_valid_fanout_reg0_q_264_q;

    // ext_sig_sync_out(GPOUT,6851)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount = i_llvm_fpga_mem_memcoalesce_load_c_compstr_fpgaunique_5126_c_compstr11_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount;

    // regfree_osync(GPOUT,12624)
    assign out_exiting_valid_out = i_llvm_fpga_pipeline_keep_going_c_compstr6_out_exiting_valid_out;

endmodule
